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Wishbone ChaCha Accelerator

This is an extremely simple, ChaCha20 accelerator for the MPW2-C multi project submission. The accelerator is exposed to the Wishbone bus. The state of the accelerator consists of a key-register, an iv/nonce-register, as well as a counter. The Wishbone bus exposes an interface to shift 32-bit words in or out of the key/iv/counter registers, and a status bit to check the status and initialize the permutation. After the permutation is initialized, the key stream can be read in 32-bit chunks. After 16 chunks are read, the counter is automatically incremented and the next key stream block is generated. The core also exposes an (untested) interrupt line, that can be en-/disabled via the status register.

Image of the core

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This project is licensed under Apache 2

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Wishbone ChaCha Accelerator for MPW2-C

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