diff --git a/Processor/Src/Pipeline/CommitStage.sv b/Processor/Src/Pipeline/CommitStage.sv
index 14081822..5cf53258 100644
--- a/Processor/Src/Pipeline/CommitStage.sv
+++ b/Processor/Src/Pipeline/CommitStage.sv
@@ -128,7 +128,10 @@ function automatic void DecideCommit(
                                 REFETCH_TYPE_NEXT_PC
             );
         end
-        else if (execState[i] == EXEC_STATE_REFETCH_THIS) begin
+        else if (execState[i] inside {
+            EXEC_STATE_REFETCH_THIS,
+            EXEC_STATE_STORE_LOAD_FORWARDING_MISS
+        }) begin
             recovery[i] = TRUE;
             recoveryPoint[i] = headOfThisInsn[i];
             opRefetchType[i] = REFETCH_TYPE_THIS_PC;
@@ -192,6 +195,7 @@ function automatic void DecideCommit(
                     commit[i] =
                         ( ((execState[i] inside {
                             EXEC_STATE_REFETCH_THIS,
+                            EXEC_STATE_STORE_LOAD_FORWARDING_MISS,
                             EXEC_STATE_FAULT_LOAD_MISALIGNED,
                             EXEC_STATE_FAULT_LOAD_VIOLATION,
                             EXEC_STATE_FAULT_STORE_MISALIGNED,
diff --git a/Processor/Src/Pipeline/MemoryBackEnd/MemoryTagAccessStage.sv b/Processor/Src/Pipeline/MemoryBackEnd/MemoryTagAccessStage.sv
index 974887a3..c6b2f83d 100644
--- a/Processor/Src/Pipeline/MemoryBackEnd/MemoryTagAccessStage.sv
+++ b/Processor/Src/Pipeline/MemoryBackEnd/MemoryTagAccessStage.sv
@@ -199,7 +199,7 @@ module MemoryTagAccessStage(
 `ifdef RSD_ENABLE_REISSUE_ON_CACHE_MISS
             if (isLoad[i]) begin
                 if (loadStoreUnit.storeLoadForwarded[i]) begin
-                    ldRegValid[i] = loadStoreUnit.forwardMiss[i] ? FALSE : ldPipeReg[i].regValid;
+                    ldRegValid[i] = ldPipeReg[i].regValid;
                 end
                 else if (ldRecordData[i].hasAllocatedMSHR) begin
                     // When the load has allocated an MSHR entry,
@@ -271,8 +271,10 @@ module MemoryTagAccessStage(
                 // そのロード命令からやり直す
                 if ( loadStoreUnit.storeLoadForwarded[i] ) begin
                     // フォワードされた場合
+                    // A load instruction that caused a store-load forwarding miss is not replayed but flushed to prevent a deadlock due to replay.
+                    // To wait for the commit of the dependent store instruction, The flush is performed in commit stage.
                     ldNextStage[i].execState =
-                        loadStoreUnit.forwardMiss[i] ? EXEC_STATE_REFETCH_THIS : EXEC_STATE_SUCCESS;
+                        loadStoreUnit.forwardMiss[i] ? EXEC_STATE_STORE_LOAD_FORWARDING_MISS : EXEC_STATE_SUCCESS;
                 end
                 else if (ldRecordData[i].hasAllocatedMSHR) begin
                     ldNextStage[i].execState =
diff --git a/Processor/Src/Scheduler/SchedulerTypes.sv b/Processor/Src/Scheduler/SchedulerTypes.sv
index 54352167..43d9c50a 100644
--- a/Processor/Src/Scheduler/SchedulerTypes.sv
+++ b/Processor/Src/Scheduler/SchedulerTypes.sv
@@ -74,6 +74,7 @@ typedef enum logic [3:0] // ExecutionState
     EXEC_STATE_FAULT_LOAD_VIOLATION   = 4'b1001,  // Load access violation
     EXEC_STATE_FAULT_STORE_MISALIGNED = 4'b1010,  // Misaligned store is executed
     EXEC_STATE_FAULT_STORE_VIOLATION  = 4'b1011,  // Store access violation
+    EXEC_STATE_STORE_LOAD_FORWARDING_MISS  = 4'b1111,  // Store load forwarding miss
 
     EXEC_STATE_FAULT_INSN_ILLEGAL     = 4'b1100,  // Illegal instruction
     EXEC_STATE_FAULT_INSN_VIOLATION   = 4'b1101,  // Illegal instruction