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Commits on Feb 19, 2013
  1. ARM: AM33XX: Add functions to save and restore am33xx wkup context.

    Russ Dill authored
    This is necessary for hibernation and RTC-only support.
    
    Signed-off-by: Russ Dill <Russ.Dill@ti.com>
  2. ARM: AM33XX: Add ability to reinitialize M3

    Russ Dill authored
    This is required for hibernate and RTC only suspend since power
    is lost to the WKUP domain where the M3 is located.
    
    Signed-off-by: Russ Dill <Russ.Dill@ti.com>
  3. ARM: AM33XX: Cleanup AM33XX PM.

    Russ Dill authored
    This cleans up pm33xx.c and pm33xx.h in preperation for RTC-only
    and hibernation changes.
    
         * Move cefuse_pwrdm into the only function it is used in
         * Create am33xx_per_save/restore_context functions
         * Move code from am33xx_pm_init into new function, am33xx_setup_deep_sleep
    
    Signed-off-by: Russ Dill <Russ.Dill@ti.com>
  4. ARM: AM33XX: Update am33xx device tree with padconf information.

    Russ Dill authored
    This updates the am33xx.dtsi with information about which padconf
    registers are stored in which power domain. This allows them to be
    saved and restored when that power domain loses power.
    
    Signed-off-by: Russ Dill <Russ.Dill@ti.com>
  5. @ghebbar

    ARM: OMAP2+: edma: add support for suspend/resume

    ghebbar authored Russ Dill committed
    This patch adds suspend/resume support along with context save and
    restore to edma module. All registers updated during probe, channel,
    event allocation, param-set, interrupts are saved and restored.
    
    This patch is tested on AM335x Beagle bone HS-MMC module.
    
    TODO:
    Currently all register are backed up and restored irrespective whether
    there was any change from the values that was programmed or not.
    This is likely to negatively impact the overall suspend/resume time.
    
    Param-set saving can be optimized by looking at the actual usage. A
    caching mechanism can be implemented and values can be cached when they
    are changed. This way noting needs to be saved & restore is just a copy
    from the cache.
    
    Signed-off-by: Hebbar, Gururaja <gururaja.hebbar@ti.com>
  6. ARM: OMAP: Fixup gpio-omap context save/restore.

    Russ Dill authored
    We need to save and restore context even if they are not in use as they
    may have been reconfigured by u-boot or configured differently than
    reset by a resume kernel.
    
    Signed-off-by: Russ Dill <Russ.Dill@ti.com>
  7. [HACK] Fix DT related context tracking regression

    Russ Dill authored
    In the move to device trees, there has been no solution for specifying a
    function to track context loss count. Jam omap_pm_dev_context_loss_count
    in for now.
    
    Signed-off-by Russ Dill <Russ.Dill@ti.com>
  8. ARM: Restore TI TSCADC clkdiv setting on resume.

    Russ Dill authored
    This was not being restored if context was lost.
    
    Signed-off-by: Russ Dill <Russ.Dill@ti.com>
  9. ARM: OMAP2: Extend omap3_sram_restore_context to be generic.

    Russ Dill authored
    The current SRAM context restore function is omap34xx specific, it re-pushes
    the omap3_sram_configure_core_dpll code and the idle code.
    
    Instead of repushing the code on restore, save it on save, and restore it on
    restore.
    
    Signed-off-by: Russ Dill <Russ.Dill@ti.com>
Commits on Feb 13, 2013
  1. ARM: OMAP2: Drop the concept of certain power domains not being able …

    Russ Dill authored
    …to lose context.
    
    It isn't much of a win, and with hibernation, everything loses context.
    
    Signed-off-by: Russ Dill <Russ.Dill@ti.com
  2. ARM: OMAP2: Add functions to save and restore pinctrl context.

    Russ Dill authored
    This adds a pair of context save/restore functions to save/restore the state
    of a set of pinctrl registers. This simplifies some of the AM33XX PM code as
    some of the pinctrl registers are lost when the per power domain loses power.
    The pincrtl code can perform the necessary save/restore.
    
    This will also be necessary for hibernation and RTC only sleep, as all
    pinctrl registers all lost.
    
    Signed-off-by: Russ Dill <Russ.Dill@gmail.com>
  3. ARM: OMAP2: Restore clocksource dmtimer context if it is lost.

    Russ Dill authored
    During RTC-only suspend and also hibernate, the context for the
    clocksource dmtimer is lost. Check for this and restore the context if
    necessary.
    
    Signed-off-by: Russ Dill <Russ.Dill@ti.com>
  4. ARM: AM33XX: Add functions to save/restore am33xx control registers.

    Russ Dill authored
    These registers are part of the wkup domain and are lost during RTC only
    suspend and also hibernation, so storing/restoring their state is
    necessary.
    
    Signed-off-by: Russ Dill <russ.dill@ti.com>
  5. ARM: OMAP2: Add functions to save and restore powerdomain context en-…

    Russ Dill authored
    …masse.
    
    The powerdomain control registers are stored in the WKUP powerdomain on
    AM33XX, which is lost on RTC-only suspend and also hibernate. This adds
    context save and restore functions for those registers.
    
    Signed-off-by: Russ Dill <Russ.Dill@ti.com>
  6. ARM: OMAP2: Add functions to save and restore omap hwmod context en-m…

    Russ Dill authored
    …asse.
    
    This is used to support suspend modes like RTC-only and hibernate where
    the state of these registers is lost.
    
    Signed-off-by: Russ Dill <Russ.Dill@ti.com>
  7. ARM: OMAP2: Add functions to save and restore clockdomain context en-…

    Russ Dill authored
    …masse.
    
    This is used to support suspend modes like RTC-only and hibernate where
    the state of the registers controlling clockdomains is lost.
    
    Signed-off-by: Russ Dill <Russ.Dill@ti.com>
  8. ARM: OMAP2: Add functions to save and restore clock/dpll context en-m…

    Russ Dill authored
    …asse.
    
    The clock/dpll registers are in the WKUP power domain. Under both RTC-only
    suspend and hibernation, these registers are lost.
    
    Signed-off-by: Russ Dill <Russ.Dill@ti.com>
  9. @swarren

    regulator: clear state each invocation of of_regulator_match

    swarren authored Russ Dill committed
    of_regulator_match() saves some dynamcially allocated state into the
    match table that's passed to it. By implementation and not contract, for
    each match table entry, if non-NULL state is already present,
    of_regulator_match() will not overwrite it. of_regulator_match() is
    typically called each time a regulator is probe()d. This means it is
    called with the same match table over and over again if a regulator
    triggers deferred probe. This results in stale, kfree()d data being left
    in the match table from probe to probe, which causes a variety of crashes
    or use of invalid data.
    
    Explicitly free all output state from of_regulator_match() before
    generating new results in order to avoid this.
    
    Signed-off-by: Stephen Warren <swarren@nvidia.com>
    Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
    Cc: stable@vger.kernel.org
  10. regulator: Fix memory garbage dev_err printout.

    Russ Dill authored
    commit dd8004a: 'regulator: core: Log when a device causes a voltage
    constraint fail', tried to print out some information about the
    check consumer min/max uV fixup, however, it uses a garbage pointer
    left over from list_for_each_entry leading to boot messages in the
    form:
    
    '[    2.079890] <RANDOM ASCII>: Restricting voltage, 3735899821-4294967295uV'
    
    This can also cause a panic on restore from hibernation.
    
    This patch instead uses rdev and the updated min/max uV values.
    
    Signed-off-by: Russ Dill <Russ.Dill@ti.com>
Commits on Feb 9, 2013
  1. ARM: OMAP2+: irq: Add support for more no of interrupts

    Vaibhav Hiremath authored Russ Dill committed
    With addition to TI81XX, AM33XX family of devices, the number
    of interrupts supported has increased to 128, compared to 96
    in OMAP3 family of devices.
    The current implementation for irq handling is hardcoded to
    96 interrupts (with 3 registers to handle), this patch cleanups
    the code, to increase maximum number of interrupts support
    to 128, with dynamic detection of no of registers required for
    handling all interrupts.
    
    NOTE: Ideally, we should use dynamic allocation to allocate memory
          for registers, will align with community and implement/submit it.
    
    Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
    Signed-off-by: Afzal Mohammed <afzal@ti.com>
  2. ARM: OMAP2+: am335x: Change the wdt1 func clk src to per_32k clk

    Vaibhav Hiremath authored Russ Dill committed
    WDT1 module can take one of the below clocks as input functional
    clock -
         - On-Chip 32K RC Osc [default/reset]
         - 32K from PRCM
    
    The On-Chip 32K RC Osc clock is not an accurate clock-source as per
    the design/spec, so as a result, for example, timer which supposed
    to get expired @60Sec, but will expire somewhere ~@40Sec, which is
    not expected by any use-case.
    
    The solution here is to switch the input clock-source to PRCM
    generated 32K clock-source during boot-time itself.
    
    Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
  3. ARM: OMAP2+: AM335x: hwmod: Add missing sysc definition to wdt1 entry

    Vaibhav Hiremath authored Russ Dill committed
    While using WDT instance, anoying prints comes on the console,
    
    [root@arago /]# echo 123 > /dev/watchdog
    [   96.104949] omap_hwmod: wd_timer2: _wait_target_disable failed
    [   96.114593] omap_hwmod: wd_timer2: _wait_target_disable failed
    [   96.120727] omap_wdt: Unexpected close, not stopping!
    [root@arago /]#
    
    This failure is coming from module_disable api, as part of runtime_pm
    calls, since as per PRCM CLKCTRL idle_sts bit-fields, module has
    not entered into idle state.
    After further debugging it is observed that, sysc register value
    is set to 0x10 (reset state), but as per TRM, bit-fields 3-4 are
    reserved bits. So when I looked at OMAP4 TRM, there bits are allocated
    for 'idle" state configuration and reset value '1' means no_idle state.
    
    This patch adds sysc definitions to the wdt1 hwmod entry, which in-turn
    makes sure that sysc idle bit-fields are configured to valid state on
    enable/disable callbacks.
    
    TRM change request will also need to be raised for this issue.
    
    Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
  4. @ghebbar

    ARM: OMAP2: am33xx-hwmod: Fix "register offset NULL check" bug

    ghebbar authored Russ Dill committed
    am33xx_cm_wait_module_ready() checks if register offset is NULL.
    
    int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs)
    {
    	int i = 0;
    
    	if (!clkctrl_offs)
    		return 0;
    
    In case of AM33xx, CLKCTRL register offset for different clock domains
    are not uniformly placed. An example of this would be the RTC clock
    domain with CLKCTRL offset at 0x00.
    In such cases the module ready check is skipped which leads to a data
    abort during boot-up when RTC registers is accessed.
    
    Remove this check here to avoid checking module readiness for modules
    with clkctrl register offset at 0x00.
    
    Signed-off-by: Hebbar Gururaja <gururaja.hebbar@ti.com>
    Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
  5. @ghebbar

    ARM: OMAP2+: AM33xx: hwmod: add missing HWMOD_NO_IDLEST flags

    ghebbar authored Russ Dill committed
    struct omap_hwmod records belonging to wkup m3 domain is missing
    HWMOD_NO_IDLEST flags; add them.
    
    Signed-off-by: Hebbar Gururaja <gururaja.hebbar@ti.com>
    Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Commits on Feb 6, 2013
  1. Merge remote-tracking branch 'ti-linux-kernel/ti-linux-kernel/ti-linu…

    Russ Dill authored
    …x-3.8-rc5' into omap5_pm-3.8-rc5
Commits on Feb 1, 2013
  1. @t-kristo
  2. @t-kristo
  3. @t-kristo

    Merge branch 'paul_pwrdm_tweaks' into omap5_pm-3.8-rc5

    t-kristo authored
    Conflicts:
    	arch/arm/mach-omap2/clockdomain.h
    
    Signed-off-by: Tero Kristo <t-kristo@ti.com>
Commits on Jan 31, 2013
  1. @VaibhavBedia-xx

    ARM: OMAP2+: AM33XX: Hookup AM33XX PM code into OMAP builds

    VaibhavBedia-xx authored
    With all the requisite changes in place we can now
    enable basic PM support on AM33XX. This patch updates
    the various OMAP files to enable suspend-resume on
    AM33XX.
    
    Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
    Cc: Tony Lingren <tony@atomide.com>
    Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
    Cc: Benoit Cousson <b-cousson@ti.com>
    Cc: Paul Walmsley <paul@pwsan.com>
    Cc: Kevin Hilman <khilman@deeprootsystems.com>
  2. @VaibhavBedia-xx

    ARM: OMAP2+: AM33XX: Select Mailbox when PM is enabled

    VaibhavBedia-xx authored
    PM services on AM33XX depend on mailbox for communication
    with WKUP-M3 core so ensure that the right config options
    are selected. Thanks to Kevin Hilman <khilman@deeprootsystems.com>
    for the suggestion on updating the Kconfig and not just
    the omap2plus_defconfig which was done in the previous version
    of the AM33XX suspend-resume support.
    
    Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
    Cc: Tony Lingren <tony@atomide.com>
    Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
    Cc: Benoit Cousson <b-cousson@ti.com>
    Cc: Paul Walmsley <paul@pwsan.com>
    Cc: Kevin Hilman <khilman@deeprootsystems.com>
  3. @VaibhavBedia-xx

    ARM: OMAP2+: AM33XX: Basic suspend resume support

    VaibhavBedia-xx authored
    AM335x supports various low power modes as documented
    in section 8.1.4.3 of the AM335x TRM which is available
    @ http://www.ti.com/litv/pdf/spruh73f
    
    DeepSleep0 mode offers the lowest power mode with limited
    wakeup sources without a system reboot and is mapped as
    the suspend state in the kernel. In this state, MPU and
    PER domains are turned off with the internal RAM held in
    retention to facilitate resume process. As part of the boot
    process, the assembly code is copied over to OCMCRAM using
    the OMAP SRAM code.
    
    AM335x has a Cortex-M3 (WKUP_M3) which assists the MPU
    in DeepSleep0 entry and exit. WKUP_M3 takes care of the
    clockdomain and powerdomain transitions based on the
    intended low power state. MPU needs to load the appropriate
    WKUP_M3 binary onto the WKUP_M3 memory space before it can
    leverage any of the PM features like DeepSleep.
    
    The IPC mechanism between MPU and WKUP_M3 uses a mailbox
    sub-module and 8 IPC registers in the Control module. MPU
    uses the assigned Mailbox for issuing an interrupt to
    WKUP_M3 which then goes and checks the IPC registers for
    the payload. WKUP_M3 has the ability to trigger on interrupt
    to MPU by executing the "sev" instruction.
    
    In the current implementation when the suspend process
    is initiated MPU interrupts the WKUP_M3 to let it know about
    the intent of entering DeepSleep0 and waits for an ACK. When
    the ACK is received MPU continues with its suspend process
    to suspend all the drivers and then jumps to assembly in
    OCMC RAM. The assembly code puts the PLLs in bypass, puts the
    external RAM in self-refresh mode and then finally execute the
    WFI instruction. Execution of the WFI instruction triggers another
    interrupt to the WKUP_M3 which then continues wiht the power down
    sequence wherein the clockdomain and powerdomain transition takes
    place. As part of the sleep sequence, WKUP_M3 unmasks the interrupt
    lines for the wakeup sources. WFI execution on WKUP_M3 causes the
    hardware to disable the main oscillator of the SoC.
    
    When a wakeup event occurs, WKUP_M3 starts the power-up
    sequence by switching on the power domains and finally
    enabling the clock to MPU. Since the MPU gets powered down
    as part of the sleep sequence in the resume path ROM code
    starts executing. The ROM code detects a wakeup from sleep
    and then jumps to the resume location in OCMC which was
    populated in one of the IPC registers as part of the suspend
    sequence.
    
    The low level code in OCMC relocks the PLLs, enables access
    to external RAM and then jumps to the cpu_resume code of
    the kernel to finish the resume process.
    
    Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
    Cc: Tony Lingren <tony@atomide.com>
    Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
    Cc: Benoit Cousson <b-cousson@ti.com>
    Cc: Paul Walmsley <paul@pwsan.com>
    Cc: Kevin Hilman <khilman@deeprootsystems.com>
  4. @VaibhavBedia-xx

    ARM: OMAP2+: AM33XX: Add assembly code for PM operations

    VaibhavBedia-xx authored
    In preparation for suspend-resume support for AM33XX, add
    the assembly file with the code which is copied to internal
    memory (OCMC RAM) during bootup and runs from there.
    
    As part of the low power entry (DeepSleep0 mode in AM33XX TRM),
    the code running from OCMC RAM does the following
    1. Stores the EMIF configuration
    2. Puts external memory in self-refresh
    3. Disables EMIF clock
    4. Puts the PLLs in bypass
    5. Executes WFI after writing to MPU_CLKCTRL register.
    
    If no interrupts have come, WFI execution on MPU gets registered
    as an interrupt with the WKUP-M3. WKUP-M3 takes care of disabling
    some clocks which MPU should not (L3, L4, OCMC RAM etc) and takes
    care of clockdomain and powerdomain transitions as part of the
    DeepSleep0 mode entry.
    
    In case a late interrupt comes in, WFI ends up as a NOP and MPU
    continues execution from internal memory. The 'abort path' code
    undoes whatever was done as part of the low power entry and indicates
    a suspend failure by passing a non-zero value to the cpu_resume routine.
    
    The 'resume path' code is similar to the 'abort path' with the key
    difference of MMU being enabled in the 'abort path' but being
    disabled in the 'resume path' due to MPU getting powered off.
    
    In addition to the top level steps outlined above, there are some
    additional register writes related to external memory controller
    which help in lowering the overall power consumption in the suspended
    state. These include changing the state of the IOs to LVCMOS mode
    and enabling pull downs on the IOs to reduce leakage in low power state.
    
    Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
    Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
    Cc: Kevin Hilman <khilman@deeprootsystems.com>
  5. @VaibhavBedia-xx

    ARM: OMAP2+: AM33XX: timer: Interchange clkevt and clksrc timers

    VaibhavBedia-xx authored
    AM33XX has two timers (DTIMER0/1) in the WKUP domain.
    On GP devices the source of DMTIMER0 is fixed to an
    inaccurate internal 32k RC oscillator and this makes
    the DMTIMER0 practically either as a clocksource or
    as clockevent.
    
    Currently the timer instance in WKUP domain is used
    as the clockevent and the timer in non-WKUP domain
    as the clocksource. DMTIMER1 in WKUP domain can keep
    running in suspend from a 32K clock fed from external
    OSC and can serve as the persistent clock for the kernel.
    To enable this, interchange the timers used as clocksource
    and clockevent for AM33XX.
    
    For now a new DT property has been added to allow the timer code
    to select the timer with the right property.
    
    It has been pointed out by Santosh Shilimkar and Kevin Hilman
    that such a change will result in soc-idle never being achieved
    on AM33XX. There are other reasons why soc-idle does not look
    feasible on AM33XX so for now we go ahead with the interchange
    of the the timers. If at a later point of time we do come up
    with an approach which makes soc-idle possible on AM33XX, this
    can be revisited.
    
    Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
    Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
    Cc: Tony Lingren <tony@atomide.com>
    Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
    Cc: Benoit Cousson <b-cousson@ti.com>
    Cc: Paul Walmsley <paul@pwsan.com>
    Cc: Kevin Hilman <khilman@deeprootsystems.com>
    Cc: Jon Hunter <jon-hunter@ti.com>
  6. @VaibhavBedia-xx

    ARM: OMAP2+: timer: Add suspend-resume callbacks for clockevent device

    VaibhavBedia-xx authored
    The current OMAP timer code registers two timers -
    one as clocksource and one as clockevent.
    AM33XX has only one usable timer in the WKUP domain
    so one of the timers needs suspend-resume support
    to restore the configuration to pre-suspend state.
    
    commit adc78e6 (timekeeping: Add suspend and resume
    of clock event devices) introduced .suspend and .resume
    callbacks for clock event devices. Leverages these
    callbacks to have AM33XX clockevent timer which is
    in not in WKUP domain to behave properly across system
    suspend.
    
    Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
    Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
    Cc: Benoit Cousson <b-cousson@ti.com>
    Cc: Paul Walmsley <paul@pwsan.com>
    Cc: Kevin Hilman <khilman@deeprootsystems.com>
    Cc: Vaibhav Hiremath <hvaibhav@ti.com>
    Cc: Jon Hunter <jon-hunter@ti.com>
  7. @VaibhavBedia-xx

    ARM: OMAP: DTB: Update IRQ data for WKUP_M3

    VaibhavBedia-xx authored
    Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
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