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Add support for custom vexriscv instructions #37

Merged
merged 3 commits into from Mar 11, 2020
Merged

Add support for custom vexriscv instructions #37

merged 3 commits into from Mar 11, 2020

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xobs
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@xobs xobs commented Mar 11, 2020

This adds a new namespace under "registers" to support the custom interrupt controller on vexriscv.

@xobs xobs requested a review from a team as a code owner March 11, 2020 01:59
@xobs xobs force-pushed the vexriscv branch 2 times, most recently from 3aa4c98 to fb9c6a8 Compare March 11, 2020 05:37
Disasm
Disasm suggested changes Mar 11, 2020
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Thank you for the contribution!
A few moments:

  1. Could you add module docs for the vexriscv module?
  2. It seems like vmip, vsip and vdci are read-only, not read-write

src/register/vexriscv/mod.rs Outdated Show resolved Hide resolved
src/register/mod.rs Outdated Show resolved Hide resolved
@xobs
register: add vexriscv-specific registers
54a0364 
VexRiscv contains its own custom registers for external interrupt
mapping.  Add these registers under the `register::vexriscv` namespace,
and prefix the assembly routines with "v-" in order to avoid ambiguity
with e.g. `sip` and `mip` registers.

Signed-off-by: Sean Cross <sean@xobs.io>
@xobs
bin: rebuild asm file with vexriscv instructions
8f7f541 
Signed-off-by: Sean Cross <sean@xobs.io>
@xobs
assemble: add powershell script
f54f90f 
This script allows Windows users to rebuild the assembly files.

Signed-off-by: Sean Cross <sean@xobs.io>
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xobs commented Mar 11, 2020

  1. I've added some module docs. Please let me know if that's what you're looking for, or if you'd prefer something else.

  2. You're correct: https://github.com/SpinalHDL/VexRiscv/blob/master/src/main/scala/vexriscv/plugin/ExternalInterruptArrayPlugin.scala#L25 and https://github.com/SpinalHDL/VexRiscv/blob/95237b23ea2d658cb3e0aa77680ca2851ef5d882/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala#L358 -- I'll update those to be readonly.

Disasm
Disasm approved these changes Mar 11, 2020
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Looks good, thank you!

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Disasm commented Mar 11, 2020

bors r+

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bors bot commented Mar 11, 2020

Build succeeded

@bors bors bot merged commit 30af64c into rust-embedded:master Mar 11, 2020
@Disasm Disasm mentioned this pull request Jun 10, 2020
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romancardenas pushed a commit that referenced this pull request Nov 17, 2023
@bors @Disasm
Merge #37
0427294 
37: Fix _start_trap save/restore sequences r=laanwj a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>
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