diff --git a/riscv/CHANGELOG.md b/riscv/CHANGELOG.md
index 81f03add..2e709014 100644
--- a/riscv/CHANGELOG.md
+++ b/riscv/CHANGELOG.md
@@ -9,6 +9,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ### Added
 
+- Add `dcsratch0` and `dscratch1` CSRs
+- Add new `read-write_csr_as_usize` macro for registers
 - Add `dpc` CSR support for RISC-V
 - Add Mtopi
 - Added DCSR (Debug Control and Status Register) CSR support for the RISC-V
diff --git a/riscv/src/register.rs b/riscv/src/register.rs
index 4655facb..a38527db 100644
--- a/riscv/src/register.rs
+++ b/riscv/src/register.rs
@@ -132,3 +132,5 @@ mod tests;
 // TODO: Debug Mode Registers
 pub mod dcsr;
 pub mod dpc;
+pub mod dscratch0;
+pub mod dscratch1;
diff --git a/riscv/src/register/dscratch0.rs b/riscv/src/register/dscratch0.rs
new file mode 100644
index 00000000..f49687f9
--- /dev/null
+++ b/riscv/src/register/dscratch0.rs
@@ -0,0 +1,18 @@
+//! dscratch0
+
+read_write_csr_as_usize!(0x7b2);
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+    use crate::result::Error;
+
+    #[test]
+    fn test_dscratch0_read_write() {
+        for i in 0..usize::BITS {
+            let val = 1usize << i;
+            assert_eq!(unsafe { try_write(val) }, Err(Error::Unimplemented));
+            assert_eq!(try_read(), Err(Error::Unimplemented));
+        }
+    }
+}
diff --git a/riscv/src/register/dscratch1.rs b/riscv/src/register/dscratch1.rs
new file mode 100644
index 00000000..44db9e55
--- /dev/null
+++ b/riscv/src/register/dscratch1.rs
@@ -0,0 +1,18 @@
+//! dscratch1
+
+read_write_csr_as_usize!(0x7b3);
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+    use crate::result::Error;
+
+    #[test]
+    fn test_dscratch1_read_write() {
+        for i in 0..usize::BITS {
+            let val = 1usize << i;
+            assert_eq!(unsafe { try_write(val) }, Err(Error::Unimplemented));
+            assert_eq!(try_read(), Err(Error::Unimplemented));
+        }
+    }
+}
diff --git a/riscv/src/register/macros.rs b/riscv/src/register/macros.rs
index 255f0f4e..ef291857 100644
--- a/riscv/src/register/macros.rs
+++ b/riscv/src/register/macros.rs
@@ -301,6 +301,30 @@ macro_rules! write_csr_as_usize_rv32 {
     };
 }
 
+/// Convenience macro to provide combined read/write of a CSR as a `usize`.
+///
+/// This composes [`read_csr_as_usize`] and [`write_csr_as_usize`]. Use the
+/// `safe` form to get safe wrappers instead of unsafe.
+#[macro_export]
+macro_rules! read_write_csr_as_usize {
+    ($csr_number:literal) => {
+        $crate::read_csr_as_usize!($csr_number);
+        $crate::write_csr_as_usize!($csr_number);
+    };
+    (safe $csr_number:literal) => {
+        $crate::read_csr_as_usize!($csr_number);
+        $crate::write_csr_as_usize!(safe $csr_number);
+    };
+    ($csr_number:literal, $($cfg:meta),*) => {
+        $crate::read_csr_as_usize!($csr_number, $($cfg),*);
+        $crate::write_csr_as_usize!($csr_number, $($cfg),*);
+    };
+    (safe $csr_number:literal, $($cfg:meta),*) => {
+        $crate::read_csr_as_usize!($csr_number, $($cfg),*);
+        $crate::write_csr_as_usize!(safe $csr_number, $($cfg),*);
+    };
+}
+
 /// Convenience macro around the `csrrs` assembly instruction to set the CSR register.
 ///
 /// This macro is intended for use with the [set_csr](crate::set_csr) or [set_clear_csr](crate::set_clear_csr) macros.