From 5852eed8e3e67a3da5a73b629ec3857c9725ab6a Mon Sep 17 00:00:00 2001 From: KushalMeghani1644 Date: Tue, 11 Nov 2025 17:05:30 +0530 Subject: [PATCH 1/7] Implement dscratch0 and dscratch1 CSRs for RISC-V --- riscv/src/register.rs | 5 +++++ riscv/src/register/dscratch0.rs | 25 +++++++++++++++++++++++++ riscv/src/register/dscratch1.rs | 25 +++++++++++++++++++++++++ 3 files changed, 55 insertions(+) create mode 100644 riscv/src/register/dscratch0.rs create mode 100644 riscv/src/register/dscratch1.rs diff --git a/riscv/src/register.rs b/riscv/src/register.rs index 4655facb..bc0a240a 100644 --- a/riscv/src/register.rs +++ b/riscv/src/register.rs @@ -131,4 +131,9 @@ mod tests; // TODO: Debug Mode Registers pub mod dcsr; +<<<<<<< HEAD pub mod dpc; +======= +pub mod dscratch0; +pub mod dscratch1; +>>>>>>> d078ccf (Implement dscratch0 and dscratch1 CSRs for RISC-V) diff --git a/riscv/src/register/dscratch0.rs b/riscv/src/register/dscratch0.rs new file mode 100644 index 00000000..c20c014c --- /dev/null +++ b/riscv/src/register/dscratch0.rs @@ -0,0 +1,25 @@ +//! dscratch0 + +read_write_csr! { + /// Debug scratch register 0 + Dscratch0: 0x7b2, + mask: usize::MAX, +} + +#[cfg(test)] +mod tests { + use super::*; + + #[test] + fn test_dscratch0_mask() { + let reg = Dscratch0::from_bits(usize::MAX); + assert_eq!(reg.bits(), usize::MAX); + assert_eq!(Dscratch0::BITMASK, usize::MAX); + } + + #[test] + fn test_dscratch0_roundtrip() { + let reg = Dscratch0::from_bits(0xDEAD_BEEFusize); + assert_eq!(reg.bits(), 0xDEAD_BEEFusize); + } +} diff --git a/riscv/src/register/dscratch1.rs b/riscv/src/register/dscratch1.rs new file mode 100644 index 00000000..33f41279 --- /dev/null +++ b/riscv/src/register/dscratch1.rs @@ -0,0 +1,25 @@ +//! dscratch1 + +read_write_csr! { + /// Debug scratch register 1 + Dscratch1: 0x7b3, + mask: usize::MAX, +} + +#[cfg(test)] +mod tests { + use super::*; + + #[test] + fn test_dscratch1_mask() { + let reg = Dscratch1::from_bits(usize::MAX); + assert_eq!(reg.bits(), usize::MAX); + assert_eq!(Dscratch1::BITMASK, usize::MAX); + } + + #[test] + fn test_dscratch1_roundtrip() { + let reg = Dscratch1::from_bits(0xDEAD_BEEFusize); + assert_eq!(reg.bits(), 0xDEAD_BEEFusize); + } +} From fe00a3f8319910e5cb869eae25e5a6169d9ebb5f Mon Sep 17 00:00:00 2001 From: KushalMeghani1644 Date: Thu, 13 Nov 2025 18:31:03 +0530 Subject: [PATCH 2/7] Update CHANGELOG.md --- riscv/CHANGELOG.md | 1 + 1 file changed, 1 insertion(+) diff --git a/riscv/CHANGELOG.md b/riscv/CHANGELOG.md index 81f03add..998f2202 100644 --- a/riscv/CHANGELOG.md +++ b/riscv/CHANGELOG.md @@ -9,6 +9,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/). ### Added +- Add `dcsratch0` and `dscratch1` CSRs - Add `dpc` CSR support for RISC-V - Add Mtopi - Added DCSR (Debug Control and Status Register) CSR support for the RISC-V From 4f9c04cf0e4ac6f7108d3d500c28e42464d40104 Mon Sep 17 00:00:00 2001 From: KushalMeghani1644 Date: Fri, 14 Nov 2025 13:30:43 +0530 Subject: [PATCH 3/7] Update macros.rs to add read_write_csr_as_usize and update dscratch0 and dcsratch1 to use them instead of read_write_csr macro --- riscv/src/register/dscratch0.rs | 6 +----- riscv/src/register/dscratch1.rs | 6 +----- riscv/src/register/macros.rs | 24 ++++++++++++++++++++++++ 3 files changed, 26 insertions(+), 10 deletions(-) diff --git a/riscv/src/register/dscratch0.rs b/riscv/src/register/dscratch0.rs index c20c014c..e29a049d 100644 --- a/riscv/src/register/dscratch0.rs +++ b/riscv/src/register/dscratch0.rs @@ -1,10 +1,6 @@ //! dscratch0 -read_write_csr! { - /// Debug scratch register 0 - Dscratch0: 0x7b2, - mask: usize::MAX, -} +read_write_csr_as_usize!(Dscratch0, 0x7b2); #[cfg(test)] mod tests { diff --git a/riscv/src/register/dscratch1.rs b/riscv/src/register/dscratch1.rs index 33f41279..3361a602 100644 --- a/riscv/src/register/dscratch1.rs +++ b/riscv/src/register/dscratch1.rs @@ -1,10 +1,6 @@ //! dscratch1 -read_write_csr! { - /// Debug scratch register 1 - Dscratch1: 0x7b3, - mask: usize::MAX, -} +read_write_csr_as_usize!(Dscratch1, 0x7b3); #[cfg(test)] mod tests { diff --git a/riscv/src/register/macros.rs b/riscv/src/register/macros.rs index 255f0f4e..ef291857 100644 --- a/riscv/src/register/macros.rs +++ b/riscv/src/register/macros.rs @@ -301,6 +301,30 @@ macro_rules! write_csr_as_usize_rv32 { }; } +/// Convenience macro to provide combined read/write of a CSR as a `usize`. +/// +/// This composes [`read_csr_as_usize`] and [`write_csr_as_usize`]. Use the +/// `safe` form to get safe wrappers instead of unsafe. +#[macro_export] +macro_rules! read_write_csr_as_usize { + ($csr_number:literal) => { + $crate::read_csr_as_usize!($csr_number); + $crate::write_csr_as_usize!($csr_number); + }; + (safe $csr_number:literal) => { + $crate::read_csr_as_usize!($csr_number); + $crate::write_csr_as_usize!(safe $csr_number); + }; + ($csr_number:literal, $($cfg:meta),*) => { + $crate::read_csr_as_usize!($csr_number, $($cfg),*); + $crate::write_csr_as_usize!($csr_number, $($cfg),*); + }; + (safe $csr_number:literal, $($cfg:meta),*) => { + $crate::read_csr_as_usize!($csr_number, $($cfg),*); + $crate::write_csr_as_usize!(safe $csr_number, $($cfg),*); + }; +} + /// Convenience macro around the `csrrs` assembly instruction to set the CSR register. /// /// This macro is intended for use with the [set_csr](crate::set_csr) or [set_clear_csr](crate::set_clear_csr) macros. From 4cf193a22b8b7d2ca220b7614d71b7c27879b2f2 Mon Sep 17 00:00:00 2001 From: KushalMeghani1644 Date: Fri, 14 Nov 2025 13:36:20 +0530 Subject: [PATCH 4/7] resolve conflict --- riscv/src/register.rs | 3 --- 1 file changed, 3 deletions(-) diff --git a/riscv/src/register.rs b/riscv/src/register.rs index bc0a240a..a38527db 100644 --- a/riscv/src/register.rs +++ b/riscv/src/register.rs @@ -131,9 +131,6 @@ mod tests; // TODO: Debug Mode Registers pub mod dcsr; -<<<<<<< HEAD pub mod dpc; -======= pub mod dscratch0; pub mod dscratch1; ->>>>>>> d078ccf (Implement dscratch0 and dscratch1 CSRs for RISC-V) From 8eabc412e507148ec77c37f9e0d20c99ab4e3360 Mon Sep 17 00:00:00 2001 From: KushalMeghani1644 Date: Fri, 14 Nov 2025 15:00:27 +0530 Subject: [PATCH 5/7] Fix errors --- riscv/src/register/dscratch0.rs | 18 +++++++----------- riscv/src/register/dscratch1.rs | 18 +++++++----------- 2 files changed, 14 insertions(+), 22 deletions(-) diff --git a/riscv/src/register/dscratch0.rs b/riscv/src/register/dscratch0.rs index e29a049d..feafb991 100644 --- a/riscv/src/register/dscratch0.rs +++ b/riscv/src/register/dscratch0.rs @@ -1,21 +1,17 @@ //! dscratch0 -read_write_csr_as_usize!(Dscratch0, 0x7b2); +read_write_csr_as_usize!(0x7b2); #[cfg(test)] mod tests { use super::*; #[test] - fn test_dscratch0_mask() { - let reg = Dscratch0::from_bits(usize::MAX); - assert_eq!(reg.bits(), usize::MAX); - assert_eq!(Dscratch0::BITMASK, usize::MAX); - } - - #[test] - fn test_dscratch0_roundtrip() { - let reg = Dscratch0::from_bits(0xDEAD_BEEFusize); - assert_eq!(reg.bits(), 0xDEAD_BEEFusize); + fn test_dscratch0_read_write() { + for i in 0..usize::BITS { + let val = 1usize << i; + let _ = unsafe { try_write(val) }; + let _ = try_read(); + } } } diff --git a/riscv/src/register/dscratch1.rs b/riscv/src/register/dscratch1.rs index 3361a602..32a4a534 100644 --- a/riscv/src/register/dscratch1.rs +++ b/riscv/src/register/dscratch1.rs @@ -1,21 +1,17 @@ //! dscratch1 -read_write_csr_as_usize!(Dscratch1, 0x7b3); +read_write_csr_as_usize!(0x7b3); #[cfg(test)] mod tests { use super::*; #[test] - fn test_dscratch1_mask() { - let reg = Dscratch1::from_bits(usize::MAX); - assert_eq!(reg.bits(), usize::MAX); - assert_eq!(Dscratch1::BITMASK, usize::MAX); - } - - #[test] - fn test_dscratch1_roundtrip() { - let reg = Dscratch1::from_bits(0xDEAD_BEEFusize); - assert_eq!(reg.bits(), 0xDEAD_BEEFusize); + fn test_dscratch1_read_write() { + for i in 0..usize::BITS { + let val = 1usize << i; + let _ = unsafe { try_write(val) }; + let _ = try_read(); + } } } From 64dec8a2ff3c78c95a9342d01ea4a02c4904ecd2 Mon Sep 17 00:00:00 2001 From: KushalMeghani1644 Date: Fri, 14 Nov 2025 21:23:41 +0530 Subject: [PATCH 6/7] Update tests --- riscv/src/register/dscratch0.rs | 5 +++-- riscv/src/register/dscratch1.rs | 5 +++-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/riscv/src/register/dscratch0.rs b/riscv/src/register/dscratch0.rs index feafb991..f49687f9 100644 --- a/riscv/src/register/dscratch0.rs +++ b/riscv/src/register/dscratch0.rs @@ -5,13 +5,14 @@ read_write_csr_as_usize!(0x7b2); #[cfg(test)] mod tests { use super::*; + use crate::result::Error; #[test] fn test_dscratch0_read_write() { for i in 0..usize::BITS { let val = 1usize << i; - let _ = unsafe { try_write(val) }; - let _ = try_read(); + assert_eq!(unsafe { try_write(val) }, Err(Error::Unimplemented)); + assert_eq!(try_read(), Err(Error::Unimplemented)); } } } diff --git a/riscv/src/register/dscratch1.rs b/riscv/src/register/dscratch1.rs index 32a4a534..44db9e55 100644 --- a/riscv/src/register/dscratch1.rs +++ b/riscv/src/register/dscratch1.rs @@ -5,13 +5,14 @@ read_write_csr_as_usize!(0x7b3); #[cfg(test)] mod tests { use super::*; + use crate::result::Error; #[test] fn test_dscratch1_read_write() { for i in 0..usize::BITS { let val = 1usize << i; - let _ = unsafe { try_write(val) }; - let _ = try_read(); + assert_eq!(unsafe { try_write(val) }, Err(Error::Unimplemented)); + assert_eq!(try_read(), Err(Error::Unimplemented)); } } } From f8565d9c3e31707472ae770c768d5a4ddbd67cbd Mon Sep 17 00:00:00 2001 From: Kushal Meghani <168952248+KushalMeghani1644@users.noreply.github.com> Date: Fri, 14 Nov 2025 21:13:49 +0530 Subject: [PATCH 7/7] Update riscv/CHANGELOG.md MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Co-authored-by: Román Cárdenas Rodríguez --- riscv/CHANGELOG.md | 1 + 1 file changed, 1 insertion(+) diff --git a/riscv/CHANGELOG.md b/riscv/CHANGELOG.md index 998f2202..2e709014 100644 --- a/riscv/CHANGELOG.md +++ b/riscv/CHANGELOG.md @@ -10,6 +10,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/). ### Added - Add `dcsratch0` and `dscratch1` CSRs +- Add new `read-write_csr_as_usize` macro for registers - Add `dpc` CSR support for RISC-V - Add Mtopi - Added DCSR (Debug Control and Status Register) CSR support for the RISC-V