From 23925f7021b1e2332175c19bebc373e73b01c287 Mon Sep 17 00:00:00 2001 From: Hennadii Chernyshchuk Date: Thu, 13 Nov 2025 15:47:55 +0200 Subject: [PATCH 1/8] Feature-gate csr instructions Add `no-mhartid` and `no-xtvec`. Necessary to run on `picorv32`. --- riscv-rt/Cargo.toml | 2 ++ riscv-rt/src/asm.rs | 12 ++++++++---- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml index 7afdbc76..41890d39 100644 --- a/riscv-rt/Cargo.toml +++ b/riscv-rt/Cargo.toml @@ -42,7 +42,9 @@ v-trap = ["riscv-rt-macros/v-trap", "riscv/rt-v-trap"] u-boot = ["riscv-rt-macros/u-boot", "single-hart"] no-interrupts = [] no-exceptions = [] +no-mhartid = [] no-xie-xip = [] +no-xtvec = [] device = [] memory = [] defmt = ["dep:defmt"] diff --git a/riscv-rt/src/asm.rs b/riscv-rt/src/asm.rs index f89d58e5..66b52469 100644 --- a/riscv-rt/src/asm.rs +++ b/riscv-rt/src/asm.rs @@ -71,13 +71,17 @@ _abs_start: #[cfg(all(not(feature = "s-mode"), not(feature = "no-xie-xip")))] "csrw mie, 0 csrw mip, 0", - #[cfg(not(feature = "s-mode"))] - "csrr a0, mhartid", // Make sure that the hart ID is in a0 in M-mode + // Make sure that the hart ID is in a0 in M-mode + #[cfg(all(not(feature = "s-mode"), not(feature = "no-mhartid")))] + "csrr a0, mhartid", + #[cfg(all(not(feature = "s-mode"), feature = "no-mhartid"))] + "li a0, 0", // Set pre-init trap vector + #[cfg(not(feature = "no-xtvec"))] "la t0, _pre_init_trap", - #[cfg(feature = "s-mode")] + #[cfg(all(feature = "s-mode", not(feature = "no-xtvec")))] "csrw stvec, t0", - #[cfg(not(feature = "s-mode"))] + #[cfg(all(not(feature = "s-mode"), not(feature = "no-xtvec")))] "csrw mtvec, t0", // If multi-hart, assert that hart ID is valid #[cfg(not(feature = "single-hart"))] From c158f190a2c8670ff3af54f82cac775396a92bb9 Mon Sep 17 00:00:00 2001 From: Hennadii Chernyshchuk Date: Thu, 13 Nov 2025 21:12:11 +0200 Subject: [PATCH 2/8] Update CHANGELOG.md --- riscv-rt/CHANGELOG.md | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/riscv-rt/CHANGELOG.md b/riscv-rt/CHANGELOG.md index 7fc255a1..b7a7f5ac 100644 --- a/riscv-rt/CHANGELOG.md +++ b/riscv-rt/CHANGELOG.md @@ -7,6 +7,12 @@ and this project adheres to [Semantic Versioning](http://semver.org/). ## [Unreleased] +### Added + +- New `no-mhartid` feature to load 0 to `a0` instead of reading `mhartid`. +- New `no-xtvec` feature that removes interrupt stuff. + + ### Changed - Update license to `MIT or Apache-2.0` From b71e121b53a69348fc2b6b4cede937f42e014747 Mon Sep 17 00:00:00 2001 From: Hennadii Chernyshchyk Date: Fri, 14 Nov 2025 16:58:54 +0200 Subject: [PATCH 3/8] Require `single-hart` --- riscv-rt/Cargo.toml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml index 41890d39..f81c0191 100644 --- a/riscv-rt/Cargo.toml +++ b/riscv-rt/Cargo.toml @@ -42,7 +42,7 @@ v-trap = ["riscv-rt-macros/v-trap", "riscv/rt-v-trap"] u-boot = ["riscv-rt-macros/u-boot", "single-hart"] no-interrupts = [] no-exceptions = [] -no-mhartid = [] +no-mhartid = ["single-hart"] no-xie-xip = [] no-xtvec = [] device = [] From 7948f61651dcf231b6aebf4fefcbf8d87e056dce Mon Sep 17 00:00:00 2001 From: Hennadii Chernyshchyk Date: Fri, 14 Nov 2025 17:02:38 +0200 Subject: [PATCH 4/8] Refactor cfgs --- riscv-rt/src/asm.rs | 31 ++++++++++++++++++------------- 1 file changed, 18 insertions(+), 13 deletions(-) diff --git a/riscv-rt/src/asm.rs b/riscv-rt/src/asm.rs index 66b52469..a11fce44 100644 --- a/riscv-rt/src/asm.rs +++ b/riscv-rt/src/asm.rs @@ -68,21 +68,26 @@ _abs_start: #[cfg(all(feature = "s-mode", not(feature = "no-xie-xip")))] "csrw sie, 0 csrw sip, 0", - #[cfg(all(not(feature = "s-mode"), not(feature = "no-xie-xip")))] - "csrw mie, 0 - csrw mip, 0", - // Make sure that the hart ID is in a0 in M-mode - #[cfg(all(not(feature = "s-mode"), not(feature = "no-mhartid")))] - "csrr a0, mhartid", - #[cfg(all(not(feature = "s-mode"), feature = "no-mhartid"))] - "li a0, 0", + #[cfg(not(feature = "s-mode"))] + { + #[cfg(not(feature = "no-xie-xip"))] + "csrw mie, 0 + csrw mip, 0", + // Make sure that the hart ID is in a0 in M-mode + #[cfg(not(feature = "no-mhartid"))] + "csrr a0, mhartid", + #[cfg(feature = "no-mhartid")] + "li a0, 0", + }, // Set pre-init trap vector #[cfg(not(feature = "no-xtvec"))] - "la t0, _pre_init_trap", - #[cfg(all(feature = "s-mode", not(feature = "no-xtvec")))] - "csrw stvec, t0", - #[cfg(all(not(feature = "s-mode"), not(feature = "no-xtvec")))] - "csrw mtvec, t0", + { + "la t0, _pre_init_trap", + #[cfg(feature = "s-mode")] + "csrw stvec, t0", + #[cfg(not(feature = "s-mode"))] + "csrw mtvec, t0", + }, // If multi-hart, assert that hart ID is valid #[cfg(not(feature = "single-hart"))] "lui t0, %hi(_max_hart_id) From 992ee1e4212a3237e20fb5182842104237fc47a6 Mon Sep 17 00:00:00 2001 From: Hennadii Chernyshchyk Date: Fri, 14 Nov 2025 17:02:52 +0200 Subject: [PATCH 5/8] Remove extra newline --- riscv-rt/CHANGELOG.md | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/riscv-rt/CHANGELOG.md b/riscv-rt/CHANGELOG.md index b7a7f5ac..bb82c85d 100644 --- a/riscv-rt/CHANGELOG.md +++ b/riscv-rt/CHANGELOG.md @@ -12,7 +12,6 @@ and this project adheres to [Semantic Versioning](http://semver.org/). - New `no-mhartid` feature to load 0 to `a0` instead of reading `mhartid`. - New `no-xtvec` feature that removes interrupt stuff. - ### Changed - Update license to `MIT or Apache-2.0` @@ -29,7 +28,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/). ### Added - New `post-init` feature to run a Rust `__post_init` function before jumping to `main`. -- New `#[riscv_rt::post_init]` attribute to aid in the definition of the `__post_init` function. +- New `#[riscv_rt::post_init]` attribute to aid in the definition of the `__post_init` function. - Added `.uninit` section to the linker file. Due to its similarities with `.bss`, the linker will place this new section in `REGION_BSS`. - Additional feature `no-xie-xip` to work on chips without the XIE and XIP CSRs (e.g. ESP32-C2, ESP32-C3) @@ -84,7 +83,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/). - New `device` feature to include `device.x` in `link.x`. This feature is based on the current implementation of `cortex-m-rt`. - New `memory` feature to include `memory.x` in `link.x`. This feature is based - on the current implementation of `cortex-m-rt`. However, in contrast with + on the current implementation of `cortex-m-rt`. However, in contrast with `cortex-m-rt`, including `memory.x` in the linker file is feature gated. The benefits of leaving this optional are backwards compatibility and allowing users to define less typical linker scripts that do not rely on a From 495f260c7c6fd6087a6a9a27740b4f83e7300595 Mon Sep 17 00:00:00 2001 From: Hennadii Chernyshchyk Date: Fri, 14 Nov 2025 17:04:30 +0200 Subject: [PATCH 6/8] Fix new clippy warnings --- riscv-rt/src/lib.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs index 4c3b79b5..f3b78339 100644 --- a/riscv-rt/src/lib.rs +++ b/riscv-rt/src/lib.rs @@ -729,9 +729,9 @@ pub unsafe extern "Rust" fn setup_interrupts() { let xtvec_val = match () { #[cfg(not(feature = "v-trap"))] - _ => Xtvec::new(_start_trap as usize, TrapMode::Direct), + _ => Xtvec::new(_start_trap as *const () as usize, TrapMode::Direct), #[cfg(feature = "v-trap")] - _ => Xtvec::new(_vector_table as usize, TrapMode::Vectored), + _ => Xtvec::new(_vector_table as *const () as usize, TrapMode::Vectored), }; xtvec::write(xtvec_val); } From c330ed084bd50a45b3c9cd5e35ea7b48d1d6cb98 Mon Sep 17 00:00:00 2001 From: Hennadii Chernyshchyk Date: Fri, 14 Nov 2025 18:04:06 +0200 Subject: [PATCH 7/8] Remove extra comma --- riscv-rt/src/asm.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/riscv-rt/src/asm.rs b/riscv-rt/src/asm.rs index a11fce44..cef84699 100644 --- a/riscv-rt/src/asm.rs +++ b/riscv-rt/src/asm.rs @@ -78,7 +78,7 @@ _abs_start: "csrr a0, mhartid", #[cfg(feature = "no-mhartid")] "li a0, 0", - }, + } // Set pre-init trap vector #[cfg(not(feature = "no-xtvec"))] { @@ -87,7 +87,7 @@ _abs_start: "csrw stvec, t0", #[cfg(not(feature = "s-mode"))] "csrw mtvec, t0", - }, + } // If multi-hart, assert that hart ID is valid #[cfg(not(feature = "single-hart"))] "lui t0, %hi(_max_hart_id) From 7d9d09dd29c3ebd3dacef40ae2884aeb5986651a Mon Sep 17 00:00:00 2001 From: Hennadii Chernyshchyk Date: Fri, 14 Nov 2025 18:08:32 +0200 Subject: [PATCH 8/8] Add docs --- riscv-rt/src/lib.rs | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs index f3b78339..8760495e 100644 --- a/riscv-rt/src/lib.rs +++ b/riscv-rt/src/lib.rs @@ -565,6 +565,15 @@ //! //! Saves a little code size if there is only one hart on the target. //! +//! ## `no-mhartid` +//! +//! Skips reading `mhartid` and uses 0 instead. Useful for targets that doesn't implement this instruction. +//! Automatically enables `single-hart`. +//! +//! ## `no-xtvec` +//! +//! Skips interrupts setup. +//! //! ## `s-mode` //! //! Supervisor mode. While most registers/instructions have variants for both `mcause` and