Add qemu CI

[KushalMeghani1644]

This PR adds a Github Actions workflow to build and execute RISC-V examples on QEMU, enabling detection of runtime bugs that static compilation checks may miss.

This PR addresses issue #311

[KushalMeghani1644]

ugh, I shall work on this more... thus I am making it a draft.

[KushalMeghani1644]

Hola @romancardenas I tried to add QEMU CI here but things are getting way harder, I have done multiple fixes but I just want to make sure the fact that am I even going in the right direction? (sorry for the noise in this PR btw)

[romancardenas]

Adding QEMU to the CI is not that easy. You must create working examples that produce an output that you can then check with something like xtasks. Check how rtic does this.

You must find a set of "illustrative" targets (e.g., e310x for riscv32imc, something else for riscv64gc...) and run examples there.

Again, it is quite a complex task, and I suggest you to leave it until you get more expertise on these subjects.

[KushalMeghani1644]

I see! Thanks for helping me out!! And I do agree/understand that setting up QEMU ci is very complex, but I feel it will be valuable challenge to give a shot. Even if it takes time, I think it would be fun learning experience! Appreciate your guidance!

[romancardenas]

Good luck with it! RTIC has a great CI that runs tests on Arm and RISC-V. You can learn a lot from their project. Also, you can check how the esp-rs folks do it.

[KushalMeghani1644]

Thanks alot for your guidance! I appreciate it alot.

[KushalMeghani1644]

HI @romancardenas I am sorry to ping you again & again... I tried a-lot to mirror the RTIC QEMU CI here and seeing the mixed results here... I need your help for further fixes and guidance for what I shall do next?

[KushalMeghani1644]

well @romancardenas I did a re-check of the RTIC crate's QEMU CI... and seems like it was easily fixable... now I just need your guidance upon what shall I change/update or what's wrong and what not! Thanks for your review and sorry for the disturbances.

[KushalMeghani1644]

@romancardenas sorry for the ping... but can you please help me figure out what to do here next... the QEMU CI passes... but I have a few doubts if the results are fine! Could you please review this once?

[romancardenas]

Hey @KushalMeghani1644

Sorry, but I currently have no time for advising and such activities. I can review contributions, but not helping people figure out how to add new functionalities. From what I can see, your QEMU tests are not useful, as the output is blank. You must set up a proper scenario with at least a working UART that allows us to print characters and check if the logic works.

Please, work out this locally, and once it works on your machine, push it here and check that it behaves exactly as it works on your machine.

[KushalMeghani1644]

Alright! sorry to disturb you... I will work on this ASAP!

[romancardenas]

Forget about the UART!

Use riscv-semihosting instead. It should work out of the box en qemu if semihisting enabled

[KushalMeghani1644]

OK, thanks for the suggestion @romancardenas ! I will use riscv-semihosting instead! and btw in my local test I was able to get this!

cargo run -p xtask -- qemu --target riscv32imac-unknown-none-elf --example hello
    Finished `dev` profile [unoptimized + debuginfo] target(s) in 0.03s
     Running `target/debug/xtask qemu --target riscv32imac-unknown-none-elf --example hello`
   Compiling riscv-rt v0.16.0 (/home/kushal/riscv/riscv-rt)
    Finished `release` profile [optimized] target(s) in 0.23s
HELLO_QEMU                                                                                                                      /2.5s
 cargo run -p xtask -- qemu --target riscv64gc-unknown-none-elf --example hello
    Finished `dev` profile [unoptimized + debuginfo] target(s) in 0.03s
     Running `target/debug/xtask qemu --target riscv64gc-unknown-none-elf --example hello`
   Compiling riscv-rt v0.16.0 (/home/kushal/riscv/riscv-rt)
    Finished `release` profile [optimized] target(s) in 0.24s
HELLO_QEMU

though this is indeed through UART... I will try and make it use riscv-semihosting!

[romancardenas]

Congrats! you are in the right track.

For this PR, two examples (one with UART, one with semihosting) could be enough. Using semihosting, you can make QEMU finish its execution so the CI can check the output with a baseline file to see if everything works as expected

[KushalMeghani1644]

Alright! thanks for the help @romancardenas I will soon push the new changes with one test using UART and one using riscv-semihosting

[KushalMeghani1644]

HEY! @romancardenas I pushed the new changes and seems like the new QEMU TESTS PASS with the expected output!