diff --git a/.lock b/.lock new file mode 100755 index 000000000..e69de29bb diff --git a/.nojekyll b/.nojekyll new file mode 100644 index 000000000..e69de29bb diff --git a/COPYRIGHT.txt b/COPYRIGHT.txt new file mode 100644 index 000000000..af77776cc --- /dev/null +++ b/COPYRIGHT.txt @@ -0,0 +1,45 @@ +These documentation pages include resources by third parties. This copyright +file applies only to those resources. The following third party resources are +included, and carry their own copyright notices and license terms: + +* Fira Sans (FiraSans-Regular.woff, FiraSans-Medium.woff): + + Copyright (c) 2014, Mozilla Foundation https://mozilla.org/ + with Reserved Font Name Fira Sans. + + Copyright (c) 2014, Telefonica S.A. + + Licensed under the SIL Open Font License, Version 1.1. + See FiraSans-LICENSE.txt. + +* rustdoc.css, main.js, and playpen.js: + + Copyright 2015 The Rust Developers. + Licensed under the Apache License, Version 2.0 (see LICENSE-APACHE.txt) or + the MIT license (LICENSE-MIT.txt) at your option. + +* normalize.css: + + Copyright (c) Nicolas Gallagher and Jonathan Neal. + Licensed under the MIT license (see LICENSE-MIT.txt). + +* Source Code Pro (SourceCodePro-Regular.woff, SourceCodePro-Semibold.woff): + + Copyright 2010, 2012 Adobe Systems Incorporated (http://www.adobe.com/), + with Reserved Font Name 'Source'. All Rights Reserved. Source is a trademark + of Adobe Systems Incorporated in the United States and/or other countries. + + Licensed under the SIL Open Font License, Version 1.1. + See SourceCodePro-LICENSE.txt. + +* Source Serif Pro (SourceSerifPro-Regular.ttf.woff, + SourceSerifPro-Bold.ttf.woff, SourceSerifPro-It.ttf.woff): + + Copyright 2014 Adobe Systems Incorporated (http://www.adobe.com/), with + Reserved Font Name 'Source'. All Rights Reserved. Source is a trademark of + Adobe Systems Incorporated in the United States and/or other countries. + + Licensed under the SIL Open Font License, Version 1.1. + See SourceSerifPro-LICENSE.txt. + +This copyright file is intended to be distributed with rustdoc output. diff --git a/FiraSans-LICENSE.txt b/FiraSans-LICENSE.txt new file mode 100644 index 000000000..d444ea92b --- /dev/null +++ b/FiraSans-LICENSE.txt @@ -0,0 +1,94 @@ +Digitized data copyright (c) 2012-2015, The Mozilla Foundation and Telefonica S.A. +with Reserved Font Name < Fira >, + +This Font Software is licensed under the SIL Open Font License, Version 1.1. +This license is copied below, and is also available with a FAQ at: +http://scripts.sil.org/OFL + + +----------------------------------------------------------- +SIL OPEN FONT LICENSE Version 1.1 - 26 February 2007 +----------------------------------------------------------- + +PREAMBLE +The goals of the Open Font License (OFL) are to stimulate worldwide +development of collaborative font projects, to support the font creation +efforts of academic and linguistic communities, and to provide a free and +open framework in which fonts may be shared and improved in partnership +with others. + +The OFL allows the licensed fonts to be used, studied, modified and +redistributed freely as long as they are not sold by themselves. The +fonts, including any derivative works, can be bundled, embedded, +redistributed and/or sold with any software provided that any reserved +names are not used by derivative works. The fonts and derivatives, +however, cannot be released under any other type of license. The +requirement for fonts to remain under this license does not apply +to any document created using the fonts or their derivatives. + +DEFINITIONS +"Font Software" refers to the set of files released by the Copyright +Holder(s) under this license and clearly marked as such. This may +include source files, build scripts and documentation. + +"Reserved Font Name" refers to any names specified as such after the +copyright statement(s). + +"Original Version" refers to the collection of Font Software components as +distributed by the Copyright Holder(s). + +"Modified Version" refers to any derivative made by adding to, deleting, +or substituting -- in part or in whole -- any of the components of the +Original Version, by changing formats or by porting the Font Software to a +new environment. + +"Author" refers to any designer, engineer, programmer, technical +writer or other person who contributed to the Font Software. + +PERMISSION & CONDITIONS +Permission is hereby granted, free of charge, to any person obtaining +a copy of the Font Software, to use, study, copy, merge, embed, modify, +redistribute, and sell modified and unmodified copies of the Font +Software, subject to the following conditions: + +1) Neither the Font Software nor any of its individual components, +in Original or Modified Versions, may be sold by itself. + +2) Original or Modified Versions of the Font Software may be bundled, +redistributed and/or sold with any software, provided that each copy +contains the above copyright notice and this license. These can be +included either as stand-alone text files, human-readable headers or +in the appropriate machine-readable metadata fields within text or +binary files as long as those fields can be easily viewed by the user. + +3) No Modified Version of the Font Software may use the Reserved Font +Name(s) unless explicit written permission is granted by the corresponding +Copyright Holder. This restriction only applies to the primary font name as +presented to the users. + +4) The name(s) of the Copyright Holder(s) or the Author(s) of the Font +Software shall not be used to promote, endorse or advertise any +Modified Version, except to acknowledge the contribution(s) of the +Copyright Holder(s) and the Author(s) or with their explicit written +permission. + +5) The Font Software, modified or unmodified, in part or in whole, +must be distributed entirely under this license, and must not be +distributed under any other license. The requirement for fonts to +remain under this license does not apply to any document created +using the Font Software. + +TERMINATION +This license becomes null and void if any of the above conditions are +not met. + +DISCLAIMER +THE FONT SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT +OF COPYRIGHT, PATENT, TRADEMARK, OR OTHER RIGHT. IN NO EVENT SHALL THE +COPYRIGHT HOLDER BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +INCLUDING ANY GENERAL, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL +DAMAGES, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF THE USE OR INABILITY TO USE THE FONT SOFTWARE OR FROM +OTHER DEALINGS IN THE FONT SOFTWARE. diff --git a/FiraSans-Medium.woff b/FiraSans-Medium.woff new file mode 100644 index 000000000..7d742c5fb Binary files /dev/null and b/FiraSans-Medium.woff differ diff --git a/FiraSans-Regular.woff b/FiraSans-Regular.woff new file mode 100644 index 000000000..d8e0363f4 Binary files /dev/null and b/FiraSans-Regular.woff differ diff --git a/LICENSE-APACHE.txt b/LICENSE-APACHE.txt new file mode 100644 index 000000000..16fe87b06 --- /dev/null +++ b/LICENSE-APACHE.txt @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + +TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + +1. 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IN NO EVENT +SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR +IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +DEALINGS IN THE SOFTWARE. diff --git a/SourceCodePro-LICENSE.txt b/SourceCodePro-LICENSE.txt new file mode 100644 index 000000000..07542572e --- /dev/null +++ b/SourceCodePro-LICENSE.txt @@ -0,0 +1,93 @@ +Copyright 2010, 2012 Adobe Systems Incorporated (http://www.adobe.com/), with Reserved Font Name 'Source'. All Rights Reserved. Source is a trademark of Adobe Systems Incorporated in the United States and/or other countries. + +This Font Software is licensed under the SIL Open Font License, Version 1.1. + +This license is copied below, and is also available with a FAQ at: http://scripts.sil.org/OFL + + +----------------------------------------------------------- +SIL OPEN FONT LICENSE Version 1.1 - 26 February 2007 +----------------------------------------------------------- + +PREAMBLE +The goals of the Open Font License (OFL) are to stimulate worldwide +development of collaborative font projects, to support the font creation +efforts of academic and linguistic communities, and to provide a free and +open framework in which fonts may be shared and improved in partnership +with others. + +The OFL allows the licensed fonts to be used, studied, modified and +redistributed freely as long as they are not sold by themselves. The +fonts, including any derivative works, can be bundled, embedded, +redistributed and/or sold with any software provided that any reserved +names are not used by derivative works. The fonts and derivatives, +however, cannot be released under any other type of license. The +requirement for fonts to remain under this license does not apply +to any document created using the fonts or their derivatives. + +DEFINITIONS +"Font Software" refers to the set of files released by the Copyright +Holder(s) under this license and clearly marked as such. This may +include source files, build scripts and documentation. + +"Reserved Font Name" refers to any names specified as such after the +copyright statement(s). + +"Original Version" refers to the collection of Font Software components as +distributed by the Copyright Holder(s). + +"Modified Version" refers to any derivative made by adding to, deleting, +or substituting -- in part or in whole -- any of the components of the +Original Version, by changing formats or by porting the Font Software to a +new environment. + +"Author" refers to any designer, engineer, programmer, technical +writer or other person who contributed to the Font Software. + +PERMISSION & CONDITIONS +Permission is hereby granted, free of charge, to any person obtaining +a copy of the Font Software, to use, study, copy, merge, embed, modify, +redistribute, and sell modified and unmodified copies of the Font +Software, subject to the following conditions: + +1) Neither the Font Software nor any of its individual components, +in Original or Modified Versions, may be sold by itself. + +2) Original or Modified Versions of the Font Software may be bundled, +redistributed and/or sold with any software, provided that each copy +contains the above copyright notice and this license. These can be +included either as stand-alone text files, human-readable headers or +in the appropriate machine-readable metadata fields within text or +binary files as long as those fields can be easily viewed by the user. + +3) No Modified Version of the Font Software may use the Reserved Font +Name(s) unless explicit written permission is granted by the corresponding +Copyright Holder. This restriction only applies to the primary font name as +presented to the users. + +4) The name(s) of the Copyright Holder(s) or the Author(s) of the Font +Software shall not be used to promote, endorse or advertise any +Modified Version, except to acknowledge the contribution(s) of the +Copyright Holder(s) and the Author(s) or with their explicit written +permission. + +5) The Font Software, modified or unmodified, in part or in whole, +must be distributed entirely under this license, and must not be +distributed under any other license. The requirement for fonts to +remain under this license does not apply to any document created +using the Font Software. + +TERMINATION +This license becomes null and void if any of the above conditions are +not met. + +DISCLAIMER +THE FONT SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT +OF COPYRIGHT, PATENT, TRADEMARK, OR OTHER RIGHT. IN NO EVENT SHALL THE +COPYRIGHT HOLDER BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +INCLUDING ANY GENERAL, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL +DAMAGES, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF THE USE OR INABILITY TO USE THE FONT SOFTWARE OR FROM +OTHER DEALINGS IN THE FONT SOFTWARE. diff --git a/SourceCodePro-Regular.woff b/SourceCodePro-Regular.woff new file mode 100644 index 000000000..557667090 Binary files /dev/null and b/SourceCodePro-Regular.woff differ diff --git a/SourceCodePro-Semibold.woff b/SourceCodePro-Semibold.woff new file mode 100644 index 000000000..ca972a11d Binary files /dev/null and b/SourceCodePro-Semibold.woff differ diff --git a/SourceSerifPro-Bold.ttf.woff b/SourceSerifPro-Bold.ttf.woff new file mode 100644 index 000000000..ca254318f Binary files /dev/null and b/SourceSerifPro-Bold.ttf.woff differ diff --git a/SourceSerifPro-It.ttf.woff b/SourceSerifPro-It.ttf.woff new file mode 100644 index 000000000..a287bbe6e Binary files /dev/null and b/SourceSerifPro-It.ttf.woff differ diff --git a/SourceSerifPro-LICENSE.md b/SourceSerifPro-LICENSE.md new file mode 100644 index 000000000..22cb755f2 --- /dev/null +++ b/SourceSerifPro-LICENSE.md @@ -0,0 +1,93 @@ +Copyright 2014-2018 Adobe (http://www.adobe.com/), with Reserved Font Name 'Source'. All Rights Reserved. Source is a trademark of Adobe in the United States and/or other countries. + +This Font Software is licensed under the SIL Open Font License, Version 1.1. + +This license is copied below, and is also available with a FAQ at: http://scripts.sil.org/OFL + + +----------------------------------------------------------- +SIL OPEN FONT LICENSE Version 1.1 - 26 February 2007 +----------------------------------------------------------- + +PREAMBLE +The goals of the Open Font License (OFL) are to stimulate worldwide +development of collaborative font projects, to support the font creation +efforts of academic and linguistic communities, and to provide a free and +open framework in which fonts may be shared and improved in partnership +with others. + +The OFL allows the licensed fonts to be used, studied, modified and +redistributed freely as long as they are not sold by themselves. The +fonts, including any derivative works, can be bundled, embedded, +redistributed and/or sold with any software provided that any reserved +names are not used by derivative works. The fonts and derivatives, +however, cannot be released under any other type of license. The +requirement for fonts to remain under this license does not apply +to any document created using the fonts or their derivatives. + +DEFINITIONS +"Font Software" refers to the set of files released by the Copyright +Holder(s) under this license and clearly marked as such. This may +include source files, build scripts and documentation. + +"Reserved Font Name" refers to any names specified as such after the +copyright statement(s). + +"Original Version" refers to the collection of Font Software components as +distributed by the Copyright Holder(s). + +"Modified Version" refers to any derivative made by adding to, deleting, +or substituting -- in part or in whole -- any of the components of the +Original Version, by changing formats or by porting the Font Software to a +new environment. + +"Author" refers to any designer, engineer, programmer, technical +writer or other person who contributed to the Font Software. + +PERMISSION & CONDITIONS +Permission is hereby granted, free of charge, to any person obtaining +a copy of the Font Software, to use, study, copy, merge, embed, modify, +redistribute, and sell modified and unmodified copies of the Font +Software, subject to the following conditions: + +1) Neither the Font Software nor any of its individual components, +in Original or Modified Versions, may be sold by itself. + +2) Original or Modified Versions of the Font Software may be bundled, +redistributed and/or sold with any software, provided that each copy +contains the above copyright notice and this license. These can be +included either as stand-alone text files, human-readable headers or +in the appropriate machine-readable metadata fields within text or +binary files as long as those fields can be easily viewed by the user. + +3) No Modified Version of the Font Software may use the Reserved Font +Name(s) unless explicit written permission is granted by the corresponding +Copyright Holder. This restriction only applies to the primary font name as +presented to the users. + +4) The name(s) of the Copyright Holder(s) or the Author(s) of the Font +Software shall not be used to promote, endorse or advertise any +Modified Version, except to acknowledge the contribution(s) of the +Copyright Holder(s) and the Author(s) or with their explicit written +permission. + +5) The Font Software, modified or unmodified, in part or in whole, +must be distributed entirely under this license, and must not be +distributed under any other license. The requirement for fonts to +remain under this license does not apply to any document created +using the Font Software. + +TERMINATION +This license becomes null and void if any of the above conditions are +not met. + +DISCLAIMER +THE FONT SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT +OF COPYRIGHT, PATENT, TRADEMARK, OR OTHER RIGHT. IN NO EVENT SHALL THE +COPYRIGHT HOLDER BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +INCLUDING ANY GENERAL, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL +DAMAGES, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF THE USE OR INABILITY TO USE THE FONT SOFTWARE OR FROM +OTHER DEALINGS IN THE FONT SOFTWARE. diff --git a/SourceSerifPro-Regular.ttf.woff b/SourceSerifPro-Regular.ttf.woff new file mode 100644 index 000000000..a3d55cfdf Binary files /dev/null and b/SourceSerifPro-Regular.ttf.woff differ diff --git a/brush.svg b/brush.svg new file mode 100644 index 000000000..ea266e856 --- /dev/null +++ b/brush.svg @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/cfg_if/all.html b/cfg_if/all.html new file mode 100644 index 000000000..9cf0d3aff --- /dev/null +++ b/cfg_if/all.html @@ -0,0 +1,3 @@ +List of all items in this crate

[−] + + List of all items

Macros

\ No newline at end of file diff --git a/cfg_if/index.html b/cfg_if/index.html new file mode 100644 index 000000000..12d0acc29 --- /dev/null +++ b/cfg_if/index.html @@ -0,0 +1,22 @@ +cfg_if - Rust

[−][src]Crate cfg_if

A macro for defining #[cfg] if-else statements.

+

The macro provided by this crate, cfg_if, is similar to the if/elif C +preprocessor macro by allowing definition of a cascade of #[cfg] cases, +emitting the implementation which matches first.

+

This allows you to conveniently provide a long list #[cfg]'d blocks of code +without having to rewrite each clause multiple times.

+

Example

+
+cfg_if::cfg_if! {
+    if #[cfg(unix)] {
+        fn foo() { /* unix specific functionality */ }
+    } else if #[cfg(target_pointer_width = "32")] {
+        fn foo() { /* non-unix, 32-bit functionality */ }
+    } else {
+        fn foo() { /* fallback implementation */ }
+    }
+}
+
+

Macros

+
cfg_if

The main macro provided by this crate. See crate documentation for more +information.

+
\ No newline at end of file diff --git a/cfg_if/macro.cfg_if!.html b/cfg_if/macro.cfg_if!.html new file mode 100644 index 000000000..36f9a6d55 --- /dev/null +++ b/cfg_if/macro.cfg_if!.html @@ -0,0 +1,10 @@ + + + + + + +

Redirecting to macro.cfg_if.html...

+ + + \ No newline at end of file diff --git a/cfg_if/macro.cfg_if.html b/cfg_if/macro.cfg_if.html new file mode 100644 index 000000000..4337233be --- /dev/null +++ b/cfg_if/macro.cfg_if.html @@ -0,0 +1,20 @@ +cfg_if::cfg_if - Rust

[−][src]Macro cfg_if::cfg_if

+macro_rules! cfg_if {
+    ($(
+        if #[cfg($($meta:meta),*)] { $($tokens:tt)* }
+    ) else * else {
+        $($tokens2:tt)*
+    }) => { ... };
+    (
+        if #[cfg($($i_met:meta),*)] { $($i_tokens:tt)* }
+        $(
+            else if #[cfg($($e_met:meta),*)] { $($e_tokens:tt)* }
+        )*
+    ) => { ... };
+    (@__items ($($not:meta,)*) ; ) => { ... };
+    (@__items ($($not:meta,)*) ; ( ($($m:meta),*) ($($tokens:tt)*) ), $($rest:tt)*) => { ... };
+    (@__identity $($tokens:tt)*) => { ... };
+}
+

The main macro provided by this crate. See crate documentation for more +information.

+
\ No newline at end of file diff --git a/cfg_if/sidebar-items.js b/cfg_if/sidebar-items.js new file mode 100644 index 000000000..dbc0f919b --- /dev/null +++ b/cfg_if/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({"macro":[["cfg_if","The main macro provided by this crate. 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i128x4","synthetic":false,"types":["packed_simd::v512::i128x4"]},{"text":"impl Eq for LexicographicallyOrdered<i128x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Eq for u128x4","synthetic":false,"types":["packed_simd::v512::u128x4"]},{"text":"impl Eq for LexicographicallyOrdered<u128x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Eq for m128x4","synthetic":false,"types":["packed_simd::v512::m128x4"]},{"text":"impl Eq for LexicographicallyOrdered<m128x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Eq for isizex2","synthetic":false,"types":["packed_simd::vSize::isizex2"]},{"text":"impl Eq for LexicographicallyOrdered<isizex2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Eq for usizex2","synthetic":false,"types":["packed_simd::vSize::usizex2"]},{"text":"impl Eq for LexicographicallyOrdered<usizex2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Eq for msizex2","synthetic":false,"types":["packed_simd::vSize::msizex2"]},{"text":"impl Eq for LexicographicallyOrdered<msizex2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Eq for isizex4","synthetic":false,"types":["packed_simd::vSize::isizex4"]},{"text":"impl Eq for LexicographicallyOrdered<isizex4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Eq for usizex4","synthetic":false,"types":["packed_simd::vSize::usizex4"]},{"text":"impl Eq for LexicographicallyOrdered<usizex4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Eq for msizex4","synthetic":false,"types":["packed_simd::vSize::msizex4"]},{"text":"impl Eq for LexicographicallyOrdered<msizex4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Eq for isizex8","synthetic":false,"types":["packed_simd::vSize::isizex8"]},{"text":"impl Eq for LexicographicallyOrdered<isizex8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Eq for usizex8","synthetic":false,"types":["packed_simd::vSize::usizex8"]},{"text":"impl Eq for LexicographicallyOrdered<usizex8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Eq for msizex8","synthetic":false,"types":["packed_simd::vSize::msizex8"]},{"text":"impl Eq for LexicographicallyOrdered<msizex8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl<T> Eq for cptrx2<T>","synthetic":false,"types":["packed_simd::vPtr::cptrx2"]},{"text":"impl<T> Eq for LexicographicallyOrdered<cptrx2<T>>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl<T> Eq for mptrx2<T>","synthetic":false,"types":["packed_simd::vPtr::mptrx2"]},{"text":"impl<T> Eq for LexicographicallyOrdered<mptrx2<T>>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl<T> Eq for cptrx4<T>","synthetic":false,"types":["packed_simd::vPtr::cptrx4"]},{"text":"impl<T> Eq for LexicographicallyOrdered<cptrx4<T>>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl<T> Eq for mptrx4<T>","synthetic":false,"types":["packed_simd::vPtr::mptrx4"]},{"text":"impl<T> Eq for LexicographicallyOrdered<mptrx4<T>>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl<T> Eq for cptrx8<T>","synthetic":false,"types":["packed_simd::vPtr::cptrx8"]},{"text":"impl<T> Eq for LexicographicallyOrdered<cptrx8<T>>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl<T> Eq for mptrx8<T>","synthetic":false,"types":["packed_simd::vPtr::mptrx8"]},{"text":"impl<T> Eq for LexicographicallyOrdered<mptrx8<T>>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]}]; +if (window.register_implementors) {window.register_implementors(implementors);} else {window.pending_implementors = implementors;}})() \ No newline at end of file diff --git a/implementors/core/cmp/trait.Ord.js b/implementors/core/cmp/trait.Ord.js new file mode 100644 index 000000000..a9adc6c26 --- /dev/null +++ b/implementors/core/cmp/trait.Ord.js @@ -0,0 +1,3 @@ +(function() {var implementors = {}; +implementors["packed_simd"] = [{"text":"impl Ord for m8","synthetic":false,"types":["packed_simd::masks::m8"]},{"text":"impl Ord for m16","synthetic":false,"types":["packed_simd::masks::m16"]},{"text":"impl Ord for m32","synthetic":false,"types":["packed_simd::masks::m32"]},{"text":"impl Ord for m64","synthetic":false,"types":["packed_simd::masks::m64"]},{"text":"impl Ord for m128","synthetic":false,"types":["packed_simd::masks::m128"]},{"text":"impl Ord for msize","synthetic":false,"types":["packed_simd::masks::msize"]},{"text":"impl Ord for LexicographicallyOrdered<i8x2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<u8x2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<m8x2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<i8x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<u8x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<m8x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<i16x2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<u16x2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<m16x2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<i8x8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<u8x8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<m8x8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<i16x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<u16x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<m16x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<i32x2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<u32x2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<m32x2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<i8x16>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<u8x16>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<m8x16>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<i16x8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<u16x8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<m16x8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<i32x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<u32x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<m32x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<i64x2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<u64x2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<m64x2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<i128x1>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<u128x1>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<m128x1>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<i8x32>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<u8x32>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<m8x32>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<i16x16>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<u16x16>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<m16x16>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<i32x8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<u32x8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<m32x8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<i64x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<u64x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<m64x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<i128x2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<u128x2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<m128x2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<i8x64>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<u8x64>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<m8x64>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<i16x32>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<u16x32>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<m16x32>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<i32x16>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<u32x16>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<m32x16>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<i64x8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<u64x8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<m64x8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<i128x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<u128x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<m128x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<isizex2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<usizex2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<msizex2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<isizex4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<usizex4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<msizex4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<isizex8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<usizex8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Ord for LexicographicallyOrdered<msizex8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]}]; +if (window.register_implementors) {window.register_implementors(implementors);} else {window.pending_implementors = implementors;}})() \ No newline at end of file diff --git a/implementors/core/cmp/trait.PartialEq.js b/implementors/core/cmp/trait.PartialEq.js new file mode 100644 index 000000000..1452c32f3 --- /dev/null +++ b/implementors/core/cmp/trait.PartialEq.js @@ -0,0 +1,3 @@ +(function() {var implementors = {}; +implementors["packed_simd"] = [{"text":"impl PartialEq<m8> for m8","synthetic":false,"types":["packed_simd::masks::m8"]},{"text":"impl PartialEq<m16> for m16","synthetic":false,"types":["packed_simd::masks::m16"]},{"text":"impl PartialEq<m32> for m32","synthetic":false,"types":["packed_simd::masks::m32"]},{"text":"impl PartialEq<m64> for m64","synthetic":false,"types":["packed_simd::masks::m64"]},{"text":"impl PartialEq<m128> for m128","synthetic":false,"types":["packed_simd::masks::m128"]},{"text":"impl PartialEq<msize> for msize","synthetic":false,"types":["packed_simd::masks::msize"]},{"text":"impl PartialEq<Simd<[i8; 2]>> for i8x2","synthetic":false,"types":["packed_simd::v16::i8x2"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[i8; 2]>>> for LexicographicallyOrdered<i8x2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[u8; 2]>> for u8x2","synthetic":false,"types":["packed_simd::v16::u8x2"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[u8; 2]>>> for LexicographicallyOrdered<u8x2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[m8; 2]>> for m8x2","synthetic":false,"types":["packed_simd::v16::m8x2"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[m8; 2]>>> for LexicographicallyOrdered<m8x2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[i8; 4]>> for i8x4","synthetic":false,"types":["packed_simd::v32::i8x4"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[i8; 4]>>> for LexicographicallyOrdered<i8x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[u8; 4]>> for u8x4","synthetic":false,"types":["packed_simd::v32::u8x4"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[u8; 4]>>> for LexicographicallyOrdered<u8x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[m8; 4]>> for m8x4","synthetic":false,"types":["packed_simd::v32::m8x4"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[m8; 4]>>> for LexicographicallyOrdered<m8x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[i16; 2]>> for i16x2","synthetic":false,"types":["packed_simd::v32::i16x2"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[i16; 2]>>> for LexicographicallyOrdered<i16x2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[u16; 2]>> for u16x2","synthetic":false,"types":["packed_simd::v32::u16x2"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[u16; 2]>>> for LexicographicallyOrdered<u16x2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[m16; 2]>> for m16x2","synthetic":false,"types":["packed_simd::v32::m16x2"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[m16; 2]>>> for LexicographicallyOrdered<m16x2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[i8; 8]>> for i8x8","synthetic":false,"types":["packed_simd::v64::i8x8"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[i8; 8]>>> for LexicographicallyOrdered<i8x8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[u8; 8]>> for u8x8","synthetic":false,"types":["packed_simd::v64::u8x8"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[u8; 8]>>> for LexicographicallyOrdered<u8x8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[m8; 8]>> for m8x8","synthetic":false,"types":["packed_simd::v64::m8x8"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[m8; 8]>>> for LexicographicallyOrdered<m8x8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[i16; 4]>> for i16x4","synthetic":false,"types":["packed_simd::v64::i16x4"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[i16; 4]>>> for LexicographicallyOrdered<i16x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[u16; 4]>> for u16x4","synthetic":false,"types":["packed_simd::v64::u16x4"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[u16; 4]>>> for LexicographicallyOrdered<u16x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[m16; 4]>> for m16x4","synthetic":false,"types":["packed_simd::v64::m16x4"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[m16; 4]>>> for LexicographicallyOrdered<m16x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[i32; 2]>> for i32x2","synthetic":false,"types":["packed_simd::v64::i32x2"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[i32; 2]>>> for LexicographicallyOrdered<i32x2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[u32; 2]>> for u32x2","synthetic":false,"types":["packed_simd::v64::u32x2"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[u32; 2]>>> for LexicographicallyOrdered<u32x2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[m32; 2]>> for m32x2","synthetic":false,"types":["packed_simd::v64::m32x2"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[m32; 2]>>> for LexicographicallyOrdered<m32x2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[f32; 2]>> for f32x2","synthetic":false,"types":["packed_simd::v64::f32x2"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[f32; 2]>>> for LexicographicallyOrdered<f32x2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[i8; 16]>> for i8x16","synthetic":false,"types":["packed_simd::v128::i8x16"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[i8; 16]>>> for LexicographicallyOrdered<i8x16>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[u8; 16]>> for u8x16","synthetic":false,"types":["packed_simd::v128::u8x16"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[u8; 16]>>> for LexicographicallyOrdered<u8x16>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[m8; 16]>> for m8x16","synthetic":false,"types":["packed_simd::v128::m8x16"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[m8; 16]>>> for LexicographicallyOrdered<m8x16>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[i16; 8]>> for i16x8","synthetic":false,"types":["packed_simd::v128::i16x8"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[i16; 8]>>> for LexicographicallyOrdered<i16x8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[u16; 8]>> for u16x8","synthetic":false,"types":["packed_simd::v128::u16x8"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[u16; 8]>>> for LexicographicallyOrdered<u16x8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[m16; 8]>> for m16x8","synthetic":false,"types":["packed_simd::v128::m16x8"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[m16; 8]>>> for LexicographicallyOrdered<m16x8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[i32; 4]>> for i32x4","synthetic":false,"types":["packed_simd::v128::i32x4"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[i32; 4]>>> for LexicographicallyOrdered<i32x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[u32; 4]>> for u32x4","synthetic":false,"types":["packed_simd::v128::u32x4"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[u32; 4]>>> for LexicographicallyOrdered<u32x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[f32; 4]>> for f32x4","synthetic":false,"types":["packed_simd::v128::f32x4"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[f32; 4]>>> for LexicographicallyOrdered<f32x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[m32; 4]>> for m32x4","synthetic":false,"types":["packed_simd::v128::m32x4"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[m32; 4]>>> for LexicographicallyOrdered<m32x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[i64; 2]>> for i64x2","synthetic":false,"types":["packed_simd::v128::i64x2"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[i64; 2]>>> for LexicographicallyOrdered<i64x2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[u64; 2]>> for u64x2","synthetic":false,"types":["packed_simd::v128::u64x2"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[u64; 2]>>> for LexicographicallyOrdered<u64x2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[f64; 2]>> for f64x2","synthetic":false,"types":["packed_simd::v128::f64x2"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[f64; 2]>>> for LexicographicallyOrdered<f64x2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[m64; 2]>> for m64x2","synthetic":false,"types":["packed_simd::v128::m64x2"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[m64; 2]>>> for LexicographicallyOrdered<m64x2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[i128; 1]>> for i128x1","synthetic":false,"types":["packed_simd::v128::i128x1"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[i128; 1]>>> for LexicographicallyOrdered<i128x1>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[u128; 1]>> for u128x1","synthetic":false,"types":["packed_simd::v128::u128x1"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[u128; 1]>>> for LexicographicallyOrdered<u128x1>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[m128; 1]>> for m128x1","synthetic":false,"types":["packed_simd::v128::m128x1"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[m128; 1]>>> for LexicographicallyOrdered<m128x1>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[i8; 32]>> for i8x32","synthetic":false,"types":["packed_simd::v256::i8x32"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[i8; 32]>>> for LexicographicallyOrdered<i8x32>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[u8; 32]>> for u8x32","synthetic":false,"types":["packed_simd::v256::u8x32"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[u8; 32]>>> for LexicographicallyOrdered<u8x32>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[m8; 32]>> for m8x32","synthetic":false,"types":["packed_simd::v256::m8x32"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[m8; 32]>>> for LexicographicallyOrdered<m8x32>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[i16; 16]>> for i16x16","synthetic":false,"types":["packed_simd::v256::i16x16"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[i16; 16]>>> for LexicographicallyOrdered<i16x16>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[u16; 16]>> for u16x16","synthetic":false,"types":["packed_simd::v256::u16x16"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[u16; 16]>>> for LexicographicallyOrdered<u16x16>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[m16; 16]>> for m16x16","synthetic":false,"types":["packed_simd::v256::m16x16"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[m16; 16]>>> for LexicographicallyOrdered<m16x16>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[i32; 8]>> for i32x8","synthetic":false,"types":["packed_simd::v256::i32x8"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[i32; 8]>>> for LexicographicallyOrdered<i32x8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[u32; 8]>> for u32x8","synthetic":false,"types":["packed_simd::v256::u32x8"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[u32; 8]>>> for LexicographicallyOrdered<u32x8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[f32; 8]>> for f32x8","synthetic":false,"types":["packed_simd::v256::f32x8"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[f32; 8]>>> for LexicographicallyOrdered<f32x8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[m32; 8]>> for m32x8","synthetic":false,"types":["packed_simd::v256::m32x8"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[m32; 8]>>> for LexicographicallyOrdered<m32x8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[i64; 4]>> for i64x4","synthetic":false,"types":["packed_simd::v256::i64x4"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[i64; 4]>>> for LexicographicallyOrdered<i64x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[u64; 4]>> for u64x4","synthetic":false,"types":["packed_simd::v256::u64x4"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[u64; 4]>>> for LexicographicallyOrdered<u64x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[f64; 4]>> for f64x4","synthetic":false,"types":["packed_simd::v256::f64x4"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[f64; 4]>>> for LexicographicallyOrdered<f64x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[m64; 4]>> for m64x4","synthetic":false,"types":["packed_simd::v256::m64x4"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[m64; 4]>>> for LexicographicallyOrdered<m64x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[i128; 2]>> for i128x2","synthetic":false,"types":["packed_simd::v256::i128x2"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[i128; 2]>>> for LexicographicallyOrdered<i128x2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[u128; 2]>> for u128x2","synthetic":false,"types":["packed_simd::v256::u128x2"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[u128; 2]>>> for LexicographicallyOrdered<u128x2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[m128; 2]>> for m128x2","synthetic":false,"types":["packed_simd::v256::m128x2"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[m128; 2]>>> for LexicographicallyOrdered<m128x2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[i8; 64]>> for i8x64","synthetic":false,"types":["packed_simd::v512::i8x64"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[i8; 64]>>> for LexicographicallyOrdered<i8x64>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[u8; 64]>> for u8x64","synthetic":false,"types":["packed_simd::v512::u8x64"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[u8; 64]>>> for LexicographicallyOrdered<u8x64>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[m8; 64]>> for m8x64","synthetic":false,"types":["packed_simd::v512::m8x64"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[m8; 64]>>> for LexicographicallyOrdered<m8x64>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[i16; 32]>> for i16x32","synthetic":false,"types":["packed_simd::v512::i16x32"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[i16; 32]>>> for LexicographicallyOrdered<i16x32>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[u16; 32]>> for u16x32","synthetic":false,"types":["packed_simd::v512::u16x32"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[u16; 32]>>> for LexicographicallyOrdered<u16x32>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[m16; 32]>> for m16x32","synthetic":false,"types":["packed_simd::v512::m16x32"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[m16; 32]>>> for LexicographicallyOrdered<m16x32>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[i32; 16]>> for i32x16","synthetic":false,"types":["packed_simd::v512::i32x16"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[i32; 16]>>> for LexicographicallyOrdered<i32x16>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[u32; 16]>> for u32x16","synthetic":false,"types":["packed_simd::v512::u32x16"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[u32; 16]>>> for LexicographicallyOrdered<u32x16>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[f32; 16]>> for f32x16","synthetic":false,"types":["packed_simd::v512::f32x16"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[f32; 16]>>> for LexicographicallyOrdered<f32x16>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[m32; 16]>> for m32x16","synthetic":false,"types":["packed_simd::v512::m32x16"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[m32; 16]>>> for LexicographicallyOrdered<m32x16>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[i64; 8]>> for i64x8","synthetic":false,"types":["packed_simd::v512::i64x8"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[i64; 8]>>> for LexicographicallyOrdered<i64x8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[u64; 8]>> for u64x8","synthetic":false,"types":["packed_simd::v512::u64x8"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[u64; 8]>>> for LexicographicallyOrdered<u64x8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[f64; 8]>> for f64x8","synthetic":false,"types":["packed_simd::v512::f64x8"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[f64; 8]>>> for LexicographicallyOrdered<f64x8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[m64; 8]>> for m64x8","synthetic":false,"types":["packed_simd::v512::m64x8"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[m64; 8]>>> for LexicographicallyOrdered<m64x8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[i128; 4]>> for i128x4","synthetic":false,"types":["packed_simd::v512::i128x4"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[i128; 4]>>> for LexicographicallyOrdered<i128x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[u128; 4]>> for u128x4","synthetic":false,"types":["packed_simd::v512::u128x4"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[u128; 4]>>> for LexicographicallyOrdered<u128x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[m128; 4]>> for m128x4","synthetic":false,"types":["packed_simd::v512::m128x4"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[m128; 4]>>> for LexicographicallyOrdered<m128x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[isize; 2]>> for isizex2","synthetic":false,"types":["packed_simd::vSize::isizex2"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[isize; 2]>>> for LexicographicallyOrdered<isizex2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[usize; 2]>> for usizex2","synthetic":false,"types":["packed_simd::vSize::usizex2"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[usize; 2]>>> for LexicographicallyOrdered<usizex2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[msize; 2]>> for msizex2","synthetic":false,"types":["packed_simd::vSize::msizex2"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[msize; 2]>>> for LexicographicallyOrdered<msizex2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[isize; 4]>> for isizex4","synthetic":false,"types":["packed_simd::vSize::isizex4"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[isize; 4]>>> for LexicographicallyOrdered<isizex4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[usize; 4]>> for usizex4","synthetic":false,"types":["packed_simd::vSize::usizex4"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[usize; 4]>>> for LexicographicallyOrdered<usizex4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[msize; 4]>> for msizex4","synthetic":false,"types":["packed_simd::vSize::msizex4"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[msize; 4]>>> for LexicographicallyOrdered<msizex4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[isize; 8]>> for isizex8","synthetic":false,"types":["packed_simd::vSize::isizex8"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[isize; 8]>>> for LexicographicallyOrdered<isizex8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[usize; 8]>> for usizex8","synthetic":false,"types":["packed_simd::vSize::usizex8"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[usize; 8]>>> for LexicographicallyOrdered<usizex8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialEq<Simd<[msize; 8]>> for msizex8","synthetic":false,"types":["packed_simd::vSize::msizex8"]},{"text":"impl PartialEq<LexicographicallyOrdered<Simd<[msize; 8]>>> for LexicographicallyOrdered<msizex8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl<T> PartialEq<Simd<[*const T; 2]>> for cptrx2<T>","synthetic":false,"types":["packed_simd::vPtr::cptrx2"]},{"text":"impl<T> PartialEq<LexicographicallyOrdered<Simd<[*const T; 2]>>> for LexicographicallyOrdered<cptrx2<T>>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl<T> PartialEq<Simd<[*mut T; 2]>> for mptrx2<T>","synthetic":false,"types":["packed_simd::vPtr::mptrx2"]},{"text":"impl<T> PartialEq<LexicographicallyOrdered<Simd<[*mut T; 2]>>> for LexicographicallyOrdered<mptrx2<T>>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl<T> PartialEq<Simd<[*const T; 4]>> for cptrx4<T>","synthetic":false,"types":["packed_simd::vPtr::cptrx4"]},{"text":"impl<T> PartialEq<LexicographicallyOrdered<Simd<[*const T; 4]>>> for LexicographicallyOrdered<cptrx4<T>>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl<T> PartialEq<Simd<[*mut T; 4]>> for mptrx4<T>","synthetic":false,"types":["packed_simd::vPtr::mptrx4"]},{"text":"impl<T> PartialEq<LexicographicallyOrdered<Simd<[*mut T; 4]>>> for LexicographicallyOrdered<mptrx4<T>>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl<T> PartialEq<Simd<[*const T; 8]>> for cptrx8<T>","synthetic":false,"types":["packed_simd::vPtr::cptrx8"]},{"text":"impl<T> PartialEq<LexicographicallyOrdered<Simd<[*const T; 8]>>> for LexicographicallyOrdered<cptrx8<T>>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl<T> PartialEq<Simd<[*mut T; 8]>> for mptrx8<T>","synthetic":false,"types":["packed_simd::vPtr::mptrx8"]},{"text":"impl<T> PartialEq<LexicographicallyOrdered<Simd<[*mut T; 8]>>> for LexicographicallyOrdered<mptrx8<T>>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]}]; +if (window.register_implementors) {window.register_implementors(implementors);} else {window.pending_implementors = implementors;}})() \ No newline at end of file diff --git a/implementors/core/cmp/trait.PartialOrd.js b/implementors/core/cmp/trait.PartialOrd.js new file mode 100644 index 000000000..9ca955116 --- /dev/null +++ b/implementors/core/cmp/trait.PartialOrd.js @@ -0,0 +1,3 @@ +(function() {var implementors = {}; +implementors["packed_simd"] = [{"text":"impl PartialOrd<m8> for m8","synthetic":false,"types":["packed_simd::masks::m8"]},{"text":"impl PartialOrd<m16> for m16","synthetic":false,"types":["packed_simd::masks::m16"]},{"text":"impl PartialOrd<m32> for m32","synthetic":false,"types":["packed_simd::masks::m32"]},{"text":"impl PartialOrd<m64> for m64","synthetic":false,"types":["packed_simd::masks::m64"]},{"text":"impl PartialOrd<m128> for m128","synthetic":false,"types":["packed_simd::masks::m128"]},{"text":"impl PartialOrd<msize> for msize","synthetic":false,"types":["packed_simd::masks::msize"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[i8; 2]>>> for LexicographicallyOrdered<i8x2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[u8; 2]>>> for LexicographicallyOrdered<u8x2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[m8; 2]>>> for LexicographicallyOrdered<m8x2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[i8; 4]>>> for LexicographicallyOrdered<i8x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[u8; 4]>>> for LexicographicallyOrdered<u8x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[m8; 4]>>> for LexicographicallyOrdered<m8x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[i16; 2]>>> for LexicographicallyOrdered<i16x2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[u16; 2]>>> for LexicographicallyOrdered<u16x2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[m16; 2]>>> for LexicographicallyOrdered<m16x2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[i8; 8]>>> for LexicographicallyOrdered<i8x8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[u8; 8]>>> for LexicographicallyOrdered<u8x8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[m8; 8]>>> for LexicographicallyOrdered<m8x8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[i16; 4]>>> for LexicographicallyOrdered<i16x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[u16; 4]>>> for LexicographicallyOrdered<u16x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[m16; 4]>>> for LexicographicallyOrdered<m16x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[i32; 2]>>> for LexicographicallyOrdered<i32x2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[u32; 2]>>> for LexicographicallyOrdered<u32x2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[m32; 2]>>> for LexicographicallyOrdered<m32x2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[i8; 16]>>> for LexicographicallyOrdered<i8x16>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[u8; 16]>>> for LexicographicallyOrdered<u8x16>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[m8; 16]>>> for LexicographicallyOrdered<m8x16>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[i16; 8]>>> for LexicographicallyOrdered<i16x8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[u16; 8]>>> for LexicographicallyOrdered<u16x8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[m16; 8]>>> for LexicographicallyOrdered<m16x8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[i32; 4]>>> for LexicographicallyOrdered<i32x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[u32; 4]>>> for LexicographicallyOrdered<u32x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[m32; 4]>>> for LexicographicallyOrdered<m32x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[i64; 2]>>> for LexicographicallyOrdered<i64x2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[u64; 2]>>> for LexicographicallyOrdered<u64x2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[m64; 2]>>> for LexicographicallyOrdered<m64x2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[i128; 1]>>> for LexicographicallyOrdered<i128x1>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[u128; 1]>>> for LexicographicallyOrdered<u128x1>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[m128; 1]>>> for LexicographicallyOrdered<m128x1>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[i8; 32]>>> for LexicographicallyOrdered<i8x32>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[u8; 32]>>> for LexicographicallyOrdered<u8x32>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[m8; 32]>>> for LexicographicallyOrdered<m8x32>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[i16; 16]>>> for LexicographicallyOrdered<i16x16>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[u16; 16]>>> for LexicographicallyOrdered<u16x16>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[m16; 16]>>> for LexicographicallyOrdered<m16x16>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[i32; 8]>>> for LexicographicallyOrdered<i32x8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[u32; 8]>>> for LexicographicallyOrdered<u32x8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[m32; 8]>>> for LexicographicallyOrdered<m32x8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[i64; 4]>>> for LexicographicallyOrdered<i64x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[u64; 4]>>> for LexicographicallyOrdered<u64x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[m64; 4]>>> for LexicographicallyOrdered<m64x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[i128; 2]>>> for LexicographicallyOrdered<i128x2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[u128; 2]>>> for LexicographicallyOrdered<u128x2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[m128; 2]>>> for LexicographicallyOrdered<m128x2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[i8; 64]>>> for LexicographicallyOrdered<i8x64>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[u8; 64]>>> for LexicographicallyOrdered<u8x64>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[m8; 64]>>> for LexicographicallyOrdered<m8x64>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[i16; 32]>>> for LexicographicallyOrdered<i16x32>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[u16; 32]>>> for LexicographicallyOrdered<u16x32>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[m16; 32]>>> for LexicographicallyOrdered<m16x32>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[i32; 16]>>> for LexicographicallyOrdered<i32x16>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[u32; 16]>>> for LexicographicallyOrdered<u32x16>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[m32; 16]>>> for LexicographicallyOrdered<m32x16>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[i64; 8]>>> for LexicographicallyOrdered<i64x8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[u64; 8]>>> for LexicographicallyOrdered<u64x8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[m64; 8]>>> for LexicographicallyOrdered<m64x8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[i128; 4]>>> for LexicographicallyOrdered<i128x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[u128; 4]>>> for LexicographicallyOrdered<u128x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[m128; 4]>>> for LexicographicallyOrdered<m128x4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[isize; 2]>>> for LexicographicallyOrdered<isizex2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[usize; 2]>>> for LexicographicallyOrdered<usizex2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[msize; 2]>>> for LexicographicallyOrdered<msizex2>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[isize; 4]>>> for LexicographicallyOrdered<isizex4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[usize; 4]>>> for LexicographicallyOrdered<usizex4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[msize; 4]>>> for LexicographicallyOrdered<msizex4>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[isize; 8]>>> for LexicographicallyOrdered<isizex8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[usize; 8]>>> for LexicographicallyOrdered<usizex8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl PartialOrd<LexicographicallyOrdered<Simd<[msize; 8]>>> for LexicographicallyOrdered<msizex8>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]}]; +if (window.register_implementors) {window.register_implementors(implementors);} else {window.pending_implementors = implementors;}})() \ No newline at end of file diff --git a/implementors/core/convert/trait.From.js b/implementors/core/convert/trait.From.js new file mode 100644 index 000000000..b6448f4a1 --- /dev/null +++ b/implementors/core/convert/trait.From.js @@ -0,0 +1,3 @@ +(function() {var implementors = {}; +implementors["packed_simd"] = [{"text":"impl From<[i8; 2]> for i8x2","synthetic":false,"types":["packed_simd::v16::i8x2"]},{"text":"impl From<Simd<[i8; 2]>> for [i8; 2]","synthetic":false,"types":[]},{"text":"impl From<[u8; 2]> for u8x2","synthetic":false,"types":["packed_simd::v16::u8x2"]},{"text":"impl From<Simd<[u8; 2]>> for [u8; 2]","synthetic":false,"types":[]},{"text":"impl From<[m8; 2]> for m8x2","synthetic":false,"types":["packed_simd::v16::m8x2"]},{"text":"impl From<Simd<[m8; 2]>> for [m8; 2]","synthetic":false,"types":["packed_simd::masks::m8"]},{"text":"impl From<Simd<[m16; 2]>> for m8x2","synthetic":false,"types":["packed_simd::v16::m8x2"]},{"text":"impl From<Simd<[m32; 2]>> for m8x2","synthetic":false,"types":["packed_simd::v16::m8x2"]},{"text":"impl From<Simd<[m64; 2]>> for m8x2","synthetic":false,"types":["packed_simd::v16::m8x2"]},{"text":"impl From<Simd<[m128; 2]>> for m8x2","synthetic":false,"types":["packed_simd::v16::m8x2"]},{"text":"impl From<[i8; 4]> for i8x4","synthetic":false,"types":["packed_simd::v32::i8x4"]},{"text":"impl From<Simd<[i8; 4]>> for [i8; 4]","synthetic":false,"types":[]},{"text":"impl From<[u8; 4]> for u8x4","synthetic":false,"types":["packed_simd::v32::u8x4"]},{"text":"impl From<Simd<[u8; 4]>> for [u8; 4]","synthetic":false,"types":[]},{"text":"impl From<[m8; 4]> for m8x4","synthetic":false,"types":["packed_simd::v32::m8x4"]},{"text":"impl From<Simd<[m8; 4]>> for [m8; 4]","synthetic":false,"types":["packed_simd::masks::m8"]},{"text":"impl From<Simd<[m16; 4]>> for m8x4","synthetic":false,"types":["packed_simd::v32::m8x4"]},{"text":"impl From<Simd<[m32; 4]>> for m8x4","synthetic":false,"types":["packed_simd::v32::m8x4"]},{"text":"impl From<Simd<[m64; 4]>> for m8x4","synthetic":false,"types":["packed_simd::v32::m8x4"]},{"text":"impl From<[i16; 2]> for i16x2","synthetic":false,"types":["packed_simd::v32::i16x2"]},{"text":"impl From<Simd<[i16; 2]>> for [i16; 2]","synthetic":false,"types":[]},{"text":"impl From<Simd<[i8; 2]>> for i16x2","synthetic":false,"types":["packed_simd::v32::i16x2"]},{"text":"impl From<Simd<[u8; 2]>> for i16x2","synthetic":false,"types":["packed_simd::v32::i16x2"]},{"text":"impl From<[u16; 2]> for u16x2","synthetic":false,"types":["packed_simd::v32::u16x2"]},{"text":"impl From<Simd<[u16; 2]>> for [u16; 2]","synthetic":false,"types":[]},{"text":"impl From<Simd<[u8; 2]>> for u16x2","synthetic":false,"types":["packed_simd::v32::u16x2"]},{"text":"impl From<[m16; 2]> for m16x2","synthetic":false,"types":["packed_simd::v32::m16x2"]},{"text":"impl From<Simd<[m16; 2]>> for [m16; 2]","synthetic":false,"types":["packed_simd::masks::m16"]},{"text":"impl From<Simd<[m8; 2]>> for m16x2","synthetic":false,"types":["packed_simd::v32::m16x2"]},{"text":"impl From<Simd<[m32; 2]>> for m16x2","synthetic":false,"types":["packed_simd::v32::m16x2"]},{"text":"impl From<Simd<[m64; 2]>> for m16x2","synthetic":false,"types":["packed_simd::v32::m16x2"]},{"text":"impl From<Simd<[m128; 2]>> for m16x2","synthetic":false,"types":["packed_simd::v32::m16x2"]},{"text":"impl From<[i8; 8]> for i8x8","synthetic":false,"types":["packed_simd::v64::i8x8"]},{"text":"impl From<Simd<[i8; 8]>> for [i8; 8]","synthetic":false,"types":[]},{"text":"impl From<[u8; 8]> for u8x8","synthetic":false,"types":["packed_simd::v64::u8x8"]},{"text":"impl From<Simd<[u8; 8]>> for [u8; 8]","synthetic":false,"types":[]},{"text":"impl From<[m8; 8]> for m8x8","synthetic":false,"types":["packed_simd::v64::m8x8"]},{"text":"impl From<Simd<[m8; 8]>> for [m8; 8]","synthetic":false,"types":["packed_simd::masks::m8"]},{"text":"impl From<Simd<[m16; 8]>> for m8x8","synthetic":false,"types":["packed_simd::v64::m8x8"]},{"text":"impl From<Simd<[m32; 8]>> for m8x8","synthetic":false,"types":["packed_simd::v64::m8x8"]},{"text":"impl From<[i16; 4]> for i16x4","synthetic":false,"types":["packed_simd::v64::i16x4"]},{"text":"impl From<Simd<[i16; 4]>> for [i16; 4]","synthetic":false,"types":[]},{"text":"impl From<Simd<[i8; 4]>> for i16x4","synthetic":false,"types":["packed_simd::v64::i16x4"]},{"text":"impl From<Simd<[u8; 4]>> for i16x4","synthetic":false,"types":["packed_simd::v64::i16x4"]},{"text":"impl From<[u16; 4]> for u16x4","synthetic":false,"types":["packed_simd::v64::u16x4"]},{"text":"impl From<Simd<[u16; 4]>> for [u16; 4]","synthetic":false,"types":[]},{"text":"impl From<Simd<[u8; 4]>> for u16x4","synthetic":false,"types":["packed_simd::v64::u16x4"]},{"text":"impl From<[m16; 4]> for m16x4","synthetic":false,"types":["packed_simd::v64::m16x4"]},{"text":"impl From<Simd<[m16; 4]>> for [m16; 4]","synthetic":false,"types":["packed_simd::masks::m16"]},{"text":"impl From<Simd<[m8; 4]>> for m16x4","synthetic":false,"types":["packed_simd::v64::m16x4"]},{"text":"impl From<Simd<[m32; 4]>> for m16x4","synthetic":false,"types":["packed_simd::v64::m16x4"]},{"text":"impl From<Simd<[m64; 4]>> for m16x4","synthetic":false,"types":["packed_simd::v64::m16x4"]},{"text":"impl From<[i32; 2]> for i32x2","synthetic":false,"types":["packed_simd::v64::i32x2"]},{"text":"impl From<Simd<[i32; 2]>> for [i32; 2]","synthetic":false,"types":[]},{"text":"impl From<Simd<[i8; 2]>> for i32x2","synthetic":false,"types":["packed_simd::v64::i32x2"]},{"text":"impl From<Simd<[u8; 2]>> for i32x2","synthetic":false,"types":["packed_simd::v64::i32x2"]},{"text":"impl From<Simd<[i16; 2]>> for i32x2","synthetic":false,"types":["packed_simd::v64::i32x2"]},{"text":"impl From<Simd<[u16; 2]>> for i32x2","synthetic":false,"types":["packed_simd::v64::i32x2"]},{"text":"impl From<[u32; 2]> for u32x2","synthetic":false,"types":["packed_simd::v64::u32x2"]},{"text":"impl From<Simd<[u32; 2]>> for [u32; 2]","synthetic":false,"types":[]},{"text":"impl From<Simd<[u8; 2]>> for u32x2","synthetic":false,"types":["packed_simd::v64::u32x2"]},{"text":"impl From<Simd<[u16; 2]>> for u32x2","synthetic":false,"types":["packed_simd::v64::u32x2"]},{"text":"impl From<[m32; 2]> for m32x2","synthetic":false,"types":["packed_simd::v64::m32x2"]},{"text":"impl From<Simd<[m32; 2]>> for [m32; 2]","synthetic":false,"types":["packed_simd::masks::m32"]},{"text":"impl From<Simd<[m8; 2]>> for m32x2","synthetic":false,"types":["packed_simd::v64::m32x2"]},{"text":"impl From<Simd<[m16; 2]>> for m32x2","synthetic":false,"types":["packed_simd::v64::m32x2"]},{"text":"impl From<Simd<[m64; 2]>> for m32x2","synthetic":false,"types":["packed_simd::v64::m32x2"]},{"text":"impl From<Simd<[m128; 2]>> for m32x2","synthetic":false,"types":["packed_simd::v64::m32x2"]},{"text":"impl From<[f32; 2]> for f32x2","synthetic":false,"types":["packed_simd::v64::f32x2"]},{"text":"impl From<Simd<[f32; 2]>> for [f32; 2]","synthetic":false,"types":[]},{"text":"impl From<Simd<[i8; 2]>> for f32x2","synthetic":false,"types":["packed_simd::v64::f32x2"]},{"text":"impl From<Simd<[u8; 2]>> for f32x2","synthetic":false,"types":["packed_simd::v64::f32x2"]},{"text":"impl From<Simd<[i16; 2]>> for f32x2","synthetic":false,"types":["packed_simd::v64::f32x2"]},{"text":"impl From<Simd<[u16; 2]>> for f32x2","synthetic":false,"types":["packed_simd::v64::f32x2"]},{"text":"impl From<[i8; 16]> for i8x16","synthetic":false,"types":["packed_simd::v128::i8x16"]},{"text":"impl From<Simd<[i8; 16]>> for [i8; 16]","synthetic":false,"types":[]},{"text":"impl From<[u8; 16]> for u8x16","synthetic":false,"types":["packed_simd::v128::u8x16"]},{"text":"impl From<Simd<[u8; 16]>> for [u8; 16]","synthetic":false,"types":[]},{"text":"impl From<[m8; 16]> for m8x16","synthetic":false,"types":["packed_simd::v128::m8x16"]},{"text":"impl From<Simd<[m8; 16]>> for [m8; 16]","synthetic":false,"types":["packed_simd::masks::m8"]},{"text":"impl From<Simd<[m16; 16]>> for m8x16","synthetic":false,"types":["packed_simd::v128::m8x16"]},{"text":"impl From<[i16; 8]> for i16x8","synthetic":false,"types":["packed_simd::v128::i16x8"]},{"text":"impl From<Simd<[i16; 8]>> for [i16; 8]","synthetic":false,"types":[]},{"text":"impl From<Simd<[i8; 8]>> for i16x8","synthetic":false,"types":["packed_simd::v128::i16x8"]},{"text":"impl From<Simd<[u8; 8]>> for i16x8","synthetic":false,"types":["packed_simd::v128::i16x8"]},{"text":"impl From<[u16; 8]> for u16x8","synthetic":false,"types":["packed_simd::v128::u16x8"]},{"text":"impl From<Simd<[u16; 8]>> for [u16; 8]","synthetic":false,"types":[]},{"text":"impl From<Simd<[u8; 8]>> for u16x8","synthetic":false,"types":["packed_simd::v128::u16x8"]},{"text":"impl From<[m16; 8]> for m16x8","synthetic":false,"types":["packed_simd::v128::m16x8"]},{"text":"impl From<Simd<[m16; 8]>> for [m16; 8]","synthetic":false,"types":["packed_simd::masks::m16"]},{"text":"impl From<Simd<[m8; 8]>> for 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T; 4]> for mptrx4<T>","synthetic":false,"types":["packed_simd::vPtr::mptrx4"]},{"text":"impl<T> From<[*const T; 8]> for cptrx8<T>","synthetic":false,"types":["packed_simd::vPtr::cptrx8"]},{"text":"impl<T> From<[*mut T; 8]> for mptrx8<T>","synthetic":false,"types":["packed_simd::vPtr::mptrx8"]}]; +if (window.register_implementors) {window.register_implementors(implementors);} else {window.pending_implementors = implementors;}})() \ No newline at end of file diff --git a/implementors/core/convert/trait.Into.js b/implementors/core/convert/trait.Into.js new file mode 100644 index 000000000..542ac8344 --- /dev/null +++ b/implementors/core/convert/trait.Into.js @@ -0,0 +1,3 @@ +(function() {var implementors = {}; +implementors["packed_simd"] = [{"text":"impl<T> Into<[*const T; 2]> for cptrx2<T>","synthetic":false,"types":["packed_simd::vPtr::cptrx2"]},{"text":"impl<T> Into<[*mut T; 2]> for mptrx2<T>","synthetic":false,"types":["packed_simd::vPtr::mptrx2"]},{"text":"impl<T> Into<[*const T; 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m16","synthetic":false,"types":["packed_simd::masks::m16"]},{"text":"impl Default for m32","synthetic":false,"types":["packed_simd::masks::m32"]},{"text":"impl Default for m64","synthetic":false,"types":["packed_simd::masks::m64"]},{"text":"impl Default for m128","synthetic":false,"types":["packed_simd::masks::m128"]},{"text":"impl Default for msize","synthetic":false,"types":["packed_simd::masks::msize"]},{"text":"impl Default for i8x2","synthetic":false,"types":["packed_simd::v16::i8x2"]},{"text":"impl Default for u8x2","synthetic":false,"types":["packed_simd::v16::u8x2"]},{"text":"impl Default for m8x2","synthetic":false,"types":["packed_simd::v16::m8x2"]},{"text":"impl Default for i8x4","synthetic":false,"types":["packed_simd::v32::i8x4"]},{"text":"impl Default for u8x4","synthetic":false,"types":["packed_simd::v32::u8x4"]},{"text":"impl Default for m8x4","synthetic":false,"types":["packed_simd::v32::m8x4"]},{"text":"impl Default for i16x2","synthetic":false,"types":["packed_simd::v32::i16x2"]},{"text":"impl Default for u16x2","synthetic":false,"types":["packed_simd::v32::u16x2"]},{"text":"impl Default for m16x2","synthetic":false,"types":["packed_simd::v32::m16x2"]},{"text":"impl Default for i8x8","synthetic":false,"types":["packed_simd::v64::i8x8"]},{"text":"impl Default for u8x8","synthetic":false,"types":["packed_simd::v64::u8x8"]},{"text":"impl Default for m8x8","synthetic":false,"types":["packed_simd::v64::m8x8"]},{"text":"impl Default for i16x4","synthetic":false,"types":["packed_simd::v64::i16x4"]},{"text":"impl Default for u16x4","synthetic":false,"types":["packed_simd::v64::u16x4"]},{"text":"impl Default for m16x4","synthetic":false,"types":["packed_simd::v64::m16x4"]},{"text":"impl Default for i32x2","synthetic":false,"types":["packed_simd::v64::i32x2"]},{"text":"impl Default for u32x2","synthetic":false,"types":["packed_simd::v64::u32x2"]},{"text":"impl Default for m32x2","synthetic":false,"types":["packed_simd::v64::m32x2"]},{"text":"impl Default for f32x2","synthetic":false,"types":["packed_simd::v64::f32x2"]},{"text":"impl Default for i8x16","synthetic":false,"types":["packed_simd::v128::i8x16"]},{"text":"impl Default for u8x16","synthetic":false,"types":["packed_simd::v128::u8x16"]},{"text":"impl Default for m8x16","synthetic":false,"types":["packed_simd::v128::m8x16"]},{"text":"impl Default for i16x8","synthetic":false,"types":["packed_simd::v128::i16x8"]},{"text":"impl Default for u16x8","synthetic":false,"types":["packed_simd::v128::u16x8"]},{"text":"impl Default for m16x8","synthetic":false,"types":["packed_simd::v128::m16x8"]},{"text":"impl Default for i32x4","synthetic":false,"types":["packed_simd::v128::i32x4"]},{"text":"impl Default for u32x4","synthetic":false,"types":["packed_simd::v128::u32x4"]},{"text":"impl Default for f32x4","synthetic":false,"types":["packed_simd::v128::f32x4"]},{"text":"impl Default for m32x4","synthetic":false,"types":["packed_simd::v128::m32x4"]},{"text":"impl Default for i64x2","synthetic":false,"types":["packed_simd::v128::i64x2"]},{"text":"impl Default for u64x2","synthetic":false,"types":["packed_simd::v128::u64x2"]},{"text":"impl Default for f64x2","synthetic":false,"types":["packed_simd::v128::f64x2"]},{"text":"impl Default for m64x2","synthetic":false,"types":["packed_simd::v128::m64x2"]},{"text":"impl Default for i128x1","synthetic":false,"types":["packed_simd::v128::i128x1"]},{"text":"impl Default for u128x1","synthetic":false,"types":["packed_simd::v128::u128x1"]},{"text":"impl Default for m128x1","synthetic":false,"types":["packed_simd::v128::m128x1"]},{"text":"impl Default for i8x32","synthetic":false,"types":["packed_simd::v256::i8x32"]},{"text":"impl Default for u8x32","synthetic":false,"types":["packed_simd::v256::u8x32"]},{"text":"impl Default for m8x32","synthetic":false,"types":["packed_simd::v256::m8x32"]},{"text":"impl Default for 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else {window.pending_implementors = implementors;}})() \ No newline at end of file diff --git a/implementors/core/fmt/trait.LowerHex.js b/implementors/core/fmt/trait.LowerHex.js new file mode 100644 index 000000000..08192de1b --- /dev/null +++ b/implementors/core/fmt/trait.LowerHex.js @@ -0,0 +1,3 @@ +(function() {var implementors = {}; +implementors["packed_simd"] = [{"text":"impl LowerHex for i8x2","synthetic":false,"types":["packed_simd::v16::i8x2"]},{"text":"impl LowerHex for u8x2","synthetic":false,"types":["packed_simd::v16::u8x2"]},{"text":"impl LowerHex for i8x4","synthetic":false,"types":["packed_simd::v32::i8x4"]},{"text":"impl LowerHex for u8x4","synthetic":false,"types":["packed_simd::v32::u8x4"]},{"text":"impl LowerHex for i16x2","synthetic":false,"types":["packed_simd::v32::i16x2"]},{"text":"impl LowerHex for u16x2","synthetic":false,"types":["packed_simd::v32::u16x2"]},{"text":"impl LowerHex for i8x8","synthetic":false,"types":["packed_simd::v64::i8x8"]},{"text":"impl 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100644 index 000000000..8a5a49b68 --- /dev/null +++ b/implementors/core/fmt/trait.Octal.js @@ -0,0 +1,3 @@ +(function() {var implementors = {}; +implementors["packed_simd"] = [{"text":"impl Octal for i8x2","synthetic":false,"types":["packed_simd::v16::i8x2"]},{"text":"impl Octal for u8x2","synthetic":false,"types":["packed_simd::v16::u8x2"]},{"text":"impl Octal for i8x4","synthetic":false,"types":["packed_simd::v32::i8x4"]},{"text":"impl Octal for u8x4","synthetic":false,"types":["packed_simd::v32::u8x4"]},{"text":"impl Octal for i16x2","synthetic":false,"types":["packed_simd::v32::i16x2"]},{"text":"impl Octal for u16x2","synthetic":false,"types":["packed_simd::v32::u16x2"]},{"text":"impl Octal for i8x8","synthetic":false,"types":["packed_simd::v64::i8x8"]},{"text":"impl Octal for u8x8","synthetic":false,"types":["packed_simd::v64::u8x8"]},{"text":"impl Octal for i16x4","synthetic":false,"types":["packed_simd::v64::i16x4"]},{"text":"impl Octal for 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UpperHex for i8x2","synthetic":false,"types":["packed_simd::v16::i8x2"]},{"text":"impl UpperHex for u8x2","synthetic":false,"types":["packed_simd::v16::u8x2"]},{"text":"impl UpperHex for i8x4","synthetic":false,"types":["packed_simd::v32::i8x4"]},{"text":"impl UpperHex for u8x4","synthetic":false,"types":["packed_simd::v32::u8x4"]},{"text":"impl UpperHex for i16x2","synthetic":false,"types":["packed_simd::v32::i16x2"]},{"text":"impl UpperHex for u16x2","synthetic":false,"types":["packed_simd::v32::u16x2"]},{"text":"impl UpperHex for i8x8","synthetic":false,"types":["packed_simd::v64::i8x8"]},{"text":"impl UpperHex for u8x8","synthetic":false,"types":["packed_simd::v64::u8x8"]},{"text":"impl UpperHex for i16x4","synthetic":false,"types":["packed_simd::v64::i16x4"]},{"text":"impl UpperHex for u16x4","synthetic":false,"types":["packed_simd::v64::u16x4"]},{"text":"impl UpperHex for i32x2","synthetic":false,"types":["packed_simd::v64::i32x2"]},{"text":"impl UpperHex for u32x2","synthetic":false,"types":["packed_simd::v64::u32x2"]},{"text":"impl UpperHex for i8x16","synthetic":false,"types":["packed_simd::v128::i8x16"]},{"text":"impl UpperHex for u8x16","synthetic":false,"types":["packed_simd::v128::u8x16"]},{"text":"impl UpperHex for i16x8","synthetic":false,"types":["packed_simd::v128::i16x8"]},{"text":"impl UpperHex for u16x8","synthetic":false,"types":["packed_simd::v128::u16x8"]},{"text":"impl UpperHex for i32x4","synthetic":false,"types":["packed_simd::v128::i32x4"]},{"text":"impl UpperHex for u32x4","synthetic":false,"types":["packed_simd::v128::u32x4"]},{"text":"impl UpperHex for i64x2","synthetic":false,"types":["packed_simd::v128::i64x2"]},{"text":"impl UpperHex for u64x2","synthetic":false,"types":["packed_simd::v128::u64x2"]},{"text":"impl UpperHex for i128x1","synthetic":false,"types":["packed_simd::v128::i128x1"]},{"text":"impl UpperHex for u128x1","synthetic":false,"types":["packed_simd::v128::u128x1"]},{"text":"impl UpperHex for i8x32","synthetic":false,"types":["packed_simd::v256::i8x32"]},{"text":"impl UpperHex for u8x32","synthetic":false,"types":["packed_simd::v256::u8x32"]},{"text":"impl UpperHex for i16x16","synthetic":false,"types":["packed_simd::v256::i16x16"]},{"text":"impl UpperHex for u16x16","synthetic":false,"types":["packed_simd::v256::u16x16"]},{"text":"impl UpperHex for i32x8","synthetic":false,"types":["packed_simd::v256::i32x8"]},{"text":"impl UpperHex for u32x8","synthetic":false,"types":["packed_simd::v256::u32x8"]},{"text":"impl UpperHex for i64x4","synthetic":false,"types":["packed_simd::v256::i64x4"]},{"text":"impl UpperHex for u64x4","synthetic":false,"types":["packed_simd::v256::u64x4"]},{"text":"impl UpperHex for i128x2","synthetic":false,"types":["packed_simd::v256::i128x2"]},{"text":"impl UpperHex for u128x2","synthetic":false,"types":["packed_simd::v256::u128x2"]},{"text":"impl UpperHex for i8x64","synthetic":false,"types":["packed_simd::v512::i8x64"]},{"text":"impl UpperHex for u8x64","synthetic":false,"types":["packed_simd::v512::u8x64"]},{"text":"impl UpperHex for i16x32","synthetic":false,"types":["packed_simd::v512::i16x32"]},{"text":"impl UpperHex for u16x32","synthetic":false,"types":["packed_simd::v512::u16x32"]},{"text":"impl UpperHex for i32x16","synthetic":false,"types":["packed_simd::v512::i32x16"]},{"text":"impl UpperHex for u32x16","synthetic":false,"types":["packed_simd::v512::u32x16"]},{"text":"impl UpperHex for i64x8","synthetic":false,"types":["packed_simd::v512::i64x8"]},{"text":"impl UpperHex for u64x8","synthetic":false,"types":["packed_simd::v512::u64x8"]},{"text":"impl UpperHex for i128x4","synthetic":false,"types":["packed_simd::v512::i128x4"]},{"text":"impl UpperHex for u128x4","synthetic":false,"types":["packed_simd::v512::u128x4"]},{"text":"impl UpperHex for isizex2","synthetic":false,"types":["packed_simd::vSize::isizex2"]},{"text":"impl UpperHex for usizex2","synthetic":false,"types":["packed_simd::vSize::usizex2"]},{"text":"impl UpperHex for isizex4","synthetic":false,"types":["packed_simd::vSize::isizex4"]},{"text":"impl UpperHex for usizex4","synthetic":false,"types":["packed_simd::vSize::usizex4"]},{"text":"impl UpperHex for isizex8","synthetic":false,"types":["packed_simd::vSize::isizex8"]},{"text":"impl UpperHex for usizex8","synthetic":false,"types":["packed_simd::vSize::usizex8"]}]; +if (window.register_implementors) {window.register_implementors(implementors);} else {window.pending_implementors = implementors;}})() \ No newline at end of file diff --git a/implementors/core/hash/trait.Hash.js b/implementors/core/hash/trait.Hash.js new file mode 100644 index 000000000..193c9b790 --- /dev/null +++ b/implementors/core/hash/trait.Hash.js @@ -0,0 +1,3 @@ +(function() {var implementors = {}; +implementors["packed_simd"] = [{"text":"impl Hash for m8","synthetic":false,"types":["packed_simd::masks::m8"]},{"text":"impl Hash for m16","synthetic":false,"types":["packed_simd::masks::m16"]},{"text":"impl Hash for m32","synthetic":false,"types":["packed_simd::masks::m32"]},{"text":"impl Hash for m64","synthetic":false,"types":["packed_simd::masks::m64"]},{"text":"impl Hash for m128","synthetic":false,"types":["packed_simd::masks::m128"]},{"text":"impl Hash for msize","synthetic":false,"types":["packed_simd::masks::msize"]},{"text":"impl Hash for i8x2","synthetic":false,"types":["packed_simd::v16::i8x2"]},{"text":"impl Hash for u8x2","synthetic":false,"types":["packed_simd::v16::u8x2"]},{"text":"impl Hash for i8x4","synthetic":false,"types":["packed_simd::v32::i8x4"]},{"text":"impl Hash for u8x4","synthetic":false,"types":["packed_simd::v32::u8x4"]},{"text":"impl Hash for i16x2","synthetic":false,"types":["packed_simd::v32::i16x2"]},{"text":"impl Hash for u16x2","synthetic":false,"types":["packed_simd::v32::u16x2"]},{"text":"impl Hash for i8x8","synthetic":false,"types":["packed_simd::v64::i8x8"]},{"text":"impl Hash for u8x8","synthetic":false,"types":["packed_simd::v64::u8x8"]},{"text":"impl Hash for i16x4","synthetic":false,"types":["packed_simd::v64::i16x4"]},{"text":"impl Hash for u16x4","synthetic":false,"types":["packed_simd::v64::u16x4"]},{"text":"impl Hash for i32x2","synthetic":false,"types":["packed_simd::v64::i32x2"]},{"text":"impl Hash for u32x2","synthetic":false,"types":["packed_simd::v64::u32x2"]},{"text":"impl Hash for i8x16","synthetic":false,"types":["packed_simd::v128::i8x16"]},{"text":"impl Hash for u8x16","synthetic":false,"types":["packed_simd::v128::u8x16"]},{"text":"impl Hash for i16x8","synthetic":false,"types":["packed_simd::v128::i16x8"]},{"text":"impl Hash for u16x8","synthetic":false,"types":["packed_simd::v128::u16x8"]},{"text":"impl Hash for i32x4","synthetic":false,"types":["packed_simd::v128::i32x4"]},{"text":"impl Hash for u32x4","synthetic":false,"types":["packed_simd::v128::u32x4"]},{"text":"impl Hash for i64x2","synthetic":false,"types":["packed_simd::v128::i64x2"]},{"text":"impl Hash for u64x2","synthetic":false,"types":["packed_simd::v128::u64x2"]},{"text":"impl Hash for i128x1","synthetic":false,"types":["packed_simd::v128::i128x1"]},{"text":"impl Hash for u128x1","synthetic":false,"types":["packed_simd::v128::u128x1"]},{"text":"impl Hash for i8x32","synthetic":false,"types":["packed_simd::v256::i8x32"]},{"text":"impl Hash for u8x32","synthetic":false,"types":["packed_simd::v256::u8x32"]},{"text":"impl Hash for i16x16","synthetic":false,"types":["packed_simd::v256::i16x16"]},{"text":"impl Hash for u16x16","synthetic":false,"types":["packed_simd::v256::u16x16"]},{"text":"impl Hash for i32x8","synthetic":false,"types":["packed_simd::v256::i32x8"]},{"text":"impl Hash for u32x8","synthetic":false,"types":["packed_simd::v256::u32x8"]},{"text":"impl Hash for i64x4","synthetic":false,"types":["packed_simd::v256::i64x4"]},{"text":"impl Hash for u64x4","synthetic":false,"types":["packed_simd::v256::u64x4"]},{"text":"impl Hash for i128x2","synthetic":false,"types":["packed_simd::v256::i128x2"]},{"text":"impl Hash for u128x2","synthetic":false,"types":["packed_simd::v256::u128x2"]},{"text":"impl Hash for i8x64","synthetic":false,"types":["packed_simd::v512::i8x64"]},{"text":"impl Hash for u8x64","synthetic":false,"types":["packed_simd::v512::u8x64"]},{"text":"impl Hash for i16x32","synthetic":false,"types":["packed_simd::v512::i16x32"]},{"text":"impl Hash for u16x32","synthetic":false,"types":["packed_simd::v512::u16x32"]},{"text":"impl Hash for i32x16","synthetic":false,"types":["packed_simd::v512::i32x16"]},{"text":"impl Hash for u32x16","synthetic":false,"types":["packed_simd::v512::u32x16"]},{"text":"impl Hash for i64x8","synthetic":false,"types":["packed_simd::v512::i64x8"]},{"text":"impl Hash for u64x8","synthetic":false,"types":["packed_simd::v512::u64x8"]},{"text":"impl Hash for i128x4","synthetic":false,"types":["packed_simd::v512::i128x4"]},{"text":"impl Hash for u128x4","synthetic":false,"types":["packed_simd::v512::u128x4"]},{"text":"impl Hash for isizex2","synthetic":false,"types":["packed_simd::vSize::isizex2"]},{"text":"impl Hash for usizex2","synthetic":false,"types":["packed_simd::vSize::usizex2"]},{"text":"impl Hash for isizex4","synthetic":false,"types":["packed_simd::vSize::isizex4"]},{"text":"impl Hash for usizex4","synthetic":false,"types":["packed_simd::vSize::usizex4"]},{"text":"impl Hash for isizex8","synthetic":false,"types":["packed_simd::vSize::isizex8"]},{"text":"impl Hash for usizex8","synthetic":false,"types":["packed_simd::vSize::usizex8"]},{"text":"impl<T> Hash for cptrx2<T>","synthetic":false,"types":["packed_simd::vPtr::cptrx2"]},{"text":"impl<T> Hash for mptrx2<T>","synthetic":false,"types":["packed_simd::vPtr::mptrx2"]},{"text":"impl<T> Hash for cptrx4<T>","synthetic":false,"types":["packed_simd::vPtr::cptrx4"]},{"text":"impl<T> Hash for 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f64x8","synthetic":false,"types":["packed_simd::v512::f64x8"]},{"text":"impl<'a> Product<&'a Simd<[f64; 8]>> for f64x8","synthetic":false,"types":["packed_simd::v512::f64x8"]},{"text":"impl Product<Simd<[i128; 4]>> for i128x4","synthetic":false,"types":["packed_simd::v512::i128x4"]},{"text":"impl<'a> Product<&'a Simd<[i128; 4]>> for i128x4","synthetic":false,"types":["packed_simd::v512::i128x4"]},{"text":"impl Product<Simd<[u128; 4]>> for u128x4","synthetic":false,"types":["packed_simd::v512::u128x4"]},{"text":"impl<'a> Product<&'a Simd<[u128; 4]>> for u128x4","synthetic":false,"types":["packed_simd::v512::u128x4"]},{"text":"impl Product<Simd<[isize; 2]>> for isizex2","synthetic":false,"types":["packed_simd::vSize::isizex2"]},{"text":"impl<'a> Product<&'a Simd<[isize; 2]>> for isizex2","synthetic":false,"types":["packed_simd::vSize::isizex2"]},{"text":"impl Product<Simd<[usize; 2]>> for usizex2","synthetic":false,"types":["packed_simd::vSize::usizex2"]},{"text":"impl<'a> Product<&'a Simd<[usize; 2]>> for usizex2","synthetic":false,"types":["packed_simd::vSize::usizex2"]},{"text":"impl Product<Simd<[isize; 4]>> for isizex4","synthetic":false,"types":["packed_simd::vSize::isizex4"]},{"text":"impl<'a> Product<&'a Simd<[isize; 4]>> for isizex4","synthetic":false,"types":["packed_simd::vSize::isizex4"]},{"text":"impl Product<Simd<[usize; 4]>> for usizex4","synthetic":false,"types":["packed_simd::vSize::usizex4"]},{"text":"impl<'a> Product<&'a Simd<[usize; 4]>> for usizex4","synthetic":false,"types":["packed_simd::vSize::usizex4"]},{"text":"impl Product<Simd<[isize; 8]>> for isizex8","synthetic":false,"types":["packed_simd::vSize::isizex8"]},{"text":"impl<'a> Product<&'a Simd<[isize; 8]>> for isizex8","synthetic":false,"types":["packed_simd::vSize::isizex8"]},{"text":"impl Product<Simd<[usize; 8]>> for usizex8","synthetic":false,"types":["packed_simd::vSize::usizex8"]},{"text":"impl<'a> Product<&'a Simd<[usize; 8]>> for usizex8","synthetic":false,"types":["packed_simd::vSize::usizex8"]}]; +if (window.register_implementors) {window.register_implementors(implementors);} else {window.pending_implementors = implementors;}})() \ No newline at end of file diff --git a/implementors/core/iter/traits/accum/trait.Sum.js b/implementors/core/iter/traits/accum/trait.Sum.js new file mode 100644 index 000000000..1c55637e4 --- /dev/null +++ b/implementors/core/iter/traits/accum/trait.Sum.js @@ -0,0 +1,3 @@ +(function() {var implementors = {}; +implementors["packed_simd"] = [{"text":"impl Sum<Simd<[i8; 2]>> for i8x2","synthetic":false,"types":["packed_simd::v16::i8x2"]},{"text":"impl<'a> Sum<&'a Simd<[i8; 2]>> for i8x2","synthetic":false,"types":["packed_simd::v16::i8x2"]},{"text":"impl Sum<Simd<[u8; 2]>> for u8x2","synthetic":false,"types":["packed_simd::v16::u8x2"]},{"text":"impl<'a> Sum<&'a Simd<[u8; 2]>> for u8x2","synthetic":false,"types":["packed_simd::v16::u8x2"]},{"text":"impl Sum<Simd<[i8; 4]>> for i8x4","synthetic":false,"types":["packed_simd::v32::i8x4"]},{"text":"impl<'a> Sum<&'a Simd<[i8; 4]>> for i8x4","synthetic":false,"types":["packed_simd::v32::i8x4"]},{"text":"impl Sum<Simd<[u8; 4]>> for u8x4","synthetic":false,"types":["packed_simd::v32::u8x4"]},{"text":"impl<'a> Sum<&'a Simd<[u8; 4]>> for u8x4","synthetic":false,"types":["packed_simd::v32::u8x4"]},{"text":"impl Sum<Simd<[i16; 2]>> for i16x2","synthetic":false,"types":["packed_simd::v32::i16x2"]},{"text":"impl<'a> Sum<&'a Simd<[i16; 2]>> for i16x2","synthetic":false,"types":["packed_simd::v32::i16x2"]},{"text":"impl Sum<Simd<[u16; 2]>> for u16x2","synthetic":false,"types":["packed_simd::v32::u16x2"]},{"text":"impl<'a> Sum<&'a Simd<[u16; 2]>> for u16x2","synthetic":false,"types":["packed_simd::v32::u16x2"]},{"text":"impl Sum<Simd<[i8; 8]>> for i8x8","synthetic":false,"types":["packed_simd::v64::i8x8"]},{"text":"impl<'a> Sum<&'a Simd<[i8; 8]>> for i8x8","synthetic":false,"types":["packed_simd::v64::i8x8"]},{"text":"impl Sum<Simd<[u8; 8]>> for u8x8","synthetic":false,"types":["packed_simd::v64::u8x8"]},{"text":"impl<'a> Sum<&'a Simd<[u8; 8]>> for u8x8","synthetic":false,"types":["packed_simd::v64::u8x8"]},{"text":"impl Sum<Simd<[i16; 4]>> for i16x4","synthetic":false,"types":["packed_simd::v64::i16x4"]},{"text":"impl<'a> Sum<&'a Simd<[i16; 4]>> for i16x4","synthetic":false,"types":["packed_simd::v64::i16x4"]},{"text":"impl Sum<Simd<[u16; 4]>> for u16x4","synthetic":false,"types":["packed_simd::v64::u16x4"]},{"text":"impl<'a> Sum<&'a Simd<[u16; 4]>> for u16x4","synthetic":false,"types":["packed_simd::v64::u16x4"]},{"text":"impl Sum<Simd<[i32; 2]>> for i32x2","synthetic":false,"types":["packed_simd::v64::i32x2"]},{"text":"impl<'a> Sum<&'a Simd<[i32; 2]>> for i32x2","synthetic":false,"types":["packed_simd::v64::i32x2"]},{"text":"impl Sum<Simd<[u32; 2]>> for u32x2","synthetic":false,"types":["packed_simd::v64::u32x2"]},{"text":"impl<'a> Sum<&'a Simd<[u32; 2]>> for u32x2","synthetic":false,"types":["packed_simd::v64::u32x2"]},{"text":"impl Sum<Simd<[f32; 2]>> for f32x2","synthetic":false,"types":["packed_simd::v64::f32x2"]},{"text":"impl<'a> Sum<&'a Simd<[f32; 2]>> for f32x2","synthetic":false,"types":["packed_simd::v64::f32x2"]},{"text":"impl Sum<Simd<[i8; 16]>> for i8x16","synthetic":false,"types":["packed_simd::v128::i8x16"]},{"text":"impl<'a> Sum<&'a Simd<[i8; 16]>> for i8x16","synthetic":false,"types":["packed_simd::v128::i8x16"]},{"text":"impl Sum<Simd<[u8; 16]>> for u8x16","synthetic":false,"types":["packed_simd::v128::u8x16"]},{"text":"impl<'a> Sum<&'a Simd<[u8; 16]>> for u8x16","synthetic":false,"types":["packed_simd::v128::u8x16"]},{"text":"impl Sum<Simd<[i16; 8]>> for i16x8","synthetic":false,"types":["packed_simd::v128::i16x8"]},{"text":"impl<'a> Sum<&'a Simd<[i16; 8]>> for i16x8","synthetic":false,"types":["packed_simd::v128::i16x8"]},{"text":"impl Sum<Simd<[u16; 8]>> for u16x8","synthetic":false,"types":["packed_simd::v128::u16x8"]},{"text":"impl<'a> Sum<&'a Simd<[u16; 8]>> for u16x8","synthetic":false,"types":["packed_simd::v128::u16x8"]},{"text":"impl Sum<Simd<[i32; 4]>> for i32x4","synthetic":false,"types":["packed_simd::v128::i32x4"]},{"text":"impl<'a> Sum<&'a Simd<[i32; 4]>> for i32x4","synthetic":false,"types":["packed_simd::v128::i32x4"]},{"text":"impl Sum<Simd<[u32; 4]>> for u32x4","synthetic":false,"types":["packed_simd::v128::u32x4"]},{"text":"impl<'a> Sum<&'a Simd<[u32; 4]>> for u32x4","synthetic":false,"types":["packed_simd::v128::u32x4"]},{"text":"impl Sum<Simd<[f32; 4]>> for f32x4","synthetic":false,"types":["packed_simd::v128::f32x4"]},{"text":"impl<'a> Sum<&'a Simd<[f32; 4]>> for f32x4","synthetic":false,"types":["packed_simd::v128::f32x4"]},{"text":"impl Sum<Simd<[i64; 2]>> for i64x2","synthetic":false,"types":["packed_simd::v128::i64x2"]},{"text":"impl<'a> Sum<&'a Simd<[i64; 2]>> for i64x2","synthetic":false,"types":["packed_simd::v128::i64x2"]},{"text":"impl Sum<Simd<[u64; 2]>> for u64x2","synthetic":false,"types":["packed_simd::v128::u64x2"]},{"text":"impl<'a> Sum<&'a Simd<[u64; 2]>> for u64x2","synthetic":false,"types":["packed_simd::v128::u64x2"]},{"text":"impl Sum<Simd<[f64; 2]>> for f64x2","synthetic":false,"types":["packed_simd::v128::f64x2"]},{"text":"impl<'a> Sum<&'a Simd<[f64; 2]>> for f64x2","synthetic":false,"types":["packed_simd::v128::f64x2"]},{"text":"impl Sum<Simd<[i128; 1]>> for i128x1","synthetic":false,"types":["packed_simd::v128::i128x1"]},{"text":"impl<'a> Sum<&'a Simd<[i128; 1]>> for i128x1","synthetic":false,"types":["packed_simd::v128::i128x1"]},{"text":"impl Sum<Simd<[u128; 1]>> for u128x1","synthetic":false,"types":["packed_simd::v128::u128x1"]},{"text":"impl<'a> Sum<&'a Simd<[u128; 1]>> for u128x1","synthetic":false,"types":["packed_simd::v128::u128x1"]},{"text":"impl Sum<Simd<[i8; 32]>> for i8x32","synthetic":false,"types":["packed_simd::v256::i8x32"]},{"text":"impl<'a> Sum<&'a Simd<[i8; 32]>> for i8x32","synthetic":false,"types":["packed_simd::v256::i8x32"]},{"text":"impl Sum<Simd<[u8; 32]>> for u8x32","synthetic":false,"types":["packed_simd::v256::u8x32"]},{"text":"impl<'a> Sum<&'a Simd<[u8; 32]>> for u8x32","synthetic":false,"types":["packed_simd::v256::u8x32"]},{"text":"impl Sum<Simd<[i16; 16]>> for i16x16","synthetic":false,"types":["packed_simd::v256::i16x16"]},{"text":"impl<'a> Sum<&'a Simd<[i16; 16]>> for i16x16","synthetic":false,"types":["packed_simd::v256::i16x16"]},{"text":"impl Sum<Simd<[u16; 16]>> for u16x16","synthetic":false,"types":["packed_simd::v256::u16x16"]},{"text":"impl<'a> Sum<&'a Simd<[u16; 16]>> for u16x16","synthetic":false,"types":["packed_simd::v256::u16x16"]},{"text":"impl Sum<Simd<[i32; 8]>> for i32x8","synthetic":false,"types":["packed_simd::v256::i32x8"]},{"text":"impl<'a> Sum<&'a Simd<[i32; 8]>> for i32x8","synthetic":false,"types":["packed_simd::v256::i32x8"]},{"text":"impl Sum<Simd<[u32; 8]>> for u32x8","synthetic":false,"types":["packed_simd::v256::u32x8"]},{"text":"impl<'a> Sum<&'a Simd<[u32; 8]>> for u32x8","synthetic":false,"types":["packed_simd::v256::u32x8"]},{"text":"impl Sum<Simd<[f32; 8]>> for f32x8","synthetic":false,"types":["packed_simd::v256::f32x8"]},{"text":"impl<'a> Sum<&'a Simd<[f32; 8]>> for f32x8","synthetic":false,"types":["packed_simd::v256::f32x8"]},{"text":"impl Sum<Simd<[i64; 4]>> for i64x4","synthetic":false,"types":["packed_simd::v256::i64x4"]},{"text":"impl<'a> Sum<&'a Simd<[i64; 4]>> for i64x4","synthetic":false,"types":["packed_simd::v256::i64x4"]},{"text":"impl Sum<Simd<[u64; 4]>> for u64x4","synthetic":false,"types":["packed_simd::v256::u64x4"]},{"text":"impl<'a> Sum<&'a Simd<[u64; 4]>> for u64x4","synthetic":false,"types":["packed_simd::v256::u64x4"]},{"text":"impl Sum<Simd<[f64; 4]>> for f64x4","synthetic":false,"types":["packed_simd::v256::f64x4"]},{"text":"impl<'a> Sum<&'a Simd<[f64; 4]>> for f64x4","synthetic":false,"types":["packed_simd::v256::f64x4"]},{"text":"impl Sum<Simd<[i128; 2]>> for i128x2","synthetic":false,"types":["packed_simd::v256::i128x2"]},{"text":"impl<'a> Sum<&'a Simd<[i128; 2]>> for i128x2","synthetic":false,"types":["packed_simd::v256::i128x2"]},{"text":"impl Sum<Simd<[u128; 2]>> for u128x2","synthetic":false,"types":["packed_simd::v256::u128x2"]},{"text":"impl<'a> Sum<&'a Simd<[u128; 2]>> for u128x2","synthetic":false,"types":["packed_simd::v256::u128x2"]},{"text":"impl Sum<Simd<[i8; 64]>> for i8x64","synthetic":false,"types":["packed_simd::v512::i8x64"]},{"text":"impl<'a> Sum<&'a Simd<[i8; 64]>> for i8x64","synthetic":false,"types":["packed_simd::v512::i8x64"]},{"text":"impl Sum<Simd<[u8; 64]>> for u8x64","synthetic":false,"types":["packed_simd::v512::u8x64"]},{"text":"impl<'a> Sum<&'a Simd<[u8; 64]>> for u8x64","synthetic":false,"types":["packed_simd::v512::u8x64"]},{"text":"impl Sum<Simd<[i16; 32]>> for i16x32","synthetic":false,"types":["packed_simd::v512::i16x32"]},{"text":"impl<'a> Sum<&'a Simd<[i16; 32]>> for i16x32","synthetic":false,"types":["packed_simd::v512::i16x32"]},{"text":"impl Sum<Simd<[u16; 32]>> for u16x32","synthetic":false,"types":["packed_simd::v512::u16x32"]},{"text":"impl<'a> Sum<&'a Simd<[u16; 32]>> for u16x32","synthetic":false,"types":["packed_simd::v512::u16x32"]},{"text":"impl Sum<Simd<[i32; 16]>> for i32x16","synthetic":false,"types":["packed_simd::v512::i32x16"]},{"text":"impl<'a> Sum<&'a Simd<[i32; 16]>> for i32x16","synthetic":false,"types":["packed_simd::v512::i32x16"]},{"text":"impl Sum<Simd<[u32; 16]>> for u32x16","synthetic":false,"types":["packed_simd::v512::u32x16"]},{"text":"impl<'a> Sum<&'a Simd<[u32; 16]>> for u32x16","synthetic":false,"types":["packed_simd::v512::u32x16"]},{"text":"impl Sum<Simd<[f32; 16]>> for f32x16","synthetic":false,"types":["packed_simd::v512::f32x16"]},{"text":"impl<'a> Sum<&'a Simd<[f32; 16]>> for f32x16","synthetic":false,"types":["packed_simd::v512::f32x16"]},{"text":"impl Sum<Simd<[i64; 8]>> for i64x8","synthetic":false,"types":["packed_simd::v512::i64x8"]},{"text":"impl<'a> Sum<&'a Simd<[i64; 8]>> for i64x8","synthetic":false,"types":["packed_simd::v512::i64x8"]},{"text":"impl Sum<Simd<[u64; 8]>> for u64x8","synthetic":false,"types":["packed_simd::v512::u64x8"]},{"text":"impl<'a> Sum<&'a Simd<[u64; 8]>> for u64x8","synthetic":false,"types":["packed_simd::v512::u64x8"]},{"text":"impl Sum<Simd<[f64; 8]>> for f64x8","synthetic":false,"types":["packed_simd::v512::f64x8"]},{"text":"impl<'a> Sum<&'a Simd<[f64; 8]>> for f64x8","synthetic":false,"types":["packed_simd::v512::f64x8"]},{"text":"impl Sum<Simd<[i128; 4]>> for i128x4","synthetic":false,"types":["packed_simd::v512::i128x4"]},{"text":"impl<'a> Sum<&'a Simd<[i128; 4]>> for i128x4","synthetic":false,"types":["packed_simd::v512::i128x4"]},{"text":"impl Sum<Simd<[u128; 4]>> for u128x4","synthetic":false,"types":["packed_simd::v512::u128x4"]},{"text":"impl<'a> Sum<&'a Simd<[u128; 4]>> for u128x4","synthetic":false,"types":["packed_simd::v512::u128x4"]},{"text":"impl Sum<Simd<[isize; 2]>> for isizex2","synthetic":false,"types":["packed_simd::vSize::isizex2"]},{"text":"impl<'a> Sum<&'a Simd<[isize; 2]>> for isizex2","synthetic":false,"types":["packed_simd::vSize::isizex2"]},{"text":"impl Sum<Simd<[usize; 2]>> for usizex2","synthetic":false,"types":["packed_simd::vSize::usizex2"]},{"text":"impl<'a> Sum<&'a Simd<[usize; 2]>> for usizex2","synthetic":false,"types":["packed_simd::vSize::usizex2"]},{"text":"impl Sum<Simd<[isize; 4]>> for isizex4","synthetic":false,"types":["packed_simd::vSize::isizex4"]},{"text":"impl<'a> Sum<&'a Simd<[isize; 4]>> for isizex4","synthetic":false,"types":["packed_simd::vSize::isizex4"]},{"text":"impl Sum<Simd<[usize; 4]>> for usizex4","synthetic":false,"types":["packed_simd::vSize::usizex4"]},{"text":"impl<'a> Sum<&'a Simd<[usize; 4]>> for usizex4","synthetic":false,"types":["packed_simd::vSize::usizex4"]},{"text":"impl Sum<Simd<[isize; 8]>> for isizex8","synthetic":false,"types":["packed_simd::vSize::isizex8"]},{"text":"impl<'a> Sum<&'a Simd<[isize; 8]>> for isizex8","synthetic":false,"types":["packed_simd::vSize::isizex8"]},{"text":"impl Sum<Simd<[usize; 8]>> for usizex8","synthetic":false,"types":["packed_simd::vSize::usizex8"]},{"text":"impl<'a> Sum<&'a Simd<[usize; 8]>> for usizex8","synthetic":false,"types":["packed_simd::vSize::usizex8"]}]; +if (window.register_implementors) {window.register_implementors(implementors);} else {window.pending_implementors = implementors;}})() \ No newline at end of file diff --git a/implementors/core/marker/trait.Copy.js b/implementors/core/marker/trait.Copy.js new file mode 100644 index 000000000..690cf875e --- /dev/null +++ b/implementors/core/marker/trait.Copy.js @@ -0,0 +1,3 @@ +(function() {var implementors = {}; +implementors["packed_simd"] = [{"text":"impl<A: Copy + SimdArray> Copy for Simd<A>","synthetic":false,"types":["packed_simd::Simd"]},{"text":"impl<T: Copy> Copy for LexicographicallyOrdered<T>","synthetic":false,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Copy for m8","synthetic":false,"types":["packed_simd::masks::m8"]},{"text":"impl Copy for m16","synthetic":false,"types":["packed_simd::masks::m16"]},{"text":"impl Copy for m32","synthetic":false,"types":["packed_simd::masks::m32"]},{"text":"impl Copy for m64","synthetic":false,"types":["packed_simd::masks::m64"]},{"text":"impl Copy for m128","synthetic":false,"types":["packed_simd::masks::m128"]},{"text":"impl Copy for msize","synthetic":false,"types":["packed_simd::masks::msize"]}]; +if (window.register_implementors) {window.register_implementors(implementors);} else {window.pending_implementors = implementors;}})() \ No newline at end of file diff --git a/implementors/core/marker/trait.Freeze.js b/implementors/core/marker/trait.Freeze.js new file mode 100644 index 000000000..8962707c0 --- /dev/null +++ b/implementors/core/marker/trait.Freeze.js @@ -0,0 +1,3 @@ +(function() {var implementors = {}; +implementors["packed_simd"] = [{"text":"impl<A> Freeze for Simd<A> where
    <A as SimdArray>::Tuple: Freeze, ","synthetic":true,"types":["packed_simd::Simd"]},{"text":"impl<T> Freeze for LexicographicallyOrdered<T> where
    T: Freeze, ","synthetic":true,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Freeze for m8","synthetic":true,"types":["packed_simd::masks::m8"]},{"text":"impl Freeze for m16","synthetic":true,"types":["packed_simd::masks::m16"]},{"text":"impl Freeze for m32","synthetic":true,"types":["packed_simd::masks::m32"]},{"text":"impl Freeze for m64","synthetic":true,"types":["packed_simd::masks::m64"]},{"text":"impl Freeze for m128","synthetic":true,"types":["packed_simd::masks::m128"]},{"text":"impl Freeze for msize","synthetic":true,"types":["packed_simd::masks::msize"]}]; +if (window.register_implementors) {window.register_implementors(implementors);} else {window.pending_implementors = implementors;}})() \ No newline at end of file diff --git a/implementors/core/marker/trait.Send.js b/implementors/core/marker/trait.Send.js new file mode 100644 index 000000000..90fd192c2 --- /dev/null +++ b/implementors/core/marker/trait.Send.js @@ -0,0 +1,3 @@ +(function() {var implementors = {}; +implementors["packed_simd"] = [{"text":"impl<A> Send for Simd<A> where
    <A as SimdArray>::Tuple: Send, ","synthetic":true,"types":["packed_simd::Simd"]},{"text":"impl<T> Send for LexicographicallyOrdered<T> where
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    <A as SimdArray>::Tuple: Sync, ","synthetic":true,"types":["packed_simd::Simd"]},{"text":"impl<T> Sync for LexicographicallyOrdered<T> where
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    <A as SimdArray>::Tuple: Unpin, ","synthetic":true,"types":["packed_simd::Simd"]},{"text":"impl<T> Unpin for LexicographicallyOrdered<T> where
    T: Unpin, ","synthetic":true,"types":["packed_simd::LexicographicallyOrdered"]},{"text":"impl Unpin for m8","synthetic":true,"types":["packed_simd::masks::m8"]},{"text":"impl Unpin for m16","synthetic":true,"types":["packed_simd::masks::m16"]},{"text":"impl Unpin for m32","synthetic":true,"types":["packed_simd::masks::m32"]},{"text":"impl Unpin for m64","synthetic":true,"types":["packed_simd::masks::m64"]},{"text":"impl Unpin for m128","synthetic":true,"types":["packed_simd::masks::m128"]},{"text":"impl Unpin for msize","synthetic":true,"types":["packed_simd::masks::msize"]}]; +if (window.register_implementors) {window.register_implementors(implementors);} else {window.pending_implementors = implementors;}})() \ No newline at end of file diff --git a/implementors/core/ops/arith/trait.Add.js b/implementors/core/ops/arith/trait.Add.js new file mode 100644 index 000000000..2f44f6f8c --- /dev/null +++ b/implementors/core/ops/arith/trait.Add.js @@ -0,0 +1,3 @@ +(function() {var implementors = {}; +implementors["packed_simd"] = [{"text":"impl Add<Simd<[i8; 2]>> for i8x2","synthetic":false,"types":["packed_simd::v16::i8x2"]},{"text":"impl Add<i8> for i8x2","synthetic":false,"types":["packed_simd::v16::i8x2"]},{"text":"impl Add<Simd<[i8; 2]>> for i8","synthetic":false,"types":[]},{"text":"impl Add<Simd<[u8; 2]>> for u8x2","synthetic":false,"types":["packed_simd::v16::u8x2"]},{"text":"impl Add<u8> for u8x2","synthetic":false,"types":["packed_simd::v16::u8x2"]},{"text":"impl Add<Simd<[u8; 2]>> for u8","synthetic":false,"types":[]},{"text":"impl Add<Simd<[i8; 4]>> for i8x4","synthetic":false,"types":["packed_simd::v32::i8x4"]},{"text":"impl Add<i8> for i8x4","synthetic":false,"types":["packed_simd::v32::i8x4"]},{"text":"impl Add<Simd<[i8; 4]>> for i8","synthetic":false,"types":[]},{"text":"impl Add<Simd<[u8; 4]>> for u8x4","synthetic":false,"types":["packed_simd::v32::u8x4"]},{"text":"impl Add<u8> for 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usizex8","synthetic":false,"types":["packed_simd::vSize::usizex8"]},{"text":"impl Add<Simd<[usize; 8]>> for usize","synthetic":false,"types":[]}]; +if (window.register_implementors) {window.register_implementors(implementors);} else {window.pending_implementors = implementors;}})() \ No newline at end of file diff --git a/implementors/core/ops/arith/trait.AddAssign.js b/implementors/core/ops/arith/trait.AddAssign.js new file mode 100644 index 000000000..dee23654c --- /dev/null +++ b/implementors/core/ops/arith/trait.AddAssign.js @@ -0,0 +1,3 @@ +(function() {var implementors = {}; +implementors["packed_simd"] = [{"text":"impl AddAssign<Simd<[i8; 2]>> for i8x2","synthetic":false,"types":["packed_simd::v16::i8x2"]},{"text":"impl AddAssign<i8> for i8x2","synthetic":false,"types":["packed_simd::v16::i8x2"]},{"text":"impl AddAssign<Simd<[u8; 2]>> for u8x2","synthetic":false,"types":["packed_simd::v16::u8x2"]},{"text":"impl AddAssign<u8> for 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u8","synthetic":false,"types":[]},{"text":"impl Div<Simd<[i16; 16]>> for i16x16","synthetic":false,"types":["packed_simd::v256::i16x16"]},{"text":"impl Div<i16> for i16x16","synthetic":false,"types":["packed_simd::v256::i16x16"]},{"text":"impl Div<Simd<[i16; 16]>> for i16","synthetic":false,"types":[]},{"text":"impl Div<Simd<[u16; 16]>> for u16x16","synthetic":false,"types":["packed_simd::v256::u16x16"]},{"text":"impl Div<u16> for u16x16","synthetic":false,"types":["packed_simd::v256::u16x16"]},{"text":"impl Div<Simd<[u16; 16]>> for u16","synthetic":false,"types":[]},{"text":"impl Div<Simd<[i32; 8]>> for i32x8","synthetic":false,"types":["packed_simd::v256::i32x8"]},{"text":"impl Div<i32> for i32x8","synthetic":false,"types":["packed_simd::v256::i32x8"]},{"text":"impl Div<Simd<[i32; 8]>> for i32","synthetic":false,"types":[]},{"text":"impl Div<Simd<[u32; 8]>> for u32x8","synthetic":false,"types":["packed_simd::v256::u32x8"]},{"text":"impl Div<u32> for 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f64x4","synthetic":false,"types":["packed_simd::v256::f64x4"]},{"text":"impl Div<f64> for f64x4","synthetic":false,"types":["packed_simd::v256::f64x4"]},{"text":"impl Div<Simd<[f64; 4]>> for f64","synthetic":false,"types":[]},{"text":"impl Div<Simd<[i128; 2]>> for i128x2","synthetic":false,"types":["packed_simd::v256::i128x2"]},{"text":"impl Div<i128> for i128x2","synthetic":false,"types":["packed_simd::v256::i128x2"]},{"text":"impl Div<Simd<[i128; 2]>> for i128","synthetic":false,"types":[]},{"text":"impl Div<Simd<[u128; 2]>> for u128x2","synthetic":false,"types":["packed_simd::v256::u128x2"]},{"text":"impl Div<u128> for u128x2","synthetic":false,"types":["packed_simd::v256::u128x2"]},{"text":"impl Div<Simd<[u128; 2]>> for u128","synthetic":false,"types":[]},{"text":"impl Div<Simd<[i8; 64]>> for i8x64","synthetic":false,"types":["packed_simd::v512::i8x64"]},{"text":"impl Div<i8> for i8x64","synthetic":false,"types":["packed_simd::v512::i8x64"]},{"text":"impl Div<Simd<[i8; 64]>> for i8","synthetic":false,"types":[]},{"text":"impl Div<Simd<[u8; 64]>> for u8x64","synthetic":false,"types":["packed_simd::v512::u8x64"]},{"text":"impl Div<u8> for u8x64","synthetic":false,"types":["packed_simd::v512::u8x64"]},{"text":"impl Div<Simd<[u8; 64]>> for u8","synthetic":false,"types":[]},{"text":"impl Div<Simd<[i16; 32]>> for i16x32","synthetic":false,"types":["packed_simd::v512::i16x32"]},{"text":"impl Div<i16> for i16x32","synthetic":false,"types":["packed_simd::v512::i16x32"]},{"text":"impl Div<Simd<[i16; 32]>> for i16","synthetic":false,"types":[]},{"text":"impl Div<Simd<[u16; 32]>> for u16x32","synthetic":false,"types":["packed_simd::v512::u16x32"]},{"text":"impl Div<u16> for u16x32","synthetic":false,"types":["packed_simd::v512::u16x32"]},{"text":"impl Div<Simd<[u16; 32]>> for u16","synthetic":false,"types":[]},{"text":"impl Div<Simd<[i32; 16]>> for i32x16","synthetic":false,"types":["packed_simd::v512::i32x16"]},{"text":"impl Div<i32> for i32x16","synthetic":false,"types":["packed_simd::v512::i32x16"]},{"text":"impl Div<Simd<[i32; 16]>> for i32","synthetic":false,"types":[]},{"text":"impl Div<Simd<[u32; 16]>> for u32x16","synthetic":false,"types":["packed_simd::v512::u32x16"]},{"text":"impl Div<u32> for u32x16","synthetic":false,"types":["packed_simd::v512::u32x16"]},{"text":"impl Div<Simd<[u32; 16]>> for u32","synthetic":false,"types":[]},{"text":"impl Div<Simd<[f32; 16]>> for f32x16","synthetic":false,"types":["packed_simd::v512::f32x16"]},{"text":"impl Div<f32> for f32x16","synthetic":false,"types":["packed_simd::v512::f32x16"]},{"text":"impl Div<Simd<[f32; 16]>> for f32","synthetic":false,"types":[]},{"text":"impl Div<Simd<[i64; 8]>> for i64x8","synthetic":false,"types":["packed_simd::v512::i64x8"]},{"text":"impl Div<i64> for i64x8","synthetic":false,"types":["packed_simd::v512::i64x8"]},{"text":"impl Div<Simd<[i64; 8]>> for i64","synthetic":false,"types":[]},{"text":"impl Div<Simd<[u64; 8]>> for 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u128","synthetic":false,"types":[]},{"text":"impl Div<Simd<[isize; 2]>> for isizex2","synthetic":false,"types":["packed_simd::vSize::isizex2"]},{"text":"impl Div<isize> for isizex2","synthetic":false,"types":["packed_simd::vSize::isizex2"]},{"text":"impl Div<Simd<[isize; 2]>> for isize","synthetic":false,"types":[]},{"text":"impl Div<Simd<[usize; 2]>> for usizex2","synthetic":false,"types":["packed_simd::vSize::usizex2"]},{"text":"impl Div<usize> for usizex2","synthetic":false,"types":["packed_simd::vSize::usizex2"]},{"text":"impl Div<Simd<[usize; 2]>> for usize","synthetic":false,"types":[]},{"text":"impl Div<Simd<[isize; 4]>> for isizex4","synthetic":false,"types":["packed_simd::vSize::isizex4"]},{"text":"impl Div<isize> for isizex4","synthetic":false,"types":["packed_simd::vSize::isizex4"]},{"text":"impl Div<Simd<[isize; 4]>> for isize","synthetic":false,"types":[]},{"text":"impl Div<Simd<[usize; 4]>> for usizex4","synthetic":false,"types":["packed_simd::vSize::usizex4"]},{"text":"impl Div<usize> for usizex4","synthetic":false,"types":["packed_simd::vSize::usizex4"]},{"text":"impl Div<Simd<[usize; 4]>> for usize","synthetic":false,"types":[]},{"text":"impl Div<Simd<[isize; 8]>> for isizex8","synthetic":false,"types":["packed_simd::vSize::isizex8"]},{"text":"impl Div<isize> for isizex8","synthetic":false,"types":["packed_simd::vSize::isizex8"]},{"text":"impl Div<Simd<[isize; 8]>> for isize","synthetic":false,"types":[]},{"text":"impl Div<Simd<[usize; 8]>> for usizex8","synthetic":false,"types":["packed_simd::vSize::usizex8"]},{"text":"impl Div<usize> for usizex8","synthetic":false,"types":["packed_simd::vSize::usizex8"]},{"text":"impl Div<Simd<[usize; 8]>> for usize","synthetic":false,"types":[]}]; +if (window.register_implementors) {window.register_implementors(implementors);} else {window.pending_implementors = implementors;}})() \ No newline at end of file diff --git a/implementors/core/ops/arith/trait.DivAssign.js b/implementors/core/ops/arith/trait.DivAssign.js new file mode 100644 index 000000000..de835a8e4 --- /dev/null +++ b/implementors/core/ops/arith/trait.DivAssign.js @@ -0,0 +1,3 @@ +(function() {var implementors = {}; +implementors["packed_simd"] = [{"text":"impl DivAssign<Simd<[i8; 2]>> for i8x2","synthetic":false,"types":["packed_simd::v16::i8x2"]},{"text":"impl DivAssign<i8> for i8x2","synthetic":false,"types":["packed_simd::v16::i8x2"]},{"text":"impl DivAssign<Simd<[u8; 2]>> for u8x2","synthetic":false,"types":["packed_simd::v16::u8x2"]},{"text":"impl DivAssign<u8> for u8x2","synthetic":false,"types":["packed_simd::v16::u8x2"]},{"text":"impl DivAssign<Simd<[i8; 4]>> for i8x4","synthetic":false,"types":["packed_simd::v32::i8x4"]},{"text":"impl DivAssign<i8> for i8x4","synthetic":false,"types":["packed_simd::v32::i8x4"]},{"text":"impl DivAssign<Simd<[u8; 4]>> for u8x4","synthetic":false,"types":["packed_simd::v32::u8x4"]},{"text":"impl DivAssign<u8> for u8x4","synthetic":false,"types":["packed_simd::v32::u8x4"]},{"text":"impl DivAssign<Simd<[i16; 2]>> for i16x2","synthetic":false,"types":["packed_simd::v32::i16x2"]},{"text":"impl DivAssign<i16> for i16x2","synthetic":false,"types":["packed_simd::v32::i16x2"]},{"text":"impl DivAssign<Simd<[u16; 2]>> for u16x2","synthetic":false,"types":["packed_simd::v32::u16x2"]},{"text":"impl DivAssign<u16> for u16x2","synthetic":false,"types":["packed_simd::v32::u16x2"]},{"text":"impl DivAssign<Simd<[i8; 8]>> for i8x8","synthetic":false,"types":["packed_simd::v64::i8x8"]},{"text":"impl DivAssign<i8> for i8x8","synthetic":false,"types":["packed_simd::v64::i8x8"]},{"text":"impl DivAssign<Simd<[u8; 8]>> for u8x8","synthetic":false,"types":["packed_simd::v64::u8x8"]},{"text":"impl DivAssign<u8> for u8x8","synthetic":false,"types":["packed_simd::v64::u8x8"]},{"text":"impl DivAssign<Simd<[i16; 4]>> for i16x4","synthetic":false,"types":["packed_simd::v64::i16x4"]},{"text":"impl DivAssign<i16> for i16x4","synthetic":false,"types":["packed_simd::v64::i16x4"]},{"text":"impl DivAssign<Simd<[u16; 4]>> for u16x4","synthetic":false,"types":["packed_simd::v64::u16x4"]},{"text":"impl DivAssign<u16> for u16x4","synthetic":false,"types":["packed_simd::v64::u16x4"]},{"text":"impl DivAssign<Simd<[i32; 2]>> for i32x2","synthetic":false,"types":["packed_simd::v64::i32x2"]},{"text":"impl DivAssign<i32> for i32x2","synthetic":false,"types":["packed_simd::v64::i32x2"]},{"text":"impl DivAssign<Simd<[u32; 2]>> for u32x2","synthetic":false,"types":["packed_simd::v64::u32x2"]},{"text":"impl DivAssign<u32> for u32x2","synthetic":false,"types":["packed_simd::v64::u32x2"]},{"text":"impl DivAssign<Simd<[f32; 2]>> for f32x2","synthetic":false,"types":["packed_simd::v64::f32x2"]},{"text":"impl DivAssign<f32> for f32x2","synthetic":false,"types":["packed_simd::v64::f32x2"]},{"text":"impl DivAssign<Simd<[i8; 16]>> for i8x16","synthetic":false,"types":["packed_simd::v128::i8x16"]},{"text":"impl DivAssign<i8> for i8x16","synthetic":false,"types":["packed_simd::v128::i8x16"]},{"text":"impl DivAssign<Simd<[u8; 16]>> for u8x16","synthetic":false,"types":["packed_simd::v128::u8x16"]},{"text":"impl DivAssign<u8> for u8x16","synthetic":false,"types":["packed_simd::v128::u8x16"]},{"text":"impl DivAssign<Simd<[i16; 8]>> for i16x8","synthetic":false,"types":["packed_simd::v128::i16x8"]},{"text":"impl DivAssign<i16> for i16x8","synthetic":false,"types":["packed_simd::v128::i16x8"]},{"text":"impl DivAssign<Simd<[u16; 8]>> for u16x8","synthetic":false,"types":["packed_simd::v128::u16x8"]},{"text":"impl DivAssign<u16> for u16x8","synthetic":false,"types":["packed_simd::v128::u16x8"]},{"text":"impl DivAssign<Simd<[i32; 4]>> for i32x4","synthetic":false,"types":["packed_simd::v128::i32x4"]},{"text":"impl DivAssign<i32> for i32x4","synthetic":false,"types":["packed_simd::v128::i32x4"]},{"text":"impl DivAssign<Simd<[u32; 4]>> for u32x4","synthetic":false,"types":["packed_simd::v128::u32x4"]},{"text":"impl DivAssign<u32> for u32x4","synthetic":false,"types":["packed_simd::v128::u32x4"]},{"text":"impl DivAssign<Simd<[f32; 4]>> for f32x4","synthetic":false,"types":["packed_simd::v128::f32x4"]},{"text":"impl DivAssign<f32> for f32x4","synthetic":false,"types":["packed_simd::v128::f32x4"]},{"text":"impl DivAssign<Simd<[i64; 2]>> for i64x2","synthetic":false,"types":["packed_simd::v128::i64x2"]},{"text":"impl DivAssign<i64> for i64x2","synthetic":false,"types":["packed_simd::v128::i64x2"]},{"text":"impl DivAssign<Simd<[u64; 2]>> for u64x2","synthetic":false,"types":["packed_simd::v128::u64x2"]},{"text":"impl DivAssign<u64> for u64x2","synthetic":false,"types":["packed_simd::v128::u64x2"]},{"text":"impl DivAssign<Simd<[f64; 2]>> for f64x2","synthetic":false,"types":["packed_simd::v128::f64x2"]},{"text":"impl DivAssign<f64> for f64x2","synthetic":false,"types":["packed_simd::v128::f64x2"]},{"text":"impl DivAssign<Simd<[i128; 1]>> for i128x1","synthetic":false,"types":["packed_simd::v128::i128x1"]},{"text":"impl DivAssign<i128> for i128x1","synthetic":false,"types":["packed_simd::v128::i128x1"]},{"text":"impl DivAssign<Simd<[u128; 1]>> for u128x1","synthetic":false,"types":["packed_simd::v128::u128x1"]},{"text":"impl DivAssign<u128> for u128x1","synthetic":false,"types":["packed_simd::v128::u128x1"]},{"text":"impl DivAssign<Simd<[i8; 32]>> for i8x32","synthetic":false,"types":["packed_simd::v256::i8x32"]},{"text":"impl DivAssign<i8> for i8x32","synthetic":false,"types":["packed_simd::v256::i8x32"]},{"text":"impl DivAssign<Simd<[u8; 32]>> for u8x32","synthetic":false,"types":["packed_simd::v256::u8x32"]},{"text":"impl DivAssign<u8> for u8x32","synthetic":false,"types":["packed_simd::v256::u8x32"]},{"text":"impl DivAssign<Simd<[i16; 16]>> for i16x16","synthetic":false,"types":["packed_simd::v256::i16x16"]},{"text":"impl DivAssign<i16> for i16x16","synthetic":false,"types":["packed_simd::v256::i16x16"]},{"text":"impl DivAssign<Simd<[u16; 16]>> for u16x16","synthetic":false,"types":["packed_simd::v256::u16x16"]},{"text":"impl DivAssign<u16> for u16x16","synthetic":false,"types":["packed_simd::v256::u16x16"]},{"text":"impl DivAssign<Simd<[i32; 8]>> for i32x8","synthetic":false,"types":["packed_simd::v256::i32x8"]},{"text":"impl DivAssign<i32> for i32x8","synthetic":false,"types":["packed_simd::v256::i32x8"]},{"text":"impl DivAssign<Simd<[u32; 8]>> for u32x8","synthetic":false,"types":["packed_simd::v256::u32x8"]},{"text":"impl DivAssign<u32> for u32x8","synthetic":false,"types":["packed_simd::v256::u32x8"]},{"text":"impl DivAssign<Simd<[f32; 8]>> for f32x8","synthetic":false,"types":["packed_simd::v256::f32x8"]},{"text":"impl DivAssign<f32> for f32x8","synthetic":false,"types":["packed_simd::v256::f32x8"]},{"text":"impl DivAssign<Simd<[i64; 4]>> for i64x4","synthetic":false,"types":["packed_simd::v256::i64x4"]},{"text":"impl DivAssign<i64> for i64x4","synthetic":false,"types":["packed_simd::v256::i64x4"]},{"text":"impl DivAssign<Simd<[u64; 4]>> for u64x4","synthetic":false,"types":["packed_simd::v256::u64x4"]},{"text":"impl DivAssign<u64> for u64x4","synthetic":false,"types":["packed_simd::v256::u64x4"]},{"text":"impl DivAssign<Simd<[f64; 4]>> for f64x4","synthetic":false,"types":["packed_simd::v256::f64x4"]},{"text":"impl DivAssign<f64> for f64x4","synthetic":false,"types":["packed_simd::v256::f64x4"]},{"text":"impl DivAssign<Simd<[i128; 2]>> for i128x2","synthetic":false,"types":["packed_simd::v256::i128x2"]},{"text":"impl DivAssign<i128> for i128x2","synthetic":false,"types":["packed_simd::v256::i128x2"]},{"text":"impl DivAssign<Simd<[u128; 2]>> for u128x2","synthetic":false,"types":["packed_simd::v256::u128x2"]},{"text":"impl DivAssign<u128> for u128x2","synthetic":false,"types":["packed_simd::v256::u128x2"]},{"text":"impl DivAssign<Simd<[i8; 64]>> for i8x64","synthetic":false,"types":["packed_simd::v512::i8x64"]},{"text":"impl DivAssign<i8> for i8x64","synthetic":false,"types":["packed_simd::v512::i8x64"]},{"text":"impl DivAssign<Simd<[u8; 64]>> for u8x64","synthetic":false,"types":["packed_simd::v512::u8x64"]},{"text":"impl DivAssign<u8> for u8x64","synthetic":false,"types":["packed_simd::v512::u8x64"]},{"text":"impl DivAssign<Simd<[i16; 32]>> for i16x32","synthetic":false,"types":["packed_simd::v512::i16x32"]},{"text":"impl DivAssign<i16> for i16x32","synthetic":false,"types":["packed_simd::v512::i16x32"]},{"text":"impl DivAssign<Simd<[u16; 32]>> for u16x32","synthetic":false,"types":["packed_simd::v512::u16x32"]},{"text":"impl DivAssign<u16> for u16x32","synthetic":false,"types":["packed_simd::v512::u16x32"]},{"text":"impl DivAssign<Simd<[i32; 16]>> for i32x16","synthetic":false,"types":["packed_simd::v512::i32x16"]},{"text":"impl DivAssign<i32> for i32x16","synthetic":false,"types":["packed_simd::v512::i32x16"]},{"text":"impl DivAssign<Simd<[u32; 16]>> for u32x16","synthetic":false,"types":["packed_simd::v512::u32x16"]},{"text":"impl DivAssign<u32> for u32x16","synthetic":false,"types":["packed_simd::v512::u32x16"]},{"text":"impl DivAssign<Simd<[f32; 16]>> for f32x16","synthetic":false,"types":["packed_simd::v512::f32x16"]},{"text":"impl DivAssign<f32> for f32x16","synthetic":false,"types":["packed_simd::v512::f32x16"]},{"text":"impl DivAssign<Simd<[i64; 8]>> for i64x8","synthetic":false,"types":["packed_simd::v512::i64x8"]},{"text":"impl DivAssign<i64> for i64x8","synthetic":false,"types":["packed_simd::v512::i64x8"]},{"text":"impl DivAssign<Simd<[u64; 8]>> for u64x8","synthetic":false,"types":["packed_simd::v512::u64x8"]},{"text":"impl DivAssign<u64> for u64x8","synthetic":false,"types":["packed_simd::v512::u64x8"]},{"text":"impl DivAssign<Simd<[f64; 8]>> for f64x8","synthetic":false,"types":["packed_simd::v512::f64x8"]},{"text":"impl DivAssign<f64> for f64x8","synthetic":false,"types":["packed_simd::v512::f64x8"]},{"text":"impl DivAssign<Simd<[i128; 4]>> for i128x4","synthetic":false,"types":["packed_simd::v512::i128x4"]},{"text":"impl DivAssign<i128> for i128x4","synthetic":false,"types":["packed_simd::v512::i128x4"]},{"text":"impl DivAssign<Simd<[u128; 4]>> for u128x4","synthetic":false,"types":["packed_simd::v512::u128x4"]},{"text":"impl DivAssign<u128> for u128x4","synthetic":false,"types":["packed_simd::v512::u128x4"]},{"text":"impl DivAssign<Simd<[isize; 2]>> for isizex2","synthetic":false,"types":["packed_simd::vSize::isizex2"]},{"text":"impl DivAssign<isize> for isizex2","synthetic":false,"types":["packed_simd::vSize::isizex2"]},{"text":"impl DivAssign<Simd<[usize; 2]>> for usizex2","synthetic":false,"types":["packed_simd::vSize::usizex2"]},{"text":"impl DivAssign<usize> for usizex2","synthetic":false,"types":["packed_simd::vSize::usizex2"]},{"text":"impl DivAssign<Simd<[isize; 4]>> for isizex4","synthetic":false,"types":["packed_simd::vSize::isizex4"]},{"text":"impl DivAssign<isize> for isizex4","synthetic":false,"types":["packed_simd::vSize::isizex4"]},{"text":"impl DivAssign<Simd<[usize; 4]>> for usizex4","synthetic":false,"types":["packed_simd::vSize::usizex4"]},{"text":"impl DivAssign<usize> for usizex4","synthetic":false,"types":["packed_simd::vSize::usizex4"]},{"text":"impl DivAssign<Simd<[isize; 8]>> for isizex8","synthetic":false,"types":["packed_simd::vSize::isizex8"]},{"text":"impl DivAssign<isize> for isizex8","synthetic":false,"types":["packed_simd::vSize::isizex8"]},{"text":"impl DivAssign<Simd<[usize; 8]>> for usizex8","synthetic":false,"types":["packed_simd::vSize::usizex8"]},{"text":"impl DivAssign<usize> for usizex8","synthetic":false,"types":["packed_simd::vSize::usizex8"]}]; +if (window.register_implementors) {window.register_implementors(implementors);} else {window.pending_implementors = implementors;}})() \ No newline at end of file diff --git a/implementors/core/ops/arith/trait.Mul.js b/implementors/core/ops/arith/trait.Mul.js new file mode 100644 index 000000000..b7285e2c8 --- /dev/null +++ b/implementors/core/ops/arith/trait.Mul.js @@ -0,0 +1,3 @@ +(function() {var implementors = {}; +implementors["packed_simd"] = [{"text":"impl Mul<Simd<[i8; 2]>> for i8x2","synthetic":false,"types":["packed_simd::v16::i8x2"]},{"text":"impl Mul<i8> for i8x2","synthetic":false,"types":["packed_simd::v16::i8x2"]},{"text":"impl Mul<Simd<[i8; 2]>> for i8","synthetic":false,"types":[]},{"text":"impl Mul<Simd<[u8; 2]>> for u8x2","synthetic":false,"types":["packed_simd::v16::u8x2"]},{"text":"impl Mul<u8> for u8x2","synthetic":false,"types":["packed_simd::v16::u8x2"]},{"text":"impl Mul<Simd<[u8; 2]>> for u8","synthetic":false,"types":[]},{"text":"impl Mul<Simd<[i8; 4]>> for i8x4","synthetic":false,"types":["packed_simd::v32::i8x4"]},{"text":"impl Mul<i8> for i8x4","synthetic":false,"types":["packed_simd::v32::i8x4"]},{"text":"impl Mul<Simd<[i8; 4]>> for i8","synthetic":false,"types":[]},{"text":"impl Mul<Simd<[u8; 4]>> for u8x4","synthetic":false,"types":["packed_simd::v32::u8x4"]},{"text":"impl Mul<u8> for u8x4","synthetic":false,"types":["packed_simd::v32::u8x4"]},{"text":"impl Mul<Simd<[u8; 4]>> for u8","synthetic":false,"types":[]},{"text":"impl Mul<Simd<[i16; 2]>> for i16x2","synthetic":false,"types":["packed_simd::v32::i16x2"]},{"text":"impl Mul<i16> for i16x2","synthetic":false,"types":["packed_simd::v32::i16x2"]},{"text":"impl Mul<Simd<[i16; 2]>> for i16","synthetic":false,"types":[]},{"text":"impl Mul<Simd<[u16; 2]>> for u16x2","synthetic":false,"types":["packed_simd::v32::u16x2"]},{"text":"impl Mul<u16> for u16x2","synthetic":false,"types":["packed_simd::v32::u16x2"]},{"text":"impl Mul<Simd<[u16; 2]>> for u16","synthetic":false,"types":[]},{"text":"impl Mul<Simd<[i8; 8]>> for i8x8","synthetic":false,"types":["packed_simd::v64::i8x8"]},{"text":"impl Mul<i8> for i8x8","synthetic":false,"types":["packed_simd::v64::i8x8"]},{"text":"impl Mul<Simd<[i8; 8]>> for i8","synthetic":false,"types":[]},{"text":"impl Mul<Simd<[u8; 8]>> for u8x8","synthetic":false,"types":["packed_simd::v64::u8x8"]},{"text":"impl Mul<u8> for u8x8","synthetic":false,"types":["packed_simd::v64::u8x8"]},{"text":"impl Mul<Simd<[u8; 8]>> for u8","synthetic":false,"types":[]},{"text":"impl Mul<Simd<[i16; 4]>> for i16x4","synthetic":false,"types":["packed_simd::v64::i16x4"]},{"text":"impl Mul<i16> for i16x4","synthetic":false,"types":["packed_simd::v64::i16x4"]},{"text":"impl Mul<Simd<[i16; 4]>> for i16","synthetic":false,"types":[]},{"text":"impl Mul<Simd<[u16; 4]>> for u16x4","synthetic":false,"types":["packed_simd::v64::u16x4"]},{"text":"impl Mul<u16> for u16x4","synthetic":false,"types":["packed_simd::v64::u16x4"]},{"text":"impl Mul<Simd<[u16; 4]>> for u16","synthetic":false,"types":[]},{"text":"impl Mul<Simd<[i32; 2]>> for i32x2","synthetic":false,"types":["packed_simd::v64::i32x2"]},{"text":"impl Mul<i32> for i32x2","synthetic":false,"types":["packed_simd::v64::i32x2"]},{"text":"impl Mul<Simd<[i32; 2]>> for i32","synthetic":false,"types":[]},{"text":"impl Mul<Simd<[u32; 2]>> for u32x2","synthetic":false,"types":["packed_simd::v64::u32x2"]},{"text":"impl Mul<u32> for u32x2","synthetic":false,"types":["packed_simd::v64::u32x2"]},{"text":"impl Mul<Simd<[u32; 2]>> for u32","synthetic":false,"types":[]},{"text":"impl Mul<Simd<[f32; 2]>> for f32x2","synthetic":false,"types":["packed_simd::v64::f32x2"]},{"text":"impl Mul<f32> for f32x2","synthetic":false,"types":["packed_simd::v64::f32x2"]},{"text":"impl Mul<Simd<[f32; 2]>> for f32","synthetic":false,"types":[]},{"text":"impl Mul<Simd<[i8; 16]>> for i8x16","synthetic":false,"types":["packed_simd::v128::i8x16"]},{"text":"impl Mul<i8> for i8x16","synthetic":false,"types":["packed_simd::v128::i8x16"]},{"text":"impl Mul<Simd<[i8; 16]>> for i8","synthetic":false,"types":[]},{"text":"impl Mul<Simd<[u8; 16]>> for u8x16","synthetic":false,"types":["packed_simd::v128::u8x16"]},{"text":"impl Mul<u8> for u8x16","synthetic":false,"types":["packed_simd::v128::u8x16"]},{"text":"impl Mul<Simd<[u8; 16]>> for u8","synthetic":false,"types":[]},{"text":"impl Mul<Simd<[i16; 8]>> for i16x8","synthetic":false,"types":["packed_simd::v128::i16x8"]},{"text":"impl Mul<i16> for i16x8","synthetic":false,"types":["packed_simd::v128::i16x8"]},{"text":"impl Mul<Simd<[i16; 8]>> for i16","synthetic":false,"types":[]},{"text":"impl Mul<Simd<[u16; 8]>> for u16x8","synthetic":false,"types":["packed_simd::v128::u16x8"]},{"text":"impl Mul<u16> for u16x8","synthetic":false,"types":["packed_simd::v128::u16x8"]},{"text":"impl Mul<Simd<[u16; 8]>> for u16","synthetic":false,"types":[]},{"text":"impl Mul<Simd<[i32; 4]>> for i32x4","synthetic":false,"types":["packed_simd::v128::i32x4"]},{"text":"impl Mul<i32> for i32x4","synthetic":false,"types":["packed_simd::v128::i32x4"]},{"text":"impl Mul<Simd<[i32; 4]>> for i32","synthetic":false,"types":[]},{"text":"impl Mul<Simd<[u32; 4]>> for u32x4","synthetic":false,"types":["packed_simd::v128::u32x4"]},{"text":"impl Mul<u32> for u32x4","synthetic":false,"types":["packed_simd::v128::u32x4"]},{"text":"impl Mul<Simd<[u32; 4]>> for u32","synthetic":false,"types":[]},{"text":"impl Mul<Simd<[f32; 4]>> for f32x4","synthetic":false,"types":["packed_simd::v128::f32x4"]},{"text":"impl Mul<f32> for f32x4","synthetic":false,"types":["packed_simd::v128::f32x4"]},{"text":"impl Mul<Simd<[f32; 4]>> for f32","synthetic":false,"types":[]},{"text":"impl Mul<Simd<[i64; 2]>> for i64x2","synthetic":false,"types":["packed_simd::v128::i64x2"]},{"text":"impl Mul<i64> for i64x2","synthetic":false,"types":["packed_simd::v128::i64x2"]},{"text":"impl Mul<Simd<[i64; 2]>> for i64","synthetic":false,"types":[]},{"text":"impl Mul<Simd<[u64; 2]>> for u64x2","synthetic":false,"types":["packed_simd::v128::u64x2"]},{"text":"impl Mul<u64> for u64x2","synthetic":false,"types":["packed_simd::v128::u64x2"]},{"text":"impl Mul<Simd<[u64; 2]>> for u64","synthetic":false,"types":[]},{"text":"impl Mul<Simd<[f64; 2]>> for f64x2","synthetic":false,"types":["packed_simd::v128::f64x2"]},{"text":"impl Mul<f64> for f64x2","synthetic":false,"types":["packed_simd::v128::f64x2"]},{"text":"impl Mul<Simd<[f64; 2]>> for f64","synthetic":false,"types":[]},{"text":"impl Mul<Simd<[i128; 1]>> for i128x1","synthetic":false,"types":["packed_simd::v128::i128x1"]},{"text":"impl Mul<i128> for i128x1","synthetic":false,"types":["packed_simd::v128::i128x1"]},{"text":"impl Mul<Simd<[i128; 1]>> for i128","synthetic":false,"types":[]},{"text":"impl Mul<Simd<[u128; 1]>> for u128x1","synthetic":false,"types":["packed_simd::v128::u128x1"]},{"text":"impl Mul<u128> for u128x1","synthetic":false,"types":["packed_simd::v128::u128x1"]},{"text":"impl Mul<Simd<[u128; 1]>> for u128","synthetic":false,"types":[]},{"text":"impl Mul<Simd<[i8; 32]>> for i8x32","synthetic":false,"types":["packed_simd::v256::i8x32"]},{"text":"impl Mul<i8> for i8x32","synthetic":false,"types":["packed_simd::v256::i8x32"]},{"text":"impl Mul<Simd<[i8; 32]>> for i8","synthetic":false,"types":[]},{"text":"impl Mul<Simd<[u8; 32]>> for u8x32","synthetic":false,"types":["packed_simd::v256::u8x32"]},{"text":"impl Mul<u8> for u8x32","synthetic":false,"types":["packed_simd::v256::u8x32"]},{"text":"impl Mul<Simd<[u8; 32]>> for u8","synthetic":false,"types":[]},{"text":"impl Mul<Simd<[i16; 16]>> for i16x16","synthetic":false,"types":["packed_simd::v256::i16x16"]},{"text":"impl Mul<i16> for i16x16","synthetic":false,"types":["packed_simd::v256::i16x16"]},{"text":"impl Mul<Simd<[i16; 16]>> for i16","synthetic":false,"types":[]},{"text":"impl Mul<Simd<[u16; 16]>> for u16x16","synthetic":false,"types":["packed_simd::v256::u16x16"]},{"text":"impl Mul<u16> for u16x16","synthetic":false,"types":["packed_simd::v256::u16x16"]},{"text":"impl Mul<Simd<[u16; 16]>> for u16","synthetic":false,"types":[]},{"text":"impl Mul<Simd<[i32; 8]>> for i32x8","synthetic":false,"types":["packed_simd::v256::i32x8"]},{"text":"impl Mul<i32> for i32x8","synthetic":false,"types":["packed_simd::v256::i32x8"]},{"text":"impl Mul<Simd<[i32; 8]>> for i32","synthetic":false,"types":[]},{"text":"impl Mul<Simd<[u32; 8]>> for u32x8","synthetic":false,"types":["packed_simd::v256::u32x8"]},{"text":"impl Mul<u32> for u32x8","synthetic":false,"types":["packed_simd::v256::u32x8"]},{"text":"impl Mul<Simd<[u32; 8]>> for u32","synthetic":false,"types":[]},{"text":"impl Mul<Simd<[f32; 8]>> for f32x8","synthetic":false,"types":["packed_simd::v256::f32x8"]},{"text":"impl Mul<f32> for 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i128x2","synthetic":false,"types":["packed_simd::v256::i128x2"]},{"text":"impl Mul<i128> for i128x2","synthetic":false,"types":["packed_simd::v256::i128x2"]},{"text":"impl Mul<Simd<[i128; 2]>> for i128","synthetic":false,"types":[]},{"text":"impl Mul<Simd<[u128; 2]>> for u128x2","synthetic":false,"types":["packed_simd::v256::u128x2"]},{"text":"impl Mul<u128> for u128x2","synthetic":false,"types":["packed_simd::v256::u128x2"]},{"text":"impl Mul<Simd<[u128; 2]>> for u128","synthetic":false,"types":[]},{"text":"impl Mul<Simd<[i8; 64]>> for i8x64","synthetic":false,"types":["packed_simd::v512::i8x64"]},{"text":"impl Mul<i8> for i8x64","synthetic":false,"types":["packed_simd::v512::i8x64"]},{"text":"impl Mul<Simd<[i8; 64]>> for i8","synthetic":false,"types":[]},{"text":"impl Mul<Simd<[u8; 64]>> for u8x64","synthetic":false,"types":["packed_simd::v512::u8x64"]},{"text":"impl Mul<u8> for u8x64","synthetic":false,"types":["packed_simd::v512::u8x64"]},{"text":"impl Mul<Simd<[u8; 64]>> for u8","synthetic":false,"types":[]},{"text":"impl Mul<Simd<[i16; 32]>> for i16x32","synthetic":false,"types":["packed_simd::v512::i16x32"]},{"text":"impl Mul<i16> for i16x32","synthetic":false,"types":["packed_simd::v512::i16x32"]},{"text":"impl Mul<Simd<[i16; 32]>> for i16","synthetic":false,"types":[]},{"text":"impl Mul<Simd<[u16; 32]>> for u16x32","synthetic":false,"types":["packed_simd::v512::u16x32"]},{"text":"impl Mul<u16> for u16x32","synthetic":false,"types":["packed_simd::v512::u16x32"]},{"text":"impl Mul<Simd<[u16; 32]>> for u16","synthetic":false,"types":[]},{"text":"impl Mul<Simd<[i32; 16]>> for i32x16","synthetic":false,"types":["packed_simd::v512::i32x16"]},{"text":"impl Mul<i32> for i32x16","synthetic":false,"types":["packed_simd::v512::i32x16"]},{"text":"impl Mul<Simd<[i32; 16]>> for i32","synthetic":false,"types":[]},{"text":"impl Mul<Simd<[u32; 16]>> for u32x16","synthetic":false,"types":["packed_simd::v512::u32x16"]},{"text":"impl Mul<u32> for u32x16","synthetic":false,"types":["packed_simd::v512::u32x16"]},{"text":"impl Mul<Simd<[u32; 16]>> for u32","synthetic":false,"types":[]},{"text":"impl Mul<Simd<[f32; 16]>> for f32x16","synthetic":false,"types":["packed_simd::v512::f32x16"]},{"text":"impl Mul<f32> for f32x16","synthetic":false,"types":["packed_simd::v512::f32x16"]},{"text":"impl Mul<Simd<[f32; 16]>> for f32","synthetic":false,"types":[]},{"text":"impl Mul<Simd<[i64; 8]>> for i64x8","synthetic":false,"types":["packed_simd::v512::i64x8"]},{"text":"impl Mul<i64> for i64x8","synthetic":false,"types":["packed_simd::v512::i64x8"]},{"text":"impl Mul<Simd<[i64; 8]>> for i64","synthetic":false,"types":[]},{"text":"impl Mul<Simd<[u64; 8]>> for u64x8","synthetic":false,"types":["packed_simd::v512::u64x8"]},{"text":"impl Mul<u64> for u64x8","synthetic":false,"types":["packed_simd::v512::u64x8"]},{"text":"impl Mul<Simd<[u64; 8]>> for u64","synthetic":false,"types":[]},{"text":"impl Mul<Simd<[f64; 8]>> for f64x8","synthetic":false,"types":["packed_simd::v512::f64x8"]},{"text":"impl Mul<f64> for f64x8","synthetic":false,"types":["packed_simd::v512::f64x8"]},{"text":"impl Mul<Simd<[f64; 8]>> for f64","synthetic":false,"types":[]},{"text":"impl Mul<Simd<[i128; 4]>> for i128x4","synthetic":false,"types":["packed_simd::v512::i128x4"]},{"text":"impl Mul<i128> for i128x4","synthetic":false,"types":["packed_simd::v512::i128x4"]},{"text":"impl Mul<Simd<[i128; 4]>> for i128","synthetic":false,"types":[]},{"text":"impl Mul<Simd<[u128; 4]>> for u128x4","synthetic":false,"types":["packed_simd::v512::u128x4"]},{"text":"impl Mul<u128> for u128x4","synthetic":false,"types":["packed_simd::v512::u128x4"]},{"text":"impl Mul<Simd<[u128; 4]>> for u128","synthetic":false,"types":[]},{"text":"impl Mul<Simd<[isize; 2]>> for isizex2","synthetic":false,"types":["packed_simd::vSize::isizex2"]},{"text":"impl Mul<isize> for isizex2","synthetic":false,"types":["packed_simd::vSize::isizex2"]},{"text":"impl Mul<Simd<[isize; 2]>> for isize","synthetic":false,"types":[]},{"text":"impl Mul<Simd<[usize; 2]>> for usizex2","synthetic":false,"types":["packed_simd::vSize::usizex2"]},{"text":"impl Mul<usize> for usizex2","synthetic":false,"types":["packed_simd::vSize::usizex2"]},{"text":"impl Mul<Simd<[usize; 2]>> for usize","synthetic":false,"types":[]},{"text":"impl Mul<Simd<[isize; 4]>> for isizex4","synthetic":false,"types":["packed_simd::vSize::isizex4"]},{"text":"impl Mul<isize> for isizex4","synthetic":false,"types":["packed_simd::vSize::isizex4"]},{"text":"impl Mul<Simd<[isize; 4]>> for isize","synthetic":false,"types":[]},{"text":"impl Mul<Simd<[usize; 4]>> for usizex4","synthetic":false,"types":["packed_simd::vSize::usizex4"]},{"text":"impl Mul<usize> for usizex4","synthetic":false,"types":["packed_simd::vSize::usizex4"]},{"text":"impl Mul<Simd<[usize; 4]>> for usize","synthetic":false,"types":[]},{"text":"impl Mul<Simd<[isize; 8]>> for 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100644 index 000000000..666f43eed --- /dev/null +++ b/implementors/core/ops/arith/trait.Neg.js @@ -0,0 +1,3 @@ +(function() {var implementors = {}; +implementors["packed_simd"] = [{"text":"impl Neg for i8x2","synthetic":false,"types":["packed_simd::v16::i8x2"]},{"text":"impl Neg for i8x4","synthetic":false,"types":["packed_simd::v32::i8x4"]},{"text":"impl Neg for i16x2","synthetic":false,"types":["packed_simd::v32::i16x2"]},{"text":"impl Neg for i8x8","synthetic":false,"types":["packed_simd::v64::i8x8"]},{"text":"impl Neg for i16x4","synthetic":false,"types":["packed_simd::v64::i16x4"]},{"text":"impl Neg for i32x2","synthetic":false,"types":["packed_simd::v64::i32x2"]},{"text":"impl Neg for f32x2","synthetic":false,"types":["packed_simd::v64::f32x2"]},{"text":"impl Neg for i8x16","synthetic":false,"types":["packed_simd::v128::i8x16"]},{"text":"impl Neg for i16x8","synthetic":false,"types":["packed_simd::v128::i16x8"]},{"text":"impl Neg for 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{window.register_implementors(implementors);} else {window.pending_implementors = implementors;}})() \ No newline at end of file diff --git a/implementors/core/ops/arith/trait.Rem.js b/implementors/core/ops/arith/trait.Rem.js new file mode 100644 index 000000000..4d903342f --- /dev/null +++ b/implementors/core/ops/arith/trait.Rem.js @@ -0,0 +1,3 @@ +(function() {var implementors = {}; +implementors["packed_simd"] = [{"text":"impl Rem<Simd<[i8; 2]>> for i8x2","synthetic":false,"types":["packed_simd::v16::i8x2"]},{"text":"impl Rem<i8> for i8x2","synthetic":false,"types":["packed_simd::v16::i8x2"]},{"text":"impl Rem<Simd<[i8; 2]>> for i8","synthetic":false,"types":[]},{"text":"impl Rem<Simd<[u8; 2]>> for u8x2","synthetic":false,"types":["packed_simd::v16::u8x2"]},{"text":"impl Rem<u8> for u8x2","synthetic":false,"types":["packed_simd::v16::u8x2"]},{"text":"impl Rem<Simd<[u8; 2]>> for u8","synthetic":false,"types":[]},{"text":"impl Rem<Simd<[i8; 4]>> for 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isizex8","synthetic":false,"types":["packed_simd::vSize::isizex8"]},{"text":"impl Rem<isize> for isizex8","synthetic":false,"types":["packed_simd::vSize::isizex8"]},{"text":"impl Rem<Simd<[isize; 8]>> for isize","synthetic":false,"types":[]},{"text":"impl Rem<Simd<[usize; 8]>> for usizex8","synthetic":false,"types":["packed_simd::vSize::usizex8"]},{"text":"impl Rem<usize> for usizex8","synthetic":false,"types":["packed_simd::vSize::usizex8"]},{"text":"impl Rem<Simd<[usize; 8]>> for usize","synthetic":false,"types":[]}]; +if (window.register_implementors) {window.register_implementors(implementors);} else {window.pending_implementors = implementors;}})() \ No newline at end of file diff --git a/implementors/core/ops/arith/trait.RemAssign.js b/implementors/core/ops/arith/trait.RemAssign.js new file mode 100644 index 000000000..5164e3789 --- /dev/null +++ b/implementors/core/ops/arith/trait.RemAssign.js @@ -0,0 +1,3 @@ +(function() {var implementors = {}; +implementors["packed_simd"] = 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i128x4","synthetic":false,"types":["packed_simd::v512::i128x4"]},{"text":"impl RemAssign<i128> for i128x4","synthetic":false,"types":["packed_simd::v512::i128x4"]},{"text":"impl RemAssign<Simd<[u128; 4]>> for u128x4","synthetic":false,"types":["packed_simd::v512::u128x4"]},{"text":"impl RemAssign<u128> for u128x4","synthetic":false,"types":["packed_simd::v512::u128x4"]},{"text":"impl RemAssign<Simd<[isize; 2]>> for isizex2","synthetic":false,"types":["packed_simd::vSize::isizex2"]},{"text":"impl RemAssign<isize> for isizex2","synthetic":false,"types":["packed_simd::vSize::isizex2"]},{"text":"impl RemAssign<Simd<[usize; 2]>> for usizex2","synthetic":false,"types":["packed_simd::vSize::usizex2"]},{"text":"impl RemAssign<usize> for usizex2","synthetic":false,"types":["packed_simd::vSize::usizex2"]},{"text":"impl RemAssign<Simd<[isize; 4]>> for isizex4","synthetic":false,"types":["packed_simd::vSize::isizex4"]},{"text":"impl RemAssign<isize> for isizex4","synthetic":false,"types":["packed_simd::vSize::isizex4"]},{"text":"impl RemAssign<Simd<[usize; 4]>> for usizex4","synthetic":false,"types":["packed_simd::vSize::usizex4"]},{"text":"impl RemAssign<usize> for usizex4","synthetic":false,"types":["packed_simd::vSize::usizex4"]},{"text":"impl RemAssign<Simd<[isize; 8]>> for isizex8","synthetic":false,"types":["packed_simd::vSize::isizex8"]},{"text":"impl RemAssign<isize> for isizex8","synthetic":false,"types":["packed_simd::vSize::isizex8"]},{"text":"impl RemAssign<Simd<[usize; 8]>> for usizex8","synthetic":false,"types":["packed_simd::vSize::usizex8"]},{"text":"impl RemAssign<usize> for usizex8","synthetic":false,"types":["packed_simd::vSize::usizex8"]}]; +if (window.register_implementors) {window.register_implementors(implementors);} else {window.pending_implementors = implementors;}})() \ No newline at end of file diff --git a/implementors/core/ops/arith/trait.Sub.js b/implementors/core/ops/arith/trait.Sub.js new file mode 100644 index 000000000..4f41d07b9 --- /dev/null +++ b/implementors/core/ops/arith/trait.Sub.js @@ -0,0 +1,3 @@ +(function() {var implementors = {}; +implementors["packed_simd"] = [{"text":"impl Sub<Simd<[i8; 2]>> for i8x2","synthetic":false,"types":["packed_simd::v16::i8x2"]},{"text":"impl Sub<i8> for i8x2","synthetic":false,"types":["packed_simd::v16::i8x2"]},{"text":"impl Sub<Simd<[i8; 2]>> for i8","synthetic":false,"types":[]},{"text":"impl Sub<Simd<[u8; 2]>> for u8x2","synthetic":false,"types":["packed_simd::v16::u8x2"]},{"text":"impl Sub<u8> for u8x2","synthetic":false,"types":["packed_simd::v16::u8x2"]},{"text":"impl Sub<Simd<[u8; 2]>> for u8","synthetic":false,"types":[]},{"text":"impl Sub<Simd<[i8; 4]>> for i8x4","synthetic":false,"types":["packed_simd::v32::i8x4"]},{"text":"impl Sub<i8> for i8x4","synthetic":false,"types":["packed_simd::v32::i8x4"]},{"text":"impl Sub<Simd<[i8; 4]>> for i8","synthetic":false,"types":[]},{"text":"impl Sub<Simd<[u8; 4]>> for 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isize","synthetic":false,"types":[]},{"text":"impl Sub<Simd<[usize; 8]>> for usizex8","synthetic":false,"types":["packed_simd::vSize::usizex8"]},{"text":"impl Sub<usize> for usizex8","synthetic":false,"types":["packed_simd::vSize::usizex8"]},{"text":"impl Sub<Simd<[usize; 8]>> for usize","synthetic":false,"types":[]}]; +if (window.register_implementors) {window.register_implementors(implementors);} else {window.pending_implementors = implementors;}})() \ No newline at end of file diff --git a/implementors/core/ops/arith/trait.SubAssign.js b/implementors/core/ops/arith/trait.SubAssign.js new file mode 100644 index 000000000..ac4e77ced --- /dev/null +++ b/implementors/core/ops/arith/trait.SubAssign.js @@ -0,0 +1,3 @@ +(function() {var implementors = {}; +implementors["packed_simd"] = [{"text":"impl SubAssign<Simd<[i8; 2]>> for i8x2","synthetic":false,"types":["packed_simd::v16::i8x2"]},{"text":"impl SubAssign<i8> for i8x2","synthetic":false,"types":["packed_simd::v16::i8x2"]},{"text":"impl SubAssign<Simd<[u8; 2]>> for u8x2","synthetic":false,"types":["packed_simd::v16::u8x2"]},{"text":"impl SubAssign<u8> for u8x2","synthetic":false,"types":["packed_simd::v16::u8x2"]},{"text":"impl SubAssign<Simd<[i8; 4]>> for i8x4","synthetic":false,"types":["packed_simd::v32::i8x4"]},{"text":"impl SubAssign<i8> for i8x4","synthetic":false,"types":["packed_simd::v32::i8x4"]},{"text":"impl SubAssign<Simd<[u8; 4]>> for u8x4","synthetic":false,"types":["packed_simd::v32::u8x4"]},{"text":"impl SubAssign<u8> for u8x4","synthetic":false,"types":["packed_simd::v32::u8x4"]},{"text":"impl SubAssign<Simd<[i16; 2]>> for i16x2","synthetic":false,"types":["packed_simd::v32::i16x2"]},{"text":"impl SubAssign<i16> for i16x2","synthetic":false,"types":["packed_simd::v32::i16x2"]},{"text":"impl SubAssign<Simd<[u16; 2]>> for u16x2","synthetic":false,"types":["packed_simd::v32::u16x2"]},{"text":"impl SubAssign<u16> for u16x2","synthetic":false,"types":["packed_simd::v32::u16x2"]},{"text":"impl SubAssign<Simd<[i8; 8]>> for i8x8","synthetic":false,"types":["packed_simd::v64::i8x8"]},{"text":"impl SubAssign<i8> for i8x8","synthetic":false,"types":["packed_simd::v64::i8x8"]},{"text":"impl SubAssign<Simd<[u8; 8]>> for u8x8","synthetic":false,"types":["packed_simd::v64::u8x8"]},{"text":"impl SubAssign<u8> for u8x8","synthetic":false,"types":["packed_simd::v64::u8x8"]},{"text":"impl SubAssign<Simd<[i16; 4]>> for i16x4","synthetic":false,"types":["packed_simd::v64::i16x4"]},{"text":"impl SubAssign<i16> for i16x4","synthetic":false,"types":["packed_simd::v64::i16x4"]},{"text":"impl SubAssign<Simd<[u16; 4]>> for u16x4","synthetic":false,"types":["packed_simd::v64::u16x4"]},{"text":"impl SubAssign<u16> for u16x4","synthetic":false,"types":["packed_simd::v64::u16x4"]},{"text":"impl SubAssign<Simd<[i32; 2]>> for i32x2","synthetic":false,"types":["packed_simd::v64::i32x2"]},{"text":"impl SubAssign<i32> for i32x2","synthetic":false,"types":["packed_simd::v64::i32x2"]},{"text":"impl SubAssign<Simd<[u32; 2]>> for u32x2","synthetic":false,"types":["packed_simd::v64::u32x2"]},{"text":"impl SubAssign<u32> for u32x2","synthetic":false,"types":["packed_simd::v64::u32x2"]},{"text":"impl SubAssign<Simd<[f32; 2]>> for f32x2","synthetic":false,"types":["packed_simd::v64::f32x2"]},{"text":"impl SubAssign<f32> for f32x2","synthetic":false,"types":["packed_simd::v64::f32x2"]},{"text":"impl SubAssign<Simd<[i8; 16]>> for i8x16","synthetic":false,"types":["packed_simd::v128::i8x16"]},{"text":"impl SubAssign<i8> for i8x16","synthetic":false,"types":["packed_simd::v128::i8x16"]},{"text":"impl SubAssign<Simd<[u8; 16]>> for u8x16","synthetic":false,"types":["packed_simd::v128::u8x16"]},{"text":"impl SubAssign<u8> for u8x16","synthetic":false,"types":["packed_simd::v128::u8x16"]},{"text":"impl SubAssign<Simd<[i16; 8]>> for i16x8","synthetic":false,"types":["packed_simd::v128::i16x8"]},{"text":"impl SubAssign<i16> for i16x8","synthetic":false,"types":["packed_simd::v128::i16x8"]},{"text":"impl SubAssign<Simd<[u16; 8]>> for u16x8","synthetic":false,"types":["packed_simd::v128::u16x8"]},{"text":"impl SubAssign<u16> for u16x8","synthetic":false,"types":["packed_simd::v128::u16x8"]},{"text":"impl SubAssign<Simd<[i32; 4]>> for i32x4","synthetic":false,"types":["packed_simd::v128::i32x4"]},{"text":"impl SubAssign<i32> for i32x4","synthetic":false,"types":["packed_simd::v128::i32x4"]},{"text":"impl SubAssign<Simd<[u32; 4]>> for u32x4","synthetic":false,"types":["packed_simd::v128::u32x4"]},{"text":"impl SubAssign<u32> for u32x4","synthetic":false,"types":["packed_simd::v128::u32x4"]},{"text":"impl SubAssign<Simd<[f32; 4]>> for f32x4","synthetic":false,"types":["packed_simd::v128::f32x4"]},{"text":"impl SubAssign<f32> for f32x4","synthetic":false,"types":["packed_simd::v128::f32x4"]},{"text":"impl SubAssign<Simd<[i64; 2]>> for i64x2","synthetic":false,"types":["packed_simd::v128::i64x2"]},{"text":"impl SubAssign<i64> for i64x2","synthetic":false,"types":["packed_simd::v128::i64x2"]},{"text":"impl SubAssign<Simd<[u64; 2]>> for u64x2","synthetic":false,"types":["packed_simd::v128::u64x2"]},{"text":"impl SubAssign<u64> for u64x2","synthetic":false,"types":["packed_simd::v128::u64x2"]},{"text":"impl SubAssign<Simd<[f64; 2]>> for f64x2","synthetic":false,"types":["packed_simd::v128::f64x2"]},{"text":"impl SubAssign<f64> for f64x2","synthetic":false,"types":["packed_simd::v128::f64x2"]},{"text":"impl SubAssign<Simd<[i128; 1]>> for i128x1","synthetic":false,"types":["packed_simd::v128::i128x1"]},{"text":"impl SubAssign<i128> for i128x1","synthetic":false,"types":["packed_simd::v128::i128x1"]},{"text":"impl SubAssign<Simd<[u128; 1]>> for u128x1","synthetic":false,"types":["packed_simd::v128::u128x1"]},{"text":"impl SubAssign<u128> for u128x1","synthetic":false,"types":["packed_simd::v128::u128x1"]},{"text":"impl SubAssign<Simd<[i8; 32]>> for i8x32","synthetic":false,"types":["packed_simd::v256::i8x32"]},{"text":"impl SubAssign<i8> for i8x32","synthetic":false,"types":["packed_simd::v256::i8x32"]},{"text":"impl SubAssign<Simd<[u8; 32]>> for u8x32","synthetic":false,"types":["packed_simd::v256::u8x32"]},{"text":"impl SubAssign<u8> for u8x32","synthetic":false,"types":["packed_simd::v256::u8x32"]},{"text":"impl SubAssign<Simd<[i16; 16]>> for i16x16","synthetic":false,"types":["packed_simd::v256::i16x16"]},{"text":"impl SubAssign<i16> for i16x16","synthetic":false,"types":["packed_simd::v256::i16x16"]},{"text":"impl SubAssign<Simd<[u16; 16]>> for u16x16","synthetic":false,"types":["packed_simd::v256::u16x16"]},{"text":"impl SubAssign<u16> for u16x16","synthetic":false,"types":["packed_simd::v256::u16x16"]},{"text":"impl SubAssign<Simd<[i32; 8]>> for i32x8","synthetic":false,"types":["packed_simd::v256::i32x8"]},{"text":"impl SubAssign<i32> for i32x8","synthetic":false,"types":["packed_simd::v256::i32x8"]},{"text":"impl SubAssign<Simd<[u32; 8]>> for u32x8","synthetic":false,"types":["packed_simd::v256::u32x8"]},{"text":"impl SubAssign<u32> for u32x8","synthetic":false,"types":["packed_simd::v256::u32x8"]},{"text":"impl SubAssign<Simd<[f32; 8]>> for f32x8","synthetic":false,"types":["packed_simd::v256::f32x8"]},{"text":"impl SubAssign<f32> for f32x8","synthetic":false,"types":["packed_simd::v256::f32x8"]},{"text":"impl SubAssign<Simd<[i64; 4]>> for i64x4","synthetic":false,"types":["packed_simd::v256::i64x4"]},{"text":"impl SubAssign<i64> for i64x4","synthetic":false,"types":["packed_simd::v256::i64x4"]},{"text":"impl SubAssign<Simd<[u64; 4]>> for u64x4","synthetic":false,"types":["packed_simd::v256::u64x4"]},{"text":"impl SubAssign<u64> for u64x4","synthetic":false,"types":["packed_simd::v256::u64x4"]},{"text":"impl SubAssign<Simd<[f64; 4]>> for f64x4","synthetic":false,"types":["packed_simd::v256::f64x4"]},{"text":"impl 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u128x4","synthetic":false,"types":["packed_simd::v512::u128x4"]},{"text":"impl SubAssign<u128> for u128x4","synthetic":false,"types":["packed_simd::v512::u128x4"]},{"text":"impl SubAssign<Simd<[isize; 2]>> for isizex2","synthetic":false,"types":["packed_simd::vSize::isizex2"]},{"text":"impl SubAssign<isize> for isizex2","synthetic":false,"types":["packed_simd::vSize::isizex2"]},{"text":"impl SubAssign<Simd<[usize; 2]>> for usizex2","synthetic":false,"types":["packed_simd::vSize::usizex2"]},{"text":"impl SubAssign<usize> for usizex2","synthetic":false,"types":["packed_simd::vSize::usizex2"]},{"text":"impl SubAssign<Simd<[isize; 4]>> for isizex4","synthetic":false,"types":["packed_simd::vSize::isizex4"]},{"text":"impl SubAssign<isize> for isizex4","synthetic":false,"types":["packed_simd::vSize::isizex4"]},{"text":"impl SubAssign<Simd<[usize; 4]>> for usizex4","synthetic":false,"types":["packed_simd::vSize::usizex4"]},{"text":"impl SubAssign<usize> for usizex4","synthetic":false,"types":["packed_simd::vSize::usizex4"]},{"text":"impl SubAssign<Simd<[isize; 8]>> for isizex8","synthetic":false,"types":["packed_simd::vSize::isizex8"]},{"text":"impl SubAssign<isize> for isizex8","synthetic":false,"types":["packed_simd::vSize::isizex8"]},{"text":"impl SubAssign<Simd<[usize; 8]>> for usizex8","synthetic":false,"types":["packed_simd::vSize::usizex8"]},{"text":"impl SubAssign<usize> for usizex8","synthetic":false,"types":["packed_simd::vSize::usizex8"]}]; +if (window.register_implementors) {window.register_implementors(implementors);} else {window.pending_implementors = implementors;}})() \ No newline at end of file diff --git a/implementors/core/ops/bit/trait.BitAnd.js b/implementors/core/ops/bit/trait.BitAnd.js new file mode 100644 index 000000000..23d46c43a --- /dev/null +++ b/implementors/core/ops/bit/trait.BitAnd.js @@ -0,0 +1,3 @@ +(function() {var implementors = {}; +implementors["packed_simd"] = [{"text":"impl BitAnd<Simd<[i8; 2]>> for i8x2","synthetic":false,"types":["packed_simd::v16::i8x2"]},{"text":"impl BitAnd<i8> for i8x2","synthetic":false,"types":["packed_simd::v16::i8x2"]},{"text":"impl BitAnd<Simd<[i8; 2]>> for i8","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[u8; 2]>> for u8x2","synthetic":false,"types":["packed_simd::v16::u8x2"]},{"text":"impl BitAnd<u8> for u8x2","synthetic":false,"types":["packed_simd::v16::u8x2"]},{"text":"impl BitAnd<Simd<[u8; 2]>> for u8","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[m8; 2]>> for m8x2","synthetic":false,"types":["packed_simd::v16::m8x2"]},{"text":"impl BitAnd<bool> for m8x2","synthetic":false,"types":["packed_simd::v16::m8x2"]},{"text":"impl BitAnd<Simd<[m8; 2]>> for bool","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[i8; 4]>> for i8x4","synthetic":false,"types":["packed_simd::v32::i8x4"]},{"text":"impl BitAnd<i8> for i8x4","synthetic":false,"types":["packed_simd::v32::i8x4"]},{"text":"impl BitAnd<Simd<[i8; 4]>> for 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4]>> for bool","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[i32; 2]>> for i32x2","synthetic":false,"types":["packed_simd::v64::i32x2"]},{"text":"impl BitAnd<i32> for i32x2","synthetic":false,"types":["packed_simd::v64::i32x2"]},{"text":"impl BitAnd<Simd<[i32; 2]>> for i32","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[u32; 2]>> for u32x2","synthetic":false,"types":["packed_simd::v64::u32x2"]},{"text":"impl BitAnd<u32> for u32x2","synthetic":false,"types":["packed_simd::v64::u32x2"]},{"text":"impl BitAnd<Simd<[u32; 2]>> for u32","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[m32; 2]>> for m32x2","synthetic":false,"types":["packed_simd::v64::m32x2"]},{"text":"impl BitAnd<bool> for m32x2","synthetic":false,"types":["packed_simd::v64::m32x2"]},{"text":"impl BitAnd<Simd<[m32; 2]>> for bool","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[i8; 16]>> for i8x16","synthetic":false,"types":["packed_simd::v128::i8x16"]},{"text":"impl BitAnd<i8> for i8x16","synthetic":false,"types":["packed_simd::v128::i8x16"]},{"text":"impl BitAnd<Simd<[i8; 16]>> for i8","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[u8; 16]>> for u8x16","synthetic":false,"types":["packed_simd::v128::u8x16"]},{"text":"impl BitAnd<u8> for u8x16","synthetic":false,"types":["packed_simd::v128::u8x16"]},{"text":"impl BitAnd<Simd<[u8; 16]>> for u8","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[m8; 16]>> for m8x16","synthetic":false,"types":["packed_simd::v128::m8x16"]},{"text":"impl BitAnd<bool> for m8x16","synthetic":false,"types":["packed_simd::v128::m8x16"]},{"text":"impl BitAnd<Simd<[m8; 16]>> for bool","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[i16; 8]>> for i16x8","synthetic":false,"types":["packed_simd::v128::i16x8"]},{"text":"impl BitAnd<i16> for i16x8","synthetic":false,"types":["packed_simd::v128::i16x8"]},{"text":"impl BitAnd<Simd<[i16; 8]>> for i16","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[u16; 8]>> for u16x8","synthetic":false,"types":["packed_simd::v128::u16x8"]},{"text":"impl BitAnd<u16> for u16x8","synthetic":false,"types":["packed_simd::v128::u16x8"]},{"text":"impl BitAnd<Simd<[u16; 8]>> for u16","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[m16; 8]>> for m16x8","synthetic":false,"types":["packed_simd::v128::m16x8"]},{"text":"impl BitAnd<bool> for m16x8","synthetic":false,"types":["packed_simd::v128::m16x8"]},{"text":"impl BitAnd<Simd<[m16; 8]>> for bool","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[i32; 4]>> for i32x4","synthetic":false,"types":["packed_simd::v128::i32x4"]},{"text":"impl BitAnd<i32> for i32x4","synthetic":false,"types":["packed_simd::v128::i32x4"]},{"text":"impl BitAnd<Simd<[i32; 4]>> for i32","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[u32; 4]>> for u32x4","synthetic":false,"types":["packed_simd::v128::u32x4"]},{"text":"impl BitAnd<u32> for u32x4","synthetic":false,"types":["packed_simd::v128::u32x4"]},{"text":"impl BitAnd<Simd<[u32; 4]>> for u32","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[m32; 4]>> for m32x4","synthetic":false,"types":["packed_simd::v128::m32x4"]},{"text":"impl BitAnd<bool> for m32x4","synthetic":false,"types":["packed_simd::v128::m32x4"]},{"text":"impl BitAnd<Simd<[m32; 4]>> for bool","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[i64; 2]>> for i64x2","synthetic":false,"types":["packed_simd::v128::i64x2"]},{"text":"impl BitAnd<i64> for i64x2","synthetic":false,"types":["packed_simd::v128::i64x2"]},{"text":"impl BitAnd<Simd<[i64; 2]>> for i64","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[u64; 2]>> for u64x2","synthetic":false,"types":["packed_simd::v128::u64x2"]},{"text":"impl BitAnd<u64> for u64x2","synthetic":false,"types":["packed_simd::v128::u64x2"]},{"text":"impl BitAnd<Simd<[u64; 2]>> for u64","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[m64; 2]>> for m64x2","synthetic":false,"types":["packed_simd::v128::m64x2"]},{"text":"impl BitAnd<bool> for m64x2","synthetic":false,"types":["packed_simd::v128::m64x2"]},{"text":"impl BitAnd<Simd<[m64; 2]>> for bool","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[i128; 1]>> for i128x1","synthetic":false,"types":["packed_simd::v128::i128x1"]},{"text":"impl BitAnd<i128> for i128x1","synthetic":false,"types":["packed_simd::v128::i128x1"]},{"text":"impl BitAnd<Simd<[i128; 1]>> for i128","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[u128; 1]>> for u128x1","synthetic":false,"types":["packed_simd::v128::u128x1"]},{"text":"impl BitAnd<u128> for u128x1","synthetic":false,"types":["packed_simd::v128::u128x1"]},{"text":"impl BitAnd<Simd<[u128; 1]>> for u128","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[m128; 1]>> for m128x1","synthetic":false,"types":["packed_simd::v128::m128x1"]},{"text":"impl BitAnd<bool> for m128x1","synthetic":false,"types":["packed_simd::v128::m128x1"]},{"text":"impl BitAnd<Simd<[m128; 1]>> for bool","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[i8; 32]>> for i8x32","synthetic":false,"types":["packed_simd::v256::i8x32"]},{"text":"impl BitAnd<i8> for i8x32","synthetic":false,"types":["packed_simd::v256::i8x32"]},{"text":"impl BitAnd<Simd<[i8; 32]>> for i8","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[u8; 32]>> for u8x32","synthetic":false,"types":["packed_simd::v256::u8x32"]},{"text":"impl BitAnd<u8> for u8x32","synthetic":false,"types":["packed_simd::v256::u8x32"]},{"text":"impl BitAnd<Simd<[u8; 32]>> for u8","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[m8; 32]>> for m8x32","synthetic":false,"types":["packed_simd::v256::m8x32"]},{"text":"impl BitAnd<bool> for m8x32","synthetic":false,"types":["packed_simd::v256::m8x32"]},{"text":"impl BitAnd<Simd<[m8; 32]>> for bool","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[i16; 16]>> for i16x16","synthetic":false,"types":["packed_simd::v256::i16x16"]},{"text":"impl BitAnd<i16> for i16x16","synthetic":false,"types":["packed_simd::v256::i16x16"]},{"text":"impl BitAnd<Simd<[i16; 16]>> for i16","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[u16; 16]>> for u16x16","synthetic":false,"types":["packed_simd::v256::u16x16"]},{"text":"impl BitAnd<u16> for u16x16","synthetic":false,"types":["packed_simd::v256::u16x16"]},{"text":"impl BitAnd<Simd<[u16; 16]>> for u16","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[m16; 16]>> for m16x16","synthetic":false,"types":["packed_simd::v256::m16x16"]},{"text":"impl BitAnd<bool> for m16x16","synthetic":false,"types":["packed_simd::v256::m16x16"]},{"text":"impl BitAnd<Simd<[m16; 16]>> for bool","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[i32; 8]>> for i32x8","synthetic":false,"types":["packed_simd::v256::i32x8"]},{"text":"impl BitAnd<i32> for i32x8","synthetic":false,"types":["packed_simd::v256::i32x8"]},{"text":"impl BitAnd<Simd<[i32; 8]>> for i32","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[u32; 8]>> for u32x8","synthetic":false,"types":["packed_simd::v256::u32x8"]},{"text":"impl BitAnd<u32> for u32x8","synthetic":false,"types":["packed_simd::v256::u32x8"]},{"text":"impl BitAnd<Simd<[u32; 8]>> for u32","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[m32; 8]>> for m32x8","synthetic":false,"types":["packed_simd::v256::m32x8"]},{"text":"impl BitAnd<bool> for m32x8","synthetic":false,"types":["packed_simd::v256::m32x8"]},{"text":"impl BitAnd<Simd<[m32; 8]>> for bool","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[i64; 4]>> for i64x4","synthetic":false,"types":["packed_simd::v256::i64x4"]},{"text":"impl BitAnd<i64> for i64x4","synthetic":false,"types":["packed_simd::v256::i64x4"]},{"text":"impl BitAnd<Simd<[i64; 4]>> for i64","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[u64; 4]>> for u64x4","synthetic":false,"types":["packed_simd::v256::u64x4"]},{"text":"impl BitAnd<u64> for u64x4","synthetic":false,"types":["packed_simd::v256::u64x4"]},{"text":"impl BitAnd<Simd<[u64; 4]>> for u64","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[m64; 4]>> for m64x4","synthetic":false,"types":["packed_simd::v256::m64x4"]},{"text":"impl BitAnd<bool> for m64x4","synthetic":false,"types":["packed_simd::v256::m64x4"]},{"text":"impl BitAnd<Simd<[m64; 4]>> for bool","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[i128; 2]>> for i128x2","synthetic":false,"types":["packed_simd::v256::i128x2"]},{"text":"impl BitAnd<i128> for i128x2","synthetic":false,"types":["packed_simd::v256::i128x2"]},{"text":"impl BitAnd<Simd<[i128; 2]>> for i128","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[u128; 2]>> for u128x2","synthetic":false,"types":["packed_simd::v256::u128x2"]},{"text":"impl BitAnd<u128> for u128x2","synthetic":false,"types":["packed_simd::v256::u128x2"]},{"text":"impl BitAnd<Simd<[u128; 2]>> for u128","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[m128; 2]>> for m128x2","synthetic":false,"types":["packed_simd::v256::m128x2"]},{"text":"impl BitAnd<bool> for m128x2","synthetic":false,"types":["packed_simd::v256::m128x2"]},{"text":"impl BitAnd<Simd<[m128; 2]>> for bool","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[i8; 64]>> for i8x64","synthetic":false,"types":["packed_simd::v512::i8x64"]},{"text":"impl BitAnd<i8> for i8x64","synthetic":false,"types":["packed_simd::v512::i8x64"]},{"text":"impl BitAnd<Simd<[i8; 64]>> for i8","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[u8; 64]>> for u8x64","synthetic":false,"types":["packed_simd::v512::u8x64"]},{"text":"impl BitAnd<u8> for u8x64","synthetic":false,"types":["packed_simd::v512::u8x64"]},{"text":"impl BitAnd<Simd<[u8; 64]>> for u8","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[m8; 64]>> for m8x64","synthetic":false,"types":["packed_simd::v512::m8x64"]},{"text":"impl BitAnd<bool> for m8x64","synthetic":false,"types":["packed_simd::v512::m8x64"]},{"text":"impl BitAnd<Simd<[m8; 64]>> for bool","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[i16; 32]>> for i16x32","synthetic":false,"types":["packed_simd::v512::i16x32"]},{"text":"impl BitAnd<i16> for i16x32","synthetic":false,"types":["packed_simd::v512::i16x32"]},{"text":"impl BitAnd<Simd<[i16; 32]>> for i16","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[u16; 32]>> for u16x32","synthetic":false,"types":["packed_simd::v512::u16x32"]},{"text":"impl BitAnd<u16> for u16x32","synthetic":false,"types":["packed_simd::v512::u16x32"]},{"text":"impl BitAnd<Simd<[u16; 32]>> for u16","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[m16; 32]>> for m16x32","synthetic":false,"types":["packed_simd::v512::m16x32"]},{"text":"impl BitAnd<bool> for m16x32","synthetic":false,"types":["packed_simd::v512::m16x32"]},{"text":"impl BitAnd<Simd<[m16; 32]>> for bool","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[i32; 16]>> for i32x16","synthetic":false,"types":["packed_simd::v512::i32x16"]},{"text":"impl BitAnd<i32> for i32x16","synthetic":false,"types":["packed_simd::v512::i32x16"]},{"text":"impl BitAnd<Simd<[i32; 16]>> for i32","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[u32; 16]>> for u32x16","synthetic":false,"types":["packed_simd::v512::u32x16"]},{"text":"impl BitAnd<u32> for u32x16","synthetic":false,"types":["packed_simd::v512::u32x16"]},{"text":"impl BitAnd<Simd<[u32; 16]>> for u32","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[m32; 16]>> for m32x16","synthetic":false,"types":["packed_simd::v512::m32x16"]},{"text":"impl BitAnd<bool> for m32x16","synthetic":false,"types":["packed_simd::v512::m32x16"]},{"text":"impl BitAnd<Simd<[m32; 16]>> for bool","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[i64; 8]>> for i64x8","synthetic":false,"types":["packed_simd::v512::i64x8"]},{"text":"impl BitAnd<i64> for i64x8","synthetic":false,"types":["packed_simd::v512::i64x8"]},{"text":"impl BitAnd<Simd<[i64; 8]>> for i64","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[u64; 8]>> for u64x8","synthetic":false,"types":["packed_simd::v512::u64x8"]},{"text":"impl BitAnd<u64> for u64x8","synthetic":false,"types":["packed_simd::v512::u64x8"]},{"text":"impl BitAnd<Simd<[u64; 8]>> for u64","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[m64; 8]>> for m64x8","synthetic":false,"types":["packed_simd::v512::m64x8"]},{"text":"impl BitAnd<bool> for m64x8","synthetic":false,"types":["packed_simd::v512::m64x8"]},{"text":"impl BitAnd<Simd<[m64; 8]>> for bool","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[i128; 4]>> for i128x4","synthetic":false,"types":["packed_simd::v512::i128x4"]},{"text":"impl BitAnd<i128> for i128x4","synthetic":false,"types":["packed_simd::v512::i128x4"]},{"text":"impl BitAnd<Simd<[i128; 4]>> for i128","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[u128; 4]>> for u128x4","synthetic":false,"types":["packed_simd::v512::u128x4"]},{"text":"impl BitAnd<u128> for u128x4","synthetic":false,"types":["packed_simd::v512::u128x4"]},{"text":"impl BitAnd<Simd<[u128; 4]>> for u128","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[m128; 4]>> for m128x4","synthetic":false,"types":["packed_simd::v512::m128x4"]},{"text":"impl BitAnd<bool> for m128x4","synthetic":false,"types":["packed_simd::v512::m128x4"]},{"text":"impl BitAnd<Simd<[m128; 4]>> for bool","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[isize; 2]>> for isizex2","synthetic":false,"types":["packed_simd::vSize::isizex2"]},{"text":"impl BitAnd<isize> for isizex2","synthetic":false,"types":["packed_simd::vSize::isizex2"]},{"text":"impl BitAnd<Simd<[isize; 2]>> for isize","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[usize; 2]>> for usizex2","synthetic":false,"types":["packed_simd::vSize::usizex2"]},{"text":"impl BitAnd<usize> for usizex2","synthetic":false,"types":["packed_simd::vSize::usizex2"]},{"text":"impl BitAnd<Simd<[usize; 2]>> for usize","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[msize; 2]>> for msizex2","synthetic":false,"types":["packed_simd::vSize::msizex2"]},{"text":"impl BitAnd<bool> for msizex2","synthetic":false,"types":["packed_simd::vSize::msizex2"]},{"text":"impl BitAnd<Simd<[msize; 2]>> for bool","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[isize; 4]>> for isizex4","synthetic":false,"types":["packed_simd::vSize::isizex4"]},{"text":"impl BitAnd<isize> for isizex4","synthetic":false,"types":["packed_simd::vSize::isizex4"]},{"text":"impl BitAnd<Simd<[isize; 4]>> for isize","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[usize; 4]>> for usizex4","synthetic":false,"types":["packed_simd::vSize::usizex4"]},{"text":"impl BitAnd<usize> for usizex4","synthetic":false,"types":["packed_simd::vSize::usizex4"]},{"text":"impl BitAnd<Simd<[usize; 4]>> for usize","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[msize; 4]>> for msizex4","synthetic":false,"types":["packed_simd::vSize::msizex4"]},{"text":"impl BitAnd<bool> for msizex4","synthetic":false,"types":["packed_simd::vSize::msizex4"]},{"text":"impl BitAnd<Simd<[msize; 4]>> for bool","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[isize; 8]>> for isizex8","synthetic":false,"types":["packed_simd::vSize::isizex8"]},{"text":"impl BitAnd<isize> for isizex8","synthetic":false,"types":["packed_simd::vSize::isizex8"]},{"text":"impl BitAnd<Simd<[isize; 8]>> for isize","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[usize; 8]>> for usizex8","synthetic":false,"types":["packed_simd::vSize::usizex8"]},{"text":"impl BitAnd<usize> for usizex8","synthetic":false,"types":["packed_simd::vSize::usizex8"]},{"text":"impl BitAnd<Simd<[usize; 8]>> for usize","synthetic":false,"types":[]},{"text":"impl BitAnd<Simd<[msize; 8]>> for msizex8","synthetic":false,"types":["packed_simd::vSize::msizex8"]},{"text":"impl BitAnd<bool> for msizex8","synthetic":false,"types":["packed_simd::vSize::msizex8"]},{"text":"impl BitAnd<Simd<[msize; 8]>> for bool","synthetic":false,"types":[]}]; +if (window.register_implementors) {window.register_implementors(implementors);} else {window.pending_implementors = implementors;}})() \ No newline at end of file diff --git a/implementors/core/ops/bit/trait.BitAndAssign.js b/implementors/core/ops/bit/trait.BitAndAssign.js new file mode 100644 index 000000000..34662bf92 --- /dev/null +++ b/implementors/core/ops/bit/trait.BitAndAssign.js @@ -0,0 +1,3 @@ +(function() {var implementors = {}; +implementors["packed_simd"] = [{"text":"impl BitAndAssign<Simd<[i8; 2]>> for i8x2","synthetic":false,"types":["packed_simd::v16::i8x2"]},{"text":"impl BitAndAssign<i8> for i8x2","synthetic":false,"types":["packed_simd::v16::i8x2"]},{"text":"impl BitAndAssign<Simd<[u8; 2]>> for u8x2","synthetic":false,"types":["packed_simd::v16::u8x2"]},{"text":"impl BitAndAssign<u8> for u8x2","synthetic":false,"types":["packed_simd::v16::u8x2"]},{"text":"impl BitAndAssign<Simd<[m8; 2]>> for m8x2","synthetic":false,"types":["packed_simd::v16::m8x2"]},{"text":"impl BitAndAssign<bool> for m8x2","synthetic":false,"types":["packed_simd::v16::m8x2"]},{"text":"impl BitAndAssign<Simd<[i8; 4]>> for i8x4","synthetic":false,"types":["packed_simd::v32::i8x4"]},{"text":"impl BitAndAssign<i8> for i8x4","synthetic":false,"types":["packed_simd::v32::i8x4"]},{"text":"impl BitAndAssign<Simd<[u8; 4]>> for u8x4","synthetic":false,"types":["packed_simd::v32::u8x4"]},{"text":"impl BitAndAssign<u8> for u8x4","synthetic":false,"types":["packed_simd::v32::u8x4"]},{"text":"impl BitAndAssign<Simd<[m8; 4]>> for m8x4","synthetic":false,"types":["packed_simd::v32::m8x4"]},{"text":"impl BitAndAssign<bool> for m8x4","synthetic":false,"types":["packed_simd::v32::m8x4"]},{"text":"impl BitAndAssign<Simd<[i16; 2]>> for i16x2","synthetic":false,"types":["packed_simd::v32::i16x2"]},{"text":"impl BitAndAssign<i16> for i16x2","synthetic":false,"types":["packed_simd::v32::i16x2"]},{"text":"impl BitAndAssign<Simd<[u16; 2]>> for u16x2","synthetic":false,"types":["packed_simd::v32::u16x2"]},{"text":"impl BitAndAssign<u16> for u16x2","synthetic":false,"types":["packed_simd::v32::u16x2"]},{"text":"impl BitAndAssign<Simd<[m16; 2]>> for m16x2","synthetic":false,"types":["packed_simd::v32::m16x2"]},{"text":"impl BitAndAssign<bool> for m16x2","synthetic":false,"types":["packed_simd::v32::m16x2"]},{"text":"impl BitAndAssign<Simd<[i8; 8]>> for i8x8","synthetic":false,"types":["packed_simd::v64::i8x8"]},{"text":"impl BitAndAssign<i8> for i8x8","synthetic":false,"types":["packed_simd::v64::i8x8"]},{"text":"impl BitAndAssign<Simd<[u8; 8]>> for u8x8","synthetic":false,"types":["packed_simd::v64::u8x8"]},{"text":"impl BitAndAssign<u8> for u8x8","synthetic":false,"types":["packed_simd::v64::u8x8"]},{"text":"impl BitAndAssign<Simd<[m8; 8]>> for m8x8","synthetic":false,"types":["packed_simd::v64::m8x8"]},{"text":"impl BitAndAssign<bool> for m8x8","synthetic":false,"types":["packed_simd::v64::m8x8"]},{"text":"impl BitAndAssign<Simd<[i16; 4]>> for i16x4","synthetic":false,"types":["packed_simd::v64::i16x4"]},{"text":"impl BitAndAssign<i16> for i16x4","synthetic":false,"types":["packed_simd::v64::i16x4"]},{"text":"impl BitAndAssign<Simd<[u16; 4]>> for u16x4","synthetic":false,"types":["packed_simd::v64::u16x4"]},{"text":"impl BitAndAssign<u16> for u16x4","synthetic":false,"types":["packed_simd::v64::u16x4"]},{"text":"impl BitAndAssign<Simd<[m16; 4]>> for m16x4","synthetic":false,"types":["packed_simd::v64::m16x4"]},{"text":"impl BitAndAssign<bool> for m16x4","synthetic":false,"types":["packed_simd::v64::m16x4"]},{"text":"impl BitAndAssign<Simd<[i32; 2]>> for i32x2","synthetic":false,"types":["packed_simd::v64::i32x2"]},{"text":"impl BitAndAssign<i32> for i32x2","synthetic":false,"types":["packed_simd::v64::i32x2"]},{"text":"impl BitAndAssign<Simd<[u32; 2]>> for u32x2","synthetic":false,"types":["packed_simd::v64::u32x2"]},{"text":"impl BitAndAssign<u32> for u32x2","synthetic":false,"types":["packed_simd::v64::u32x2"]},{"text":"impl BitAndAssign<Simd<[m32; 2]>> for m32x2","synthetic":false,"types":["packed_simd::v64::m32x2"]},{"text":"impl BitAndAssign<bool> for m32x2","synthetic":false,"types":["packed_simd::v64::m32x2"]},{"text":"impl BitAndAssign<Simd<[i8; 16]>> for i8x16","synthetic":false,"types":["packed_simd::v128::i8x16"]},{"text":"impl BitAndAssign<i8> for i8x16","synthetic":false,"types":["packed_simd::v128::i8x16"]},{"text":"impl BitAndAssign<Simd<[u8; 16]>> for u8x16","synthetic":false,"types":["packed_simd::v128::u8x16"]},{"text":"impl BitAndAssign<u8> for u8x16","synthetic":false,"types":["packed_simd::v128::u8x16"]},{"text":"impl BitAndAssign<Simd<[m8; 16]>> for m8x16","synthetic":false,"types":["packed_simd::v128::m8x16"]},{"text":"impl BitAndAssign<bool> for m8x16","synthetic":false,"types":["packed_simd::v128::m8x16"]},{"text":"impl BitAndAssign<Simd<[i16; 8]>> for i16x8","synthetic":false,"types":["packed_simd::v128::i16x8"]},{"text":"impl BitAndAssign<i16> for i16x8","synthetic":false,"types":["packed_simd::v128::i16x8"]},{"text":"impl BitAndAssign<Simd<[u16; 8]>> for u16x8","synthetic":false,"types":["packed_simd::v128::u16x8"]},{"text":"impl BitAndAssign<u16> for u16x8","synthetic":false,"types":["packed_simd::v128::u16x8"]},{"text":"impl BitAndAssign<Simd<[m16; 8]>> for m16x8","synthetic":false,"types":["packed_simd::v128::m16x8"]},{"text":"impl BitAndAssign<bool> for m16x8","synthetic":false,"types":["packed_simd::v128::m16x8"]},{"text":"impl BitAndAssign<Simd<[i32; 4]>> for i32x4","synthetic":false,"types":["packed_simd::v128::i32x4"]},{"text":"impl BitAndAssign<i32> for i32x4","synthetic":false,"types":["packed_simd::v128::i32x4"]},{"text":"impl BitAndAssign<Simd<[u32; 4]>> for u32x4","synthetic":false,"types":["packed_simd::v128::u32x4"]},{"text":"impl BitAndAssign<u32> for u32x4","synthetic":false,"types":["packed_simd::v128::u32x4"]},{"text":"impl BitAndAssign<Simd<[m32; 4]>> for m32x4","synthetic":false,"types":["packed_simd::v128::m32x4"]},{"text":"impl BitAndAssign<bool> for m32x4","synthetic":false,"types":["packed_simd::v128::m32x4"]},{"text":"impl BitAndAssign<Simd<[i64; 2]>> for i64x2","synthetic":false,"types":["packed_simd::v128::i64x2"]},{"text":"impl BitAndAssign<i64> for i64x2","synthetic":false,"types":["packed_simd::v128::i64x2"]},{"text":"impl BitAndAssign<Simd<[u64; 2]>> for u64x2","synthetic":false,"types":["packed_simd::v128::u64x2"]},{"text":"impl BitAndAssign<u64> for u64x2","synthetic":false,"types":["packed_simd::v128::u64x2"]},{"text":"impl BitAndAssign<Simd<[m64; 2]>> for m64x2","synthetic":false,"types":["packed_simd::v128::m64x2"]},{"text":"impl BitAndAssign<bool> for m64x2","synthetic":false,"types":["packed_simd::v128::m64x2"]},{"text":"impl BitAndAssign<Simd<[i128; 1]>> for i128x1","synthetic":false,"types":["packed_simd::v128::i128x1"]},{"text":"impl BitAndAssign<i128> for i128x1","synthetic":false,"types":["packed_simd::v128::i128x1"]},{"text":"impl BitAndAssign<Simd<[u128; 1]>> for u128x1","synthetic":false,"types":["packed_simd::v128::u128x1"]},{"text":"impl BitAndAssign<u128> for u128x1","synthetic":false,"types":["packed_simd::v128::u128x1"]},{"text":"impl BitAndAssign<Simd<[m128; 1]>> for m128x1","synthetic":false,"types":["packed_simd::v128::m128x1"]},{"text":"impl BitAndAssign<bool> for m128x1","synthetic":false,"types":["packed_simd::v128::m128x1"]},{"text":"impl BitAndAssign<Simd<[i8; 32]>> for i8x32","synthetic":false,"types":["packed_simd::v256::i8x32"]},{"text":"impl BitAndAssign<i8> for i8x32","synthetic":false,"types":["packed_simd::v256::i8x32"]},{"text":"impl BitAndAssign<Simd<[u8; 32]>> for u8x32","synthetic":false,"types":["packed_simd::v256::u8x32"]},{"text":"impl BitAndAssign<u8> for u8x32","synthetic":false,"types":["packed_simd::v256::u8x32"]},{"text":"impl BitAndAssign<Simd<[m8; 32]>> for m8x32","synthetic":false,"types":["packed_simd::v256::m8x32"]},{"text":"impl BitAndAssign<bool> for m8x32","synthetic":false,"types":["packed_simd::v256::m8x32"]},{"text":"impl BitAndAssign<Simd<[i16; 16]>> for i16x16","synthetic":false,"types":["packed_simd::v256::i16x16"]},{"text":"impl BitAndAssign<i16> for i16x16","synthetic":false,"types":["packed_simd::v256::i16x16"]},{"text":"impl BitAndAssign<Simd<[u16; 16]>> for u16x16","synthetic":false,"types":["packed_simd::v256::u16x16"]},{"text":"impl BitAndAssign<u16> for u16x16","synthetic":false,"types":["packed_simd::v256::u16x16"]},{"text":"impl BitAndAssign<Simd<[m16; 16]>> for m16x16","synthetic":false,"types":["packed_simd::v256::m16x16"]},{"text":"impl BitAndAssign<bool> for m16x16","synthetic":false,"types":["packed_simd::v256::m16x16"]},{"text":"impl BitAndAssign<Simd<[i32; 8]>> for i32x8","synthetic":false,"types":["packed_simd::v256::i32x8"]},{"text":"impl BitAndAssign<i32> for i32x8","synthetic":false,"types":["packed_simd::v256::i32x8"]},{"text":"impl BitAndAssign<Simd<[u32; 8]>> for u32x8","synthetic":false,"types":["packed_simd::v256::u32x8"]},{"text":"impl BitAndAssign<u32> for u32x8","synthetic":false,"types":["packed_simd::v256::u32x8"]},{"text":"impl BitAndAssign<Simd<[m32; 8]>> for m32x8","synthetic":false,"types":["packed_simd::v256::m32x8"]},{"text":"impl BitAndAssign<bool> for m32x8","synthetic":false,"types":["packed_simd::v256::m32x8"]},{"text":"impl BitAndAssign<Simd<[i64; 4]>> for i64x4","synthetic":false,"types":["packed_simd::v256::i64x4"]},{"text":"impl BitAndAssign<i64> for i64x4","synthetic":false,"types":["packed_simd::v256::i64x4"]},{"text":"impl BitAndAssign<Simd<[u64; 4]>> for u64x4","synthetic":false,"types":["packed_simd::v256::u64x4"]},{"text":"impl BitAndAssign<u64> for u64x4","synthetic":false,"types":["packed_simd::v256::u64x4"]},{"text":"impl BitAndAssign<Simd<[m64; 4]>> for m64x4","synthetic":false,"types":["packed_simd::v256::m64x4"]},{"text":"impl BitAndAssign<bool> for m64x4","synthetic":false,"types":["packed_simd::v256::m64x4"]},{"text":"impl BitAndAssign<Simd<[i128; 2]>> for i128x2","synthetic":false,"types":["packed_simd::v256::i128x2"]},{"text":"impl BitAndAssign<i128> for i128x2","synthetic":false,"types":["packed_simd::v256::i128x2"]},{"text":"impl BitAndAssign<Simd<[u128; 2]>> for u128x2","synthetic":false,"types":["packed_simd::v256::u128x2"]},{"text":"impl BitAndAssign<u128> for u128x2","synthetic":false,"types":["packed_simd::v256::u128x2"]},{"text":"impl BitAndAssign<Simd<[m128; 2]>> for m128x2","synthetic":false,"types":["packed_simd::v256::m128x2"]},{"text":"impl BitAndAssign<bool> for m128x2","synthetic":false,"types":["packed_simd::v256::m128x2"]},{"text":"impl BitAndAssign<Simd<[i8; 64]>> for i8x64","synthetic":false,"types":["packed_simd::v512::i8x64"]},{"text":"impl BitAndAssign<i8> for i8x64","synthetic":false,"types":["packed_simd::v512::i8x64"]},{"text":"impl BitAndAssign<Simd<[u8; 64]>> for u8x64","synthetic":false,"types":["packed_simd::v512::u8x64"]},{"text":"impl BitAndAssign<u8> for u8x64","synthetic":false,"types":["packed_simd::v512::u8x64"]},{"text":"impl BitAndAssign<Simd<[m8; 64]>> for m8x64","synthetic":false,"types":["packed_simd::v512::m8x64"]},{"text":"impl BitAndAssign<bool> for m8x64","synthetic":false,"types":["packed_simd::v512::m8x64"]},{"text":"impl BitAndAssign<Simd<[i16; 32]>> for i16x32","synthetic":false,"types":["packed_simd::v512::i16x32"]},{"text":"impl BitAndAssign<i16> for i16x32","synthetic":false,"types":["packed_simd::v512::i16x32"]},{"text":"impl BitAndAssign<Simd<[u16; 32]>> for u16x32","synthetic":false,"types":["packed_simd::v512::u16x32"]},{"text":"impl BitAndAssign<u16> for u16x32","synthetic":false,"types":["packed_simd::v512::u16x32"]},{"text":"impl BitAndAssign<Simd<[m16; 32]>> for m16x32","synthetic":false,"types":["packed_simd::v512::m16x32"]},{"text":"impl BitAndAssign<bool> for m16x32","synthetic":false,"types":["packed_simd::v512::m16x32"]},{"text":"impl BitAndAssign<Simd<[i32; 16]>> for i32x16","synthetic":false,"types":["packed_simd::v512::i32x16"]},{"text":"impl BitAndAssign<i32> for i32x16","synthetic":false,"types":["packed_simd::v512::i32x16"]},{"text":"impl BitAndAssign<Simd<[u32; 16]>> for u32x16","synthetic":false,"types":["packed_simd::v512::u32x16"]},{"text":"impl BitAndAssign<u32> for u32x16","synthetic":false,"types":["packed_simd::v512::u32x16"]},{"text":"impl BitAndAssign<Simd<[m32; 16]>> for m32x16","synthetic":false,"types":["packed_simd::v512::m32x16"]},{"text":"impl BitAndAssign<bool> for m32x16","synthetic":false,"types":["packed_simd::v512::m32x16"]},{"text":"impl BitAndAssign<Simd<[i64; 8]>> for i64x8","synthetic":false,"types":["packed_simd::v512::i64x8"]},{"text":"impl BitAndAssign<i64> for i64x8","synthetic":false,"types":["packed_simd::v512::i64x8"]},{"text":"impl BitAndAssign<Simd<[u64; 8]>> for u64x8","synthetic":false,"types":["packed_simd::v512::u64x8"]},{"text":"impl BitAndAssign<u64> for u64x8","synthetic":false,"types":["packed_simd::v512::u64x8"]},{"text":"impl BitAndAssign<Simd<[m64; 8]>> for m64x8","synthetic":false,"types":["packed_simd::v512::m64x8"]},{"text":"impl BitAndAssign<bool> for m64x8","synthetic":false,"types":["packed_simd::v512::m64x8"]},{"text":"impl BitAndAssign<Simd<[i128; 4]>> for i128x4","synthetic":false,"types":["packed_simd::v512::i128x4"]},{"text":"impl BitAndAssign<i128> for i128x4","synthetic":false,"types":["packed_simd::v512::i128x4"]},{"text":"impl BitAndAssign<Simd<[u128; 4]>> for u128x4","synthetic":false,"types":["packed_simd::v512::u128x4"]},{"text":"impl BitAndAssign<u128> for u128x4","synthetic":false,"types":["packed_simd::v512::u128x4"]},{"text":"impl BitAndAssign<Simd<[m128; 4]>> for m128x4","synthetic":false,"types":["packed_simd::v512::m128x4"]},{"text":"impl BitAndAssign<bool> for m128x4","synthetic":false,"types":["packed_simd::v512::m128x4"]},{"text":"impl BitAndAssign<Simd<[isize; 2]>> for isizex2","synthetic":false,"types":["packed_simd::vSize::isizex2"]},{"text":"impl BitAndAssign<isize> for isizex2","synthetic":false,"types":["packed_simd::vSize::isizex2"]},{"text":"impl BitAndAssign<Simd<[usize; 2]>> for usizex2","synthetic":false,"types":["packed_simd::vSize::usizex2"]},{"text":"impl BitAndAssign<usize> for usizex2","synthetic":false,"types":["packed_simd::vSize::usizex2"]},{"text":"impl BitAndAssign<Simd<[msize; 2]>> for msizex2","synthetic":false,"types":["packed_simd::vSize::msizex2"]},{"text":"impl BitAndAssign<bool> for msizex2","synthetic":false,"types":["packed_simd::vSize::msizex2"]},{"text":"impl BitAndAssign<Simd<[isize; 4]>> for isizex4","synthetic":false,"types":["packed_simd::vSize::isizex4"]},{"text":"impl BitAndAssign<isize> for isizex4","synthetic":false,"types":["packed_simd::vSize::isizex4"]},{"text":"impl BitAndAssign<Simd<[usize; 4]>> for usizex4","synthetic":false,"types":["packed_simd::vSize::usizex4"]},{"text":"impl BitAndAssign<usize> for usizex4","synthetic":false,"types":["packed_simd::vSize::usizex4"]},{"text":"impl BitAndAssign<Simd<[msize; 4]>> for msizex4","synthetic":false,"types":["packed_simd::vSize::msizex4"]},{"text":"impl BitAndAssign<bool> for msizex4","synthetic":false,"types":["packed_simd::vSize::msizex4"]},{"text":"impl BitAndAssign<Simd<[isize; 8]>> for isizex8","synthetic":false,"types":["packed_simd::vSize::isizex8"]},{"text":"impl BitAndAssign<isize> for isizex8","synthetic":false,"types":["packed_simd::vSize::isizex8"]},{"text":"impl BitAndAssign<Simd<[usize; 8]>> for usizex8","synthetic":false,"types":["packed_simd::vSize::usizex8"]},{"text":"impl BitAndAssign<usize> for usizex8","synthetic":false,"types":["packed_simd::vSize::usizex8"]},{"text":"impl BitAndAssign<Simd<[msize; 8]>> for msizex8","synthetic":false,"types":["packed_simd::vSize::msizex8"]},{"text":"impl BitAndAssign<bool> for msizex8","synthetic":false,"types":["packed_simd::vSize::msizex8"]}]; +if (window.register_implementors) {window.register_implementors(implementors);} else {window.pending_implementors = implementors;}})() \ No newline at end of file diff --git a/implementors/core/ops/bit/trait.BitOr.js b/implementors/core/ops/bit/trait.BitOr.js new file mode 100644 index 000000000..5aa6b22c8 --- /dev/null +++ b/implementors/core/ops/bit/trait.BitOr.js @@ -0,0 +1,3 @@ +(function() {var implementors = {}; +implementors["packed_simd"] = [{"text":"impl BitOr<Simd<[i8; 2]>> for i8x2","synthetic":false,"types":["packed_simd::v16::i8x2"]},{"text":"impl BitOr<i8> for i8x2","synthetic":false,"types":["packed_simd::v16::i8x2"]},{"text":"impl BitOr<Simd<[i8; 2]>> for i8","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[u8; 2]>> for u8x2","synthetic":false,"types":["packed_simd::v16::u8x2"]},{"text":"impl BitOr<u8> for u8x2","synthetic":false,"types":["packed_simd::v16::u8x2"]},{"text":"impl BitOr<Simd<[u8; 2]>> for u8","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[m8; 2]>> for m8x2","synthetic":false,"types":["packed_simd::v16::m8x2"]},{"text":"impl BitOr<bool> for m8x2","synthetic":false,"types":["packed_simd::v16::m8x2"]},{"text":"impl BitOr<Simd<[m8; 2]>> for bool","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[i8; 4]>> for i8x4","synthetic":false,"types":["packed_simd::v32::i8x4"]},{"text":"impl BitOr<i8> for i8x4","synthetic":false,"types":["packed_simd::v32::i8x4"]},{"text":"impl BitOr<Simd<[i8; 4]>> for i8","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[u8; 4]>> for u8x4","synthetic":false,"types":["packed_simd::v32::u8x4"]},{"text":"impl BitOr<u8> for u8x4","synthetic":false,"types":["packed_simd::v32::u8x4"]},{"text":"impl BitOr<Simd<[u8; 4]>> for u8","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[m8; 4]>> for m8x4","synthetic":false,"types":["packed_simd::v32::m8x4"]},{"text":"impl BitOr<bool> for m8x4","synthetic":false,"types":["packed_simd::v32::m8x4"]},{"text":"impl BitOr<Simd<[m8; 4]>> for bool","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[i16; 2]>> for i16x2","synthetic":false,"types":["packed_simd::v32::i16x2"]},{"text":"impl BitOr<i16> for i16x2","synthetic":false,"types":["packed_simd::v32::i16x2"]},{"text":"impl BitOr<Simd<[i16; 2]>> for i16","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[u16; 2]>> for u16x2","synthetic":false,"types":["packed_simd::v32::u16x2"]},{"text":"impl BitOr<u16> for u16x2","synthetic":false,"types":["packed_simd::v32::u16x2"]},{"text":"impl BitOr<Simd<[u16; 2]>> for u16","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[m16; 2]>> for m16x2","synthetic":false,"types":["packed_simd::v32::m16x2"]},{"text":"impl BitOr<bool> for m16x2","synthetic":false,"types":["packed_simd::v32::m16x2"]},{"text":"impl BitOr<Simd<[m16; 2]>> for bool","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[i8; 8]>> for i8x8","synthetic":false,"types":["packed_simd::v64::i8x8"]},{"text":"impl BitOr<i8> for i8x8","synthetic":false,"types":["packed_simd::v64::i8x8"]},{"text":"impl BitOr<Simd<[i8; 8]>> for i8","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[u8; 8]>> for u8x8","synthetic":false,"types":["packed_simd::v64::u8x8"]},{"text":"impl BitOr<u8> for u8x8","synthetic":false,"types":["packed_simd::v64::u8x8"]},{"text":"impl BitOr<Simd<[u8; 8]>> for u8","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[m8; 8]>> for m8x8","synthetic":false,"types":["packed_simd::v64::m8x8"]},{"text":"impl BitOr<bool> for m8x8","synthetic":false,"types":["packed_simd::v64::m8x8"]},{"text":"impl BitOr<Simd<[m8; 8]>> for bool","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[i16; 4]>> for i16x4","synthetic":false,"types":["packed_simd::v64::i16x4"]},{"text":"impl BitOr<i16> for i16x4","synthetic":false,"types":["packed_simd::v64::i16x4"]},{"text":"impl BitOr<Simd<[i16; 4]>> for i16","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[u16; 4]>> for u16x4","synthetic":false,"types":["packed_simd::v64::u16x4"]},{"text":"impl BitOr<u16> for u16x4","synthetic":false,"types":["packed_simd::v64::u16x4"]},{"text":"impl BitOr<Simd<[u16; 4]>> for u16","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[m16; 4]>> for m16x4","synthetic":false,"types":["packed_simd::v64::m16x4"]},{"text":"impl BitOr<bool> for m16x4","synthetic":false,"types":["packed_simd::v64::m16x4"]},{"text":"impl BitOr<Simd<[m16; 4]>> for bool","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[i32; 2]>> for i32x2","synthetic":false,"types":["packed_simd::v64::i32x2"]},{"text":"impl BitOr<i32> for i32x2","synthetic":false,"types":["packed_simd::v64::i32x2"]},{"text":"impl BitOr<Simd<[i32; 2]>> for i32","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[u32; 2]>> for u32x2","synthetic":false,"types":["packed_simd::v64::u32x2"]},{"text":"impl BitOr<u32> for u32x2","synthetic":false,"types":["packed_simd::v64::u32x2"]},{"text":"impl BitOr<Simd<[u32; 2]>> for u32","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[m32; 2]>> for m32x2","synthetic":false,"types":["packed_simd::v64::m32x2"]},{"text":"impl BitOr<bool> for m32x2","synthetic":false,"types":["packed_simd::v64::m32x2"]},{"text":"impl BitOr<Simd<[m32; 2]>> for bool","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[i8; 16]>> for i8x16","synthetic":false,"types":["packed_simd::v128::i8x16"]},{"text":"impl BitOr<i8> for i8x16","synthetic":false,"types":["packed_simd::v128::i8x16"]},{"text":"impl BitOr<Simd<[i8; 16]>> for i8","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[u8; 16]>> for u8x16","synthetic":false,"types":["packed_simd::v128::u8x16"]},{"text":"impl BitOr<u8> for u8x16","synthetic":false,"types":["packed_simd::v128::u8x16"]},{"text":"impl BitOr<Simd<[u8; 16]>> for u8","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[m8; 16]>> for m8x16","synthetic":false,"types":["packed_simd::v128::m8x16"]},{"text":"impl BitOr<bool> for m8x16","synthetic":false,"types":["packed_simd::v128::m8x16"]},{"text":"impl BitOr<Simd<[m8; 16]>> for bool","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[i16; 8]>> for i16x8","synthetic":false,"types":["packed_simd::v128::i16x8"]},{"text":"impl BitOr<i16> for i16x8","synthetic":false,"types":["packed_simd::v128::i16x8"]},{"text":"impl BitOr<Simd<[i16; 8]>> for i16","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[u16; 8]>> for u16x8","synthetic":false,"types":["packed_simd::v128::u16x8"]},{"text":"impl BitOr<u16> for u16x8","synthetic":false,"types":["packed_simd::v128::u16x8"]},{"text":"impl BitOr<Simd<[u16; 8]>> for u16","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[m16; 8]>> for m16x8","synthetic":false,"types":["packed_simd::v128::m16x8"]},{"text":"impl BitOr<bool> for m16x8","synthetic":false,"types":["packed_simd::v128::m16x8"]},{"text":"impl BitOr<Simd<[m16; 8]>> for bool","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[i32; 4]>> for i32x4","synthetic":false,"types":["packed_simd::v128::i32x4"]},{"text":"impl BitOr<i32> for i32x4","synthetic":false,"types":["packed_simd::v128::i32x4"]},{"text":"impl BitOr<Simd<[i32; 4]>> for i32","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[u32; 4]>> for u32x4","synthetic":false,"types":["packed_simd::v128::u32x4"]},{"text":"impl BitOr<u32> for u32x4","synthetic":false,"types":["packed_simd::v128::u32x4"]},{"text":"impl BitOr<Simd<[u32; 4]>> for u32","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[m32; 4]>> for m32x4","synthetic":false,"types":["packed_simd::v128::m32x4"]},{"text":"impl BitOr<bool> for m32x4","synthetic":false,"types":["packed_simd::v128::m32x4"]},{"text":"impl BitOr<Simd<[m32; 4]>> for bool","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[i64; 2]>> for i64x2","synthetic":false,"types":["packed_simd::v128::i64x2"]},{"text":"impl BitOr<i64> for i64x2","synthetic":false,"types":["packed_simd::v128::i64x2"]},{"text":"impl BitOr<Simd<[i64; 2]>> for i64","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[u64; 2]>> for u64x2","synthetic":false,"types":["packed_simd::v128::u64x2"]},{"text":"impl BitOr<u64> for u64x2","synthetic":false,"types":["packed_simd::v128::u64x2"]},{"text":"impl BitOr<Simd<[u64; 2]>> for u64","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[m64; 2]>> for m64x2","synthetic":false,"types":["packed_simd::v128::m64x2"]},{"text":"impl BitOr<bool> for m64x2","synthetic":false,"types":["packed_simd::v128::m64x2"]},{"text":"impl BitOr<Simd<[m64; 2]>> for bool","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[i128; 1]>> for i128x1","synthetic":false,"types":["packed_simd::v128::i128x1"]},{"text":"impl BitOr<i128> for i128x1","synthetic":false,"types":["packed_simd::v128::i128x1"]},{"text":"impl BitOr<Simd<[i128; 1]>> for i128","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[u128; 1]>> for u128x1","synthetic":false,"types":["packed_simd::v128::u128x1"]},{"text":"impl BitOr<u128> for u128x1","synthetic":false,"types":["packed_simd::v128::u128x1"]},{"text":"impl BitOr<Simd<[u128; 1]>> for u128","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[m128; 1]>> for m128x1","synthetic":false,"types":["packed_simd::v128::m128x1"]},{"text":"impl BitOr<bool> for m128x1","synthetic":false,"types":["packed_simd::v128::m128x1"]},{"text":"impl BitOr<Simd<[m128; 1]>> for bool","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[i8; 32]>> for i8x32","synthetic":false,"types":["packed_simd::v256::i8x32"]},{"text":"impl BitOr<i8> for i8x32","synthetic":false,"types":["packed_simd::v256::i8x32"]},{"text":"impl BitOr<Simd<[i8; 32]>> for i8","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[u8; 32]>> for u8x32","synthetic":false,"types":["packed_simd::v256::u8x32"]},{"text":"impl BitOr<u8> for u8x32","synthetic":false,"types":["packed_simd::v256::u8x32"]},{"text":"impl BitOr<Simd<[u8; 32]>> for u8","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[m8; 32]>> for m8x32","synthetic":false,"types":["packed_simd::v256::m8x32"]},{"text":"impl BitOr<bool> for m8x32","synthetic":false,"types":["packed_simd::v256::m8x32"]},{"text":"impl BitOr<Simd<[m8; 32]>> for bool","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[i16; 16]>> for i16x16","synthetic":false,"types":["packed_simd::v256::i16x16"]},{"text":"impl BitOr<i16> for i16x16","synthetic":false,"types":["packed_simd::v256::i16x16"]},{"text":"impl BitOr<Simd<[i16; 16]>> for i16","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[u16; 16]>> for u16x16","synthetic":false,"types":["packed_simd::v256::u16x16"]},{"text":"impl BitOr<u16> for u16x16","synthetic":false,"types":["packed_simd::v256::u16x16"]},{"text":"impl BitOr<Simd<[u16; 16]>> for u16","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[m16; 16]>> for m16x16","synthetic":false,"types":["packed_simd::v256::m16x16"]},{"text":"impl BitOr<bool> for m16x16","synthetic":false,"types":["packed_simd::v256::m16x16"]},{"text":"impl BitOr<Simd<[m16; 16]>> for bool","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[i32; 8]>> for i32x8","synthetic":false,"types":["packed_simd::v256::i32x8"]},{"text":"impl BitOr<i32> for i32x8","synthetic":false,"types":["packed_simd::v256::i32x8"]},{"text":"impl BitOr<Simd<[i32; 8]>> for i32","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[u32; 8]>> for u32x8","synthetic":false,"types":["packed_simd::v256::u32x8"]},{"text":"impl BitOr<u32> for u32x8","synthetic":false,"types":["packed_simd::v256::u32x8"]},{"text":"impl BitOr<Simd<[u32; 8]>> for u32","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[m32; 8]>> for m32x8","synthetic":false,"types":["packed_simd::v256::m32x8"]},{"text":"impl BitOr<bool> for m32x8","synthetic":false,"types":["packed_simd::v256::m32x8"]},{"text":"impl BitOr<Simd<[m32; 8]>> for bool","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[i64; 4]>> for i64x4","synthetic":false,"types":["packed_simd::v256::i64x4"]},{"text":"impl BitOr<i64> for i64x4","synthetic":false,"types":["packed_simd::v256::i64x4"]},{"text":"impl BitOr<Simd<[i64; 4]>> for i64","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[u64; 4]>> for u64x4","synthetic":false,"types":["packed_simd::v256::u64x4"]},{"text":"impl BitOr<u64> for u64x4","synthetic":false,"types":["packed_simd::v256::u64x4"]},{"text":"impl BitOr<Simd<[u64; 4]>> for u64","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[m64; 4]>> for m64x4","synthetic":false,"types":["packed_simd::v256::m64x4"]},{"text":"impl BitOr<bool> for m64x4","synthetic":false,"types":["packed_simd::v256::m64x4"]},{"text":"impl BitOr<Simd<[m64; 4]>> for bool","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[i128; 2]>> for i128x2","synthetic":false,"types":["packed_simd::v256::i128x2"]},{"text":"impl BitOr<i128> for i128x2","synthetic":false,"types":["packed_simd::v256::i128x2"]},{"text":"impl BitOr<Simd<[i128; 2]>> for i128","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[u128; 2]>> for u128x2","synthetic":false,"types":["packed_simd::v256::u128x2"]},{"text":"impl BitOr<u128> for u128x2","synthetic":false,"types":["packed_simd::v256::u128x2"]},{"text":"impl BitOr<Simd<[u128; 2]>> for u128","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[m128; 2]>> for m128x2","synthetic":false,"types":["packed_simd::v256::m128x2"]},{"text":"impl BitOr<bool> for m128x2","synthetic":false,"types":["packed_simd::v256::m128x2"]},{"text":"impl BitOr<Simd<[m128; 2]>> for bool","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[i8; 64]>> for i8x64","synthetic":false,"types":["packed_simd::v512::i8x64"]},{"text":"impl BitOr<i8> for i8x64","synthetic":false,"types":["packed_simd::v512::i8x64"]},{"text":"impl BitOr<Simd<[i8; 64]>> for i8","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[u8; 64]>> for u8x64","synthetic":false,"types":["packed_simd::v512::u8x64"]},{"text":"impl BitOr<u8> for u8x64","synthetic":false,"types":["packed_simd::v512::u8x64"]},{"text":"impl BitOr<Simd<[u8; 64]>> for u8","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[m8; 64]>> for m8x64","synthetic":false,"types":["packed_simd::v512::m8x64"]},{"text":"impl BitOr<bool> for m8x64","synthetic":false,"types":["packed_simd::v512::m8x64"]},{"text":"impl BitOr<Simd<[m8; 64]>> for bool","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[i16; 32]>> for i16x32","synthetic":false,"types":["packed_simd::v512::i16x32"]},{"text":"impl BitOr<i16> for i16x32","synthetic":false,"types":["packed_simd::v512::i16x32"]},{"text":"impl BitOr<Simd<[i16; 32]>> for i16","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[u16; 32]>> for u16x32","synthetic":false,"types":["packed_simd::v512::u16x32"]},{"text":"impl BitOr<u16> for u16x32","synthetic":false,"types":["packed_simd::v512::u16x32"]},{"text":"impl BitOr<Simd<[u16; 32]>> for u16","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[m16; 32]>> for m16x32","synthetic":false,"types":["packed_simd::v512::m16x32"]},{"text":"impl BitOr<bool> for m16x32","synthetic":false,"types":["packed_simd::v512::m16x32"]},{"text":"impl BitOr<Simd<[m16; 32]>> for bool","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[i32; 16]>> for i32x16","synthetic":false,"types":["packed_simd::v512::i32x16"]},{"text":"impl BitOr<i32> for i32x16","synthetic":false,"types":["packed_simd::v512::i32x16"]},{"text":"impl BitOr<Simd<[i32; 16]>> for i32","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[u32; 16]>> for u32x16","synthetic":false,"types":["packed_simd::v512::u32x16"]},{"text":"impl BitOr<u32> for u32x16","synthetic":false,"types":["packed_simd::v512::u32x16"]},{"text":"impl BitOr<Simd<[u32; 16]>> for u32","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[m32; 16]>> for m32x16","synthetic":false,"types":["packed_simd::v512::m32x16"]},{"text":"impl BitOr<bool> for m32x16","synthetic":false,"types":["packed_simd::v512::m32x16"]},{"text":"impl BitOr<Simd<[m32; 16]>> for bool","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[i64; 8]>> for i64x8","synthetic":false,"types":["packed_simd::v512::i64x8"]},{"text":"impl BitOr<i64> for i64x8","synthetic":false,"types":["packed_simd::v512::i64x8"]},{"text":"impl BitOr<Simd<[i64; 8]>> for i64","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[u64; 8]>> for u64x8","synthetic":false,"types":["packed_simd::v512::u64x8"]},{"text":"impl BitOr<u64> for u64x8","synthetic":false,"types":["packed_simd::v512::u64x8"]},{"text":"impl BitOr<Simd<[u64; 8]>> for u64","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[m64; 8]>> for m64x8","synthetic":false,"types":["packed_simd::v512::m64x8"]},{"text":"impl BitOr<bool> for m64x8","synthetic":false,"types":["packed_simd::v512::m64x8"]},{"text":"impl BitOr<Simd<[m64; 8]>> for bool","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[i128; 4]>> for i128x4","synthetic":false,"types":["packed_simd::v512::i128x4"]},{"text":"impl BitOr<i128> for i128x4","synthetic":false,"types":["packed_simd::v512::i128x4"]},{"text":"impl BitOr<Simd<[i128; 4]>> for i128","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[u128; 4]>> for u128x4","synthetic":false,"types":["packed_simd::v512::u128x4"]},{"text":"impl BitOr<u128> for u128x4","synthetic":false,"types":["packed_simd::v512::u128x4"]},{"text":"impl BitOr<Simd<[u128; 4]>> for u128","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[m128; 4]>> for m128x4","synthetic":false,"types":["packed_simd::v512::m128x4"]},{"text":"impl BitOr<bool> for m128x4","synthetic":false,"types":["packed_simd::v512::m128x4"]},{"text":"impl BitOr<Simd<[m128; 4]>> for bool","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[isize; 2]>> for isizex2","synthetic":false,"types":["packed_simd::vSize::isizex2"]},{"text":"impl BitOr<isize> for isizex2","synthetic":false,"types":["packed_simd::vSize::isizex2"]},{"text":"impl BitOr<Simd<[isize; 2]>> for isize","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[usize; 2]>> for usizex2","synthetic":false,"types":["packed_simd::vSize::usizex2"]},{"text":"impl BitOr<usize> for usizex2","synthetic":false,"types":["packed_simd::vSize::usizex2"]},{"text":"impl BitOr<Simd<[usize; 2]>> for usize","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[msize; 2]>> for msizex2","synthetic":false,"types":["packed_simd::vSize::msizex2"]},{"text":"impl BitOr<bool> for msizex2","synthetic":false,"types":["packed_simd::vSize::msizex2"]},{"text":"impl BitOr<Simd<[msize; 2]>> for bool","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[isize; 4]>> for isizex4","synthetic":false,"types":["packed_simd::vSize::isizex4"]},{"text":"impl BitOr<isize> for isizex4","synthetic":false,"types":["packed_simd::vSize::isizex4"]},{"text":"impl BitOr<Simd<[isize; 4]>> for isize","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[usize; 4]>> for usizex4","synthetic":false,"types":["packed_simd::vSize::usizex4"]},{"text":"impl BitOr<usize> for usizex4","synthetic":false,"types":["packed_simd::vSize::usizex4"]},{"text":"impl BitOr<Simd<[usize; 4]>> for usize","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[msize; 4]>> for msizex4","synthetic":false,"types":["packed_simd::vSize::msizex4"]},{"text":"impl BitOr<bool> for msizex4","synthetic":false,"types":["packed_simd::vSize::msizex4"]},{"text":"impl BitOr<Simd<[msize; 4]>> for bool","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[isize; 8]>> for isizex8","synthetic":false,"types":["packed_simd::vSize::isizex8"]},{"text":"impl BitOr<isize> for isizex8","synthetic":false,"types":["packed_simd::vSize::isizex8"]},{"text":"impl BitOr<Simd<[isize; 8]>> for isize","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[usize; 8]>> for usizex8","synthetic":false,"types":["packed_simd::vSize::usizex8"]},{"text":"impl BitOr<usize> for usizex8","synthetic":false,"types":["packed_simd::vSize::usizex8"]},{"text":"impl BitOr<Simd<[usize; 8]>> for usize","synthetic":false,"types":[]},{"text":"impl BitOr<Simd<[msize; 8]>> for msizex8","synthetic":false,"types":["packed_simd::vSize::msizex8"]},{"text":"impl BitOr<bool> for msizex8","synthetic":false,"types":["packed_simd::vSize::msizex8"]},{"text":"impl BitOr<Simd<[msize; 8]>> for bool","synthetic":false,"types":[]}]; +if (window.register_implementors) {window.register_implementors(implementors);} else {window.pending_implementors = implementors;}})() \ No newline at end of file diff --git a/implementors/core/ops/bit/trait.BitOrAssign.js b/implementors/core/ops/bit/trait.BitOrAssign.js new file mode 100644 index 000000000..437c3cae4 --- /dev/null +++ b/implementors/core/ops/bit/trait.BitOrAssign.js @@ -0,0 +1,3 @@ +(function() {var implementors = {}; +implementors["packed_simd"] = [{"text":"impl BitOrAssign<Simd<[i8; 2]>> for i8x2","synthetic":false,"types":["packed_simd::v16::i8x2"]},{"text":"impl BitOrAssign<i8> for i8x2","synthetic":false,"types":["packed_simd::v16::i8x2"]},{"text":"impl BitOrAssign<Simd<[u8; 2]>> for u8x2","synthetic":false,"types":["packed_simd::v16::u8x2"]},{"text":"impl BitOrAssign<u8> for u8x2","synthetic":false,"types":["packed_simd::v16::u8x2"]},{"text":"impl BitOrAssign<Simd<[m8; 2]>> for m8x2","synthetic":false,"types":["packed_simd::v16::m8x2"]},{"text":"impl BitOrAssign<bool> for m8x2","synthetic":false,"types":["packed_simd::v16::m8x2"]},{"text":"impl BitOrAssign<Simd<[i8; 4]>> for i8x4","synthetic":false,"types":["packed_simd::v32::i8x4"]},{"text":"impl BitOrAssign<i8> for i8x4","synthetic":false,"types":["packed_simd::v32::i8x4"]},{"text":"impl BitOrAssign<Simd<[u8; 4]>> for u8x4","synthetic":false,"types":["packed_simd::v32::u8x4"]},{"text":"impl BitOrAssign<u8> for u8x4","synthetic":false,"types":["packed_simd::v32::u8x4"]},{"text":"impl BitOrAssign<Simd<[m8; 4]>> for m8x4","synthetic":false,"types":["packed_simd::v32::m8x4"]},{"text":"impl BitOrAssign<bool> for m8x4","synthetic":false,"types":["packed_simd::v32::m8x4"]},{"text":"impl BitOrAssign<Simd<[i16; 2]>> for i16x2","synthetic":false,"types":["packed_simd::v32::i16x2"]},{"text":"impl BitOrAssign<i16> for i16x2","synthetic":false,"types":["packed_simd::v32::i16x2"]},{"text":"impl BitOrAssign<Simd<[u16; 2]>> for u16x2","synthetic":false,"types":["packed_simd::v32::u16x2"]},{"text":"impl BitOrAssign<u16> for u16x2","synthetic":false,"types":["packed_simd::v32::u16x2"]},{"text":"impl BitOrAssign<Simd<[m16; 2]>> for m16x2","synthetic":false,"types":["packed_simd::v32::m16x2"]},{"text":"impl BitOrAssign<bool> for m16x2","synthetic":false,"types":["packed_simd::v32::m16x2"]},{"text":"impl BitOrAssign<Simd<[i8; 8]>> for i8x8","synthetic":false,"types":["packed_simd::v64::i8x8"]},{"text":"impl BitOrAssign<i8> for i8x8","synthetic":false,"types":["packed_simd::v64::i8x8"]},{"text":"impl BitOrAssign<Simd<[u8; 8]>> for u8x8","synthetic":false,"types":["packed_simd::v64::u8x8"]},{"text":"impl BitOrAssign<u8> for u8x8","synthetic":false,"types":["packed_simd::v64::u8x8"]},{"text":"impl BitOrAssign<Simd<[m8; 8]>> for m8x8","synthetic":false,"types":["packed_simd::v64::m8x8"]},{"text":"impl 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usizex8","synthetic":false,"types":["packed_simd::vSize::usizex8"]},{"text":"impl BitOrAssign<Simd<[msize; 8]>> for msizex8","synthetic":false,"types":["packed_simd::vSize::msizex8"]},{"text":"impl BitOrAssign<bool> for msizex8","synthetic":false,"types":["packed_simd::vSize::msizex8"]}]; +if (window.register_implementors) {window.register_implementors(implementors);} else {window.pending_implementors = implementors;}})() \ No newline at end of file diff --git a/implementors/core/ops/bit/trait.BitXor.js b/implementors/core/ops/bit/trait.BitXor.js new file mode 100644 index 000000000..c6ee6af8c --- /dev/null +++ b/implementors/core/ops/bit/trait.BitXor.js @@ -0,0 +1,3 @@ +(function() {var implementors = {}; +implementors["packed_simd"] = [{"text":"impl BitXor<Simd<[i8; 2]>> for i8x2","synthetic":false,"types":["packed_simd::v16::i8x2"]},{"text":"impl BitXor<i8> for i8x2","synthetic":false,"types":["packed_simd::v16::i8x2"]},{"text":"impl BitXor<Simd<[i8; 2]>> for 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BitXor<Simd<[u16; 8]>> for u16","synthetic":false,"types":[]},{"text":"impl BitXor<Simd<[m16; 8]>> for m16x8","synthetic":false,"types":["packed_simd::v128::m16x8"]},{"text":"impl BitXor<bool> for m16x8","synthetic":false,"types":["packed_simd::v128::m16x8"]},{"text":"impl BitXor<Simd<[m16; 8]>> for bool","synthetic":false,"types":[]},{"text":"impl BitXor<Simd<[i32; 4]>> for i32x4","synthetic":false,"types":["packed_simd::v128::i32x4"]},{"text":"impl BitXor<i32> for i32x4","synthetic":false,"types":["packed_simd::v128::i32x4"]},{"text":"impl BitXor<Simd<[i32; 4]>> for i32","synthetic":false,"types":[]},{"text":"impl BitXor<Simd<[u32; 4]>> for u32x4","synthetic":false,"types":["packed_simd::v128::u32x4"]},{"text":"impl BitXor<u32> for u32x4","synthetic":false,"types":["packed_simd::v128::u32x4"]},{"text":"impl BitXor<Simd<[u32; 4]>> for u32","synthetic":false,"types":[]},{"text":"impl BitXor<Simd<[m32; 4]>> for m32x4","synthetic":false,"types":["packed_simd::v128::m32x4"]},{"text":"impl BitXor<bool> for m32x4","synthetic":false,"types":["packed_simd::v128::m32x4"]},{"text":"impl BitXor<Simd<[m32; 4]>> for bool","synthetic":false,"types":[]},{"text":"impl BitXor<Simd<[i64; 2]>> for i64x2","synthetic":false,"types":["packed_simd::v128::i64x2"]},{"text":"impl BitXor<i64> for i64x2","synthetic":false,"types":["packed_simd::v128::i64x2"]},{"text":"impl BitXor<Simd<[i64; 2]>> for i64","synthetic":false,"types":[]},{"text":"impl BitXor<Simd<[u64; 2]>> for u64x2","synthetic":false,"types":["packed_simd::v128::u64x2"]},{"text":"impl BitXor<u64> for u64x2","synthetic":false,"types":["packed_simd::v128::u64x2"]},{"text":"impl BitXor<Simd<[u64; 2]>> for u64","synthetic":false,"types":[]},{"text":"impl BitXor<Simd<[m64; 2]>> for m64x2","synthetic":false,"types":["packed_simd::v128::m64x2"]},{"text":"impl BitXor<bool> for m64x2","synthetic":false,"types":["packed_simd::v128::m64x2"]},{"text":"impl BitXor<Simd<[m64; 2]>> for bool","synthetic":false,"types":[]},{"text":"impl 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i8x32","synthetic":false,"types":["packed_simd::v256::i8x32"]},{"text":"impl BitXor<Simd<[i8; 32]>> for i8","synthetic":false,"types":[]},{"text":"impl BitXor<Simd<[u8; 32]>> for u8x32","synthetic":false,"types":["packed_simd::v256::u8x32"]},{"text":"impl BitXor<u8> for u8x32","synthetic":false,"types":["packed_simd::v256::u8x32"]},{"text":"impl BitXor<Simd<[u8; 32]>> for u8","synthetic":false,"types":[]},{"text":"impl BitXor<Simd<[m8; 32]>> for m8x32","synthetic":false,"types":["packed_simd::v256::m8x32"]},{"text":"impl BitXor<bool> for m8x32","synthetic":false,"types":["packed_simd::v256::m8x32"]},{"text":"impl BitXor<Simd<[m8; 32]>> for bool","synthetic":false,"types":[]},{"text":"impl BitXor<Simd<[i16; 16]>> for i16x16","synthetic":false,"types":["packed_simd::v256::i16x16"]},{"text":"impl BitXor<i16> for i16x16","synthetic":false,"types":["packed_simd::v256::i16x16"]},{"text":"impl BitXor<Simd<[i16; 16]>> for i16","synthetic":false,"types":[]},{"text":"impl BitXor<Simd<[u16; 16]>> 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u32x8","synthetic":false,"types":["packed_simd::v256::u32x8"]},{"text":"impl BitXor<Simd<[u32; 8]>> for u32","synthetic":false,"types":[]},{"text":"impl BitXor<Simd<[m32; 8]>> for m32x8","synthetic":false,"types":["packed_simd::v256::m32x8"]},{"text":"impl BitXor<bool> for m32x8","synthetic":false,"types":["packed_simd::v256::m32x8"]},{"text":"impl BitXor<Simd<[m32; 8]>> for bool","synthetic":false,"types":[]},{"text":"impl BitXor<Simd<[i64; 4]>> for i64x4","synthetic":false,"types":["packed_simd::v256::i64x4"]},{"text":"impl BitXor<i64> for i64x4","synthetic":false,"types":["packed_simd::v256::i64x4"]},{"text":"impl BitXor<Simd<[i64; 4]>> for i64","synthetic":false,"types":[]},{"text":"impl BitXor<Simd<[u64; 4]>> for u64x4","synthetic":false,"types":["packed_simd::v256::u64x4"]},{"text":"impl BitXor<u64> for u64x4","synthetic":false,"types":["packed_simd::v256::u64x4"]},{"text":"impl BitXor<Simd<[u64; 4]>> for u64","synthetic":false,"types":[]},{"text":"impl BitXor<Simd<[m64; 4]>> for m64x4","synthetic":false,"types":["packed_simd::v256::m64x4"]},{"text":"impl BitXor<bool> for m64x4","synthetic":false,"types":["packed_simd::v256::m64x4"]},{"text":"impl BitXor<Simd<[m64; 4]>> for bool","synthetic":false,"types":[]},{"text":"impl BitXor<Simd<[i128; 2]>> for i128x2","synthetic":false,"types":["packed_simd::v256::i128x2"]},{"text":"impl BitXor<i128> for i128x2","synthetic":false,"types":["packed_simd::v256::i128x2"]},{"text":"impl BitXor<Simd<[i128; 2]>> for i128","synthetic":false,"types":[]},{"text":"impl BitXor<Simd<[u128; 2]>> for u128x2","synthetic":false,"types":["packed_simd::v256::u128x2"]},{"text":"impl BitXor<u128> for u128x2","synthetic":false,"types":["packed_simd::v256::u128x2"]},{"text":"impl BitXor<Simd<[u128; 2]>> for u128","synthetic":false,"types":[]},{"text":"impl BitXor<Simd<[m128; 2]>> for m128x2","synthetic":false,"types":["packed_simd::v256::m128x2"]},{"text":"impl BitXor<bool> for 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for i16x32","synthetic":false,"types":["packed_simd::v512::i16x32"]},{"text":"impl BitXor<i16> for i16x32","synthetic":false,"types":["packed_simd::v512::i16x32"]},{"text":"impl BitXor<Simd<[i16; 32]>> for i16","synthetic":false,"types":[]},{"text":"impl BitXor<Simd<[u16; 32]>> for u16x32","synthetic":false,"types":["packed_simd::v512::u16x32"]},{"text":"impl BitXor<u16> for u16x32","synthetic":false,"types":["packed_simd::v512::u16x32"]},{"text":"impl BitXor<Simd<[u16; 32]>> for u16","synthetic":false,"types":[]},{"text":"impl BitXor<Simd<[m16; 32]>> for m16x32","synthetic":false,"types":["packed_simd::v512::m16x32"]},{"text":"impl BitXor<bool> for m16x32","synthetic":false,"types":["packed_simd::v512::m16x32"]},{"text":"impl BitXor<Simd<[m16; 32]>> for bool","synthetic":false,"types":[]},{"text":"impl BitXor<Simd<[i32; 16]>> for i32x16","synthetic":false,"types":["packed_simd::v512::i32x16"]},{"text":"impl BitXor<i32> for i32x16","synthetic":false,"types":["packed_simd::v512::i32x16"]},{"text":"impl BitXor<Simd<[i32; 16]>> for i32","synthetic":false,"types":[]},{"text":"impl BitXor<Simd<[u32; 16]>> for u32x16","synthetic":false,"types":["packed_simd::v512::u32x16"]},{"text":"impl BitXor<u32> for u32x16","synthetic":false,"types":["packed_simd::v512::u32x16"]},{"text":"impl BitXor<Simd<[u32; 16]>> for u32","synthetic":false,"types":[]},{"text":"impl BitXor<Simd<[m32; 16]>> for m32x16","synthetic":false,"types":["packed_simd::v512::m32x16"]},{"text":"impl BitXor<bool> for m32x16","synthetic":false,"types":["packed_simd::v512::m32x16"]},{"text":"impl BitXor<Simd<[m32; 16]>> for bool","synthetic":false,"types":[]},{"text":"impl BitXor<Simd<[i64; 8]>> for i64x8","synthetic":false,"types":["packed_simd::v512::i64x8"]},{"text":"impl BitXor<i64> for i64x8","synthetic":false,"types":["packed_simd::v512::i64x8"]},{"text":"impl BitXor<Simd<[i64; 8]>> for i64","synthetic":false,"types":[]},{"text":"impl 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usize","synthetic":false,"types":[]},{"text":"impl BitXor<Simd<[msize; 2]>> for msizex2","synthetic":false,"types":["packed_simd::vSize::msizex2"]},{"text":"impl BitXor<bool> for msizex2","synthetic":false,"types":["packed_simd::vSize::msizex2"]},{"text":"impl BitXor<Simd<[msize; 2]>> for bool","synthetic":false,"types":[]},{"text":"impl BitXor<Simd<[isize; 4]>> for isizex4","synthetic":false,"types":["packed_simd::vSize::isizex4"]},{"text":"impl BitXor<isize> for isizex4","synthetic":false,"types":["packed_simd::vSize::isizex4"]},{"text":"impl BitXor<Simd<[isize; 4]>> for isize","synthetic":false,"types":[]},{"text":"impl BitXor<Simd<[usize; 4]>> for usizex4","synthetic":false,"types":["packed_simd::vSize::usizex4"]},{"text":"impl BitXor<usize> for usizex4","synthetic":false,"types":["packed_simd::vSize::usizex4"]},{"text":"impl BitXor<Simd<[usize; 4]>> for usize","synthetic":false,"types":[]},{"text":"impl BitXor<Simd<[msize; 4]>> for msizex4","synthetic":false,"types":["packed_simd::vSize::msizex4"]},{"text":"impl BitXor<bool> for msizex4","synthetic":false,"types":["packed_simd::vSize::msizex4"]},{"text":"impl BitXor<Simd<[msize; 4]>> for bool","synthetic":false,"types":[]},{"text":"impl BitXor<Simd<[isize; 8]>> for isizex8","synthetic":false,"types":["packed_simd::vSize::isizex8"]},{"text":"impl BitXor<isize> for isizex8","synthetic":false,"types":["packed_simd::vSize::isizex8"]},{"text":"impl BitXor<Simd<[isize; 8]>> for isize","synthetic":false,"types":[]},{"text":"impl BitXor<Simd<[usize; 8]>> for usizex8","synthetic":false,"types":["packed_simd::vSize::usizex8"]},{"text":"impl BitXor<usize> for usizex8","synthetic":false,"types":["packed_simd::vSize::usizex8"]},{"text":"impl BitXor<Simd<[usize; 8]>> for usize","synthetic":false,"types":[]},{"text":"impl BitXor<Simd<[msize; 8]>> for msizex8","synthetic":false,"types":["packed_simd::vSize::msizex8"]},{"text":"impl BitXor<bool> for msizex8","synthetic":false,"types":["packed_simd::vSize::msizex8"]},{"text":"impl BitXor<Simd<[msize; 8]>> for bool","synthetic":false,"types":[]}]; +if (window.register_implementors) {window.register_implementors(implementors);} else {window.pending_implementors = implementors;}})() \ No newline at end of file diff --git a/implementors/core/ops/bit/trait.BitXorAssign.js b/implementors/core/ops/bit/trait.BitXorAssign.js new file mode 100644 index 000000000..6ebdfff7d --- /dev/null +++ b/implementors/core/ops/bit/trait.BitXorAssign.js @@ -0,0 +1,3 @@ +(function() {var implementors = {}; +implementors["packed_simd"] = [{"text":"impl BitXorAssign<Simd<[i8; 2]>> for i8x2","synthetic":false,"types":["packed_simd::v16::i8x2"]},{"text":"impl BitXorAssign<i8> for i8x2","synthetic":false,"types":["packed_simd::v16::i8x2"]},{"text":"impl BitXorAssign<Simd<[u8; 2]>> for u8x2","synthetic":false,"types":["packed_simd::v16::u8x2"]},{"text":"impl BitXorAssign<u8> for u8x2","synthetic":false,"types":["packed_simd::v16::u8x2"]},{"text":"impl BitXorAssign<Simd<[m8; 2]>> for m8x2","synthetic":false,"types":["packed_simd::v16::m8x2"]},{"text":"impl BitXorAssign<bool> for m8x2","synthetic":false,"types":["packed_simd::v16::m8x2"]},{"text":"impl BitXorAssign<Simd<[i8; 4]>> for i8x4","synthetic":false,"types":["packed_simd::v32::i8x4"]},{"text":"impl BitXorAssign<i8> for i8x4","synthetic":false,"types":["packed_simd::v32::i8x4"]},{"text":"impl BitXorAssign<Simd<[u8; 4]>> for u8x4","synthetic":false,"types":["packed_simd::v32::u8x4"]},{"text":"impl BitXorAssign<u8> for u8x4","synthetic":false,"types":["packed_simd::v32::u8x4"]},{"text":"impl BitXorAssign<Simd<[m8; 4]>> for m8x4","synthetic":false,"types":["packed_simd::v32::m8x4"]},{"text":"impl BitXorAssign<bool> for m8x4","synthetic":false,"types":["packed_simd::v32::m8x4"]},{"text":"impl BitXorAssign<Simd<[i16; 2]>> for i16x2","synthetic":false,"types":["packed_simd::v32::i16x2"]},{"text":"impl BitXorAssign<i16> for i16x2","synthetic":false,"types":["packed_simd::v32::i16x2"]},{"text":"impl BitXorAssign<Simd<[u16; 2]>> for u16x2","synthetic":false,"types":["packed_simd::v32::u16x2"]},{"text":"impl BitXorAssign<u16> for u16x2","synthetic":false,"types":["packed_simd::v32::u16x2"]},{"text":"impl BitXorAssign<Simd<[m16; 2]>> for m16x2","synthetic":false,"types":["packed_simd::v32::m16x2"]},{"text":"impl BitXorAssign<bool> for m16x2","synthetic":false,"types":["packed_simd::v32::m16x2"]},{"text":"impl BitXorAssign<Simd<[i8; 8]>> for i8x8","synthetic":false,"types":["packed_simd::v64::i8x8"]},{"text":"impl BitXorAssign<i8> for i8x8","synthetic":false,"types":["packed_simd::v64::i8x8"]},{"text":"impl BitXorAssign<Simd<[u8; 8]>> for u8x8","synthetic":false,"types":["packed_simd::v64::u8x8"]},{"text":"impl BitXorAssign<u8> for u8x8","synthetic":false,"types":["packed_simd::v64::u8x8"]},{"text":"impl BitXorAssign<Simd<[m8; 8]>> for m8x8","synthetic":false,"types":["packed_simd::v64::m8x8"]},{"text":"impl BitXorAssign<bool> for m8x8","synthetic":false,"types":["packed_simd::v64::m8x8"]},{"text":"impl BitXorAssign<Simd<[i16; 4]>> for i16x4","synthetic":false,"types":["packed_simd::v64::i16x4"]},{"text":"impl BitXorAssign<i16> for i16x4","synthetic":false,"types":["packed_simd::v64::i16x4"]},{"text":"impl BitXorAssign<Simd<[u16; 4]>> for u16x4","synthetic":false,"types":["packed_simd::v64::u16x4"]},{"text":"impl BitXorAssign<u16> for u16x4","synthetic":false,"types":["packed_simd::v64::u16x4"]},{"text":"impl BitXorAssign<Simd<[m16; 4]>> for m16x4","synthetic":false,"types":["packed_simd::v64::m16x4"]},{"text":"impl BitXorAssign<bool> for m16x4","synthetic":false,"types":["packed_simd::v64::m16x4"]},{"text":"impl BitXorAssign<Simd<[i32; 2]>> for i32x2","synthetic":false,"types":["packed_simd::v64::i32x2"]},{"text":"impl BitXorAssign<i32> for i32x2","synthetic":false,"types":["packed_simd::v64::i32x2"]},{"text":"impl BitXorAssign<Simd<[u32; 2]>> for u32x2","synthetic":false,"types":["packed_simd::v64::u32x2"]},{"text":"impl BitXorAssign<u32> for u32x2","synthetic":false,"types":["packed_simd::v64::u32x2"]},{"text":"impl BitXorAssign<Simd<[m32; 2]>> for m32x2","synthetic":false,"types":["packed_simd::v64::m32x2"]},{"text":"impl BitXorAssign<bool> for m32x2","synthetic":false,"types":["packed_simd::v64::m32x2"]},{"text":"impl BitXorAssign<Simd<[i8; 16]>> for i8x16","synthetic":false,"types":["packed_simd::v128::i8x16"]},{"text":"impl BitXorAssign<i8> for i8x16","synthetic":false,"types":["packed_simd::v128::i8x16"]},{"text":"impl BitXorAssign<Simd<[u8; 16]>> for u8x16","synthetic":false,"types":["packed_simd::v128::u8x16"]},{"text":"impl BitXorAssign<u8> for u8x16","synthetic":false,"types":["packed_simd::v128::u8x16"]},{"text":"impl BitXorAssign<Simd<[m8; 16]>> for m8x16","synthetic":false,"types":["packed_simd::v128::m8x16"]},{"text":"impl BitXorAssign<bool> for m8x16","synthetic":false,"types":["packed_simd::v128::m8x16"]},{"text":"impl BitXorAssign<Simd<[i16; 8]>> for i16x8","synthetic":false,"types":["packed_simd::v128::i16x8"]},{"text":"impl BitXorAssign<i16> for i16x8","synthetic":false,"types":["packed_simd::v128::i16x8"]},{"text":"impl BitXorAssign<Simd<[u16; 8]>> for u16x8","synthetic":false,"types":["packed_simd::v128::u16x8"]},{"text":"impl BitXorAssign<u16> for u16x8","synthetic":false,"types":["packed_simd::v128::u16x8"]},{"text":"impl BitXorAssign<Simd<[m16; 8]>> for m16x8","synthetic":false,"types":["packed_simd::v128::m16x8"]},{"text":"impl BitXorAssign<bool> for m16x8","synthetic":false,"types":["packed_simd::v128::m16x8"]},{"text":"impl BitXorAssign<Simd<[i32; 4]>> for i32x4","synthetic":false,"types":["packed_simd::v128::i32x4"]},{"text":"impl BitXorAssign<i32> for i32x4","synthetic":false,"types":["packed_simd::v128::i32x4"]},{"text":"impl BitXorAssign<Simd<[u32; 4]>> for u32x4","synthetic":false,"types":["packed_simd::v128::u32x4"]},{"text":"impl BitXorAssign<u32> for u32x4","synthetic":false,"types":["packed_simd::v128::u32x4"]},{"text":"impl BitXorAssign<Simd<[m32; 4]>> for m32x4","synthetic":false,"types":["packed_simd::v128::m32x4"]},{"text":"impl BitXorAssign<bool> for m32x4","synthetic":false,"types":["packed_simd::v128::m32x4"]},{"text":"impl BitXorAssign<Simd<[i64; 2]>> for i64x2","synthetic":false,"types":["packed_simd::v128::i64x2"]},{"text":"impl BitXorAssign<i64> for i64x2","synthetic":false,"types":["packed_simd::v128::i64x2"]},{"text":"impl BitXorAssign<Simd<[u64; 2]>> for u64x2","synthetic":false,"types":["packed_simd::v128::u64x2"]},{"text":"impl BitXorAssign<u64> for u64x2","synthetic":false,"types":["packed_simd::v128::u64x2"]},{"text":"impl BitXorAssign<Simd<[m64; 2]>> for m64x2","synthetic":false,"types":["packed_simd::v128::m64x2"]},{"text":"impl BitXorAssign<bool> for m64x2","synthetic":false,"types":["packed_simd::v128::m64x2"]},{"text":"impl BitXorAssign<Simd<[i128; 1]>> for i128x1","synthetic":false,"types":["packed_simd::v128::i128x1"]},{"text":"impl BitXorAssign<i128> for i128x1","synthetic":false,"types":["packed_simd::v128::i128x1"]},{"text":"impl BitXorAssign<Simd<[u128; 1]>> for u128x1","synthetic":false,"types":["packed_simd::v128::u128x1"]},{"text":"impl BitXorAssign<u128> for u128x1","synthetic":false,"types":["packed_simd::v128::u128x1"]},{"text":"impl BitXorAssign<Simd<[m128; 1]>> for m128x1","synthetic":false,"types":["packed_simd::v128::m128x1"]},{"text":"impl BitXorAssign<bool> for m128x1","synthetic":false,"types":["packed_simd::v128::m128x1"]},{"text":"impl BitXorAssign<Simd<[i8; 32]>> for i8x32","synthetic":false,"types":["packed_simd::v256::i8x32"]},{"text":"impl BitXorAssign<i8> for i8x32","synthetic":false,"types":["packed_simd::v256::i8x32"]},{"text":"impl BitXorAssign<Simd<[u8; 32]>> for u8x32","synthetic":false,"types":["packed_simd::v256::u8x32"]},{"text":"impl BitXorAssign<u8> for u8x32","synthetic":false,"types":["packed_simd::v256::u8x32"]},{"text":"impl BitXorAssign<Simd<[m8; 32]>> for m8x32","synthetic":false,"types":["packed_simd::v256::m8x32"]},{"text":"impl BitXorAssign<bool> for m8x32","synthetic":false,"types":["packed_simd::v256::m8x32"]},{"text":"impl BitXorAssign<Simd<[i16; 16]>> for i16x16","synthetic":false,"types":["packed_simd::v256::i16x16"]},{"text":"impl BitXorAssign<i16> for i16x16","synthetic":false,"types":["packed_simd::v256::i16x16"]},{"text":"impl BitXorAssign<Simd<[u16; 16]>> for u16x16","synthetic":false,"types":["packed_simd::v256::u16x16"]},{"text":"impl BitXorAssign<u16> for u16x16","synthetic":false,"types":["packed_simd::v256::u16x16"]},{"text":"impl BitXorAssign<Simd<[m16; 16]>> for m16x16","synthetic":false,"types":["packed_simd::v256::m16x16"]},{"text":"impl BitXorAssign<bool> for m16x16","synthetic":false,"types":["packed_simd::v256::m16x16"]},{"text":"impl BitXorAssign<Simd<[i32; 8]>> for i32x8","synthetic":false,"types":["packed_simd::v256::i32x8"]},{"text":"impl BitXorAssign<i32> for i32x8","synthetic":false,"types":["packed_simd::v256::i32x8"]},{"text":"impl BitXorAssign<Simd<[u32; 8]>> for u32x8","synthetic":false,"types":["packed_simd::v256::u32x8"]},{"text":"impl BitXorAssign<u32> for u32x8","synthetic":false,"types":["packed_simd::v256::u32x8"]},{"text":"impl BitXorAssign<Simd<[m32; 8]>> for m32x8","synthetic":false,"types":["packed_simd::v256::m32x8"]},{"text":"impl BitXorAssign<bool> for m32x8","synthetic":false,"types":["packed_simd::v256::m32x8"]},{"text":"impl BitXorAssign<Simd<[i64; 4]>> for i64x4","synthetic":false,"types":["packed_simd::v256::i64x4"]},{"text":"impl BitXorAssign<i64> for i64x4","synthetic":false,"types":["packed_simd::v256::i64x4"]},{"text":"impl BitXorAssign<Simd<[u64; 4]>> for u64x4","synthetic":false,"types":["packed_simd::v256::u64x4"]},{"text":"impl BitXorAssign<u64> for u64x4","synthetic":false,"types":["packed_simd::v256::u64x4"]},{"text":"impl BitXorAssign<Simd<[m64; 4]>> for m64x4","synthetic":false,"types":["packed_simd::v256::m64x4"]},{"text":"impl BitXorAssign<bool> for m64x4","synthetic":false,"types":["packed_simd::v256::m64x4"]},{"text":"impl BitXorAssign<Simd<[i128; 2]>> for i128x2","synthetic":false,"types":["packed_simd::v256::i128x2"]},{"text":"impl BitXorAssign<i128> for i128x2","synthetic":false,"types":["packed_simd::v256::i128x2"]},{"text":"impl BitXorAssign<Simd<[u128; 2]>> for u128x2","synthetic":false,"types":["packed_simd::v256::u128x2"]},{"text":"impl BitXorAssign<u128> for u128x2","synthetic":false,"types":["packed_simd::v256::u128x2"]},{"text":"impl BitXorAssign<Simd<[m128; 2]>> for m128x2","synthetic":false,"types":["packed_simd::v256::m128x2"]},{"text":"impl BitXorAssign<bool> for m128x2","synthetic":false,"types":["packed_simd::v256::m128x2"]},{"text":"impl BitXorAssign<Simd<[i8; 64]>> for i8x64","synthetic":false,"types":["packed_simd::v512::i8x64"]},{"text":"impl BitXorAssign<i8> for i8x64","synthetic":false,"types":["packed_simd::v512::i8x64"]},{"text":"impl BitXorAssign<Simd<[u8; 64]>> for u8x64","synthetic":false,"types":["packed_simd::v512::u8x64"]},{"text":"impl BitXorAssign<u8> for u8x64","synthetic":false,"types":["packed_simd::v512::u8x64"]},{"text":"impl BitXorAssign<Simd<[m8; 64]>> for m8x64","synthetic":false,"types":["packed_simd::v512::m8x64"]},{"text":"impl BitXorAssign<bool> for m8x64","synthetic":false,"types":["packed_simd::v512::m8x64"]},{"text":"impl BitXorAssign<Simd<[i16; 32]>> for i16x32","synthetic":false,"types":["packed_simd::v512::i16x32"]},{"text":"impl BitXorAssign<i16> for i16x32","synthetic":false,"types":["packed_simd::v512::i16x32"]},{"text":"impl BitXorAssign<Simd<[u16; 32]>> for u16x32","synthetic":false,"types":["packed_simd::v512::u16x32"]},{"text":"impl BitXorAssign<u16> for u16x32","synthetic":false,"types":["packed_simd::v512::u16x32"]},{"text":"impl BitXorAssign<Simd<[m16; 32]>> for m16x32","synthetic":false,"types":["packed_simd::v512::m16x32"]},{"text":"impl BitXorAssign<bool> for m16x32","synthetic":false,"types":["packed_simd::v512::m16x32"]},{"text":"impl BitXorAssign<Simd<[i32; 16]>> for i32x16","synthetic":false,"types":["packed_simd::v512::i32x16"]},{"text":"impl BitXorAssign<i32> for i32x16","synthetic":false,"types":["packed_simd::v512::i32x16"]},{"text":"impl BitXorAssign<Simd<[u32; 16]>> for u32x16","synthetic":false,"types":["packed_simd::v512::u32x16"]},{"text":"impl BitXorAssign<u32> for u32x16","synthetic":false,"types":["packed_simd::v512::u32x16"]},{"text":"impl BitXorAssign<Simd<[m32; 16]>> for m32x16","synthetic":false,"types":["packed_simd::v512::m32x16"]},{"text":"impl BitXorAssign<bool> for m32x16","synthetic":false,"types":["packed_simd::v512::m32x16"]},{"text":"impl BitXorAssign<Simd<[i64; 8]>> for i64x8","synthetic":false,"types":["packed_simd::v512::i64x8"]},{"text":"impl BitXorAssign<i64> for i64x8","synthetic":false,"types":["packed_simd::v512::i64x8"]},{"text":"impl BitXorAssign<Simd<[u64; 8]>> for u64x8","synthetic":false,"types":["packed_simd::v512::u64x8"]},{"text":"impl BitXorAssign<u64> for u64x8","synthetic":false,"types":["packed_simd::v512::u64x8"]},{"text":"impl BitXorAssign<Simd<[m64; 8]>> for m64x8","synthetic":false,"types":["packed_simd::v512::m64x8"]},{"text":"impl BitXorAssign<bool> for m64x8","synthetic":false,"types":["packed_simd::v512::m64x8"]},{"text":"impl BitXorAssign<Simd<[i128; 4]>> for i128x4","synthetic":false,"types":["packed_simd::v512::i128x4"]},{"text":"impl BitXorAssign<i128> for i128x4","synthetic":false,"types":["packed_simd::v512::i128x4"]},{"text":"impl BitXorAssign<Simd<[u128; 4]>> for u128x4","synthetic":false,"types":["packed_simd::v512::u128x4"]},{"text":"impl BitXorAssign<u128> for u128x4","synthetic":false,"types":["packed_simd::v512::u128x4"]},{"text":"impl BitXorAssign<Simd<[m128; 4]>> for m128x4","synthetic":false,"types":["packed_simd::v512::m128x4"]},{"text":"impl BitXorAssign<bool> for m128x4","synthetic":false,"types":["packed_simd::v512::m128x4"]},{"text":"impl BitXorAssign<Simd<[isize; 2]>> for isizex2","synthetic":false,"types":["packed_simd::vSize::isizex2"]},{"text":"impl BitXorAssign<isize> for isizex2","synthetic":false,"types":["packed_simd::vSize::isizex2"]},{"text":"impl BitXorAssign<Simd<[usize; 2]>> for usizex2","synthetic":false,"types":["packed_simd::vSize::usizex2"]},{"text":"impl BitXorAssign<usize> for usizex2","synthetic":false,"types":["packed_simd::vSize::usizex2"]},{"text":"impl BitXorAssign<Simd<[msize; 2]>> for msizex2","synthetic":false,"types":["packed_simd::vSize::msizex2"]},{"text":"impl BitXorAssign<bool> for msizex2","synthetic":false,"types":["packed_simd::vSize::msizex2"]},{"text":"impl BitXorAssign<Simd<[isize; 4]>> for isizex4","synthetic":false,"types":["packed_simd::vSize::isizex4"]},{"text":"impl BitXorAssign<isize> for isizex4","synthetic":false,"types":["packed_simd::vSize::isizex4"]},{"text":"impl BitXorAssign<Simd<[usize; 4]>> for usizex4","synthetic":false,"types":["packed_simd::vSize::usizex4"]},{"text":"impl BitXorAssign<usize> for usizex4","synthetic":false,"types":["packed_simd::vSize::usizex4"]},{"text":"impl BitXorAssign<Simd<[msize; 4]>> for msizex4","synthetic":false,"types":["packed_simd::vSize::msizex4"]},{"text":"impl BitXorAssign<bool> for msizex4","synthetic":false,"types":["packed_simd::vSize::msizex4"]},{"text":"impl BitXorAssign<Simd<[isize; 8]>> for isizex8","synthetic":false,"types":["packed_simd::vSize::isizex8"]},{"text":"impl BitXorAssign<isize> for isizex8","synthetic":false,"types":["packed_simd::vSize::isizex8"]},{"text":"impl BitXorAssign<Simd<[usize; 8]>> for usizex8","synthetic":false,"types":["packed_simd::vSize::usizex8"]},{"text":"impl BitXorAssign<usize> for usizex8","synthetic":false,"types":["packed_simd::vSize::usizex8"]},{"text":"impl BitXorAssign<Simd<[msize; 8]>> for msizex8","synthetic":false,"types":["packed_simd::vSize::msizex8"]},{"text":"impl BitXorAssign<bool> for msizex8","synthetic":false,"types":["packed_simd::vSize::msizex8"]}]; +if (window.register_implementors) {window.register_implementors(implementors);} else {window.pending_implementors = implementors;}})() \ No newline at end of file diff --git a/implementors/core/ops/bit/trait.Not.js b/implementors/core/ops/bit/trait.Not.js new file mode 100644 index 000000000..2d27be379 --- /dev/null +++ b/implementors/core/ops/bit/trait.Not.js @@ -0,0 +1,3 @@ +(function() {var implementors = {}; +implementors["packed_simd"] = [{"text":"impl Not for i8x2","synthetic":false,"types":["packed_simd::v16::i8x2"]},{"text":"impl Not for u8x2","synthetic":false,"types":["packed_simd::v16::u8x2"]},{"text":"impl Not for m8x2","synthetic":false,"types":["packed_simd::v16::m8x2"]},{"text":"impl Not for i8x4","synthetic":false,"types":["packed_simd::v32::i8x4"]},{"text":"impl Not for u8x4","synthetic":false,"types":["packed_simd::v32::u8x4"]},{"text":"impl Not for m8x4","synthetic":false,"types":["packed_simd::v32::m8x4"]},{"text":"impl Not for i16x2","synthetic":false,"types":["packed_simd::v32::i16x2"]},{"text":"impl Not for u16x2","synthetic":false,"types":["packed_simd::v32::u16x2"]},{"text":"impl Not for m16x2","synthetic":false,"types":["packed_simd::v32::m16x2"]},{"text":"impl Not for i8x8","synthetic":false,"types":["packed_simd::v64::i8x8"]},{"text":"impl Not for u8x8","synthetic":false,"types":["packed_simd::v64::u8x8"]},{"text":"impl Not for m8x8","synthetic":false,"types":["packed_simd::v64::m8x8"]},{"text":"impl Not for i16x4","synthetic":false,"types":["packed_simd::v64::i16x4"]},{"text":"impl Not for u16x4","synthetic":false,"types":["packed_simd::v64::u16x4"]},{"text":"impl Not for m16x4","synthetic":false,"types":["packed_simd::v64::m16x4"]},{"text":"impl Not for i32x2","synthetic":false,"types":["packed_simd::v64::i32x2"]},{"text":"impl Not for u32x2","synthetic":false,"types":["packed_simd::v64::u32x2"]},{"text":"impl Not for m32x2","synthetic":false,"types":["packed_simd::v64::m32x2"]},{"text":"impl Not for i8x16","synthetic":false,"types":["packed_simd::v128::i8x16"]},{"text":"impl Not for u8x16","synthetic":false,"types":["packed_simd::v128::u8x16"]},{"text":"impl Not for m8x16","synthetic":false,"types":["packed_simd::v128::m8x16"]},{"text":"impl Not for i16x8","synthetic":false,"types":["packed_simd::v128::i16x8"]},{"text":"impl Not for u16x8","synthetic":false,"types":["packed_simd::v128::u16x8"]},{"text":"impl Not for m16x8","synthetic":false,"types":["packed_simd::v128::m16x8"]},{"text":"impl Not for i32x4","synthetic":false,"types":["packed_simd::v128::i32x4"]},{"text":"impl Not for u32x4","synthetic":false,"types":["packed_simd::v128::u32x4"]},{"text":"impl Not for m32x4","synthetic":false,"types":["packed_simd::v128::m32x4"]},{"text":"impl Not for i64x2","synthetic":false,"types":["packed_simd::v128::i64x2"]},{"text":"impl Not for u64x2","synthetic":false,"types":["packed_simd::v128::u64x2"]},{"text":"impl Not for m64x2","synthetic":false,"types":["packed_simd::v128::m64x2"]},{"text":"impl Not for i128x1","synthetic":false,"types":["packed_simd::v128::i128x1"]},{"text":"impl Not for u128x1","synthetic":false,"types":["packed_simd::v128::u128x1"]},{"text":"impl Not for m128x1","synthetic":false,"types":["packed_simd::v128::m128x1"]},{"text":"impl Not for i8x32","synthetic":false,"types":["packed_simd::v256::i8x32"]},{"text":"impl Not for u8x32","synthetic":false,"types":["packed_simd::v256::u8x32"]},{"text":"impl Not for m8x32","synthetic":false,"types":["packed_simd::v256::m8x32"]},{"text":"impl Not for i16x16","synthetic":false,"types":["packed_simd::v256::i16x16"]},{"text":"impl Not for u16x16","synthetic":false,"types":["packed_simd::v256::u16x16"]},{"text":"impl Not for m16x16","synthetic":false,"types":["packed_simd::v256::m16x16"]},{"text":"impl Not for i32x8","synthetic":false,"types":["packed_simd::v256::i32x8"]},{"text":"impl Not for u32x8","synthetic":false,"types":["packed_simd::v256::u32x8"]},{"text":"impl Not for m32x8","synthetic":false,"types":["packed_simd::v256::m32x8"]},{"text":"impl Not for i64x4","synthetic":false,"types":["packed_simd::v256::i64x4"]},{"text":"impl Not for u64x4","synthetic":false,"types":["packed_simd::v256::u64x4"]},{"text":"impl Not for m64x4","synthetic":false,"types":["packed_simd::v256::m64x4"]},{"text":"impl Not for i128x2","synthetic":false,"types":["packed_simd::v256::i128x2"]},{"text":"impl Not for u128x2","synthetic":false,"types":["packed_simd::v256::u128x2"]},{"text":"impl Not for m128x2","synthetic":false,"types":["packed_simd::v256::m128x2"]},{"text":"impl Not for i8x64","synthetic":false,"types":["packed_simd::v512::i8x64"]},{"text":"impl Not for u8x64","synthetic":false,"types":["packed_simd::v512::u8x64"]},{"text":"impl Not for m8x64","synthetic":false,"types":["packed_simd::v512::m8x64"]},{"text":"impl Not for i16x32","synthetic":false,"types":["packed_simd::v512::i16x32"]},{"text":"impl Not for u16x32","synthetic":false,"types":["packed_simd::v512::u16x32"]},{"text":"impl Not for m16x32","synthetic":false,"types":["packed_simd::v512::m16x32"]},{"text":"impl Not for i32x16","synthetic":false,"types":["packed_simd::v512::i32x16"]},{"text":"impl Not for u32x16","synthetic":false,"types":["packed_simd::v512::u32x16"]},{"text":"impl Not for m32x16","synthetic":false,"types":["packed_simd::v512::m32x16"]},{"text":"impl Not for i64x8","synthetic":false,"types":["packed_simd::v512::i64x8"]},{"text":"impl Not for u64x8","synthetic":false,"types":["packed_simd::v512::u64x8"]},{"text":"impl Not for m64x8","synthetic":false,"types":["packed_simd::v512::m64x8"]},{"text":"impl Not for i128x4","synthetic":false,"types":["packed_simd::v512::i128x4"]},{"text":"impl Not for u128x4","synthetic":false,"types":["packed_simd::v512::u128x4"]},{"text":"impl Not for m128x4","synthetic":false,"types":["packed_simd::v512::m128x4"]},{"text":"impl Not for isizex2","synthetic":false,"types":["packed_simd::vSize::isizex2"]},{"text":"impl Not for usizex2","synthetic":false,"types":["packed_simd::vSize::usizex2"]},{"text":"impl Not for msizex2","synthetic":false,"types":["packed_simd::vSize::msizex2"]},{"text":"impl Not for isizex4","synthetic":false,"types":["packed_simd::vSize::isizex4"]},{"text":"impl Not for usizex4","synthetic":false,"types":["packed_simd::vSize::usizex4"]},{"text":"impl Not for msizex4","synthetic":false,"types":["packed_simd::vSize::msizex4"]},{"text":"impl Not for isizex8","synthetic":false,"types":["packed_simd::vSize::isizex8"]},{"text":"impl Not for usizex8","synthetic":false,"types":["packed_simd::vSize::usizex8"]},{"text":"impl Not for msizex8","synthetic":false,"types":["packed_simd::vSize::msizex8"]}]; +if (window.register_implementors) {window.register_implementors(implementors);} else {window.pending_implementors = implementors;}})() \ No newline at end of file diff --git a/implementors/core/ops/bit/trait.Shl.js b/implementors/core/ops/bit/trait.Shl.js new file mode 100644 index 000000000..f1b9c7363 --- /dev/null +++ b/implementors/core/ops/bit/trait.Shl.js @@ -0,0 +1,3 @@ +(function() {var implementors = {}; +implementors["packed_simd"] = [{"text":"impl Shl<Simd<[i8; 2]>> for i8x2","synthetic":false,"types":["packed_simd::v16::i8x2"]},{"text":"impl Shl<u32> for i8x2","synthetic":false,"types":["packed_simd::v16::i8x2"]},{"text":"impl Shl<Simd<[u8; 2]>> for u8x2","synthetic":false,"types":["packed_simd::v16::u8x2"]},{"text":"impl Shl<u32> for u8x2","synthetic":false,"types":["packed_simd::v16::u8x2"]},{"text":"impl Shl<Simd<[i8; 4]>> for i8x4","synthetic":false,"types":["packed_simd::v32::i8x4"]},{"text":"impl Shl<u32> for i8x4","synthetic":false,"types":["packed_simd::v32::i8x4"]},{"text":"impl Shl<Simd<[u8; 4]>> for u8x4","synthetic":false,"types":["packed_simd::v32::u8x4"]},{"text":"impl Shl<u32> for u8x4","synthetic":false,"types":["packed_simd::v32::u8x4"]},{"text":"impl Shl<Simd<[i16; 2]>> for i16x2","synthetic":false,"types":["packed_simd::v32::i16x2"]},{"text":"impl Shl<u32> for i16x2","synthetic":false,"types":["packed_simd::v32::i16x2"]},{"text":"impl Shl<Simd<[u16; 2]>> for u16x2","synthetic":false,"types":["packed_simd::v32::u16x2"]},{"text":"impl Shl<u32> for u16x2","synthetic":false,"types":["packed_simd::v32::u16x2"]},{"text":"impl Shl<Simd<[i8; 8]>> for i8x8","synthetic":false,"types":["packed_simd::v64::i8x8"]},{"text":"impl Shl<u32> for i8x8","synthetic":false,"types":["packed_simd::v64::i8x8"]},{"text":"impl Shl<Simd<[u8; 8]>> for u8x8","synthetic":false,"types":["packed_simd::v64::u8x8"]},{"text":"impl Shl<u32> for u8x8","synthetic":false,"types":["packed_simd::v64::u8x8"]},{"text":"impl Shl<Simd<[i16; 4]>> for i16x4","synthetic":false,"types":["packed_simd::v64::i16x4"]},{"text":"impl Shl<u32> for i16x4","synthetic":false,"types":["packed_simd::v64::i16x4"]},{"text":"impl Shl<Simd<[u16; 4]>> for u16x4","synthetic":false,"types":["packed_simd::v64::u16x4"]},{"text":"impl Shl<u32> for u16x4","synthetic":false,"types":["packed_simd::v64::u16x4"]},{"text":"impl Shl<Simd<[i32; 2]>> for i32x2","synthetic":false,"types":["packed_simd::v64::i32x2"]},{"text":"impl Shl<u32> for i32x2","synthetic":false,"types":["packed_simd::v64::i32x2"]},{"text":"impl Shl<Simd<[u32; 2]>> for u32x2","synthetic":false,"types":["packed_simd::v64::u32x2"]},{"text":"impl Shl<u32> for u32x2","synthetic":false,"types":["packed_simd::v64::u32x2"]},{"text":"impl Shl<Simd<[i8; 16]>> for i8x16","synthetic":false,"types":["packed_simd::v128::i8x16"]},{"text":"impl Shl<u32> for i8x16","synthetic":false,"types":["packed_simd::v128::i8x16"]},{"text":"impl Shl<Simd<[u8; 16]>> for u8x16","synthetic":false,"types":["packed_simd::v128::u8x16"]},{"text":"impl Shl<u32> for u8x16","synthetic":false,"types":["packed_simd::v128::u8x16"]},{"text":"impl Shl<Simd<[i16; 8]>> for i16x8","synthetic":false,"types":["packed_simd::v128::i16x8"]},{"text":"impl Shl<u32> for i16x8","synthetic":false,"types":["packed_simd::v128::i16x8"]},{"text":"impl Shl<Simd<[u16; 8]>> for u16x8","synthetic":false,"types":["packed_simd::v128::u16x8"]},{"text":"impl Shl<u32> for u16x8","synthetic":false,"types":["packed_simd::v128::u16x8"]},{"text":"impl Shl<Simd<[i32; 4]>> for i32x4","synthetic":false,"types":["packed_simd::v128::i32x4"]},{"text":"impl Shl<u32> for i32x4","synthetic":false,"types":["packed_simd::v128::i32x4"]},{"text":"impl Shl<Simd<[u32; 4]>> for u32x4","synthetic":false,"types":["packed_simd::v128::u32x4"]},{"text":"impl Shl<u32> for u32x4","synthetic":false,"types":["packed_simd::v128::u32x4"]},{"text":"impl Shl<Simd<[i64; 2]>> for i64x2","synthetic":false,"types":["packed_simd::v128::i64x2"]},{"text":"impl Shl<u32> for i64x2","synthetic":false,"types":["packed_simd::v128::i64x2"]},{"text":"impl Shl<Simd<[u64; 2]>> for u64x2","synthetic":false,"types":["packed_simd::v128::u64x2"]},{"text":"impl Shl<u32> for u64x2","synthetic":false,"types":["packed_simd::v128::u64x2"]},{"text":"impl Shl<Simd<[i128; 1]>> for i128x1","synthetic":false,"types":["packed_simd::v128::i128x1"]},{"text":"impl Shl<u32> for i128x1","synthetic":false,"types":["packed_simd::v128::i128x1"]},{"text":"impl Shl<Simd<[u128; 1]>> for u128x1","synthetic":false,"types":["packed_simd::v128::u128x1"]},{"text":"impl Shl<u32> for u128x1","synthetic":false,"types":["packed_simd::v128::u128x1"]},{"text":"impl Shl<Simd<[i8; 32]>> for i8x32","synthetic":false,"types":["packed_simd::v256::i8x32"]},{"text":"impl Shl<u32> for i8x32","synthetic":false,"types":["packed_simd::v256::i8x32"]},{"text":"impl Shl<Simd<[u8; 32]>> for u8x32","synthetic":false,"types":["packed_simd::v256::u8x32"]},{"text":"impl Shl<u32> for u8x32","synthetic":false,"types":["packed_simd::v256::u8x32"]},{"text":"impl Shl<Simd<[i16; 16]>> for i16x16","synthetic":false,"types":["packed_simd::v256::i16x16"]},{"text":"impl Shl<u32> for i16x16","synthetic":false,"types":["packed_simd::v256::i16x16"]},{"text":"impl Shl<Simd<[u16; 16]>> for u16x16","synthetic":false,"types":["packed_simd::v256::u16x16"]},{"text":"impl Shl<u32> for u16x16","synthetic":false,"types":["packed_simd::v256::u16x16"]},{"text":"impl Shl<Simd<[i32; 8]>> for i32x8","synthetic":false,"types":["packed_simd::v256::i32x8"]},{"text":"impl Shl<u32> for i32x8","synthetic":false,"types":["packed_simd::v256::i32x8"]},{"text":"impl Shl<Simd<[u32; 8]>> for u32x8","synthetic":false,"types":["packed_simd::v256::u32x8"]},{"text":"impl Shl<u32> for u32x8","synthetic":false,"types":["packed_simd::v256::u32x8"]},{"text":"impl Shl<Simd<[i64; 4]>> for i64x4","synthetic":false,"types":["packed_simd::v256::i64x4"]},{"text":"impl Shl<u32> for i64x4","synthetic":false,"types":["packed_simd::v256::i64x4"]},{"text":"impl Shl<Simd<[u64; 4]>> for u64x4","synthetic":false,"types":["packed_simd::v256::u64x4"]},{"text":"impl Shl<u32> for u64x4","synthetic":false,"types":["packed_simd::v256::u64x4"]},{"text":"impl Shl<Simd<[i128; 2]>> for i128x2","synthetic":false,"types":["packed_simd::v256::i128x2"]},{"text":"impl Shl<u32> for i128x2","synthetic":false,"types":["packed_simd::v256::i128x2"]},{"text":"impl Shl<Simd<[u128; 2]>> for u128x2","synthetic":false,"types":["packed_simd::v256::u128x2"]},{"text":"impl Shl<u32> for u128x2","synthetic":false,"types":["packed_simd::v256::u128x2"]},{"text":"impl Shl<Simd<[i8; 64]>> for i8x64","synthetic":false,"types":["packed_simd::v512::i8x64"]},{"text":"impl Shl<u32> for i8x64","synthetic":false,"types":["packed_simd::v512::i8x64"]},{"text":"impl Shl<Simd<[u8; 64]>> for u8x64","synthetic":false,"types":["packed_simd::v512::u8x64"]},{"text":"impl Shl<u32> for u8x64","synthetic":false,"types":["packed_simd::v512::u8x64"]},{"text":"impl Shl<Simd<[i16; 32]>> for i16x32","synthetic":false,"types":["packed_simd::v512::i16x32"]},{"text":"impl Shl<u32> for i16x32","synthetic":false,"types":["packed_simd::v512::i16x32"]},{"text":"impl Shl<Simd<[u16; 32]>> for u16x32","synthetic":false,"types":["packed_simd::v512::u16x32"]},{"text":"impl Shl<u32> for u16x32","synthetic":false,"types":["packed_simd::v512::u16x32"]},{"text":"impl Shl<Simd<[i32; 16]>> for i32x16","synthetic":false,"types":["packed_simd::v512::i32x16"]},{"text":"impl Shl<u32> for i32x16","synthetic":false,"types":["packed_simd::v512::i32x16"]},{"text":"impl Shl<Simd<[u32; 16]>> for u32x16","synthetic":false,"types":["packed_simd::v512::u32x16"]},{"text":"impl Shl<u32> for u32x16","synthetic":false,"types":["packed_simd::v512::u32x16"]},{"text":"impl Shl<Simd<[i64; 8]>> for i64x8","synthetic":false,"types":["packed_simd::v512::i64x8"]},{"text":"impl Shl<u32> for i64x8","synthetic":false,"types":["packed_simd::v512::i64x8"]},{"text":"impl Shl<Simd<[u64; 8]>> for u64x8","synthetic":false,"types":["packed_simd::v512::u64x8"]},{"text":"impl Shl<u32> for u64x8","synthetic":false,"types":["packed_simd::v512::u64x8"]},{"text":"impl Shl<Simd<[i128; 4]>> for i128x4","synthetic":false,"types":["packed_simd::v512::i128x4"]},{"text":"impl Shl<u32> for i128x4","synthetic":false,"types":["packed_simd::v512::i128x4"]},{"text":"impl Shl<Simd<[u128; 4]>> for u128x4","synthetic":false,"types":["packed_simd::v512::u128x4"]},{"text":"impl Shl<u32> for u128x4","synthetic":false,"types":["packed_simd::v512::u128x4"]},{"text":"impl Shl<Simd<[isize; 2]>> for isizex2","synthetic":false,"types":["packed_simd::vSize::isizex2"]},{"text":"impl Shl<u32> for isizex2","synthetic":false,"types":["packed_simd::vSize::isizex2"]},{"text":"impl Shl<Simd<[usize; 2]>> for usizex2","synthetic":false,"types":["packed_simd::vSize::usizex2"]},{"text":"impl Shl<u32> for usizex2","synthetic":false,"types":["packed_simd::vSize::usizex2"]},{"text":"impl Shl<Simd<[isize; 4]>> for isizex4","synthetic":false,"types":["packed_simd::vSize::isizex4"]},{"text":"impl Shl<u32> for isizex4","synthetic":false,"types":["packed_simd::vSize::isizex4"]},{"text":"impl Shl<Simd<[usize; 4]>> for usizex4","synthetic":false,"types":["packed_simd::vSize::usizex4"]},{"text":"impl Shl<u32> for usizex4","synthetic":false,"types":["packed_simd::vSize::usizex4"]},{"text":"impl Shl<Simd<[isize; 8]>> for isizex8","synthetic":false,"types":["packed_simd::vSize::isizex8"]},{"text":"impl Shl<u32> for isizex8","synthetic":false,"types":["packed_simd::vSize::isizex8"]},{"text":"impl Shl<Simd<[usize; 8]>> for usizex8","synthetic":false,"types":["packed_simd::vSize::usizex8"]},{"text":"impl Shl<u32> for usizex8","synthetic":false,"types":["packed_simd::vSize::usizex8"]}]; +if (window.register_implementors) {window.register_implementors(implementors);} else {window.pending_implementors = implementors;}})() \ No newline at end of file diff --git a/implementors/core/ops/bit/trait.ShlAssign.js b/implementors/core/ops/bit/trait.ShlAssign.js new file mode 100644 index 000000000..a36b64f98 --- /dev/null +++ b/implementors/core/ops/bit/trait.ShlAssign.js @@ -0,0 +1,3 @@ +(function() {var implementors = {}; +implementors["packed_simd"] = [{"text":"impl ShlAssign<Simd<[i8; 2]>> for i8x2","synthetic":false,"types":["packed_simd::v16::i8x2"]},{"text":"impl ShlAssign<u32> for i8x2","synthetic":false,"types":["packed_simd::v16::i8x2"]},{"text":"impl ShlAssign<Simd<[u8; 2]>> for u8x2","synthetic":false,"types":["packed_simd::v16::u8x2"]},{"text":"impl ShlAssign<u32> for u8x2","synthetic":false,"types":["packed_simd::v16::u8x2"]},{"text":"impl ShlAssign<Simd<[i8; 4]>> for i8x4","synthetic":false,"types":["packed_simd::v32::i8x4"]},{"text":"impl ShlAssign<u32> for i8x4","synthetic":false,"types":["packed_simd::v32::i8x4"]},{"text":"impl ShlAssign<Simd<[u8; 4]>> for u8x4","synthetic":false,"types":["packed_simd::v32::u8x4"]},{"text":"impl ShlAssign<u32> for u8x4","synthetic":false,"types":["packed_simd::v32::u8x4"]},{"text":"impl ShlAssign<Simd<[i16; 2]>> for i16x2","synthetic":false,"types":["packed_simd::v32::i16x2"]},{"text":"impl ShlAssign<u32> for i16x2","synthetic":false,"types":["packed_simd::v32::i16x2"]},{"text":"impl ShlAssign<Simd<[u16; 2]>> for u16x2","synthetic":false,"types":["packed_simd::v32::u16x2"]},{"text":"impl ShlAssign<u32> for u16x2","synthetic":false,"types":["packed_simd::v32::u16x2"]},{"text":"impl ShlAssign<Simd<[i8; 8]>> for i8x8","synthetic":false,"types":["packed_simd::v64::i8x8"]},{"text":"impl ShlAssign<u32> for i8x8","synthetic":false,"types":["packed_simd::v64::i8x8"]},{"text":"impl ShlAssign<Simd<[u8; 8]>> for u8x8","synthetic":false,"types":["packed_simd::v64::u8x8"]},{"text":"impl ShlAssign<u32> for u8x8","synthetic":false,"types":["packed_simd::v64::u8x8"]},{"text":"impl ShlAssign<Simd<[i16; 4]>> for i16x4","synthetic":false,"types":["packed_simd::v64::i16x4"]},{"text":"impl ShlAssign<u32> for i16x4","synthetic":false,"types":["packed_simd::v64::i16x4"]},{"text":"impl ShlAssign<Simd<[u16; 4]>> for u16x4","synthetic":false,"types":["packed_simd::v64::u16x4"]},{"text":"impl ShlAssign<u32> for u16x4","synthetic":false,"types":["packed_simd::v64::u16x4"]},{"text":"impl ShlAssign<Simd<[i32; 2]>> for i32x2","synthetic":false,"types":["packed_simd::v64::i32x2"]},{"text":"impl ShlAssign<u32> for i32x2","synthetic":false,"types":["packed_simd::v64::i32x2"]},{"text":"impl ShlAssign<Simd<[u32; 2]>> for u32x2","synthetic":false,"types":["packed_simd::v64::u32x2"]},{"text":"impl ShlAssign<u32> for u32x2","synthetic":false,"types":["packed_simd::v64::u32x2"]},{"text":"impl ShlAssign<Simd<[i8; 16]>> for i8x16","synthetic":false,"types":["packed_simd::v128::i8x16"]},{"text":"impl ShlAssign<u32> for i8x16","synthetic":false,"types":["packed_simd::v128::i8x16"]},{"text":"impl ShlAssign<Simd<[u8; 16]>> for u8x16","synthetic":false,"types":["packed_simd::v128::u8x16"]},{"text":"impl ShlAssign<u32> for u8x16","synthetic":false,"types":["packed_simd::v128::u8x16"]},{"text":"impl ShlAssign<Simd<[i16; 8]>> for i16x8","synthetic":false,"types":["packed_simd::v128::i16x8"]},{"text":"impl ShlAssign<u32> for i16x8","synthetic":false,"types":["packed_simd::v128::i16x8"]},{"text":"impl ShlAssign<Simd<[u16; 8]>> for u16x8","synthetic":false,"types":["packed_simd::v128::u16x8"]},{"text":"impl ShlAssign<u32> for u16x8","synthetic":false,"types":["packed_simd::v128::u16x8"]},{"text":"impl ShlAssign<Simd<[i32; 4]>> for i32x4","synthetic":false,"types":["packed_simd::v128::i32x4"]},{"text":"impl ShlAssign<u32> for i32x4","synthetic":false,"types":["packed_simd::v128::i32x4"]},{"text":"impl ShlAssign<Simd<[u32; 4]>> for u32x4","synthetic":false,"types":["packed_simd::v128::u32x4"]},{"text":"impl ShlAssign<u32> for u32x4","synthetic":false,"types":["packed_simd::v128::u32x4"]},{"text":"impl ShlAssign<Simd<[i64; 2]>> for i64x2","synthetic":false,"types":["packed_simd::v128::i64x2"]},{"text":"impl ShlAssign<u32> for i64x2","synthetic":false,"types":["packed_simd::v128::i64x2"]},{"text":"impl ShlAssign<Simd<[u64; 2]>> for u64x2","synthetic":false,"types":["packed_simd::v128::u64x2"]},{"text":"impl ShlAssign<u32> for u64x2","synthetic":false,"types":["packed_simd::v128::u64x2"]},{"text":"impl ShlAssign<Simd<[i128; 1]>> for i128x1","synthetic":false,"types":["packed_simd::v128::i128x1"]},{"text":"impl ShlAssign<u32> for i128x1","synthetic":false,"types":["packed_simd::v128::i128x1"]},{"text":"impl ShlAssign<Simd<[u128; 1]>> for u128x1","synthetic":false,"types":["packed_simd::v128::u128x1"]},{"text":"impl ShlAssign<u32> for u128x1","synthetic":false,"types":["packed_simd::v128::u128x1"]},{"text":"impl ShlAssign<Simd<[i8; 32]>> for i8x32","synthetic":false,"types":["packed_simd::v256::i8x32"]},{"text":"impl ShlAssign<u32> for i8x32","synthetic":false,"types":["packed_simd::v256::i8x32"]},{"text":"impl ShlAssign<Simd<[u8; 32]>> for u8x32","synthetic":false,"types":["packed_simd::v256::u8x32"]},{"text":"impl ShlAssign<u32> for u8x32","synthetic":false,"types":["packed_simd::v256::u8x32"]},{"text":"impl ShlAssign<Simd<[i16; 16]>> for i16x16","synthetic":false,"types":["packed_simd::v256::i16x16"]},{"text":"impl ShlAssign<u32> for i16x16","synthetic":false,"types":["packed_simd::v256::i16x16"]},{"text":"impl ShlAssign<Simd<[u16; 16]>> for u16x16","synthetic":false,"types":["packed_simd::v256::u16x16"]},{"text":"impl ShlAssign<u32> for u16x16","synthetic":false,"types":["packed_simd::v256::u16x16"]},{"text":"impl ShlAssign<Simd<[i32; 8]>> for i32x8","synthetic":false,"types":["packed_simd::v256::i32x8"]},{"text":"impl ShlAssign<u32> for i32x8","synthetic":false,"types":["packed_simd::v256::i32x8"]},{"text":"impl ShlAssign<Simd<[u32; 8]>> for u32x8","synthetic":false,"types":["packed_simd::v256::u32x8"]},{"text":"impl ShlAssign<u32> for u32x8","synthetic":false,"types":["packed_simd::v256::u32x8"]},{"text":"impl ShlAssign<Simd<[i64; 4]>> for i64x4","synthetic":false,"types":["packed_simd::v256::i64x4"]},{"text":"impl ShlAssign<u32> for i64x4","synthetic":false,"types":["packed_simd::v256::i64x4"]},{"text":"impl ShlAssign<Simd<[u64; 4]>> for u64x4","synthetic":false,"types":["packed_simd::v256::u64x4"]},{"text":"impl ShlAssign<u32> for u64x4","synthetic":false,"types":["packed_simd::v256::u64x4"]},{"text":"impl ShlAssign<Simd<[i128; 2]>> for i128x2","synthetic":false,"types":["packed_simd::v256::i128x2"]},{"text":"impl ShlAssign<u32> for i128x2","synthetic":false,"types":["packed_simd::v256::i128x2"]},{"text":"impl ShlAssign<Simd<[u128; 2]>> for u128x2","synthetic":false,"types":["packed_simd::v256::u128x2"]},{"text":"impl ShlAssign<u32> for u128x2","synthetic":false,"types":["packed_simd::v256::u128x2"]},{"text":"impl ShlAssign<Simd<[i8; 64]>> for i8x64","synthetic":false,"types":["packed_simd::v512::i8x64"]},{"text":"impl ShlAssign<u32> for i8x64","synthetic":false,"types":["packed_simd::v512::i8x64"]},{"text":"impl ShlAssign<Simd<[u8; 64]>> for u8x64","synthetic":false,"types":["packed_simd::v512::u8x64"]},{"text":"impl ShlAssign<u32> for u8x64","synthetic":false,"types":["packed_simd::v512::u8x64"]},{"text":"impl ShlAssign<Simd<[i16; 32]>> for i16x32","synthetic":false,"types":["packed_simd::v512::i16x32"]},{"text":"impl ShlAssign<u32> for i16x32","synthetic":false,"types":["packed_simd::v512::i16x32"]},{"text":"impl ShlAssign<Simd<[u16; 32]>> for u16x32","synthetic":false,"types":["packed_simd::v512::u16x32"]},{"text":"impl ShlAssign<u32> for u16x32","synthetic":false,"types":["packed_simd::v512::u16x32"]},{"text":"impl ShlAssign<Simd<[i32; 16]>> for i32x16","synthetic":false,"types":["packed_simd::v512::i32x16"]},{"text":"impl ShlAssign<u32> for i32x16","synthetic":false,"types":["packed_simd::v512::i32x16"]},{"text":"impl ShlAssign<Simd<[u32; 16]>> for u32x16","synthetic":false,"types":["packed_simd::v512::u32x16"]},{"text":"impl ShlAssign<u32> for u32x16","synthetic":false,"types":["packed_simd::v512::u32x16"]},{"text":"impl ShlAssign<Simd<[i64; 8]>> for i64x8","synthetic":false,"types":["packed_simd::v512::i64x8"]},{"text":"impl ShlAssign<u32> for i64x8","synthetic":false,"types":["packed_simd::v512::i64x8"]},{"text":"impl ShlAssign<Simd<[u64; 8]>> for u64x8","synthetic":false,"types":["packed_simd::v512::u64x8"]},{"text":"impl ShlAssign<u32> for u64x8","synthetic":false,"types":["packed_simd::v512::u64x8"]},{"text":"impl ShlAssign<Simd<[i128; 4]>> for i128x4","synthetic":false,"types":["packed_simd::v512::i128x4"]},{"text":"impl ShlAssign<u32> for i128x4","synthetic":false,"types":["packed_simd::v512::i128x4"]},{"text":"impl ShlAssign<Simd<[u128; 4]>> for u128x4","synthetic":false,"types":["packed_simd::v512::u128x4"]},{"text":"impl ShlAssign<u32> for u128x4","synthetic":false,"types":["packed_simd::v512::u128x4"]},{"text":"impl ShlAssign<Simd<[isize; 2]>> for isizex2","synthetic":false,"types":["packed_simd::vSize::isizex2"]},{"text":"impl ShlAssign<u32> for isizex2","synthetic":false,"types":["packed_simd::vSize::isizex2"]},{"text":"impl ShlAssign<Simd<[usize; 2]>> for usizex2","synthetic":false,"types":["packed_simd::vSize::usizex2"]},{"text":"impl ShlAssign<u32> for usizex2","synthetic":false,"types":["packed_simd::vSize::usizex2"]},{"text":"impl ShlAssign<Simd<[isize; 4]>> for isizex4","synthetic":false,"types":["packed_simd::vSize::isizex4"]},{"text":"impl ShlAssign<u32> for isizex4","synthetic":false,"types":["packed_simd::vSize::isizex4"]},{"text":"impl ShlAssign<Simd<[usize; 4]>> for usizex4","synthetic":false,"types":["packed_simd::vSize::usizex4"]},{"text":"impl ShlAssign<u32> for usizex4","synthetic":false,"types":["packed_simd::vSize::usizex4"]},{"text":"impl ShlAssign<Simd<[isize; 8]>> for isizex8","synthetic":false,"types":["packed_simd::vSize::isizex8"]},{"text":"impl ShlAssign<u32> for isizex8","synthetic":false,"types":["packed_simd::vSize::isizex8"]},{"text":"impl ShlAssign<Simd<[usize; 8]>> for usizex8","synthetic":false,"types":["packed_simd::vSize::usizex8"]},{"text":"impl ShlAssign<u32> for usizex8","synthetic":false,"types":["packed_simd::vSize::usizex8"]}]; +if (window.register_implementors) {window.register_implementors(implementors);} else {window.pending_implementors = implementors;}})() \ No newline at end of file diff --git a/implementors/core/ops/bit/trait.Shr.js b/implementors/core/ops/bit/trait.Shr.js new file mode 100644 index 000000000..b51faf2fb --- /dev/null +++ b/implementors/core/ops/bit/trait.Shr.js @@ -0,0 +1,3 @@ +(function() {var implementors = {}; +implementors["packed_simd"] = [{"text":"impl Shr<Simd<[i8; 2]>> for i8x2","synthetic":false,"types":["packed_simd::v16::i8x2"]},{"text":"impl Shr<u32> for i8x2","synthetic":false,"types":["packed_simd::v16::i8x2"]},{"text":"impl Shr<Simd<[u8; 2]>> for u8x2","synthetic":false,"types":["packed_simd::v16::u8x2"]},{"text":"impl Shr<u32> for u8x2","synthetic":false,"types":["packed_simd::v16::u8x2"]},{"text":"impl Shr<Simd<[i8; 4]>> for i8x4","synthetic":false,"types":["packed_simd::v32::i8x4"]},{"text":"impl Shr<u32> for i8x4","synthetic":false,"types":["packed_simd::v32::i8x4"]},{"text":"impl Shr<Simd<[u8; 4]>> for u8x4","synthetic":false,"types":["packed_simd::v32::u8x4"]},{"text":"impl Shr<u32> for u8x4","synthetic":false,"types":["packed_simd::v32::u8x4"]},{"text":"impl Shr<Simd<[i16; 2]>> for i16x2","synthetic":false,"types":["packed_simd::v32::i16x2"]},{"text":"impl Shr<u32> for i16x2","synthetic":false,"types":["packed_simd::v32::i16x2"]},{"text":"impl Shr<Simd<[u16; 2]>> for u16x2","synthetic":false,"types":["packed_simd::v32::u16x2"]},{"text":"impl Shr<u32> for u16x2","synthetic":false,"types":["packed_simd::v32::u16x2"]},{"text":"impl Shr<Simd<[i8; 8]>> for i8x8","synthetic":false,"types":["packed_simd::v64::i8x8"]},{"text":"impl Shr<u32> for i8x8","synthetic":false,"types":["packed_simd::v64::i8x8"]},{"text":"impl Shr<Simd<[u8; 8]>> for u8x8","synthetic":false,"types":["packed_simd::v64::u8x8"]},{"text":"impl Shr<u32> for u8x8","synthetic":false,"types":["packed_simd::v64::u8x8"]},{"text":"impl Shr<Simd<[i16; 4]>> for i16x4","synthetic":false,"types":["packed_simd::v64::i16x4"]},{"text":"impl Shr<u32> for i16x4","synthetic":false,"types":["packed_simd::v64::i16x4"]},{"text":"impl Shr<Simd<[u16; 4]>> for u16x4","synthetic":false,"types":["packed_simd::v64::u16x4"]},{"text":"impl Shr<u32> for u16x4","synthetic":false,"types":["packed_simd::v64::u16x4"]},{"text":"impl Shr<Simd<[i32; 2]>> for i32x2","synthetic":false,"types":["packed_simd::v64::i32x2"]},{"text":"impl Shr<u32> for i32x2","synthetic":false,"types":["packed_simd::v64::i32x2"]},{"text":"impl Shr<Simd<[u32; 2]>> for u32x2","synthetic":false,"types":["packed_simd::v64::u32x2"]},{"text":"impl Shr<u32> for u32x2","synthetic":false,"types":["packed_simd::v64::u32x2"]},{"text":"impl Shr<Simd<[i8; 16]>> for i8x16","synthetic":false,"types":["packed_simd::v128::i8x16"]},{"text":"impl Shr<u32> for i8x16","synthetic":false,"types":["packed_simd::v128::i8x16"]},{"text":"impl Shr<Simd<[u8; 16]>> for u8x16","synthetic":false,"types":["packed_simd::v128::u8x16"]},{"text":"impl Shr<u32> for u8x16","synthetic":false,"types":["packed_simd::v128::u8x16"]},{"text":"impl Shr<Simd<[i16; 8]>> for i16x8","synthetic":false,"types":["packed_simd::v128::i16x8"]},{"text":"impl Shr<u32> for i16x8","synthetic":false,"types":["packed_simd::v128::i16x8"]},{"text":"impl Shr<Simd<[u16; 8]>> for u16x8","synthetic":false,"types":["packed_simd::v128::u16x8"]},{"text":"impl Shr<u32> for u16x8","synthetic":false,"types":["packed_simd::v128::u16x8"]},{"text":"impl Shr<Simd<[i32; 4]>> for i32x4","synthetic":false,"types":["packed_simd::v128::i32x4"]},{"text":"impl Shr<u32> for i32x4","synthetic":false,"types":["packed_simd::v128::i32x4"]},{"text":"impl Shr<Simd<[u32; 4]>> for u32x4","synthetic":false,"types":["packed_simd::v128::u32x4"]},{"text":"impl Shr<u32> for u32x4","synthetic":false,"types":["packed_simd::v128::u32x4"]},{"text":"impl Shr<Simd<[i64; 2]>> for i64x2","synthetic":false,"types":["packed_simd::v128::i64x2"]},{"text":"impl Shr<u32> for i64x2","synthetic":false,"types":["packed_simd::v128::i64x2"]},{"text":"impl Shr<Simd<[u64; 2]>> for u64x2","synthetic":false,"types":["packed_simd::v128::u64x2"]},{"text":"impl Shr<u32> for u64x2","synthetic":false,"types":["packed_simd::v128::u64x2"]},{"text":"impl Shr<Simd<[i128; 1]>> for i128x1","synthetic":false,"types":["packed_simd::v128::i128x1"]},{"text":"impl Shr<u32> for i128x1","synthetic":false,"types":["packed_simd::v128::i128x1"]},{"text":"impl Shr<Simd<[u128; 1]>> for u128x1","synthetic":false,"types":["packed_simd::v128::u128x1"]},{"text":"impl Shr<u32> for u128x1","synthetic":false,"types":["packed_simd::v128::u128x1"]},{"text":"impl Shr<Simd<[i8; 32]>> for i8x32","synthetic":false,"types":["packed_simd::v256::i8x32"]},{"text":"impl Shr<u32> for i8x32","synthetic":false,"types":["packed_simd::v256::i8x32"]},{"text":"impl Shr<Simd<[u8; 32]>> for u8x32","synthetic":false,"types":["packed_simd::v256::u8x32"]},{"text":"impl Shr<u32> for u8x32","synthetic":false,"types":["packed_simd::v256::u8x32"]},{"text":"impl Shr<Simd<[i16; 16]>> for i16x16","synthetic":false,"types":["packed_simd::v256::i16x16"]},{"text":"impl Shr<u32> for i16x16","synthetic":false,"types":["packed_simd::v256::i16x16"]},{"text":"impl Shr<Simd<[u16; 16]>> for u16x16","synthetic":false,"types":["packed_simd::v256::u16x16"]},{"text":"impl Shr<u32> for u16x16","synthetic":false,"types":["packed_simd::v256::u16x16"]},{"text":"impl Shr<Simd<[i32; 8]>> for i32x8","synthetic":false,"types":["packed_simd::v256::i32x8"]},{"text":"impl Shr<u32> for i32x8","synthetic":false,"types":["packed_simd::v256::i32x8"]},{"text":"impl Shr<Simd<[u32; 8]>> for u32x8","synthetic":false,"types":["packed_simd::v256::u32x8"]},{"text":"impl Shr<u32> for u32x8","synthetic":false,"types":["packed_simd::v256::u32x8"]},{"text":"impl Shr<Simd<[i64; 4]>> for i64x4","synthetic":false,"types":["packed_simd::v256::i64x4"]},{"text":"impl Shr<u32> for i64x4","synthetic":false,"types":["packed_simd::v256::i64x4"]},{"text":"impl Shr<Simd<[u64; 4]>> for u64x4","synthetic":false,"types":["packed_simd::v256::u64x4"]},{"text":"impl Shr<u32> for u64x4","synthetic":false,"types":["packed_simd::v256::u64x4"]},{"text":"impl Shr<Simd<[i128; 2]>> for i128x2","synthetic":false,"types":["packed_simd::v256::i128x2"]},{"text":"impl Shr<u32> for i128x2","synthetic":false,"types":["packed_simd::v256::i128x2"]},{"text":"impl Shr<Simd<[u128; 2]>> for u128x2","synthetic":false,"types":["packed_simd::v256::u128x2"]},{"text":"impl Shr<u32> for u128x2","synthetic":false,"types":["packed_simd::v256::u128x2"]},{"text":"impl Shr<Simd<[i8; 64]>> for i8x64","synthetic":false,"types":["packed_simd::v512::i8x64"]},{"text":"impl Shr<u32> for i8x64","synthetic":false,"types":["packed_simd::v512::i8x64"]},{"text":"impl Shr<Simd<[u8; 64]>> for u8x64","synthetic":false,"types":["packed_simd::v512::u8x64"]},{"text":"impl Shr<u32> for u8x64","synthetic":false,"types":["packed_simd::v512::u8x64"]},{"text":"impl Shr<Simd<[i16; 32]>> for i16x32","synthetic":false,"types":["packed_simd::v512::i16x32"]},{"text":"impl Shr<u32> for i16x32","synthetic":false,"types":["packed_simd::v512::i16x32"]},{"text":"impl Shr<Simd<[u16; 32]>> for u16x32","synthetic":false,"types":["packed_simd::v512::u16x32"]},{"text":"impl Shr<u32> for u16x32","synthetic":false,"types":["packed_simd::v512::u16x32"]},{"text":"impl Shr<Simd<[i32; 16]>> for i32x16","synthetic":false,"types":["packed_simd::v512::i32x16"]},{"text":"impl Shr<u32> for i32x16","synthetic":false,"types":["packed_simd::v512::i32x16"]},{"text":"impl Shr<Simd<[u32; 16]>> for u32x16","synthetic":false,"types":["packed_simd::v512::u32x16"]},{"text":"impl Shr<u32> for u32x16","synthetic":false,"types":["packed_simd::v512::u32x16"]},{"text":"impl Shr<Simd<[i64; 8]>> for i64x8","synthetic":false,"types":["packed_simd::v512::i64x8"]},{"text":"impl Shr<u32> for i64x8","synthetic":false,"types":["packed_simd::v512::i64x8"]},{"text":"impl Shr<Simd<[u64; 8]>> for u64x8","synthetic":false,"types":["packed_simd::v512::u64x8"]},{"text":"impl Shr<u32> for u64x8","synthetic":false,"types":["packed_simd::v512::u64x8"]},{"text":"impl Shr<Simd<[i128; 4]>> for i128x4","synthetic":false,"types":["packed_simd::v512::i128x4"]},{"text":"impl Shr<u32> for i128x4","synthetic":false,"types":["packed_simd::v512::i128x4"]},{"text":"impl Shr<Simd<[u128; 4]>> for u128x4","synthetic":false,"types":["packed_simd::v512::u128x4"]},{"text":"impl Shr<u32> for u128x4","synthetic":false,"types":["packed_simd::v512::u128x4"]},{"text":"impl Shr<Simd<[isize; 2]>> for isizex2","synthetic":false,"types":["packed_simd::vSize::isizex2"]},{"text":"impl Shr<u32> for isizex2","synthetic":false,"types":["packed_simd::vSize::isizex2"]},{"text":"impl Shr<Simd<[usize; 2]>> for usizex2","synthetic":false,"types":["packed_simd::vSize::usizex2"]},{"text":"impl Shr<u32> for usizex2","synthetic":false,"types":["packed_simd::vSize::usizex2"]},{"text":"impl Shr<Simd<[isize; 4]>> for isizex4","synthetic":false,"types":["packed_simd::vSize::isizex4"]},{"text":"impl Shr<u32> for isizex4","synthetic":false,"types":["packed_simd::vSize::isizex4"]},{"text":"impl Shr<Simd<[usize; 4]>> for usizex4","synthetic":false,"types":["packed_simd::vSize::usizex4"]},{"text":"impl Shr<u32> for usizex4","synthetic":false,"types":["packed_simd::vSize::usizex4"]},{"text":"impl Shr<Simd<[isize; 8]>> for isizex8","synthetic":false,"types":["packed_simd::vSize::isizex8"]},{"text":"impl Shr<u32> for isizex8","synthetic":false,"types":["packed_simd::vSize::isizex8"]},{"text":"impl Shr<Simd<[usize; 8]>> for usizex8","synthetic":false,"types":["packed_simd::vSize::usizex8"]},{"text":"impl Shr<u32> for usizex8","synthetic":false,"types":["packed_simd::vSize::usizex8"]}]; +if (window.register_implementors) {window.register_implementors(implementors);} else {window.pending_implementors = implementors;}})() \ No newline at end of file diff --git a/implementors/core/ops/bit/trait.ShrAssign.js b/implementors/core/ops/bit/trait.ShrAssign.js new file mode 100644 index 000000000..acc6d5d58 --- /dev/null +++ b/implementors/core/ops/bit/trait.ShrAssign.js @@ -0,0 +1,3 @@ +(function() {var implementors = {}; +implementors["packed_simd"] = [{"text":"impl ShrAssign<Simd<[i8; 2]>> for i8x2","synthetic":false,"types":["packed_simd::v16::i8x2"]},{"text":"impl ShrAssign<u32> for i8x2","synthetic":false,"types":["packed_simd::v16::i8x2"]},{"text":"impl ShrAssign<Simd<[u8; 2]>> for u8x2","synthetic":false,"types":["packed_simd::v16::u8x2"]},{"text":"impl ShrAssign<u32> for u8x2","synthetic":false,"types":["packed_simd::v16::u8x2"]},{"text":"impl ShrAssign<Simd<[i8; 4]>> for i8x4","synthetic":false,"types":["packed_simd::v32::i8x4"]},{"text":"impl ShrAssign<u32> for i8x4","synthetic":false,"types":["packed_simd::v32::i8x4"]},{"text":"impl ShrAssign<Simd<[u8; 4]>> for u8x4","synthetic":false,"types":["packed_simd::v32::u8x4"]},{"text":"impl ShrAssign<u32> for u8x4","synthetic":false,"types":["packed_simd::v32::u8x4"]},{"text":"impl ShrAssign<Simd<[i16; 2]>> for i16x2","synthetic":false,"types":["packed_simd::v32::i16x2"]},{"text":"impl ShrAssign<u32> for i16x2","synthetic":false,"types":["packed_simd::v32::i16x2"]},{"text":"impl ShrAssign<Simd<[u16; 2]>> for u16x2","synthetic":false,"types":["packed_simd::v32::u16x2"]},{"text":"impl ShrAssign<u32> for u16x2","synthetic":false,"types":["packed_simd::v32::u16x2"]},{"text":"impl ShrAssign<Simd<[i8; 8]>> for i8x8","synthetic":false,"types":["packed_simd::v64::i8x8"]},{"text":"impl ShrAssign<u32> for i8x8","synthetic":false,"types":["packed_simd::v64::i8x8"]},{"text":"impl ShrAssign<Simd<[u8; 8]>> for u8x8","synthetic":false,"types":["packed_simd::v64::u8x8"]},{"text":"impl ShrAssign<u32> for u8x8","synthetic":false,"types":["packed_simd::v64::u8x8"]},{"text":"impl ShrAssign<Simd<[i16; 4]>> for i16x4","synthetic":false,"types":["packed_simd::v64::i16x4"]},{"text":"impl ShrAssign<u32> for i16x4","synthetic":false,"types":["packed_simd::v64::i16x4"]},{"text":"impl ShrAssign<Simd<[u16; 4]>> for u16x4","synthetic":false,"types":["packed_simd::v64::u16x4"]},{"text":"impl ShrAssign<u32> for u16x4","synthetic":false,"types":["packed_simd::v64::u16x4"]},{"text":"impl ShrAssign<Simd<[i32; 2]>> for i32x2","synthetic":false,"types":["packed_simd::v64::i32x2"]},{"text":"impl ShrAssign<u32> for i32x2","synthetic":false,"types":["packed_simd::v64::i32x2"]},{"text":"impl ShrAssign<Simd<[u32; 2]>> for u32x2","synthetic":false,"types":["packed_simd::v64::u32x2"]},{"text":"impl ShrAssign<u32> for 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ShrAssign<u32> for i32x4","synthetic":false,"types":["packed_simd::v128::i32x4"]},{"text":"impl ShrAssign<Simd<[u32; 4]>> for u32x4","synthetic":false,"types":["packed_simd::v128::u32x4"]},{"text":"impl ShrAssign<u32> for u32x4","synthetic":false,"types":["packed_simd::v128::u32x4"]},{"text":"impl ShrAssign<Simd<[i64; 2]>> for i64x2","synthetic":false,"types":["packed_simd::v128::i64x2"]},{"text":"impl ShrAssign<u32> for i64x2","synthetic":false,"types":["packed_simd::v128::i64x2"]},{"text":"impl ShrAssign<Simd<[u64; 2]>> for u64x2","synthetic":false,"types":["packed_simd::v128::u64x2"]},{"text":"impl ShrAssign<u32> for u64x2","synthetic":false,"types":["packed_simd::v128::u64x2"]},{"text":"impl ShrAssign<Simd<[i128; 1]>> for i128x1","synthetic":false,"types":["packed_simd::v128::i128x1"]},{"text":"impl ShrAssign<u32> for i128x1","synthetic":false,"types":["packed_simd::v128::i128x1"]},{"text":"impl ShrAssign<Simd<[u128; 1]>> for u128x1","synthetic":false,"types":["packed_simd::v128::u128x1"]},{"text":"impl ShrAssign<u32> for u128x1","synthetic":false,"types":["packed_simd::v128::u128x1"]},{"text":"impl ShrAssign<Simd<[i8; 32]>> for i8x32","synthetic":false,"types":["packed_simd::v256::i8x32"]},{"text":"impl ShrAssign<u32> for i8x32","synthetic":false,"types":["packed_simd::v256::i8x32"]},{"text":"impl ShrAssign<Simd<[u8; 32]>> for u8x32","synthetic":false,"types":["packed_simd::v256::u8x32"]},{"text":"impl ShrAssign<u32> for u8x32","synthetic":false,"types":["packed_simd::v256::u8x32"]},{"text":"impl ShrAssign<Simd<[i16; 16]>> for i16x16","synthetic":false,"types":["packed_simd::v256::i16x16"]},{"text":"impl ShrAssign<u32> for i16x16","synthetic":false,"types":["packed_simd::v256::i16x16"]},{"text":"impl ShrAssign<Simd<[u16; 16]>> for u16x16","synthetic":false,"types":["packed_simd::v256::u16x16"]},{"text":"impl ShrAssign<u32> for u16x16","synthetic":false,"types":["packed_simd::v256::u16x16"]},{"text":"impl ShrAssign<Simd<[i32; 8]>> for i32x8","synthetic":false,"types":["packed_simd::v256::i32x8"]},{"text":"impl ShrAssign<u32> for i32x8","synthetic":false,"types":["packed_simd::v256::i32x8"]},{"text":"impl ShrAssign<Simd<[u32; 8]>> for u32x8","synthetic":false,"types":["packed_simd::v256::u32x8"]},{"text":"impl ShrAssign<u32> for u32x8","synthetic":false,"types":["packed_simd::v256::u32x8"]},{"text":"impl ShrAssign<Simd<[i64; 4]>> for i64x4","synthetic":false,"types":["packed_simd::v256::i64x4"]},{"text":"impl ShrAssign<u32> for i64x4","synthetic":false,"types":["packed_simd::v256::i64x4"]},{"text":"impl ShrAssign<Simd<[u64; 4]>> for u64x4","synthetic":false,"types":["packed_simd::v256::u64x4"]},{"text":"impl ShrAssign<u32> for u64x4","synthetic":false,"types":["packed_simd::v256::u64x4"]},{"text":"impl ShrAssign<Simd<[i128; 2]>> for i128x2","synthetic":false,"types":["packed_simd::v256::i128x2"]},{"text":"impl ShrAssign<u32> for i128x2","synthetic":false,"types":["packed_simd::v256::i128x2"]},{"text":"impl ShrAssign<Simd<[u128; 2]>> for u128x2","synthetic":false,"types":["packed_simd::v256::u128x2"]},{"text":"impl ShrAssign<u32> for u128x2","synthetic":false,"types":["packed_simd::v256::u128x2"]},{"text":"impl ShrAssign<Simd<[i8; 64]>> for i8x64","synthetic":false,"types":["packed_simd::v512::i8x64"]},{"text":"impl ShrAssign<u32> for i8x64","synthetic":false,"types":["packed_simd::v512::i8x64"]},{"text":"impl ShrAssign<Simd<[u8; 64]>> for u8x64","synthetic":false,"types":["packed_simd::v512::u8x64"]},{"text":"impl ShrAssign<u32> for u8x64","synthetic":false,"types":["packed_simd::v512::u8x64"]},{"text":"impl ShrAssign<Simd<[i16; 32]>> for i16x32","synthetic":false,"types":["packed_simd::v512::i16x32"]},{"text":"impl ShrAssign<u32> for i16x32","synthetic":false,"types":["packed_simd::v512::i16x32"]},{"text":"impl ShrAssign<Simd<[u16; 32]>> for u16x32","synthetic":false,"types":["packed_simd::v512::u16x32"]},{"text":"impl ShrAssign<u32> for u16x32","synthetic":false,"types":["packed_simd::v512::u16x32"]},{"text":"impl ShrAssign<Simd<[i32; 16]>> for i32x16","synthetic":false,"types":["packed_simd::v512::i32x16"]},{"text":"impl ShrAssign<u32> for i32x16","synthetic":false,"types":["packed_simd::v512::i32x16"]},{"text":"impl ShrAssign<Simd<[u32; 16]>> for u32x16","synthetic":false,"types":["packed_simd::v512::u32x16"]},{"text":"impl ShrAssign<u32> for u32x16","synthetic":false,"types":["packed_simd::v512::u32x16"]},{"text":"impl ShrAssign<Simd<[i64; 8]>> for i64x8","synthetic":false,"types":["packed_simd::v512::i64x8"]},{"text":"impl ShrAssign<u32> for i64x8","synthetic":false,"types":["packed_simd::v512::i64x8"]},{"text":"impl ShrAssign<Simd<[u64; 8]>> for u64x8","synthetic":false,"types":["packed_simd::v512::u64x8"]},{"text":"impl ShrAssign<u32> for u64x8","synthetic":false,"types":["packed_simd::v512::u64x8"]},{"text":"impl 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isizex4","synthetic":false,"types":["packed_simd::vSize::isizex4"]},{"text":"impl ShrAssign<Simd<[usize; 4]>> for usizex4","synthetic":false,"types":["packed_simd::vSize::usizex4"]},{"text":"impl ShrAssign<u32> for usizex4","synthetic":false,"types":["packed_simd::vSize::usizex4"]},{"text":"impl ShrAssign<Simd<[isize; 8]>> for isizex8","synthetic":false,"types":["packed_simd::vSize::isizex8"]},{"text":"impl ShrAssign<u32> for isizex8","synthetic":false,"types":["packed_simd::vSize::isizex8"]},{"text":"impl ShrAssign<Simd<[usize; 8]>> for usizex8","synthetic":false,"types":["packed_simd::vSize::usizex8"]},{"text":"impl ShrAssign<u32> for usizex8","synthetic":false,"types":["packed_simd::vSize::usizex8"]}]; +if (window.register_implementors) {window.register_implementors(implementors);} else {window.pending_implementors = implementors;}})() \ No newline at end of file diff --git a/implementors/libm/trait.F32Ext.js b/implementors/libm/trait.F32Ext.js new file mode 100644 index 000000000..849ca5a74 --- /dev/null +++ b/implementors/libm/trait.F32Ext.js @@ -0,0 +1,3 @@ +(function() {var implementors = {}; +implementors["libm"] = []; +if (window.register_implementors) {window.register_implementors(implementors);} else {window.pending_implementors = implementors;}})() \ No newline at end of file diff --git a/implementors/libm/trait.F64Ext.js b/implementors/libm/trait.F64Ext.js new file mode 100644 index 000000000..849ca5a74 --- /dev/null +++ b/implementors/libm/trait.F64Ext.js @@ -0,0 +1,3 @@ +(function() {var implementors = {}; +implementors["libm"] = []; +if (window.register_implementors) {window.register_implementors(implementors);} else {window.pending_implementors = implementors;}})() \ No newline at end of file diff --git a/implementors/packed_simd/trait.Cast.js b/implementors/packed_simd/trait.Cast.js new file mode 100644 index 000000000..668d57c9a --- /dev/null +++ b/implementors/packed_simd/trait.Cast.js @@ -0,0 +1,3 @@ +(function() {var implementors = {}; +implementors["packed_simd"] = []; +if (window.register_implementors) {window.register_implementors(implementors);} else {window.pending_implementors = implementors;}})() \ No newline at end of file diff --git a/implementors/packed_simd/trait.FromBits.js b/implementors/packed_simd/trait.FromBits.js new file mode 100644 index 000000000..668d57c9a --- /dev/null +++ b/implementors/packed_simd/trait.FromBits.js @@ -0,0 +1,3 @@ +(function() {var implementors = {}; +implementors["packed_simd"] = []; +if (window.register_implementors) {window.register_implementors(implementors);} else {window.pending_implementors = implementors;}})() \ No newline at end of file diff --git a/implementors/packed_simd/trait.FromCast.js b/implementors/packed_simd/trait.FromCast.js new file mode 100644 index 000000000..668d57c9a --- /dev/null +++ b/implementors/packed_simd/trait.FromCast.js @@ -0,0 +1,3 @@ +(function() {var implementors = {}; +implementors["packed_simd"] = []; +if (window.register_implementors) {window.register_implementors(implementors);} else {window.pending_implementors = implementors;}})() \ No newline at end of file diff --git a/implementors/packed_simd/trait.IntoBits.js b/implementors/packed_simd/trait.IntoBits.js new file mode 100644 index 000000000..668d57c9a --- /dev/null +++ b/implementors/packed_simd/trait.IntoBits.js @@ -0,0 +1,3 @@ +(function() {var implementors = {}; +implementors["packed_simd"] = []; +if (window.register_implementors) {window.register_implementors(implementors);} else {window.pending_implementors = implementors;}})() \ No newline at end of file diff --git a/implementors/packed_simd/trait.Mask.js b/implementors/packed_simd/trait.Mask.js new file mode 100644 index 000000000..668d57c9a --- /dev/null +++ b/implementors/packed_simd/trait.Mask.js @@ -0,0 +1,3 @@ +(function() {var implementors = {}; +implementors["packed_simd"] = []; +if (window.register_implementors) {window.register_implementors(implementors);} else {window.pending_implementors = implementors;}})() \ No newline at end of file diff --git a/implementors/packed_simd/trait.SimdArray.js b/implementors/packed_simd/trait.SimdArray.js new file mode 100644 index 000000000..668d57c9a --- /dev/null +++ b/implementors/packed_simd/trait.SimdArray.js @@ -0,0 +1,3 @@ +(function() {var implementors = {}; +implementors["packed_simd"] = []; +if (window.register_implementors) {window.register_implementors(implementors);} else {window.pending_implementors = implementors;}})() \ No newline at end of file diff --git a/implementors/packed_simd/trait.SimdVector.js b/implementors/packed_simd/trait.SimdVector.js new file mode 100644 index 000000000..668d57c9a --- /dev/null +++ b/implementors/packed_simd/trait.SimdVector.js @@ -0,0 +1,3 @@ +(function() {var implementors = {}; +implementors["packed_simd"] = []; +if (window.register_implementors) {window.register_implementors(implementors);} else {window.pending_implementors = implementors;}})() \ No newline at end of file diff --git a/libm/all.html b/libm/all.html new file mode 100644 index 000000000..dbf2c70d3 --- /dev/null +++ b/libm/all.html @@ -0,0 +1,3 @@ +List of all items in this crate

[−] + + List of all items

Traits

Functions

\ No newline at end of file diff --git a/libm/fn.acos.html b/libm/fn.acos.html new file mode 100644 index 000000000..65ae631d4 --- /dev/null +++ b/libm/fn.acos.html @@ -0,0 +1,5 @@ +libm::acos - Rust

[−][src]Function libm::acos

pub fn acos(x: f64) -> f64

Arccosine (f64)

+

Computes the inverse cosine (arc cosine) of the input value. +Arguments must be in the range -1 to 1. +Returns values in radians, in the range of 0 to pi.

+
\ No newline at end of file diff --git a/libm/fn.acosf.html b/libm/fn.acosf.html new file mode 100644 index 000000000..1ff609c15 --- /dev/null +++ b/libm/fn.acosf.html @@ -0,0 +1,5 @@ +libm::acosf - Rust

[−][src]Function libm::acosf

pub fn acosf(x: f32) -> f32

Arccosine (f32)

+

Computes the inverse cosine (arc cosine) of the input value. +Arguments must be in the range -1 to 1. +Returns values in radians, in the range of 0 to pi.

+
\ No newline at end of file diff --git a/libm/fn.acosh.html b/libm/fn.acosh.html new file mode 100644 index 000000000..d6e47fa9e --- /dev/null +++ b/libm/fn.acosh.html @@ -0,0 +1,5 @@ +libm::acosh - Rust

[−][src]Function libm::acosh

pub fn acosh(x: f64) -> f64

Inverse hyperbolic cosine (f64)

+

Calculates the inverse hyperbolic cosine of x. +Is defined as log(x + sqrt(x*x-1)). +x must be a number greater than or equal to 1.

+
\ No newline at end of file diff --git a/libm/fn.acoshf.html b/libm/fn.acoshf.html new file mode 100644 index 000000000..e02c197b1 --- /dev/null +++ b/libm/fn.acoshf.html @@ -0,0 +1,5 @@ +libm::acoshf - Rust

[−][src]Function libm::acoshf

pub fn acoshf(x: f32) -> f32

Inverse hyperbolic cosine (f32)

+

Calculates the inverse hyperbolic cosine of x. +Is defined as log(x + sqrt(x*x-1)). +x must be a number greater than or equal to 1.

+
\ No newline at end of file diff --git a/libm/fn.asin.html b/libm/fn.asin.html new file mode 100644 index 000000000..614b4137f --- /dev/null +++ b/libm/fn.asin.html @@ -0,0 +1,5 @@ +libm::asin - Rust

[−][src]Function libm::asin

pub fn asin(x: f64) -> f64

Arcsine (f64)

+

Computes the inverse sine (arc sine) of the argument x. +Arguments to asin must be in the range -1 to 1. +Returns values in radians, in the range of -pi/2 to pi/2.

+
\ No newline at end of file diff --git a/libm/fn.asinf.html b/libm/fn.asinf.html new file mode 100644 index 000000000..355d680c6 --- /dev/null +++ b/libm/fn.asinf.html @@ -0,0 +1,5 @@ +libm::asinf - Rust

[−][src]Function libm::asinf

pub fn asinf(x: f32) -> f32

Arcsine (f32)

+

Computes the inverse sine (arc sine) of the argument x. +Arguments to asin must be in the range -1 to 1. +Returns values in radians, in the range of -pi/2 to pi/2.

+
\ No newline at end of file diff --git a/libm/fn.asinh.html b/libm/fn.asinh.html new file mode 100644 index 000000000..7eca6ed7b --- /dev/null +++ b/libm/fn.asinh.html @@ -0,0 +1,4 @@ +libm::asinh - Rust

[−][src]Function libm::asinh

pub fn asinh(x: f64) -> f64

Inverse hyperbolic sine (f64)

+

Calculates the inverse hyperbolic sine of x. +Is defined as sgn(x)*log(|x|+sqrt(x*x+1)).

+
\ No newline at end of file diff --git a/libm/fn.asinhf.html b/libm/fn.asinhf.html new file mode 100644 index 000000000..d42dcfd15 --- /dev/null +++ b/libm/fn.asinhf.html @@ -0,0 +1,4 @@ +libm::asinhf - Rust

[−][src]Function libm::asinhf

pub fn asinhf(x: f32) -> f32

Inverse hyperbolic sine (f32)

+

Calculates the inverse hyperbolic sine of x. +Is defined as sgn(x)*log(|x|+sqrt(x*x+1)).

+
\ No newline at end of file diff --git a/libm/fn.atan.html b/libm/fn.atan.html new file mode 100644 index 000000000..4f702c26c --- /dev/null +++ b/libm/fn.atan.html @@ -0,0 +1,4 @@ +libm::atan - Rust

[−][src]Function libm::atan

pub fn atan(x: f64) -> f64

Arctangent (f64)

+

Computes the inverse tangent (arc tangent) of the input value. +Returns a value in radians, in the range of -pi/2 to pi/2.

+
\ No newline at end of file diff --git a/libm/fn.atan2.html b/libm/fn.atan2.html new file mode 100644 index 000000000..b4d745994 --- /dev/null +++ b/libm/fn.atan2.html @@ -0,0 +1,5 @@ +libm::atan2 - Rust

[−][src]Function libm::atan2

pub fn atan2(y: f64, x: f64) -> f64

Arctangent of y/x (f64)

+

Computes the inverse tangent (arc tangent) of y/x. +Produces the correct result even for angles near pi/2 or -pi/2 (that is, when x is near 0). +Returns a value in radians, in the range of -pi to pi.

+
\ No newline at end of file diff --git a/libm/fn.atan2f.html b/libm/fn.atan2f.html new file mode 100644 index 000000000..84455f335 --- /dev/null +++ b/libm/fn.atan2f.html @@ -0,0 +1,5 @@ +libm::atan2f - Rust

[−][src]Function libm::atan2f

pub fn atan2f(y: f32, x: f32) -> f32

Arctangent of y/x (f32)

+

Computes the inverse tangent (arc tangent) of y/x. +Produces the correct result even for angles near pi/2 or -pi/2 (that is, when x is near 0). +Returns a value in radians, in the range of -pi to pi.

+
\ No newline at end of file diff --git a/libm/fn.atanf.html b/libm/fn.atanf.html new file mode 100644 index 000000000..698713918 --- /dev/null +++ b/libm/fn.atanf.html @@ -0,0 +1,4 @@ +libm::atanf - Rust

[−][src]Function libm::atanf

pub fn atanf(x: f32) -> f32

Arctangent (f32)

+

Computes the inverse tangent (arc tangent) of the input value. +Returns a value in radians, in the range of -pi/2 to pi/2.

+
\ No newline at end of file diff --git a/libm/fn.atanh.html b/libm/fn.atanh.html new file mode 100644 index 000000000..fe061b570 --- /dev/null +++ b/libm/fn.atanh.html @@ -0,0 +1,4 @@ +libm::atanh - Rust

[−][src]Function libm::atanh

pub fn atanh(x: f64) -> f64

Inverse hyperbolic tangent (f64)

+

Calculates the inverse hyperbolic tangent of x. +Is defined as log((1+x)/(1-x))/2 = log1p(2x/(1-x))/2.

+
\ No newline at end of file diff --git a/libm/fn.atanhf.html b/libm/fn.atanhf.html new file mode 100644 index 000000000..c9008fc03 --- /dev/null +++ b/libm/fn.atanhf.html @@ -0,0 +1,4 @@ +libm::atanhf - Rust

[−][src]Function libm::atanhf

pub fn atanhf(x: f32) -> f32

Inverse hyperbolic tangent (f32)

+

Calculates the inverse hyperbolic tangent of x. +Is defined as log((1+x)/(1-x))/2 = log1p(2x/(1-x))/2.

+
\ No newline at end of file diff --git a/libm/fn.cbrt.html b/libm/fn.cbrt.html new file mode 100644 index 000000000..d60f6cc02 --- /dev/null +++ b/libm/fn.cbrt.html @@ -0,0 +1,2 @@ +libm::cbrt - Rust

[−][src]Function libm::cbrt

pub fn cbrt(x: f64) -> f64

Computes the cube root of the argument.

+
\ No newline at end of file diff --git a/libm/fn.cbrtf.html b/libm/fn.cbrtf.html new file mode 100644 index 000000000..d5a6f7c8a --- /dev/null +++ b/libm/fn.cbrtf.html @@ -0,0 +1,3 @@ +libm::cbrtf - Rust

[−][src]Function libm::cbrtf

pub fn cbrtf(x: f32) -> f32

Cube root (f32)

+

Computes the cube root of the argument.

+
\ No newline at end of file diff --git a/libm/fn.ceil.html b/libm/fn.ceil.html new file mode 100644 index 000000000..ff1cba5c1 --- /dev/null +++ b/libm/fn.ceil.html @@ -0,0 +1,3 @@ +libm::ceil - Rust

[−][src]Function libm::ceil

pub fn ceil(x: f64) -> f64

Ceil (f64)

+

Finds the nearest integer greater than or equal to x.

+
\ No newline at end of file diff --git a/libm/fn.ceilf.html b/libm/fn.ceilf.html new file mode 100644 index 000000000..d2d5d023c --- /dev/null +++ b/libm/fn.ceilf.html @@ -0,0 +1,3 @@ +libm::ceilf - Rust

[−][src]Function libm::ceilf

pub fn ceilf(x: f32) -> f32

Ceil (f32)

+

Finds the nearest integer greater than or equal to x.

+
\ No newline at end of file diff --git a/libm/fn.copysign.html b/libm/fn.copysign.html new file mode 100644 index 000000000..88c05dc5c --- /dev/null +++ b/libm/fn.copysign.html @@ -0,0 +1,4 @@ +libm::copysign - Rust

[−][src]Function libm::copysign

pub fn copysign(x: f64, y: f64) -> f64

Sign of Y, magnitude of X (f64)

+

Constructs a number with the magnitude (absolute value) of its +first argument, x, and the sign of its second argument, y.

+
\ No newline at end of file diff --git a/libm/fn.copysignf.html b/libm/fn.copysignf.html new file mode 100644 index 000000000..398c3b0ef --- /dev/null +++ b/libm/fn.copysignf.html @@ -0,0 +1,4 @@ +libm::copysignf - Rust

[−][src]Function libm::copysignf

pub fn copysignf(x: f32, y: f32) -> f32

Sign of Y, magnitude of X (f32)

+

Constructs a number with the magnitude (absolute value) of its +first argument, x, and the sign of its second argument, y.

+
\ No newline at end of file diff --git a/libm/fn.cos.html b/libm/fn.cos.html new file mode 100644 index 000000000..64524c592 --- /dev/null +++ b/libm/fn.cos.html @@ -0,0 +1 @@ +libm::cos - Rust

[−][src]Function libm::cos

pub fn cos(x: f64) -> f64
\ No newline at end of file diff --git a/libm/fn.cosf.html b/libm/fn.cosf.html new file mode 100644 index 000000000..21344d468 --- /dev/null +++ b/libm/fn.cosf.html @@ -0,0 +1 @@ +libm::cosf - Rust

[−][src]Function libm::cosf

pub fn cosf(x: f32) -> f32
\ No newline at end of file diff --git a/libm/fn.cosh.html b/libm/fn.cosh.html new file mode 100644 index 000000000..e74c673a7 --- /dev/null +++ b/libm/fn.cosh.html @@ -0,0 +1,5 @@ +libm::cosh - Rust

[−][src]Function libm::cosh

pub fn cosh(x: f64) -> f64

Hyperbolic cosine (f64)

+

Computes the hyperbolic cosine of the argument x. +Is defined as (exp(x) + exp(-x))/2 +Angles are specified in radians.

+
\ No newline at end of file diff --git a/libm/fn.coshf.html b/libm/fn.coshf.html new file mode 100644 index 000000000..3ce06b7e4 --- /dev/null +++ b/libm/fn.coshf.html @@ -0,0 +1,5 @@ +libm::coshf - Rust

[−][src]Function libm::coshf

pub fn coshf(x: f32) -> f32

Hyperbolic cosine (f64)

+

Computes the hyperbolic cosine of the argument x. +Is defined as (exp(x) + exp(-x))/2 +Angles are specified in radians.

+
\ No newline at end of file diff --git a/libm/fn.erf.html b/libm/fn.erf.html new file mode 100644 index 000000000..5dab19582 --- /dev/null +++ b/libm/fn.erf.html @@ -0,0 +1,5 @@ +libm::erf - Rust

[−][src]Function libm::erf

pub fn erf(x: f64) -> f64

Error function (f64)

+

Calculates an approximation to the “error function”, which estimates +the probability that an observation will fall within x standard +deviations of the mean (assuming a normal distribution).

+
\ No newline at end of file diff --git a/libm/fn.erfc.html b/libm/fn.erfc.html new file mode 100644 index 000000000..6c29cdc6e --- /dev/null +++ b/libm/fn.erfc.html @@ -0,0 +1,6 @@ +libm::erfc - Rust

[−][src]Function libm::erfc

pub fn erfc(x: f64) -> f64

Error function (f64)

+

Calculates the complementary probability. +Is 1 - erf(x). Is computed directly, so that you can use it to avoid +the loss of precision that would result from subtracting +large probabilities (on large x) from 1.

+
\ No newline at end of file diff --git a/libm/fn.erfcf.html b/libm/fn.erfcf.html new file mode 100644 index 000000000..a8cb444c8 --- /dev/null +++ b/libm/fn.erfcf.html @@ -0,0 +1,6 @@ +libm::erfcf - Rust

[−][src]Function libm::erfcf

pub fn erfcf(x: f32) -> f32

Error function (f32)

+

Calculates the complementary probability. +Is 1 - erf(x). Is computed directly, so that you can use it to avoid +the loss of precision that would result from subtracting +large probabilities (on large x) from 1.

+
\ No newline at end of file diff --git a/libm/fn.erff.html b/libm/fn.erff.html new file mode 100644 index 000000000..7b1fb7a94 --- /dev/null +++ b/libm/fn.erff.html @@ -0,0 +1,5 @@ +libm::erff - Rust

[−][src]Function libm::erff

pub fn erff(x: f32) -> f32

Error function (f32)

+

Calculates an approximation to the “error function”, which estimates +the probability that an observation will fall within x standard +deviations of the mean (assuming a normal distribution).

+
\ No newline at end of file diff --git a/libm/fn.exp.html b/libm/fn.exp.html new file mode 100644 index 000000000..bf2200749 --- /dev/null +++ b/libm/fn.exp.html @@ -0,0 +1,4 @@ +libm::exp - Rust

[−][src]Function libm::exp

pub fn exp(x: f64) -> f64

Exponential, base e (f64)

+

Calculate the exponential of x, that is, e raised to the power x +(where e is the base of the natural system of logarithms, approximately 2.71828).

+
\ No newline at end of file diff --git a/libm/fn.exp10.html b/libm/fn.exp10.html new file mode 100644 index 000000000..6a6181ebd --- /dev/null +++ b/libm/fn.exp10.html @@ -0,0 +1 @@ +libm::exp10 - Rust

[−][src]Function libm::exp10

pub fn exp10(x: f64) -> f64
\ No newline at end of file diff --git a/libm/fn.exp10f.html b/libm/fn.exp10f.html new file mode 100644 index 000000000..daba3465e --- /dev/null +++ b/libm/fn.exp10f.html @@ -0,0 +1 @@ +libm::exp10f - Rust

[−][src]Function libm::exp10f

pub fn exp10f(x: f32) -> f32
\ No newline at end of file diff --git a/libm/fn.exp2.html b/libm/fn.exp2.html new file mode 100644 index 000000000..cb6f6dbb4 --- /dev/null +++ b/libm/fn.exp2.html @@ -0,0 +1,3 @@ +libm::exp2 - Rust

[−][src]Function libm::exp2

pub fn exp2(x: f64) -> f64

Exponential, base 2 (f64)

+

Calculate 2^x, that is, 2 raised to the power x.

+
\ No newline at end of file diff --git a/libm/fn.exp2f.html b/libm/fn.exp2f.html new file mode 100644 index 000000000..35c43ed0d --- /dev/null +++ b/libm/fn.exp2f.html @@ -0,0 +1,3 @@ +libm::exp2f - Rust

[−][src]Function libm::exp2f

pub fn exp2f(x: f32) -> f32

Exponential, base 2 (f32)

+

Calculate 2^x, that is, 2 raised to the power x.

+
\ No newline at end of file diff --git a/libm/fn.expf.html b/libm/fn.expf.html new file mode 100644 index 000000000..154079c80 --- /dev/null +++ b/libm/fn.expf.html @@ -0,0 +1,4 @@ +libm::expf - Rust

[−][src]Function libm::expf

pub fn expf(x: f32) -> f32

Exponential, base e (f32)

+

Calculate the exponential of x, that is, e raised to the power x +(where e is the base of the natural system of logarithms, approximately 2.71828).

+
\ No newline at end of file diff --git a/libm/fn.expm1.html b/libm/fn.expm1.html new file mode 100644 index 000000000..88720f798 --- /dev/null +++ b/libm/fn.expm1.html @@ -0,0 +1,7 @@ +libm::expm1 - Rust

[−][src]Function libm::expm1

pub fn expm1(x: f64) -> f64

Exponential, base e, of x-1 (f64)

+

Calculates the exponential of x and subtract 1, that is, e raised +to the power x minus 1 (where e is the base of the natural +system of logarithms, approximately 2.71828). +The result is accurate even for small values of x, +where using exp(x)-1 would lose many significant digits.

+
\ No newline at end of file diff --git a/libm/fn.expm1f.html b/libm/fn.expm1f.html new file mode 100644 index 000000000..15095b107 --- /dev/null +++ b/libm/fn.expm1f.html @@ -0,0 +1,7 @@ +libm::expm1f - Rust

[−][src]Function libm::expm1f

pub fn expm1f(x: f32) -> f32

Exponential, base e, of x-1 (f32)

+

Calculates the exponential of x and subtract 1, that is, e raised +to the power x minus 1 (where e is the base of the natural +system of logarithms, approximately 2.71828). +The result is accurate even for small values of x, +where using exp(x)-1 would lose many significant digits.

+
\ No newline at end of file diff --git a/libm/fn.fabs.html b/libm/fn.fabs.html new file mode 100644 index 000000000..27e3ae971 --- /dev/null +++ b/libm/fn.fabs.html @@ -0,0 +1,4 @@ +libm::fabs - Rust

[−][src]Function libm::fabs

pub fn fabs(x: f64) -> f64

Absolute value (magnitude) (f64) +Calculates the absolute value (magnitude) of the argument x, +by direct manipulation of the bit representation of x.

+
\ No newline at end of file diff --git a/libm/fn.fabsf.html b/libm/fn.fabsf.html new file mode 100644 index 000000000..bab1663e8 --- /dev/null +++ b/libm/fn.fabsf.html @@ -0,0 +1,4 @@ +libm::fabsf - Rust

[−][src]Function libm::fabsf

pub fn fabsf(x: f32) -> f32

Absolute value (magnitude) (f32) +Calculates the absolute value (magnitude) of the argument x, +by direct manipulation of the bit representation of x.

+
\ No newline at end of file diff --git a/libm/fn.fdim.html b/libm/fn.fdim.html new file mode 100644 index 000000000..48ad15fdc --- /dev/null +++ b/libm/fn.fdim.html @@ -0,0 +1,9 @@ +libm::fdim - Rust

[−][src]Function libm::fdim

pub fn fdim(x: f64, y: f64) -> f64

Positive difference (f64)

+

Determines the positive difference between arguments, returning:

+ +

A range error may occur.

+
\ No newline at end of file diff --git a/libm/fn.fdimf.html b/libm/fn.fdimf.html new file mode 100644 index 000000000..59ad90d33 --- /dev/null +++ b/libm/fn.fdimf.html @@ -0,0 +1,9 @@ +libm::fdimf - Rust

[−][src]Function libm::fdimf

pub fn fdimf(x: f32, y: f32) -> f32

Positive difference (f32)

+

Determines the positive difference between arguments, returning:

+ +

A range error may occur.

+
\ No newline at end of file diff --git a/libm/fn.floor.html b/libm/fn.floor.html new file mode 100644 index 000000000..2e3505d8e --- /dev/null +++ b/libm/fn.floor.html @@ -0,0 +1,3 @@ +libm::floor - Rust

[−][src]Function libm::floor

pub fn floor(x: f64) -> f64

Floor (f64)

+

Finds the nearest integer less than or equal to x.

+
\ No newline at end of file diff --git a/libm/fn.floorf.html b/libm/fn.floorf.html new file mode 100644 index 000000000..47c110afb --- /dev/null +++ b/libm/fn.floorf.html @@ -0,0 +1,3 @@ +libm::floorf - Rust

[−][src]Function libm::floorf

pub fn floorf(x: f32) -> f32

Floor (f64)

+

Finds the nearest integer less than or equal to x.

+
\ No newline at end of file diff --git a/libm/fn.fma.html b/libm/fn.fma.html new file mode 100644 index 000000000..5af9e368c --- /dev/null +++ b/libm/fn.fma.html @@ -0,0 +1,5 @@ +libm::fma - Rust

[−][src]Function libm::fma

pub fn fma(x: f64, y: f64, z: f64) -> f64

Floating multiply add (f64)

+

Computes (x*y)+z, rounded as one ternary operation: +Computes the value (as if) to infinite precision and rounds once to the result format, +according to the rounding mode characterized by the value of FLT_ROUNDS.

+
\ No newline at end of file diff --git a/libm/fn.fmaf.html b/libm/fn.fmaf.html new file mode 100644 index 000000000..57c4ce149 --- /dev/null +++ b/libm/fn.fmaf.html @@ -0,0 +1,5 @@ +libm::fmaf - Rust

[−][src]Function libm::fmaf

pub fn fmaf(x: f32, y: f32, z: f32) -> f32

Floating multiply add (f32)

+

Computes (x*y)+z, rounded as one ternary operation: +Computes the value (as if) to infinite precision and rounds once to the result format, +according to the rounding mode characterized by the value of FLT_ROUNDS.

+
\ No newline at end of file diff --git a/libm/fn.fmax.html b/libm/fn.fmax.html new file mode 100644 index 000000000..be7c2ce3c --- /dev/null +++ b/libm/fn.fmax.html @@ -0,0 +1 @@ +libm::fmax - Rust

[−][src]Function libm::fmax

pub fn fmax(x: f64, y: f64) -> f64
\ No newline at end of file diff --git a/libm/fn.fmaxf.html b/libm/fn.fmaxf.html new file mode 100644 index 000000000..3664f2cda --- /dev/null +++ b/libm/fn.fmaxf.html @@ -0,0 +1 @@ +libm::fmaxf - Rust

[−][src]Function libm::fmaxf

pub fn fmaxf(x: f32, y: f32) -> f32
\ No newline at end of file diff --git a/libm/fn.fmin.html b/libm/fn.fmin.html new file mode 100644 index 000000000..839e33446 --- /dev/null +++ b/libm/fn.fmin.html @@ -0,0 +1 @@ +libm::fmin - Rust

[−][src]Function libm::fmin

pub fn fmin(x: f64, y: f64) -> f64
\ No newline at end of file diff --git a/libm/fn.fminf.html b/libm/fn.fminf.html new file mode 100644 index 000000000..18272cc3f --- /dev/null +++ b/libm/fn.fminf.html @@ -0,0 +1 @@ +libm::fminf - Rust

[−][src]Function libm::fminf

pub fn fminf(x: f32, y: f32) -> f32
\ No newline at end of file diff --git a/libm/fn.fmod.html b/libm/fn.fmod.html new file mode 100644 index 000000000..c50850030 --- /dev/null +++ b/libm/fn.fmod.html @@ -0,0 +1 @@ +libm::fmod - Rust

[−][src]Function libm::fmod

pub fn fmod(x: f64, y: f64) -> f64
\ No newline at end of file diff --git a/libm/fn.fmodf.html b/libm/fn.fmodf.html new file mode 100644 index 000000000..a231826e5 --- /dev/null +++ b/libm/fn.fmodf.html @@ -0,0 +1 @@ +libm::fmodf - Rust

[−][src]Function libm::fmodf

pub fn fmodf(x: f32, y: f32) -> f32
\ No newline at end of file diff --git a/libm/fn.frexp.html b/libm/fn.frexp.html new file mode 100644 index 000000000..d04626c9f --- /dev/null +++ b/libm/fn.frexp.html @@ -0,0 +1 @@ +libm::frexp - Rust

[−][src]Function libm::frexp

pub fn frexp(x: f64) -> (f64, i32)
\ No newline at end of file diff --git a/libm/fn.frexpf.html b/libm/fn.frexpf.html new file mode 100644 index 000000000..bd8643c8f --- /dev/null +++ b/libm/fn.frexpf.html @@ -0,0 +1 @@ +libm::frexpf - Rust

[−][src]Function libm::frexpf

pub fn frexpf(x: f32) -> (f32, i32)
\ No newline at end of file diff --git a/libm/fn.hypot.html b/libm/fn.hypot.html new file mode 100644 index 000000000..41b88e3a2 --- /dev/null +++ b/libm/fn.hypot.html @@ -0,0 +1 @@ +libm::hypot - Rust

[−][src]Function libm::hypot

pub fn hypot(x: f64, y: f64) -> f64
\ No newline at end of file diff --git a/libm/fn.hypotf.html b/libm/fn.hypotf.html new file mode 100644 index 000000000..532783e76 --- /dev/null +++ b/libm/fn.hypotf.html @@ -0,0 +1 @@ +libm::hypotf - Rust

[−][src]Function libm::hypotf

pub fn hypotf(x: f32, y: f32) -> f32
\ No newline at end of file diff --git a/libm/fn.ilogb.html b/libm/fn.ilogb.html new file mode 100644 index 000000000..48b1cfeaa --- /dev/null +++ b/libm/fn.ilogb.html @@ -0,0 +1 @@ +libm::ilogb - Rust

[−][src]Function libm::ilogb

pub fn ilogb(x: f64) -> i32
\ No newline at end of file diff --git a/libm/fn.ilogbf.html b/libm/fn.ilogbf.html new file mode 100644 index 000000000..506557d7d --- /dev/null +++ b/libm/fn.ilogbf.html @@ -0,0 +1 @@ +libm::ilogbf - Rust

[−][src]Function libm::ilogbf

pub fn ilogbf(x: f32) -> i32
\ No newline at end of file diff --git a/libm/fn.j0.html b/libm/fn.j0.html new file mode 100644 index 000000000..2fa005784 --- /dev/null +++ b/libm/fn.j0.html @@ -0,0 +1 @@ +libm::j0 - Rust

[−][src]Function libm::j0

pub fn j0(x: f64) -> f64
\ No newline at end of file diff --git a/libm/fn.j0f.html b/libm/fn.j0f.html new file mode 100644 index 000000000..e2fc5a29c --- /dev/null +++ b/libm/fn.j0f.html @@ -0,0 +1 @@ +libm::j0f - Rust

[−][src]Function libm::j0f

pub fn j0f(x: f32) -> f32
\ No newline at end of file diff --git a/libm/fn.j1.html b/libm/fn.j1.html new file mode 100644 index 000000000..d4287fbc3 --- /dev/null +++ b/libm/fn.j1.html @@ -0,0 +1 @@ +libm::j1 - Rust

[−][src]Function libm::j1

pub fn j1(x: f64) -> f64
\ No newline at end of file diff --git a/libm/fn.j1f.html b/libm/fn.j1f.html new file mode 100644 index 000000000..214650979 --- /dev/null +++ b/libm/fn.j1f.html @@ -0,0 +1 @@ +libm::j1f - Rust

[−][src]Function libm::j1f

pub fn j1f(x: f32) -> f32
\ No newline at end of file diff --git a/libm/fn.jn.html b/libm/fn.jn.html new file mode 100644 index 000000000..ab78b1c1a --- /dev/null +++ b/libm/fn.jn.html @@ -0,0 +1 @@ +libm::jn - Rust

[−][src]Function libm::jn

pub fn jn(n: i32, x: f64) -> f64
\ No newline at end of file diff --git a/libm/fn.jnf.html b/libm/fn.jnf.html new file mode 100644 index 000000000..d938702a3 --- /dev/null +++ b/libm/fn.jnf.html @@ -0,0 +1 @@ +libm::jnf - Rust

[−][src]Function libm::jnf

pub fn jnf(n: i32, x: f32) -> f32
\ No newline at end of file diff --git a/libm/fn.ldexp.html b/libm/fn.ldexp.html new file mode 100644 index 000000000..205edcf97 --- /dev/null +++ b/libm/fn.ldexp.html @@ -0,0 +1 @@ +libm::ldexp - Rust

[−][src]Function libm::ldexp

pub fn ldexp(x: f64, n: i32) -> f64
\ No newline at end of file diff --git a/libm/fn.ldexpf.html b/libm/fn.ldexpf.html new file mode 100644 index 000000000..84cfb8192 --- /dev/null +++ b/libm/fn.ldexpf.html @@ -0,0 +1 @@ +libm::ldexpf - Rust

[−][src]Function libm::ldexpf

pub fn ldexpf(x: f32, n: i32) -> f32
\ No newline at end of file diff --git a/libm/fn.lgamma.html b/libm/fn.lgamma.html new file mode 100644 index 000000000..95dd8400b --- /dev/null +++ b/libm/fn.lgamma.html @@ -0,0 +1 @@ +libm::lgamma - Rust

[−][src]Function libm::lgamma

pub fn lgamma(x: f64) -> f64
\ No newline at end of file diff --git a/libm/fn.lgamma_r.html b/libm/fn.lgamma_r.html new file mode 100644 index 000000000..d40edff90 --- /dev/null +++ b/libm/fn.lgamma_r.html @@ -0,0 +1 @@ +libm::lgamma_r - Rust

[−][src]Function libm::lgamma_r

pub fn lgamma_r(x: f64) -> (f64, i32)
\ No newline at end of file diff --git a/libm/fn.lgammaf.html b/libm/fn.lgammaf.html new file mode 100644 index 000000000..6804e54aa --- /dev/null +++ b/libm/fn.lgammaf.html @@ -0,0 +1 @@ +libm::lgammaf - Rust

[−][src]Function libm::lgammaf

pub fn lgammaf(x: f32) -> f32
\ No newline at end of file diff --git a/libm/fn.lgammaf_r.html b/libm/fn.lgammaf_r.html new file mode 100644 index 000000000..3281ec75d --- /dev/null +++ b/libm/fn.lgammaf_r.html @@ -0,0 +1 @@ +libm::lgammaf_r - Rust

[−][src]Function libm::lgammaf_r

pub fn lgammaf_r(x: f32) -> (f32, i32)
\ No newline at end of file diff --git a/libm/fn.log.html b/libm/fn.log.html new file mode 100644 index 000000000..9d2e9c89d --- /dev/null +++ b/libm/fn.log.html @@ -0,0 +1 @@ +libm::log - Rust

[−][src]Function libm::log

pub fn log(x: f64) -> f64
\ No newline at end of file diff --git a/libm/fn.log10.html b/libm/fn.log10.html new file mode 100644 index 000000000..b43d8bc4e --- /dev/null +++ b/libm/fn.log10.html @@ -0,0 +1 @@ +libm::log10 - Rust

[−][src]Function libm::log10

pub fn log10(x: f64) -> f64
\ No newline at end of file diff --git a/libm/fn.log10f.html b/libm/fn.log10f.html new file mode 100644 index 000000000..9e802a13d --- /dev/null +++ b/libm/fn.log10f.html @@ -0,0 +1 @@ +libm::log10f - Rust

[−][src]Function libm::log10f

pub fn log10f(x: f32) -> f32
\ No newline at end of file diff --git a/libm/fn.log1p.html b/libm/fn.log1p.html new file mode 100644 index 000000000..30cd9b877 --- /dev/null +++ b/libm/fn.log1p.html @@ -0,0 +1 @@ +libm::log1p - Rust

[−][src]Function libm::log1p

pub fn log1p(x: f64) -> f64
\ No newline at end of file diff --git a/libm/fn.log1pf.html b/libm/fn.log1pf.html new file mode 100644 index 000000000..b0c0b2b3d --- /dev/null +++ b/libm/fn.log1pf.html @@ -0,0 +1 @@ +libm::log1pf - Rust

[−][src]Function libm::log1pf

pub fn log1pf(x: f32) -> f32
\ No newline at end of file diff --git a/libm/fn.log2.html b/libm/fn.log2.html new file mode 100644 index 000000000..472ccc7c9 --- /dev/null +++ b/libm/fn.log2.html @@ -0,0 +1 @@ +libm::log2 - Rust

[−][src]Function libm::log2

pub fn log2(x: f64) -> f64
\ No newline at end of file diff --git a/libm/fn.log2f.html b/libm/fn.log2f.html new file mode 100644 index 000000000..d19f200bf --- /dev/null +++ b/libm/fn.log2f.html @@ -0,0 +1 @@ +libm::log2f - Rust

[−][src]Function libm::log2f

pub fn log2f(x: f32) -> f32
\ No newline at end of file diff --git a/libm/fn.logf.html b/libm/fn.logf.html new file mode 100644 index 000000000..923357579 --- /dev/null +++ b/libm/fn.logf.html @@ -0,0 +1 @@ +libm::logf - Rust

[−][src]Function libm::logf

pub fn logf(x: f32) -> f32
\ No newline at end of file diff --git a/libm/fn.modf.html b/libm/fn.modf.html new file mode 100644 index 000000000..81d237827 --- /dev/null +++ b/libm/fn.modf.html @@ -0,0 +1 @@ +libm::modf - Rust

[−][src]Function libm::modf

pub fn modf(x: f64) -> (f64, f64)
\ No newline at end of file diff --git a/libm/fn.modff.html b/libm/fn.modff.html new file mode 100644 index 000000000..9273c5ca2 --- /dev/null +++ b/libm/fn.modff.html @@ -0,0 +1 @@ +libm::modff - Rust

[−][src]Function libm::modff

pub fn modff(x: f32) -> (f32, f32)
\ No newline at end of file diff --git a/libm/fn.pow.html b/libm/fn.pow.html new file mode 100644 index 000000000..460a75e1d --- /dev/null +++ b/libm/fn.pow.html @@ -0,0 +1 @@ +libm::pow - Rust

[−][src]Function libm::pow

pub fn pow(x: f64, y: f64) -> f64
\ No newline at end of file diff --git a/libm/fn.powf.html b/libm/fn.powf.html new file mode 100644 index 000000000..194769b4f --- /dev/null +++ b/libm/fn.powf.html @@ -0,0 +1 @@ +libm::powf - Rust

[−][src]Function libm::powf

pub fn powf(x: f32, y: f32) -> f32
\ No newline at end of file diff --git a/libm/fn.remquo.html b/libm/fn.remquo.html new file mode 100644 index 000000000..2eef182ac --- /dev/null +++ b/libm/fn.remquo.html @@ -0,0 +1 @@ +libm::remquo - Rust

[−][src]Function libm::remquo

pub fn remquo(x: f64, y: f64) -> (f64, i32)
\ No newline at end of file diff --git a/libm/fn.remquof.html b/libm/fn.remquof.html new file mode 100644 index 000000000..86a7b0d20 --- /dev/null +++ b/libm/fn.remquof.html @@ -0,0 +1 @@ +libm::remquof - Rust

[−][src]Function libm::remquof

pub fn remquof(x: f32, y: f32) -> (f32, i32)
\ No newline at end of file diff --git a/libm/fn.round.html b/libm/fn.round.html new file mode 100644 index 000000000..5660dd62a --- /dev/null +++ b/libm/fn.round.html @@ -0,0 +1 @@ +libm::round - Rust

[−][src]Function libm::round

pub fn round(x: f64) -> f64
\ No newline at end of file diff --git a/libm/fn.roundf.html b/libm/fn.roundf.html new file mode 100644 index 000000000..c95ac9f50 --- /dev/null +++ b/libm/fn.roundf.html @@ -0,0 +1 @@ +libm::roundf - Rust

[−][src]Function libm::roundf

pub fn roundf(x: f32) -> f32
\ No newline at end of file diff --git a/libm/fn.scalbn.html b/libm/fn.scalbn.html new file mode 100644 index 000000000..b60905905 --- /dev/null +++ b/libm/fn.scalbn.html @@ -0,0 +1 @@ +libm::scalbn - Rust

[−][src]Function libm::scalbn

pub fn scalbn(x: f64, n: i32) -> f64
\ No newline at end of file diff --git a/libm/fn.scalbnf.html b/libm/fn.scalbnf.html new file mode 100644 index 000000000..35d4dcde9 --- /dev/null +++ b/libm/fn.scalbnf.html @@ -0,0 +1 @@ +libm::scalbnf - Rust

[−][src]Function libm::scalbnf

pub fn scalbnf(x: f32, n: i32) -> f32
\ No newline at end of file diff --git a/libm/fn.sin.html b/libm/fn.sin.html new file mode 100644 index 000000000..0c11ad109 --- /dev/null +++ b/libm/fn.sin.html @@ -0,0 +1 @@ +libm::sin - Rust

[−][src]Function libm::sin

pub fn sin(x: f64) -> f64
\ No newline at end of file diff --git a/libm/fn.sincos.html b/libm/fn.sincos.html new file mode 100644 index 000000000..05f84ff7f --- /dev/null +++ b/libm/fn.sincos.html @@ -0,0 +1 @@ +libm::sincos - Rust

[−][src]Function libm::sincos

pub fn sincos(x: f64) -> (f64, f64)
\ No newline at end of file diff --git a/libm/fn.sincosf.html b/libm/fn.sincosf.html new file mode 100644 index 000000000..3930d5731 --- /dev/null +++ b/libm/fn.sincosf.html @@ -0,0 +1 @@ +libm::sincosf - Rust

[−][src]Function libm::sincosf

pub fn sincosf(x: f32) -> (f32, f32)
\ No newline at end of file diff --git a/libm/fn.sinf.html b/libm/fn.sinf.html new file mode 100644 index 000000000..1924178eb --- /dev/null +++ b/libm/fn.sinf.html @@ -0,0 +1 @@ +libm::sinf - Rust

[−][src]Function libm::sinf

pub fn sinf(x: f32) -> f32
\ No newline at end of file diff --git a/libm/fn.sinh.html b/libm/fn.sinh.html new file mode 100644 index 000000000..b028788fa --- /dev/null +++ b/libm/fn.sinh.html @@ -0,0 +1 @@ +libm::sinh - Rust

[−][src]Function libm::sinh

pub fn sinh(x: f64) -> f64
\ No newline at end of file diff --git a/libm/fn.sinhf.html b/libm/fn.sinhf.html new file mode 100644 index 000000000..1d9299502 --- /dev/null +++ b/libm/fn.sinhf.html @@ -0,0 +1 @@ +libm::sinhf - Rust

[−][src]Function libm::sinhf

pub fn sinhf(x: f32) -> f32
\ No newline at end of file diff --git a/libm/fn.sqrt.html b/libm/fn.sqrt.html new file mode 100644 index 000000000..068bcbae5 --- /dev/null +++ b/libm/fn.sqrt.html @@ -0,0 +1 @@ +libm::sqrt - Rust

[−][src]Function libm::sqrt

pub fn sqrt(x: f64) -> f64
\ No newline at end of file diff --git a/libm/fn.sqrtf.html b/libm/fn.sqrtf.html new file mode 100644 index 000000000..293f4d47f --- /dev/null +++ b/libm/fn.sqrtf.html @@ -0,0 +1 @@ +libm::sqrtf - Rust

[−][src]Function libm::sqrtf

pub fn sqrtf(x: f32) -> f32
\ No newline at end of file diff --git a/libm/fn.tan.html b/libm/fn.tan.html new file mode 100644 index 000000000..6ba99533f --- /dev/null +++ b/libm/fn.tan.html @@ -0,0 +1 @@ +libm::tan - Rust

[−][src]Function libm::tan

pub fn tan(x: f64) -> f64
\ No newline at end of file diff --git a/libm/fn.tanf.html b/libm/fn.tanf.html new file mode 100644 index 000000000..1880a598d --- /dev/null +++ b/libm/fn.tanf.html @@ -0,0 +1 @@ +libm::tanf - Rust

[−][src]Function libm::tanf

pub fn tanf(x: f32) -> f32
\ No newline at end of file diff --git a/libm/fn.tanh.html b/libm/fn.tanh.html new file mode 100644 index 000000000..ce763ed99 --- /dev/null +++ b/libm/fn.tanh.html @@ -0,0 +1 @@ +libm::tanh - Rust

[−][src]Function libm::tanh

pub fn tanh(x: f64) -> f64
\ No newline at end of file diff --git a/libm/fn.tanhf.html b/libm/fn.tanhf.html new file mode 100644 index 000000000..4a1106c12 --- /dev/null +++ b/libm/fn.tanhf.html @@ -0,0 +1 @@ +libm::tanhf - Rust

[−][src]Function libm::tanhf

pub fn tanhf(x: f32) -> f32
\ No newline at end of file diff --git a/libm/fn.tgamma.html b/libm/fn.tgamma.html new file mode 100644 index 000000000..7573bfaaa --- /dev/null +++ b/libm/fn.tgamma.html @@ -0,0 +1 @@ +libm::tgamma - Rust

[−][src]Function libm::tgamma

pub fn tgamma(x: f64) -> f64
\ No newline at end of file diff --git a/libm/fn.tgammaf.html b/libm/fn.tgammaf.html new file mode 100644 index 000000000..2c4990935 --- /dev/null +++ b/libm/fn.tgammaf.html @@ -0,0 +1 @@ +libm::tgammaf - Rust

[−][src]Function libm::tgammaf

pub fn tgammaf(x: f32) -> f32
\ No newline at end of file diff --git a/libm/fn.trunc.html b/libm/fn.trunc.html new file mode 100644 index 000000000..5cd9f03ff --- /dev/null +++ b/libm/fn.trunc.html @@ -0,0 +1 @@ +libm::trunc - Rust

[−][src]Function libm::trunc

pub fn trunc(x: f64) -> f64
\ No newline at end of file diff --git a/libm/fn.truncf.html b/libm/fn.truncf.html new file mode 100644 index 000000000..94d1d6694 --- /dev/null +++ b/libm/fn.truncf.html @@ -0,0 +1 @@ +libm::truncf - Rust

[−][src]Function libm::truncf

pub fn truncf(x: f32) -> f32
\ No newline at end of file diff --git a/libm/fn.y0.html b/libm/fn.y0.html new file mode 100644 index 000000000..521993d62 --- /dev/null +++ b/libm/fn.y0.html @@ -0,0 +1 @@ +libm::y0 - Rust

[−][src]Function libm::y0

pub fn y0(x: f64) -> f64
\ No newline at end of file diff --git a/libm/fn.y0f.html b/libm/fn.y0f.html new file mode 100644 index 000000000..0be5fd747 --- /dev/null +++ b/libm/fn.y0f.html @@ -0,0 +1 @@ +libm::y0f - Rust

[−][src]Function libm::y0f

pub fn y0f(x: f32) -> f32
\ No newline at end of file diff --git a/libm/fn.y1.html b/libm/fn.y1.html new file mode 100644 index 000000000..2c4aa4589 --- /dev/null +++ b/libm/fn.y1.html @@ -0,0 +1 @@ +libm::y1 - Rust

[−][src]Function libm::y1

pub fn y1(x: f64) -> f64
\ No newline at end of file diff --git a/libm/fn.y1f.html b/libm/fn.y1f.html new file mode 100644 index 000000000..40b4710fe --- /dev/null +++ b/libm/fn.y1f.html @@ -0,0 +1 @@ +libm::y1f - Rust

[−][src]Function libm::y1f

pub fn y1f(x: f32) -> f32
\ No newline at end of file diff --git a/libm/fn.yn.html b/libm/fn.yn.html new file mode 100644 index 000000000..08d775cc7 --- /dev/null +++ b/libm/fn.yn.html @@ -0,0 +1 @@ +libm::yn - Rust

[−][src]Function libm::yn

pub fn yn(n: i32, x: f64) -> f64
\ No newline at end of file diff --git a/libm/fn.ynf.html b/libm/fn.ynf.html new file mode 100644 index 000000000..cc879c01d --- /dev/null +++ b/libm/fn.ynf.html @@ -0,0 +1 @@ +libm::ynf - Rust

[−][src]Function libm::ynf

pub fn ynf(n: i32, x: f32) -> f32
\ No newline at end of file diff --git a/libm/index.html b/libm/index.html new file mode 100644 index 000000000..663a20c1d --- /dev/null +++ b/libm/index.html @@ -0,0 +1,61 @@ +libm - Rust

[−][src]Crate libm

libm in pure Rust

+

Usage

+

You can use this crate in two ways:

+ +

Traits

+
F32Ext

Math support for f32

+
F64Ext

Math support for f64

+

Functions

+
acos

Arccosine (f64)

+
acosf

Arccosine (f32)

+
acosh

Inverse hyperbolic cosine (f64)

+
acoshf

Inverse hyperbolic cosine (f32)

+
asin

Arcsine (f64)

+
asinf

Arcsine (f32)

+
asinh

Inverse hyperbolic sine (f64)

+
asinhf

Inverse hyperbolic sine (f32)

+
atan

Arctangent (f64)

+
atan2

Arctangent of y/x (f64)

+
atan2f

Arctangent of y/x (f32)

+
atanf

Arctangent (f32)

+
atanh

Inverse hyperbolic tangent (f64)

+
atanhf

Inverse hyperbolic tangent (f32)

+
cbrt

Computes the cube root of the argument.

+
cbrtf

Cube root (f32)

+
ceil

Ceil (f64)

+
ceilf

Ceil (f32)

+
copysign

Sign of Y, magnitude of X (f64)

+
copysignf

Sign of Y, magnitude of X (f32)

+
cos
cosf
cosh

Hyperbolic cosine (f64)

+
coshf

Hyperbolic cosine (f64)

+
erf

Error function (f64)

+
erfc

Error function (f64)

+
erfcf

Error function (f32)

+
erff

Error function (f32)

+
exp

Exponential, base e (f64)

+
exp2

Exponential, base 2 (f64)

+
exp2f

Exponential, base 2 (f32)

+
exp10
exp10f
expf

Exponential, base e (f32)

+
expm1

Exponential, base e, of x-1 (f64)

+
expm1f

Exponential, base e, of x-1 (f32)

+
fabs

Absolute value (magnitude) (f64) +Calculates the absolute value (magnitude) of the argument x, +by direct manipulation of the bit representation of x.

+
fabsf

Absolute value (magnitude) (f32) +Calculates the absolute value (magnitude) of the argument x, +by direct manipulation of the bit representation of x.

+
fdim

Positive difference (f64)

+
fdimf

Positive difference (f32)

+
floor

Floor (f64)

+
floorf

Floor (f64)

+
fma

Floating multiply add (f64)

+
fmaf

Floating multiply add (f32)

+
fmax
fmaxf
fmin
fminf
fmod
fmodf
frexp
frexpf
hypot
hypotf
ilogb
ilogbf
j0
j0f
j1
j1f
jn
jnf
ldexp
ldexpf
lgamma
lgamma_r
lgammaf
lgammaf_r
log
log1p
log1pf
log2
log2f
log10
log10f
logf
modf
modff
pow
powf
remquo
remquof
round
roundf
scalbn
scalbnf
sin
sincos
sincosf
sinf
sinh
sinhf
sqrt
sqrtf
tan
tanf
tanh
tanhf
tgamma
tgammaf
trunc
truncf
y0
y0f
y1
y1f
yn
ynf
\ No newline at end of file diff --git a/libm/math/acos/fn.acos.html b/libm/math/acos/fn.acos.html new file mode 100644 index 000000000..5d1fa2a30 --- /dev/null +++ b/libm/math/acos/fn.acos.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/libm/math/acosf/fn.acosf.html b/libm/math/acosf/fn.acosf.html new file mode 100644 index 000000000..f95217eda --- /dev/null +++ b/libm/math/acosf/fn.acosf.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/libm/math/acosh/fn.acosh.html b/libm/math/acosh/fn.acosh.html new file mode 100644 index 000000000..f5ca3fb68 --- /dev/null +++ b/libm/math/acosh/fn.acosh.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/libm/math/acoshf/fn.acoshf.html b/libm/math/acoshf/fn.acoshf.html new file mode 100644 index 000000000..d1e024046 --- /dev/null +++ b/libm/math/acoshf/fn.acoshf.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/libm/math/asin/fn.asin.html b/libm/math/asin/fn.asin.html new file mode 100644 index 000000000..c21e66032 --- /dev/null +++ b/libm/math/asin/fn.asin.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/libm/math/asinf/fn.asinf.html b/libm/math/asinf/fn.asinf.html new file mode 100644 index 000000000..3b5fc2a04 --- /dev/null +++ b/libm/math/asinf/fn.asinf.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/libm/math/asinh/fn.asinh.html b/libm/math/asinh/fn.asinh.html new file mode 100644 index 000000000..c772f95da --- /dev/null +++ b/libm/math/asinh/fn.asinh.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/libm/math/asinhf/fn.asinhf.html b/libm/math/asinhf/fn.asinhf.html new file mode 100644 index 000000000..6de67246e --- /dev/null +++ b/libm/math/asinhf/fn.asinhf.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/libm/math/atan/fn.atan.html b/libm/math/atan/fn.atan.html new file mode 100644 index 000000000..1ea7a27d1 --- /dev/null +++ b/libm/math/atan/fn.atan.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/libm/math/atan2/fn.atan2.html b/libm/math/atan2/fn.atan2.html new file mode 100644 index 000000000..574c41e6e --- /dev/null +++ b/libm/math/atan2/fn.atan2.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/libm/math/atan2f/fn.atan2f.html b/libm/math/atan2f/fn.atan2f.html new file mode 100644 index 000000000..332cb4865 --- /dev/null +++ b/libm/math/atan2f/fn.atan2f.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/libm/math/atanf/fn.atanf.html b/libm/math/atanf/fn.atanf.html new file mode 100644 index 000000000..4133a0df3 --- /dev/null +++ b/libm/math/atanf/fn.atanf.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/libm/math/atanh/fn.atanh.html b/libm/math/atanh/fn.atanh.html new file mode 100644 index 000000000..133556c75 --- /dev/null +++ b/libm/math/atanh/fn.atanh.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/libm/math/atanhf/fn.atanhf.html b/libm/math/atanhf/fn.atanhf.html new file mode 100644 index 000000000..69fa98341 --- /dev/null +++ b/libm/math/atanhf/fn.atanhf.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/libm/math/cbrt/fn.cbrt.html b/libm/math/cbrt/fn.cbrt.html new file mode 100644 index 000000000..7de81dd0a --- /dev/null +++ b/libm/math/cbrt/fn.cbrt.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/libm/math/cbrtf/fn.cbrtf.html b/libm/math/cbrtf/fn.cbrtf.html new file mode 100644 index 000000000..9d20563a3 --- /dev/null +++ b/libm/math/cbrtf/fn.cbrtf.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/libm/math/ceil/fn.ceil.html b/libm/math/ceil/fn.ceil.html new file mode 100644 index 000000000..e0a43c081 --- /dev/null +++ b/libm/math/ceil/fn.ceil.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/libm/math/ceilf/fn.ceilf.html b/libm/math/ceilf/fn.ceilf.html new file mode 100644 index 000000000..aa710880f --- /dev/null +++ b/libm/math/ceilf/fn.ceilf.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/libm/math/copysign/fn.copysign.html b/libm/math/copysign/fn.copysign.html new file mode 100644 index 000000000..bf309b544 --- /dev/null +++ b/libm/math/copysign/fn.copysign.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/libm/math/copysignf/fn.copysignf.html b/libm/math/copysignf/fn.copysignf.html new file mode 100644 index 000000000..406fd5610 --- /dev/null +++ b/libm/math/copysignf/fn.copysignf.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/libm/math/cos/fn.cos.html b/libm/math/cos/fn.cos.html new file mode 100644 index 000000000..dfbbc8218 --- /dev/null +++ b/libm/math/cos/fn.cos.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/libm/math/cosf/fn.cosf.html b/libm/math/cosf/fn.cosf.html new file mode 100644 index 000000000..54a23aae0 --- /dev/null +++ b/libm/math/cosf/fn.cosf.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/libm/math/cosh/fn.cosh.html b/libm/math/cosh/fn.cosh.html new file mode 100644 index 000000000..4c4df4fe9 --- /dev/null +++ b/libm/math/cosh/fn.cosh.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/libm/math/roundf/fn.roundf.html b/libm/math/roundf/fn.roundf.html new file mode 100644 index 000000000..6b7fb2391 --- /dev/null +++ b/libm/math/roundf/fn.roundf.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/libm/math/scalbn/fn.scalbn.html b/libm/math/scalbn/fn.scalbn.html new file mode 100644 index 000000000..27b781b6c --- /dev/null +++ b/libm/math/scalbn/fn.scalbn.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/libm/math/sinhf/fn.sinhf.html b/libm/math/sinhf/fn.sinhf.html new file mode 100644 index 000000000..fa62255f8 --- /dev/null +++ b/libm/math/sinhf/fn.sinhf.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/libm/math/sqrt/fn.sqrt.html b/libm/math/sqrt/fn.sqrt.html new file mode 100644 index 000000000..11b57912c --- /dev/null +++ b/libm/math/sqrt/fn.sqrt.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/libm/math/sqrtf/fn.sqrtf.html b/libm/math/sqrtf/fn.sqrtf.html new file mode 100644 index 000000000..aa23fac24 --- /dev/null +++ b/libm/math/sqrtf/fn.sqrtf.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/libm/math/tan/fn.tan.html b/libm/math/tan/fn.tan.html new file mode 100644 index 000000000..32620c8cd --- /dev/null +++ b/libm/math/tan/fn.tan.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/libm/math/tanf/fn.tanf.html b/libm/math/tanf/fn.tanf.html new file mode 100644 index 000000000..a9d01a307 --- /dev/null +++ b/libm/math/tanf/fn.tanf.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/libm/math/tgamma/fn.tgamma.html b/libm/math/tgamma/fn.tgamma.html new file mode 100644 index 000000000..c2dc6616d --- /dev/null +++ b/libm/math/tgamma/fn.tgamma.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/libm/math/trunc/fn.trunc.html b/libm/math/trunc/fn.trunc.html new file mode 100644 index 000000000..e615a5d6b --- /dev/null +++ b/libm/math/trunc/fn.trunc.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/libm/math/truncf/fn.truncf.html b/libm/math/truncf/fn.truncf.html new file mode 100644 index 000000000..41859aceb --- /dev/null +++ b/libm/math/truncf/fn.truncf.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/libm/sidebar-items.js b/libm/sidebar-items.js new file mode 100644 index 000000000..468bb0edf --- /dev/null +++ b/libm/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({"fn":[["acos","Arccosine (f64)"],["acosf","Arccosine (f32)"],["acosh","Inverse hyperbolic cosine (f64)"],["acoshf","Inverse hyperbolic cosine (f32)"],["asin","Arcsine (f64)"],["asinf","Arcsine (f32)"],["asinh","Inverse hyperbolic sine (f64)"],["asinhf","Inverse hyperbolic sine (f32)"],["atan","Arctangent (f64)"],["atan2","Arctangent of y/x (f64)"],["atan2f","Arctangent of y/x (f32)"],["atanf","Arctangent (f32)"],["atanh","Inverse hyperbolic tangent (f64)"],["atanhf","Inverse hyperbolic tangent (f32)"],["cbrt","Computes the cube root of the argument."],["cbrtf","Cube root (f32)"],["ceil","Ceil (f64)"],["ceilf","Ceil (f32)"],["copysign","Sign of Y, magnitude of X (f64)"],["copysignf","Sign of Y, magnitude of X (f32)"],["cos",""],["cosf",""],["cosh","Hyperbolic cosine (f64)"],["coshf","Hyperbolic cosine (f64)"],["erf","Error function (f64)"],["erfc","Error function (f64)"],["erfcf","Error function (f32)"],["erff","Error function (f32)"],["exp","Exponential, base e (f64)"],["exp10",""],["exp10f",""],["exp2","Exponential, base 2 (f64)"],["exp2f","Exponential, base 2 (f32)"],["expf","Exponential, base e (f32)"],["expm1","Exponential, base e, of x-1 (f64)"],["expm1f","Exponential, base e, of x-1 (f32)"],["fabs","Absolute value (magnitude) (f64) Calculates the absolute value (magnitude) of the argument `x`, by direct manipulation of the bit representation of `x`."],["fabsf","Absolute value (magnitude) (f32) Calculates the absolute value (magnitude) of the argument `x`, by direct manipulation of the bit representation of `x`."],["fdim","Positive difference (f64)"],["fdimf","Positive difference (f32)"],["floor","Floor (f64)"],["floorf","Floor (f64)"],["fma","Floating multiply add (f64)"],["fmaf","Floating multiply add (f32)"],["fmax",""],["fmaxf",""],["fmin",""],["fminf",""],["fmod",""],["fmodf",""],["frexp",""],["frexpf",""],["hypot",""],["hypotf",""],["ilogb",""],["ilogbf",""],["j0",""],["j0f",""],["j1",""],["j1f",""],["jn",""],["jnf",""],["ldexp",""],["ldexpf",""],["lgamma",""],["lgamma_r",""],["lgammaf",""],["lgammaf_r",""],["log",""],["log10",""],["log10f",""],["log1p",""],["log1pf",""],["log2",""],["log2f",""],["logf",""],["modf",""],["modff",""],["pow",""],["powf",""],["remquo",""],["remquof",""],["round",""],["roundf",""],["scalbn",""],["scalbnf",""],["sin",""],["sincos",""],["sincosf",""],["sinf",""],["sinh",""],["sinhf",""],["sqrt",""],["sqrtf",""],["tan",""],["tanf",""],["tanh",""],["tanhf",""],["tgamma",""],["tgammaf",""],["trunc",""],["truncf",""],["y0",""],["y0f",""],["y1",""],["y1f",""],["yn",""],["ynf",""]],"trait":[["F32Ext","Math support for `f32`"],["F64Ext","Math support for `f64`"]]}); \ No newline at end of file diff --git a/libm/trait.F32Ext.html b/libm/trait.F32Ext.html new file mode 100644 index 000000000..3f09a3540 --- /dev/null +++ b/libm/trait.F32Ext.html @@ -0,0 +1,44 @@ +libm::F32Ext - Rust

[−][src]Trait libm::F32Ext

pub trait F32Ext: Sealed + Sized {
+    fn floor(self) -> Self;
+
    fn ceil(self) -> Self;
+
    fn round(self) -> Self;
+
    fn trunc(self) -> Self;
+
    fn fdim(self, rhs: Self) -> Self;
+
    fn fract(self) -> Self;
+
    fn abs(self) -> Self;
+
    fn mul_add(self, a: Self, b: Self) -> Self;
+
    fn div_euc(self, rhs: Self) -> Self;
+
    fn mod_euc(self, rhs: Self) -> Self;
+
    fn powf(self, n: Self) -> Self;
+
    fn sqrt(self) -> Self;
+
    fn exp(self) -> Self;
+
    fn exp2(self) -> Self;
+
    fn ln(self) -> Self;
+
    fn log(self, base: Self) -> Self;
+
    fn log2(self) -> Self;
+
    fn log10(self) -> Self;
+
    fn cbrt(self) -> Self;
+
    fn hypot(self, other: Self) -> Self;
+
    fn sin(self) -> Self;
+
    fn cos(self) -> Self;
+
    fn tan(self) -> Self;
+
    fn asin(self) -> Self;
+
    fn acos(self) -> Self;
+
    fn atan(self) -> Self;
+
    fn atan2(self, other: Self) -> Self;
+
    fn sin_cos(self) -> (Self, Self);
+
    fn exp_m1(self) -> Self;
+
    fn ln_1p(self) -> Self;
+
    fn sinh(self) -> Self;
+
    fn cosh(self) -> Self;
+
    fn tanh(self) -> Self;
+
    fn asinh(self) -> Self;
+
    fn acosh(self) -> Self;
+
    fn atanh(self) -> Self;
+
    fn min(self, other: Self) -> Self;
+
    fn max(self, other: Self) -> Self;
+}

Math support for f32

+

This trait is sealed and cannot be implemented outside of libm.

+
+

Required methods

fn floor(self) -> Self

fn ceil(self) -> Self

fn round(self) -> Self

fn trunc(self) -> Self

fn fdim(self, rhs: Self) -> Self

fn fract(self) -> Self

fn abs(self) -> Self

fn mul_add(self, a: Self, b: Self) -> Self

fn div_euc(self, rhs: Self) -> Self

fn mod_euc(self, rhs: Self) -> Self

fn powf(self, n: Self) -> Self

fn sqrt(self) -> Self

fn exp(self) -> Self

fn exp2(self) -> Self

fn ln(self) -> Self

fn log(self, base: Self) -> Self

fn log2(self) -> Self

fn log10(self) -> Self

fn cbrt(self) -> Self

fn hypot(self, other: Self) -> Self

fn sin(self) -> Self

fn cos(self) -> Self

fn tan(self) -> Self

fn asin(self) -> Self

fn acos(self) -> Self

fn atan(self) -> Self

fn atan2(self, other: Self) -> Self

fn sin_cos(self) -> (Self, Self)

fn exp_m1(self) -> Self

fn ln_1p(self) -> Self

fn sinh(self) -> Self

fn cosh(self) -> Self

fn tanh(self) -> Self

fn asinh(self) -> Self

fn acosh(self) -> Self

fn atanh(self) -> Self

fn min(self, other: Self) -> Self

fn max(self, other: Self) -> Self

Loading content... +

Implementors

impl F32Ext for f32[src]

Loading content...
\ No newline at end of file diff --git a/libm/trait.F64Ext.html b/libm/trait.F64Ext.html new file mode 100644 index 000000000..c6248de85 --- /dev/null +++ b/libm/trait.F64Ext.html @@ -0,0 +1,44 @@ +libm::F64Ext - Rust

[−][src]Trait libm::F64Ext

pub trait F64Ext: Sealed + Sized {
+    fn floor(self) -> Self;
+
    fn ceil(self) -> Self;
+
    fn round(self) -> Self;
+
    fn trunc(self) -> Self;
+
    fn fdim(self, rhs: Self) -> Self;
+
    fn fract(self) -> Self;
+
    fn abs(self) -> Self;
+
    fn mul_add(self, a: Self, b: Self) -> Self;
+
    fn div_euc(self, rhs: Self) -> Self;
+
    fn mod_euc(self, rhs: Self) -> Self;
+
    fn powf(self, n: Self) -> Self;
+
    fn sqrt(self) -> Self;
+
    fn exp(self) -> Self;
+
    fn exp2(self) -> Self;
+
    fn ln(self) -> Self;
+
    fn log(self, base: Self) -> Self;
+
    fn log2(self) -> Self;
+
    fn log10(self) -> Self;
+
    fn cbrt(self) -> Self;
+
    fn hypot(self, other: Self) -> Self;
+
    fn sin(self) -> Self;
+
    fn cos(self) -> Self;
+
    fn tan(self) -> Self;
+
    fn asin(self) -> Self;
+
    fn acos(self) -> Self;
+
    fn atan(self) -> Self;
+
    fn atan2(self, other: Self) -> Self;
+
    fn sin_cos(self) -> (Self, Self);
+
    fn exp_m1(self) -> Self;
+
    fn ln_1p(self) -> Self;
+
    fn sinh(self) -> Self;
+
    fn cosh(self) -> Self;
+
    fn tanh(self) -> Self;
+
    fn asinh(self) -> Self;
+
    fn acosh(self) -> Self;
+
    fn atanh(self) -> Self;
+
    fn min(self, other: Self) -> Self;
+
    fn max(self, other: Self) -> Self;
+}

Math support for f64

+

This trait is sealed and cannot be implemented outside of libm.

+
+

Required methods

fn floor(self) -> Self

fn ceil(self) -> Self

fn round(self) -> Self

fn trunc(self) -> Self

fn fdim(self, rhs: Self) -> Self

fn fract(self) -> Self

fn abs(self) -> Self

fn mul_add(self, a: Self, b: Self) -> Self

fn div_euc(self, rhs: Self) -> Self

fn mod_euc(self, rhs: Self) -> Self

fn powf(self, n: Self) -> Self

fn sqrt(self) -> Self

fn exp(self) -> Self

fn exp2(self) -> Self

fn ln(self) -> Self

fn log(self, base: Self) -> Self

fn log2(self) -> Self

fn log10(self) -> Self

fn cbrt(self) -> Self

fn hypot(self, other: Self) -> Self

fn sin(self) -> Self

fn cos(self) -> Self

fn tan(self) -> Self

fn asin(self) -> Self

fn acos(self) -> Self

fn atan(self) -> Self

fn atan2(self, other: Self) -> Self

fn sin_cos(self) -> (Self, Self)

fn exp_m1(self) -> Self

fn ln_1p(self) -> Self

fn sinh(self) -> Self

fn cosh(self) -> Self

fn tanh(self) -> Self

fn asinh(self) -> Self

fn acosh(self) -> Self

fn atanh(self) -> Self

fn min(self, other: Self) -> Self

fn max(self, other: Self) -> Self

Loading content... +

Implementors

impl F64Ext for f64[src]

Loading content...
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[−] + + List of all items

Structs

Traits

Macros

Typedefs

\ No newline at end of file diff --git a/packed_simd/api/cast/trait.Cast.html b/packed_simd/api/cast/trait.Cast.html new file mode 100644 index 000000000..c9d8178d1 --- /dev/null +++ b/packed_simd/api/cast/trait.Cast.html @@ -0,0 +1,10 @@ + + + + + + +

Redirecting to ../../../packed_simd/trait.Cast.html...

+ + + \ No newline at end of file diff --git a/packed_simd/api/cast/trait.FromCast.html b/packed_simd/api/cast/trait.FromCast.html new file mode 100644 index 000000000..c05d12a8f --- /dev/null +++ b/packed_simd/api/cast/trait.FromCast.html @@ -0,0 +1,10 @@ + + + + + + +

Redirecting to ../../../packed_simd/trait.FromCast.html...

+ + + \ No newline at end of file diff --git a/packed_simd/api/into_bits/trait.FromBits.html b/packed_simd/api/into_bits/trait.FromBits.html new file mode 100644 index 000000000..2c23e00fe --- /dev/null +++ b/packed_simd/api/into_bits/trait.FromBits.html @@ -0,0 +1,10 @@ + + + + + + +

Redirecting to ../../../packed_simd/trait.FromBits.html...

+ + + \ No newline at end of file diff --git a/packed_simd/api/into_bits/trait.IntoBits.html b/packed_simd/api/into_bits/trait.IntoBits.html new file mode 100644 index 000000000..28f067d7b --- /dev/null +++ b/packed_simd/api/into_bits/trait.IntoBits.html @@ -0,0 +1,10 @@ + + + + + + +

Redirecting to ../../../packed_simd/trait.IntoBits.html...

+ + + \ No newline at end of file diff --git a/packed_simd/index.html b/packed_simd/index.html new file mode 100644 index 000000000..1e310e418 --- /dev/null +++ b/packed_simd/index.html @@ -0,0 +1,290 @@ +packed_simd - Rust

[−][src]Crate packed_simd

Portable packed SIMD vectors

+

This crate is proposed for stabilization as std::packed_simd in RFC2366: +std::simd .

+

The examples available in the +examples/ +sub-directory of the crate showcase how to use the library in practice.

+

Table of contents

+ +

Introduction

+

This crate exports Simd<[T; N]>: a packed vector of N +elements of type T as well as many type aliases for this type: for +example, f32x4, which is just an alias for Simd<[f32; 4]>.

+

The operations on packed vectors are, by default, "vertical", that is, they +are applied to each vector lane in isolation of the others:

+ +
+let a = i32x4::new(1, 2, 3, 4);
+let b = i32x4::new(5, 6, 7, 8);
+assert_eq!(a + b, i32x4::new(6, 8, 10, 12));
+

Many "horizontal" operations are also provided:

+ +
+assert_eq!(a.wrapping_sum(), 10);
+

In virtually all architectures vertical operations are fast, while +horizontal operations are, by comparison, much slower. That is, the +most portably-efficient way of performing a reduction over a slice +is to collect the results into a vector using vertical operations, +and performing a single horizontal operation at the end:

+ +
+fn reduce(x: &[i32]) -> i32 {
+    assert!(x.len() % 4 == 0);
+    let mut sum = i32x4::splat(0); // [0, 0, 0, 0]
+    for i in (0..x.len()).step_by(4) {
+        sum += i32x4::from_slice_unaligned(&x[i..]);
+    }
+    sum.wrapping_sum()
+}
+
+let x = [0, 1, 2, 3, 4, 5, 6, 7];
+assert_eq!(reduce(&x), 28);
+

Vector types

+

The vector type aliases are named according to the following scheme:

+
+

{element_type}x{number_of_lanes} == Simd<[element_type; number_of_lanes]>

+
+

where the following element types are supported:

+
    +
  • i{element_width}: signed integer
    • +
  • u{element_width}: unsigned integer
    • +
  • f{element_width}: float
    • +
  • m{element_width}: mask (see below)
    • +
  • *{const,mut} T: const and mut pointers
    • +
+

Basic operations

+
+// Sets all elements to `0`:
+let a = i32x4::splat(0);
+
+// Reads a vector from a slice:
+let mut arr = [0, 0, 0, 1, 2, 3, 4, 5];
+let b = i32x4::from_slice_unaligned(&arr);
+
+// Reads the 4-th element of a vector:
+assert_eq!(b.extract(3), 1);
+
+// Returns a new vector where the 4-th element is replaced with `1`:
+let a = a.replace(3, 1);
+assert_eq!(a, b);
+
+// Writes a vector to a slice:
+let a = a.replace(2, 1);
+a.write_to_slice_unaligned(&mut arr[4..]);
+assert_eq!(arr, [0, 0, 0, 1, 0, 0, 1, 1]);
+

Conditional operations

+

One often needs to perform an operation on some lanes of the vector. Vector +masks, like m32x4, allow selecting on which vector lanes an operation is +to be performed:

+ +
+let a = i32x4::new(1, 1, 2, 2);
+
+// Add `1` to the first two lanes of the vector.
+let m = m16x4::new(true, true, false, false);
+let a = m.select(a + 1, a);
+assert_eq!(a, i32x4::splat(2));
+

The elements of a vector mask are either true or false. Here true +means that a lane is "selected", while false means that a lane is not +selected.

+

All vector masks implement a mask.select(a: T, b: T) -> T method that +works on all vectors that have the same number of lanes as the mask. The +resulting vector contains the elements of a for those lanes for which the +mask is true, and the elements of b otherwise.

+

The example constructs a mask with the first two lanes set to true and +the last two lanes set to false. This selects the first two lanes of a + 1 and the last two lanes of a, producing a vector where the first two +lanes have been incremented by 1.

+
+

note: mask select can be used on vector types that have the same number +of lanes as the mask. The example shows this by using m16x4 instead +of m32x4. It is typically more performant to use a mask element +width equal to the element width of the vectors being operated upon. +This is, however, not true for 512-bit wide vectors when targetting +AVX-512, where the most efficient masks use only 1-bit per element.

+
+

All vertical comparison operations returns masks:

+ +
+let a = i32x4::new(1, 1, 3, 3);
+let b = i32x4::new(2, 2, 0, 0);
+
+// ge: >= (Greater Eequal; see also lt, le, gt, eq, ne).
+let m = a.ge(i32x4::splat(2));
+
+if m.any() {
+    // all / any / none allow coherent control flow
+    let d = m.select(a, b);
+    assert_eq!(d, i32x4::new(2, 2, 3, 3));
+}
+

Conversions

+
    +
  • +

    lossless widening conversions: From/Into are implemented for +vectors with the same number of lanes when the conversion is value +preserving (same as in std).

    +
    • +
  • +

    safe bitwise conversions: The cargo feature into_bits provides the +IntoBits/FromBits traits (x.into_bits()). These perform safe bitwise +transmutes when all bit patterns of the source type are valid bit +patterns of the target type and are also implemented for the +architecture-specific vector types of std::arch. For example, let x: u8x8 = m8x8::splat(true).into_bits(); is provided because all m8x8 bit +patterns are valid u8x8 bit patterns. However, the opposite is not +true, not all u8x8 bit patterns are valid m8x8 bit-patterns, so this +operation cannot be peformed safely using x.into_bits(); one needs to +use unsafe { crate::mem::transmute(x) } for that, making sure that the +value in the u8x8 is a valid bit-pattern of m8x8.

    +
    • +
  • +

    numeric casts (as): are peformed using FromCast/Cast +(x.cast()), just like as:

    +
      +
    • +

      casting integer vectors whose lane types have the same size (e.g. +i32xN -> u32xN) is a no-op,

      +
      • +
    • +

      casting from a larger integer to a smaller integer (e.g. u32xN -> +u8xN) will truncate,

      +
      • +
    • +

      casting from a smaller integer to a larger integer (e.g. u8xN -> +u32xN) will:

      +
        +
      • zero-extend if the source is unsigned, or
        • +
      • sign-extend if the source is signed,
        • +
      +
      • +
    • +

      casting from a float to an integer will round the float towards +zero,

      +
      • +
    • +

      casting from an integer to float will produce the floating point +representation of the integer, rounding to nearest, ties to even,

      +
      • +
    • +

      casting from an f32 to an f64 is perfect and lossless,

      +
      • +
    • +

      casting from an f64 to an f32 rounds to nearest, ties to even.

      +
      • +
    +

    Numeric casts are not very "precise": sometimes lossy, sometimes value +preserving, etc.

    +
    • +
+

Macros

+
shuffle

Shuffles vector elements.

+

Structs

+
LexicographicallyOrdered

Wrapper over T implementing a lexicoraphical order via the PartialOrd +and/or Ord traits.

+
Simd

Packed SIMD vector type.

+
m8

8-bit wide mask.

+
m16

16-bit wide mask.

+
m32

32-bit wide mask.

+
m64

64-bit wide mask.

+
m128

128-bit wide mask.

+
msize

isize-wide mask.

+

Traits

+
Cast

Numeric cast from Self to T.

+
FromBits

Safe lossless bitwise conversion from T to Self.

+
FromCast

Numeric cast from T to Self.

+
IntoBits

Safe lossless bitwise conversion from Self to T.

+
Mask

This trait is implemented by all mask types

+
SimdArray

Trait implemented by arrays that can be SIMD types.

+
SimdVector

This trait is implemented by all SIMD vector types.

+

Type Definitions

+
cptrx2

A vector with 2 *const T lanes

+
cptrx4

A vector with 4 *const T lanes

+
cptrx8

A vector with 8 *const T lanes

+
f32x2

A 64-bit vector with 2 f32 lanes.

+
f32x4

A 128-bit vector with 4 f32 lanes.

+
f32x8

A 256-bit vector with 8 f32 lanes.

+
f32x16

A 512-bit vector with 16 f32 lanes.

+
f64x2

A 128-bit vector with 2 f64 lanes.

+
f64x4

A 256-bit vector with 4 f64 lanes.

+
f64x8

A 512-bit vector with 8 f64 lanes.

+
i128x1

A 128-bit vector with 1 i128 lane.

+
i128x2

A 256-bit vector with 2 i128 lanes.

+
i128x4

A 512-bit vector with 4 i128 lanes.

+
i16x2

A 32-bit vector with 2 i16 lanes.

+
i16x4

A 64-bit vector with 4 i16 lanes.

+
i16x8

A 128-bit vector with 8 i16 lanes.

+
i16x16

A 256-bit vector with 16 i16 lanes.

+
i16x32

A 512-bit vector with 32 i16 lanes.

+
i32x2

A 64-bit vector with 2 i32 lanes.

+
i32x4

A 128-bit vector with 4 i32 lanes.

+
i32x8

A 256-bit vector with 8 i32 lanes.

+
i32x16

A 512-bit vector with 16 i32 lanes.

+
i64x2

A 128-bit vector with 2 i64 lanes.

+
i64x4

A 256-bit vector with 4 i64 lanes.

+
i64x8

A 512-bit vector with 8 i64 lanes.

+
i8x2

A 16-bit vector with 2 i8 lanes.

+
i8x4

A 32-bit vector with 4 i8 lanes.

+
i8x8

A 64-bit vector with 8 i8 lanes.

+
i8x16

A 128-bit vector with 16 i8 lanes.

+
i8x32

A 256-bit vector with 32 i8 lanes.

+
i8x64

A 512-bit vector with 64 i8 lanes.

+
isizex2

A vector with 2 isize lanes.

+
isizex4

A vector with 4 isize lanes.

+
isizex8

A vector with 4 isize lanes.

+
m128x1

A 128-bit vector mask with 1 m128 lane.

+
m128x2

A 256-bit vector mask with 2 m128 lanes.

+
m128x4

A 512-bit vector mask with 4 m128 lanes.

+
m16x2

A 32-bit vector mask with 2 m16 lanes.

+
m16x4

A 64-bit vector mask with 4 m16 lanes.

+
m16x8

A 128-bit vector mask with 8 m16 lanes.

+
m16x16

A 256-bit vector mask with 16 m16 lanes.

+
m16x32

A 512-bit vector mask with 32 m16 lanes.

+
m32x2

A 64-bit vector mask with 2 m32 lanes.

+
m32x4

A 128-bit vector mask with 4 m32 lanes.

+
m32x8

A 256-bit vector mask with 8 m32 lanes.

+
m32x16

A 512-bit vector mask with 16 m32 lanes.

+
m64x2

A 128-bit vector mask with 2 m64 lanes.

+
m64x4

A 256-bit vector mask with 4 m64 lanes.

+
m64x8

A 512-bit vector mask with 8 m64 lanes.

+
m8x2

A 16-bit vector mask with 2 m8 lanes.

+
m8x4

A 32-bit vector mask with 4 m8 lanes.

+
m8x8

A 64-bit vector mask with 8 m8 lanes.

+
m8x16

A 128-bit vector mask with 16 m8 lanes.

+
m8x32

A 256-bit vector mask with 32 m8 lanes.

+
m8x64

A 512-bit vector mask with 64 m8 lanes.

+
mptrx2

A vector with 2 *mut T lanes

+
mptrx4

A vector with 4 *mut T lanes

+
mptrx8

A vector with 8 *mut T lanes

+
msizex2

A vector mask with 2 msize lanes.

+
msizex4

A vector mask with 4 msize lanes.

+
msizex8

A vector mask with 8 msize lanes.

+
u128x1

A 128-bit vector with 1 u128 lane.

+
u128x2

A 256-bit vector with 2 u128 lanes.

+
u128x4

A 512-bit vector with 4 u128 lanes.

+
u16x2

A 32-bit vector with 2 u16 lanes.

+
u16x4

A 64-bit vector with 4 u16 lanes.

+
u16x8

A 128-bit vector with 8 u16 lanes.

+
u16x16

A 256-bit vector with 16 u16 lanes.

+
u16x32

A 512-bit vector with 32 u16 lanes.

+
u32x2

A 64-bit vector with 2 u32 lanes.

+
u32x4

A 128-bit vector with 4 u32 lanes.

+
u32x8

A 256-bit vector with 8 u32 lanes.

+
u32x16

A 512-bit vector with 16 u32 lanes.

+
u64x2

A 128-bit vector with 2 u64 lanes.

+
u64x4

A 256-bit vector with 4 u64 lanes.

+
u64x8

A 512-bit vector with 8 u64 lanes.

+
u8x2

A 16-bit vector with 2 u8 lanes.

+
u8x4

A 32-bit vector with 4 u8 lanes.

+
u8x8

A 64-bit vector with 8 u8 lanes.

+
u8x16

A 128-bit vector with 16 u8 lanes.

+
u8x32

A 256-bit vector with 32 u8 lanes.

+
u8x64

A 512-bit vector with 64 u8 lanes.

+
usizex2

A vector with 2 usize lanes.

+
usizex4

A vector with 4 usize lanes.

+
usizex8

A vector with 8 usize lanes.

+
\ No newline at end of file diff --git a/packed_simd/macro.shuffle!.html b/packed_simd/macro.shuffle!.html new file mode 100644 index 000000000..8ba23da2e --- /dev/null +++ b/packed_simd/macro.shuffle!.html @@ -0,0 +1,10 @@ + + + + + + +

Redirecting to macro.shuffle.html...

+ + + \ No newline at end of file diff --git a/packed_simd/macro.shuffle.html b/packed_simd/macro.shuffle.html new file mode 100644 index 000000000..d3a817c09 --- /dev/null +++ b/packed_simd/macro.shuffle.html @@ -0,0 +1,92 @@ +packed_simd::shuffle - Rust

[−][src]Macro packed_simd::shuffle

+macro_rules! shuffle {
+    ($vec0:expr, $vec1:expr, [$l0:expr, $l1:expr]) => { ... };
+    ($vec0:expr, $vec1:expr, [$l0:expr, $l1:expr, $l2:expr, $l3:expr]) => { ... };
+    ($vec0:expr, $vec1:expr,
+     [$l0:expr, $l1:expr, $l2:expr, $l3:expr,
+      $l4:expr, $l5:expr, $l6:expr, $l7:expr]) => { ... };
+    ($vec0:expr, $vec1:expr,
+     [$l0:expr, $l1:expr, $l2:expr, $l3:expr,
+      $l4:expr, $l5:expr, $l6:expr, $l7:expr,
+      $l8:expr, $l9:expr, $l10:expr, $l11:expr,
+      $l12:expr, $l13:expr, $l14:expr, $l15:expr]) => { ... };
+    ($vec0:expr, $vec1:expr,
+     [$l0:expr, $l1:expr, $l2:expr, $l3:expr,
+      $l4:expr, $l5:expr, $l6:expr, $l7:expr,
+      $l8:expr, $l9:expr, $l10:expr, $l11:expr,
+      $l12:expr, $l13:expr, $l14:expr, $l15:expr,
+      $l16:expr, $l17:expr, $l18:expr, $l19:expr,
+      $l20:expr, $l21:expr, $l22:expr, $l23:expr,
+      $l24:expr, $l25:expr, $l26:expr, $l27:expr,
+      $l28:expr, $l29:expr, $l30:expr, $l31:expr]) => { ... };
+    ($vec0:expr, $vec1:expr,
+     [$l0:expr, $l1:expr, $l2:expr, $l3:expr,
+      $l4:expr, $l5:expr, $l6:expr, $l7:expr,
+      $l8:expr, $l9:expr, $l10:expr, $l11:expr,
+      $l12:expr, $l13:expr, $l14:expr, $l15:expr,
+      $l16:expr, $l17:expr, $l18:expr, $l19:expr,
+      $l20:expr, $l21:expr, $l22:expr, $l23:expr,
+      $l24:expr, $l25:expr, $l26:expr, $l27:expr,
+      $l28:expr, $l29:expr, $l30:expr, $l31:expr,
+      $l32:expr, $l33:expr, $l34:expr, $l35:expr,
+      $l36:expr, $l37:expr, $l38:expr, $l39:expr,
+      $l40:expr, $l41:expr, $l42:expr, $l43:expr,
+      $l44:expr, $l45:expr, $l46:expr, $l47:expr,
+      $l48:expr, $l49:expr, $l50:expr, $l51:expr,
+      $l52:expr, $l53:expr, $l54:expr, $l55:expr,
+      $l56:expr, $l57:expr, $l58:expr, $l59:expr,
+      $l60:expr, $l61:expr, $l62:expr, $l63:expr]) => { ... };
+    ($vec:expr, [$($l:expr),*]) => { ... };
+}
+

Shuffles vector elements.

+

This macro returns a new vector that contains a shuffle of the elements in +one (shuffle!(vec, [indices...])) or two (shuffle!(vec0, vec1, [indices...])) input vectors.

+

The type of vec0 and vec1 must be equal, and the element type of the +resulting vector is the element type of the input vector.

+

The number of indices must be a power-of-two in range [0, 64), since +currently, the largest vector supported by the library has 64 lanes. The +length of the resulting vector equals the number of indices provided.

+

The indices must be in range [0, M * N) where M is the number of input +vectors (1 or 2) and N is the number of lanes of the input vectors. +The indices i in range [0, N) refer to the i-th element of vec0, +while the indices in range [N, 2*N) refer to the i - N-th element of +vec1.

+

Examples

+

Shuffling elements of two vectors:

+ +
+// Shuffle allows reordering the elements:
+let x = i32x4::new(1, 2, 3, 4);
+let y = i32x4::new(5, 6, 7, 8);
+let r = shuffle!(x, y, [4, 0, 5, 1]);
+assert_eq!(r, i32x4::new(5, 1, 6, 2));
+
+// The resulting vector can als be smaller than the input:
+let r = shuffle!(x, y, [1, 6]);
+assert_eq!(r, i32x2::new(2, 7));
+
+// Or larger:
+let r = shuffle!(x, y, [1, 3, 4, 2, 1, 7, 2, 2]);
+assert_eq!(r, i32x8::new(2, 4, 5, 3, 2, 8, 3, 3));
+// At most 2 * the number of lanes in the input vector.
+

Shuffling elements of one vector:

+ +
+// Shuffle allows reordering the elements of a vector:
+let x = i32x4::new(1, 2, 3, 4);
+let r = shuffle!(x, [2, 1, 3, 0]);
+assert_eq!(r, i32x4::new(3, 2, 4, 1));
+
+// The resulting vector can be smaller than the input:
+let r = shuffle!(x, [1, 3]);
+assert_eq!(r, i32x2::new(2, 4));
+
+// Equal:
+let r = shuffle!(x, [1, 3, 2, 0]);
+assert_eq!(r, i32x4::new(2, 4, 3, 1));
+
+// Or larger:
+let r = shuffle!(x, [1, 3, 2, 2, 1, 3, 2, 2]);
+assert_eq!(r, i32x8::new(2, 4, 3, 3, 2, 4, 3, 3));
+// At most 2 * the number of lanes in the input vector.
+
\ No newline at end of file diff --git a/packed_simd/masks/struct.m128.html b/packed_simd/masks/struct.m128.html new file mode 100644 index 000000000..16f94f2b2 --- /dev/null +++ b/packed_simd/masks/struct.m128.html @@ -0,0 +1,10 @@ + + + + + + +

Redirecting to ../../packed_simd/struct.m128.html...

+ + + \ No newline at end of file diff --git a/packed_simd/masks/struct.m16.html b/packed_simd/masks/struct.m16.html new file mode 100644 index 000000000..b325bded2 --- /dev/null +++ b/packed_simd/masks/struct.m16.html @@ -0,0 +1,10 @@ + + + + + + +

Redirecting to ../../packed_simd/struct.m16.html...

+ + + \ No newline at end of file diff --git a/packed_simd/masks/struct.m32.html b/packed_simd/masks/struct.m32.html new file mode 100644 index 000000000..1227cfb92 --- /dev/null +++ b/packed_simd/masks/struct.m32.html @@ -0,0 +1,10 @@ + + + + + + +

Redirecting to ../../packed_simd/struct.m32.html...

+ + + \ No newline at end of file diff --git a/packed_simd/masks/struct.m64.html b/packed_simd/masks/struct.m64.html new file mode 100644 index 000000000..6df1ad61d --- /dev/null +++ b/packed_simd/masks/struct.m64.html @@ -0,0 +1,10 @@ + + + + + + +

Redirecting to ../../packed_simd/struct.m64.html...

+ + + \ No newline at end of file diff --git a/packed_simd/masks/struct.m8.html b/packed_simd/masks/struct.m8.html new file mode 100644 index 000000000..a05f8ec22 --- /dev/null +++ b/packed_simd/masks/struct.m8.html @@ -0,0 +1,10 @@ + + + + + + +

Redirecting to ../../packed_simd/struct.m8.html...

+ + + \ No newline at end of file diff --git a/packed_simd/masks/struct.msize.html b/packed_simd/masks/struct.msize.html new file mode 100644 index 000000000..57f8b1276 --- /dev/null +++ b/packed_simd/masks/struct.msize.html @@ -0,0 +1,10 @@ + + + + + + +

Redirecting to ../../packed_simd/struct.msize.html...

+ + + \ No newline at end of file diff --git a/packed_simd/sealed/trait.Mask.html b/packed_simd/sealed/trait.Mask.html new file mode 100644 index 000000000..71611d4ee --- /dev/null +++ b/packed_simd/sealed/trait.Mask.html @@ -0,0 +1,10 @@ + + + + + + +

Redirecting to ../../packed_simd/trait.Mask.html...

+ + + \ No newline at end of file diff --git a/packed_simd/sealed/trait.Simd.html b/packed_simd/sealed/trait.Simd.html new file mode 100644 index 000000000..d78b1b9c3 --- /dev/null +++ b/packed_simd/sealed/trait.Simd.html @@ -0,0 +1,10 @@ + + + + + + +

Redirecting to ../../packed_simd/trait.SimdVector.html...

+ + + \ No newline at end of file diff --git a/packed_simd/sealed/trait.SimdArray.html b/packed_simd/sealed/trait.SimdArray.html new file mode 100644 index 000000000..374fbb0e4 --- /dev/null +++ b/packed_simd/sealed/trait.SimdArray.html @@ -0,0 +1,10 @@ + + + + + + +

Redirecting to ../../packed_simd/trait.SimdArray.html...

+ + + \ No newline at end of file diff --git a/packed_simd/sidebar-items.js b/packed_simd/sidebar-items.js new file mode 100644 index 000000000..7f50794bc --- /dev/null +++ b/packed_simd/sidebar-items.js @@ -0,0 +1 @@ +initSidebarItems({"macro":[["shuffle","Shuffles vector elements."]],"struct":[["LexicographicallyOrdered","Wrapper over `T` implementing a lexicoraphical order via the `PartialOrd` and/or `Ord` traits."],["Simd","Packed SIMD vector type."],["m128","128-bit wide mask."],["m16","16-bit wide mask."],["m32","32-bit wide mask."],["m64","64-bit wide mask."],["m8","8-bit wide mask."],["msize","isize-wide mask."]],"trait":[["Cast","Numeric cast from `Self` to `T`."],["FromBits","Safe lossless bitwise conversion from `T` to `Self`."],["FromCast","Numeric cast from `T` to `Self`."],["IntoBits","Safe lossless bitwise conversion from `Self` to `T`."],["Mask","This trait is implemented by all mask types"],["SimdArray","Trait implemented by arrays that can be SIMD types."],["SimdVector","This trait is implemented by all SIMD vector types."]],"type":[["cptrx2","A vector with 2 `*const T` lanes"],["cptrx4","A vector with 4 `*const T` lanes"],["cptrx8","A vector with 8 `*const T` lanes"],["f32x16","A 512-bit vector with 16 `f32` lanes."],["f32x2","A 64-bit vector with 2 `f32` lanes."],["f32x4","A 128-bit vector with 4 `f32` lanes."],["f32x8","A 256-bit vector with 8 `f32` lanes."],["f64x2","A 128-bit vector with 2 `f64` lanes."],["f64x4","A 256-bit vector with 4 `f64` lanes."],["f64x8","A 512-bit vector with 8 `f64` lanes."],["i128x1","A 128-bit vector with 1 `i128` lane."],["i128x2","A 256-bit vector with 2 `i128` lanes."],["i128x4","A 512-bit vector with 4 `i128` lanes."],["i16x16","A 256-bit vector with 16 `i16` lanes."],["i16x2","A 32-bit vector with 2 `i16` lanes."],["i16x32","A 512-bit vector with 32 `i16` lanes."],["i16x4","A 64-bit vector with 4 `i16` lanes."],["i16x8","A 128-bit vector with 8 `i16` lanes."],["i32x16","A 512-bit vector with 16 `i32` lanes."],["i32x2","A 64-bit vector with 2 `i32` lanes."],["i32x4","A 128-bit vector with 4 `i32` lanes."],["i32x8","A 256-bit vector with 8 `i32` lanes."],["i64x2","A 128-bit vector with 2 `i64` lanes."],["i64x4","A 256-bit vector with 4 `i64` lanes."],["i64x8","A 512-bit vector with 8 `i64` lanes."],["i8x16","A 128-bit vector with 16 `i8` lanes."],["i8x2","A 16-bit vector with 2 `i8` lanes."],["i8x32","A 256-bit vector with 32 `i8` lanes."],["i8x4","A 32-bit vector with 4 `i8` lanes."],["i8x64","A 512-bit vector with 64 `i8` lanes."],["i8x8","A 64-bit vector with 8 `i8` lanes."],["isizex2","A vector with 2 `isize` lanes."],["isizex4","A vector with 4 `isize` lanes."],["isizex8","A vector with 4 `isize` lanes."],["m128x1","A 128-bit vector mask with 1 `m128` lane."],["m128x2","A 256-bit vector mask with 2 `m128` lanes."],["m128x4","A 512-bit vector mask with 4 `m128` lanes."],["m16x16","A 256-bit vector mask with 16 `m16` lanes."],["m16x2","A 32-bit vector mask with 2 `m16` lanes."],["m16x32","A 512-bit vector mask with 32 `m16` lanes."],["m16x4","A 64-bit vector mask with 4 `m16` lanes."],["m16x8","A 128-bit vector mask with 8 `m16` lanes."],["m32x16","A 512-bit vector mask with 16 `m32` lanes."],["m32x2","A 64-bit vector mask with 2 `m32` lanes."],["m32x4","A 128-bit vector mask with 4 `m32` lanes."],["m32x8","A 256-bit vector mask with 8 `m32` lanes."],["m64x2","A 128-bit vector mask with 2 `m64` lanes."],["m64x4","A 256-bit vector mask with 4 `m64` lanes."],["m64x8","A 512-bit vector mask with 8 `m64` lanes."],["m8x16","A 128-bit vector mask with 16 `m8` lanes."],["m8x2","A 16-bit vector mask with 2 `m8` lanes."],["m8x32","A 256-bit vector mask with 32 `m8` lanes."],["m8x4","A 32-bit vector mask with 4 `m8` lanes."],["m8x64","A 512-bit vector mask with 64 `m8` lanes."],["m8x8","A 64-bit vector mask with 8 `m8` lanes."],["mptrx2","A vector with 2 `*mut T` lanes"],["mptrx4","A vector with 4 `*mut T` lanes"],["mptrx8","A vector with 8 `*mut T` lanes"],["msizex2","A vector mask with 2 `msize` lanes."],["msizex4","A vector mask with 4 `msize` lanes."],["msizex8","A vector mask with 8 `msize` lanes."],["u128x1","A 128-bit vector with 1 `u128` lane."],["u128x2","A 256-bit vector with 2 `u128` lanes."],["u128x4","A 512-bit vector with 4 `u128` lanes."],["u16x16","A 256-bit vector with 16 `u16` lanes."],["u16x2","A 32-bit vector with 2 `u16` lanes."],["u16x32","A 512-bit vector with 32 `u16` lanes."],["u16x4","A 64-bit vector with 4 `u16` lanes."],["u16x8","A 128-bit vector with 8 `u16` lanes."],["u32x16","A 512-bit vector with 16 `u32` lanes."],["u32x2","A 64-bit vector with 2 `u32` lanes."],["u32x4","A 128-bit vector with 4 `u32` lanes."],["u32x8","A 256-bit vector with 8 `u32` lanes."],["u64x2","A 128-bit vector with 2 `u64` lanes."],["u64x4","A 256-bit vector with 4 `u64` lanes."],["u64x8","A 512-bit vector with 8 `u64` lanes."],["u8x16","A 128-bit vector with 16 `u8` lanes."],["u8x2","A 16-bit vector with 2 `u8` lanes."],["u8x32","A 256-bit vector with 32 `u8` lanes."],["u8x4","A 32-bit vector with 4 `u8` lanes."],["u8x64","A 512-bit vector with 64 `u8` lanes."],["u8x8","A 64-bit vector with 8 `u8` lanes."],["usizex2","A vector with 2 `usize` lanes."],["usizex4","A vector with 4 `usize` lanes."],["usizex8","A vector with 8 `usize` lanes."]]}); \ No newline at end of file diff --git a/packed_simd/struct.LexicographicallyOrdered.html b/packed_simd/struct.LexicographicallyOrdered.html new file mode 100644 index 000000000..abea6e9e9 --- /dev/null +++ b/packed_simd/struct.LexicographicallyOrdered.html @@ -0,0 +1,833 @@ +packed_simd::LexicographicallyOrdered - Rust

[−][src]Struct packed_simd::LexicographicallyOrdered

#[repr(transparent)]pub struct LexicographicallyOrdered<T>(_);

Wrapper over T implementing a lexicoraphical order via the PartialOrd +and/or Ord traits.

+

Trait Implementations

impl<T: Clone> Clone for LexicographicallyOrdered<T>[src]

impl<T: Copy> Copy for LexicographicallyOrdered<T>[src]

impl<T: Debug> Debug for LexicographicallyOrdered<T>[src]

impl Eq for LexicographicallyOrdered<i8x2>[src]

impl Eq for LexicographicallyOrdered<u8x2>[src]

impl Eq for LexicographicallyOrdered<u8x8>[src]

impl Eq for LexicographicallyOrdered<m8x8>[src]

impl Eq for LexicographicallyOrdered<i16x4>[src]

impl Eq for LexicographicallyOrdered<u16x4>[src]

impl Eq for LexicographicallyOrdered<m16x4>[src]

impl Eq for LexicographicallyOrdered<i32x2>[src]

impl Eq for LexicographicallyOrdered<u32x2>[src]

impl Eq for LexicographicallyOrdered<m32x2>[src]

impl Eq for LexicographicallyOrdered<i8x16>[src]

impl Eq for LexicographicallyOrdered<u8x16>[src]

impl Eq for LexicographicallyOrdered<m8x2>[src]

impl Eq for LexicographicallyOrdered<m8x16>[src]

impl Eq for LexicographicallyOrdered<i16x8>[src]

impl Eq for LexicographicallyOrdered<u16x8>[src]

impl Eq for LexicographicallyOrdered<m16x8>[src]

impl Eq for LexicographicallyOrdered<i32x4>[src]

impl Eq for LexicographicallyOrdered<u32x4>[src]

impl Eq for LexicographicallyOrdered<m32x4>[src]

impl Eq for LexicographicallyOrdered<i64x2>[src]

impl Eq for LexicographicallyOrdered<u64x2>[src]

impl Eq for LexicographicallyOrdered<m64x2>[src]

impl Eq for LexicographicallyOrdered<i8x4>[src]

impl Eq for LexicographicallyOrdered<i128x1>[src]

impl Eq for LexicographicallyOrdered<u128x1>[src]

impl Eq for LexicographicallyOrdered<m128x1>[src]

impl Eq for LexicographicallyOrdered<i8x32>[src]

impl Eq for LexicographicallyOrdered<u8x32>[src]

impl Eq for LexicographicallyOrdered<m8x32>[src]

impl Eq for LexicographicallyOrdered<i16x16>[src]

impl Eq for LexicographicallyOrdered<u16x16>[src]

impl Eq for LexicographicallyOrdered<m16x16>[src]

impl Eq for LexicographicallyOrdered<i32x8>[src]

impl Eq for LexicographicallyOrdered<u8x4>[src]

impl Eq for LexicographicallyOrdered<u32x8>[src]

impl Eq for LexicographicallyOrdered<m32x8>[src]

impl Eq for LexicographicallyOrdered<i64x4>[src]

impl Eq for LexicographicallyOrdered<u64x4>[src]

impl Eq for LexicographicallyOrdered<m64x4>[src]

impl Eq for LexicographicallyOrdered<i128x2>[src]

impl Eq for LexicographicallyOrdered<u128x2>[src]

impl Eq for LexicographicallyOrdered<m128x2>[src]

impl Eq for LexicographicallyOrdered<i8x64>[src]

impl Eq for LexicographicallyOrdered<u8x64>[src]

impl Eq for LexicographicallyOrdered<m8x4>[src]

impl Eq for LexicographicallyOrdered<m8x64>[src]

impl Eq for LexicographicallyOrdered<i16x32>[src]

impl Eq for LexicographicallyOrdered<u16x32>[src]

impl Eq for LexicographicallyOrdered<m16x32>[src]

impl Eq for LexicographicallyOrdered<i32x16>[src]

impl Eq for LexicographicallyOrdered<u32x16>[src]

impl Eq for LexicographicallyOrdered<m32x16>[src]

impl Eq for LexicographicallyOrdered<i64x8>[src]

impl Eq for LexicographicallyOrdered<u64x8>[src]

impl Eq for LexicographicallyOrdered<m64x8>[src]

impl Eq for LexicographicallyOrdered<i16x2>[src]

impl Eq for LexicographicallyOrdered<i128x4>[src]

impl Eq for LexicographicallyOrdered<u128x4>[src]

impl Eq for LexicographicallyOrdered<m128x4>[src]

impl Eq for LexicographicallyOrdered<isizex2>[src]

impl Eq for LexicographicallyOrdered<usizex2>[src]

impl Eq for LexicographicallyOrdered<msizex2>[src]

impl Eq for LexicographicallyOrdered<isizex4>[src]

impl Eq for LexicographicallyOrdered<usizex4>[src]

impl Eq for LexicographicallyOrdered<msizex4>[src]

impl Eq for LexicographicallyOrdered<isizex8>[src]

impl Eq for LexicographicallyOrdered<u16x2>[src]

impl Eq for LexicographicallyOrdered<usizex8>[src]

impl Eq for LexicographicallyOrdered<msizex8>[src]

impl<T> Eq for LexicographicallyOrdered<cptrx2<T>>[src]

impl<T> Eq for LexicographicallyOrdered<mptrx2<T>>[src]

impl<T> Eq for LexicographicallyOrdered<cptrx4<T>>[src]

impl<T> Eq for LexicographicallyOrdered<mptrx4<T>>[src]

impl<T> Eq for LexicographicallyOrdered<cptrx8<T>>[src]

impl<T> Eq for LexicographicallyOrdered<mptrx8<T>>[src]

impl Eq for LexicographicallyOrdered<m16x2>[src]

impl Eq for LexicographicallyOrdered<i8x8>[src]

impl Ord for LexicographicallyOrdered<i8x2>[src]

impl Ord for LexicographicallyOrdered<u8x2>[src]

impl Ord for LexicographicallyOrdered<u8x8>[src]

impl Ord for LexicographicallyOrdered<m8x8>[src]

impl Ord for LexicographicallyOrdered<i16x4>[src]

impl Ord for LexicographicallyOrdered<u16x4>[src]

impl Ord for LexicographicallyOrdered<m16x4>[src]

impl Ord for LexicographicallyOrdered<i32x2>[src]

impl Ord for LexicographicallyOrdered<u32x2>[src]

impl Ord for LexicographicallyOrdered<m32x2>[src]

impl Ord for LexicographicallyOrdered<i8x16>[src]

impl Ord for LexicographicallyOrdered<u8x16>[src]

impl Ord for LexicographicallyOrdered<m8x2>[src]

impl Ord for LexicographicallyOrdered<m8x16>[src]

impl Ord for LexicographicallyOrdered<i16x8>[src]

impl Ord for LexicographicallyOrdered<u16x8>[src]

impl Ord for LexicographicallyOrdered<m16x8>[src]

impl Ord for LexicographicallyOrdered<i32x4>[src]

impl Ord for LexicographicallyOrdered<u32x4>[src]

impl Ord for LexicographicallyOrdered<m32x4>[src]

impl Ord for LexicographicallyOrdered<i64x2>[src]

impl Ord for LexicographicallyOrdered<u64x2>[src]

impl Ord for LexicographicallyOrdered<m64x2>[src]

impl Ord for LexicographicallyOrdered<i8x4>[src]

impl Ord for LexicographicallyOrdered<i128x1>[src]

impl Ord for LexicographicallyOrdered<u128x1>[src]

impl Ord for LexicographicallyOrdered<m128x1>[src]

impl Ord for LexicographicallyOrdered<i8x32>[src]

impl Ord for LexicographicallyOrdered<u8x32>[src]

impl Ord for LexicographicallyOrdered<m8x32>[src]

impl Ord for LexicographicallyOrdered<i16x16>[src]

impl Ord for LexicographicallyOrdered<u16x16>[src]

impl Ord for LexicographicallyOrdered<m16x16>[src]

impl Ord for LexicographicallyOrdered<i32x8>[src]

impl Ord for LexicographicallyOrdered<u8x4>[src]

impl Ord for LexicographicallyOrdered<u32x8>[src]

impl Ord for LexicographicallyOrdered<m32x8>[src]

impl Ord for LexicographicallyOrdered<i64x4>[src]

impl Ord for LexicographicallyOrdered<u64x4>[src]

impl Ord for LexicographicallyOrdered<m64x4>[src]

impl Ord for LexicographicallyOrdered<i128x2>[src]

impl Ord for LexicographicallyOrdered<u128x2>[src]

impl Ord for LexicographicallyOrdered<m128x2>[src]

impl Ord for LexicographicallyOrdered<i8x64>[src]

impl Ord for LexicographicallyOrdered<u8x64>[src]

impl Ord for LexicographicallyOrdered<m8x4>[src]

impl Ord for LexicographicallyOrdered<m8x64>[src]

impl Ord for LexicographicallyOrdered<i16x32>[src]

impl Ord for LexicographicallyOrdered<u16x32>[src]

impl Ord for LexicographicallyOrdered<m16x32>[src]

impl Ord for LexicographicallyOrdered<i32x16>[src]

impl Ord for LexicographicallyOrdered<u32x16>[src]

impl Ord for LexicographicallyOrdered<m32x16>[src]

impl Ord for LexicographicallyOrdered<i64x8>[src]

impl Ord for LexicographicallyOrdered<u64x8>[src]

impl Ord for LexicographicallyOrdered<m64x8>[src]

impl Ord for LexicographicallyOrdered<i16x2>[src]

impl Ord for LexicographicallyOrdered<i128x4>[src]

impl Ord for LexicographicallyOrdered<u128x4>[src]

impl Ord for LexicographicallyOrdered<m128x4>[src]

impl Ord for LexicographicallyOrdered<isizex2>[src]

impl Ord for LexicographicallyOrdered<usizex2>[src]

impl Ord for LexicographicallyOrdered<msizex2>[src]

impl Ord for LexicographicallyOrdered<isizex4>[src]

impl Ord for LexicographicallyOrdered<usizex4>[src]

impl Ord for LexicographicallyOrdered<msizex4>[src]

impl Ord for LexicographicallyOrdered<isizex8>[src]

impl Ord for LexicographicallyOrdered<u16x2>[src]

impl Ord for LexicographicallyOrdered<usizex8>[src]

impl Ord for LexicographicallyOrdered<msizex8>[src]

impl Ord for LexicographicallyOrdered<m16x2>[src]

impl Ord for LexicographicallyOrdered<i8x8>[src]

impl<T> PartialEq<LexicographicallyOrdered<Simd<[*const T; 2]>>> for LexicographicallyOrdered<cptrx2<T>>[src]

impl<T> PartialEq<LexicographicallyOrdered<Simd<[*const T; 4]>>> for LexicographicallyOrdered<cptrx4<T>>[src]

impl<T> PartialEq<LexicographicallyOrdered<Simd<[*const T; 8]>>> for LexicographicallyOrdered<cptrx8<T>>[src]

impl<T> PartialEq<LexicographicallyOrdered<Simd<[*mut T; 2]>>> for LexicographicallyOrdered<mptrx2<T>>[src]

impl<T> PartialEq<LexicographicallyOrdered<Simd<[*mut T; 4]>>> for LexicographicallyOrdered<mptrx4<T>>[src]

impl<T> PartialEq<LexicographicallyOrdered<Simd<[*mut T; 8]>>> for LexicographicallyOrdered<mptrx8<T>>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[f32; 16]>>> for LexicographicallyOrdered<f32x16>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[f32; 2]>>> for LexicographicallyOrdered<f32x2>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[f32; 4]>>> for LexicographicallyOrdered<f32x4>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[f32; 8]>>> for LexicographicallyOrdered<f32x8>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[f64; 2]>>> for LexicographicallyOrdered<f64x2>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[f64; 4]>>> for LexicographicallyOrdered<f64x4>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[f64; 8]>>> for LexicographicallyOrdered<f64x8>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[i128; 1]>>> for LexicographicallyOrdered<i128x1>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[i128; 2]>>> for LexicographicallyOrdered<i128x2>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[i128; 4]>>> for LexicographicallyOrdered<i128x4>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[i16; 16]>>> for LexicographicallyOrdered<i16x16>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[i16; 2]>>> for LexicographicallyOrdered<i16x2>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[i16; 32]>>> for LexicographicallyOrdered<i16x32>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[i16; 4]>>> for LexicographicallyOrdered<i16x4>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[i16; 8]>>> for LexicographicallyOrdered<i16x8>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[i32; 16]>>> for LexicographicallyOrdered<i32x16>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[i32; 2]>>> for LexicographicallyOrdered<i32x2>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[i32; 4]>>> for LexicographicallyOrdered<i32x4>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[i32; 8]>>> for LexicographicallyOrdered<i32x8>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[i64; 2]>>> for LexicographicallyOrdered<i64x2>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[i64; 4]>>> for LexicographicallyOrdered<i64x4>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[i64; 8]>>> for LexicographicallyOrdered<i64x8>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[i8; 16]>>> for LexicographicallyOrdered<i8x16>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[i8; 2]>>> for LexicographicallyOrdered<i8x2>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[i8; 32]>>> for LexicographicallyOrdered<i8x32>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[i8; 4]>>> for LexicographicallyOrdered<i8x4>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[i8; 64]>>> for LexicographicallyOrdered<i8x64>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[i8; 8]>>> for LexicographicallyOrdered<i8x8>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[isize; 2]>>> for LexicographicallyOrdered<isizex2>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[isize; 4]>>> for LexicographicallyOrdered<isizex4>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[isize; 8]>>> for LexicographicallyOrdered<isizex8>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[m128; 1]>>> for LexicographicallyOrdered<m128x1>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[m128; 2]>>> for LexicographicallyOrdered<m128x2>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[m128; 4]>>> for LexicographicallyOrdered<m128x4>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[m16; 16]>>> for LexicographicallyOrdered<m16x16>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[m16; 2]>>> for LexicographicallyOrdered<m16x2>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[m16; 32]>>> for LexicographicallyOrdered<m16x32>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[m16; 4]>>> for LexicographicallyOrdered<m16x4>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[m16; 8]>>> for LexicographicallyOrdered<m16x8>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[m32; 16]>>> for LexicographicallyOrdered<m32x16>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[m32; 2]>>> for LexicographicallyOrdered<m32x2>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[m32; 4]>>> for LexicographicallyOrdered<m32x4>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[m32; 8]>>> for LexicographicallyOrdered<m32x8>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[m64; 2]>>> for LexicographicallyOrdered<m64x2>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[m64; 4]>>> for LexicographicallyOrdered<m64x4>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[m64; 8]>>> for LexicographicallyOrdered<m64x8>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[m8; 16]>>> for LexicographicallyOrdered<m8x16>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[m8; 2]>>> for LexicographicallyOrdered<m8x2>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[m8; 32]>>> for LexicographicallyOrdered<m8x32>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[m8; 4]>>> for LexicographicallyOrdered<m8x4>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[m8; 64]>>> for LexicographicallyOrdered<m8x64>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[m8; 8]>>> for LexicographicallyOrdered<m8x8>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[msize; 2]>>> for LexicographicallyOrdered<msizex2>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[msize; 4]>>> for LexicographicallyOrdered<msizex4>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[msize; 8]>>> for LexicographicallyOrdered<msizex8>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[u128; 1]>>> for LexicographicallyOrdered<u128x1>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[u128; 2]>>> for LexicographicallyOrdered<u128x2>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[u128; 4]>>> for LexicographicallyOrdered<u128x4>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[u16; 16]>>> for LexicographicallyOrdered<u16x16>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[u16; 2]>>> for LexicographicallyOrdered<u16x2>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[u16; 32]>>> for LexicographicallyOrdered<u16x32>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[u16; 4]>>> for LexicographicallyOrdered<u16x4>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[u16; 8]>>> for LexicographicallyOrdered<u16x8>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[u32; 16]>>> for LexicographicallyOrdered<u32x16>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[u32; 2]>>> for LexicographicallyOrdered<u32x2>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[u32; 4]>>> for LexicographicallyOrdered<u32x4>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[u32; 8]>>> for LexicographicallyOrdered<u32x8>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[u64; 2]>>> for LexicographicallyOrdered<u64x2>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[u64; 4]>>> for LexicographicallyOrdered<u64x4>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[u64; 8]>>> for LexicographicallyOrdered<u64x8>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[u8; 16]>>> for LexicographicallyOrdered<u8x16>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[u8; 2]>>> for LexicographicallyOrdered<u8x2>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[u8; 32]>>> for LexicographicallyOrdered<u8x32>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[u8; 4]>>> for LexicographicallyOrdered<u8x4>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[u8; 64]>>> for LexicographicallyOrdered<u8x64>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[u8; 8]>>> for LexicographicallyOrdered<u8x8>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[usize; 2]>>> for LexicographicallyOrdered<usizex2>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[usize; 4]>>> for LexicographicallyOrdered<usizex4>[src]

impl PartialEq<LexicographicallyOrdered<Simd<[usize; 8]>>> for LexicographicallyOrdered<usizex8>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[i128; 1]>>> for LexicographicallyOrdered<i128x1>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[i128; 2]>>> for LexicographicallyOrdered<i128x2>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[i128; 4]>>> for LexicographicallyOrdered<i128x4>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[i16; 16]>>> for LexicographicallyOrdered<i16x16>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[i16; 2]>>> for LexicographicallyOrdered<i16x2>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[i16; 32]>>> for LexicographicallyOrdered<i16x32>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[i16; 4]>>> for LexicographicallyOrdered<i16x4>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[i16; 8]>>> for LexicographicallyOrdered<i16x8>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[i32; 16]>>> for LexicographicallyOrdered<i32x16>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[i32; 2]>>> for LexicographicallyOrdered<i32x2>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[i32; 4]>>> for LexicographicallyOrdered<i32x4>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[i32; 8]>>> for LexicographicallyOrdered<i32x8>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[i64; 2]>>> for LexicographicallyOrdered<i64x2>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[i64; 4]>>> for LexicographicallyOrdered<i64x4>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[i64; 8]>>> for LexicographicallyOrdered<i64x8>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[i8; 16]>>> for LexicographicallyOrdered<i8x16>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[i8; 2]>>> for LexicographicallyOrdered<i8x2>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[i8; 32]>>> for LexicographicallyOrdered<i8x32>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[i8; 4]>>> for LexicographicallyOrdered<i8x4>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[i8; 64]>>> for LexicographicallyOrdered<i8x64>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[i8; 8]>>> for LexicographicallyOrdered<i8x8>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[isize; 2]>>> for LexicographicallyOrdered<isizex2>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[isize; 4]>>> for LexicographicallyOrdered<isizex4>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[isize; 8]>>> for LexicographicallyOrdered<isizex8>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[m128; 1]>>> for LexicographicallyOrdered<m128x1>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[m128; 2]>>> for LexicographicallyOrdered<m128x2>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[m128; 4]>>> for LexicographicallyOrdered<m128x4>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[m16; 16]>>> for LexicographicallyOrdered<m16x16>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[m16; 2]>>> for LexicographicallyOrdered<m16x2>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[m16; 32]>>> for LexicographicallyOrdered<m16x32>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[m16; 4]>>> for LexicographicallyOrdered<m16x4>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[m16; 8]>>> for LexicographicallyOrdered<m16x8>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[m32; 16]>>> for LexicographicallyOrdered<m32x16>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[m32; 2]>>> for LexicographicallyOrdered<m32x2>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[m32; 4]>>> for LexicographicallyOrdered<m32x4>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[m32; 8]>>> for LexicographicallyOrdered<m32x8>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[m64; 2]>>> for LexicographicallyOrdered<m64x2>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[m64; 4]>>> for LexicographicallyOrdered<m64x4>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[m64; 8]>>> for LexicographicallyOrdered<m64x8>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[m8; 16]>>> for LexicographicallyOrdered<m8x16>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[m8; 2]>>> for LexicographicallyOrdered<m8x2>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[m8; 32]>>> for LexicographicallyOrdered<m8x32>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[m8; 4]>>> for LexicographicallyOrdered<m8x4>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[m8; 64]>>> for LexicographicallyOrdered<m8x64>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[m8; 8]>>> for LexicographicallyOrdered<m8x8>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[msize; 2]>>> for LexicographicallyOrdered<msizex2>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[msize; 4]>>> for LexicographicallyOrdered<msizex4>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[msize; 8]>>> for LexicographicallyOrdered<msizex8>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[u128; 1]>>> for LexicographicallyOrdered<u128x1>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[u128; 2]>>> for LexicographicallyOrdered<u128x2>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[u128; 4]>>> for LexicographicallyOrdered<u128x4>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[u16; 16]>>> for LexicographicallyOrdered<u16x16>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[u16; 2]>>> for LexicographicallyOrdered<u16x2>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[u16; 32]>>> for LexicographicallyOrdered<u16x32>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[u16; 4]>>> for LexicographicallyOrdered<u16x4>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[u16; 8]>>> for LexicographicallyOrdered<u16x8>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[u32; 16]>>> for LexicographicallyOrdered<u32x16>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[u32; 2]>>> for LexicographicallyOrdered<u32x2>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[u32; 4]>>> for LexicographicallyOrdered<u32x4>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[u32; 8]>>> for LexicographicallyOrdered<u32x8>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[u64; 2]>>> for LexicographicallyOrdered<u64x2>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[u64; 4]>>> for LexicographicallyOrdered<u64x4>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[u64; 8]>>> for LexicographicallyOrdered<u64x8>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[u8; 16]>>> for LexicographicallyOrdered<u8x16>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[u8; 2]>>> for LexicographicallyOrdered<u8x2>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[u8; 32]>>> for LexicographicallyOrdered<u8x32>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[u8; 4]>>> for LexicographicallyOrdered<u8x4>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[u8; 64]>>> for LexicographicallyOrdered<u8x64>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[u8; 8]>>> for LexicographicallyOrdered<u8x8>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[usize; 2]>>> for LexicographicallyOrdered<usizex2>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[usize; 4]>>> for LexicographicallyOrdered<usizex4>[src]

impl PartialOrd<LexicographicallyOrdered<Simd<[usize; 8]>>> for LexicographicallyOrdered<usizex8>[src]

Auto Trait Implementations

impl<T> Send for LexicographicallyOrdered<T> where
    T: Send, 

impl<T> Sync for LexicographicallyOrdered<T> where
    T: Sync, 

impl<T> Unpin for LexicographicallyOrdered<T> where
    T: Unpin, 

Blanket Implementations

impl<T> Any for T where
    T: 'static + ?Sized, [src]

impl<T> Borrow<T> for T where
    T: ?Sized, [src]

impl<T> BorrowMut<T> for T where
    T: ?Sized, [src]

impl<T> From<T> for T[src]

impl<T, U> Into<U> for T where
    U: From<T>, [src]

impl<T, U> TryFrom<U> for T where
    U: Into<T>, [src]

type Error = Infallible

The type returned in the event of a conversion error.

+

impl<T, U> TryInto<U> for T where
    U: TryFrom<T>, [src]

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.

+
\ No newline at end of file diff --git a/packed_simd/struct.Simd.html b/packed_simd/struct.Simd.html new file mode 100644 index 000000000..03b1b2378 --- /dev/null +++ b/packed_simd/struct.Simd.html @@ -0,0 +1,15270 @@ +packed_simd::Simd - Rust

[−][src]Struct packed_simd::Simd

#[repr(transparent)]pub struct Simd<A: SimdArray>(_);

Packed SIMD vector type.

+

Examples

+
+let v = Simd::<[i32; 4]>::new(0, 1, 2, 3);
+assert_eq!(v.extract(2), 2);
+

Implementations

impl Simd<[i8; 2]>[src]

pub const fn new(x0: i8, x1: i8) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: i8) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> i8[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> i8[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: i8) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: i8) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[i8; 2]>[src]

pub fn rotate_left(self, n: i8x2) -> i8x2[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: i8x2) -> i8x2[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl Simd<[i8; 2]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[i8; 2]>[src]

pub fn wrapping_sum(self) -> i8[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> i8[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl Simd<[i8; 2]>[src]

pub fn max_element(self) -> i8[src]

Largest vector element value.

+

pub fn min_element(self) -> i8[src]

Smallest vector element value.

+

impl Simd<[i8; 2]>[src]

pub fn and(self) -> i8[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> i8[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> i8[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[i8; 2]>[src]

pub fn from_slice_aligned(slice: &[i8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[i8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[i8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[i8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[i8; 2]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [i8])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [i8])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [i8])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [i8])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[i8; 2]>[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl Simd<[i8; 2]>[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl Simd<[i8; 2]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[i8; 2]>[src]

pub fn eq(self, other: Self) -> m8x2[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m8x2[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m8x2[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m8x2[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m8x2[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m8x2[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[i8; 2]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<i8x2>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[i8; 2]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<i8x2>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[i8; 2]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[u8; 2]>[src]

pub const fn new(x0: u8, x1: u8) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: u8) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> u8[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> u8[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: u8) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: u8) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[u8; 2]>[src]

pub fn rotate_left(self, n: u8x2) -> u8x2[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: u8x2) -> u8x2[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl Simd<[u8; 2]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[u8; 2]>[src]

pub fn wrapping_sum(self) -> u8[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> u8[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl Simd<[u8; 2]>[src]

pub fn max_element(self) -> u8[src]

Largest vector element value.

+

pub fn min_element(self) -> u8[src]

Smallest vector element value.

+

impl Simd<[u8; 2]>[src]

pub fn and(self) -> u8[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> u8[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> u8[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[u8; 2]>[src]

pub fn from_slice_aligned(slice: &[u8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[u8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[u8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[u8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[u8; 2]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [u8])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [u8])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [u8])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [u8])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[u8; 2]>[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl Simd<[u8; 2]>[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl Simd<[u8; 2]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[u8; 2]>[src]

pub fn eq(self, other: Self) -> m8x2[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m8x2[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m8x2[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m8x2[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m8x2[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m8x2[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[u8; 2]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<u8x2>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[u8; 2]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<u8x2>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[u8; 2]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[m8; 2]>[src]

pub const fn new(x0: bool, x1: bool) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: bool) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> bool[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> bool[src]

Extracts the value at index.

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

impl Simd<[m8; 2]>[src]

pub fn and(self) -> bool[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> bool[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> bool[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[m8; 2]>[src]

pub fn all(self) -> bool[src]

Are all vector lanes true?

+

pub fn any(self) -> bool[src]

Is any vector lane true?

+

pub fn none(self) -> bool[src]

Are all vector lanes false?

+

impl Simd<[m8; 2]>[src]

pub fn eq(self, other: Self) -> m8x2[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m8x2[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m8x2[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m8x2[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m8x2[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m8x2[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[m8; 2]>[src]

pub fn select<T>(self, a: Simd<T>, b: Simd<T>) -> Simd<T> where
    T: SimdArray<NT = <[m8; 2] as SimdArray>::NT>, [src]

Selects elements of a and b using mask.

+

The lanes of the result for which the mask is true contain +the values of a. The remaining lanes contain the values of +b.

+

impl Simd<[m8; 2]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<m8x2>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[m8; 2]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<m8x2>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[m8; 2]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[m8; 2]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[i8; 4]>[src]

pub const fn new(x0: i8, x1: i8, x2: i8, x3: i8) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: i8) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> i8[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> i8[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: i8) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: i8) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[i8; 4]>[src]

pub fn rotate_left(self, n: i8x4) -> i8x4[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: i8x4) -> i8x4[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl Simd<[i8; 4]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[i8; 4]>[src]

pub fn wrapping_sum(self) -> i8[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> i8[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl Simd<[i8; 4]>[src]

pub fn max_element(self) -> i8[src]

Largest vector element value.

+

pub fn min_element(self) -> i8[src]

Smallest vector element value.

+

impl Simd<[i8; 4]>[src]

pub fn and(self) -> i8[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> i8[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> i8[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[i8; 4]>[src]

pub fn from_slice_aligned(slice: &[i8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[i8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[i8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[i8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[i8; 4]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [i8])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [i8])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [i8])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [i8])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[i8; 4]>[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl Simd<[i8; 4]>[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl Simd<[i8; 4]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[i8; 4]>[src]

pub fn eq(self, other: Self) -> m8x4[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m8x4[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m8x4[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m8x4[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m8x4[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m8x4[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[i8; 4]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<i8x4>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[i8; 4]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<i8x4>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[i8; 4]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[u8; 4]>[src]

pub const fn new(x0: u8, x1: u8, x2: u8, x3: u8) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: u8) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> u8[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> u8[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: u8) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: u8) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[u8; 4]>[src]

pub fn rotate_left(self, n: u8x4) -> u8x4[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: u8x4) -> u8x4[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl Simd<[u8; 4]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[u8; 4]>[src]

pub fn wrapping_sum(self) -> u8[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> u8[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl Simd<[u8; 4]>[src]

pub fn max_element(self) -> u8[src]

Largest vector element value.

+

pub fn min_element(self) -> u8[src]

Smallest vector element value.

+

impl Simd<[u8; 4]>[src]

pub fn and(self) -> u8[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> u8[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> u8[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[u8; 4]>[src]

pub fn from_slice_aligned(slice: &[u8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[u8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[u8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[u8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[u8; 4]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [u8])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [u8])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [u8])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [u8])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[u8; 4]>[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl Simd<[u8; 4]>[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl Simd<[u8; 4]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[u8; 4]>[src]

pub fn eq(self, other: Self) -> m8x4[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m8x4[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m8x4[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m8x4[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m8x4[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m8x4[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[u8; 4]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<u8x4>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[u8; 4]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<u8x4>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[u8; 4]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[m8; 4]>[src]

pub const fn new(x0: bool, x1: bool, x2: bool, x3: bool) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: bool) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> bool[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> bool[src]

Extracts the value at index.

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

impl Simd<[m8; 4]>[src]

pub fn and(self) -> bool[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> bool[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> bool[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[m8; 4]>[src]

pub fn all(self) -> bool[src]

Are all vector lanes true?

+

pub fn any(self) -> bool[src]

Is any vector lane true?

+

pub fn none(self) -> bool[src]

Are all vector lanes false?

+

impl Simd<[m8; 4]>[src]

pub fn eq(self, other: Self) -> m8x4[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m8x4[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m8x4[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m8x4[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m8x4[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m8x4[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[m8; 4]>[src]

pub fn select<T>(self, a: Simd<T>, b: Simd<T>) -> Simd<T> where
    T: SimdArray<NT = <[m8; 4] as SimdArray>::NT>, [src]

Selects elements of a and b using mask.

+

The lanes of the result for which the mask is true contain +the values of a. The remaining lanes contain the values of +b.

+

impl Simd<[m8; 4]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<m8x4>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[m8; 4]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<m8x4>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[m8; 4]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[m8; 4]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[i16; 2]>[src]

pub const fn new(x0: i16, x1: i16) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: i16) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> i16[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> i16[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: i16) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: i16) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[i16; 2]>[src]

pub fn rotate_left(self, n: i16x2) -> i16x2[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: i16x2) -> i16x2[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl Simd<[i16; 2]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[i16; 2]>[src]

pub fn wrapping_sum(self) -> i16[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> i16[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl Simd<[i16; 2]>[src]

pub fn max_element(self) -> i16[src]

Largest vector element value.

+

pub fn min_element(self) -> i16[src]

Smallest vector element value.

+

impl Simd<[i16; 2]>[src]

pub fn and(self) -> i16[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> i16[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> i16[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[i16; 2]>[src]

pub fn from_slice_aligned(slice: &[i16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[i16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[i16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[i16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[i16; 2]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [i16])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [i16])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [i16])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [i16])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[i16; 2]>[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl Simd<[i16; 2]>[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl Simd<[i16; 2]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[i16; 2]>[src]

pub fn eq(self, other: Self) -> m16x2[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m16x2[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m16x2[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m16x2[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m16x2[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m16x2[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[i16; 2]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<i16x2>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[i16; 2]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<i16x2>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[i16; 2]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[u16; 2]>[src]

pub const fn new(x0: u16, x1: u16) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: u16) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> u16[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> u16[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: u16) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: u16) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[u16; 2]>[src]

pub fn rotate_left(self, n: u16x2) -> u16x2[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: u16x2) -> u16x2[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl Simd<[u16; 2]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[u16; 2]>[src]

pub fn wrapping_sum(self) -> u16[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> u16[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl Simd<[u16; 2]>[src]

pub fn max_element(self) -> u16[src]

Largest vector element value.

+

pub fn min_element(self) -> u16[src]

Smallest vector element value.

+

impl Simd<[u16; 2]>[src]

pub fn and(self) -> u16[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> u16[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> u16[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[u16; 2]>[src]

pub fn from_slice_aligned(slice: &[u16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[u16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[u16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[u16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[u16; 2]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [u16])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [u16])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [u16])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [u16])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[u16; 2]>[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl Simd<[u16; 2]>[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl Simd<[u16; 2]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[u16; 2]>[src]

pub fn eq(self, other: Self) -> m16x2[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m16x2[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m16x2[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m16x2[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m16x2[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m16x2[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[u16; 2]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<u16x2>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[u16; 2]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<u16x2>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[u16; 2]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[m16; 2]>[src]

pub const fn new(x0: bool, x1: bool) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: bool) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> bool[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> bool[src]

Extracts the value at index.

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

impl Simd<[m16; 2]>[src]

pub fn and(self) -> bool[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> bool[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> bool[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[m16; 2]>[src]

pub fn all(self) -> bool[src]

Are all vector lanes true?

+

pub fn any(self) -> bool[src]

Is any vector lane true?

+

pub fn none(self) -> bool[src]

Are all vector lanes false?

+

impl Simd<[m16; 2]>[src]

pub fn eq(self, other: Self) -> m16x2[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m16x2[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m16x2[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m16x2[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m16x2[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m16x2[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[m16; 2]>[src]

pub fn select<T>(self, a: Simd<T>, b: Simd<T>) -> Simd<T> where
    T: SimdArray<NT = <[m16; 2] as SimdArray>::NT>, [src]

Selects elements of a and b using mask.

+

The lanes of the result for which the mask is true contain +the values of a. The remaining lanes contain the values of +b.

+

impl Simd<[m16; 2]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<m16x2>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[m16; 2]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<m16x2>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[m16; 2]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[m16; 2]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[i8; 8]>[src]

pub const fn new(
    x0: i8,
    x1: i8,
    x2: i8,
    x3: i8,
    x4: i8,
    x5: i8,
    x6: i8,
    x7: i8
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: i8) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> i8[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> i8[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: i8) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: i8) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[i8; 8]>[src]

pub fn rotate_left(self, n: i8x8) -> i8x8[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: i8x8) -> i8x8[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl Simd<[i8; 8]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[i8; 8]>[src]

pub fn wrapping_sum(self) -> i8[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> i8[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl Simd<[i8; 8]>[src]

pub fn max_element(self) -> i8[src]

Largest vector element value.

+

pub fn min_element(self) -> i8[src]

Smallest vector element value.

+

impl Simd<[i8; 8]>[src]

pub fn and(self) -> i8[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> i8[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> i8[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[i8; 8]>[src]

pub fn from_slice_aligned(slice: &[i8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[i8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[i8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[i8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[i8; 8]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [i8])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [i8])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [i8])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [i8])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[i8; 8]>[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl Simd<[i8; 8]>[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl Simd<[i8; 8]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[i8; 8]>[src]

pub fn eq(self, other: Self) -> m8x8[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m8x8[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m8x8[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m8x8[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m8x8[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m8x8[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[i8; 8]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<i8x8>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[i8; 8]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<i8x8>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[i8; 8]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[u8; 8]>[src]

pub const fn new(
    x0: u8,
    x1: u8,
    x2: u8,
    x3: u8,
    x4: u8,
    x5: u8,
    x6: u8,
    x7: u8
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: u8) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> u8[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> u8[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: u8) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: u8) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[u8; 8]>[src]

pub fn rotate_left(self, n: u8x8) -> u8x8[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: u8x8) -> u8x8[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl Simd<[u8; 8]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[u8; 8]>[src]

pub fn wrapping_sum(self) -> u8[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> u8[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl Simd<[u8; 8]>[src]

pub fn max_element(self) -> u8[src]

Largest vector element value.

+

pub fn min_element(self) -> u8[src]

Smallest vector element value.

+

impl Simd<[u8; 8]>[src]

pub fn and(self) -> u8[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> u8[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> u8[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[u8; 8]>[src]

pub fn from_slice_aligned(slice: &[u8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[u8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[u8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[u8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[u8; 8]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [u8])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [u8])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [u8])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [u8])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[u8; 8]>[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl Simd<[u8; 8]>[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl Simd<[u8; 8]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[u8; 8]>[src]

pub fn eq(self, other: Self) -> m8x8[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m8x8[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m8x8[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m8x8[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m8x8[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m8x8[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[u8; 8]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<u8x8>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[u8; 8]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<u8x8>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[u8; 8]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[m8; 8]>[src]

pub const fn new(
    x0: bool,
    x1: bool,
    x2: bool,
    x3: bool,
    x4: bool,
    x5: bool,
    x6: bool,
    x7: bool
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: bool) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> bool[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> bool[src]

Extracts the value at index.

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

impl Simd<[m8; 8]>[src]

pub fn and(self) -> bool[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> bool[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> bool[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[m8; 8]>[src]

pub fn all(self) -> bool[src]

Are all vector lanes true?

+

pub fn any(self) -> bool[src]

Is any vector lane true?

+

pub fn none(self) -> bool[src]

Are all vector lanes false?

+

impl Simd<[m8; 8]>[src]

pub fn eq(self, other: Self) -> m8x8[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m8x8[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m8x8[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m8x8[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m8x8[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m8x8[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[m8; 8]>[src]

pub fn select<T>(self, a: Simd<T>, b: Simd<T>) -> Simd<T> where
    T: SimdArray<NT = <[m8; 8] as SimdArray>::NT>, [src]

Selects elements of a and b using mask.

+

The lanes of the result for which the mask is true contain +the values of a. The remaining lanes contain the values of +b.

+

impl Simd<[m8; 8]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<m8x8>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[m8; 8]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<m8x8>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[m8; 8]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[m8; 8]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[i16; 4]>[src]

pub const fn new(x0: i16, x1: i16, x2: i16, x3: i16) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: i16) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> i16[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> i16[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: i16) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: i16) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[i16; 4]>[src]

pub fn rotate_left(self, n: i16x4) -> i16x4[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: i16x4) -> i16x4[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl Simd<[i16; 4]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[i16; 4]>[src]

pub fn wrapping_sum(self) -> i16[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> i16[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl Simd<[i16; 4]>[src]

pub fn max_element(self) -> i16[src]

Largest vector element value.

+

pub fn min_element(self) -> i16[src]

Smallest vector element value.

+

impl Simd<[i16; 4]>[src]

pub fn and(self) -> i16[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> i16[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> i16[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[i16; 4]>[src]

pub fn from_slice_aligned(slice: &[i16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[i16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[i16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[i16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[i16; 4]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [i16])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [i16])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [i16])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [i16])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[i16; 4]>[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl Simd<[i16; 4]>[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl Simd<[i16; 4]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[i16; 4]>[src]

pub fn eq(self, other: Self) -> m16x4[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m16x4[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m16x4[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m16x4[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m16x4[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m16x4[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[i16; 4]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<i16x4>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[i16; 4]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<i16x4>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[i16; 4]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[u16; 4]>[src]

pub const fn new(x0: u16, x1: u16, x2: u16, x3: u16) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: u16) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> u16[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> u16[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: u16) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: u16) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[u16; 4]>[src]

pub fn rotate_left(self, n: u16x4) -> u16x4[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: u16x4) -> u16x4[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl Simd<[u16; 4]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[u16; 4]>[src]

pub fn wrapping_sum(self) -> u16[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> u16[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl Simd<[u16; 4]>[src]

pub fn max_element(self) -> u16[src]

Largest vector element value.

+

pub fn min_element(self) -> u16[src]

Smallest vector element value.

+

impl Simd<[u16; 4]>[src]

pub fn and(self) -> u16[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> u16[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> u16[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[u16; 4]>[src]

pub fn from_slice_aligned(slice: &[u16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[u16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[u16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[u16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[u16; 4]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [u16])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [u16])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [u16])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [u16])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[u16; 4]>[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl Simd<[u16; 4]>[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl Simd<[u16; 4]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[u16; 4]>[src]

pub fn eq(self, other: Self) -> m16x4[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m16x4[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m16x4[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m16x4[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m16x4[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m16x4[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[u16; 4]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<u16x4>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[u16; 4]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<u16x4>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[u16; 4]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[m16; 4]>[src]

pub const fn new(x0: bool, x1: bool, x2: bool, x3: bool) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: bool) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> bool[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> bool[src]

Extracts the value at index.

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

impl Simd<[m16; 4]>[src]

pub fn and(self) -> bool[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> bool[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> bool[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[m16; 4]>[src]

pub fn all(self) -> bool[src]

Are all vector lanes true?

+

pub fn any(self) -> bool[src]

Is any vector lane true?

+

pub fn none(self) -> bool[src]

Are all vector lanes false?

+

impl Simd<[m16; 4]>[src]

pub fn eq(self, other: Self) -> m16x4[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m16x4[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m16x4[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m16x4[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m16x4[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m16x4[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[m16; 4]>[src]

pub fn select<T>(self, a: Simd<T>, b: Simd<T>) -> Simd<T> where
    T: SimdArray<NT = <[m16; 4] as SimdArray>::NT>, [src]

Selects elements of a and b using mask.

+

The lanes of the result for which the mask is true contain +the values of a. The remaining lanes contain the values of +b.

+

impl Simd<[m16; 4]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<m16x4>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[m16; 4]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<m16x4>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[m16; 4]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[m16; 4]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[i32; 2]>[src]

pub const fn new(x0: i32, x1: i32) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: i32) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> i32[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> i32[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: i32) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: i32) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[i32; 2]>[src]

pub fn rotate_left(self, n: i32x2) -> i32x2[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: i32x2) -> i32x2[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl Simd<[i32; 2]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[i32; 2]>[src]

pub fn wrapping_sum(self) -> i32[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> i32[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl Simd<[i32; 2]>[src]

pub fn max_element(self) -> i32[src]

Largest vector element value.

+

pub fn min_element(self) -> i32[src]

Smallest vector element value.

+

impl Simd<[i32; 2]>[src]

pub fn and(self) -> i32[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> i32[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> i32[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[i32; 2]>[src]

pub fn from_slice_aligned(slice: &[i32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[i32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[i32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[i32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[i32; 2]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [i32])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [i32])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [i32])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [i32])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[i32; 2]>[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl Simd<[i32; 2]>[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl Simd<[i32; 2]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[i32; 2]>[src]

pub fn eq(self, other: Self) -> m32x2[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m32x2[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m32x2[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m32x2[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m32x2[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m32x2[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[i32; 2]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<i32x2>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[i32; 2]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<i32x2>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[i32; 2]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[u32; 2]>[src]

pub const fn new(x0: u32, x1: u32) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: u32) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> u32[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> u32[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: u32) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: u32) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[u32; 2]>[src]

pub fn rotate_left(self, n: u32x2) -> u32x2[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: u32x2) -> u32x2[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl Simd<[u32; 2]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[u32; 2]>[src]

pub fn wrapping_sum(self) -> u32[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> u32[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl Simd<[u32; 2]>[src]

pub fn max_element(self) -> u32[src]

Largest vector element value.

+

pub fn min_element(self) -> u32[src]

Smallest vector element value.

+

impl Simd<[u32; 2]>[src]

pub fn and(self) -> u32[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> u32[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> u32[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[u32; 2]>[src]

pub fn from_slice_aligned(slice: &[u32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[u32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[u32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[u32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[u32; 2]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [u32])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [u32])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [u32])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [u32])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[u32; 2]>[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl Simd<[u32; 2]>[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl Simd<[u32; 2]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[u32; 2]>[src]

pub fn eq(self, other: Self) -> m32x2[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m32x2[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m32x2[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m32x2[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m32x2[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m32x2[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[u32; 2]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<u32x2>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[u32; 2]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<u32x2>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[u32; 2]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[m32; 2]>[src]

pub const fn new(x0: bool, x1: bool) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: bool) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> bool[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> bool[src]

Extracts the value at index.

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

impl Simd<[m32; 2]>[src]

pub fn and(self) -> bool[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> bool[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> bool[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[m32; 2]>[src]

pub fn all(self) -> bool[src]

Are all vector lanes true?

+

pub fn any(self) -> bool[src]

Is any vector lane true?

+

pub fn none(self) -> bool[src]

Are all vector lanes false?

+

impl Simd<[m32; 2]>[src]

pub fn eq(self, other: Self) -> m32x2[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m32x2[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m32x2[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m32x2[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m32x2[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m32x2[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[m32; 2]>[src]

pub fn select<T>(self, a: Simd<T>, b: Simd<T>) -> Simd<T> where
    T: SimdArray<NT = <[m32; 2] as SimdArray>::NT>, [src]

Selects elements of a and b using mask.

+

The lanes of the result for which the mask is true contain +the values of a. The remaining lanes contain the values of +b.

+

impl Simd<[m32; 2]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<m32x2>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[m32; 2]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<m32x2>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[m32; 2]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[m32; 2]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[f32; 2]>[src]

pub const fn new(x0: f32, x1: f32) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: f32) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> f32[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> f32[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: f32) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: f32) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[f32; 2]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[f32; 2]>[src]

pub fn sum(self) -> f32[src]

Horizontal sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If one of the vector element is NaN the reduction returns +NaN. The resulting NaN is not required to be equal to any +of the NaNs in the vector.

+

pub fn product(self) -> f32[src]

Horizontal product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If one of the vector element is NaN the reduction returns +NaN. The resulting NaN is not required to be equal to any +of the NaNs in the vector.

+

impl Simd<[f32; 2]>[src]

pub fn max_element(self) -> f32[src]

Largest vector element value.

+

pub fn min_element(self) -> f32[src]

Smallest vector element value.

+

impl Simd<[f32; 2]>[src]

pub fn from_slice_aligned(slice: &[f32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[f32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[f32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[f32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[f32; 2]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [f32])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [f32])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [f32])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [f32])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[f32; 2]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[f32; 2]>[src]

pub const EPSILON: f32x2[src]

Machine epsilon value.

+

pub const MIN: f32x2[src]

Smallest finite value.

+

pub const MIN_POSITIVE: f32x2[src]

Smallest positive normal value.

+

pub const MAX: f32x2[src]

Largest finite value.

+

pub const NAN: f32x2[src]

Not a Number (NaN).

+

pub const INFINITY: f32x2[src]

Infinity (∞).

+

pub const NEG_INFINITY: f32x2[src]

Negative infinity (-∞).

+

pub const PI: f32x2[src]

Archimedes' constant (π)

+

pub const FRAC_PI_2: f32x2[src]

π/2

+

pub const FRAC_PI_3: f32x2[src]

π/3

+

pub const FRAC_PI_4: f32x2[src]

π/4

+

pub const FRAC_PI_6: f32x2[src]

π/6

+

pub const FRAC_PI_8: f32x2[src]

π/8

+

pub const FRAC_1_PI: f32x2[src]

1/π

+

pub const FRAC_2_PI: f32x2[src]

2/π

+

pub const FRAC_2_SQRT_PI: f32x2[src]

2/sqrt(π)

+

pub const SQRT_2: f32x2[src]

sqrt(2)

+

pub const FRAC_1_SQRT_2: f32x2[src]

1/sqrt(2)

+

pub const E: f32x2[src]

Euler's number (e)

+

pub const LOG2_E: f32x2[src]

log2(e)

+

pub const LOG10_E: f32x2[src]

log10(e)

+

pub const LN_2: f32x2[src]

ln(2)

+

pub const LN_10: f32x2[src]

ln(10)

+

impl Simd<[f32; 2]>[src]

pub fn is_nan(self) -> m32x2[src]

pub fn is_infinite(self) -> m32x2[src]

pub fn is_finite(self) -> m32x2[src]

impl Simd<[f32; 2]>[src]

pub fn abs(self) -> Self[src]

Absolute value.

+

impl Simd<[f32; 2]>[src]

pub fn cos(self) -> Self[src]

Cosine.

+

pub fn cos_pi(self) -> Self[src]

Cosine of self * PI.

+

impl Simd<[f32; 2]>[src]

pub fn exp(self) -> Self[src]

Returns the exponential function of self: e^(self).

+

impl Simd<[f32; 2]>[src]

pub fn ln(self) -> Self[src]

Returns the natural logarithm of self.

+

impl Simd<[f32; 2]>[src]

pub fn mul_add(self, y: Self, z: Self) -> Self[src]

Fused multiply add: self * y + z

+

impl Simd<[f32; 2]>[src]

pub fn mul_adde(self, y: Self, z: Self) -> Self[src]

Fused multiply add estimate: ~= self * y + z

+

While fused multiply-add (fma) has infinite precision, +mul_adde has at worst the same precision of a multiply followed by an add. +This might be more efficient on architectures that do not have an fma instruction.

+

impl Simd<[f32; 2]>[src]

pub fn powf(self, x: Self) -> Self[src]

Raises self number to the floating point power of x.

+

impl Simd<[f32; 2]>[src]

pub fn recpre(self) -> Self[src]

Reciprocal estimate: ~= 1. / self.

+

FIXME: The precision of the estimate is currently unspecified.

+

impl Simd<[f32; 2]>[src]

pub fn rsqrte(self) -> Self[src]

Reciprocal square-root estimate: ~= 1. / self.sqrt().

+

FIXME: The precision of the estimate is currently unspecified.

+

impl Simd<[f32; 2]>[src]

pub fn sin(self) -> Self[src]

Sine.

+

pub fn sin_pi(self) -> Self[src]

Sine of self * PI.

+

pub fn sin_cos_pi(self) -> (Self, Self)[src]

Sine and cosine of self * PI.

+

impl Simd<[f32; 2]>[src]

pub fn sqrt(self) -> Self[src]

impl Simd<[f32; 2]>[src]

pub fn sqrte(self) -> Self[src]

Square-root estimate.

+

FIXME: The precision of the estimate is currently unspecified.

+

impl Simd<[f32; 2]>[src]

pub fn tanh(self) -> Self[src]

Tanh.

+

impl Simd<[f32; 2]>[src]

pub fn eq(self, other: Self) -> m32x2[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m32x2[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m32x2[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m32x2[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m32x2[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m32x2[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[i8; 16]>[src]

pub const fn new(
    x0: i8,
    x1: i8,
    x2: i8,
    x3: i8,
    x4: i8,
    x5: i8,
    x6: i8,
    x7: i8,
    x8: i8,
    x9: i8,
    x10: i8,
    x11: i8,
    x12: i8,
    x13: i8,
    x14: i8,
    x15: i8
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: i8) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> i8[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> i8[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: i8) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: i8) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[i8; 16]>[src]

pub fn rotate_left(self, n: i8x16) -> i8x16[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: i8x16) -> i8x16[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl Simd<[i8; 16]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[i8; 16]>[src]

pub fn wrapping_sum(self) -> i8[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> i8[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl Simd<[i8; 16]>[src]

pub fn max_element(self) -> i8[src]

Largest vector element value.

+

pub fn min_element(self) -> i8[src]

Smallest vector element value.

+

impl Simd<[i8; 16]>[src]

pub fn and(self) -> i8[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> i8[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> i8[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[i8; 16]>[src]

pub fn from_slice_aligned(slice: &[i8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[i8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[i8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[i8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[i8; 16]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [i8])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [i8])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [i8])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [i8])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[i8; 16]>[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl Simd<[i8; 16]>[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl Simd<[i8; 16]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[i8; 16]>[src]

pub fn eq(self, other: Self) -> m8x16[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m8x16[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m8x16[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m8x16[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m8x16[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m8x16[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[i8; 16]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<i8x16>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[i8; 16]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<i8x16>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[i8; 16]>[src]

pub fn bitmask(self) -> u16[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[u8; 16]>[src]

pub const fn new(
    x0: u8,
    x1: u8,
    x2: u8,
    x3: u8,
    x4: u8,
    x5: u8,
    x6: u8,
    x7: u8,
    x8: u8,
    x9: u8,
    x10: u8,
    x11: u8,
    x12: u8,
    x13: u8,
    x14: u8,
    x15: u8
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: u8) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> u8[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> u8[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: u8) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: u8) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[u8; 16]>[src]

pub fn rotate_left(self, n: u8x16) -> u8x16[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: u8x16) -> u8x16[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl Simd<[u8; 16]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[u8; 16]>[src]

pub fn wrapping_sum(self) -> u8[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> u8[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl Simd<[u8; 16]>[src]

pub fn max_element(self) -> u8[src]

Largest vector element value.

+

pub fn min_element(self) -> u8[src]

Smallest vector element value.

+

impl Simd<[u8; 16]>[src]

pub fn and(self) -> u8[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> u8[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> u8[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[u8; 16]>[src]

pub fn from_slice_aligned(slice: &[u8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[u8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[u8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[u8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[u8; 16]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [u8])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [u8])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [u8])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [u8])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[u8; 16]>[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl Simd<[u8; 16]>[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl Simd<[u8; 16]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[u8; 16]>[src]

pub fn eq(self, other: Self) -> m8x16[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m8x16[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m8x16[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m8x16[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m8x16[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m8x16[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[u8; 16]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<u8x16>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[u8; 16]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<u8x16>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[u8; 16]>[src]

pub fn bitmask(self) -> u16[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[m8; 16]>[src]

pub const fn new(
    x0: bool,
    x1: bool,
    x2: bool,
    x3: bool,
    x4: bool,
    x5: bool,
    x6: bool,
    x7: bool,
    x8: bool,
    x9: bool,
    x10: bool,
    x11: bool,
    x12: bool,
    x13: bool,
    x14: bool,
    x15: bool
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: bool) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> bool[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> bool[src]

Extracts the value at index.

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

impl Simd<[m8; 16]>[src]

pub fn and(self) -> bool[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> bool[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> bool[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[m8; 16]>[src]

pub fn all(self) -> bool[src]

Are all vector lanes true?

+

pub fn any(self) -> bool[src]

Is any vector lane true?

+

pub fn none(self) -> bool[src]

Are all vector lanes false?

+

impl Simd<[m8; 16]>[src]

pub fn eq(self, other: Self) -> m8x16[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m8x16[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m8x16[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m8x16[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m8x16[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m8x16[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[m8; 16]>[src]

pub fn select<T>(self, a: Simd<T>, b: Simd<T>) -> Simd<T> where
    T: SimdArray<NT = <[m8; 16] as SimdArray>::NT>, [src]

Selects elements of a and b using mask.

+

The lanes of the result for which the mask is true contain +the values of a. The remaining lanes contain the values of +b.

+

impl Simd<[m8; 16]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<m8x16>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[m8; 16]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<m8x16>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[m8; 16]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[m8; 16]>[src]

pub fn bitmask(self) -> u16[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[i16; 8]>[src]

pub const fn new(
    x0: i16,
    x1: i16,
    x2: i16,
    x3: i16,
    x4: i16,
    x5: i16,
    x6: i16,
    x7: i16
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: i16) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> i16[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> i16[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: i16) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: i16) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[i16; 8]>[src]

pub fn rotate_left(self, n: i16x8) -> i16x8[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: i16x8) -> i16x8[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl Simd<[i16; 8]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[i16; 8]>[src]

pub fn wrapping_sum(self) -> i16[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> i16[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl Simd<[i16; 8]>[src]

pub fn max_element(self) -> i16[src]

Largest vector element value.

+

pub fn min_element(self) -> i16[src]

Smallest vector element value.

+

impl Simd<[i16; 8]>[src]

pub fn and(self) -> i16[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> i16[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> i16[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[i16; 8]>[src]

pub fn from_slice_aligned(slice: &[i16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[i16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[i16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[i16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[i16; 8]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [i16])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [i16])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [i16])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [i16])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[i16; 8]>[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl Simd<[i16; 8]>[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl Simd<[i16; 8]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[i16; 8]>[src]

pub fn eq(self, other: Self) -> m16x8[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m16x8[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m16x8[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m16x8[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m16x8[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m16x8[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[i16; 8]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<i16x8>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[i16; 8]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<i16x8>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[i16; 8]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[u16; 8]>[src]

pub const fn new(
    x0: u16,
    x1: u16,
    x2: u16,
    x3: u16,
    x4: u16,
    x5: u16,
    x6: u16,
    x7: u16
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: u16) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> u16[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> u16[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: u16) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: u16) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[u16; 8]>[src]

pub fn rotate_left(self, n: u16x8) -> u16x8[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: u16x8) -> u16x8[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl Simd<[u16; 8]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[u16; 8]>[src]

pub fn wrapping_sum(self) -> u16[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> u16[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl Simd<[u16; 8]>[src]

pub fn max_element(self) -> u16[src]

Largest vector element value.

+

pub fn min_element(self) -> u16[src]

Smallest vector element value.

+

impl Simd<[u16; 8]>[src]

pub fn and(self) -> u16[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> u16[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> u16[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[u16; 8]>[src]

pub fn from_slice_aligned(slice: &[u16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[u16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[u16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[u16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[u16; 8]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [u16])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [u16])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [u16])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [u16])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[u16; 8]>[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl Simd<[u16; 8]>[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl Simd<[u16; 8]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[u16; 8]>[src]

pub fn eq(self, other: Self) -> m16x8[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m16x8[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m16x8[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m16x8[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m16x8[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m16x8[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[u16; 8]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<u16x8>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[u16; 8]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<u16x8>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[u16; 8]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[m16; 8]>[src]

pub const fn new(
    x0: bool,
    x1: bool,
    x2: bool,
    x3: bool,
    x4: bool,
    x5: bool,
    x6: bool,
    x7: bool
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: bool) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> bool[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> bool[src]

Extracts the value at index.

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

impl Simd<[m16; 8]>[src]

pub fn and(self) -> bool[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> bool[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> bool[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[m16; 8]>[src]

pub fn all(self) -> bool[src]

Are all vector lanes true?

+

pub fn any(self) -> bool[src]

Is any vector lane true?

+

pub fn none(self) -> bool[src]

Are all vector lanes false?

+

impl Simd<[m16; 8]>[src]

pub fn eq(self, other: Self) -> m16x8[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m16x8[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m16x8[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m16x8[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m16x8[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m16x8[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[m16; 8]>[src]

pub fn select<T>(self, a: Simd<T>, b: Simd<T>) -> Simd<T> where
    T: SimdArray<NT = <[m16; 8] as SimdArray>::NT>, [src]

Selects elements of a and b using mask.

+

The lanes of the result for which the mask is true contain +the values of a. The remaining lanes contain the values of +b.

+

impl Simd<[m16; 8]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<m16x8>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[m16; 8]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<m16x8>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[m16; 8]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[m16; 8]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[i32; 4]>[src]

pub const fn new(x0: i32, x1: i32, x2: i32, x3: i32) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: i32) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> i32[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> i32[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: i32) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: i32) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[i32; 4]>[src]

pub fn rotate_left(self, n: i32x4) -> i32x4[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: i32x4) -> i32x4[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl Simd<[i32; 4]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[i32; 4]>[src]

pub fn wrapping_sum(self) -> i32[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> i32[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl Simd<[i32; 4]>[src]

pub fn max_element(self) -> i32[src]

Largest vector element value.

+

pub fn min_element(self) -> i32[src]

Smallest vector element value.

+

impl Simd<[i32; 4]>[src]

pub fn and(self) -> i32[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> i32[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> i32[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[i32; 4]>[src]

pub fn from_slice_aligned(slice: &[i32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[i32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[i32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[i32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[i32; 4]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [i32])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [i32])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [i32])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [i32])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[i32; 4]>[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl Simd<[i32; 4]>[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl Simd<[i32; 4]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[i32; 4]>[src]

pub fn eq(self, other: Self) -> m32x4[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m32x4[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m32x4[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m32x4[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m32x4[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m32x4[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[i32; 4]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<i32x4>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[i32; 4]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<i32x4>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[i32; 4]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[u32; 4]>[src]

pub const fn new(x0: u32, x1: u32, x2: u32, x3: u32) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: u32) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> u32[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> u32[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: u32) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: u32) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[u32; 4]>[src]

pub fn rotate_left(self, n: u32x4) -> u32x4[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: u32x4) -> u32x4[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl Simd<[u32; 4]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[u32; 4]>[src]

pub fn wrapping_sum(self) -> u32[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> u32[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl Simd<[u32; 4]>[src]

pub fn max_element(self) -> u32[src]

Largest vector element value.

+

pub fn min_element(self) -> u32[src]

Smallest vector element value.

+

impl Simd<[u32; 4]>[src]

pub fn and(self) -> u32[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> u32[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> u32[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[u32; 4]>[src]

pub fn from_slice_aligned(slice: &[u32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[u32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[u32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[u32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[u32; 4]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [u32])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [u32])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [u32])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [u32])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[u32; 4]>[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl Simd<[u32; 4]>[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl Simd<[u32; 4]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[u32; 4]>[src]

pub fn eq(self, other: Self) -> m32x4[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m32x4[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m32x4[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m32x4[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m32x4[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m32x4[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[u32; 4]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<u32x4>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[u32; 4]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<u32x4>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[u32; 4]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[f32; 4]>[src]

pub const fn new(x0: f32, x1: f32, x2: f32, x3: f32) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: f32) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> f32[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> f32[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: f32) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: f32) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[f32; 4]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[f32; 4]>[src]

pub fn sum(self) -> f32[src]

Horizontal sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If one of the vector element is NaN the reduction returns +NaN. The resulting NaN is not required to be equal to any +of the NaNs in the vector.

+

pub fn product(self) -> f32[src]

Horizontal product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If one of the vector element is NaN the reduction returns +NaN. The resulting NaN is not required to be equal to any +of the NaNs in the vector.

+

impl Simd<[f32; 4]>[src]

pub fn max_element(self) -> f32[src]

Largest vector element value.

+

pub fn min_element(self) -> f32[src]

Smallest vector element value.

+

impl Simd<[f32; 4]>[src]

pub fn from_slice_aligned(slice: &[f32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[f32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[f32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[f32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[f32; 4]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [f32])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [f32])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [f32])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [f32])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[f32; 4]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[f32; 4]>[src]

pub const EPSILON: f32x4[src]

Machine epsilon value.

+

pub const MIN: f32x4[src]

Smallest finite value.

+

pub const MIN_POSITIVE: f32x4[src]

Smallest positive normal value.

+

pub const MAX: f32x4[src]

Largest finite value.

+

pub const NAN: f32x4[src]

Not a Number (NaN).

+

pub const INFINITY: f32x4[src]

Infinity (∞).

+

pub const NEG_INFINITY: f32x4[src]

Negative infinity (-∞).

+

pub const PI: f32x4[src]

Archimedes' constant (π)

+

pub const FRAC_PI_2: f32x4[src]

π/2

+

pub const FRAC_PI_3: f32x4[src]

π/3

+

pub const FRAC_PI_4: f32x4[src]

π/4

+

pub const FRAC_PI_6: f32x4[src]

π/6

+

pub const FRAC_PI_8: f32x4[src]

π/8

+

pub const FRAC_1_PI: f32x4[src]

1/π

+

pub const FRAC_2_PI: f32x4[src]

2/π

+

pub const FRAC_2_SQRT_PI: f32x4[src]

2/sqrt(π)

+

pub const SQRT_2: f32x4[src]

sqrt(2)

+

pub const FRAC_1_SQRT_2: f32x4[src]

1/sqrt(2)

+

pub const E: f32x4[src]

Euler's number (e)

+

pub const LOG2_E: f32x4[src]

log2(e)

+

pub const LOG10_E: f32x4[src]

log10(e)

+

pub const LN_2: f32x4[src]

ln(2)

+

pub const LN_10: f32x4[src]

ln(10)

+

impl Simd<[f32; 4]>[src]

pub fn is_nan(self) -> m32x4[src]

pub fn is_infinite(self) -> m32x4[src]

pub fn is_finite(self) -> m32x4[src]

impl Simd<[f32; 4]>[src]

pub fn abs(self) -> Self[src]

Absolute value.

+

impl Simd<[f32; 4]>[src]

pub fn cos(self) -> Self[src]

Cosine.

+

pub fn cos_pi(self) -> Self[src]

Cosine of self * PI.

+

impl Simd<[f32; 4]>[src]

pub fn exp(self) -> Self[src]

Returns the exponential function of self: e^(self).

+

impl Simd<[f32; 4]>[src]

pub fn ln(self) -> Self[src]

Returns the natural logarithm of self.

+

impl Simd<[f32; 4]>[src]

pub fn mul_add(self, y: Self, z: Self) -> Self[src]

Fused multiply add: self * y + z

+

impl Simd<[f32; 4]>[src]

pub fn mul_adde(self, y: Self, z: Self) -> Self[src]

Fused multiply add estimate: ~= self * y + z

+

While fused multiply-add (fma) has infinite precision, +mul_adde has at worst the same precision of a multiply followed by an add. +This might be more efficient on architectures that do not have an fma instruction.

+

impl Simd<[f32; 4]>[src]

pub fn powf(self, x: Self) -> Self[src]

Raises self number to the floating point power of x.

+

impl Simd<[f32; 4]>[src]

pub fn recpre(self) -> Self[src]

Reciprocal estimate: ~= 1. / self.

+

FIXME: The precision of the estimate is currently unspecified.

+

impl Simd<[f32; 4]>[src]

pub fn rsqrte(self) -> Self[src]

Reciprocal square-root estimate: ~= 1. / self.sqrt().

+

FIXME: The precision of the estimate is currently unspecified.

+

impl Simd<[f32; 4]>[src]

pub fn sin(self) -> Self[src]

Sine.

+

pub fn sin_pi(self) -> Self[src]

Sine of self * PI.

+

pub fn sin_cos_pi(self) -> (Self, Self)[src]

Sine and cosine of self * PI.

+

impl Simd<[f32; 4]>[src]

pub fn sqrt(self) -> Self[src]

impl Simd<[f32; 4]>[src]

pub fn sqrte(self) -> Self[src]

Square-root estimate.

+

FIXME: The precision of the estimate is currently unspecified.

+

impl Simd<[f32; 4]>[src]

pub fn tanh(self) -> Self[src]

Tanh.

+

impl Simd<[f32; 4]>[src]

pub fn eq(self, other: Self) -> m32x4[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m32x4[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m32x4[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m32x4[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m32x4[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m32x4[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[m32; 4]>[src]

pub const fn new(x0: bool, x1: bool, x2: bool, x3: bool) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: bool) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> bool[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> bool[src]

Extracts the value at index.

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

impl Simd<[m32; 4]>[src]

pub fn and(self) -> bool[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> bool[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> bool[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[m32; 4]>[src]

pub fn all(self) -> bool[src]

Are all vector lanes true?

+

pub fn any(self) -> bool[src]

Is any vector lane true?

+

pub fn none(self) -> bool[src]

Are all vector lanes false?

+

impl Simd<[m32; 4]>[src]

pub fn eq(self, other: Self) -> m32x4[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m32x4[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m32x4[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m32x4[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m32x4[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m32x4[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[m32; 4]>[src]

pub fn select<T>(self, a: Simd<T>, b: Simd<T>) -> Simd<T> where
    T: SimdArray<NT = <[m32; 4] as SimdArray>::NT>, [src]

Selects elements of a and b using mask.

+

The lanes of the result for which the mask is true contain +the values of a. The remaining lanes contain the values of +b.

+

impl Simd<[m32; 4]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<m32x4>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[m32; 4]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<m32x4>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[m32; 4]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[m32; 4]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[i64; 2]>[src]

pub const fn new(x0: i64, x1: i64) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: i64) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> i64[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> i64[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: i64) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: i64) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[i64; 2]>[src]

pub fn rotate_left(self, n: i64x2) -> i64x2[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: i64x2) -> i64x2[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl Simd<[i64; 2]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[i64; 2]>[src]

pub fn wrapping_sum(self) -> i64[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> i64[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl Simd<[i64; 2]>[src]

pub fn max_element(self) -> i64[src]

Largest vector element value.

+

pub fn min_element(self) -> i64[src]

Smallest vector element value.

+

impl Simd<[i64; 2]>[src]

pub fn and(self) -> i64[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> i64[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> i64[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[i64; 2]>[src]

pub fn from_slice_aligned(slice: &[i64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[i64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[i64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[i64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[i64; 2]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [i64])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [i64])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [i64])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [i64])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[i64; 2]>[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl Simd<[i64; 2]>[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl Simd<[i64; 2]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[i64; 2]>[src]

pub fn eq(self, other: Self) -> m64x2[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m64x2[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m64x2[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m64x2[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m64x2[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m64x2[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[i64; 2]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<i64x2>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[i64; 2]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<i64x2>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[i64; 2]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[u64; 2]>[src]

pub const fn new(x0: u64, x1: u64) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: u64) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> u64[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> u64[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: u64) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: u64) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[u64; 2]>[src]

pub fn rotate_left(self, n: u64x2) -> u64x2[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: u64x2) -> u64x2[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl Simd<[u64; 2]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[u64; 2]>[src]

pub fn wrapping_sum(self) -> u64[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> u64[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl Simd<[u64; 2]>[src]

pub fn max_element(self) -> u64[src]

Largest vector element value.

+

pub fn min_element(self) -> u64[src]

Smallest vector element value.

+

impl Simd<[u64; 2]>[src]

pub fn and(self) -> u64[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> u64[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> u64[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[u64; 2]>[src]

pub fn from_slice_aligned(slice: &[u64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[u64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[u64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[u64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[u64; 2]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [u64])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [u64])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [u64])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [u64])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[u64; 2]>[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl Simd<[u64; 2]>[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl Simd<[u64; 2]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[u64; 2]>[src]

pub fn eq(self, other: Self) -> m64x2[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m64x2[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m64x2[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m64x2[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m64x2[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m64x2[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[u64; 2]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<u64x2>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[u64; 2]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<u64x2>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[u64; 2]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[f64; 2]>[src]

pub const fn new(x0: f64, x1: f64) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: f64) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> f64[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> f64[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: f64) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: f64) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[f64; 2]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[f64; 2]>[src]

pub fn sum(self) -> f64[src]

Horizontal sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If one of the vector element is NaN the reduction returns +NaN. The resulting NaN is not required to be equal to any +of the NaNs in the vector.

+

pub fn product(self) -> f64[src]

Horizontal product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If one of the vector element is NaN the reduction returns +NaN. The resulting NaN is not required to be equal to any +of the NaNs in the vector.

+

impl Simd<[f64; 2]>[src]

pub fn max_element(self) -> f64[src]

Largest vector element value.

+

pub fn min_element(self) -> f64[src]

Smallest vector element value.

+

impl Simd<[f64; 2]>[src]

pub fn from_slice_aligned(slice: &[f64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[f64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[f64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[f64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[f64; 2]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [f64])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [f64])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [f64])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [f64])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[f64; 2]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[f64; 2]>[src]

pub const EPSILON: f64x2[src]

Machine epsilon value.

+

pub const MIN: f64x2[src]

Smallest finite value.

+

pub const MIN_POSITIVE: f64x2[src]

Smallest positive normal value.

+

pub const MAX: f64x2[src]

Largest finite value.

+

pub const NAN: f64x2[src]

Not a Number (NaN).

+

pub const INFINITY: f64x2[src]

Infinity (∞).

+

pub const NEG_INFINITY: f64x2[src]

Negative infinity (-∞).

+

pub const PI: f64x2[src]

Archimedes' constant (π)

+

pub const FRAC_PI_2: f64x2[src]

π/2

+

pub const FRAC_PI_3: f64x2[src]

π/3

+

pub const FRAC_PI_4: f64x2[src]

π/4

+

pub const FRAC_PI_6: f64x2[src]

π/6

+

pub const FRAC_PI_8: f64x2[src]

π/8

+

pub const FRAC_1_PI: f64x2[src]

1/π

+

pub const FRAC_2_PI: f64x2[src]

2/π

+

pub const FRAC_2_SQRT_PI: f64x2[src]

2/sqrt(π)

+

pub const SQRT_2: f64x2[src]

sqrt(2)

+

pub const FRAC_1_SQRT_2: f64x2[src]

1/sqrt(2)

+

pub const E: f64x2[src]

Euler's number (e)

+

pub const LOG2_E: f64x2[src]

log2(e)

+

pub const LOG10_E: f64x2[src]

log10(e)

+

pub const LN_2: f64x2[src]

ln(2)

+

pub const LN_10: f64x2[src]

ln(10)

+

impl Simd<[f64; 2]>[src]

pub fn is_nan(self) -> m64x2[src]

pub fn is_infinite(self) -> m64x2[src]

pub fn is_finite(self) -> m64x2[src]

impl Simd<[f64; 2]>[src]

pub fn abs(self) -> Self[src]

Absolute value.

+

impl Simd<[f64; 2]>[src]

pub fn cos(self) -> Self[src]

Cosine.

+

pub fn cos_pi(self) -> Self[src]

Cosine of self * PI.

+

impl Simd<[f64; 2]>[src]

pub fn exp(self) -> Self[src]

Returns the exponential function of self: e^(self).

+

impl Simd<[f64; 2]>[src]

pub fn ln(self) -> Self[src]

Returns the natural logarithm of self.

+

impl Simd<[f64; 2]>[src]

pub fn mul_add(self, y: Self, z: Self) -> Self[src]

Fused multiply add: self * y + z

+

impl Simd<[f64; 2]>[src]

pub fn mul_adde(self, y: Self, z: Self) -> Self[src]

Fused multiply add estimate: ~= self * y + z

+

While fused multiply-add (fma) has infinite precision, +mul_adde has at worst the same precision of a multiply followed by an add. +This might be more efficient on architectures that do not have an fma instruction.

+

impl Simd<[f64; 2]>[src]

pub fn powf(self, x: Self) -> Self[src]

Raises self number to the floating point power of x.

+

impl Simd<[f64; 2]>[src]

pub fn recpre(self) -> Self[src]

Reciprocal estimate: ~= 1. / self.

+

FIXME: The precision of the estimate is currently unspecified.

+

impl Simd<[f64; 2]>[src]

pub fn rsqrte(self) -> Self[src]

Reciprocal square-root estimate: ~= 1. / self.sqrt().

+

FIXME: The precision of the estimate is currently unspecified.

+

impl Simd<[f64; 2]>[src]

pub fn sin(self) -> Self[src]

Sine.

+

pub fn sin_pi(self) -> Self[src]

Sine of self * PI.

+

pub fn sin_cos_pi(self) -> (Self, Self)[src]

Sine and cosine of self * PI.

+

impl Simd<[f64; 2]>[src]

pub fn sqrt(self) -> Self[src]

impl Simd<[f64; 2]>[src]

pub fn sqrte(self) -> Self[src]

Square-root estimate.

+

FIXME: The precision of the estimate is currently unspecified.

+

impl Simd<[f64; 2]>[src]

pub fn tanh(self) -> Self[src]

Tanh.

+

impl Simd<[f64; 2]>[src]

pub fn eq(self, other: Self) -> m64x2[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m64x2[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m64x2[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m64x2[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m64x2[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m64x2[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[m64; 2]>[src]

pub const fn new(x0: bool, x1: bool) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: bool) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> bool[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> bool[src]

Extracts the value at index.

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

impl Simd<[m64; 2]>[src]

pub fn and(self) -> bool[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> bool[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> bool[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[m64; 2]>[src]

pub fn all(self) -> bool[src]

Are all vector lanes true?

+

pub fn any(self) -> bool[src]

Is any vector lane true?

+

pub fn none(self) -> bool[src]

Are all vector lanes false?

+

impl Simd<[m64; 2]>[src]

pub fn eq(self, other: Self) -> m64x2[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m64x2[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m64x2[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m64x2[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m64x2[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m64x2[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[m64; 2]>[src]

pub fn select<T>(self, a: Simd<T>, b: Simd<T>) -> Simd<T> where
    T: SimdArray<NT = <[m64; 2] as SimdArray>::NT>, [src]

Selects elements of a and b using mask.

+

The lanes of the result for which the mask is true contain +the values of a. The remaining lanes contain the values of +b.

+

impl Simd<[m64; 2]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<m64x2>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[m64; 2]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<m64x2>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[m64; 2]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[m64; 2]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[i128; 1]>[src]

pub const fn new(x0: i128) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: i128) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> i128[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> i128[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: i128) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: i128) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[i128; 1]>[src]

pub fn rotate_left(self, n: i128x1) -> i128x1[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: i128x1) -> i128x1[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl Simd<[i128; 1]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[i128; 1]>[src]

pub fn wrapping_sum(self) -> i128[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> i128[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl Simd<[i128; 1]>[src]

pub fn max_element(self) -> i128[src]

Largest vector element value.

+

pub fn min_element(self) -> i128[src]

Smallest vector element value.

+

impl Simd<[i128; 1]>[src]

pub fn and(self) -> i128[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> i128[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> i128[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[i128; 1]>[src]

pub fn from_slice_aligned(slice: &[i128]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[i128]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[i128]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[i128]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[i128; 1]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [i128])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [i128])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [i128])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [i128])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[i128; 1]>[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl Simd<[i128; 1]>[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl Simd<[i128; 1]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[i128; 1]>[src]

pub fn eq(self, other: Self) -> m128x1[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m128x1[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m128x1[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m128x1[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m128x1[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m128x1[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[i128; 1]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<i128x1>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[i128; 1]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<i128x1>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[i128; 1]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[u128; 1]>[src]

pub const fn new(x0: u128) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: u128) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> u128[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> u128[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: u128) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: u128) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[u128; 1]>[src]

pub fn rotate_left(self, n: u128x1) -> u128x1[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: u128x1) -> u128x1[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl Simd<[u128; 1]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[u128; 1]>[src]

pub fn wrapping_sum(self) -> u128[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> u128[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl Simd<[u128; 1]>[src]

pub fn max_element(self) -> u128[src]

Largest vector element value.

+

pub fn min_element(self) -> u128[src]

Smallest vector element value.

+

impl Simd<[u128; 1]>[src]

pub fn and(self) -> u128[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> u128[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> u128[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[u128; 1]>[src]

pub fn from_slice_aligned(slice: &[u128]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[u128]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[u128]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[u128]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[u128; 1]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [u128])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [u128])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [u128])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [u128])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[u128; 1]>[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl Simd<[u128; 1]>[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl Simd<[u128; 1]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[u128; 1]>[src]

pub fn eq(self, other: Self) -> m128x1[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m128x1[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m128x1[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m128x1[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m128x1[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m128x1[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[u128; 1]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<u128x1>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[u128; 1]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<u128x1>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[u128; 1]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[m128; 1]>[src]

pub const fn new(x0: bool) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: bool) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> bool[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> bool[src]

Extracts the value at index.

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

impl Simd<[m128; 1]>[src]

pub fn and(self) -> bool[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> bool[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> bool[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[m128; 1]>[src]

pub fn all(self) -> bool[src]

Are all vector lanes true?

+

pub fn any(self) -> bool[src]

Is any vector lane true?

+

pub fn none(self) -> bool[src]

Are all vector lanes false?

+

impl Simd<[m128; 1]>[src]

pub fn eq(self, other: Self) -> m128x1[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m128x1[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m128x1[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m128x1[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m128x1[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m128x1[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[m128; 1]>[src]

pub fn select<T>(self, a: Simd<T>, b: Simd<T>) -> Simd<T> where
    T: SimdArray<NT = <[m128; 1] as SimdArray>::NT>, [src]

Selects elements of a and b using mask.

+

The lanes of the result for which the mask is true contain +the values of a. The remaining lanes contain the values of +b.

+

impl Simd<[m128; 1]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<m128x1>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[m128; 1]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<m128x1>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[m128; 1]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[m128; 1]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[i8; 32]>[src]

pub const fn new(
    x0: i8,
    x1: i8,
    x2: i8,
    x3: i8,
    x4: i8,
    x5: i8,
    x6: i8,
    x7: i8,
    x8: i8,
    x9: i8,
    x10: i8,
    x11: i8,
    x12: i8,
    x13: i8,
    x14: i8,
    x15: i8,
    x16: i8,
    x17: i8,
    x18: i8,
    x19: i8,
    x20: i8,
    x21: i8,
    x22: i8,
    x23: i8,
    x24: i8,
    x25: i8,
    x26: i8,
    x27: i8,
    x28: i8,
    x29: i8,
    x30: i8,
    x31: i8
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: i8) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> i8[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> i8[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: i8) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: i8) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[i8; 32]>[src]

pub fn rotate_left(self, n: i8x32) -> i8x32[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: i8x32) -> i8x32[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl Simd<[i8; 32]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[i8; 32]>[src]

pub fn wrapping_sum(self) -> i8[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> i8[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl Simd<[i8; 32]>[src]

pub fn max_element(self) -> i8[src]

Largest vector element value.

+

pub fn min_element(self) -> i8[src]

Smallest vector element value.

+

impl Simd<[i8; 32]>[src]

pub fn and(self) -> i8[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> i8[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> i8[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[i8; 32]>[src]

pub fn from_slice_aligned(slice: &[i8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[i8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[i8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[i8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[i8; 32]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [i8])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [i8])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [i8])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [i8])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[i8; 32]>[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl Simd<[i8; 32]>[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl Simd<[i8; 32]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[i8; 32]>[src]

pub fn eq(self, other: Self) -> m8x32[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m8x32[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m8x32[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m8x32[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m8x32[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m8x32[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[i8; 32]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<i8x32>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[i8; 32]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<i8x32>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[i8; 32]>[src]

pub fn bitmask(self) -> u32[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[u8; 32]>[src]

pub const fn new(
    x0: u8,
    x1: u8,
    x2: u8,
    x3: u8,
    x4: u8,
    x5: u8,
    x6: u8,
    x7: u8,
    x8: u8,
    x9: u8,
    x10: u8,
    x11: u8,
    x12: u8,
    x13: u8,
    x14: u8,
    x15: u8,
    x16: u8,
    x17: u8,
    x18: u8,
    x19: u8,
    x20: u8,
    x21: u8,
    x22: u8,
    x23: u8,
    x24: u8,
    x25: u8,
    x26: u8,
    x27: u8,
    x28: u8,
    x29: u8,
    x30: u8,
    x31: u8
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: u8) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> u8[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> u8[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: u8) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: u8) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[u8; 32]>[src]

pub fn rotate_left(self, n: u8x32) -> u8x32[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: u8x32) -> u8x32[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl Simd<[u8; 32]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[u8; 32]>[src]

pub fn wrapping_sum(self) -> u8[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> u8[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl Simd<[u8; 32]>[src]

pub fn max_element(self) -> u8[src]

Largest vector element value.

+

pub fn min_element(self) -> u8[src]

Smallest vector element value.

+

impl Simd<[u8; 32]>[src]

pub fn and(self) -> u8[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> u8[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> u8[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[u8; 32]>[src]

pub fn from_slice_aligned(slice: &[u8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[u8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[u8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[u8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[u8; 32]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [u8])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [u8])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [u8])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [u8])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[u8; 32]>[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl Simd<[u8; 32]>[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl Simd<[u8; 32]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[u8; 32]>[src]

pub fn eq(self, other: Self) -> m8x32[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m8x32[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m8x32[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m8x32[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m8x32[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m8x32[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[u8; 32]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<u8x32>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[u8; 32]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<u8x32>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[u8; 32]>[src]

pub fn bitmask(self) -> u32[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[m8; 32]>[src]

pub const fn new(
    x0: bool,
    x1: bool,
    x2: bool,
    x3: bool,
    x4: bool,
    x5: bool,
    x6: bool,
    x7: bool,
    x8: bool,
    x9: bool,
    x10: bool,
    x11: bool,
    x12: bool,
    x13: bool,
    x14: bool,
    x15: bool,
    x16: bool,
    x17: bool,
    x18: bool,
    x19: bool,
    x20: bool,
    x21: bool,
    x22: bool,
    x23: bool,
    x24: bool,
    x25: bool,
    x26: bool,
    x27: bool,
    x28: bool,
    x29: bool,
    x30: bool,
    x31: bool
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: bool) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> bool[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> bool[src]

Extracts the value at index.

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

impl Simd<[m8; 32]>[src]

pub fn and(self) -> bool[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> bool[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> bool[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[m8; 32]>[src]

pub fn all(self) -> bool[src]

Are all vector lanes true?

+

pub fn any(self) -> bool[src]

Is any vector lane true?

+

pub fn none(self) -> bool[src]

Are all vector lanes false?

+

impl Simd<[m8; 32]>[src]

pub fn eq(self, other: Self) -> m8x32[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m8x32[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m8x32[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m8x32[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m8x32[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m8x32[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[m8; 32]>[src]

pub fn select<T>(self, a: Simd<T>, b: Simd<T>) -> Simd<T> where
    T: SimdArray<NT = <[m8; 32] as SimdArray>::NT>, [src]

Selects elements of a and b using mask.

+

The lanes of the result for which the mask is true contain +the values of a. The remaining lanes contain the values of +b.

+

impl Simd<[m8; 32]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<m8x32>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[m8; 32]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<m8x32>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[m8; 32]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[m8; 32]>[src]

pub fn bitmask(self) -> u32[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[i16; 16]>[src]

pub const fn new(
    x0: i16,
    x1: i16,
    x2: i16,
    x3: i16,
    x4: i16,
    x5: i16,
    x6: i16,
    x7: i16,
    x8: i16,
    x9: i16,
    x10: i16,
    x11: i16,
    x12: i16,
    x13: i16,
    x14: i16,
    x15: i16
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: i16) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> i16[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> i16[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: i16) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: i16) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[i16; 16]>[src]

pub fn rotate_left(self, n: i16x16) -> i16x16[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: i16x16) -> i16x16[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl Simd<[i16; 16]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[i16; 16]>[src]

pub fn wrapping_sum(self) -> i16[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> i16[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl Simd<[i16; 16]>[src]

pub fn max_element(self) -> i16[src]

Largest vector element value.

+

pub fn min_element(self) -> i16[src]

Smallest vector element value.

+

impl Simd<[i16; 16]>[src]

pub fn and(self) -> i16[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> i16[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> i16[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[i16; 16]>[src]

pub fn from_slice_aligned(slice: &[i16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[i16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[i16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[i16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[i16; 16]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [i16])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [i16])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [i16])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [i16])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[i16; 16]>[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl Simd<[i16; 16]>[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl Simd<[i16; 16]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[i16; 16]>[src]

pub fn eq(self, other: Self) -> m16x16[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m16x16[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m16x16[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m16x16[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m16x16[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m16x16[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[i16; 16]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<i16x16>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[i16; 16]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<i16x16>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[i16; 16]>[src]

pub fn bitmask(self) -> u16[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[u16; 16]>[src]

pub const fn new(
    x0: u16,
    x1: u16,
    x2: u16,
    x3: u16,
    x4: u16,
    x5: u16,
    x6: u16,
    x7: u16,
    x8: u16,
    x9: u16,
    x10: u16,
    x11: u16,
    x12: u16,
    x13: u16,
    x14: u16,
    x15: u16
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: u16) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> u16[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> u16[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: u16) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: u16) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[u16; 16]>[src]

pub fn rotate_left(self, n: u16x16) -> u16x16[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: u16x16) -> u16x16[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl Simd<[u16; 16]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[u16; 16]>[src]

pub fn wrapping_sum(self) -> u16[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> u16[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl Simd<[u16; 16]>[src]

pub fn max_element(self) -> u16[src]

Largest vector element value.

+

pub fn min_element(self) -> u16[src]

Smallest vector element value.

+

impl Simd<[u16; 16]>[src]

pub fn and(self) -> u16[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> u16[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> u16[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[u16; 16]>[src]

pub fn from_slice_aligned(slice: &[u16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[u16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[u16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[u16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[u16; 16]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [u16])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [u16])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [u16])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [u16])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[u16; 16]>[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl Simd<[u16; 16]>[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl Simd<[u16; 16]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[u16; 16]>[src]

pub fn eq(self, other: Self) -> m16x16[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m16x16[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m16x16[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m16x16[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m16x16[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m16x16[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[u16; 16]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<u16x16>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[u16; 16]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<u16x16>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[u16; 16]>[src]

pub fn bitmask(self) -> u16[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[m16; 16]>[src]

pub const fn new(
    x0: bool,
    x1: bool,
    x2: bool,
    x3: bool,
    x4: bool,
    x5: bool,
    x6: bool,
    x7: bool,
    x8: bool,
    x9: bool,
    x10: bool,
    x11: bool,
    x12: bool,
    x13: bool,
    x14: bool,
    x15: bool
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: bool) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> bool[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> bool[src]

Extracts the value at index.

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

impl Simd<[m16; 16]>[src]

pub fn and(self) -> bool[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> bool[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> bool[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[m16; 16]>[src]

pub fn all(self) -> bool[src]

Are all vector lanes true?

+

pub fn any(self) -> bool[src]

Is any vector lane true?

+

pub fn none(self) -> bool[src]

Are all vector lanes false?

+

impl Simd<[m16; 16]>[src]

pub fn eq(self, other: Self) -> m16x16[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m16x16[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m16x16[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m16x16[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m16x16[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m16x16[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[m16; 16]>[src]

pub fn select<T>(self, a: Simd<T>, b: Simd<T>) -> Simd<T> where
    T: SimdArray<NT = <[m16; 16] as SimdArray>::NT>, [src]

Selects elements of a and b using mask.

+

The lanes of the result for which the mask is true contain +the values of a. The remaining lanes contain the values of +b.

+

impl Simd<[m16; 16]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<m16x16>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[m16; 16]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<m16x16>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[m16; 16]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[m16; 16]>[src]

pub fn bitmask(self) -> u16[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[i32; 8]>[src]

pub const fn new(
    x0: i32,
    x1: i32,
    x2: i32,
    x3: i32,
    x4: i32,
    x5: i32,
    x6: i32,
    x7: i32
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: i32) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> i32[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> i32[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: i32) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: i32) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[i32; 8]>[src]

pub fn rotate_left(self, n: i32x8) -> i32x8[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: i32x8) -> i32x8[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl Simd<[i32; 8]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[i32; 8]>[src]

pub fn wrapping_sum(self) -> i32[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> i32[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl Simd<[i32; 8]>[src]

pub fn max_element(self) -> i32[src]

Largest vector element value.

+

pub fn min_element(self) -> i32[src]

Smallest vector element value.

+

impl Simd<[i32; 8]>[src]

pub fn and(self) -> i32[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> i32[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> i32[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[i32; 8]>[src]

pub fn from_slice_aligned(slice: &[i32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[i32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[i32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[i32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[i32; 8]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [i32])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [i32])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [i32])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [i32])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[i32; 8]>[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl Simd<[i32; 8]>[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl Simd<[i32; 8]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[i32; 8]>[src]

pub fn eq(self, other: Self) -> m32x8[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m32x8[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m32x8[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m32x8[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m32x8[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m32x8[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[i32; 8]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<i32x8>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[i32; 8]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<i32x8>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[i32; 8]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[u32; 8]>[src]

pub const fn new(
    x0: u32,
    x1: u32,
    x2: u32,
    x3: u32,
    x4: u32,
    x5: u32,
    x6: u32,
    x7: u32
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: u32) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> u32[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> u32[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: u32) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: u32) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[u32; 8]>[src]

pub fn rotate_left(self, n: u32x8) -> u32x8[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: u32x8) -> u32x8[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl Simd<[u32; 8]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[u32; 8]>[src]

pub fn wrapping_sum(self) -> u32[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> u32[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl Simd<[u32; 8]>[src]

pub fn max_element(self) -> u32[src]

Largest vector element value.

+

pub fn min_element(self) -> u32[src]

Smallest vector element value.

+

impl Simd<[u32; 8]>[src]

pub fn and(self) -> u32[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> u32[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> u32[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[u32; 8]>[src]

pub fn from_slice_aligned(slice: &[u32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[u32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[u32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[u32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[u32; 8]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [u32])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [u32])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [u32])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [u32])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[u32; 8]>[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl Simd<[u32; 8]>[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl Simd<[u32; 8]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[u32; 8]>[src]

pub fn eq(self, other: Self) -> m32x8[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m32x8[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m32x8[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m32x8[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m32x8[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m32x8[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[u32; 8]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<u32x8>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[u32; 8]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<u32x8>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[u32; 8]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[f32; 8]>[src]

pub const fn new(
    x0: f32,
    x1: f32,
    x2: f32,
    x3: f32,
    x4: f32,
    x5: f32,
    x6: f32,
    x7: f32
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: f32) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> f32[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> f32[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: f32) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: f32) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[f32; 8]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[f32; 8]>[src]

pub fn sum(self) -> f32[src]

Horizontal sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If one of the vector element is NaN the reduction returns +NaN. The resulting NaN is not required to be equal to any +of the NaNs in the vector.

+

pub fn product(self) -> f32[src]

Horizontal product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If one of the vector element is NaN the reduction returns +NaN. The resulting NaN is not required to be equal to any +of the NaNs in the vector.

+

impl Simd<[f32; 8]>[src]

pub fn max_element(self) -> f32[src]

Largest vector element value.

+

pub fn min_element(self) -> f32[src]

Smallest vector element value.

+

impl Simd<[f32; 8]>[src]

pub fn from_slice_aligned(slice: &[f32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[f32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[f32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[f32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[f32; 8]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [f32])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [f32])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [f32])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [f32])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[f32; 8]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[f32; 8]>[src]

pub const EPSILON: f32x8[src]

Machine epsilon value.

+

pub const MIN: f32x8[src]

Smallest finite value.

+

pub const MIN_POSITIVE: f32x8[src]

Smallest positive normal value.

+

pub const MAX: f32x8[src]

Largest finite value.

+

pub const NAN: f32x8[src]

Not a Number (NaN).

+

pub const INFINITY: f32x8[src]

Infinity (∞).

+

pub const NEG_INFINITY: f32x8[src]

Negative infinity (-∞).

+

pub const PI: f32x8[src]

Archimedes' constant (π)

+

pub const FRAC_PI_2: f32x8[src]

π/2

+

pub const FRAC_PI_3: f32x8[src]

π/3

+

pub const FRAC_PI_4: f32x8[src]

π/4

+

pub const FRAC_PI_6: f32x8[src]

π/6

+

pub const FRAC_PI_8: f32x8[src]

π/8

+

pub const FRAC_1_PI: f32x8[src]

1/π

+

pub const FRAC_2_PI: f32x8[src]

2/π

+

pub const FRAC_2_SQRT_PI: f32x8[src]

2/sqrt(π)

+

pub const SQRT_2: f32x8[src]

sqrt(2)

+

pub const FRAC_1_SQRT_2: f32x8[src]

1/sqrt(2)

+

pub const E: f32x8[src]

Euler's number (e)

+

pub const LOG2_E: f32x8[src]

log2(e)

+

pub const LOG10_E: f32x8[src]

log10(e)

+

pub const LN_2: f32x8[src]

ln(2)

+

pub const LN_10: f32x8[src]

ln(10)

+

impl Simd<[f32; 8]>[src]

pub fn is_nan(self) -> m32x8[src]

pub fn is_infinite(self) -> m32x8[src]

pub fn is_finite(self) -> m32x8[src]

impl Simd<[f32; 8]>[src]

pub fn abs(self) -> Self[src]

Absolute value.

+

impl Simd<[f32; 8]>[src]

pub fn cos(self) -> Self[src]

Cosine.

+

pub fn cos_pi(self) -> Self[src]

Cosine of self * PI.

+

impl Simd<[f32; 8]>[src]

pub fn exp(self) -> Self[src]

Returns the exponential function of self: e^(self).

+

impl Simd<[f32; 8]>[src]

pub fn ln(self) -> Self[src]

Returns the natural logarithm of self.

+

impl Simd<[f32; 8]>[src]

pub fn mul_add(self, y: Self, z: Self) -> Self[src]

Fused multiply add: self * y + z

+

impl Simd<[f32; 8]>[src]

pub fn mul_adde(self, y: Self, z: Self) -> Self[src]

Fused multiply add estimate: ~= self * y + z

+

While fused multiply-add (fma) has infinite precision, +mul_adde has at worst the same precision of a multiply followed by an add. +This might be more efficient on architectures that do not have an fma instruction.

+

impl Simd<[f32; 8]>[src]

pub fn powf(self, x: Self) -> Self[src]

Raises self number to the floating point power of x.

+

impl Simd<[f32; 8]>[src]

pub fn recpre(self) -> Self[src]

Reciprocal estimate: ~= 1. / self.

+

FIXME: The precision of the estimate is currently unspecified.

+

impl Simd<[f32; 8]>[src]

pub fn rsqrte(self) -> Self[src]

Reciprocal square-root estimate: ~= 1. / self.sqrt().

+

FIXME: The precision of the estimate is currently unspecified.

+

impl Simd<[f32; 8]>[src]

pub fn sin(self) -> Self[src]

Sine.

+

pub fn sin_pi(self) -> Self[src]

Sine of self * PI.

+

pub fn sin_cos_pi(self) -> (Self, Self)[src]

Sine and cosine of self * PI.

+

impl Simd<[f32; 8]>[src]

pub fn sqrt(self) -> Self[src]

impl Simd<[f32; 8]>[src]

pub fn sqrte(self) -> Self[src]

Square-root estimate.

+

FIXME: The precision of the estimate is currently unspecified.

+

impl Simd<[f32; 8]>[src]

pub fn tanh(self) -> Self[src]

Tanh.

+

impl Simd<[f32; 8]>[src]

pub fn eq(self, other: Self) -> m32x8[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m32x8[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m32x8[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m32x8[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m32x8[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m32x8[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[m32; 8]>[src]

pub const fn new(
    x0: bool,
    x1: bool,
    x2: bool,
    x3: bool,
    x4: bool,
    x5: bool,
    x6: bool,
    x7: bool
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: bool) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> bool[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> bool[src]

Extracts the value at index.

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

impl Simd<[m32; 8]>[src]

pub fn and(self) -> bool[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> bool[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> bool[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[m32; 8]>[src]

pub fn all(self) -> bool[src]

Are all vector lanes true?

+

pub fn any(self) -> bool[src]

Is any vector lane true?

+

pub fn none(self) -> bool[src]

Are all vector lanes false?

+

impl Simd<[m32; 8]>[src]

pub fn eq(self, other: Self) -> m32x8[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m32x8[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m32x8[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m32x8[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m32x8[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m32x8[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[m32; 8]>[src]

pub fn select<T>(self, a: Simd<T>, b: Simd<T>) -> Simd<T> where
    T: SimdArray<NT = <[m32; 8] as SimdArray>::NT>, [src]

Selects elements of a and b using mask.

+

The lanes of the result for which the mask is true contain +the values of a. The remaining lanes contain the values of +b.

+

impl Simd<[m32; 8]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<m32x8>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[m32; 8]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<m32x8>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[m32; 8]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[m32; 8]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[i64; 4]>[src]

pub const fn new(x0: i64, x1: i64, x2: i64, x3: i64) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: i64) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> i64[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> i64[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: i64) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: i64) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[i64; 4]>[src]

pub fn rotate_left(self, n: i64x4) -> i64x4[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: i64x4) -> i64x4[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl Simd<[i64; 4]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[i64; 4]>[src]

pub fn wrapping_sum(self) -> i64[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> i64[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl Simd<[i64; 4]>[src]

pub fn max_element(self) -> i64[src]

Largest vector element value.

+

pub fn min_element(self) -> i64[src]

Smallest vector element value.

+

impl Simd<[i64; 4]>[src]

pub fn and(self) -> i64[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> i64[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> i64[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[i64; 4]>[src]

pub fn from_slice_aligned(slice: &[i64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[i64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[i64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[i64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[i64; 4]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [i64])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [i64])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [i64])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [i64])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[i64; 4]>[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl Simd<[i64; 4]>[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl Simd<[i64; 4]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[i64; 4]>[src]

pub fn eq(self, other: Self) -> m64x4[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m64x4[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m64x4[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m64x4[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m64x4[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m64x4[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[i64; 4]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<i64x4>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[i64; 4]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<i64x4>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[i64; 4]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[u64; 4]>[src]

pub const fn new(x0: u64, x1: u64, x2: u64, x3: u64) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: u64) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> u64[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> u64[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: u64) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: u64) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[u64; 4]>[src]

pub fn rotate_left(self, n: u64x4) -> u64x4[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: u64x4) -> u64x4[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl Simd<[u64; 4]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[u64; 4]>[src]

pub fn wrapping_sum(self) -> u64[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> u64[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl Simd<[u64; 4]>[src]

pub fn max_element(self) -> u64[src]

Largest vector element value.

+

pub fn min_element(self) -> u64[src]

Smallest vector element value.

+

impl Simd<[u64; 4]>[src]

pub fn and(self) -> u64[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> u64[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> u64[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[u64; 4]>[src]

pub fn from_slice_aligned(slice: &[u64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[u64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[u64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[u64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[u64; 4]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [u64])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [u64])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [u64])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [u64])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[u64; 4]>[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl Simd<[u64; 4]>[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl Simd<[u64; 4]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[u64; 4]>[src]

pub fn eq(self, other: Self) -> m64x4[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m64x4[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m64x4[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m64x4[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m64x4[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m64x4[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[u64; 4]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<u64x4>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[u64; 4]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<u64x4>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[u64; 4]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[f64; 4]>[src]

pub const fn new(x0: f64, x1: f64, x2: f64, x3: f64) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: f64) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> f64[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> f64[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: f64) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: f64) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[f64; 4]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[f64; 4]>[src]

pub fn sum(self) -> f64[src]

Horizontal sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If one of the vector element is NaN the reduction returns +NaN. The resulting NaN is not required to be equal to any +of the NaNs in the vector.

+

pub fn product(self) -> f64[src]

Horizontal product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If one of the vector element is NaN the reduction returns +NaN. The resulting NaN is not required to be equal to any +of the NaNs in the vector.

+

impl Simd<[f64; 4]>[src]

pub fn max_element(self) -> f64[src]

Largest vector element value.

+

pub fn min_element(self) -> f64[src]

Smallest vector element value.

+

impl Simd<[f64; 4]>[src]

pub fn from_slice_aligned(slice: &[f64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[f64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[f64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[f64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[f64; 4]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [f64])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [f64])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [f64])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [f64])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[f64; 4]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[f64; 4]>[src]

pub const EPSILON: f64x4[src]

Machine epsilon value.

+

pub const MIN: f64x4[src]

Smallest finite value.

+

pub const MIN_POSITIVE: f64x4[src]

Smallest positive normal value.

+

pub const MAX: f64x4[src]

Largest finite value.

+

pub const NAN: f64x4[src]

Not a Number (NaN).

+

pub const INFINITY: f64x4[src]

Infinity (∞).

+

pub const NEG_INFINITY: f64x4[src]

Negative infinity (-∞).

+

pub const PI: f64x4[src]

Archimedes' constant (π)

+

pub const FRAC_PI_2: f64x4[src]

π/2

+

pub const FRAC_PI_3: f64x4[src]

π/3

+

pub const FRAC_PI_4: f64x4[src]

π/4

+

pub const FRAC_PI_6: f64x4[src]

π/6

+

pub const FRAC_PI_8: f64x4[src]

π/8

+

pub const FRAC_1_PI: f64x4[src]

1/π

+

pub const FRAC_2_PI: f64x4[src]

2/π

+

pub const FRAC_2_SQRT_PI: f64x4[src]

2/sqrt(π)

+

pub const SQRT_2: f64x4[src]

sqrt(2)

+

pub const FRAC_1_SQRT_2: f64x4[src]

1/sqrt(2)

+

pub const E: f64x4[src]

Euler's number (e)

+

pub const LOG2_E: f64x4[src]

log2(e)

+

pub const LOG10_E: f64x4[src]

log10(e)

+

pub const LN_2: f64x4[src]

ln(2)

+

pub const LN_10: f64x4[src]

ln(10)

+

impl Simd<[f64; 4]>[src]

pub fn is_nan(self) -> m64x4[src]

pub fn is_infinite(self) -> m64x4[src]

pub fn is_finite(self) -> m64x4[src]

impl Simd<[f64; 4]>[src]

pub fn abs(self) -> Self[src]

Absolute value.

+

impl Simd<[f64; 4]>[src]

pub fn cos(self) -> Self[src]

Cosine.

+

pub fn cos_pi(self) -> Self[src]

Cosine of self * PI.

+

impl Simd<[f64; 4]>[src]

pub fn exp(self) -> Self[src]

Returns the exponential function of self: e^(self).

+

impl Simd<[f64; 4]>[src]

pub fn ln(self) -> Self[src]

Returns the natural logarithm of self.

+

impl Simd<[f64; 4]>[src]

pub fn mul_add(self, y: Self, z: Self) -> Self[src]

Fused multiply add: self * y + z

+

impl Simd<[f64; 4]>[src]

pub fn mul_adde(self, y: Self, z: Self) -> Self[src]

Fused multiply add estimate: ~= self * y + z

+

While fused multiply-add (fma) has infinite precision, +mul_adde has at worst the same precision of a multiply followed by an add. +This might be more efficient on architectures that do not have an fma instruction.

+

impl Simd<[f64; 4]>[src]

pub fn powf(self, x: Self) -> Self[src]

Raises self number to the floating point power of x.

+

impl Simd<[f64; 4]>[src]

pub fn recpre(self) -> Self[src]

Reciprocal estimate: ~= 1. / self.

+

FIXME: The precision of the estimate is currently unspecified.

+

impl Simd<[f64; 4]>[src]

pub fn rsqrte(self) -> Self[src]

Reciprocal square-root estimate: ~= 1. / self.sqrt().

+

FIXME: The precision of the estimate is currently unspecified.

+

impl Simd<[f64; 4]>[src]

pub fn sin(self) -> Self[src]

Sine.

+

pub fn sin_pi(self) -> Self[src]

Sine of self * PI.

+

pub fn sin_cos_pi(self) -> (Self, Self)[src]

Sine and cosine of self * PI.

+

impl Simd<[f64; 4]>[src]

pub fn sqrt(self) -> Self[src]

impl Simd<[f64; 4]>[src]

pub fn sqrte(self) -> Self[src]

Square-root estimate.

+

FIXME: The precision of the estimate is currently unspecified.

+

impl Simd<[f64; 4]>[src]

pub fn tanh(self) -> Self[src]

Tanh.

+

impl Simd<[f64; 4]>[src]

pub fn eq(self, other: Self) -> m64x4[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m64x4[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m64x4[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m64x4[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m64x4[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m64x4[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[m64; 4]>[src]

pub const fn new(x0: bool, x1: bool, x2: bool, x3: bool) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: bool) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> bool[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> bool[src]

Extracts the value at index.

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

impl Simd<[m64; 4]>[src]

pub fn and(self) -> bool[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> bool[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> bool[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[m64; 4]>[src]

pub fn all(self) -> bool[src]

Are all vector lanes true?

+

pub fn any(self) -> bool[src]

Is any vector lane true?

+

pub fn none(self) -> bool[src]

Are all vector lanes false?

+

impl Simd<[m64; 4]>[src]

pub fn eq(self, other: Self) -> m64x4[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m64x4[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m64x4[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m64x4[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m64x4[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m64x4[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[m64; 4]>[src]

pub fn select<T>(self, a: Simd<T>, b: Simd<T>) -> Simd<T> where
    T: SimdArray<NT = <[m64; 4] as SimdArray>::NT>, [src]

Selects elements of a and b using mask.

+

The lanes of the result for which the mask is true contain +the values of a. The remaining lanes contain the values of +b.

+

impl Simd<[m64; 4]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<m64x4>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[m64; 4]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<m64x4>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[m64; 4]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[m64; 4]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[i128; 2]>[src]

pub const fn new(x0: i128, x1: i128) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: i128) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> i128[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> i128[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: i128) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: i128) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[i128; 2]>[src]

pub fn rotate_left(self, n: i128x2) -> i128x2[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: i128x2) -> i128x2[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl Simd<[i128; 2]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[i128; 2]>[src]

pub fn wrapping_sum(self) -> i128[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> i128[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl Simd<[i128; 2]>[src]

pub fn max_element(self) -> i128[src]

Largest vector element value.

+

pub fn min_element(self) -> i128[src]

Smallest vector element value.

+

impl Simd<[i128; 2]>[src]

pub fn and(self) -> i128[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> i128[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> i128[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[i128; 2]>[src]

pub fn from_slice_aligned(slice: &[i128]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[i128]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[i128]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[i128]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[i128; 2]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [i128])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [i128])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [i128])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [i128])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[i128; 2]>[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl Simd<[i128; 2]>[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl Simd<[i128; 2]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[i128; 2]>[src]

pub fn eq(self, other: Self) -> m128x2[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m128x2[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m128x2[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m128x2[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m128x2[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m128x2[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[i128; 2]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<i128x2>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[i128; 2]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<i128x2>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[i128; 2]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[u128; 2]>[src]

pub const fn new(x0: u128, x1: u128) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: u128) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> u128[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> u128[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: u128) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: u128) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[u128; 2]>[src]

pub fn rotate_left(self, n: u128x2) -> u128x2[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: u128x2) -> u128x2[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl Simd<[u128; 2]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[u128; 2]>[src]

pub fn wrapping_sum(self) -> u128[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> u128[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl Simd<[u128; 2]>[src]

pub fn max_element(self) -> u128[src]

Largest vector element value.

+

pub fn min_element(self) -> u128[src]

Smallest vector element value.

+

impl Simd<[u128; 2]>[src]

pub fn and(self) -> u128[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> u128[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> u128[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[u128; 2]>[src]

pub fn from_slice_aligned(slice: &[u128]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[u128]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[u128]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[u128]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[u128; 2]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [u128])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [u128])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [u128])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [u128])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[u128; 2]>[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl Simd<[u128; 2]>[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl Simd<[u128; 2]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[u128; 2]>[src]

pub fn eq(self, other: Self) -> m128x2[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m128x2[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m128x2[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m128x2[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m128x2[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m128x2[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[u128; 2]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<u128x2>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[u128; 2]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<u128x2>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[u128; 2]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[m128; 2]>[src]

pub const fn new(x0: bool, x1: bool) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: bool) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> bool[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> bool[src]

Extracts the value at index.

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

impl Simd<[m128; 2]>[src]

pub fn and(self) -> bool[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> bool[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> bool[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[m128; 2]>[src]

pub fn all(self) -> bool[src]

Are all vector lanes true?

+

pub fn any(self) -> bool[src]

Is any vector lane true?

+

pub fn none(self) -> bool[src]

Are all vector lanes false?

+

impl Simd<[m128; 2]>[src]

pub fn eq(self, other: Self) -> m128x2[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m128x2[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m128x2[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m128x2[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m128x2[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m128x2[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[m128; 2]>[src]

pub fn select<T>(self, a: Simd<T>, b: Simd<T>) -> Simd<T> where
    T: SimdArray<NT = <[m128; 2] as SimdArray>::NT>, [src]

Selects elements of a and b using mask.

+

The lanes of the result for which the mask is true contain +the values of a. The remaining lanes contain the values of +b.

+

impl Simd<[m128; 2]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<m128x2>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[m128; 2]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<m128x2>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[m128; 2]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[m128; 2]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[i8; 64]>[src]

pub const fn new(
    x0: i8,
    x1: i8,
    x2: i8,
    x3: i8,
    x4: i8,
    x5: i8,
    x6: i8,
    x7: i8,
    x8: i8,
    x9: i8,
    x10: i8,
    x11: i8,
    x12: i8,
    x13: i8,
    x14: i8,
    x15: i8,
    x16: i8,
    x17: i8,
    x18: i8,
    x19: i8,
    x20: i8,
    x21: i8,
    x22: i8,
    x23: i8,
    x24: i8,
    x25: i8,
    x26: i8,
    x27: i8,
    x28: i8,
    x29: i8,
    x30: i8,
    x31: i8,
    x32: i8,
    x33: i8,
    x34: i8,
    x35: i8,
    x36: i8,
    x37: i8,
    x38: i8,
    x39: i8,
    x40: i8,
    x41: i8,
    x42: i8,
    x43: i8,
    x44: i8,
    x45: i8,
    x46: i8,
    x47: i8,
    x48: i8,
    x49: i8,
    x50: i8,
    x51: i8,
    x52: i8,
    x53: i8,
    x54: i8,
    x55: i8,
    x56: i8,
    x57: i8,
    x58: i8,
    x59: i8,
    x60: i8,
    x61: i8,
    x62: i8,
    x63: i8
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: i8) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> i8[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> i8[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: i8) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: i8) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[i8; 64]>[src]

pub fn rotate_left(self, n: i8x64) -> i8x64[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: i8x64) -> i8x64[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl Simd<[i8; 64]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[i8; 64]>[src]

pub fn wrapping_sum(self) -> i8[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> i8[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl Simd<[i8; 64]>[src]

pub fn max_element(self) -> i8[src]

Largest vector element value.

+

pub fn min_element(self) -> i8[src]

Smallest vector element value.

+

impl Simd<[i8; 64]>[src]

pub fn and(self) -> i8[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> i8[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> i8[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[i8; 64]>[src]

pub fn from_slice_aligned(slice: &[i8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[i8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[i8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[i8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[i8; 64]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [i8])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [i8])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [i8])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [i8])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[i8; 64]>[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl Simd<[i8; 64]>[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl Simd<[i8; 64]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[i8; 64]>[src]

pub fn eq(self, other: Self) -> m8x64[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m8x64[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m8x64[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m8x64[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m8x64[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m8x64[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[i8; 64]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<i8x64>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[i8; 64]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<i8x64>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[i8; 64]>[src]

pub fn bitmask(self) -> u64[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[u8; 64]>[src]

pub const fn new(
    x0: u8,
    x1: u8,
    x2: u8,
    x3: u8,
    x4: u8,
    x5: u8,
    x6: u8,
    x7: u8,
    x8: u8,
    x9: u8,
    x10: u8,
    x11: u8,
    x12: u8,
    x13: u8,
    x14: u8,
    x15: u8,
    x16: u8,
    x17: u8,
    x18: u8,
    x19: u8,
    x20: u8,
    x21: u8,
    x22: u8,
    x23: u8,
    x24: u8,
    x25: u8,
    x26: u8,
    x27: u8,
    x28: u8,
    x29: u8,
    x30: u8,
    x31: u8,
    x32: u8,
    x33: u8,
    x34: u8,
    x35: u8,
    x36: u8,
    x37: u8,
    x38: u8,
    x39: u8,
    x40: u8,
    x41: u8,
    x42: u8,
    x43: u8,
    x44: u8,
    x45: u8,
    x46: u8,
    x47: u8,
    x48: u8,
    x49: u8,
    x50: u8,
    x51: u8,
    x52: u8,
    x53: u8,
    x54: u8,
    x55: u8,
    x56: u8,
    x57: u8,
    x58: u8,
    x59: u8,
    x60: u8,
    x61: u8,
    x62: u8,
    x63: u8
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: u8) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> u8[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> u8[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: u8) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: u8) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[u8; 64]>[src]

pub fn rotate_left(self, n: u8x64) -> u8x64[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: u8x64) -> u8x64[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl Simd<[u8; 64]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[u8; 64]>[src]

pub fn wrapping_sum(self) -> u8[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> u8[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl Simd<[u8; 64]>[src]

pub fn max_element(self) -> u8[src]

Largest vector element value.

+

pub fn min_element(self) -> u8[src]

Smallest vector element value.

+

impl Simd<[u8; 64]>[src]

pub fn and(self) -> u8[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> u8[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> u8[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[u8; 64]>[src]

pub fn from_slice_aligned(slice: &[u8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[u8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[u8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[u8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[u8; 64]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [u8])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [u8])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [u8])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [u8])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[u8; 64]>[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl Simd<[u8; 64]>[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl Simd<[u8; 64]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[u8; 64]>[src]

pub fn eq(self, other: Self) -> m8x64[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m8x64[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m8x64[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m8x64[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m8x64[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m8x64[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[u8; 64]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<u8x64>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[u8; 64]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<u8x64>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[u8; 64]>[src]

pub fn bitmask(self) -> u64[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[m8; 64]>[src]

pub const fn new(
    x0: bool,
    x1: bool,
    x2: bool,
    x3: bool,
    x4: bool,
    x5: bool,
    x6: bool,
    x7: bool,
    x8: bool,
    x9: bool,
    x10: bool,
    x11: bool,
    x12: bool,
    x13: bool,
    x14: bool,
    x15: bool,
    x16: bool,
    x17: bool,
    x18: bool,
    x19: bool,
    x20: bool,
    x21: bool,
    x22: bool,
    x23: bool,
    x24: bool,
    x25: bool,
    x26: bool,
    x27: bool,
    x28: bool,
    x29: bool,
    x30: bool,
    x31: bool,
    x32: bool,
    x33: bool,
    x34: bool,
    x35: bool,
    x36: bool,
    x37: bool,
    x38: bool,
    x39: bool,
    x40: bool,
    x41: bool,
    x42: bool,
    x43: bool,
    x44: bool,
    x45: bool,
    x46: bool,
    x47: bool,
    x48: bool,
    x49: bool,
    x50: bool,
    x51: bool,
    x52: bool,
    x53: bool,
    x54: bool,
    x55: bool,
    x56: bool,
    x57: bool,
    x58: bool,
    x59: bool,
    x60: bool,
    x61: bool,
    x62: bool,
    x63: bool
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: bool) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> bool[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> bool[src]

Extracts the value at index.

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

impl Simd<[m8; 64]>[src]

pub fn and(self) -> bool[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> bool[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> bool[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[m8; 64]>[src]

pub fn all(self) -> bool[src]

Are all vector lanes true?

+

pub fn any(self) -> bool[src]

Is any vector lane true?

+

pub fn none(self) -> bool[src]

Are all vector lanes false?

+

impl Simd<[m8; 64]>[src]

pub fn eq(self, other: Self) -> m8x64[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m8x64[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m8x64[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m8x64[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m8x64[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m8x64[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[m8; 64]>[src]

pub fn select<T>(self, a: Simd<T>, b: Simd<T>) -> Simd<T> where
    T: SimdArray<NT = <[m8; 64] as SimdArray>::NT>, [src]

Selects elements of a and b using mask.

+

The lanes of the result for which the mask is true contain +the values of a. The remaining lanes contain the values of +b.

+

impl Simd<[m8; 64]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<m8x64>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[m8; 64]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<m8x64>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[m8; 64]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[m8; 64]>[src]

pub fn bitmask(self) -> u64[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[i16; 32]>[src]

pub const fn new(
    x0: i16,
    x1: i16,
    x2: i16,
    x3: i16,
    x4: i16,
    x5: i16,
    x6: i16,
    x7: i16,
    x8: i16,
    x9: i16,
    x10: i16,
    x11: i16,
    x12: i16,
    x13: i16,
    x14: i16,
    x15: i16,
    x16: i16,
    x17: i16,
    x18: i16,
    x19: i16,
    x20: i16,
    x21: i16,
    x22: i16,
    x23: i16,
    x24: i16,
    x25: i16,
    x26: i16,
    x27: i16,
    x28: i16,
    x29: i16,
    x30: i16,
    x31: i16
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: i16) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> i16[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> i16[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: i16) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: i16) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[i16; 32]>[src]

pub fn rotate_left(self, n: i16x32) -> i16x32[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: i16x32) -> i16x32[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl Simd<[i16; 32]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[i16; 32]>[src]

pub fn wrapping_sum(self) -> i16[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> i16[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl Simd<[i16; 32]>[src]

pub fn max_element(self) -> i16[src]

Largest vector element value.

+

pub fn min_element(self) -> i16[src]

Smallest vector element value.

+

impl Simd<[i16; 32]>[src]

pub fn and(self) -> i16[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> i16[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> i16[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[i16; 32]>[src]

pub fn from_slice_aligned(slice: &[i16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[i16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[i16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[i16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[i16; 32]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [i16])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [i16])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [i16])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [i16])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[i16; 32]>[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl Simd<[i16; 32]>[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl Simd<[i16; 32]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[i16; 32]>[src]

pub fn eq(self, other: Self) -> m16x32[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m16x32[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m16x32[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m16x32[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m16x32[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m16x32[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[i16; 32]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<i16x32>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[i16; 32]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<i16x32>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[i16; 32]>[src]

pub fn bitmask(self) -> u32[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[u16; 32]>[src]

pub const fn new(
    x0: u16,
    x1: u16,
    x2: u16,
    x3: u16,
    x4: u16,
    x5: u16,
    x6: u16,
    x7: u16,
    x8: u16,
    x9: u16,
    x10: u16,
    x11: u16,
    x12: u16,
    x13: u16,
    x14: u16,
    x15: u16,
    x16: u16,
    x17: u16,
    x18: u16,
    x19: u16,
    x20: u16,
    x21: u16,
    x22: u16,
    x23: u16,
    x24: u16,
    x25: u16,
    x26: u16,
    x27: u16,
    x28: u16,
    x29: u16,
    x30: u16,
    x31: u16
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: u16) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> u16[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> u16[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: u16) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: u16) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[u16; 32]>[src]

pub fn rotate_left(self, n: u16x32) -> u16x32[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: u16x32) -> u16x32[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl Simd<[u16; 32]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[u16; 32]>[src]

pub fn wrapping_sum(self) -> u16[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> u16[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl Simd<[u16; 32]>[src]

pub fn max_element(self) -> u16[src]

Largest vector element value.

+

pub fn min_element(self) -> u16[src]

Smallest vector element value.

+

impl Simd<[u16; 32]>[src]

pub fn and(self) -> u16[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> u16[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> u16[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[u16; 32]>[src]

pub fn from_slice_aligned(slice: &[u16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[u16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[u16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[u16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[u16; 32]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [u16])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [u16])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [u16])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [u16])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[u16; 32]>[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl Simd<[u16; 32]>[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl Simd<[u16; 32]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[u16; 32]>[src]

pub fn eq(self, other: Self) -> m16x32[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m16x32[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m16x32[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m16x32[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m16x32[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m16x32[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[u16; 32]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<u16x32>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[u16; 32]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<u16x32>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[u16; 32]>[src]

pub fn bitmask(self) -> u32[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[m16; 32]>[src]

pub const fn new(
    x0: bool,
    x1: bool,
    x2: bool,
    x3: bool,
    x4: bool,
    x5: bool,
    x6: bool,
    x7: bool,
    x8: bool,
    x9: bool,
    x10: bool,
    x11: bool,
    x12: bool,
    x13: bool,
    x14: bool,
    x15: bool,
    x16: bool,
    x17: bool,
    x18: bool,
    x19: bool,
    x20: bool,
    x21: bool,
    x22: bool,
    x23: bool,
    x24: bool,
    x25: bool,
    x26: bool,
    x27: bool,
    x28: bool,
    x29: bool,
    x30: bool,
    x31: bool
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: bool) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> bool[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> bool[src]

Extracts the value at index.

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

impl Simd<[m16; 32]>[src]

pub fn and(self) -> bool[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> bool[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> bool[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[m16; 32]>[src]

pub fn all(self) -> bool[src]

Are all vector lanes true?

+

pub fn any(self) -> bool[src]

Is any vector lane true?

+

pub fn none(self) -> bool[src]

Are all vector lanes false?

+

impl Simd<[m16; 32]>[src]

pub fn eq(self, other: Self) -> m16x32[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m16x32[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m16x32[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m16x32[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m16x32[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m16x32[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[m16; 32]>[src]

pub fn select<T>(self, a: Simd<T>, b: Simd<T>) -> Simd<T> where
    T: SimdArray<NT = <[m16; 32] as SimdArray>::NT>, [src]

Selects elements of a and b using mask.

+

The lanes of the result for which the mask is true contain +the values of a. The remaining lanes contain the values of +b.

+

impl Simd<[m16; 32]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<m16x32>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[m16; 32]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<m16x32>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[m16; 32]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[m16; 32]>[src]

pub fn bitmask(self) -> u32[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[i32; 16]>[src]

pub const fn new(
    x0: i32,
    x1: i32,
    x2: i32,
    x3: i32,
    x4: i32,
    x5: i32,
    x6: i32,
    x7: i32,
    x8: i32,
    x9: i32,
    x10: i32,
    x11: i32,
    x12: i32,
    x13: i32,
    x14: i32,
    x15: i32
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: i32) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> i32[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> i32[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: i32) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: i32) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[i32; 16]>[src]

pub fn rotate_left(self, n: i32x16) -> i32x16[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: i32x16) -> i32x16[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl Simd<[i32; 16]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[i32; 16]>[src]

pub fn wrapping_sum(self) -> i32[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> i32[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl Simd<[i32; 16]>[src]

pub fn max_element(self) -> i32[src]

Largest vector element value.

+

pub fn min_element(self) -> i32[src]

Smallest vector element value.

+

impl Simd<[i32; 16]>[src]

pub fn and(self) -> i32[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> i32[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> i32[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[i32; 16]>[src]

pub fn from_slice_aligned(slice: &[i32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[i32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[i32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[i32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[i32; 16]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [i32])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [i32])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [i32])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [i32])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[i32; 16]>[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl Simd<[i32; 16]>[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl Simd<[i32; 16]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[i32; 16]>[src]

pub fn eq(self, other: Self) -> m32x16[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m32x16[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m32x16[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m32x16[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m32x16[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m32x16[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[i32; 16]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<i32x16>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[i32; 16]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<i32x16>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[i32; 16]>[src]

pub fn bitmask(self) -> u16[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[u32; 16]>[src]

pub const fn new(
    x0: u32,
    x1: u32,
    x2: u32,
    x3: u32,
    x4: u32,
    x5: u32,
    x6: u32,
    x7: u32,
    x8: u32,
    x9: u32,
    x10: u32,
    x11: u32,
    x12: u32,
    x13: u32,
    x14: u32,
    x15: u32
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: u32) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> u32[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> u32[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: u32) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: u32) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[u32; 16]>[src]

pub fn rotate_left(self, n: u32x16) -> u32x16[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: u32x16) -> u32x16[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl Simd<[u32; 16]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[u32; 16]>[src]

pub fn wrapping_sum(self) -> u32[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> u32[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl Simd<[u32; 16]>[src]

pub fn max_element(self) -> u32[src]

Largest vector element value.

+

pub fn min_element(self) -> u32[src]

Smallest vector element value.

+

impl Simd<[u32; 16]>[src]

pub fn and(self) -> u32[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> u32[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> u32[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[u32; 16]>[src]

pub fn from_slice_aligned(slice: &[u32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[u32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[u32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[u32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[u32; 16]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [u32])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [u32])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [u32])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [u32])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[u32; 16]>[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl Simd<[u32; 16]>[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl Simd<[u32; 16]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[u32; 16]>[src]

pub fn eq(self, other: Self) -> m32x16[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m32x16[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m32x16[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m32x16[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m32x16[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m32x16[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[u32; 16]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<u32x16>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[u32; 16]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<u32x16>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[u32; 16]>[src]

pub fn bitmask(self) -> u16[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[f32; 16]>[src]

pub const fn new(
    x0: f32,
    x1: f32,
    x2: f32,
    x3: f32,
    x4: f32,
    x5: f32,
    x6: f32,
    x7: f32,
    x8: f32,
    x9: f32,
    x10: f32,
    x11: f32,
    x12: f32,
    x13: f32,
    x14: f32,
    x15: f32
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: f32) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> f32[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> f32[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: f32) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: f32) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[f32; 16]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[f32; 16]>[src]

pub fn sum(self) -> f32[src]

Horizontal sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If one of the vector element is NaN the reduction returns +NaN. The resulting NaN is not required to be equal to any +of the NaNs in the vector.

+

pub fn product(self) -> f32[src]

Horizontal product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If one of the vector element is NaN the reduction returns +NaN. The resulting NaN is not required to be equal to any +of the NaNs in the vector.

+

impl Simd<[f32; 16]>[src]

pub fn max_element(self) -> f32[src]

Largest vector element value.

+

pub fn min_element(self) -> f32[src]

Smallest vector element value.

+

impl Simd<[f32; 16]>[src]

pub fn from_slice_aligned(slice: &[f32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[f32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[f32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[f32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[f32; 16]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [f32])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [f32])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [f32])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [f32])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[f32; 16]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[f32; 16]>[src]

pub const EPSILON: f32x16[src]

Machine epsilon value.

+

pub const MIN: f32x16[src]

Smallest finite value.

+

pub const MIN_POSITIVE: f32x16[src]

Smallest positive normal value.

+

pub const MAX: f32x16[src]

Largest finite value.

+

pub const NAN: f32x16[src]

Not a Number (NaN).

+

pub const INFINITY: f32x16[src]

Infinity (∞).

+

pub const NEG_INFINITY: f32x16[src]

Negative infinity (-∞).

+

pub const PI: f32x16[src]

Archimedes' constant (π)

+

pub const FRAC_PI_2: f32x16[src]

π/2

+

pub const FRAC_PI_3: f32x16[src]

π/3

+

pub const FRAC_PI_4: f32x16[src]

π/4

+

pub const FRAC_PI_6: f32x16[src]

π/6

+

pub const FRAC_PI_8: f32x16[src]

π/8

+

pub const FRAC_1_PI: f32x16[src]

1/π

+

pub const FRAC_2_PI: f32x16[src]

2/π

+

pub const FRAC_2_SQRT_PI: f32x16[src]

2/sqrt(π)

+

pub const SQRT_2: f32x16[src]

sqrt(2)

+

pub const FRAC_1_SQRT_2: f32x16[src]

1/sqrt(2)

+

pub const E: f32x16[src]

Euler's number (e)

+

pub const LOG2_E: f32x16[src]

log2(e)

+

pub const LOG10_E: f32x16[src]

log10(e)

+

pub const LN_2: f32x16[src]

ln(2)

+

pub const LN_10: f32x16[src]

ln(10)

+

impl Simd<[f32; 16]>[src]

pub fn is_nan(self) -> m32x16[src]

pub fn is_infinite(self) -> m32x16[src]

pub fn is_finite(self) -> m32x16[src]

impl Simd<[f32; 16]>[src]

pub fn abs(self) -> Self[src]

Absolute value.

+

impl Simd<[f32; 16]>[src]

pub fn cos(self) -> Self[src]

Cosine.

+

pub fn cos_pi(self) -> Self[src]

Cosine of self * PI.

+

impl Simd<[f32; 16]>[src]

pub fn exp(self) -> Self[src]

Returns the exponential function of self: e^(self).

+

impl Simd<[f32; 16]>[src]

pub fn ln(self) -> Self[src]

Returns the natural logarithm of self.

+

impl Simd<[f32; 16]>[src]

pub fn mul_add(self, y: Self, z: Self) -> Self[src]

Fused multiply add: self * y + z

+

impl Simd<[f32; 16]>[src]

pub fn mul_adde(self, y: Self, z: Self) -> Self[src]

Fused multiply add estimate: ~= self * y + z

+

While fused multiply-add (fma) has infinite precision, +mul_adde has at worst the same precision of a multiply followed by an add. +This might be more efficient on architectures that do not have an fma instruction.

+

impl Simd<[f32; 16]>[src]

pub fn powf(self, x: Self) -> Self[src]

Raises self number to the floating point power of x.

+

impl Simd<[f32; 16]>[src]

pub fn recpre(self) -> Self[src]

Reciprocal estimate: ~= 1. / self.

+

FIXME: The precision of the estimate is currently unspecified.

+

impl Simd<[f32; 16]>[src]

pub fn rsqrte(self) -> Self[src]

Reciprocal square-root estimate: ~= 1. / self.sqrt().

+

FIXME: The precision of the estimate is currently unspecified.

+

impl Simd<[f32; 16]>[src]

pub fn sin(self) -> Self[src]

Sine.

+

pub fn sin_pi(self) -> Self[src]

Sine of self * PI.

+

pub fn sin_cos_pi(self) -> (Self, Self)[src]

Sine and cosine of self * PI.

+

impl Simd<[f32; 16]>[src]

pub fn sqrt(self) -> Self[src]

impl Simd<[f32; 16]>[src]

pub fn sqrte(self) -> Self[src]

Square-root estimate.

+

FIXME: The precision of the estimate is currently unspecified.

+

impl Simd<[f32; 16]>[src]

pub fn tanh(self) -> Self[src]

Tanh.

+

impl Simd<[f32; 16]>[src]

pub fn eq(self, other: Self) -> m32x16[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m32x16[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m32x16[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m32x16[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m32x16[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m32x16[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[m32; 16]>[src]

pub const fn new(
    x0: bool,
    x1: bool,
    x2: bool,
    x3: bool,
    x4: bool,
    x5: bool,
    x6: bool,
    x7: bool,
    x8: bool,
    x9: bool,
    x10: bool,
    x11: bool,
    x12: bool,
    x13: bool,
    x14: bool,
    x15: bool
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: bool) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> bool[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> bool[src]

Extracts the value at index.

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

impl Simd<[m32; 16]>[src]

pub fn and(self) -> bool[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> bool[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> bool[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[m32; 16]>[src]

pub fn all(self) -> bool[src]

Are all vector lanes true?

+

pub fn any(self) -> bool[src]

Is any vector lane true?

+

pub fn none(self) -> bool[src]

Are all vector lanes false?

+

impl Simd<[m32; 16]>[src]

pub fn eq(self, other: Self) -> m32x16[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m32x16[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m32x16[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m32x16[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m32x16[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m32x16[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[m32; 16]>[src]

pub fn select<T>(self, a: Simd<T>, b: Simd<T>) -> Simd<T> where
    T: SimdArray<NT = <[m32; 16] as SimdArray>::NT>, [src]

Selects elements of a and b using mask.

+

The lanes of the result for which the mask is true contain +the values of a. The remaining lanes contain the values of +b.

+

impl Simd<[m32; 16]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<m32x16>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[m32; 16]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<m32x16>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[m32; 16]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[m32; 16]>[src]

pub fn bitmask(self) -> u16[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[i64; 8]>[src]

pub const fn new(
    x0: i64,
    x1: i64,
    x2: i64,
    x3: i64,
    x4: i64,
    x5: i64,
    x6: i64,
    x7: i64
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: i64) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> i64[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> i64[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: i64) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: i64) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[i64; 8]>[src]

pub fn rotate_left(self, n: i64x8) -> i64x8[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: i64x8) -> i64x8[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl Simd<[i64; 8]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[i64; 8]>[src]

pub fn wrapping_sum(self) -> i64[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> i64[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl Simd<[i64; 8]>[src]

pub fn max_element(self) -> i64[src]

Largest vector element value.

+

pub fn min_element(self) -> i64[src]

Smallest vector element value.

+

impl Simd<[i64; 8]>[src]

pub fn and(self) -> i64[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> i64[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> i64[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[i64; 8]>[src]

pub fn from_slice_aligned(slice: &[i64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[i64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[i64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[i64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[i64; 8]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [i64])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [i64])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [i64])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [i64])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[i64; 8]>[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl Simd<[i64; 8]>[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl Simd<[i64; 8]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[i64; 8]>[src]

pub fn eq(self, other: Self) -> m64x8[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m64x8[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m64x8[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m64x8[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m64x8[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m64x8[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[i64; 8]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<i64x8>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[i64; 8]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<i64x8>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[i64; 8]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[u64; 8]>[src]

pub const fn new(
    x0: u64,
    x1: u64,
    x2: u64,
    x3: u64,
    x4: u64,
    x5: u64,
    x6: u64,
    x7: u64
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: u64) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> u64[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> u64[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: u64) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: u64) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[u64; 8]>[src]

pub fn rotate_left(self, n: u64x8) -> u64x8[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: u64x8) -> u64x8[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl Simd<[u64; 8]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[u64; 8]>[src]

pub fn wrapping_sum(self) -> u64[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> u64[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl Simd<[u64; 8]>[src]

pub fn max_element(self) -> u64[src]

Largest vector element value.

+

pub fn min_element(self) -> u64[src]

Smallest vector element value.

+

impl Simd<[u64; 8]>[src]

pub fn and(self) -> u64[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> u64[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> u64[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[u64; 8]>[src]

pub fn from_slice_aligned(slice: &[u64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[u64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[u64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[u64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[u64; 8]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [u64])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [u64])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [u64])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [u64])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[u64; 8]>[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl Simd<[u64; 8]>[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl Simd<[u64; 8]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[u64; 8]>[src]

pub fn eq(self, other: Self) -> m64x8[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m64x8[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m64x8[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m64x8[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m64x8[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m64x8[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[u64; 8]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<u64x8>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[u64; 8]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<u64x8>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[u64; 8]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[f64; 8]>[src]

pub const fn new(
    x0: f64,
    x1: f64,
    x2: f64,
    x3: f64,
    x4: f64,
    x5: f64,
    x6: f64,
    x7: f64
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: f64) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> f64[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> f64[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: f64) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: f64) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[f64; 8]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[f64; 8]>[src]

pub fn sum(self) -> f64[src]

Horizontal sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If one of the vector element is NaN the reduction returns +NaN. The resulting NaN is not required to be equal to any +of the NaNs in the vector.

+

pub fn product(self) -> f64[src]

Horizontal product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If one of the vector element is NaN the reduction returns +NaN. The resulting NaN is not required to be equal to any +of the NaNs in the vector.

+

impl Simd<[f64; 8]>[src]

pub fn max_element(self) -> f64[src]

Largest vector element value.

+

pub fn min_element(self) -> f64[src]

Smallest vector element value.

+

impl Simd<[f64; 8]>[src]

pub fn from_slice_aligned(slice: &[f64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[f64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[f64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[f64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[f64; 8]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [f64])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [f64])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [f64])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [f64])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[f64; 8]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[f64; 8]>[src]

pub const EPSILON: f64x8[src]

Machine epsilon value.

+

pub const MIN: f64x8[src]

Smallest finite value.

+

pub const MIN_POSITIVE: f64x8[src]

Smallest positive normal value.

+

pub const MAX: f64x8[src]

Largest finite value.

+

pub const NAN: f64x8[src]

Not a Number (NaN).

+

pub const INFINITY: f64x8[src]

Infinity (∞).

+

pub const NEG_INFINITY: f64x8[src]

Negative infinity (-∞).

+

pub const PI: f64x8[src]

Archimedes' constant (π)

+

pub const FRAC_PI_2: f64x8[src]

π/2

+

pub const FRAC_PI_3: f64x8[src]

π/3

+

pub const FRAC_PI_4: f64x8[src]

π/4

+

pub const FRAC_PI_6: f64x8[src]

π/6

+

pub const FRAC_PI_8: f64x8[src]

π/8

+

pub const FRAC_1_PI: f64x8[src]

1/π

+

pub const FRAC_2_PI: f64x8[src]

2/π

+

pub const FRAC_2_SQRT_PI: f64x8[src]

2/sqrt(π)

+

pub const SQRT_2: f64x8[src]

sqrt(2)

+

pub const FRAC_1_SQRT_2: f64x8[src]

1/sqrt(2)

+

pub const E: f64x8[src]

Euler's number (e)

+

pub const LOG2_E: f64x8[src]

log2(e)

+

pub const LOG10_E: f64x8[src]

log10(e)

+

pub const LN_2: f64x8[src]

ln(2)

+

pub const LN_10: f64x8[src]

ln(10)

+

impl Simd<[f64; 8]>[src]

pub fn is_nan(self) -> m64x8[src]

pub fn is_infinite(self) -> m64x8[src]

pub fn is_finite(self) -> m64x8[src]

impl Simd<[f64; 8]>[src]

pub fn abs(self) -> Self[src]

Absolute value.

+

impl Simd<[f64; 8]>[src]

pub fn cos(self) -> Self[src]

Cosine.

+

pub fn cos_pi(self) -> Self[src]

Cosine of self * PI.

+

impl Simd<[f64; 8]>[src]

pub fn exp(self) -> Self[src]

Returns the exponential function of self: e^(self).

+

impl Simd<[f64; 8]>[src]

pub fn ln(self) -> Self[src]

Returns the natural logarithm of self.

+

impl Simd<[f64; 8]>[src]

pub fn mul_add(self, y: Self, z: Self) -> Self[src]

Fused multiply add: self * y + z

+

impl Simd<[f64; 8]>[src]

pub fn mul_adde(self, y: Self, z: Self) -> Self[src]

Fused multiply add estimate: ~= self * y + z

+

While fused multiply-add (fma) has infinite precision, +mul_adde has at worst the same precision of a multiply followed by an add. +This might be more efficient on architectures that do not have an fma instruction.

+

impl Simd<[f64; 8]>[src]

pub fn powf(self, x: Self) -> Self[src]

Raises self number to the floating point power of x.

+

impl Simd<[f64; 8]>[src]

pub fn recpre(self) -> Self[src]

Reciprocal estimate: ~= 1. / self.

+

FIXME: The precision of the estimate is currently unspecified.

+

impl Simd<[f64; 8]>[src]

pub fn rsqrte(self) -> Self[src]

Reciprocal square-root estimate: ~= 1. / self.sqrt().

+

FIXME: The precision of the estimate is currently unspecified.

+

impl Simd<[f64; 8]>[src]

pub fn sin(self) -> Self[src]

Sine.

+

pub fn sin_pi(self) -> Self[src]

Sine of self * PI.

+

pub fn sin_cos_pi(self) -> (Self, Self)[src]

Sine and cosine of self * PI.

+

impl Simd<[f64; 8]>[src]

pub fn sqrt(self) -> Self[src]

impl Simd<[f64; 8]>[src]

pub fn sqrte(self) -> Self[src]

Square-root estimate.

+

FIXME: The precision of the estimate is currently unspecified.

+

impl Simd<[f64; 8]>[src]

pub fn tanh(self) -> Self[src]

Tanh.

+

impl Simd<[f64; 8]>[src]

pub fn eq(self, other: Self) -> m64x8[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m64x8[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m64x8[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m64x8[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m64x8[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m64x8[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[m64; 8]>[src]

pub const fn new(
    x0: bool,
    x1: bool,
    x2: bool,
    x3: bool,
    x4: bool,
    x5: bool,
    x6: bool,
    x7: bool
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: bool) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> bool[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> bool[src]

Extracts the value at index.

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

impl Simd<[m64; 8]>[src]

pub fn and(self) -> bool[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> bool[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> bool[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[m64; 8]>[src]

pub fn all(self) -> bool[src]

Are all vector lanes true?

+

pub fn any(self) -> bool[src]

Is any vector lane true?

+

pub fn none(self) -> bool[src]

Are all vector lanes false?

+

impl Simd<[m64; 8]>[src]

pub fn eq(self, other: Self) -> m64x8[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m64x8[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m64x8[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m64x8[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m64x8[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m64x8[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[m64; 8]>[src]

pub fn select<T>(self, a: Simd<T>, b: Simd<T>) -> Simd<T> where
    T: SimdArray<NT = <[m64; 8] as SimdArray>::NT>, [src]

Selects elements of a and b using mask.

+

The lanes of the result for which the mask is true contain +the values of a. The remaining lanes contain the values of +b.

+

impl Simd<[m64; 8]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<m64x8>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[m64; 8]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<m64x8>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[m64; 8]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[m64; 8]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[i128; 4]>[src]

pub const fn new(x0: i128, x1: i128, x2: i128, x3: i128) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: i128) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> i128[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> i128[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: i128) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: i128) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[i128; 4]>[src]

pub fn rotate_left(self, n: i128x4) -> i128x4[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: i128x4) -> i128x4[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl Simd<[i128; 4]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[i128; 4]>[src]

pub fn wrapping_sum(self) -> i128[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> i128[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl Simd<[i128; 4]>[src]

pub fn max_element(self) -> i128[src]

Largest vector element value.

+

pub fn min_element(self) -> i128[src]

Smallest vector element value.

+

impl Simd<[i128; 4]>[src]

pub fn and(self) -> i128[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> i128[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> i128[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[i128; 4]>[src]

pub fn from_slice_aligned(slice: &[i128]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[i128]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[i128]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[i128]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[i128; 4]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [i128])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [i128])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [i128])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [i128])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[i128; 4]>[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl Simd<[i128; 4]>[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl Simd<[i128; 4]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[i128; 4]>[src]

pub fn eq(self, other: Self) -> m128x4[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m128x4[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m128x4[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m128x4[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m128x4[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m128x4[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[i128; 4]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<i128x4>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[i128; 4]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<i128x4>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[i128; 4]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[u128; 4]>[src]

pub const fn new(x0: u128, x1: u128, x2: u128, x3: u128) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: u128) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> u128[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> u128[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: u128) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: u128) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[u128; 4]>[src]

pub fn rotate_left(self, n: u128x4) -> u128x4[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: u128x4) -> u128x4[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl Simd<[u128; 4]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[u128; 4]>[src]

pub fn wrapping_sum(self) -> u128[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> u128[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl Simd<[u128; 4]>[src]

pub fn max_element(self) -> u128[src]

Largest vector element value.

+

pub fn min_element(self) -> u128[src]

Smallest vector element value.

+

impl Simd<[u128; 4]>[src]

pub fn and(self) -> u128[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> u128[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> u128[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[u128; 4]>[src]

pub fn from_slice_aligned(slice: &[u128]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[u128]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[u128]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[u128]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[u128; 4]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [u128])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [u128])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [u128])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [u128])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[u128; 4]>[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl Simd<[u128; 4]>[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl Simd<[u128; 4]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[u128; 4]>[src]

pub fn eq(self, other: Self) -> m128x4[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m128x4[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m128x4[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m128x4[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m128x4[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m128x4[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[u128; 4]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<u128x4>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[u128; 4]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<u128x4>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[u128; 4]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[m128; 4]>[src]

pub const fn new(x0: bool, x1: bool, x2: bool, x3: bool) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: bool) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> bool[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> bool[src]

Extracts the value at index.

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

impl Simd<[m128; 4]>[src]

pub fn and(self) -> bool[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> bool[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> bool[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[m128; 4]>[src]

pub fn all(self) -> bool[src]

Are all vector lanes true?

+

pub fn any(self) -> bool[src]

Is any vector lane true?

+

pub fn none(self) -> bool[src]

Are all vector lanes false?

+

impl Simd<[m128; 4]>[src]

pub fn eq(self, other: Self) -> m128x4[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m128x4[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m128x4[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m128x4[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m128x4[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m128x4[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[m128; 4]>[src]

pub fn select<T>(self, a: Simd<T>, b: Simd<T>) -> Simd<T> where
    T: SimdArray<NT = <[m128; 4] as SimdArray>::NT>, [src]

Selects elements of a and b using mask.

+

The lanes of the result for which the mask is true contain +the values of a. The remaining lanes contain the values of +b.

+

impl Simd<[m128; 4]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<m128x4>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[m128; 4]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<m128x4>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[m128; 4]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[m128; 4]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[isize; 2]>[src]

pub const fn new(x0: isize, x1: isize) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: isize) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> isize[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> isize[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: isize) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: isize) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[isize; 2]>[src]

pub fn rotate_left(self, n: isizex2) -> isizex2[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: isizex2) -> isizex2[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl Simd<[isize; 2]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[isize; 2]>[src]

pub fn wrapping_sum(self) -> isize[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> isize[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl Simd<[isize; 2]>[src]

pub fn max_element(self) -> isize[src]

Largest vector element value.

+

pub fn min_element(self) -> isize[src]

Smallest vector element value.

+

impl Simd<[isize; 2]>[src]

pub fn and(self) -> isize[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> isize[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> isize[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[isize; 2]>[src]

pub fn from_slice_aligned(slice: &[isize]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[isize]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[isize]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[isize]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[isize; 2]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [isize])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [isize])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [isize])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [isize])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[isize; 2]>[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl Simd<[isize; 2]>[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl Simd<[isize; 2]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[isize; 2]>[src]

pub fn eq(self, other: Self) -> msizex2[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> msizex2[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> msizex2[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> msizex2[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> msizex2[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> msizex2[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[isize; 2]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<isizex2>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[isize; 2]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<isizex2>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[isize; 2]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[usize; 2]>[src]

pub const fn new(x0: usize, x1: usize) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: usize) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> usize[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> usize[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: usize) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: usize) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[usize; 2]>[src]

pub fn rotate_left(self, n: usizex2) -> usizex2[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: usizex2) -> usizex2[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl Simd<[usize; 2]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[usize; 2]>[src]

pub fn wrapping_sum(self) -> usize[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> usize[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl Simd<[usize; 2]>[src]

pub fn max_element(self) -> usize[src]

Largest vector element value.

+

pub fn min_element(self) -> usize[src]

Smallest vector element value.

+

impl Simd<[usize; 2]>[src]

pub fn and(self) -> usize[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> usize[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> usize[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[usize; 2]>[src]

pub fn from_slice_aligned(slice: &[usize]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[usize]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[usize]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[usize]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[usize; 2]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [usize])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [usize])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [usize])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [usize])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[usize; 2]>[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl Simd<[usize; 2]>[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl Simd<[usize; 2]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[usize; 2]>[src]

pub fn eq(self, other: Self) -> msizex2[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> msizex2[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> msizex2[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> msizex2[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> msizex2[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> msizex2[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[usize; 2]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<usizex2>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[usize; 2]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<usizex2>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[usize; 2]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[msize; 2]>[src]

pub const fn new(x0: bool, x1: bool) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: bool) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> bool[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> bool[src]

Extracts the value at index.

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

impl Simd<[msize; 2]>[src]

pub fn and(self) -> bool[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> bool[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> bool[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[msize; 2]>[src]

pub fn all(self) -> bool[src]

Are all vector lanes true?

+

pub fn any(self) -> bool[src]

Is any vector lane true?

+

pub fn none(self) -> bool[src]

Are all vector lanes false?

+

impl Simd<[msize; 2]>[src]

pub fn eq(self, other: Self) -> msizex2[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> msizex2[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> msizex2[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> msizex2[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> msizex2[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> msizex2[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[msize; 2]>[src]

pub fn select<T>(self, a: Simd<T>, b: Simd<T>) -> Simd<T> where
    T: SimdArray<NT = <[msize; 2] as SimdArray>::NT>, [src]

Selects elements of a and b using mask.

+

The lanes of the result for which the mask is true contain +the values of a. The remaining lanes contain the values of +b.

+

impl Simd<[msize; 2]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<msizex2>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[msize; 2]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<msizex2>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[msize; 2]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[msize; 2]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[isize; 4]>[src]

pub const fn new(x0: isize, x1: isize, x2: isize, x3: isize) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: isize) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> isize[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> isize[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: isize) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: isize) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[isize; 4]>[src]

pub fn rotate_left(self, n: isizex4) -> isizex4[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: isizex4) -> isizex4[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl Simd<[isize; 4]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[isize; 4]>[src]

pub fn wrapping_sum(self) -> isize[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> isize[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl Simd<[isize; 4]>[src]

pub fn max_element(self) -> isize[src]

Largest vector element value.

+

pub fn min_element(self) -> isize[src]

Smallest vector element value.

+

impl Simd<[isize; 4]>[src]

pub fn and(self) -> isize[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> isize[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> isize[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[isize; 4]>[src]

pub fn from_slice_aligned(slice: &[isize]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[isize]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[isize]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[isize]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[isize; 4]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [isize])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [isize])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [isize])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [isize])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[isize; 4]>[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl Simd<[isize; 4]>[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl Simd<[isize; 4]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[isize; 4]>[src]

pub fn eq(self, other: Self) -> msizex4[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> msizex4[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> msizex4[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> msizex4[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> msizex4[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> msizex4[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[isize; 4]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<isizex4>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[isize; 4]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<isizex4>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[isize; 4]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[usize; 4]>[src]

pub const fn new(x0: usize, x1: usize, x2: usize, x3: usize) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: usize) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> usize[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> usize[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: usize) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: usize) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[usize; 4]>[src]

pub fn rotate_left(self, n: usizex4) -> usizex4[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: usizex4) -> usizex4[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl Simd<[usize; 4]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[usize; 4]>[src]

pub fn wrapping_sum(self) -> usize[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> usize[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl Simd<[usize; 4]>[src]

pub fn max_element(self) -> usize[src]

Largest vector element value.

+

pub fn min_element(self) -> usize[src]

Smallest vector element value.

+

impl Simd<[usize; 4]>[src]

pub fn and(self) -> usize[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> usize[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> usize[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[usize; 4]>[src]

pub fn from_slice_aligned(slice: &[usize]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[usize]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[usize]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[usize]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[usize; 4]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [usize])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [usize])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [usize])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [usize])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[usize; 4]>[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl Simd<[usize; 4]>[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl Simd<[usize; 4]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[usize; 4]>[src]

pub fn eq(self, other: Self) -> msizex4[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> msizex4[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> msizex4[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> msizex4[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> msizex4[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> msizex4[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[usize; 4]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<usizex4>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[usize; 4]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<usizex4>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[usize; 4]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[msize; 4]>[src]

pub const fn new(x0: bool, x1: bool, x2: bool, x3: bool) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: bool) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> bool[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> bool[src]

Extracts the value at index.

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

impl Simd<[msize; 4]>[src]

pub fn and(self) -> bool[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> bool[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> bool[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[msize; 4]>[src]

pub fn all(self) -> bool[src]

Are all vector lanes true?

+

pub fn any(self) -> bool[src]

Is any vector lane true?

+

pub fn none(self) -> bool[src]

Are all vector lanes false?

+

impl Simd<[msize; 4]>[src]

pub fn eq(self, other: Self) -> msizex4[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> msizex4[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> msizex4[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> msizex4[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> msizex4[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> msizex4[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[msize; 4]>[src]

pub fn select<T>(self, a: Simd<T>, b: Simd<T>) -> Simd<T> where
    T: SimdArray<NT = <[msize; 4] as SimdArray>::NT>, [src]

Selects elements of a and b using mask.

+

The lanes of the result for which the mask is true contain +the values of a. The remaining lanes contain the values of +b.

+

impl Simd<[msize; 4]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<msizex4>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[msize; 4]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<msizex4>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[msize; 4]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[msize; 4]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[isize; 8]>[src]

pub const fn new(
    x0: isize,
    x1: isize,
    x2: isize,
    x3: isize,
    x4: isize,
    x5: isize,
    x6: isize,
    x7: isize
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: isize) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> isize[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> isize[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: isize) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: isize) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[isize; 8]>[src]

pub fn rotate_left(self, n: isizex8) -> isizex8[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: isizex8) -> isizex8[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl Simd<[isize; 8]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[isize; 8]>[src]

pub fn wrapping_sum(self) -> isize[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> isize[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl Simd<[isize; 8]>[src]

pub fn max_element(self) -> isize[src]

Largest vector element value.

+

pub fn min_element(self) -> isize[src]

Smallest vector element value.

+

impl Simd<[isize; 8]>[src]

pub fn and(self) -> isize[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> isize[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> isize[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[isize; 8]>[src]

pub fn from_slice_aligned(slice: &[isize]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[isize]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[isize]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[isize]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[isize; 8]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [isize])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [isize])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [isize])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [isize])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[isize; 8]>[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl Simd<[isize; 8]>[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl Simd<[isize; 8]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[isize; 8]>[src]

pub fn eq(self, other: Self) -> msizex8[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> msizex8[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> msizex8[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> msizex8[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> msizex8[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> msizex8[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[isize; 8]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<isizex8>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[isize; 8]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<isizex8>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[isize; 8]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[usize; 8]>[src]

pub const fn new(
    x0: usize,
    x1: usize,
    x2: usize,
    x3: usize,
    x4: usize,
    x5: usize,
    x6: usize,
    x7: usize
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: usize) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> usize[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> usize[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: usize) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: usize) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl Simd<[usize; 8]>[src]

pub fn rotate_left(self, n: usizex8) -> usizex8[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: usizex8) -> usizex8[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl Simd<[usize; 8]>[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl Simd<[usize; 8]>[src]

pub fn wrapping_sum(self) -> usize[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> usize[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl Simd<[usize; 8]>[src]

pub fn max_element(self) -> usize[src]

Largest vector element value.

+

pub fn min_element(self) -> usize[src]

Smallest vector element value.

+

impl Simd<[usize; 8]>[src]

pub fn and(self) -> usize[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> usize[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> usize[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[usize; 8]>[src]

pub fn from_slice_aligned(slice: &[usize]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[usize]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[usize]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[usize]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[usize; 8]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [usize])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [usize])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [usize])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [usize])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl Simd<[usize; 8]>[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl Simd<[usize; 8]>[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl Simd<[usize; 8]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[usize; 8]>[src]

pub fn eq(self, other: Self) -> msizex8[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> msizex8[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> msizex8[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> msizex8[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> msizex8[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> msizex8[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[usize; 8]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<usizex8>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[usize; 8]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<usizex8>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[usize; 8]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl Simd<[msize; 8]>[src]

pub const fn new(
    x0: bool,
    x1: bool,
    x2: bool,
    x3: bool,
    x4: bool,
    x5: bool,
    x6: bool,
    x7: bool
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: bool) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> bool[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> bool[src]

Extracts the value at index.

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

impl Simd<[msize; 8]>[src]

pub fn and(self) -> bool[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> bool[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> bool[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl Simd<[msize; 8]>[src]

pub fn all(self) -> bool[src]

Are all vector lanes true?

+

pub fn any(self) -> bool[src]

Is any vector lane true?

+

pub fn none(self) -> bool[src]

Are all vector lanes false?

+

impl Simd<[msize; 8]>[src]

pub fn eq(self, other: Self) -> msizex8[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> msizex8[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> msizex8[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> msizex8[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> msizex8[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> msizex8[src]

Lane-wise greater-than-or-equals comparison.

+

impl Simd<[msize; 8]>[src]

pub fn select<T>(self, a: Simd<T>, b: Simd<T>) -> Simd<T> where
    T: SimdArray<NT = <[msize; 8] as SimdArray>::NT>, [src]

Selects elements of a and b using mask.

+

The lanes of the result for which the mask is true contain +the values of a. The remaining lanes contain the values of +b.

+

impl Simd<[msize; 8]>[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<msizex8>[src]

Returns a wrapper that implements PartialOrd.

+

impl Simd<[msize; 8]>[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<msizex8>[src]

Returns a wrapper that implements Ord.

+

impl Simd<[msize; 8]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl Simd<[msize; 8]>[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

impl<T> Simd<[*const T; 2]>[src]

pub const fn new(x0: *const T, x1: *const T) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: *const T) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub const fn null() -> Self[src]

Constructs a new instance with each element initialized to +null.

+

pub fn is_null(self) -> msizex2[src]

Returns a mask that selects those lanes that contain null +pointers.

+

pub fn extract(self, index: usize) -> *const T[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> *const T[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: *const T) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: *const T) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl<T> Simd<[*const T; 2]>[src]

pub fn eq(self, other: Self) -> msizex2[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> msizex2[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> msizex2[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> msizex2[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> msizex2[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> msizex2[src]

Lane-wise greater-than-or-equals comparison.

+

impl<T> Simd<[*const T; 2]>[src]

pub fn from_slice_aligned(slice: &[*const T]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[*const T]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[*const T]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[*const T]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl<T> Simd<[*const T; 2]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [*const T])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [*const T])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [*const T])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [*const T])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl<T> Simd<[*const T; 2]>[src]

pub unsafe fn offset(self, count: isizex2) -> Self[src]

Calculates the offset from a pointer.

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

If any of the following conditions are violated, the result is +Undefined Behavior:

+
    +
  • +

    Both the starting and resulting pointer must be either in +bounds or one byte past the end of an allocated object.

    +
    • +
  • +

    The computed offset, in bytes, cannot overflow an isize.

    +
    • +
  • +

    The offset being in bounds cannot rely on "wrapping around" +the address space. That is, the infinite-precision sum, in bytes +must fit in a usize.

    +
    • +
+

The compiler and standard library generally tries to ensure +allocations never reach a size where an offset is a concern. For +instance, Vec and Box ensure they never allocate more than +isize::MAX bytes, so vec.as_ptr().offset(vec.len() as isize) +is always safe.

+

Most platforms fundamentally can't even construct such an +allocation. For instance, no known 64-bit platform can ever +serve a request for 263 bytes due to page-table limitations or +splitting the address space. However, some 32-bit and 16-bit +platforms may successfully serve a request for more than +isize::MAX bytes with things like Physical Address Extension. +As such, memory acquired directly from allocators or memory +mapped files may be too large to handle with this function.

+

Consider using wrapping_offset instead if these constraints +are difficult to satisfy. The only advantage of this method is +that it enables more aggressive compiler optimizations.

+

pub fn wrapping_offset(self, count: isizex2) -> Self[src]

Calculates the offset from a pointer using wrapping arithmetic.

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

The resulting pointer does not need to be in bounds, but it is +potentially hazardous to dereference (which requires unsafe).

+

Always use .offset(count) instead when possible, because +offset allows the compiler to optimize better.

+

pub unsafe fn offset_from(self, origin: Self) -> isizex2[src]

Calculates the distance between two pointers.

+

The returned value is in units of T: the distance in bytes is +divided by mem::size_of::<T>().

+

This function is the inverse of offset.

+

Safety

+

If any of the following conditions are violated, the result is +Undefined Behavior:

+
    +
  • +

    Both the starting and other pointer must be either in bounds +or one byte past the end of the same allocated object.

    +
    • +
  • +

    The distance between the pointers, in bytes, cannot overflow +an isize.

    +
    • +
  • +

    The distance between the pointers, in bytes, must be an exact +multiple of the size of T.

    +
    • +
  • +

    The distance being in bounds cannot rely on "wrapping around" +the address space.

    +
    • +
+

The compiler and standard library generally try to ensure +allocations never reach a size where an offset is a concern. For +instance, Vec and Box ensure they never allocate more than +isize::MAX bytes, so ptr_into_vec.offset_from(vec.as_ptr()) +is always safe.

+

Most platforms fundamentally can't even construct such an +allocation. For instance, no known 64-bit platform can ever +serve a request for 263 bytes due to page-table limitations or +splitting the address space. However, some 32-bit and 16-bit +platforms may successfully serve a request for more than +isize::MAX bytes with things like Physical Address Extension. +As such, memory acquired directly from allocators or memory +mapped files may be too large to handle with this function.

+

Consider using wrapping_offset_from instead if these constraints +are difficult to satisfy. The only advantage of this method is +that it enables more aggressive compiler optimizations.

+

pub fn wrapping_offset_from(self, origin: Self) -> isizex2[src]

Calculates the distance between two pointers.

+

The returned value is in units of T: the distance in bytes is +divided by mem::size_of::<T>().

+

If the address different between the two pointers is not a +multiple of mem::size_of::<T>() then the result of the +division is rounded towards zero.

+

Though this method is safe for any two pointers, note that its +result will be mostly useless if the two pointers aren't into +the same allocated object, for example if they point to two +different local variables.

+

pub unsafe fn add(self, count: usizex2) -> Self[src]

Calculates the offset from a pointer (convenience for +.offset(count as isize)).

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

If any of the following conditions are violated, the result is +Undefined Behavior:

+
    +
  • +

    Both the starting and resulting pointer must be either in +bounds or one byte past the end of an allocated object.

    +
    • +
  • +

    The computed offset, in bytes, cannot overflow an isize.

    +
    • +
  • +

    The offset being in bounds cannot rely on "wrapping around" +the address space. That is, the infinite-precision sum must fit +in a usize.

    +
    • +
+

The compiler and standard library generally tries to ensure +allocations never reach a size where an offset is a concern. For +instance, Vec and Box ensure they never allocate more than +isize::MAX bytes, so vec.as_ptr().add(vec.len()) is always +safe.

+

Most platforms fundamentally can't even construct such an +allocation. For instance, no known 64-bit platform can ever +serve a request for 263 bytes due to page-table limitations or +splitting the address space. However, some 32-bit and 16-bit +platforms may successfully serve a request for more than +isize::MAX bytes with things like Physical Address Extension. +As such, memory acquired directly from allocators or memory +mapped files may be too large to handle with this function.

+

Consider using wrapping_offset instead if these constraints +are difficult to satisfy. The only advantage of this method is +that it enables more aggressive compiler optimizations.

+

pub unsafe fn sub(self, count: usizex2) -> Self[src]

Calculates the offset from a pointer (convenience for +.offset((count as isize).wrapping_neg())).

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

If any of the following conditions are violated, the result is +Undefined Behavior:

+
    +
  • +

    Both the starting and resulting pointer must be either in +bounds or one byte past the end of an allocated object.

    +
    • +
  • +

    The computed offset cannot exceed isize::MAX bytes.

    +
    • +
  • +

    The offset being in bounds cannot rely on "wrapping around" +the address space. That is, the infinite-precision sum must fit +in a usize.

    +
    • +
+

The compiler and standard library generally tries to ensure +allocations never reach a size where an offset is a concern. For +instance, Vec and Box ensure they never allocate more than +isize::MAX bytes, so +vec.as_ptr().add(vec.len()).sub(vec.len()) is always safe.

+

Most platforms fundamentally can't even construct such an +allocation. For instance, no known 64-bit platform can ever +serve a request for 263 bytes due to page-table +limitations or splitting the address space. However, some 32-bit +and 16-bit platforms may successfully serve a request for more +than isize::MAX bytes with things like Physical Address +Extension. As such, memory acquired directly from allocators or +memory mapped files may be too large to handle with this +function.

+

Consider using wrapping_offset instead if these constraints +are difficult to satisfy. The only advantage of this method is +that it enables more aggressive compiler optimizations.

+

pub fn wrapping_add(self, count: usizex2) -> Self[src]

Calculates the offset from a pointer using wrapping arithmetic. +(convenience for .wrapping_offset(count as isize))

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

The resulting pointer does not need to be in bounds, but it is +potentially hazardous to dereference (which requires unsafe).

+

Always use .add(count) instead when possible, because add +allows the compiler to optimize better.

+

pub fn wrapping_sub(self, count: usizex2) -> Self[src]

Calculates the offset from a pointer using wrapping arithmetic. +(convenience for .wrapping_offset((count as isize).wrapping_sub()))

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

The resulting pointer does not need to be in bounds, but it is +potentially hazardous to dereference (which requires unsafe).

+

Always use .sub(count) instead when possible, because sub +allows the compiler to optimize better.

+

impl<T> Simd<[*const T; 2]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl<T> Simd<[*const T; 2]> where
    [T; 2]: SimdArray, [src]

pub unsafe fn read<M>(
    self,
    mask: Simd<[M; 2]>,
    value: Simd<[T; 2]>
) -> Simd<[T; 2]> where
    M: Mask,
    [M; 2]: SimdArray, [src]

Reads selected vector elements from memory.

+

Instantiates a new vector by reading the values from self for +those lanes whose mask is true, and using the elements of +value otherwise.

+

No memory is accessed for those lanes of self whose mask is +false.

+

Safety

+

This method is unsafe because it dereferences raw pointers. The +pointers must be aligned to mem::align_of::<T>().

+

impl<T> Simd<[*mut T; 2]>[src]

pub const fn new(x0: *mut T, x1: *mut T) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: *mut T) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub const fn null() -> Self[src]

Constructs a new instance with each element initialized to +null.

+

pub fn is_null(self) -> msizex2[src]

Returns a mask that selects those lanes that contain null +pointers.

+

pub fn extract(self, index: usize) -> *mut T[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> *mut T[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: *mut T) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: *mut T) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl<T> Simd<[*mut T; 2]>[src]

pub fn eq(self, other: Self) -> msizex2[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> msizex2[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> msizex2[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> msizex2[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> msizex2[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> msizex2[src]

Lane-wise greater-than-or-equals comparison.

+

impl<T> Simd<[*mut T; 2]>[src]

pub fn from_slice_aligned(slice: &[*mut T]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[*mut T]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[*mut T]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[*mut T]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl<T> Simd<[*mut T; 2]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [*mut T])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [*mut T])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [*mut T])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [*mut T])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl<T> Simd<[*mut T; 2]>[src]

pub unsafe fn offset(self, count: isizex2) -> Self[src]

Calculates the offset from a pointer.

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

If any of the following conditions are violated, the result is +Undefined Behavior:

+
    +
  • +

    Both the starting and resulting pointer must be either in +bounds or one byte past the end of an allocated object.

    +
    • +
  • +

    The computed offset, in bytes, cannot overflow an isize.

    +
    • +
  • +

    The offset being in bounds cannot rely on "wrapping around" +the address space. That is, the infinite-precision sum, in bytes +must fit in a usize.

    +
    • +
+

The compiler and standard library generally tries to ensure +allocations never reach a size where an offset is a concern. For +instance, Vec and Box ensure they never allocate more than +isize::MAX bytes, so vec.as_ptr().offset(vec.len() as isize) +is always safe.

+

Most platforms fundamentally can't even construct such an +allocation. For instance, no known 64-bit platform can ever +serve a request for 263 bytes due to page-table limitations or +splitting the address space. However, some 32-bit and 16-bit +platforms may successfully serve a request for more than +isize::MAX bytes with things like Physical Address Extension. +As such, memory acquired directly from allocators or memory +mapped files may be too large to handle with this function.

+

Consider using wrapping_offset instead if these constraints +are difficult to satisfy. The only advantage of this method is +that it enables more aggressive compiler optimizations.

+

pub fn wrapping_offset(self, count: isizex2) -> Self[src]

Calculates the offset from a pointer using wrapping arithmetic.

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

The resulting pointer does not need to be in bounds, but it is +potentially hazardous to dereference (which requires unsafe).

+

Always use .offset(count) instead when possible, because +offset allows the compiler to optimize better.

+

pub unsafe fn offset_from(self, origin: Self) -> isizex2[src]

Calculates the distance between two pointers.

+

The returned value is in units of T: the distance in bytes is +divided by mem::size_of::<T>().

+

This function is the inverse of offset.

+

Safety

+

If any of the following conditions are violated, the result is +Undefined Behavior:

+
    +
  • +

    Both the starting and other pointer must be either in bounds +or one byte past the end of the same allocated object.

    +
    • +
  • +

    The distance between the pointers, in bytes, cannot overflow +an isize.

    +
    • +
  • +

    The distance between the pointers, in bytes, must be an exact +multiple of the size of T.

    +
    • +
  • +

    The distance being in bounds cannot rely on "wrapping around" +the address space.

    +
    • +
+

The compiler and standard library generally try to ensure +allocations never reach a size where an offset is a concern. For +instance, Vec and Box ensure they never allocate more than +isize::MAX bytes, so ptr_into_vec.offset_from(vec.as_ptr()) +is always safe.

+

Most platforms fundamentally can't even construct such an +allocation. For instance, no known 64-bit platform can ever +serve a request for 263 bytes due to page-table limitations or +splitting the address space. However, some 32-bit and 16-bit +platforms may successfully serve a request for more than +isize::MAX bytes with things like Physical Address Extension. +As such, memory acquired directly from allocators or memory +mapped files may be too large to handle with this function.

+

Consider using wrapping_offset_from instead if these constraints +are difficult to satisfy. The only advantage of this method is +that it enables more aggressive compiler optimizations.

+

pub fn wrapping_offset_from(self, origin: Self) -> isizex2[src]

Calculates the distance between two pointers.

+

The returned value is in units of T: the distance in bytes is +divided by mem::size_of::<T>().

+

If the address different between the two pointers is not a +multiple of mem::size_of::<T>() then the result of the +division is rounded towards zero.

+

Though this method is safe for any two pointers, note that its +result will be mostly useless if the two pointers aren't into +the same allocated object, for example if they point to two +different local variables.

+

pub unsafe fn add(self, count: usizex2) -> Self[src]

Calculates the offset from a pointer (convenience for +.offset(count as isize)).

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

If any of the following conditions are violated, the result is +Undefined Behavior:

+
    +
  • +

    Both the starting and resulting pointer must be either in +bounds or one byte past the end of an allocated object.

    +
    • +
  • +

    The computed offset, in bytes, cannot overflow an isize.

    +
    • +
  • +

    The offset being in bounds cannot rely on "wrapping around" +the address space. That is, the infinite-precision sum must fit +in a usize.

    +
    • +
+

The compiler and standard library generally tries to ensure +allocations never reach a size where an offset is a concern. For +instance, Vec and Box ensure they never allocate more than +isize::MAX bytes, so vec.as_ptr().add(vec.len()) is always +safe.

+

Most platforms fundamentally can't even construct such an +allocation. For instance, no known 64-bit platform can ever +serve a request for 263 bytes due to page-table limitations or +splitting the address space. However, some 32-bit and 16-bit +platforms may successfully serve a request for more than +isize::MAX bytes with things like Physical Address Extension. +As such, memory acquired directly from allocators or memory +mapped files may be too large to handle with this function.

+

Consider using wrapping_offset instead if these constraints +are difficult to satisfy. The only advantage of this method is +that it enables more aggressive compiler optimizations.

+

pub unsafe fn sub(self, count: usizex2) -> Self[src]

Calculates the offset from a pointer (convenience for +.offset((count as isize).wrapping_neg())).

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

If any of the following conditions are violated, the result is +Undefined Behavior:

+
    +
  • +

    Both the starting and resulting pointer must be either in +bounds or one byte past the end of an allocated object.

    +
    • +
  • +

    The computed offset cannot exceed isize::MAX bytes.

    +
    • +
  • +

    The offset being in bounds cannot rely on "wrapping around" +the address space. That is, the infinite-precision sum must fit +in a usize.

    +
    • +
+

The compiler and standard library generally tries to ensure +allocations never reach a size where an offset is a concern. For +instance, Vec and Box ensure they never allocate more than +isize::MAX bytes, so +vec.as_ptr().add(vec.len()).sub(vec.len()) is always safe.

+

Most platforms fundamentally can't even construct such an +allocation. For instance, no known 64-bit platform can ever +serve a request for 263 bytes due to page-table +limitations or splitting the address space. However, some 32-bit +and 16-bit platforms may successfully serve a request for more +than isize::MAX bytes with things like Physical Address +Extension. As such, memory acquired directly from allocators or +memory mapped files may be too large to handle with this +function.

+

Consider using wrapping_offset instead if these constraints +are difficult to satisfy. The only advantage of this method is +that it enables more aggressive compiler optimizations.

+

pub fn wrapping_add(self, count: usizex2) -> Self[src]

Calculates the offset from a pointer using wrapping arithmetic. +(convenience for .wrapping_offset(count as isize))

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

The resulting pointer does not need to be in bounds, but it is +potentially hazardous to dereference (which requires unsafe).

+

Always use .add(count) instead when possible, because add +allows the compiler to optimize better.

+

pub fn wrapping_sub(self, count: usizex2) -> Self[src]

Calculates the offset from a pointer using wrapping arithmetic. +(convenience for .wrapping_offset((count as isize).wrapping_sub()))

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

The resulting pointer does not need to be in bounds, but it is +potentially hazardous to dereference (which requires unsafe).

+

Always use .sub(count) instead when possible, because sub +allows the compiler to optimize better.

+

impl<T> Simd<[*mut T; 2]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl<T> Simd<[*mut T; 2]> where
    [T; 2]: SimdArray, [src]

pub unsafe fn read<M>(
    self,
    mask: Simd<[M; 2]>,
    value: Simd<[T; 2]>
) -> Simd<[T; 2]> where
    M: Mask,
    [M; 2]: SimdArray, [src]

Reads selected vector elements from memory.

+

Instantiates a new vector by reading the values from self for +those lanes whose mask is true, and using the elements of +value otherwise.

+

No memory is accessed for those lanes of self whose mask is +false.

+

Safety

+

This method is unsafe because it dereferences raw pointers. The +pointers must be aligned to mem::align_of::<T>().

+

impl<T> Simd<[*mut T; 2]> where
    [T; 2]: SimdArray, [src]

pub unsafe fn write<M>(self, mask: Simd<[M; 2]>, value: Simd<[T; 2]>) where
    M: Mask,
    [M; 2]: SimdArray, [src]

Writes selected vector elements to memory.

+

Writes the lanes of values for which the mask is true to +their corresponding memory addresses in self.

+

No memory is accessed for those lanes of self whose mask is +false.

+

Overlapping memory addresses of self are written to in order +from the lest-significant to the most-significant element.

+

Safety

+

This method is unsafe because it dereferences raw pointers. The +pointers must be aligned to mem::align_of::<T>().

+

impl<T> Simd<[*const T; 4]>[src]

pub const fn new(x0: *const T, x1: *const T, x2: *const T, x3: *const T) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: *const T) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub const fn null() -> Self[src]

Constructs a new instance with each element initialized to +null.

+

pub fn is_null(self) -> msizex4[src]

Returns a mask that selects those lanes that contain null +pointers.

+

pub fn extract(self, index: usize) -> *const T[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> *const T[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: *const T) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: *const T) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl<T> Simd<[*const T; 4]>[src]

pub fn eq(self, other: Self) -> msizex4[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> msizex4[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> msizex4[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> msizex4[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> msizex4[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> msizex4[src]

Lane-wise greater-than-or-equals comparison.

+

impl<T> Simd<[*const T; 4]>[src]

pub fn from_slice_aligned(slice: &[*const T]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[*const T]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[*const T]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[*const T]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl<T> Simd<[*const T; 4]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [*const T])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [*const T])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [*const T])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [*const T])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl<T> Simd<[*const T; 4]>[src]

pub unsafe fn offset(self, count: isizex4) -> Self[src]

Calculates the offset from a pointer.

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

If any of the following conditions are violated, the result is +Undefined Behavior:

+
    +
  • +

    Both the starting and resulting pointer must be either in +bounds or one byte past the end of an allocated object.

    +
    • +
  • +

    The computed offset, in bytes, cannot overflow an isize.

    +
    • +
  • +

    The offset being in bounds cannot rely on "wrapping around" +the address space. That is, the infinite-precision sum, in bytes +must fit in a usize.

    +
    • +
+

The compiler and standard library generally tries to ensure +allocations never reach a size where an offset is a concern. For +instance, Vec and Box ensure they never allocate more than +isize::MAX bytes, so vec.as_ptr().offset(vec.len() as isize) +is always safe.

+

Most platforms fundamentally can't even construct such an +allocation. For instance, no known 64-bit platform can ever +serve a request for 263 bytes due to page-table limitations or +splitting the address space. However, some 32-bit and 16-bit +platforms may successfully serve a request for more than +isize::MAX bytes with things like Physical Address Extension. +As such, memory acquired directly from allocators or memory +mapped files may be too large to handle with this function.

+

Consider using wrapping_offset instead if these constraints +are difficult to satisfy. The only advantage of this method is +that it enables more aggressive compiler optimizations.

+

pub fn wrapping_offset(self, count: isizex4) -> Self[src]

Calculates the offset from a pointer using wrapping arithmetic.

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

The resulting pointer does not need to be in bounds, but it is +potentially hazardous to dereference (which requires unsafe).

+

Always use .offset(count) instead when possible, because +offset allows the compiler to optimize better.

+

pub unsafe fn offset_from(self, origin: Self) -> isizex4[src]

Calculates the distance between two pointers.

+

The returned value is in units of T: the distance in bytes is +divided by mem::size_of::<T>().

+

This function is the inverse of offset.

+

Safety

+

If any of the following conditions are violated, the result is +Undefined Behavior:

+
    +
  • +

    Both the starting and other pointer must be either in bounds +or one byte past the end of the same allocated object.

    +
    • +
  • +

    The distance between the pointers, in bytes, cannot overflow +an isize.

    +
    • +
  • +

    The distance between the pointers, in bytes, must be an exact +multiple of the size of T.

    +
    • +
  • +

    The distance being in bounds cannot rely on "wrapping around" +the address space.

    +
    • +
+

The compiler and standard library generally try to ensure +allocations never reach a size where an offset is a concern. For +instance, Vec and Box ensure they never allocate more than +isize::MAX bytes, so ptr_into_vec.offset_from(vec.as_ptr()) +is always safe.

+

Most platforms fundamentally can't even construct such an +allocation. For instance, no known 64-bit platform can ever +serve a request for 263 bytes due to page-table limitations or +splitting the address space. However, some 32-bit and 16-bit +platforms may successfully serve a request for more than +isize::MAX bytes with things like Physical Address Extension. +As such, memory acquired directly from allocators or memory +mapped files may be too large to handle with this function.

+

Consider using wrapping_offset_from instead if these constraints +are difficult to satisfy. The only advantage of this method is +that it enables more aggressive compiler optimizations.

+

pub fn wrapping_offset_from(self, origin: Self) -> isizex4[src]

Calculates the distance between two pointers.

+

The returned value is in units of T: the distance in bytes is +divided by mem::size_of::<T>().

+

If the address different between the two pointers is not a +multiple of mem::size_of::<T>() then the result of the +division is rounded towards zero.

+

Though this method is safe for any two pointers, note that its +result will be mostly useless if the two pointers aren't into +the same allocated object, for example if they point to two +different local variables.

+

pub unsafe fn add(self, count: usizex4) -> Self[src]

Calculates the offset from a pointer (convenience for +.offset(count as isize)).

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

If any of the following conditions are violated, the result is +Undefined Behavior:

+
    +
  • +

    Both the starting and resulting pointer must be either in +bounds or one byte past the end of an allocated object.

    +
    • +
  • +

    The computed offset, in bytes, cannot overflow an isize.

    +
    • +
  • +

    The offset being in bounds cannot rely on "wrapping around" +the address space. That is, the infinite-precision sum must fit +in a usize.

    +
    • +
+

The compiler and standard library generally tries to ensure +allocations never reach a size where an offset is a concern. For +instance, Vec and Box ensure they never allocate more than +isize::MAX bytes, so vec.as_ptr().add(vec.len()) is always +safe.

+

Most platforms fundamentally can't even construct such an +allocation. For instance, no known 64-bit platform can ever +serve a request for 263 bytes due to page-table limitations or +splitting the address space. However, some 32-bit and 16-bit +platforms may successfully serve a request for more than +isize::MAX bytes with things like Physical Address Extension. +As such, memory acquired directly from allocators or memory +mapped files may be too large to handle with this function.

+

Consider using wrapping_offset instead if these constraints +are difficult to satisfy. The only advantage of this method is +that it enables more aggressive compiler optimizations.

+

pub unsafe fn sub(self, count: usizex4) -> Self[src]

Calculates the offset from a pointer (convenience for +.offset((count as isize).wrapping_neg())).

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

If any of the following conditions are violated, the result is +Undefined Behavior:

+
    +
  • +

    Both the starting and resulting pointer must be either in +bounds or one byte past the end of an allocated object.

    +
    • +
  • +

    The computed offset cannot exceed isize::MAX bytes.

    +
    • +
  • +

    The offset being in bounds cannot rely on "wrapping around" +the address space. That is, the infinite-precision sum must fit +in a usize.

    +
    • +
+

The compiler and standard library generally tries to ensure +allocations never reach a size where an offset is a concern. For +instance, Vec and Box ensure they never allocate more than +isize::MAX bytes, so +vec.as_ptr().add(vec.len()).sub(vec.len()) is always safe.

+

Most platforms fundamentally can't even construct such an +allocation. For instance, no known 64-bit platform can ever +serve a request for 263 bytes due to page-table +limitations or splitting the address space. However, some 32-bit +and 16-bit platforms may successfully serve a request for more +than isize::MAX bytes with things like Physical Address +Extension. As such, memory acquired directly from allocators or +memory mapped files may be too large to handle with this +function.

+

Consider using wrapping_offset instead if these constraints +are difficult to satisfy. The only advantage of this method is +that it enables more aggressive compiler optimizations.

+

pub fn wrapping_add(self, count: usizex4) -> Self[src]

Calculates the offset from a pointer using wrapping arithmetic. +(convenience for .wrapping_offset(count as isize))

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

The resulting pointer does not need to be in bounds, but it is +potentially hazardous to dereference (which requires unsafe).

+

Always use .add(count) instead when possible, because add +allows the compiler to optimize better.

+

pub fn wrapping_sub(self, count: usizex4) -> Self[src]

Calculates the offset from a pointer using wrapping arithmetic. +(convenience for .wrapping_offset((count as isize).wrapping_sub()))

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

The resulting pointer does not need to be in bounds, but it is +potentially hazardous to dereference (which requires unsafe).

+

Always use .sub(count) instead when possible, because sub +allows the compiler to optimize better.

+

impl<T> Simd<[*const T; 4]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl<T> Simd<[*const T; 4]> where
    [T; 4]: SimdArray, [src]

pub unsafe fn read<M>(
    self,
    mask: Simd<[M; 4]>,
    value: Simd<[T; 4]>
) -> Simd<[T; 4]> where
    M: Mask,
    [M; 4]: SimdArray, [src]

Reads selected vector elements from memory.

+

Instantiates a new vector by reading the values from self for +those lanes whose mask is true, and using the elements of +value otherwise.

+

No memory is accessed for those lanes of self whose mask is +false.

+

Safety

+

This method is unsafe because it dereferences raw pointers. The +pointers must be aligned to mem::align_of::<T>().

+

impl<T> Simd<[*mut T; 4]>[src]

pub const fn new(x0: *mut T, x1: *mut T, x2: *mut T, x3: *mut T) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: *mut T) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub const fn null() -> Self[src]

Constructs a new instance with each element initialized to +null.

+

pub fn is_null(self) -> msizex4[src]

Returns a mask that selects those lanes that contain null +pointers.

+

pub fn extract(self, index: usize) -> *mut T[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> *mut T[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: *mut T) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: *mut T) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl<T> Simd<[*mut T; 4]>[src]

pub fn eq(self, other: Self) -> msizex4[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> msizex4[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> msizex4[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> msizex4[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> msizex4[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> msizex4[src]

Lane-wise greater-than-or-equals comparison.

+

impl<T> Simd<[*mut T; 4]>[src]

pub fn from_slice_aligned(slice: &[*mut T]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[*mut T]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[*mut T]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[*mut T]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl<T> Simd<[*mut T; 4]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [*mut T])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [*mut T])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [*mut T])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [*mut T])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl<T> Simd<[*mut T; 4]>[src]

pub unsafe fn offset(self, count: isizex4) -> Self[src]

Calculates the offset from a pointer.

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

If any of the following conditions are violated, the result is +Undefined Behavior:

+
    +
  • +

    Both the starting and resulting pointer must be either in +bounds or one byte past the end of an allocated object.

    +
    • +
  • +

    The computed offset, in bytes, cannot overflow an isize.

    +
    • +
  • +

    The offset being in bounds cannot rely on "wrapping around" +the address space. That is, the infinite-precision sum, in bytes +must fit in a usize.

    +
    • +
+

The compiler and standard library generally tries to ensure +allocations never reach a size where an offset is a concern. For +instance, Vec and Box ensure they never allocate more than +isize::MAX bytes, so vec.as_ptr().offset(vec.len() as isize) +is always safe.

+

Most platforms fundamentally can't even construct such an +allocation. For instance, no known 64-bit platform can ever +serve a request for 263 bytes due to page-table limitations or +splitting the address space. However, some 32-bit and 16-bit +platforms may successfully serve a request for more than +isize::MAX bytes with things like Physical Address Extension. +As such, memory acquired directly from allocators or memory +mapped files may be too large to handle with this function.

+

Consider using wrapping_offset instead if these constraints +are difficult to satisfy. The only advantage of this method is +that it enables more aggressive compiler optimizations.

+

pub fn wrapping_offset(self, count: isizex4) -> Self[src]

Calculates the offset from a pointer using wrapping arithmetic.

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

The resulting pointer does not need to be in bounds, but it is +potentially hazardous to dereference (which requires unsafe).

+

Always use .offset(count) instead when possible, because +offset allows the compiler to optimize better.

+

pub unsafe fn offset_from(self, origin: Self) -> isizex4[src]

Calculates the distance between two pointers.

+

The returned value is in units of T: the distance in bytes is +divided by mem::size_of::<T>().

+

This function is the inverse of offset.

+

Safety

+

If any of the following conditions are violated, the result is +Undefined Behavior:

+
    +
  • +

    Both the starting and other pointer must be either in bounds +or one byte past the end of the same allocated object.

    +
    • +
  • +

    The distance between the pointers, in bytes, cannot overflow +an isize.

    +
    • +
  • +

    The distance between the pointers, in bytes, must be an exact +multiple of the size of T.

    +
    • +
  • +

    The distance being in bounds cannot rely on "wrapping around" +the address space.

    +
    • +
+

The compiler and standard library generally try to ensure +allocations never reach a size where an offset is a concern. For +instance, Vec and Box ensure they never allocate more than +isize::MAX bytes, so ptr_into_vec.offset_from(vec.as_ptr()) +is always safe.

+

Most platforms fundamentally can't even construct such an +allocation. For instance, no known 64-bit platform can ever +serve a request for 263 bytes due to page-table limitations or +splitting the address space. However, some 32-bit and 16-bit +platforms may successfully serve a request for more than +isize::MAX bytes with things like Physical Address Extension. +As such, memory acquired directly from allocators or memory +mapped files may be too large to handle with this function.

+

Consider using wrapping_offset_from instead if these constraints +are difficult to satisfy. The only advantage of this method is +that it enables more aggressive compiler optimizations.

+

pub fn wrapping_offset_from(self, origin: Self) -> isizex4[src]

Calculates the distance between two pointers.

+

The returned value is in units of T: the distance in bytes is +divided by mem::size_of::<T>().

+

If the address different between the two pointers is not a +multiple of mem::size_of::<T>() then the result of the +division is rounded towards zero.

+

Though this method is safe for any two pointers, note that its +result will be mostly useless if the two pointers aren't into +the same allocated object, for example if they point to two +different local variables.

+

pub unsafe fn add(self, count: usizex4) -> Self[src]

Calculates the offset from a pointer (convenience for +.offset(count as isize)).

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

If any of the following conditions are violated, the result is +Undefined Behavior:

+
    +
  • +

    Both the starting and resulting pointer must be either in +bounds or one byte past the end of an allocated object.

    +
    • +
  • +

    The computed offset, in bytes, cannot overflow an isize.

    +
    • +
  • +

    The offset being in bounds cannot rely on "wrapping around" +the address space. That is, the infinite-precision sum must fit +in a usize.

    +
    • +
+

The compiler and standard library generally tries to ensure +allocations never reach a size where an offset is a concern. For +instance, Vec and Box ensure they never allocate more than +isize::MAX bytes, so vec.as_ptr().add(vec.len()) is always +safe.

+

Most platforms fundamentally can't even construct such an +allocation. For instance, no known 64-bit platform can ever +serve a request for 263 bytes due to page-table limitations or +splitting the address space. However, some 32-bit and 16-bit +platforms may successfully serve a request for more than +isize::MAX bytes with things like Physical Address Extension. +As such, memory acquired directly from allocators or memory +mapped files may be too large to handle with this function.

+

Consider using wrapping_offset instead if these constraints +are difficult to satisfy. The only advantage of this method is +that it enables more aggressive compiler optimizations.

+

pub unsafe fn sub(self, count: usizex4) -> Self[src]

Calculates the offset from a pointer (convenience for +.offset((count as isize).wrapping_neg())).

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

If any of the following conditions are violated, the result is +Undefined Behavior:

+
    +
  • +

    Both the starting and resulting pointer must be either in +bounds or one byte past the end of an allocated object.

    +
    • +
  • +

    The computed offset cannot exceed isize::MAX bytes.

    +
    • +
  • +

    The offset being in bounds cannot rely on "wrapping around" +the address space. That is, the infinite-precision sum must fit +in a usize.

    +
    • +
+

The compiler and standard library generally tries to ensure +allocations never reach a size where an offset is a concern. For +instance, Vec and Box ensure they never allocate more than +isize::MAX bytes, so +vec.as_ptr().add(vec.len()).sub(vec.len()) is always safe.

+

Most platforms fundamentally can't even construct such an +allocation. For instance, no known 64-bit platform can ever +serve a request for 263 bytes due to page-table +limitations or splitting the address space. However, some 32-bit +and 16-bit platforms may successfully serve a request for more +than isize::MAX bytes with things like Physical Address +Extension. As such, memory acquired directly from allocators or +memory mapped files may be too large to handle with this +function.

+

Consider using wrapping_offset instead if these constraints +are difficult to satisfy. The only advantage of this method is +that it enables more aggressive compiler optimizations.

+

pub fn wrapping_add(self, count: usizex4) -> Self[src]

Calculates the offset from a pointer using wrapping arithmetic. +(convenience for .wrapping_offset(count as isize))

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

The resulting pointer does not need to be in bounds, but it is +potentially hazardous to dereference (which requires unsafe).

+

Always use .add(count) instead when possible, because add +allows the compiler to optimize better.

+

pub fn wrapping_sub(self, count: usizex4) -> Self[src]

Calculates the offset from a pointer using wrapping arithmetic. +(convenience for .wrapping_offset((count as isize).wrapping_sub()))

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

The resulting pointer does not need to be in bounds, but it is +potentially hazardous to dereference (which requires unsafe).

+

Always use .sub(count) instead when possible, because sub +allows the compiler to optimize better.

+

impl<T> Simd<[*mut T; 4]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl<T> Simd<[*mut T; 4]> where
    [T; 4]: SimdArray, [src]

pub unsafe fn read<M>(
    self,
    mask: Simd<[M; 4]>,
    value: Simd<[T; 4]>
) -> Simd<[T; 4]> where
    M: Mask,
    [M; 4]: SimdArray, [src]

Reads selected vector elements from memory.

+

Instantiates a new vector by reading the values from self for +those lanes whose mask is true, and using the elements of +value otherwise.

+

No memory is accessed for those lanes of self whose mask is +false.

+

Safety

+

This method is unsafe because it dereferences raw pointers. The +pointers must be aligned to mem::align_of::<T>().

+

impl<T> Simd<[*mut T; 4]> where
    [T; 4]: SimdArray, [src]

pub unsafe fn write<M>(self, mask: Simd<[M; 4]>, value: Simd<[T; 4]>) where
    M: Mask,
    [M; 4]: SimdArray, [src]

Writes selected vector elements to memory.

+

Writes the lanes of values for which the mask is true to +their corresponding memory addresses in self.

+

No memory is accessed for those lanes of self whose mask is +false.

+

Overlapping memory addresses of self are written to in order +from the lest-significant to the most-significant element.

+

Safety

+

This method is unsafe because it dereferences raw pointers. The +pointers must be aligned to mem::align_of::<T>().

+

impl<T> Simd<[*const T; 8]>[src]

pub const fn new(
    x0: *const T,
    x1: *const T,
    x2: *const T,
    x3: *const T,
    x4: *const T,
    x5: *const T,
    x6: *const T,
    x7: *const T
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: *const T) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub const fn null() -> Self[src]

Constructs a new instance with each element initialized to +null.

+

pub fn is_null(self) -> msizex8[src]

Returns a mask that selects those lanes that contain null +pointers.

+

pub fn extract(self, index: usize) -> *const T[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> *const T[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: *const T) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: *const T) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl<T> Simd<[*const T; 8]>[src]

pub fn eq(self, other: Self) -> msizex8[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> msizex8[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> msizex8[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> msizex8[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> msizex8[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> msizex8[src]

Lane-wise greater-than-or-equals comparison.

+

impl<T> Simd<[*const T; 8]>[src]

pub fn from_slice_aligned(slice: &[*const T]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[*const T]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[*const T]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[*const T]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl<T> Simd<[*const T; 8]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [*const T])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [*const T])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [*const T])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [*const T])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl<T> Simd<[*const T; 8]>[src]

pub unsafe fn offset(self, count: isizex8) -> Self[src]

Calculates the offset from a pointer.

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

If any of the following conditions are violated, the result is +Undefined Behavior:

+
    +
  • +

    Both the starting and resulting pointer must be either in +bounds or one byte past the end of an allocated object.

    +
    • +
  • +

    The computed offset, in bytes, cannot overflow an isize.

    +
    • +
  • +

    The offset being in bounds cannot rely on "wrapping around" +the address space. That is, the infinite-precision sum, in bytes +must fit in a usize.

    +
    • +
+

The compiler and standard library generally tries to ensure +allocations never reach a size where an offset is a concern. For +instance, Vec and Box ensure they never allocate more than +isize::MAX bytes, so vec.as_ptr().offset(vec.len() as isize) +is always safe.

+

Most platforms fundamentally can't even construct such an +allocation. For instance, no known 64-bit platform can ever +serve a request for 263 bytes due to page-table limitations or +splitting the address space. However, some 32-bit and 16-bit +platforms may successfully serve a request for more than +isize::MAX bytes with things like Physical Address Extension. +As such, memory acquired directly from allocators or memory +mapped files may be too large to handle with this function.

+

Consider using wrapping_offset instead if these constraints +are difficult to satisfy. The only advantage of this method is +that it enables more aggressive compiler optimizations.

+

pub fn wrapping_offset(self, count: isizex8) -> Self[src]

Calculates the offset from a pointer using wrapping arithmetic.

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

The resulting pointer does not need to be in bounds, but it is +potentially hazardous to dereference (which requires unsafe).

+

Always use .offset(count) instead when possible, because +offset allows the compiler to optimize better.

+

pub unsafe fn offset_from(self, origin: Self) -> isizex8[src]

Calculates the distance between two pointers.

+

The returned value is in units of T: the distance in bytes is +divided by mem::size_of::<T>().

+

This function is the inverse of offset.

+

Safety

+

If any of the following conditions are violated, the result is +Undefined Behavior:

+
    +
  • +

    Both the starting and other pointer must be either in bounds +or one byte past the end of the same allocated object.

    +
    • +
  • +

    The distance between the pointers, in bytes, cannot overflow +an isize.

    +
    • +
  • +

    The distance between the pointers, in bytes, must be an exact +multiple of the size of T.

    +
    • +
  • +

    The distance being in bounds cannot rely on "wrapping around" +the address space.

    +
    • +
+

The compiler and standard library generally try to ensure +allocations never reach a size where an offset is a concern. For +instance, Vec and Box ensure they never allocate more than +isize::MAX bytes, so ptr_into_vec.offset_from(vec.as_ptr()) +is always safe.

+

Most platforms fundamentally can't even construct such an +allocation. For instance, no known 64-bit platform can ever +serve a request for 263 bytes due to page-table limitations or +splitting the address space. However, some 32-bit and 16-bit +platforms may successfully serve a request for more than +isize::MAX bytes with things like Physical Address Extension. +As such, memory acquired directly from allocators or memory +mapped files may be too large to handle with this function.

+

Consider using wrapping_offset_from instead if these constraints +are difficult to satisfy. The only advantage of this method is +that it enables more aggressive compiler optimizations.

+

pub fn wrapping_offset_from(self, origin: Self) -> isizex8[src]

Calculates the distance between two pointers.

+

The returned value is in units of T: the distance in bytes is +divided by mem::size_of::<T>().

+

If the address different between the two pointers is not a +multiple of mem::size_of::<T>() then the result of the +division is rounded towards zero.

+

Though this method is safe for any two pointers, note that its +result will be mostly useless if the two pointers aren't into +the same allocated object, for example if they point to two +different local variables.

+

pub unsafe fn add(self, count: usizex8) -> Self[src]

Calculates the offset from a pointer (convenience for +.offset(count as isize)).

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

If any of the following conditions are violated, the result is +Undefined Behavior:

+
    +
  • +

    Both the starting and resulting pointer must be either in +bounds or one byte past the end of an allocated object.

    +
    • +
  • +

    The computed offset, in bytes, cannot overflow an isize.

    +
    • +
  • +

    The offset being in bounds cannot rely on "wrapping around" +the address space. That is, the infinite-precision sum must fit +in a usize.

    +
    • +
+

The compiler and standard library generally tries to ensure +allocations never reach a size where an offset is a concern. For +instance, Vec and Box ensure they never allocate more than +isize::MAX bytes, so vec.as_ptr().add(vec.len()) is always +safe.

+

Most platforms fundamentally can't even construct such an +allocation. For instance, no known 64-bit platform can ever +serve a request for 263 bytes due to page-table limitations or +splitting the address space. However, some 32-bit and 16-bit +platforms may successfully serve a request for more than +isize::MAX bytes with things like Physical Address Extension. +As such, memory acquired directly from allocators or memory +mapped files may be too large to handle with this function.

+

Consider using wrapping_offset instead if these constraints +are difficult to satisfy. The only advantage of this method is +that it enables more aggressive compiler optimizations.

+

pub unsafe fn sub(self, count: usizex8) -> Self[src]

Calculates the offset from a pointer (convenience for +.offset((count as isize).wrapping_neg())).

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

If any of the following conditions are violated, the result is +Undefined Behavior:

+
    +
  • +

    Both the starting and resulting pointer must be either in +bounds or one byte past the end of an allocated object.

    +
    • +
  • +

    The computed offset cannot exceed isize::MAX bytes.

    +
    • +
  • +

    The offset being in bounds cannot rely on "wrapping around" +the address space. That is, the infinite-precision sum must fit +in a usize.

    +
    • +
+

The compiler and standard library generally tries to ensure +allocations never reach a size where an offset is a concern. For +instance, Vec and Box ensure they never allocate more than +isize::MAX bytes, so +vec.as_ptr().add(vec.len()).sub(vec.len()) is always safe.

+

Most platforms fundamentally can't even construct such an +allocation. For instance, no known 64-bit platform can ever +serve a request for 263 bytes due to page-table +limitations or splitting the address space. However, some 32-bit +and 16-bit platforms may successfully serve a request for more +than isize::MAX bytes with things like Physical Address +Extension. As such, memory acquired directly from allocators or +memory mapped files may be too large to handle with this +function.

+

Consider using wrapping_offset instead if these constraints +are difficult to satisfy. The only advantage of this method is +that it enables more aggressive compiler optimizations.

+

pub fn wrapping_add(self, count: usizex8) -> Self[src]

Calculates the offset from a pointer using wrapping arithmetic. +(convenience for .wrapping_offset(count as isize))

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

The resulting pointer does not need to be in bounds, but it is +potentially hazardous to dereference (which requires unsafe).

+

Always use .add(count) instead when possible, because add +allows the compiler to optimize better.

+

pub fn wrapping_sub(self, count: usizex8) -> Self[src]

Calculates the offset from a pointer using wrapping arithmetic. +(convenience for .wrapping_offset((count as isize).wrapping_sub()))

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

The resulting pointer does not need to be in bounds, but it is +potentially hazardous to dereference (which requires unsafe).

+

Always use .sub(count) instead when possible, because sub +allows the compiler to optimize better.

+

impl<T> Simd<[*const T; 8]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl<T> Simd<[*const T; 8]> where
    [T; 8]: SimdArray, [src]

pub unsafe fn read<M>(
    self,
    mask: Simd<[M; 8]>,
    value: Simd<[T; 8]>
) -> Simd<[T; 8]> where
    M: Mask,
    [M; 8]: SimdArray, [src]

Reads selected vector elements from memory.

+

Instantiates a new vector by reading the values from self for +those lanes whose mask is true, and using the elements of +value otherwise.

+

No memory is accessed for those lanes of self whose mask is +false.

+

Safety

+

This method is unsafe because it dereferences raw pointers. The +pointers must be aligned to mem::align_of::<T>().

+

impl<T> Simd<[*mut T; 8]>[src]

pub const fn new(
    x0: *mut T,
    x1: *mut T,
    x2: *mut T,
    x3: *mut T,
    x4: *mut T,
    x5: *mut T,
    x6: *mut T,
    x7: *mut T
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: *mut T) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub const fn null() -> Self[src]

Constructs a new instance with each element initialized to +null.

+

pub fn is_null(self) -> msizex8[src]

Returns a mask that selects those lanes that contain null +pointers.

+

pub fn extract(self, index: usize) -> *mut T[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> *mut T[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: *mut T) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: *mut T) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl<T> Simd<[*mut T; 8]>[src]

pub fn eq(self, other: Self) -> msizex8[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> msizex8[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> msizex8[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> msizex8[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> msizex8[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> msizex8[src]

Lane-wise greater-than-or-equals comparison.

+

impl<T> Simd<[*mut T; 8]>[src]

pub fn from_slice_aligned(slice: &[*mut T]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[*mut T]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[*mut T]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[*mut T]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl<T> Simd<[*mut T; 8]>[src]

pub fn write_to_slice_aligned(self, slice: &mut [*mut T])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [*mut T])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [*mut T])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [*mut T])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl<T> Simd<[*mut T; 8]>[src]

pub unsafe fn offset(self, count: isizex8) -> Self[src]

Calculates the offset from a pointer.

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

If any of the following conditions are violated, the result is +Undefined Behavior:

+
    +
  • +

    Both the starting and resulting pointer must be either in +bounds or one byte past the end of an allocated object.

    +
    • +
  • +

    The computed offset, in bytes, cannot overflow an isize.

    +
    • +
  • +

    The offset being in bounds cannot rely on "wrapping around" +the address space. That is, the infinite-precision sum, in bytes +must fit in a usize.

    +
    • +
+

The compiler and standard library generally tries to ensure +allocations never reach a size where an offset is a concern. For +instance, Vec and Box ensure they never allocate more than +isize::MAX bytes, so vec.as_ptr().offset(vec.len() as isize) +is always safe.

+

Most platforms fundamentally can't even construct such an +allocation. For instance, no known 64-bit platform can ever +serve a request for 263 bytes due to page-table limitations or +splitting the address space. However, some 32-bit and 16-bit +platforms may successfully serve a request for more than +isize::MAX bytes with things like Physical Address Extension. +As such, memory acquired directly from allocators or memory +mapped files may be too large to handle with this function.

+

Consider using wrapping_offset instead if these constraints +are difficult to satisfy. The only advantage of this method is +that it enables more aggressive compiler optimizations.

+

pub fn wrapping_offset(self, count: isizex8) -> Self[src]

Calculates the offset from a pointer using wrapping arithmetic.

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

The resulting pointer does not need to be in bounds, but it is +potentially hazardous to dereference (which requires unsafe).

+

Always use .offset(count) instead when possible, because +offset allows the compiler to optimize better.

+

pub unsafe fn offset_from(self, origin: Self) -> isizex8[src]

Calculates the distance between two pointers.

+

The returned value is in units of T: the distance in bytes is +divided by mem::size_of::<T>().

+

This function is the inverse of offset.

+

Safety

+

If any of the following conditions are violated, the result is +Undefined Behavior:

+
    +
  • +

    Both the starting and other pointer must be either in bounds +or one byte past the end of the same allocated object.

    +
    • +
  • +

    The distance between the pointers, in bytes, cannot overflow +an isize.

    +
    • +
  • +

    The distance between the pointers, in bytes, must be an exact +multiple of the size of T.

    +
    • +
  • +

    The distance being in bounds cannot rely on "wrapping around" +the address space.

    +
    • +
+

The compiler and standard library generally try to ensure +allocations never reach a size where an offset is a concern. For +instance, Vec and Box ensure they never allocate more than +isize::MAX bytes, so ptr_into_vec.offset_from(vec.as_ptr()) +is always safe.

+

Most platforms fundamentally can't even construct such an +allocation. For instance, no known 64-bit platform can ever +serve a request for 263 bytes due to page-table limitations or +splitting the address space. However, some 32-bit and 16-bit +platforms may successfully serve a request for more than +isize::MAX bytes with things like Physical Address Extension. +As such, memory acquired directly from allocators or memory +mapped files may be too large to handle with this function.

+

Consider using wrapping_offset_from instead if these constraints +are difficult to satisfy. The only advantage of this method is +that it enables more aggressive compiler optimizations.

+

pub fn wrapping_offset_from(self, origin: Self) -> isizex8[src]

Calculates the distance between two pointers.

+

The returned value is in units of T: the distance in bytes is +divided by mem::size_of::<T>().

+

If the address different between the two pointers is not a +multiple of mem::size_of::<T>() then the result of the +division is rounded towards zero.

+

Though this method is safe for any two pointers, note that its +result will be mostly useless if the two pointers aren't into +the same allocated object, for example if they point to two +different local variables.

+

pub unsafe fn add(self, count: usizex8) -> Self[src]

Calculates the offset from a pointer (convenience for +.offset(count as isize)).

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

If any of the following conditions are violated, the result is +Undefined Behavior:

+
    +
  • +

    Both the starting and resulting pointer must be either in +bounds or one byte past the end of an allocated object.

    +
    • +
  • +

    The computed offset, in bytes, cannot overflow an isize.

    +
    • +
  • +

    The offset being in bounds cannot rely on "wrapping around" +the address space. That is, the infinite-precision sum must fit +in a usize.

    +
    • +
+

The compiler and standard library generally tries to ensure +allocations never reach a size where an offset is a concern. For +instance, Vec and Box ensure they never allocate more than +isize::MAX bytes, so vec.as_ptr().add(vec.len()) is always +safe.

+

Most platforms fundamentally can't even construct such an +allocation. For instance, no known 64-bit platform can ever +serve a request for 263 bytes due to page-table limitations or +splitting the address space. However, some 32-bit and 16-bit +platforms may successfully serve a request for more than +isize::MAX bytes with things like Physical Address Extension. +As such, memory acquired directly from allocators or memory +mapped files may be too large to handle with this function.

+

Consider using wrapping_offset instead if these constraints +are difficult to satisfy. The only advantage of this method is +that it enables more aggressive compiler optimizations.

+

pub unsafe fn sub(self, count: usizex8) -> Self[src]

Calculates the offset from a pointer (convenience for +.offset((count as isize).wrapping_neg())).

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

If any of the following conditions are violated, the result is +Undefined Behavior:

+
    +
  • +

    Both the starting and resulting pointer must be either in +bounds or one byte past the end of an allocated object.

    +
    • +
  • +

    The computed offset cannot exceed isize::MAX bytes.

    +
    • +
  • +

    The offset being in bounds cannot rely on "wrapping around" +the address space. That is, the infinite-precision sum must fit +in a usize.

    +
    • +
+

The compiler and standard library generally tries to ensure +allocations never reach a size where an offset is a concern. For +instance, Vec and Box ensure they never allocate more than +isize::MAX bytes, so +vec.as_ptr().add(vec.len()).sub(vec.len()) is always safe.

+

Most platforms fundamentally can't even construct such an +allocation. For instance, no known 64-bit platform can ever +serve a request for 263 bytes due to page-table +limitations or splitting the address space. However, some 32-bit +and 16-bit platforms may successfully serve a request for more +than isize::MAX bytes with things like Physical Address +Extension. As such, memory acquired directly from allocators or +memory mapped files may be too large to handle with this +function.

+

Consider using wrapping_offset instead if these constraints +are difficult to satisfy. The only advantage of this method is +that it enables more aggressive compiler optimizations.

+

pub fn wrapping_add(self, count: usizex8) -> Self[src]

Calculates the offset from a pointer using wrapping arithmetic. +(convenience for .wrapping_offset(count as isize))

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

The resulting pointer does not need to be in bounds, but it is +potentially hazardous to dereference (which requires unsafe).

+

Always use .add(count) instead when possible, because add +allows the compiler to optimize better.

+

pub fn wrapping_sub(self, count: usizex8) -> Self[src]

Calculates the offset from a pointer using wrapping arithmetic. +(convenience for .wrapping_offset((count as isize).wrapping_sub()))

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

The resulting pointer does not need to be in bounds, but it is +potentially hazardous to dereference (which requires unsafe).

+

Always use .sub(count) instead when possible, because sub +allows the compiler to optimize better.

+

impl<T> Simd<[*mut T; 8]>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl<T> Simd<[*mut T; 8]> where
    [T; 8]: SimdArray, [src]

pub unsafe fn read<M>(
    self,
    mask: Simd<[M; 8]>,
    value: Simd<[T; 8]>
) -> Simd<[T; 8]> where
    M: Mask,
    [M; 8]: SimdArray, [src]

Reads selected vector elements from memory.

+

Instantiates a new vector by reading the values from self for +those lanes whose mask is true, and using the elements of +value otherwise.

+

No memory is accessed for those lanes of self whose mask is +false.

+

Safety

+

This method is unsafe because it dereferences raw pointers. The +pointers must be aligned to mem::align_of::<T>().

+

impl<T> Simd<[*mut T; 8]> where
    [T; 8]: SimdArray, [src]

pub unsafe fn write<M>(self, mask: Simd<[M; 8]>, value: Simd<[T; 8]>) where
    M: Mask,
    [M; 8]: SimdArray, [src]

Writes selected vector elements to memory.

+

Writes the lanes of values for which the mask is true to +their corresponding memory addresses in self.

+

No memory is accessed for those lanes of self whose mask is +false.

+

Overlapping memory addresses of self are written to in order +from the lest-significant to the most-significant element.

+

Safety

+

This method is unsafe because it dereferences raw pointers. The +pointers must be aligned to mem::align_of::<T>().

+

Trait Implementations

impl Add<Simd<[f32; 16]>> for f32x16[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[f32; 16]>> for f32[src]

type Output = f32x16

The resulting type after applying the + operator.

+

impl Add<Simd<[f32; 2]>> for f32x2[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[f32; 2]>> for f32[src]

type Output = f32x2

The resulting type after applying the + operator.

+

impl Add<Simd<[f32; 4]>> for f32x4[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[f32; 4]>> for f32[src]

type Output = f32x4

The resulting type after applying the + operator.

+

impl Add<Simd<[f32; 8]>> for f32x8[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[f32; 8]>> for f32[src]

type Output = f32x8

The resulting type after applying the + operator.

+

impl Add<Simd<[f64; 2]>> for f64x2[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[f64; 2]>> for f64[src]

type Output = f64x2

The resulting type after applying the + operator.

+

impl Add<Simd<[f64; 4]>> for f64x4[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[f64; 4]>> for f64[src]

type Output = f64x4

The resulting type after applying the + operator.

+

impl Add<Simd<[f64; 8]>> for f64x8[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[f64; 8]>> for f64[src]

type Output = f64x8

The resulting type after applying the + operator.

+

impl Add<Simd<[i128; 1]>> for i128x1[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[i128; 1]>> for i128[src]

type Output = i128x1

The resulting type after applying the + operator.

+

impl Add<Simd<[i128; 2]>> for i128x2[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[i128; 2]>> for i128[src]

type Output = i128x2

The resulting type after applying the + operator.

+

impl Add<Simd<[i128; 4]>> for i128x4[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[i128; 4]>> for i128[src]

type Output = i128x4

The resulting type after applying the + operator.

+

impl Add<Simd<[i16; 16]>> for i16x16[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[i16; 16]>> for i16[src]

type Output = i16x16

The resulting type after applying the + operator.

+

impl Add<Simd<[i16; 2]>> for i16x2[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[i16; 2]>> for i16[src]

type Output = i16x2

The resulting type after applying the + operator.

+

impl Add<Simd<[i16; 32]>> for i16x32[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[i16; 32]>> for i16[src]

type Output = i16x32

The resulting type after applying the + operator.

+

impl Add<Simd<[i16; 4]>> for i16x4[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[i16; 4]>> for i16[src]

type Output = i16x4

The resulting type after applying the + operator.

+

impl Add<Simd<[i16; 8]>> for i16x8[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[i16; 8]>> for i16[src]

type Output = i16x8

The resulting type after applying the + operator.

+

impl Add<Simd<[i32; 16]>> for i32x16[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[i32; 16]>> for i32[src]

type Output = i32x16

The resulting type after applying the + operator.

+

impl Add<Simd<[i32; 2]>> for i32x2[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[i32; 2]>> for i32[src]

type Output = i32x2

The resulting type after applying the + operator.

+

impl Add<Simd<[i32; 4]>> for i32x4[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[i32; 4]>> for i32[src]

type Output = i32x4

The resulting type after applying the + operator.

+

impl Add<Simd<[i32; 8]>> for i32x8[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[i32; 8]>> for i32[src]

type Output = i32x8

The resulting type after applying the + operator.

+

impl Add<Simd<[i64; 2]>> for i64x2[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[i64; 2]>> for i64[src]

type Output = i64x2

The resulting type after applying the + operator.

+

impl Add<Simd<[i64; 4]>> for i64x4[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[i64; 4]>> for i64[src]

type Output = i64x4

The resulting type after applying the + operator.

+

impl Add<Simd<[i64; 8]>> for i64x8[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[i64; 8]>> for i64[src]

type Output = i64x8

The resulting type after applying the + operator.

+

impl Add<Simd<[i8; 16]>> for i8x16[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[i8; 16]>> for i8[src]

type Output = i8x16

The resulting type after applying the + operator.

+

impl Add<Simd<[i8; 2]>> for i8x2[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[i8; 2]>> for i8[src]

type Output = i8x2

The resulting type after applying the + operator.

+

impl Add<Simd<[i8; 32]>> for i8x32[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[i8; 32]>> for i8[src]

type Output = i8x32

The resulting type after applying the + operator.

+

impl Add<Simd<[i8; 4]>> for i8x4[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[i8; 4]>> for i8[src]

type Output = i8x4

The resulting type after applying the + operator.

+

impl Add<Simd<[i8; 64]>> for i8x64[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[i8; 64]>> for i8[src]

type Output = i8x64

The resulting type after applying the + operator.

+

impl Add<Simd<[i8; 8]>> for i8x8[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[i8; 8]>> for i8[src]

type Output = i8x8

The resulting type after applying the + operator.

+

impl Add<Simd<[isize; 2]>> for isizex2[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[isize; 2]>> for isize[src]

type Output = isizex2

The resulting type after applying the + operator.

+

impl Add<Simd<[isize; 4]>> for isizex4[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[isize; 4]>> for isize[src]

type Output = isizex4

The resulting type after applying the + operator.

+

impl Add<Simd<[isize; 8]>> for isizex8[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[isize; 8]>> for isize[src]

type Output = isizex8

The resulting type after applying the + operator.

+

impl Add<Simd<[u128; 1]>> for u128x1[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[u128; 1]>> for u128[src]

type Output = u128x1

The resulting type after applying the + operator.

+

impl Add<Simd<[u128; 2]>> for u128x2[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[u128; 2]>> for u128[src]

type Output = u128x2

The resulting type after applying the + operator.

+

impl Add<Simd<[u128; 4]>> for u128x4[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[u128; 4]>> for u128[src]

type Output = u128x4

The resulting type after applying the + operator.

+

impl Add<Simd<[u16; 16]>> for u16x16[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[u16; 16]>> for u16[src]

type Output = u16x16

The resulting type after applying the + operator.

+

impl Add<Simd<[u16; 2]>> for u16x2[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[u16; 2]>> for u16[src]

type Output = u16x2

The resulting type after applying the + operator.

+

impl Add<Simd<[u16; 32]>> for u16x32[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[u16; 32]>> for u16[src]

type Output = u16x32

The resulting type after applying the + operator.

+

impl Add<Simd<[u16; 4]>> for u16x4[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[u16; 4]>> for u16[src]

type Output = u16x4

The resulting type after applying the + operator.

+

impl Add<Simd<[u16; 8]>> for u16x8[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[u16; 8]>> for u16[src]

type Output = u16x8

The resulting type after applying the + operator.

+

impl Add<Simd<[u32; 16]>> for u32x16[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[u32; 16]>> for u32[src]

type Output = u32x16

The resulting type after applying the + operator.

+

impl Add<Simd<[u32; 2]>> for u32x2[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[u32; 2]>> for u32[src]

type Output = u32x2

The resulting type after applying the + operator.

+

impl Add<Simd<[u32; 4]>> for u32x4[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[u32; 4]>> for u32[src]

type Output = u32x4

The resulting type after applying the + operator.

+

impl Add<Simd<[u32; 8]>> for u32x8[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[u32; 8]>> for u32[src]

type Output = u32x8

The resulting type after applying the + operator.

+

impl Add<Simd<[u64; 2]>> for u64x2[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[u64; 2]>> for u64[src]

type Output = u64x2

The resulting type after applying the + operator.

+

impl Add<Simd<[u64; 4]>> for u64x4[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[u64; 4]>> for u64[src]

type Output = u64x4

The resulting type after applying the + operator.

+

impl Add<Simd<[u64; 8]>> for u64x8[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[u64; 8]>> for u64[src]

type Output = u64x8

The resulting type after applying the + operator.

+

impl Add<Simd<[u8; 16]>> for u8x16[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[u8; 16]>> for u8[src]

type Output = u8x16

The resulting type after applying the + operator.

+

impl Add<Simd<[u8; 2]>> for u8x2[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[u8; 2]>> for u8[src]

type Output = u8x2

The resulting type after applying the + operator.

+

impl Add<Simd<[u8; 32]>> for u8x32[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[u8; 32]>> for u8[src]

type Output = u8x32

The resulting type after applying the + operator.

+

impl Add<Simd<[u8; 4]>> for u8x4[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[u8; 4]>> for u8[src]

type Output = u8x4

The resulting type after applying the + operator.

+

impl Add<Simd<[u8; 64]>> for u8x64[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[u8; 64]>> for u8[src]

type Output = u8x64

The resulting type after applying the + operator.

+

impl Add<Simd<[u8; 8]>> for u8x8[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[u8; 8]>> for u8[src]

type Output = u8x8

The resulting type after applying the + operator.

+

impl Add<Simd<[usize; 2]>> for usizex2[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[usize; 2]>> for usize[src]

type Output = usizex2

The resulting type after applying the + operator.

+

impl Add<Simd<[usize; 4]>> for usizex4[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[usize; 4]>> for usize[src]

type Output = usizex4

The resulting type after applying the + operator.

+

impl Add<Simd<[usize; 8]>> for usizex8[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<Simd<[usize; 8]>> for usize[src]

type Output = usizex8

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[f32; 16]>> for f32x16[src]

impl AddAssign<Simd<[f32; 2]>> for f32x2[src]

impl AddAssign<Simd<[f32; 4]>> for f32x4[src]

impl AddAssign<Simd<[f32; 8]>> for f32x8[src]

impl AddAssign<Simd<[f64; 2]>> for f64x2[src]

impl AddAssign<Simd<[f64; 4]>> for f64x4[src]

impl AddAssign<Simd<[f64; 8]>> for f64x8[src]

impl AddAssign<Simd<[i128; 1]>> for i128x1[src]

impl AddAssign<Simd<[i128; 2]>> for i128x2[src]

impl AddAssign<Simd<[i128; 4]>> for i128x4[src]

impl AddAssign<Simd<[i16; 16]>> for i16x16[src]

impl AddAssign<Simd<[i16; 2]>> for i16x2[src]

impl AddAssign<Simd<[i16; 32]>> for i16x32[src]

impl AddAssign<Simd<[i16; 4]>> for i16x4[src]

impl AddAssign<Simd<[i16; 8]>> for i16x8[src]

impl AddAssign<Simd<[i32; 16]>> for i32x16[src]

impl AddAssign<Simd<[i32; 2]>> for i32x2[src]

impl AddAssign<Simd<[i32; 4]>> for i32x4[src]

impl AddAssign<Simd<[i32; 8]>> for i32x8[src]

impl AddAssign<Simd<[i64; 2]>> for i64x2[src]

impl AddAssign<Simd<[i64; 4]>> for i64x4[src]

impl AddAssign<Simd<[i64; 8]>> for i64x8[src]

impl AddAssign<Simd<[i8; 16]>> for i8x16[src]

impl AddAssign<Simd<[i8; 2]>> for i8x2[src]

impl AddAssign<Simd<[i8; 32]>> for i8x32[src]

impl AddAssign<Simd<[i8; 4]>> for i8x4[src]

impl AddAssign<Simd<[i8; 64]>> for i8x64[src]

impl AddAssign<Simd<[i8; 8]>> for i8x8[src]

impl AddAssign<Simd<[isize; 2]>> for isizex2[src]

impl AddAssign<Simd<[isize; 4]>> for isizex4[src]

impl AddAssign<Simd<[isize; 8]>> for isizex8[src]

impl AddAssign<Simd<[u128; 1]>> for u128x1[src]

impl AddAssign<Simd<[u128; 2]>> for u128x2[src]

impl AddAssign<Simd<[u128; 4]>> for u128x4[src]

impl AddAssign<Simd<[u16; 16]>> for u16x16[src]

impl AddAssign<Simd<[u16; 2]>> for u16x2[src]

impl AddAssign<Simd<[u16; 32]>> for u16x32[src]

impl AddAssign<Simd<[u16; 4]>> for u16x4[src]

impl AddAssign<Simd<[u16; 8]>> for u16x8[src]

impl AddAssign<Simd<[u32; 16]>> for u32x16[src]

impl AddAssign<Simd<[u32; 2]>> for u32x2[src]

impl AddAssign<Simd<[u32; 4]>> for u32x4[src]

impl AddAssign<Simd<[u32; 8]>> for u32x8[src]

impl AddAssign<Simd<[u64; 2]>> for u64x2[src]

impl AddAssign<Simd<[u64; 4]>> for u64x4[src]

impl AddAssign<Simd<[u64; 8]>> for u64x8[src]

impl AddAssign<Simd<[u8; 16]>> for u8x16[src]

impl AddAssign<Simd<[u8; 2]>> for u8x2[src]

impl AddAssign<Simd<[u8; 32]>> for u8x32[src]

impl AddAssign<Simd<[u8; 4]>> for u8x4[src]

impl AddAssign<Simd<[u8; 64]>> for u8x64[src]

impl AddAssign<Simd<[u8; 8]>> for u8x8[src]

impl AddAssign<Simd<[usize; 2]>> for usizex2[src]

impl AddAssign<Simd<[usize; 4]>> for usizex4[src]

impl AddAssign<Simd<[usize; 8]>> for usizex8[src]

impl BitAnd<Simd<[i128; 1]>> for i128x1[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[i128; 1]>> for i128[src]

type Output = i128x1

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[i128; 2]>> for i128x2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[i128; 2]>> for i128[src]

type Output = i128x2

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[i128; 4]>> for i128x4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[i128; 4]>> for i128[src]

type Output = i128x4

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[i16; 16]>> for i16x16[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[i16; 16]>> for i16[src]

type Output = i16x16

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[i16; 2]>> for i16x2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[i16; 2]>> for i16[src]

type Output = i16x2

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[i16; 32]>> for i16x32[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[i16; 32]>> for i16[src]

type Output = i16x32

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[i16; 4]>> for i16x4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[i16; 4]>> for i16[src]

type Output = i16x4

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[i16; 8]>> for i16x8[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[i16; 8]>> for i16[src]

type Output = i16x8

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[i32; 16]>> for i32x16[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[i32; 16]>> for i32[src]

type Output = i32x16

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[i32; 2]>> for i32x2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[i32; 2]>> for i32[src]

type Output = i32x2

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[i32; 4]>> for i32x4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[i32; 4]>> for i32[src]

type Output = i32x4

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[i32; 8]>> for i32x8[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[i32; 8]>> for i32[src]

type Output = i32x8

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[i64; 2]>> for i64x2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[i64; 2]>> for i64[src]

type Output = i64x2

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[i64; 4]>> for i64x4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[i64; 4]>> for i64[src]

type Output = i64x4

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[i64; 8]>> for i64x8[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[i64; 8]>> for i64[src]

type Output = i64x8

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[i8; 16]>> for i8x16[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[i8; 16]>> for i8[src]

type Output = i8x16

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[i8; 2]>> for i8x2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[i8; 2]>> for i8[src]

type Output = i8x2

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[i8; 32]>> for i8x32[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[i8; 32]>> for i8[src]

type Output = i8x32

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[i8; 4]>> for i8x4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[i8; 4]>> for i8[src]

type Output = i8x4

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[i8; 64]>> for i8x64[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[i8; 64]>> for i8[src]

type Output = i8x64

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[i8; 8]>> for i8x8[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[i8; 8]>> for i8[src]

type Output = i8x8

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[isize; 2]>> for isizex2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[isize; 2]>> for isize[src]

type Output = isizex2

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[isize; 4]>> for isizex4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[isize; 4]>> for isize[src]

type Output = isizex4

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[isize; 8]>> for isizex8[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[isize; 8]>> for isize[src]

type Output = isizex8

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[m128; 1]>> for m128x1[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[m128; 1]>> for bool[src]

type Output = m128x1

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[m128; 2]>> for m128x2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[m128; 2]>> for bool[src]

type Output = m128x2

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[m128; 4]>> for m128x4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[m128; 4]>> for bool[src]

type Output = m128x4

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[m16; 16]>> for m16x16[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[m16; 16]>> for bool[src]

type Output = m16x16

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[m16; 2]>> for m16x2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[m16; 2]>> for bool[src]

type Output = m16x2

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[m16; 32]>> for m16x32[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[m16; 32]>> for bool[src]

type Output = m16x32

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[m16; 4]>> for m16x4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[m16; 4]>> for bool[src]

type Output = m16x4

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[m16; 8]>> for m16x8[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[m16; 8]>> for bool[src]

type Output = m16x8

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[m32; 16]>> for m32x16[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[m32; 16]>> for bool[src]

type Output = m32x16

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[m32; 2]>> for m32x2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[m32; 2]>> for bool[src]

type Output = m32x2

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[m32; 4]>> for m32x4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[m32; 4]>> for bool[src]

type Output = m32x4

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[m32; 8]>> for m32x8[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[m32; 8]>> for bool[src]

type Output = m32x8

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[m64; 2]>> for m64x2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[m64; 2]>> for bool[src]

type Output = m64x2

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[m64; 4]>> for m64x4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[m64; 4]>> for bool[src]

type Output = m64x4

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[m64; 8]>> for m64x8[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[m64; 8]>> for bool[src]

type Output = m64x8

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[m8; 16]>> for m8x16[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[m8; 16]>> for bool[src]

type Output = m8x16

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[m8; 2]>> for m8x2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[m8; 2]>> for bool[src]

type Output = m8x2

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[m8; 32]>> for m8x32[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[m8; 32]>> for bool[src]

type Output = m8x32

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[m8; 4]>> for m8x4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[m8; 4]>> for bool[src]

type Output = m8x4

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[m8; 64]>> for m8x64[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[m8; 64]>> for bool[src]

type Output = m8x64

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[m8; 8]>> for m8x8[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[m8; 8]>> for bool[src]

type Output = m8x8

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[msize; 2]>> for msizex2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[msize; 2]>> for bool[src]

type Output = msizex2

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[msize; 4]>> for msizex4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[msize; 4]>> for bool[src]

type Output = msizex4

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[msize; 8]>> for msizex8[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[msize; 8]>> for bool[src]

type Output = msizex8

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[u128; 1]>> for u128x1[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[u128; 1]>> for u128[src]

type Output = u128x1

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[u128; 2]>> for u128x2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[u128; 2]>> for u128[src]

type Output = u128x2

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[u128; 4]>> for u128x4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[u128; 4]>> for u128[src]

type Output = u128x4

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[u16; 16]>> for u16x16[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[u16; 16]>> for u16[src]

type Output = u16x16

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[u16; 2]>> for u16x2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[u16; 2]>> for u16[src]

type Output = u16x2

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[u16; 32]>> for u16x32[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[u16; 32]>> for u16[src]

type Output = u16x32

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[u16; 4]>> for u16x4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[u16; 4]>> for u16[src]

type Output = u16x4

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[u16; 8]>> for u16x8[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[u16; 8]>> for u16[src]

type Output = u16x8

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[u32; 16]>> for u32x16[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[u32; 16]>> for u32[src]

type Output = u32x16

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[u32; 2]>> for u32x2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[u32; 2]>> for u32[src]

type Output = u32x2

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[u32; 4]>> for u32x4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[u32; 4]>> for u32[src]

type Output = u32x4

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[u32; 8]>> for u32x8[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[u32; 8]>> for u32[src]

type Output = u32x8

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[u64; 2]>> for u64x2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[u64; 2]>> for u64[src]

type Output = u64x2

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[u64; 4]>> for u64x4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[u64; 4]>> for u64[src]

type Output = u64x4

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[u64; 8]>> for u64x8[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[u64; 8]>> for u64[src]

type Output = u64x8

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[u8; 16]>> for u8x16[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[u8; 16]>> for u8[src]

type Output = u8x16

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[u8; 2]>> for u8x2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[u8; 2]>> for u8[src]

type Output = u8x2

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[u8; 32]>> for u8x32[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[u8; 32]>> for u8[src]

type Output = u8x32

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[u8; 4]>> for u8x4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[u8; 4]>> for u8[src]

type Output = u8x4

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[u8; 64]>> for u8x64[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[u8; 64]>> for u8[src]

type Output = u8x64

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[u8; 8]>> for u8x8[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[u8; 8]>> for u8[src]

type Output = u8x8

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[usize; 2]>> for usizex2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[usize; 2]>> for usize[src]

type Output = usizex2

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[usize; 4]>> for usizex4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[usize; 4]>> for usize[src]

type Output = usizex4

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[usize; 8]>> for usizex8[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<Simd<[usize; 8]>> for usize[src]

type Output = usizex8

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[i128; 1]>> for i128x1[src]

impl BitAndAssign<Simd<[i128; 2]>> for i128x2[src]

impl BitAndAssign<Simd<[i128; 4]>> for i128x4[src]

impl BitAndAssign<Simd<[i16; 16]>> for i16x16[src]

impl BitAndAssign<Simd<[i16; 2]>> for i16x2[src]

impl BitAndAssign<Simd<[i16; 32]>> for i16x32[src]

impl BitAndAssign<Simd<[i16; 4]>> for i16x4[src]

impl BitAndAssign<Simd<[i16; 8]>> for i16x8[src]

impl BitAndAssign<Simd<[i32; 16]>> for i32x16[src]

impl BitAndAssign<Simd<[i32; 2]>> for i32x2[src]

impl BitAndAssign<Simd<[i32; 4]>> for i32x4[src]

impl BitAndAssign<Simd<[i32; 8]>> for i32x8[src]

impl BitAndAssign<Simd<[i64; 2]>> for i64x2[src]

impl BitAndAssign<Simd<[i64; 4]>> for i64x4[src]

impl BitAndAssign<Simd<[i64; 8]>> for i64x8[src]

impl BitAndAssign<Simd<[i8; 16]>> for i8x16[src]

impl BitAndAssign<Simd<[i8; 2]>> for i8x2[src]

impl BitAndAssign<Simd<[i8; 32]>> for i8x32[src]

impl BitAndAssign<Simd<[i8; 4]>> for i8x4[src]

impl BitAndAssign<Simd<[i8; 64]>> for i8x64[src]

impl BitAndAssign<Simd<[i8; 8]>> for i8x8[src]

impl BitAndAssign<Simd<[isize; 2]>> for isizex2[src]

impl BitAndAssign<Simd<[isize; 4]>> for isizex4[src]

impl BitAndAssign<Simd<[isize; 8]>> for isizex8[src]

impl BitAndAssign<Simd<[m128; 1]>> for m128x1[src]

impl BitAndAssign<Simd<[m128; 2]>> for m128x2[src]

impl BitAndAssign<Simd<[m128; 4]>> for m128x4[src]

impl BitAndAssign<Simd<[m16; 16]>> for m16x16[src]

impl BitAndAssign<Simd<[m16; 2]>> for m16x2[src]

impl BitAndAssign<Simd<[m16; 32]>> for m16x32[src]

impl BitAndAssign<Simd<[m16; 4]>> for m16x4[src]

impl BitAndAssign<Simd<[m16; 8]>> for m16x8[src]

impl BitAndAssign<Simd<[m32; 16]>> for m32x16[src]

impl BitAndAssign<Simd<[m32; 2]>> for m32x2[src]

impl BitAndAssign<Simd<[m32; 4]>> for m32x4[src]

impl BitAndAssign<Simd<[m32; 8]>> for m32x8[src]

impl BitAndAssign<Simd<[m64; 2]>> for m64x2[src]

impl BitAndAssign<Simd<[m64; 4]>> for m64x4[src]

impl BitAndAssign<Simd<[m64; 8]>> for m64x8[src]

impl BitAndAssign<Simd<[m8; 16]>> for m8x16[src]

impl BitAndAssign<Simd<[m8; 2]>> for m8x2[src]

impl BitAndAssign<Simd<[m8; 32]>> for m8x32[src]

impl BitAndAssign<Simd<[m8; 4]>> for m8x4[src]

impl BitAndAssign<Simd<[m8; 64]>> for m8x64[src]

impl BitAndAssign<Simd<[m8; 8]>> for m8x8[src]

impl BitAndAssign<Simd<[msize; 2]>> for msizex2[src]

impl BitAndAssign<Simd<[msize; 4]>> for msizex4[src]

impl BitAndAssign<Simd<[msize; 8]>> for msizex8[src]

impl BitAndAssign<Simd<[u128; 1]>> for u128x1[src]

impl BitAndAssign<Simd<[u128; 2]>> for u128x2[src]

impl BitAndAssign<Simd<[u128; 4]>> for u128x4[src]

impl BitAndAssign<Simd<[u16; 16]>> for u16x16[src]

impl BitAndAssign<Simd<[u16; 2]>> for u16x2[src]

impl BitAndAssign<Simd<[u16; 32]>> for u16x32[src]

impl BitAndAssign<Simd<[u16; 4]>> for u16x4[src]

impl BitAndAssign<Simd<[u16; 8]>> for u16x8[src]

impl BitAndAssign<Simd<[u32; 16]>> for u32x16[src]

impl BitAndAssign<Simd<[u32; 2]>> for u32x2[src]

impl BitAndAssign<Simd<[u32; 4]>> for u32x4[src]

impl BitAndAssign<Simd<[u32; 8]>> for u32x8[src]

impl BitAndAssign<Simd<[u64; 2]>> for u64x2[src]

impl BitAndAssign<Simd<[u64; 4]>> for u64x4[src]

impl BitAndAssign<Simd<[u64; 8]>> for u64x8[src]

impl BitAndAssign<Simd<[u8; 16]>> for u8x16[src]

impl BitAndAssign<Simd<[u8; 2]>> for u8x2[src]

impl BitAndAssign<Simd<[u8; 32]>> for u8x32[src]

impl BitAndAssign<Simd<[u8; 4]>> for u8x4[src]

impl BitAndAssign<Simd<[u8; 64]>> for u8x64[src]

impl BitAndAssign<Simd<[u8; 8]>> for u8x8[src]

impl BitAndAssign<Simd<[usize; 2]>> for usizex2[src]

impl BitAndAssign<Simd<[usize; 4]>> for usizex4[src]

impl BitAndAssign<Simd<[usize; 8]>> for usizex8[src]

impl BitOr<Simd<[i128; 1]>> for i128x1[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[i128; 1]>> for i128[src]

type Output = i128x1

The resulting type after applying the | operator.

+

impl BitOr<Simd<[i128; 2]>> for i128x2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[i128; 2]>> for i128[src]

type Output = i128x2

The resulting type after applying the | operator.

+

impl BitOr<Simd<[i128; 4]>> for i128x4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[i128; 4]>> for i128[src]

type Output = i128x4

The resulting type after applying the | operator.

+

impl BitOr<Simd<[i16; 16]>> for i16x16[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[i16; 16]>> for i16[src]

type Output = i16x16

The resulting type after applying the | operator.

+

impl BitOr<Simd<[i16; 2]>> for i16x2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[i16; 2]>> for i16[src]

type Output = i16x2

The resulting type after applying the | operator.

+

impl BitOr<Simd<[i16; 32]>> for i16x32[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[i16; 32]>> for i16[src]

type Output = i16x32

The resulting type after applying the | operator.

+

impl BitOr<Simd<[i16; 4]>> for i16x4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[i16; 4]>> for i16[src]

type Output = i16x4

The resulting type after applying the | operator.

+

impl BitOr<Simd<[i16; 8]>> for i16x8[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[i16; 8]>> for i16[src]

type Output = i16x8

The resulting type after applying the | operator.

+

impl BitOr<Simd<[i32; 16]>> for i32x16[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[i32; 16]>> for i32[src]

type Output = i32x16

The resulting type after applying the | operator.

+

impl BitOr<Simd<[i32; 2]>> for i32x2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[i32; 2]>> for i32[src]

type Output = i32x2

The resulting type after applying the | operator.

+

impl BitOr<Simd<[i32; 4]>> for i32x4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[i32; 4]>> for i32[src]

type Output = i32x4

The resulting type after applying the | operator.

+

impl BitOr<Simd<[i32; 8]>> for i32x8[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[i32; 8]>> for i32[src]

type Output = i32x8

The resulting type after applying the | operator.

+

impl BitOr<Simd<[i64; 2]>> for i64x2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[i64; 2]>> for i64[src]

type Output = i64x2

The resulting type after applying the | operator.

+

impl BitOr<Simd<[i64; 4]>> for i64x4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[i64; 4]>> for i64[src]

type Output = i64x4

The resulting type after applying the | operator.

+

impl BitOr<Simd<[i64; 8]>> for i64x8[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[i64; 8]>> for i64[src]

type Output = i64x8

The resulting type after applying the | operator.

+

impl BitOr<Simd<[i8; 16]>> for i8x16[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[i8; 16]>> for i8[src]

type Output = i8x16

The resulting type after applying the | operator.

+

impl BitOr<Simd<[i8; 2]>> for i8x2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[i8; 2]>> for i8[src]

type Output = i8x2

The resulting type after applying the | operator.

+

impl BitOr<Simd<[i8; 32]>> for i8x32[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[i8; 32]>> for i8[src]

type Output = i8x32

The resulting type after applying the | operator.

+

impl BitOr<Simd<[i8; 4]>> for i8x4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[i8; 4]>> for i8[src]

type Output = i8x4

The resulting type after applying the | operator.

+

impl BitOr<Simd<[i8; 64]>> for i8x64[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[i8; 64]>> for i8[src]

type Output = i8x64

The resulting type after applying the | operator.

+

impl BitOr<Simd<[i8; 8]>> for i8x8[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[i8; 8]>> for i8[src]

type Output = i8x8

The resulting type after applying the | operator.

+

impl BitOr<Simd<[isize; 2]>> for isizex2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[isize; 2]>> for isize[src]

type Output = isizex2

The resulting type after applying the | operator.

+

impl BitOr<Simd<[isize; 4]>> for isizex4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[isize; 4]>> for isize[src]

type Output = isizex4

The resulting type after applying the | operator.

+

impl BitOr<Simd<[isize; 8]>> for isizex8[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[isize; 8]>> for isize[src]

type Output = isizex8

The resulting type after applying the | operator.

+

impl BitOr<Simd<[m128; 1]>> for m128x1[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[m128; 1]>> for bool[src]

type Output = m128x1

The resulting type after applying the | operator.

+

impl BitOr<Simd<[m128; 2]>> for m128x2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[m128; 2]>> for bool[src]

type Output = m128x2

The resulting type after applying the | operator.

+

impl BitOr<Simd<[m128; 4]>> for m128x4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[m128; 4]>> for bool[src]

type Output = m128x4

The resulting type after applying the | operator.

+

impl BitOr<Simd<[m16; 16]>> for m16x16[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[m16; 16]>> for bool[src]

type Output = m16x16

The resulting type after applying the | operator.

+

impl BitOr<Simd<[m16; 2]>> for m16x2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[m16; 2]>> for bool[src]

type Output = m16x2

The resulting type after applying the | operator.

+

impl BitOr<Simd<[m16; 32]>> for m16x32[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[m16; 32]>> for bool[src]

type Output = m16x32

The resulting type after applying the | operator.

+

impl BitOr<Simd<[m16; 4]>> for m16x4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[m16; 4]>> for bool[src]

type Output = m16x4

The resulting type after applying the | operator.

+

impl BitOr<Simd<[m16; 8]>> for m16x8[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[m16; 8]>> for bool[src]

type Output = m16x8

The resulting type after applying the | operator.

+

impl BitOr<Simd<[m32; 16]>> for m32x16[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[m32; 16]>> for bool[src]

type Output = m32x16

The resulting type after applying the | operator.

+

impl BitOr<Simd<[m32; 2]>> for m32x2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[m32; 2]>> for bool[src]

type Output = m32x2

The resulting type after applying the | operator.

+

impl BitOr<Simd<[m32; 4]>> for m32x4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[m32; 4]>> for bool[src]

type Output = m32x4

The resulting type after applying the | operator.

+

impl BitOr<Simd<[m32; 8]>> for m32x8[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[m32; 8]>> for bool[src]

type Output = m32x8

The resulting type after applying the | operator.

+

impl BitOr<Simd<[m64; 2]>> for m64x2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[m64; 2]>> for bool[src]

type Output = m64x2

The resulting type after applying the | operator.

+

impl BitOr<Simd<[m64; 4]>> for m64x4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[m64; 4]>> for bool[src]

type Output = m64x4

The resulting type after applying the | operator.

+

impl BitOr<Simd<[m64; 8]>> for m64x8[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[m64; 8]>> for bool[src]

type Output = m64x8

The resulting type after applying the | operator.

+

impl BitOr<Simd<[m8; 16]>> for m8x16[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[m8; 16]>> for bool[src]

type Output = m8x16

The resulting type after applying the | operator.

+

impl BitOr<Simd<[m8; 2]>> for m8x2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[m8; 2]>> for bool[src]

type Output = m8x2

The resulting type after applying the | operator.

+

impl BitOr<Simd<[m8; 32]>> for m8x32[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[m8; 32]>> for bool[src]

type Output = m8x32

The resulting type after applying the | operator.

+

impl BitOr<Simd<[m8; 4]>> for m8x4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[m8; 4]>> for bool[src]

type Output = m8x4

The resulting type after applying the | operator.

+

impl BitOr<Simd<[m8; 64]>> for m8x64[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[m8; 64]>> for bool[src]

type Output = m8x64

The resulting type after applying the | operator.

+

impl BitOr<Simd<[m8; 8]>> for m8x8[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[m8; 8]>> for bool[src]

type Output = m8x8

The resulting type after applying the | operator.

+

impl BitOr<Simd<[msize; 2]>> for msizex2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[msize; 2]>> for bool[src]

type Output = msizex2

The resulting type after applying the | operator.

+

impl BitOr<Simd<[msize; 4]>> for msizex4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[msize; 4]>> for bool[src]

type Output = msizex4

The resulting type after applying the | operator.

+

impl BitOr<Simd<[msize; 8]>> for msizex8[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[msize; 8]>> for bool[src]

type Output = msizex8

The resulting type after applying the | operator.

+

impl BitOr<Simd<[u128; 1]>> for u128x1[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[u128; 1]>> for u128[src]

type Output = u128x1

The resulting type after applying the | operator.

+

impl BitOr<Simd<[u128; 2]>> for u128x2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[u128; 2]>> for u128[src]

type Output = u128x2

The resulting type after applying the | operator.

+

impl BitOr<Simd<[u128; 4]>> for u128x4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[u128; 4]>> for u128[src]

type Output = u128x4

The resulting type after applying the | operator.

+

impl BitOr<Simd<[u16; 16]>> for u16x16[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[u16; 16]>> for u16[src]

type Output = u16x16

The resulting type after applying the | operator.

+

impl BitOr<Simd<[u16; 2]>> for u16x2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[u16; 2]>> for u16[src]

type Output = u16x2

The resulting type after applying the | operator.

+

impl BitOr<Simd<[u16; 32]>> for u16x32[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[u16; 32]>> for u16[src]

type Output = u16x32

The resulting type after applying the | operator.

+

impl BitOr<Simd<[u16; 4]>> for u16x4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[u16; 4]>> for u16[src]

type Output = u16x4

The resulting type after applying the | operator.

+

impl BitOr<Simd<[u16; 8]>> for u16x8[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[u16; 8]>> for u16[src]

type Output = u16x8

The resulting type after applying the | operator.

+

impl BitOr<Simd<[u32; 16]>> for u32x16[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[u32; 16]>> for u32[src]

type Output = u32x16

The resulting type after applying the | operator.

+

impl BitOr<Simd<[u32; 2]>> for u32x2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[u32; 2]>> for u32[src]

type Output = u32x2

The resulting type after applying the | operator.

+

impl BitOr<Simd<[u32; 4]>> for u32x4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[u32; 4]>> for u32[src]

type Output = u32x4

The resulting type after applying the | operator.

+

impl BitOr<Simd<[u32; 8]>> for u32x8[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[u32; 8]>> for u32[src]

type Output = u32x8

The resulting type after applying the | operator.

+

impl BitOr<Simd<[u64; 2]>> for u64x2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[u64; 2]>> for u64[src]

type Output = u64x2

The resulting type after applying the | operator.

+

impl BitOr<Simd<[u64; 4]>> for u64x4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[u64; 4]>> for u64[src]

type Output = u64x4

The resulting type after applying the | operator.

+

impl BitOr<Simd<[u64; 8]>> for u64x8[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[u64; 8]>> for u64[src]

type Output = u64x8

The resulting type after applying the | operator.

+

impl BitOr<Simd<[u8; 16]>> for u8x16[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[u8; 16]>> for u8[src]

type Output = u8x16

The resulting type after applying the | operator.

+

impl BitOr<Simd<[u8; 2]>> for u8x2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[u8; 2]>> for u8[src]

type Output = u8x2

The resulting type after applying the | operator.

+

impl BitOr<Simd<[u8; 32]>> for u8x32[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[u8; 32]>> for u8[src]

type Output = u8x32

The resulting type after applying the | operator.

+

impl BitOr<Simd<[u8; 4]>> for u8x4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[u8; 4]>> for u8[src]

type Output = u8x4

The resulting type after applying the | operator.

+

impl BitOr<Simd<[u8; 64]>> for u8x64[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[u8; 64]>> for u8[src]

type Output = u8x64

The resulting type after applying the | operator.

+

impl BitOr<Simd<[u8; 8]>> for u8x8[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[u8; 8]>> for u8[src]

type Output = u8x8

The resulting type after applying the | operator.

+

impl BitOr<Simd<[usize; 2]>> for usizex2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[usize; 2]>> for usize[src]

type Output = usizex2

The resulting type after applying the | operator.

+

impl BitOr<Simd<[usize; 4]>> for usizex4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[usize; 4]>> for usize[src]

type Output = usizex4

The resulting type after applying the | operator.

+

impl BitOr<Simd<[usize; 8]>> for usizex8[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<Simd<[usize; 8]>> for usize[src]

type Output = usizex8

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[i128; 1]>> for i128x1[src]

impl BitOrAssign<Simd<[i128; 2]>> for i128x2[src]

impl BitOrAssign<Simd<[i128; 4]>> for i128x4[src]

impl BitOrAssign<Simd<[i16; 16]>> for i16x16[src]

impl BitOrAssign<Simd<[i16; 2]>> for i16x2[src]

impl BitOrAssign<Simd<[i16; 32]>> for i16x32[src]

impl BitOrAssign<Simd<[i16; 4]>> for i16x4[src]

impl BitOrAssign<Simd<[i16; 8]>> for i16x8[src]

impl BitOrAssign<Simd<[i32; 16]>> for i32x16[src]

impl BitOrAssign<Simd<[i32; 2]>> for i32x2[src]

impl BitOrAssign<Simd<[i32; 4]>> for i32x4[src]

impl BitOrAssign<Simd<[i32; 8]>> for i32x8[src]

impl BitOrAssign<Simd<[i64; 2]>> for i64x2[src]

impl BitOrAssign<Simd<[i64; 4]>> for i64x4[src]

impl BitOrAssign<Simd<[i64; 8]>> for i64x8[src]

impl BitOrAssign<Simd<[i8; 16]>> for i8x16[src]

impl BitOrAssign<Simd<[i8; 2]>> for i8x2[src]

impl BitOrAssign<Simd<[i8; 32]>> for i8x32[src]

impl BitOrAssign<Simd<[i8; 4]>> for i8x4[src]

impl BitOrAssign<Simd<[i8; 64]>> for i8x64[src]

impl BitOrAssign<Simd<[i8; 8]>> for i8x8[src]

impl BitOrAssign<Simd<[isize; 2]>> for isizex2[src]

impl BitOrAssign<Simd<[isize; 4]>> for isizex4[src]

impl BitOrAssign<Simd<[isize; 8]>> for isizex8[src]

impl BitOrAssign<Simd<[m128; 1]>> for m128x1[src]

impl BitOrAssign<Simd<[m128; 2]>> for m128x2[src]

impl BitOrAssign<Simd<[m128; 4]>> for m128x4[src]

impl BitOrAssign<Simd<[m16; 16]>> for m16x16[src]

impl BitOrAssign<Simd<[m16; 2]>> for m16x2[src]

impl BitOrAssign<Simd<[m16; 32]>> for m16x32[src]

impl BitOrAssign<Simd<[m16; 4]>> for m16x4[src]

impl BitOrAssign<Simd<[m16; 8]>> for m16x8[src]

impl BitOrAssign<Simd<[m32; 16]>> for m32x16[src]

impl BitOrAssign<Simd<[m32; 2]>> for m32x2[src]

impl BitOrAssign<Simd<[m32; 4]>> for m32x4[src]

impl BitOrAssign<Simd<[m32; 8]>> for m32x8[src]

impl BitOrAssign<Simd<[m64; 2]>> for m64x2[src]

impl BitOrAssign<Simd<[m64; 4]>> for m64x4[src]

impl BitOrAssign<Simd<[m64; 8]>> for m64x8[src]

impl BitOrAssign<Simd<[m8; 16]>> for m8x16[src]

impl BitOrAssign<Simd<[m8; 2]>> for m8x2[src]

impl BitOrAssign<Simd<[m8; 32]>> for m8x32[src]

impl BitOrAssign<Simd<[m8; 4]>> for m8x4[src]

impl BitOrAssign<Simd<[m8; 64]>> for m8x64[src]

impl BitOrAssign<Simd<[m8; 8]>> for m8x8[src]

impl BitOrAssign<Simd<[msize; 2]>> for msizex2[src]

impl BitOrAssign<Simd<[msize; 4]>> for msizex4[src]

impl BitOrAssign<Simd<[msize; 8]>> for msizex8[src]

impl BitOrAssign<Simd<[u128; 1]>> for u128x1[src]

impl BitOrAssign<Simd<[u128; 2]>> for u128x2[src]

impl BitOrAssign<Simd<[u128; 4]>> for u128x4[src]

impl BitOrAssign<Simd<[u16; 16]>> for u16x16[src]

impl BitOrAssign<Simd<[u16; 2]>> for u16x2[src]

impl BitOrAssign<Simd<[u16; 32]>> for u16x32[src]

impl BitOrAssign<Simd<[u16; 4]>> for u16x4[src]

impl BitOrAssign<Simd<[u16; 8]>> for u16x8[src]

impl BitOrAssign<Simd<[u32; 16]>> for u32x16[src]

impl BitOrAssign<Simd<[u32; 2]>> for u32x2[src]

impl BitOrAssign<Simd<[u32; 4]>> for u32x4[src]

impl BitOrAssign<Simd<[u32; 8]>> for u32x8[src]

impl BitOrAssign<Simd<[u64; 2]>> for u64x2[src]

impl BitOrAssign<Simd<[u64; 4]>> for u64x4[src]

impl BitOrAssign<Simd<[u64; 8]>> for u64x8[src]

impl BitOrAssign<Simd<[u8; 16]>> for u8x16[src]

impl BitOrAssign<Simd<[u8; 2]>> for u8x2[src]

impl BitOrAssign<Simd<[u8; 32]>> for u8x32[src]

impl BitOrAssign<Simd<[u8; 4]>> for u8x4[src]

impl BitOrAssign<Simd<[u8; 64]>> for u8x64[src]

impl BitOrAssign<Simd<[u8; 8]>> for u8x8[src]

impl BitOrAssign<Simd<[usize; 2]>> for usizex2[src]

impl BitOrAssign<Simd<[usize; 4]>> for usizex4[src]

impl BitOrAssign<Simd<[usize; 8]>> for usizex8[src]

impl BitXor<Simd<[i128; 1]>> for i128x1[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[i128; 1]>> for i128[src]

type Output = i128x1

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[i128; 2]>> for i128x2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[i128; 2]>> for i128[src]

type Output = i128x2

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[i128; 4]>> for i128x4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[i128; 4]>> for i128[src]

type Output = i128x4

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[i16; 16]>> for i16x16[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[i16; 16]>> for i16[src]

type Output = i16x16

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[i16; 2]>> for i16x2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[i16; 2]>> for i16[src]

type Output = i16x2

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[i16; 32]>> for i16x32[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[i16; 32]>> for i16[src]

type Output = i16x32

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[i16; 4]>> for i16x4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[i16; 4]>> for i16[src]

type Output = i16x4

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[i16; 8]>> for i16x8[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[i16; 8]>> for i16[src]

type Output = i16x8

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[i32; 16]>> for i32x16[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[i32; 16]>> for i32[src]

type Output = i32x16

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[i32; 2]>> for i32x2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[i32; 2]>> for i32[src]

type Output = i32x2

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[i32; 4]>> for i32x4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[i32; 4]>> for i32[src]

type Output = i32x4

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[i32; 8]>> for i32x8[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[i32; 8]>> for i32[src]

type Output = i32x8

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[i64; 2]>> for i64x2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[i64; 2]>> for i64[src]

type Output = i64x2

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[i64; 4]>> for i64x4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[i64; 4]>> for i64[src]

type Output = i64x4

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[i64; 8]>> for i64x8[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[i64; 8]>> for i64[src]

type Output = i64x8

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[i8; 16]>> for i8x16[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[i8; 16]>> for i8[src]

type Output = i8x16

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[i8; 2]>> for i8x2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[i8; 2]>> for i8[src]

type Output = i8x2

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[i8; 32]>> for i8x32[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[i8; 32]>> for i8[src]

type Output = i8x32

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[i8; 4]>> for i8x4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[i8; 4]>> for i8[src]

type Output = i8x4

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[i8; 64]>> for i8x64[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[i8; 64]>> for i8[src]

type Output = i8x64

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[i8; 8]>> for i8x8[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[i8; 8]>> for i8[src]

type Output = i8x8

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[isize; 2]>> for isizex2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[isize; 2]>> for isize[src]

type Output = isizex2

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[isize; 4]>> for isizex4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[isize; 4]>> for isize[src]

type Output = isizex4

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[isize; 8]>> for isizex8[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[isize; 8]>> for isize[src]

type Output = isizex8

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[m128; 1]>> for m128x1[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[m128; 1]>> for bool[src]

type Output = m128x1

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[m128; 2]>> for m128x2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[m128; 2]>> for bool[src]

type Output = m128x2

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[m128; 4]>> for m128x4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[m128; 4]>> for bool[src]

type Output = m128x4

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[m16; 16]>> for m16x16[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[m16; 16]>> for bool[src]

type Output = m16x16

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[m16; 2]>> for m16x2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[m16; 2]>> for bool[src]

type Output = m16x2

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[m16; 32]>> for m16x32[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[m16; 32]>> for bool[src]

type Output = m16x32

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[m16; 4]>> for m16x4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[m16; 4]>> for bool[src]

type Output = m16x4

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[m16; 8]>> for m16x8[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[m16; 8]>> for bool[src]

type Output = m16x8

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[m32; 16]>> for m32x16[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[m32; 16]>> for bool[src]

type Output = m32x16

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[m32; 2]>> for m32x2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[m32; 2]>> for bool[src]

type Output = m32x2

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[m32; 4]>> for m32x4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[m32; 4]>> for bool[src]

type Output = m32x4

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[m32; 8]>> for m32x8[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[m32; 8]>> for bool[src]

type Output = m32x8

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[m64; 2]>> for m64x2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[m64; 2]>> for bool[src]

type Output = m64x2

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[m64; 4]>> for m64x4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[m64; 4]>> for bool[src]

type Output = m64x4

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[m64; 8]>> for m64x8[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[m64; 8]>> for bool[src]

type Output = m64x8

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[m8; 16]>> for m8x16[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[m8; 16]>> for bool[src]

type Output = m8x16

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[m8; 2]>> for m8x2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[m8; 2]>> for bool[src]

type Output = m8x2

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[m8; 32]>> for m8x32[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[m8; 32]>> for bool[src]

type Output = m8x32

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[m8; 4]>> for m8x4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[m8; 4]>> for bool[src]

type Output = m8x4

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[m8; 64]>> for m8x64[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[m8; 64]>> for bool[src]

type Output = m8x64

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[m8; 8]>> for m8x8[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[m8; 8]>> for bool[src]

type Output = m8x8

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[msize; 2]>> for msizex2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[msize; 2]>> for bool[src]

type Output = msizex2

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[msize; 4]>> for msizex4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[msize; 4]>> for bool[src]

type Output = msizex4

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[msize; 8]>> for msizex8[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[msize; 8]>> for bool[src]

type Output = msizex8

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[u128; 1]>> for u128x1[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[u128; 1]>> for u128[src]

type Output = u128x1

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[u128; 2]>> for u128x2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[u128; 2]>> for u128[src]

type Output = u128x2

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[u128; 4]>> for u128x4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[u128; 4]>> for u128[src]

type Output = u128x4

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[u16; 16]>> for u16x16[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[u16; 16]>> for u16[src]

type Output = u16x16

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[u16; 2]>> for u16x2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[u16; 2]>> for u16[src]

type Output = u16x2

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[u16; 32]>> for u16x32[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[u16; 32]>> for u16[src]

type Output = u16x32

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[u16; 4]>> for u16x4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[u16; 4]>> for u16[src]

type Output = u16x4

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[u16; 8]>> for u16x8[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[u16; 8]>> for u16[src]

type Output = u16x8

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[u32; 16]>> for u32x16[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[u32; 16]>> for u32[src]

type Output = u32x16

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[u32; 2]>> for u32x2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[u32; 2]>> for u32[src]

type Output = u32x2

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[u32; 4]>> for u32x4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[u32; 4]>> for u32[src]

type Output = u32x4

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[u32; 8]>> for u32x8[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[u32; 8]>> for u32[src]

type Output = u32x8

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[u64; 2]>> for u64x2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[u64; 2]>> for u64[src]

type Output = u64x2

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[u64; 4]>> for u64x4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[u64; 4]>> for u64[src]

type Output = u64x4

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[u64; 8]>> for u64x8[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[u64; 8]>> for u64[src]

type Output = u64x8

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[u8; 16]>> for u8x16[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[u8; 16]>> for u8[src]

type Output = u8x16

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[u8; 2]>> for u8x2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[u8; 2]>> for u8[src]

type Output = u8x2

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[u8; 32]>> for u8x32[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[u8; 32]>> for u8[src]

type Output = u8x32

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[u8; 4]>> for u8x4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[u8; 4]>> for u8[src]

type Output = u8x4

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[u8; 64]>> for u8x64[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[u8; 64]>> for u8[src]

type Output = u8x64

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[u8; 8]>> for u8x8[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[u8; 8]>> for u8[src]

type Output = u8x8

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[usize; 2]>> for usizex2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[usize; 2]>> for usize[src]

type Output = usizex2

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[usize; 4]>> for usizex4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[usize; 4]>> for usize[src]

type Output = usizex4

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[usize; 8]>> for usizex8[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<Simd<[usize; 8]>> for usize[src]

type Output = usizex8

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[i128; 1]>> for i128x1[src]

impl BitXorAssign<Simd<[i128; 2]>> for i128x2[src]

impl BitXorAssign<Simd<[i128; 4]>> for i128x4[src]

impl BitXorAssign<Simd<[i16; 16]>> for i16x16[src]

impl BitXorAssign<Simd<[i16; 2]>> for i16x2[src]

impl BitXorAssign<Simd<[i16; 32]>> for i16x32[src]

impl BitXorAssign<Simd<[i16; 4]>> for i16x4[src]

impl BitXorAssign<Simd<[i16; 8]>> for i16x8[src]

impl BitXorAssign<Simd<[i32; 16]>> for i32x16[src]

impl BitXorAssign<Simd<[i32; 2]>> for i32x2[src]

impl BitXorAssign<Simd<[i32; 4]>> for i32x4[src]

impl BitXorAssign<Simd<[i32; 8]>> for i32x8[src]

impl BitXorAssign<Simd<[i64; 2]>> for i64x2[src]

impl BitXorAssign<Simd<[i64; 4]>> for i64x4[src]

impl BitXorAssign<Simd<[i64; 8]>> for i64x8[src]

impl BitXorAssign<Simd<[i8; 16]>> for i8x16[src]

impl BitXorAssign<Simd<[i8; 2]>> for i8x2[src]

impl BitXorAssign<Simd<[i8; 32]>> for i8x32[src]

impl BitXorAssign<Simd<[i8; 4]>> for i8x4[src]

impl BitXorAssign<Simd<[i8; 64]>> for i8x64[src]

impl BitXorAssign<Simd<[i8; 8]>> for i8x8[src]

impl BitXorAssign<Simd<[isize; 2]>> for isizex2[src]

impl BitXorAssign<Simd<[isize; 4]>> for isizex4[src]

impl BitXorAssign<Simd<[isize; 8]>> for isizex8[src]

impl BitXorAssign<Simd<[m128; 1]>> for m128x1[src]

impl BitXorAssign<Simd<[m128; 2]>> for m128x2[src]

impl BitXorAssign<Simd<[m128; 4]>> for m128x4[src]

impl BitXorAssign<Simd<[m16; 16]>> for m16x16[src]

impl BitXorAssign<Simd<[m16; 2]>> for m16x2[src]

impl BitXorAssign<Simd<[m16; 32]>> for m16x32[src]

impl BitXorAssign<Simd<[m16; 4]>> for m16x4[src]

impl BitXorAssign<Simd<[m16; 8]>> for m16x8[src]

impl BitXorAssign<Simd<[m32; 16]>> for m32x16[src]

impl BitXorAssign<Simd<[m32; 2]>> for m32x2[src]

impl BitXorAssign<Simd<[m32; 4]>> for m32x4[src]

impl BitXorAssign<Simd<[m32; 8]>> for m32x8[src]

impl BitXorAssign<Simd<[m64; 2]>> for m64x2[src]

impl BitXorAssign<Simd<[m64; 4]>> for m64x4[src]

impl BitXorAssign<Simd<[m64; 8]>> for m64x8[src]

impl BitXorAssign<Simd<[m8; 16]>> for m8x16[src]

impl BitXorAssign<Simd<[m8; 2]>> for m8x2[src]

impl BitXorAssign<Simd<[m8; 32]>> for m8x32[src]

impl BitXorAssign<Simd<[m8; 4]>> for m8x4[src]

impl BitXorAssign<Simd<[m8; 64]>> for m8x64[src]

impl BitXorAssign<Simd<[m8; 8]>> for m8x8[src]

impl BitXorAssign<Simd<[msize; 2]>> for msizex2[src]

impl BitXorAssign<Simd<[msize; 4]>> for msizex4[src]

impl BitXorAssign<Simd<[msize; 8]>> for msizex8[src]

impl BitXorAssign<Simd<[u128; 1]>> for u128x1[src]

impl BitXorAssign<Simd<[u128; 2]>> for u128x2[src]

impl BitXorAssign<Simd<[u128; 4]>> for u128x4[src]

impl BitXorAssign<Simd<[u16; 16]>> for u16x16[src]

impl BitXorAssign<Simd<[u16; 2]>> for u16x2[src]

impl BitXorAssign<Simd<[u16; 32]>> for u16x32[src]

impl BitXorAssign<Simd<[u16; 4]>> for u16x4[src]

impl BitXorAssign<Simd<[u16; 8]>> for u16x8[src]

impl BitXorAssign<Simd<[u32; 16]>> for u32x16[src]

impl BitXorAssign<Simd<[u32; 2]>> for u32x2[src]

impl BitXorAssign<Simd<[u32; 4]>> for u32x4[src]

impl BitXorAssign<Simd<[u32; 8]>> for u32x8[src]

impl BitXorAssign<Simd<[u64; 2]>> for u64x2[src]

impl BitXorAssign<Simd<[u64; 4]>> for u64x4[src]

impl BitXorAssign<Simd<[u64; 8]>> for u64x8[src]

impl BitXorAssign<Simd<[u8; 16]>> for u8x16[src]

impl BitXorAssign<Simd<[u8; 2]>> for u8x2[src]

impl BitXorAssign<Simd<[u8; 32]>> for u8x32[src]

impl BitXorAssign<Simd<[u8; 4]>> for u8x4[src]

impl BitXorAssign<Simd<[u8; 64]>> for u8x64[src]

impl BitXorAssign<Simd<[u8; 8]>> for u8x8[src]

impl BitXorAssign<Simd<[usize; 2]>> for usizex2[src]

impl BitXorAssign<Simd<[usize; 4]>> for usizex4[src]

impl BitXorAssign<Simd<[usize; 8]>> for usizex8[src]

impl<A: Clone + SimdArray> Clone for Simd<A>[src]

impl<A: Copy + SimdArray> Copy for Simd<A>[src]

impl Div<Simd<[f32; 16]>> for f32x16[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[f32; 16]>> for f32[src]

type Output = f32x16

The resulting type after applying the / operator.

+

impl Div<Simd<[f32; 2]>> for f32x2[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[f32; 2]>> for f32[src]

type Output = f32x2

The resulting type after applying the / operator.

+

impl Div<Simd<[f32; 4]>> for f32x4[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[f32; 4]>> for f32[src]

type Output = f32x4

The resulting type after applying the / operator.

+

impl Div<Simd<[f32; 8]>> for f32x8[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[f32; 8]>> for f32[src]

type Output = f32x8

The resulting type after applying the / operator.

+

impl Div<Simd<[f64; 2]>> for f64x2[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[f64; 2]>> for f64[src]

type Output = f64x2

The resulting type after applying the / operator.

+

impl Div<Simd<[f64; 4]>> for f64x4[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[f64; 4]>> for f64[src]

type Output = f64x4

The resulting type after applying the / operator.

+

impl Div<Simd<[f64; 8]>> for f64x8[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[f64; 8]>> for f64[src]

type Output = f64x8

The resulting type after applying the / operator.

+

impl Div<Simd<[i128; 1]>> for i128x1[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[i128; 1]>> for i128[src]

type Output = i128x1

The resulting type after applying the / operator.

+

impl Div<Simd<[i128; 2]>> for i128x2[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[i128; 2]>> for i128[src]

type Output = i128x2

The resulting type after applying the / operator.

+

impl Div<Simd<[i128; 4]>> for i128x4[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[i128; 4]>> for i128[src]

type Output = i128x4

The resulting type after applying the / operator.

+

impl Div<Simd<[i16; 16]>> for i16x16[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[i16; 16]>> for i16[src]

type Output = i16x16

The resulting type after applying the / operator.

+

impl Div<Simd<[i16; 2]>> for i16x2[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[i16; 2]>> for i16[src]

type Output = i16x2

The resulting type after applying the / operator.

+

impl Div<Simd<[i16; 32]>> for i16x32[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[i16; 32]>> for i16[src]

type Output = i16x32

The resulting type after applying the / operator.

+

impl Div<Simd<[i16; 4]>> for i16x4[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[i16; 4]>> for i16[src]

type Output = i16x4

The resulting type after applying the / operator.

+

impl Div<Simd<[i16; 8]>> for i16x8[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[i16; 8]>> for i16[src]

type Output = i16x8

The resulting type after applying the / operator.

+

impl Div<Simd<[i32; 16]>> for i32x16[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[i32; 16]>> for i32[src]

type Output = i32x16

The resulting type after applying the / operator.

+

impl Div<Simd<[i32; 2]>> for i32x2[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[i32; 2]>> for i32[src]

type Output = i32x2

The resulting type after applying the / operator.

+

impl Div<Simd<[i32; 4]>> for i32x4[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[i32; 4]>> for i32[src]

type Output = i32x4

The resulting type after applying the / operator.

+

impl Div<Simd<[i32; 8]>> for i32x8[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[i32; 8]>> for i32[src]

type Output = i32x8

The resulting type after applying the / operator.

+

impl Div<Simd<[i64; 2]>> for i64x2[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[i64; 2]>> for i64[src]

type Output = i64x2

The resulting type after applying the / operator.

+

impl Div<Simd<[i64; 4]>> for i64x4[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[i64; 4]>> for i64[src]

type Output = i64x4

The resulting type after applying the / operator.

+

impl Div<Simd<[i64; 8]>> for i64x8[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[i64; 8]>> for i64[src]

type Output = i64x8

The resulting type after applying the / operator.

+

impl Div<Simd<[i8; 16]>> for i8x16[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[i8; 16]>> for i8[src]

type Output = i8x16

The resulting type after applying the / operator.

+

impl Div<Simd<[i8; 2]>> for i8x2[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[i8; 2]>> for i8[src]

type Output = i8x2

The resulting type after applying the / operator.

+

impl Div<Simd<[i8; 32]>> for i8x32[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[i8; 32]>> for i8[src]

type Output = i8x32

The resulting type after applying the / operator.

+

impl Div<Simd<[i8; 4]>> for i8x4[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[i8; 4]>> for i8[src]

type Output = i8x4

The resulting type after applying the / operator.

+

impl Div<Simd<[i8; 64]>> for i8x64[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[i8; 64]>> for i8[src]

type Output = i8x64

The resulting type after applying the / operator.

+

impl Div<Simd<[i8; 8]>> for i8x8[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[i8; 8]>> for i8[src]

type Output = i8x8

The resulting type after applying the / operator.

+

impl Div<Simd<[isize; 2]>> for isizex2[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[isize; 2]>> for isize[src]

type Output = isizex2

The resulting type after applying the / operator.

+

impl Div<Simd<[isize; 4]>> for isizex4[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[isize; 4]>> for isize[src]

type Output = isizex4

The resulting type after applying the / operator.

+

impl Div<Simd<[isize; 8]>> for isizex8[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[isize; 8]>> for isize[src]

type Output = isizex8

The resulting type after applying the / operator.

+

impl Div<Simd<[u128; 1]>> for u128x1[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[u128; 1]>> for u128[src]

type Output = u128x1

The resulting type after applying the / operator.

+

impl Div<Simd<[u128; 2]>> for u128x2[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[u128; 2]>> for u128[src]

type Output = u128x2

The resulting type after applying the / operator.

+

impl Div<Simd<[u128; 4]>> for u128x4[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[u128; 4]>> for u128[src]

type Output = u128x4

The resulting type after applying the / operator.

+

impl Div<Simd<[u16; 16]>> for u16x16[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[u16; 16]>> for u16[src]

type Output = u16x16

The resulting type after applying the / operator.

+

impl Div<Simd<[u16; 2]>> for u16x2[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[u16; 2]>> for u16[src]

type Output = u16x2

The resulting type after applying the / operator.

+

impl Div<Simd<[u16; 32]>> for u16x32[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[u16; 32]>> for u16[src]

type Output = u16x32

The resulting type after applying the / operator.

+

impl Div<Simd<[u16; 4]>> for u16x4[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[u16; 4]>> for u16[src]

type Output = u16x4

The resulting type after applying the / operator.

+

impl Div<Simd<[u16; 8]>> for u16x8[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[u16; 8]>> for u16[src]

type Output = u16x8

The resulting type after applying the / operator.

+

impl Div<Simd<[u32; 16]>> for u32x16[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[u32; 16]>> for u32[src]

type Output = u32x16

The resulting type after applying the / operator.

+

impl Div<Simd<[u32; 2]>> for u32x2[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[u32; 2]>> for u32[src]

type Output = u32x2

The resulting type after applying the / operator.

+

impl Div<Simd<[u32; 4]>> for u32x4[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[u32; 4]>> for u32[src]

type Output = u32x4

The resulting type after applying the / operator.

+

impl Div<Simd<[u32; 8]>> for u32x8[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[u32; 8]>> for u32[src]

type Output = u32x8

The resulting type after applying the / operator.

+

impl Div<Simd<[u64; 2]>> for u64x2[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[u64; 2]>> for u64[src]

type Output = u64x2

The resulting type after applying the / operator.

+

impl Div<Simd<[u64; 4]>> for u64x4[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[u64; 4]>> for u64[src]

type Output = u64x4

The resulting type after applying the / operator.

+

impl Div<Simd<[u64; 8]>> for u64x8[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[u64; 8]>> for u64[src]

type Output = u64x8

The resulting type after applying the / operator.

+

impl Div<Simd<[u8; 16]>> for u8x16[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[u8; 16]>> for u8[src]

type Output = u8x16

The resulting type after applying the / operator.

+

impl Div<Simd<[u8; 2]>> for u8x2[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[u8; 2]>> for u8[src]

type Output = u8x2

The resulting type after applying the / operator.

+

impl Div<Simd<[u8; 32]>> for u8x32[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[u8; 32]>> for u8[src]

type Output = u8x32

The resulting type after applying the / operator.

+

impl Div<Simd<[u8; 4]>> for u8x4[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[u8; 4]>> for u8[src]

type Output = u8x4

The resulting type after applying the / operator.

+

impl Div<Simd<[u8; 64]>> for u8x64[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[u8; 64]>> for u8[src]

type Output = u8x64

The resulting type after applying the / operator.

+

impl Div<Simd<[u8; 8]>> for u8x8[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[u8; 8]>> for u8[src]

type Output = u8x8

The resulting type after applying the / operator.

+

impl Div<Simd<[usize; 2]>> for usizex2[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[usize; 2]>> for usize[src]

type Output = usizex2

The resulting type after applying the / operator.

+

impl Div<Simd<[usize; 4]>> for usizex4[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[usize; 4]>> for usize[src]

type Output = usizex4

The resulting type after applying the / operator.

+

impl Div<Simd<[usize; 8]>> for usizex8[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<Simd<[usize; 8]>> for usize[src]

type Output = usizex8

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[f32; 16]>> for f32x16[src]

impl DivAssign<Simd<[f32; 2]>> for f32x2[src]

impl DivAssign<Simd<[f32; 4]>> for f32x4[src]

impl DivAssign<Simd<[f32; 8]>> for f32x8[src]

impl DivAssign<Simd<[f64; 2]>> for f64x2[src]

impl DivAssign<Simd<[f64; 4]>> for f64x4[src]

impl DivAssign<Simd<[f64; 8]>> for f64x8[src]

impl DivAssign<Simd<[i128; 1]>> for i128x1[src]

impl DivAssign<Simd<[i128; 2]>> for i128x2[src]

impl DivAssign<Simd<[i128; 4]>> for i128x4[src]

impl DivAssign<Simd<[i16; 16]>> for i16x16[src]

impl DivAssign<Simd<[i16; 2]>> for i16x2[src]

impl DivAssign<Simd<[i16; 32]>> for i16x32[src]

impl DivAssign<Simd<[i16; 4]>> for i16x4[src]

impl DivAssign<Simd<[i16; 8]>> for i16x8[src]

impl DivAssign<Simd<[i32; 16]>> for i32x16[src]

impl DivAssign<Simd<[i32; 2]>> for i32x2[src]

impl DivAssign<Simd<[i32; 4]>> for i32x4[src]

impl DivAssign<Simd<[i32; 8]>> for i32x8[src]

impl DivAssign<Simd<[i64; 2]>> for i64x2[src]

impl DivAssign<Simd<[i64; 4]>> for i64x4[src]

impl DivAssign<Simd<[i64; 8]>> for i64x8[src]

impl DivAssign<Simd<[i8; 16]>> for i8x16[src]

impl DivAssign<Simd<[i8; 2]>> for i8x2[src]

impl DivAssign<Simd<[i8; 32]>> for i8x32[src]

impl DivAssign<Simd<[i8; 4]>> for i8x4[src]

impl DivAssign<Simd<[i8; 64]>> for i8x64[src]

impl DivAssign<Simd<[i8; 8]>> for i8x8[src]

impl DivAssign<Simd<[isize; 2]>> for isizex2[src]

impl DivAssign<Simd<[isize; 4]>> for isizex4[src]

impl DivAssign<Simd<[isize; 8]>> for isizex8[src]

impl DivAssign<Simd<[u128; 1]>> for u128x1[src]

impl DivAssign<Simd<[u128; 2]>> for u128x2[src]

impl DivAssign<Simd<[u128; 4]>> for u128x4[src]

impl DivAssign<Simd<[u16; 16]>> for u16x16[src]

impl DivAssign<Simd<[u16; 2]>> for u16x2[src]

impl DivAssign<Simd<[u16; 32]>> for u16x32[src]

impl DivAssign<Simd<[u16; 4]>> for u16x4[src]

impl DivAssign<Simd<[u16; 8]>> for u16x8[src]

impl DivAssign<Simd<[u32; 16]>> for u32x16[src]

impl DivAssign<Simd<[u32; 2]>> for u32x2[src]

impl DivAssign<Simd<[u32; 4]>> for u32x4[src]

impl DivAssign<Simd<[u32; 8]>> for u32x8[src]

impl DivAssign<Simd<[u64; 2]>> for u64x2[src]

impl DivAssign<Simd<[u64; 4]>> for u64x4[src]

impl DivAssign<Simd<[u64; 8]>> for u64x8[src]

impl DivAssign<Simd<[u8; 16]>> for u8x16[src]

impl DivAssign<Simd<[u8; 2]>> for u8x2[src]

impl DivAssign<Simd<[u8; 32]>> for u8x32[src]

impl DivAssign<Simd<[u8; 4]>> for u8x4[src]

impl DivAssign<Simd<[u8; 64]>> for u8x64[src]

impl DivAssign<Simd<[u8; 8]>> for u8x8[src]

impl DivAssign<Simd<[usize; 2]>> for usizex2[src]

impl DivAssign<Simd<[usize; 4]>> for usizex4[src]

impl DivAssign<Simd<[usize; 8]>> for usizex8[src]

impl From<Simd<[f32; 16]>> for [f32; 16][src]

impl From<Simd<[f32; 2]>> for [f32; 2][src]

impl From<Simd<[f32; 2]>> for f64x2[src]

impl From<Simd<[f32; 4]>> for [f32; 4][src]

impl From<Simd<[f32; 4]>> for f64x4[src]

impl From<Simd<[f32; 8]>> for [f32; 8][src]

impl From<Simd<[f32; 8]>> for f64x8[src]

impl From<Simd<[f64; 2]>> for [f64; 2][src]

impl From<Simd<[f64; 4]>> for [f64; 4][src]

impl From<Simd<[f64; 8]>> for [f64; 8][src]

impl From<Simd<[i128; 1]>> for [i128; 1][src]

impl From<Simd<[i128; 2]>> for [i128; 2][src]

impl From<Simd<[i128; 4]>> for [i128; 4][src]

impl From<Simd<[i16; 16]>> for [i16; 16][src]

impl From<Simd<[i16; 16]>> for i32x16[src]

impl From<Simd<[i16; 16]>> for f32x16[src]

impl From<Simd<[i16; 2]>> for [i16; 2][src]

impl From<Simd<[i16; 2]>> for i32x2[src]

impl From<Simd<[i16; 2]>> for f32x2[src]

impl From<Simd<[i16; 2]>> for i64x2[src]

impl From<Simd<[i16; 2]>> for f64x2[src]

impl From<Simd<[i16; 2]>> for i128x2[src]

impl From<Simd<[i16; 32]>> for [i16; 32][src]

impl From<Simd<[i16; 4]>> for [i16; 4][src]

impl From<Simd<[i16; 4]>> for i32x4[src]

impl From<Simd<[i16; 4]>> for f32x4[src]

impl From<Simd<[i16; 4]>> for i64x4[src]

impl From<Simd<[i16; 4]>> for f64x4[src]

impl From<Simd<[i16; 4]>> for i128x4[src]

impl From<Simd<[i16; 8]>> for [i16; 8][src]

impl From<Simd<[i16; 8]>> for i32x8[src]

impl From<Simd<[i16; 8]>> for f32x8[src]

impl From<Simd<[i16; 8]>> for i64x8[src]

impl From<Simd<[i16; 8]>> for f64x8[src]

impl From<Simd<[i32; 16]>> for [i32; 16][src]

impl From<Simd<[i32; 2]>> for [i32; 2][src]

impl From<Simd<[i32; 2]>> for i64x2[src]

impl From<Simd<[i32; 2]>> for f64x2[src]

impl From<Simd<[i32; 2]>> for i128x2[src]

impl From<Simd<[i32; 4]>> for [i32; 4][src]

impl From<Simd<[i32; 4]>> for i64x4[src]

impl From<Simd<[i32; 4]>> for f64x4[src]

impl From<Simd<[i32; 4]>> for i128x4[src]

impl From<Simd<[i32; 8]>> for [i32; 8][src]

impl From<Simd<[i32; 8]>> for i64x8[src]

impl From<Simd<[i32; 8]>> for f64x8[src]

impl From<Simd<[i64; 2]>> for [i64; 2][src]

impl From<Simd<[i64; 2]>> for i128x2[src]

impl From<Simd<[i64; 4]>> for [i64; 4][src]

impl From<Simd<[i64; 4]>> for i128x4[src]

impl From<Simd<[i64; 8]>> for [i64; 8][src]

impl From<Simd<[i8; 16]>> for [i8; 16][src]

impl From<Simd<[i8; 16]>> for i16x16[src]

impl From<Simd<[i8; 16]>> for i32x16[src]

impl From<Simd<[i8; 16]>> for f32x16[src]

impl From<Simd<[i8; 2]>> for [i8; 2][src]

impl From<Simd<[i8; 2]>> for i16x2[src]

impl From<Simd<[i8; 2]>> for i32x2[src]

impl From<Simd<[i8; 2]>> for f32x2[src]

impl From<Simd<[i8; 2]>> for i64x2[src]

impl From<Simd<[i8; 2]>> for f64x2[src]

impl From<Simd<[i8; 2]>> for i128x2[src]

impl From<Simd<[i8; 32]>> for [i8; 32][src]

impl From<Simd<[i8; 32]>> for i16x32[src]

impl From<Simd<[i8; 4]>> for [i8; 4][src]

impl From<Simd<[i8; 4]>> for i16x4[src]

impl From<Simd<[i8; 4]>> for i32x4[src]

impl From<Simd<[i8; 4]>> for f32x4[src]

impl From<Simd<[i8; 4]>> for i64x4[src]

impl From<Simd<[i8; 4]>> for f64x4[src]

impl From<Simd<[i8; 4]>> for i128x4[src]

impl From<Simd<[i8; 64]>> for [i8; 64][src]

impl From<Simd<[i8; 8]>> for [i8; 8][src]

impl From<Simd<[i8; 8]>> for i16x8[src]

impl From<Simd<[i8; 8]>> for i32x8[src]

impl From<Simd<[i8; 8]>> for f32x8[src]

impl From<Simd<[i8; 8]>> for i64x8[src]

impl From<Simd<[i8; 8]>> for f64x8[src]

impl From<Simd<[isize; 2]>> for [isize; 2][src]

impl From<Simd<[isize; 4]>> for [isize; 4][src]

impl From<Simd<[isize; 8]>> for [isize; 8][src]

impl From<Simd<[m128; 1]>> for [m128; 1][src]

impl From<Simd<[m128; 2]>> for m8x2[src]

impl From<Simd<[m128; 2]>> for m16x2[src]

impl From<Simd<[m128; 2]>> for m32x2[src]

impl From<Simd<[m128; 2]>> for m64x2[src]

impl From<Simd<[m128; 2]>> for [m128; 2][src]

impl From<Simd<[m128; 4]>> for [m128; 4][src]

impl From<Simd<[m16; 16]>> for m8x16[src]

impl From<Simd<[m16; 16]>> for [m16; 16][src]

impl From<Simd<[m16; 16]>> for m32x16[src]

impl From<Simd<[m16; 2]>> for m8x2[src]

impl From<Simd<[m16; 2]>> for [m16; 2][src]

impl From<Simd<[m16; 2]>> for m32x2[src]

impl From<Simd<[m16; 2]>> for m64x2[src]

impl From<Simd<[m16; 2]>> for m128x2[src]

impl From<Simd<[m16; 32]>> for [m16; 32][src]

impl From<Simd<[m16; 4]>> for m8x4[src]

impl From<Simd<[m16; 4]>> for [m16; 4][src]

impl From<Simd<[m16; 4]>> for m32x4[src]

impl From<Simd<[m16; 4]>> for m64x4[src]

impl From<Simd<[m16; 4]>> for m128x4[src]

impl From<Simd<[m16; 8]>> for m8x8[src]

impl From<Simd<[m16; 8]>> for [m16; 8][src]

impl From<Simd<[m16; 8]>> for m32x8[src]

impl From<Simd<[m16; 8]>> for m64x8[src]

impl From<Simd<[m32; 16]>> for [m32; 16][src]

impl From<Simd<[m32; 2]>> for m8x2[src]

impl From<Simd<[m32; 2]>> for m16x2[src]

impl From<Simd<[m32; 2]>> for [m32; 2][src]

impl From<Simd<[m32; 2]>> for m64x2[src]

impl From<Simd<[m32; 2]>> for m128x2[src]

impl From<Simd<[m32; 4]>> for m8x4[src]

impl From<Simd<[m32; 4]>> for m16x4[src]

impl From<Simd<[m32; 4]>> for [m32; 4][src]

impl From<Simd<[m32; 4]>> for m64x4[src]

impl From<Simd<[m32; 4]>> for m128x4[src]

impl From<Simd<[m32; 8]>> for m8x8[src]

impl From<Simd<[m32; 8]>> for m16x8[src]

impl From<Simd<[m32; 8]>> for [m32; 8][src]

impl From<Simd<[m32; 8]>> for m64x8[src]

impl From<Simd<[m64; 2]>> for m8x2[src]

impl From<Simd<[m64; 2]>> for m16x2[src]

impl From<Simd<[m64; 2]>> for m32x2[src]

impl From<Simd<[m64; 2]>> for [m64; 2][src]

impl From<Simd<[m64; 2]>> for m128x2[src]

impl From<Simd<[m64; 4]>> for m8x4[src]

impl From<Simd<[m64; 4]>> for m16x4[src]

impl From<Simd<[m64; 4]>> for m32x4[src]

impl From<Simd<[m64; 4]>> for [m64; 4][src]

impl From<Simd<[m64; 4]>> for m128x4[src]

impl From<Simd<[m64; 8]>> for [m64; 8][src]

impl From<Simd<[m8; 16]>> for [m8; 16][src]

impl From<Simd<[m8; 16]>> for m16x16[src]

impl From<Simd<[m8; 16]>> for m32x16[src]

impl From<Simd<[m8; 2]>> for [m8; 2][src]

impl From<Simd<[m8; 2]>> for m16x2[src]

impl From<Simd<[m8; 2]>> for m32x2[src]

impl From<Simd<[m8; 2]>> for m64x2[src]

impl From<Simd<[m8; 2]>> for m128x2[src]

impl From<Simd<[m8; 32]>> for [m8; 32][src]

impl From<Simd<[m8; 32]>> for m16x32[src]

impl From<Simd<[m8; 4]>> for [m8; 4][src]

impl From<Simd<[m8; 4]>> for m16x4[src]

impl From<Simd<[m8; 4]>> for m32x4[src]

impl From<Simd<[m8; 4]>> for m64x4[src]

impl From<Simd<[m8; 4]>> for m128x4[src]

impl From<Simd<[m8; 64]>> for [m8; 64][src]

impl From<Simd<[m8; 8]>> for [m8; 8][src]

impl From<Simd<[m8; 8]>> for m16x8[src]

impl From<Simd<[m8; 8]>> for m32x8[src]

impl From<Simd<[m8; 8]>> for m64x8[src]

impl From<Simd<[msize; 2]>> for [msize; 2][src]

impl From<Simd<[msize; 4]>> for [msize; 4][src]

impl From<Simd<[msize; 8]>> for [msize; 8][src]

impl From<Simd<[u128; 1]>> for [u128; 1][src]

impl From<Simd<[u128; 2]>> for [u128; 2][src]

impl From<Simd<[u128; 4]>> for [u128; 4][src]

impl From<Simd<[u16; 16]>> for [u16; 16][src]

impl From<Simd<[u16; 16]>> for i32x16[src]

impl From<Simd<[u16; 16]>> for u32x16[src]

impl From<Simd<[u16; 16]>> for f32x16[src]

impl From<Simd<[u16; 2]>> for [u16; 2][src]

impl From<Simd<[u16; 2]>> for i32x2[src]

impl From<Simd<[u16; 2]>> for u32x2[src]

impl From<Simd<[u16; 2]>> for f32x2[src]

impl From<Simd<[u16; 2]>> for i64x2[src]

impl From<Simd<[u16; 2]>> for u64x2[src]

impl From<Simd<[u16; 2]>> for f64x2[src]

impl From<Simd<[u16; 2]>> for i128x2[src]

impl From<Simd<[u16; 2]>> for u128x2[src]

impl From<Simd<[u16; 32]>> for [u16; 32][src]

impl From<Simd<[u16; 4]>> for [u16; 4][src]

impl From<Simd<[u16; 4]>> for i32x4[src]

impl From<Simd<[u16; 4]>> for u32x4[src]

impl From<Simd<[u16; 4]>> for f32x4[src]

impl From<Simd<[u16; 4]>> for i64x4[src]

impl From<Simd<[u16; 4]>> for u64x4[src]

impl From<Simd<[u16; 4]>> for f64x4[src]

impl From<Simd<[u16; 4]>> for i128x4[src]

impl From<Simd<[u16; 4]>> for u128x4[src]

impl From<Simd<[u16; 8]>> for [u16; 8][src]

impl From<Simd<[u16; 8]>> for i32x8[src]

impl From<Simd<[u16; 8]>> for u32x8[src]

impl From<Simd<[u16; 8]>> for f32x8[src]

impl From<Simd<[u16; 8]>> for i64x8[src]

impl From<Simd<[u16; 8]>> for u64x8[src]

impl From<Simd<[u16; 8]>> for f64x8[src]

impl From<Simd<[u32; 16]>> for [u32; 16][src]

impl From<Simd<[u32; 2]>> for [u32; 2][src]

impl From<Simd<[u32; 2]>> for i64x2[src]

impl From<Simd<[u32; 2]>> for u64x2[src]

impl From<Simd<[u32; 2]>> for f64x2[src]

impl From<Simd<[u32; 2]>> for i128x2[src]

impl From<Simd<[u32; 2]>> for u128x2[src]

impl From<Simd<[u32; 4]>> for [u32; 4][src]

impl From<Simd<[u32; 4]>> for i64x4[src]

impl From<Simd<[u32; 4]>> for u64x4[src]

impl From<Simd<[u32; 4]>> for f64x4[src]

impl From<Simd<[u32; 4]>> for i128x4[src]

impl From<Simd<[u32; 4]>> for u128x4[src]

impl From<Simd<[u32; 8]>> for [u32; 8][src]

impl From<Simd<[u32; 8]>> for i64x8[src]

impl From<Simd<[u32; 8]>> for u64x8[src]

impl From<Simd<[u32; 8]>> for f64x8[src]

impl From<Simd<[u64; 2]>> for [u64; 2][src]

impl From<Simd<[u64; 2]>> for i128x2[src]

impl From<Simd<[u64; 2]>> for u128x2[src]

impl From<Simd<[u64; 4]>> for [u64; 4][src]

impl From<Simd<[u64; 4]>> for i128x4[src]

impl From<Simd<[u64; 4]>> for u128x4[src]

impl From<Simd<[u64; 8]>> for [u64; 8][src]

impl From<Simd<[u8; 16]>> for [u8; 16][src]

impl From<Simd<[u8; 16]>> for i16x16[src]

impl From<Simd<[u8; 16]>> for u16x16[src]

impl From<Simd<[u8; 16]>> for i32x16[src]

impl From<Simd<[u8; 16]>> for u32x16[src]

impl From<Simd<[u8; 16]>> for f32x16[src]

impl From<Simd<[u8; 2]>> for [u8; 2][src]

impl From<Simd<[u8; 2]>> for i16x2[src]

impl From<Simd<[u8; 2]>> for u128x2[src]

impl From<Simd<[u8; 2]>> for u16x2[src]

impl From<Simd<[u8; 2]>> for i32x2[src]

impl From<Simd<[u8; 2]>> for u32x2[src]

impl From<Simd<[u8; 2]>> for f32x2[src]

impl From<Simd<[u8; 2]>> for i64x2[src]

impl From<Simd<[u8; 2]>> for u64x2[src]

impl From<Simd<[u8; 2]>> for f64x2[src]

impl From<Simd<[u8; 2]>> for i128x2[src]

impl From<Simd<[u8; 32]>> for [u8; 32][src]

impl From<Simd<[u8; 32]>> for i16x32[src]

impl From<Simd<[u8; 32]>> for u16x32[src]

impl From<Simd<[u8; 4]>> for [u8; 4][src]

impl From<Simd<[u8; 4]>> for i16x4[src]

impl From<Simd<[u8; 4]>> for u128x4[src]

impl From<Simd<[u8; 4]>> for u16x4[src]

impl From<Simd<[u8; 4]>> for i32x4[src]

impl From<Simd<[u8; 4]>> for u32x4[src]

impl From<Simd<[u8; 4]>> for f32x4[src]

impl From<Simd<[u8; 4]>> for i64x4[src]

impl From<Simd<[u8; 4]>> for u64x4[src]

impl From<Simd<[u8; 4]>> for f64x4[src]

impl From<Simd<[u8; 4]>> for i128x4[src]

impl From<Simd<[u8; 64]>> for [u8; 64][src]

impl From<Simd<[u8; 8]>> for [u8; 8][src]

impl From<Simd<[u8; 8]>> for i16x8[src]

impl From<Simd<[u8; 8]>> for u16x8[src]

impl From<Simd<[u8; 8]>> for i32x8[src]

impl From<Simd<[u8; 8]>> for u32x8[src]

impl From<Simd<[u8; 8]>> for f32x8[src]

impl From<Simd<[u8; 8]>> for i64x8[src]

impl From<Simd<[u8; 8]>> for u64x8[src]

impl From<Simd<[u8; 8]>> for f64x8[src]

impl From<Simd<[usize; 2]>> for [usize; 2][src]

impl From<Simd<[usize; 4]>> for [usize; 4][src]

impl From<Simd<[usize; 8]>> for [usize; 8][src]

impl FromBits<Simd<[f32; 16]>> for i8x64[src]

impl FromBits<Simd<[f32; 16]>> for u8x64[src]

impl FromBits<Simd<[f32; 16]>> for u128x4[src]

impl FromBits<Simd<[f32; 16]>> for i16x32[src]

impl FromBits<Simd<[f32; 16]>> for u16x32[src]

impl FromBits<Simd<[f32; 16]>> for i32x16[src]

impl FromBits<Simd<[f32; 16]>> for u32x16[src]

impl FromBits<Simd<[f32; 16]>> for i64x8[src]

impl FromBits<Simd<[f32; 16]>> for u64x8[src]

impl FromBits<Simd<[f32; 16]>> for f64x8[src]

impl FromBits<Simd<[f32; 16]>> for i128x4[src]

impl FromBits<Simd<[f32; 2]>> for i8x8[src]

impl FromBits<Simd<[f32; 2]>> for u8x8[src]

impl FromBits<Simd<[f32; 2]>> for i16x4[src]

impl FromBits<Simd<[f32; 2]>> for u16x4[src]

impl FromBits<Simd<[f32; 2]>> for i32x2[src]

impl FromBits<Simd<[f32; 2]>> for u32x2[src]

impl FromBits<Simd<[f32; 2]>> for __m64[src]

impl FromBits<Simd<[f32; 4]>> for i8x16[src]

impl FromBits<Simd<[f32; 4]>> for u8x16[src]

impl FromBits<Simd<[f32; 4]>> for u128x1[src]

impl FromBits<Simd<[f32; 4]>> for __m128[src]

impl FromBits<Simd<[f32; 4]>> for __m128i[src]

impl FromBits<Simd<[f32; 4]>> for __m128d[src]

impl FromBits<Simd<[f32; 4]>> for i16x8[src]

impl FromBits<Simd<[f32; 4]>> for u16x8[src]

impl FromBits<Simd<[f32; 4]>> for i32x4[src]

impl FromBits<Simd<[f32; 4]>> for u32x4[src]

impl FromBits<Simd<[f32; 4]>> for i64x2[src]

impl FromBits<Simd<[f32; 4]>> for u64x2[src]

impl FromBits<Simd<[f32; 4]>> for f64x2[src]

impl FromBits<Simd<[f32; 4]>> for i128x1[src]

impl FromBits<Simd<[f32; 8]>> for i8x32[src]

impl FromBits<Simd<[f32; 8]>> for u8x32[src]

impl FromBits<Simd<[f32; 8]>> for u128x2[src]

impl FromBits<Simd<[f32; 8]>> for __m256[src]

impl FromBits<Simd<[f32; 8]>> for __m256i[src]

impl FromBits<Simd<[f32; 8]>> for __m256d[src]

impl FromBits<Simd<[f32; 8]>> for i16x16[src]

impl FromBits<Simd<[f32; 8]>> for u16x16[src]

impl FromBits<Simd<[f32; 8]>> for i32x8[src]

impl FromBits<Simd<[f32; 8]>> for u32x8[src]

impl FromBits<Simd<[f32; 8]>> for i64x4[src]

impl FromBits<Simd<[f32; 8]>> for u64x4[src]

impl FromBits<Simd<[f32; 8]>> for f64x4[src]

impl FromBits<Simd<[f32; 8]>> for i128x2[src]

impl FromBits<Simd<[f64; 2]>> for i8x16[src]

impl FromBits<Simd<[f64; 2]>> for u8x16[src]

impl FromBits<Simd<[f64; 2]>> for u128x1[src]

impl FromBits<Simd<[f64; 2]>> for __m128[src]

impl FromBits<Simd<[f64; 2]>> for __m128i[src]

impl FromBits<Simd<[f64; 2]>> for __m128d[src]

impl FromBits<Simd<[f64; 2]>> for i16x8[src]

impl FromBits<Simd<[f64; 2]>> for u16x8[src]

impl FromBits<Simd<[f64; 2]>> for i32x4[src]

impl FromBits<Simd<[f64; 2]>> for u32x4[src]

impl FromBits<Simd<[f64; 2]>> for f32x4[src]

impl FromBits<Simd<[f64; 2]>> for i64x2[src]

impl FromBits<Simd<[f64; 2]>> for u64x2[src]

impl FromBits<Simd<[f64; 2]>> for i128x1[src]

impl FromBits<Simd<[f64; 4]>> for i8x32[src]

impl FromBits<Simd<[f64; 4]>> for u8x32[src]

impl FromBits<Simd<[f64; 4]>> for u128x2[src]

impl FromBits<Simd<[f64; 4]>> for __m256[src]

impl FromBits<Simd<[f64; 4]>> for __m256i[src]

impl FromBits<Simd<[f64; 4]>> for __m256d[src]

impl FromBits<Simd<[f64; 4]>> for i16x16[src]

impl FromBits<Simd<[f64; 4]>> for u16x16[src]

impl FromBits<Simd<[f64; 4]>> for i32x8[src]

impl FromBits<Simd<[f64; 4]>> for u32x8[src]

impl FromBits<Simd<[f64; 4]>> for f32x8[src]

impl FromBits<Simd<[f64; 4]>> for i64x4[src]

impl FromBits<Simd<[f64; 4]>> for u64x4[src]

impl FromBits<Simd<[f64; 4]>> for i128x2[src]

impl FromBits<Simd<[f64; 8]>> for i8x64[src]

impl FromBits<Simd<[f64; 8]>> for u8x64[src]

impl FromBits<Simd<[f64; 8]>> for u128x4[src]

impl FromBits<Simd<[f64; 8]>> for i16x32[src]

impl FromBits<Simd<[f64; 8]>> for u16x32[src]

impl FromBits<Simd<[f64; 8]>> for i32x16[src]

impl FromBits<Simd<[f64; 8]>> for u32x16[src]

impl FromBits<Simd<[f64; 8]>> for f32x16[src]

impl FromBits<Simd<[f64; 8]>> for i64x8[src]

impl FromBits<Simd<[f64; 8]>> for u64x8[src]

impl FromBits<Simd<[f64; 8]>> for i128x4[src]

impl FromBits<Simd<[i128; 1]>> for i8x16[src]

impl FromBits<Simd<[i128; 1]>> for u8x16[src]

impl FromBits<Simd<[i128; 1]>> for u128x1[src]

impl FromBits<Simd<[i128; 1]>> for __m128[src]

impl FromBits<Simd<[i128; 1]>> for __m128i[src]

impl FromBits<Simd<[i128; 1]>> for __m128d[src]

impl FromBits<Simd<[i128; 1]>> for i16x8[src]

impl FromBits<Simd<[i128; 1]>> for u16x8[src]

impl FromBits<Simd<[i128; 1]>> for i32x4[src]

impl FromBits<Simd<[i128; 1]>> for u32x4[src]

impl FromBits<Simd<[i128; 1]>> for f32x4[src]

impl FromBits<Simd<[i128; 1]>> for i64x2[src]

impl FromBits<Simd<[i128; 1]>> for u64x2[src]

impl FromBits<Simd<[i128; 1]>> for f64x2[src]

impl FromBits<Simd<[i128; 2]>> for i8x32[src]

impl FromBits<Simd<[i128; 2]>> for u8x32[src]

impl FromBits<Simd<[i128; 2]>> for u128x2[src]

impl FromBits<Simd<[i128; 2]>> for __m256[src]

impl FromBits<Simd<[i128; 2]>> for __m256i[src]

impl FromBits<Simd<[i128; 2]>> for __m256d[src]

impl FromBits<Simd<[i128; 2]>> for i16x16[src]

impl FromBits<Simd<[i128; 2]>> for u16x16[src]

impl FromBits<Simd<[i128; 2]>> for i32x8[src]

impl FromBits<Simd<[i128; 2]>> for u32x8[src]

impl FromBits<Simd<[i128; 2]>> for f32x8[src]

impl FromBits<Simd<[i128; 2]>> for i64x4[src]

impl FromBits<Simd<[i128; 2]>> for u64x4[src]

impl FromBits<Simd<[i128; 2]>> for f64x4[src]

impl FromBits<Simd<[i128; 4]>> for i8x64[src]

impl FromBits<Simd<[i128; 4]>> for u8x64[src]

impl FromBits<Simd<[i128; 4]>> for u128x4[src]

impl FromBits<Simd<[i128; 4]>> for i16x32[src]

impl FromBits<Simd<[i128; 4]>> for u16x32[src]

impl FromBits<Simd<[i128; 4]>> for i32x16[src]

impl FromBits<Simd<[i128; 4]>> for u32x16[src]

impl FromBits<Simd<[i128; 4]>> for f32x16[src]

impl FromBits<Simd<[i128; 4]>> for i64x8[src]

impl FromBits<Simd<[i128; 4]>> for u64x8[src]

impl FromBits<Simd<[i128; 4]>> for f64x8[src]

impl FromBits<Simd<[i16; 16]>> for i8x32[src]

impl FromBits<Simd<[i16; 16]>> for u8x32[src]

impl FromBits<Simd<[i16; 16]>> for u128x2[src]

impl FromBits<Simd<[i16; 16]>> for __m256[src]

impl FromBits<Simd<[i16; 16]>> for __m256i[src]

impl FromBits<Simd<[i16; 16]>> for __m256d[src]

impl FromBits<Simd<[i16; 16]>> for u16x16[src]

impl FromBits<Simd<[i16; 16]>> for i32x8[src]

impl FromBits<Simd<[i16; 16]>> for u32x8[src]

impl FromBits<Simd<[i16; 16]>> for f32x8[src]

impl FromBits<Simd<[i16; 16]>> for i64x4[src]

impl FromBits<Simd<[i16; 16]>> for u64x4[src]

impl FromBits<Simd<[i16; 16]>> for f64x4[src]

impl FromBits<Simd<[i16; 16]>> for i128x2[src]

impl FromBits<Simd<[i16; 2]>> for i8x4[src]

impl FromBits<Simd<[i16; 2]>> for u8x4[src]

impl FromBits<Simd<[i16; 2]>> for u16x2[src]

impl FromBits<Simd<[i16; 32]>> for i8x64[src]

impl FromBits<Simd<[i16; 32]>> for u8x64[src]

impl FromBits<Simd<[i16; 32]>> for u128x4[src]

impl FromBits<Simd<[i16; 32]>> for u16x32[src]

impl FromBits<Simd<[i16; 32]>> for i32x16[src]

impl FromBits<Simd<[i16; 32]>> for u32x16[src]

impl FromBits<Simd<[i16; 32]>> for f32x16[src]

impl FromBits<Simd<[i16; 32]>> for i64x8[src]

impl FromBits<Simd<[i16; 32]>> for u64x8[src]

impl FromBits<Simd<[i16; 32]>> for f64x8[src]

impl FromBits<Simd<[i16; 32]>> for i128x4[src]

impl FromBits<Simd<[i16; 4]>> for i8x8[src]

impl FromBits<Simd<[i16; 4]>> for u8x8[src]

impl FromBits<Simd<[i16; 4]>> for u16x4[src]

impl FromBits<Simd<[i16; 4]>> for i32x2[src]

impl FromBits<Simd<[i16; 4]>> for u32x2[src]

impl FromBits<Simd<[i16; 4]>> for f32x2[src]

impl FromBits<Simd<[i16; 4]>> for __m64[src]

impl FromBits<Simd<[i16; 8]>> for i8x16[src]

impl FromBits<Simd<[i16; 8]>> for u8x16[src]

impl FromBits<Simd<[i16; 8]>> for u128x1[src]

impl FromBits<Simd<[i16; 8]>> for __m128[src]

impl FromBits<Simd<[i16; 8]>> for __m128i[src]

impl FromBits<Simd<[i16; 8]>> for __m128d[src]

impl FromBits<Simd<[i16; 8]>> for u16x8[src]

impl FromBits<Simd<[i16; 8]>> for i32x4[src]

impl FromBits<Simd<[i16; 8]>> for u32x4[src]

impl FromBits<Simd<[i16; 8]>> for f32x4[src]

impl FromBits<Simd<[i16; 8]>> for i64x2[src]

impl FromBits<Simd<[i16; 8]>> for u64x2[src]

impl FromBits<Simd<[i16; 8]>> for f64x2[src]

impl FromBits<Simd<[i16; 8]>> for i128x1[src]

impl FromBits<Simd<[i32; 16]>> for i8x64[src]

impl FromBits<Simd<[i32; 16]>> for u8x64[src]

impl FromBits<Simd<[i32; 16]>> for u128x4[src]

impl FromBits<Simd<[i32; 16]>> for i16x32[src]

impl FromBits<Simd<[i32; 16]>> for u16x32[src]

impl FromBits<Simd<[i32; 16]>> for u32x16[src]

impl FromBits<Simd<[i32; 16]>> for f32x16[src]

impl FromBits<Simd<[i32; 16]>> for i64x8[src]

impl FromBits<Simd<[i32; 16]>> for u64x8[src]

impl FromBits<Simd<[i32; 16]>> for f64x8[src]

impl FromBits<Simd<[i32; 16]>> for i128x4[src]

impl FromBits<Simd<[i32; 2]>> for i8x8[src]

impl FromBits<Simd<[i32; 2]>> for u8x8[src]

impl FromBits<Simd<[i32; 2]>> for i16x4[src]

impl FromBits<Simd<[i32; 2]>> for u16x4[src]

impl FromBits<Simd<[i32; 2]>> for u32x2[src]

impl FromBits<Simd<[i32; 2]>> for f32x2[src]

impl FromBits<Simd<[i32; 2]>> for __m64[src]

impl FromBits<Simd<[i32; 4]>> for i8x16[src]

impl FromBits<Simd<[i32; 4]>> for u8x16[src]

impl FromBits<Simd<[i32; 4]>> for u128x1[src]

impl FromBits<Simd<[i32; 4]>> for __m128[src]

impl FromBits<Simd<[i32; 4]>> for __m128i[src]

impl FromBits<Simd<[i32; 4]>> for __m128d[src]

impl FromBits<Simd<[i32; 4]>> for i16x8[src]

impl FromBits<Simd<[i32; 4]>> for u16x8[src]

impl FromBits<Simd<[i32; 4]>> for u32x4[src]

impl FromBits<Simd<[i32; 4]>> for f32x4[src]

impl FromBits<Simd<[i32; 4]>> for i64x2[src]

impl FromBits<Simd<[i32; 4]>> for u64x2[src]

impl FromBits<Simd<[i32; 4]>> for f64x2[src]

impl FromBits<Simd<[i32; 4]>> for i128x1[src]

impl FromBits<Simd<[i32; 8]>> for i8x32[src]

impl FromBits<Simd<[i32; 8]>> for u8x32[src]

impl FromBits<Simd<[i32; 8]>> for u128x2[src]

impl FromBits<Simd<[i32; 8]>> for __m256[src]

impl FromBits<Simd<[i32; 8]>> for __m256i[src]

impl FromBits<Simd<[i32; 8]>> for __m256d[src]

impl FromBits<Simd<[i32; 8]>> for i16x16[src]

impl FromBits<Simd<[i32; 8]>> for u16x16[src]

impl FromBits<Simd<[i32; 8]>> for u32x8[src]

impl FromBits<Simd<[i32; 8]>> for f32x8[src]

impl FromBits<Simd<[i32; 8]>> for i64x4[src]

impl FromBits<Simd<[i32; 8]>> for u64x4[src]

impl FromBits<Simd<[i32; 8]>> for f64x4[src]

impl FromBits<Simd<[i32; 8]>> for i128x2[src]

impl FromBits<Simd<[i64; 2]>> for i8x16[src]

impl FromBits<Simd<[i64; 2]>> for u8x16[src]

impl FromBits<Simd<[i64; 2]>> for u128x1[src]

impl FromBits<Simd<[i64; 2]>> for __m128[src]

impl FromBits<Simd<[i64; 2]>> for __m128i[src]

impl FromBits<Simd<[i64; 2]>> for __m128d[src]

impl FromBits<Simd<[i64; 2]>> for i16x8[src]

impl FromBits<Simd<[i64; 2]>> for u16x8[src]

impl FromBits<Simd<[i64; 2]>> for i32x4[src]

impl FromBits<Simd<[i64; 2]>> for u32x4[src]

impl FromBits<Simd<[i64; 2]>> for f32x4[src]

impl FromBits<Simd<[i64; 2]>> for u64x2[src]

impl FromBits<Simd<[i64; 2]>> for f64x2[src]

impl FromBits<Simd<[i64; 2]>> for i128x1[src]

impl FromBits<Simd<[i64; 4]>> for i8x32[src]

impl FromBits<Simd<[i64; 4]>> for u8x32[src]

impl FromBits<Simd<[i64; 4]>> for u128x2[src]

impl FromBits<Simd<[i64; 4]>> for __m256[src]

impl FromBits<Simd<[i64; 4]>> for __m256i[src]

impl FromBits<Simd<[i64; 4]>> for __m256d[src]

impl FromBits<Simd<[i64; 4]>> for i16x16[src]

impl FromBits<Simd<[i64; 4]>> for u16x16[src]

impl FromBits<Simd<[i64; 4]>> for i32x8[src]

impl FromBits<Simd<[i64; 4]>> for u32x8[src]

impl FromBits<Simd<[i64; 4]>> for f32x8[src]

impl FromBits<Simd<[i64; 4]>> for u64x4[src]

impl FromBits<Simd<[i64; 4]>> for f64x4[src]

impl FromBits<Simd<[i64; 4]>> for i128x2[src]

impl FromBits<Simd<[i64; 8]>> for i8x64[src]

impl FromBits<Simd<[i64; 8]>> for u8x64[src]

impl FromBits<Simd<[i64; 8]>> for u128x4[src]

impl FromBits<Simd<[i64; 8]>> for i16x32[src]

impl FromBits<Simd<[i64; 8]>> for u16x32[src]

impl FromBits<Simd<[i64; 8]>> for i32x16[src]

impl FromBits<Simd<[i64; 8]>> for u32x16[src]

impl FromBits<Simd<[i64; 8]>> for f32x16[src]

impl FromBits<Simd<[i64; 8]>> for u64x8[src]

impl FromBits<Simd<[i64; 8]>> for f64x8[src]

impl FromBits<Simd<[i64; 8]>> for i128x4[src]

impl FromBits<Simd<[i8; 16]>> for u8x16[src]

impl FromBits<Simd<[i8; 16]>> for i16x8[src]

impl FromBits<Simd<[i8; 16]>> for u128x1[src]

impl FromBits<Simd<[i8; 16]>> for __m128[src]

impl FromBits<Simd<[i8; 16]>> for __m128i[src]

impl FromBits<Simd<[i8; 16]>> for __m128d[src]

impl FromBits<Simd<[i8; 16]>> for u16x8[src]

impl FromBits<Simd<[i8; 16]>> for i32x4[src]

impl FromBits<Simd<[i8; 16]>> for u32x4[src]

impl FromBits<Simd<[i8; 16]>> for f32x4[src]

impl FromBits<Simd<[i8; 16]>> for i64x2[src]

impl FromBits<Simd<[i8; 16]>> for u64x2[src]

impl FromBits<Simd<[i8; 16]>> for f64x2[src]

impl FromBits<Simd<[i8; 16]>> for i128x1[src]

impl FromBits<Simd<[i8; 2]>> for u8x2[src]

impl FromBits<Simd<[i8; 32]>> for u8x32[src]

impl FromBits<Simd<[i8; 32]>> for i16x16[src]

impl FromBits<Simd<[i8; 32]>> for u128x2[src]

impl FromBits<Simd<[i8; 32]>> for __m256[src]

impl FromBits<Simd<[i8; 32]>> for __m256i[src]

impl FromBits<Simd<[i8; 32]>> for __m256d[src]

impl FromBits<Simd<[i8; 32]>> for u16x16[src]

impl FromBits<Simd<[i8; 32]>> for i32x8[src]

impl FromBits<Simd<[i8; 32]>> for u32x8[src]

impl FromBits<Simd<[i8; 32]>> for f32x8[src]

impl FromBits<Simd<[i8; 32]>> for i64x4[src]

impl FromBits<Simd<[i8; 32]>> for u64x4[src]

impl FromBits<Simd<[i8; 32]>> for f64x4[src]

impl FromBits<Simd<[i8; 32]>> for i128x2[src]

impl FromBits<Simd<[i8; 4]>> for u8x4[src]

impl FromBits<Simd<[i8; 4]>> for i16x2[src]

impl FromBits<Simd<[i8; 4]>> for u16x2[src]

impl FromBits<Simd<[i8; 64]>> for u8x64[src]

impl FromBits<Simd<[i8; 64]>> for i16x32[src]

impl FromBits<Simd<[i8; 64]>> for u128x4[src]

impl FromBits<Simd<[i8; 64]>> for u16x32[src]

impl FromBits<Simd<[i8; 64]>> for i32x16[src]

impl FromBits<Simd<[i8; 64]>> for u32x16[src]

impl FromBits<Simd<[i8; 64]>> for f32x16[src]

impl FromBits<Simd<[i8; 64]>> for i64x8[src]

impl FromBits<Simd<[i8; 64]>> for u64x8[src]

impl FromBits<Simd<[i8; 64]>> for f64x8[src]

impl FromBits<Simd<[i8; 64]>> for i128x4[src]

impl FromBits<Simd<[i8; 8]>> for u8x8[src]

impl FromBits<Simd<[i8; 8]>> for i16x4[src]

impl FromBits<Simd<[i8; 8]>> for u16x4[src]

impl FromBits<Simd<[i8; 8]>> for i32x2[src]

impl FromBits<Simd<[i8; 8]>> for u32x2[src]

impl FromBits<Simd<[i8; 8]>> for f32x2[src]

impl FromBits<Simd<[i8; 8]>> for __m64[src]

impl FromBits<Simd<[m128; 1]>> for i8x16[src]

impl FromBits<Simd<[m128; 1]>> for u8x16[src]

impl FromBits<Simd<[m128; 1]>> for i64x2[src]

impl FromBits<Simd<[m128; 1]>> for u64x2[src]

impl FromBits<Simd<[m128; 1]>> for f64x2[src]

impl FromBits<Simd<[m128; 1]>> for m64x2[src]

impl FromBits<Simd<[m128; 1]>> for i128x1[src]

impl FromBits<Simd<[m128; 1]>> for u128x1[src]

impl FromBits<Simd<[m128; 1]>> for __m128[src]

impl FromBits<Simd<[m128; 1]>> for __m128i[src]

impl FromBits<Simd<[m128; 1]>> for __m128d[src]

impl FromBits<Simd<[m128; 1]>> for m8x16[src]

impl FromBits<Simd<[m128; 1]>> for i16x8[src]

impl FromBits<Simd<[m128; 1]>> for u16x8[src]

impl FromBits<Simd<[m128; 1]>> for m16x8[src]

impl FromBits<Simd<[m128; 1]>> for i32x4[src]

impl FromBits<Simd<[m128; 1]>> for u32x4[src]

impl FromBits<Simd<[m128; 1]>> for f32x4[src]

impl FromBits<Simd<[m128; 1]>> for m32x4[src]

impl FromBits<Simd<[m128; 2]>> for i8x32[src]

impl FromBits<Simd<[m128; 2]>> for u8x32[src]

impl FromBits<Simd<[m128; 2]>> for i64x4[src]

impl FromBits<Simd<[m128; 2]>> for u64x4[src]

impl FromBits<Simd<[m128; 2]>> for f64x4[src]

impl FromBits<Simd<[m128; 2]>> for m64x4[src]

impl FromBits<Simd<[m128; 2]>> for i128x2[src]

impl FromBits<Simd<[m128; 2]>> for u128x2[src]

impl FromBits<Simd<[m128; 2]>> for __m256[src]

impl FromBits<Simd<[m128; 2]>> for __m256i[src]

impl FromBits<Simd<[m128; 2]>> for __m256d[src]

impl FromBits<Simd<[m128; 2]>> for m8x32[src]

impl FromBits<Simd<[m128; 2]>> for i16x16[src]

impl FromBits<Simd<[m128; 2]>> for u16x16[src]

impl FromBits<Simd<[m128; 2]>> for m16x16[src]

impl FromBits<Simd<[m128; 2]>> for i32x8[src]

impl FromBits<Simd<[m128; 2]>> for u32x8[src]

impl FromBits<Simd<[m128; 2]>> for f32x8[src]

impl FromBits<Simd<[m128; 2]>> for m32x8[src]

impl FromBits<Simd<[m128; 4]>> for i8x64[src]

impl FromBits<Simd<[m128; 4]>> for u8x64[src]

impl FromBits<Simd<[m128; 4]>> for i64x8[src]

impl FromBits<Simd<[m128; 4]>> for u64x8[src]

impl FromBits<Simd<[m128; 4]>> for f64x8[src]

impl FromBits<Simd<[m128; 4]>> for m64x8[src]

impl FromBits<Simd<[m128; 4]>> for i128x4[src]

impl FromBits<Simd<[m128; 4]>> for u128x4[src]

impl FromBits<Simd<[m128; 4]>> for m8x64[src]

impl FromBits<Simd<[m128; 4]>> for i16x32[src]

impl FromBits<Simd<[m128; 4]>> for u16x32[src]

impl FromBits<Simd<[m128; 4]>> for m16x32[src]

impl FromBits<Simd<[m128; 4]>> for i32x16[src]

impl FromBits<Simd<[m128; 4]>> for u32x16[src]

impl FromBits<Simd<[m128; 4]>> for f32x16[src]

impl FromBits<Simd<[m128; 4]>> for m32x16[src]

impl FromBits<Simd<[m16; 16]>> for i8x32[src]

impl FromBits<Simd<[m16; 16]>> for u8x32[src]

impl FromBits<Simd<[m16; 16]>> for f64x4[src]

impl FromBits<Simd<[m16; 16]>> for i128x2[src]

impl FromBits<Simd<[m16; 16]>> for u128x2[src]

impl FromBits<Simd<[m16; 16]>> for __m256[src]

impl FromBits<Simd<[m16; 16]>> for __m256i[src]

impl FromBits<Simd<[m16; 16]>> for __m256d[src]

impl FromBits<Simd<[m16; 16]>> for m8x32[src]

impl FromBits<Simd<[m16; 16]>> for i16x16[src]

impl FromBits<Simd<[m16; 16]>> for u16x16[src]

impl FromBits<Simd<[m16; 16]>> for i32x8[src]

impl FromBits<Simd<[m16; 16]>> for u32x8[src]

impl FromBits<Simd<[m16; 16]>> for f32x8[src]

impl FromBits<Simd<[m16; 16]>> for i64x4[src]

impl FromBits<Simd<[m16; 16]>> for u64x4[src]

impl FromBits<Simd<[m16; 2]>> for i8x4[src]

impl FromBits<Simd<[m16; 2]>> for u8x4[src]

impl FromBits<Simd<[m16; 2]>> for m8x4[src]

impl FromBits<Simd<[m16; 2]>> for i16x2[src]

impl FromBits<Simd<[m16; 2]>> for u16x2[src]

impl FromBits<Simd<[m16; 32]>> for i8x64[src]

impl FromBits<Simd<[m16; 32]>> for u8x64[src]

impl FromBits<Simd<[m16; 32]>> for f64x8[src]

impl FromBits<Simd<[m16; 32]>> for i128x4[src]

impl FromBits<Simd<[m16; 32]>> for u128x4[src]

impl FromBits<Simd<[m16; 32]>> for m8x64[src]

impl FromBits<Simd<[m16; 32]>> for i16x32[src]

impl FromBits<Simd<[m16; 32]>> for u16x32[src]

impl FromBits<Simd<[m16; 32]>> for i32x16[src]

impl FromBits<Simd<[m16; 32]>> for u32x16[src]

impl FromBits<Simd<[m16; 32]>> for f32x16[src]

impl FromBits<Simd<[m16; 32]>> for i64x8[src]

impl FromBits<Simd<[m16; 32]>> for u64x8[src]

impl FromBits<Simd<[m16; 4]>> for i8x8[src]

impl FromBits<Simd<[m16; 4]>> for u8x8[src]

impl FromBits<Simd<[m16; 4]>> for m8x8[src]

impl FromBits<Simd<[m16; 4]>> for i16x4[src]

impl FromBits<Simd<[m16; 4]>> for u16x4[src]

impl FromBits<Simd<[m16; 4]>> for i32x2[src]

impl FromBits<Simd<[m16; 4]>> for u32x2[src]

impl FromBits<Simd<[m16; 4]>> for f32x2[src]

impl FromBits<Simd<[m16; 4]>> for __m64[src]

impl FromBits<Simd<[m16; 8]>> for i8x16[src]

impl FromBits<Simd<[m16; 8]>> for u8x16[src]

impl FromBits<Simd<[m16; 8]>> for f64x2[src]

impl FromBits<Simd<[m16; 8]>> for i128x1[src]

impl FromBits<Simd<[m16; 8]>> for u128x1[src]

impl FromBits<Simd<[m16; 8]>> for __m128[src]

impl FromBits<Simd<[m16; 8]>> for __m128i[src]

impl FromBits<Simd<[m16; 8]>> for __m128d[src]

impl FromBits<Simd<[m16; 8]>> for m8x16[src]

impl FromBits<Simd<[m16; 8]>> for i16x8[src]

impl FromBits<Simd<[m16; 8]>> for u16x8[src]

impl FromBits<Simd<[m16; 8]>> for i32x4[src]

impl FromBits<Simd<[m16; 8]>> for u32x4[src]

impl FromBits<Simd<[m16; 8]>> for f32x4[src]

impl FromBits<Simd<[m16; 8]>> for i64x2[src]

impl FromBits<Simd<[m16; 8]>> for u64x2[src]

impl FromBits<Simd<[m32; 16]>> for i8x64[src]

impl FromBits<Simd<[m32; 16]>> for u8x64[src]

impl FromBits<Simd<[m32; 16]>> for u64x8[src]

impl FromBits<Simd<[m32; 16]>> for f64x8[src]

impl FromBits<Simd<[m32; 16]>> for i128x4[src]

impl FromBits<Simd<[m32; 16]>> for u128x4[src]

impl FromBits<Simd<[m32; 16]>> for m8x64[src]

impl FromBits<Simd<[m32; 16]>> for i16x32[src]

impl FromBits<Simd<[m32; 16]>> for u16x32[src]

impl FromBits<Simd<[m32; 16]>> for m16x32[src]

impl FromBits<Simd<[m32; 16]>> for i32x16[src]

impl FromBits<Simd<[m32; 16]>> for u32x16[src]

impl FromBits<Simd<[m32; 16]>> for f32x16[src]

impl FromBits<Simd<[m32; 16]>> for i64x8[src]

impl FromBits<Simd<[m32; 2]>> for i8x8[src]

impl FromBits<Simd<[m32; 2]>> for u8x8[src]

impl FromBits<Simd<[m32; 2]>> for m8x8[src]

impl FromBits<Simd<[m32; 2]>> for i16x4[src]

impl FromBits<Simd<[m32; 2]>> for u16x4[src]

impl FromBits<Simd<[m32; 2]>> for m16x4[src]

impl FromBits<Simd<[m32; 2]>> for i32x2[src]

impl FromBits<Simd<[m32; 2]>> for u32x2[src]

impl FromBits<Simd<[m32; 2]>> for f32x2[src]

impl FromBits<Simd<[m32; 2]>> for __m64[src]

impl FromBits<Simd<[m32; 4]>> for i8x16[src]

impl FromBits<Simd<[m32; 4]>> for u8x16[src]

impl FromBits<Simd<[m32; 4]>> for u64x2[src]

impl FromBits<Simd<[m32; 4]>> for f64x2[src]

impl FromBits<Simd<[m32; 4]>> for i128x1[src]

impl FromBits<Simd<[m32; 4]>> for u128x1[src]

impl FromBits<Simd<[m32; 4]>> for __m128[src]

impl FromBits<Simd<[m32; 4]>> for __m128i[src]

impl FromBits<Simd<[m32; 4]>> for __m128d[src]

impl FromBits<Simd<[m32; 4]>> for m8x16[src]

impl FromBits<Simd<[m32; 4]>> for i16x8[src]

impl FromBits<Simd<[m32; 4]>> for u16x8[src]

impl FromBits<Simd<[m32; 4]>> for m16x8[src]

impl FromBits<Simd<[m32; 4]>> for i32x4[src]

impl FromBits<Simd<[m32; 4]>> for u32x4[src]

impl FromBits<Simd<[m32; 4]>> for f32x4[src]

impl FromBits<Simd<[m32; 4]>> for i64x2[src]

impl FromBits<Simd<[m32; 8]>> for i8x32[src]

impl FromBits<Simd<[m32; 8]>> for u8x32[src]

impl FromBits<Simd<[m32; 8]>> for u64x4[src]

impl FromBits<Simd<[m32; 8]>> for f64x4[src]

impl FromBits<Simd<[m32; 8]>> for i128x2[src]

impl FromBits<Simd<[m32; 8]>> for u128x2[src]

impl FromBits<Simd<[m32; 8]>> for __m256[src]

impl FromBits<Simd<[m32; 8]>> for __m256i[src]

impl FromBits<Simd<[m32; 8]>> for __m256d[src]

impl FromBits<Simd<[m32; 8]>> for m8x32[src]

impl FromBits<Simd<[m32; 8]>> for i16x16[src]

impl FromBits<Simd<[m32; 8]>> for u16x16[src]

impl FromBits<Simd<[m32; 8]>> for m16x16[src]

impl FromBits<Simd<[m32; 8]>> for i32x8[src]

impl FromBits<Simd<[m32; 8]>> for u32x8[src]

impl FromBits<Simd<[m32; 8]>> for f32x8[src]

impl FromBits<Simd<[m32; 8]>> for i64x4[src]

impl FromBits<Simd<[m64; 2]>> for i8x16[src]

impl FromBits<Simd<[m64; 2]>> for u8x16[src]

impl FromBits<Simd<[m64; 2]>> for i64x2[src]

impl FromBits<Simd<[m64; 2]>> for u64x2[src]

impl FromBits<Simd<[m64; 2]>> for f64x2[src]

impl FromBits<Simd<[m64; 2]>> for i128x1[src]

impl FromBits<Simd<[m64; 2]>> for u128x1[src]

impl FromBits<Simd<[m64; 2]>> for __m128[src]

impl FromBits<Simd<[m64; 2]>> for __m128i[src]

impl FromBits<Simd<[m64; 2]>> for __m128d[src]

impl FromBits<Simd<[m64; 2]>> for m8x16[src]

impl FromBits<Simd<[m64; 2]>> for i16x8[src]

impl FromBits<Simd<[m64; 2]>> for u16x8[src]

impl FromBits<Simd<[m64; 2]>> for m16x8[src]

impl FromBits<Simd<[m64; 2]>> for i32x4[src]

impl FromBits<Simd<[m64; 2]>> for u32x4[src]

impl FromBits<Simd<[m64; 2]>> for f32x4[src]

impl FromBits<Simd<[m64; 2]>> for m32x4[src]

impl FromBits<Simd<[m64; 4]>> for i8x32[src]

impl FromBits<Simd<[m64; 4]>> for u8x32[src]

impl FromBits<Simd<[m64; 4]>> for i64x4[src]

impl FromBits<Simd<[m64; 4]>> for u64x4[src]

impl FromBits<Simd<[m64; 4]>> for f64x4[src]

impl FromBits<Simd<[m64; 4]>> for i128x2[src]

impl FromBits<Simd<[m64; 4]>> for u128x2[src]

impl FromBits<Simd<[m64; 4]>> for __m256[src]

impl FromBits<Simd<[m64; 4]>> for __m256i[src]

impl FromBits<Simd<[m64; 4]>> for __m256d[src]

impl FromBits<Simd<[m64; 4]>> for m8x32[src]

impl FromBits<Simd<[m64; 4]>> for i16x16[src]

impl FromBits<Simd<[m64; 4]>> for u16x16[src]

impl FromBits<Simd<[m64; 4]>> for m16x16[src]

impl FromBits<Simd<[m64; 4]>> for i32x8[src]

impl FromBits<Simd<[m64; 4]>> for u32x8[src]

impl FromBits<Simd<[m64; 4]>> for f32x8[src]

impl FromBits<Simd<[m64; 4]>> for m32x8[src]

impl FromBits<Simd<[m64; 8]>> for i8x64[src]

impl FromBits<Simd<[m64; 8]>> for u8x64[src]

impl FromBits<Simd<[m64; 8]>> for i64x8[src]

impl FromBits<Simd<[m64; 8]>> for u64x8[src]

impl FromBits<Simd<[m64; 8]>> for f64x8[src]

impl FromBits<Simd<[m64; 8]>> for i128x4[src]

impl FromBits<Simd<[m64; 8]>> for u128x4[src]

impl FromBits<Simd<[m64; 8]>> for m8x64[src]

impl FromBits<Simd<[m64; 8]>> for i16x32[src]

impl FromBits<Simd<[m64; 8]>> for u16x32[src]

impl FromBits<Simd<[m64; 8]>> for m16x32[src]

impl FromBits<Simd<[m64; 8]>> for i32x16[src]

impl FromBits<Simd<[m64; 8]>> for u32x16[src]

impl FromBits<Simd<[m64; 8]>> for f32x16[src]

impl FromBits<Simd<[m64; 8]>> for m32x16[src]

impl FromBits<Simd<[m8; 16]>> for i8x16[src]

impl FromBits<Simd<[m8; 16]>> for u8x16[src]

impl FromBits<Simd<[m8; 16]>> for i128x1[src]

impl FromBits<Simd<[m8; 16]>> for u128x1[src]

impl FromBits<Simd<[m8; 16]>> for __m128[src]

impl FromBits<Simd<[m8; 16]>> for __m128i[src]

impl FromBits<Simd<[m8; 16]>> for __m128d[src]

impl FromBits<Simd<[m8; 16]>> for i16x8[src]

impl FromBits<Simd<[m8; 16]>> for u16x8[src]

impl FromBits<Simd<[m8; 16]>> for i32x4[src]

impl FromBits<Simd<[m8; 16]>> for u32x4[src]

impl FromBits<Simd<[m8; 16]>> for f32x4[src]

impl FromBits<Simd<[m8; 16]>> for i64x2[src]

impl FromBits<Simd<[m8; 16]>> for u64x2[src]

impl FromBits<Simd<[m8; 16]>> for f64x2[src]

impl FromBits<Simd<[m8; 2]>> for i8x2[src]

impl FromBits<Simd<[m8; 2]>> for u8x2[src]

impl FromBits<Simd<[m8; 32]>> for i8x32[src]

impl FromBits<Simd<[m8; 32]>> for u8x32[src]

impl FromBits<Simd<[m8; 32]>> for i128x2[src]

impl FromBits<Simd<[m8; 32]>> for u128x2[src]

impl FromBits<Simd<[m8; 32]>> for __m256[src]

impl FromBits<Simd<[m8; 32]>> for __m256i[src]

impl FromBits<Simd<[m8; 32]>> for __m256d[src]

impl FromBits<Simd<[m8; 32]>> for i16x16[src]

impl FromBits<Simd<[m8; 32]>> for u16x16[src]

impl FromBits<Simd<[m8; 32]>> for i32x8[src]

impl FromBits<Simd<[m8; 32]>> for u32x8[src]

impl FromBits<Simd<[m8; 32]>> for f32x8[src]

impl FromBits<Simd<[m8; 32]>> for i64x4[src]

impl FromBits<Simd<[m8; 32]>> for u64x4[src]

impl FromBits<Simd<[m8; 32]>> for f64x4[src]

impl FromBits<Simd<[m8; 4]>> for i8x4[src]

impl FromBits<Simd<[m8; 4]>> for u8x4[src]

impl FromBits<Simd<[m8; 4]>> for i16x2[src]

impl FromBits<Simd<[m8; 4]>> for u16x2[src]

impl FromBits<Simd<[m8; 64]>> for i8x64[src]

impl FromBits<Simd<[m8; 64]>> for u8x64[src]

impl FromBits<Simd<[m8; 64]>> for i128x4[src]

impl FromBits<Simd<[m8; 64]>> for u128x4[src]

impl FromBits<Simd<[m8; 64]>> for i16x32[src]

impl FromBits<Simd<[m8; 64]>> for u16x32[src]

impl FromBits<Simd<[m8; 64]>> for i32x16[src]

impl FromBits<Simd<[m8; 64]>> for u32x16[src]

impl FromBits<Simd<[m8; 64]>> for f32x16[src]

impl FromBits<Simd<[m8; 64]>> for i64x8[src]

impl FromBits<Simd<[m8; 64]>> for u64x8[src]

impl FromBits<Simd<[m8; 64]>> for f64x8[src]

impl FromBits<Simd<[m8; 8]>> for i8x8[src]

impl FromBits<Simd<[m8; 8]>> for u8x8[src]

impl FromBits<Simd<[m8; 8]>> for i16x4[src]

impl FromBits<Simd<[m8; 8]>> for u16x4[src]

impl FromBits<Simd<[m8; 8]>> for i32x2[src]

impl FromBits<Simd<[m8; 8]>> for u32x2[src]

impl FromBits<Simd<[m8; 8]>> for f32x2[src]

impl FromBits<Simd<[m8; 8]>> for __m64[src]

impl FromBits<Simd<[u128; 1]>> for i8x16[src]

impl FromBits<Simd<[u128; 1]>> for u8x16[src]

impl FromBits<Simd<[u128; 1]>> for i128x1[src]

impl FromBits<Simd<[u128; 1]>> for __m128[src]

impl FromBits<Simd<[u128; 1]>> for __m128i[src]

impl FromBits<Simd<[u128; 1]>> for __m128d[src]

impl FromBits<Simd<[u128; 1]>> for i16x8[src]

impl FromBits<Simd<[u128; 1]>> for u16x8[src]

impl FromBits<Simd<[u128; 1]>> for i32x4[src]

impl FromBits<Simd<[u128; 1]>> for u32x4[src]

impl FromBits<Simd<[u128; 1]>> for f32x4[src]

impl FromBits<Simd<[u128; 1]>> for i64x2[src]

impl FromBits<Simd<[u128; 1]>> for u64x2[src]

impl FromBits<Simd<[u128; 1]>> for f64x2[src]

impl FromBits<Simd<[u128; 2]>> for i8x32[src]

impl FromBits<Simd<[u128; 2]>> for u8x32[src]

impl FromBits<Simd<[u128; 2]>> for i128x2[src]

impl FromBits<Simd<[u128; 2]>> for __m256[src]

impl FromBits<Simd<[u128; 2]>> for __m256i[src]

impl FromBits<Simd<[u128; 2]>> for __m256d[src]

impl FromBits<Simd<[u128; 2]>> for i16x16[src]

impl FromBits<Simd<[u128; 2]>> for u16x16[src]

impl FromBits<Simd<[u128; 2]>> for i32x8[src]

impl FromBits<Simd<[u128; 2]>> for u32x8[src]

impl FromBits<Simd<[u128; 2]>> for f32x8[src]

impl FromBits<Simd<[u128; 2]>> for i64x4[src]

impl FromBits<Simd<[u128; 2]>> for u64x4[src]

impl FromBits<Simd<[u128; 2]>> for f64x4[src]

impl FromBits<Simd<[u128; 4]>> for i8x64[src]

impl FromBits<Simd<[u128; 4]>> for u8x64[src]

impl FromBits<Simd<[u128; 4]>> for i128x4[src]

impl FromBits<Simd<[u128; 4]>> for i16x32[src]

impl FromBits<Simd<[u128; 4]>> for u16x32[src]

impl FromBits<Simd<[u128; 4]>> for i32x16[src]

impl FromBits<Simd<[u128; 4]>> for u32x16[src]

impl FromBits<Simd<[u128; 4]>> for f32x16[src]

impl FromBits<Simd<[u128; 4]>> for i64x8[src]

impl FromBits<Simd<[u128; 4]>> for u64x8[src]

impl FromBits<Simd<[u128; 4]>> for f64x8[src]

impl FromBits<Simd<[u16; 16]>> for i8x32[src]

impl FromBits<Simd<[u16; 16]>> for u8x32[src]

impl FromBits<Simd<[u16; 16]>> for u128x2[src]

impl FromBits<Simd<[u16; 16]>> for __m256[src]

impl FromBits<Simd<[u16; 16]>> for __m256i[src]

impl FromBits<Simd<[u16; 16]>> for __m256d[src]

impl FromBits<Simd<[u16; 16]>> for i16x16[src]

impl FromBits<Simd<[u16; 16]>> for i32x8[src]

impl FromBits<Simd<[u16; 16]>> for u32x8[src]

impl FromBits<Simd<[u16; 16]>> for f32x8[src]

impl FromBits<Simd<[u16; 16]>> for i64x4[src]

impl FromBits<Simd<[u16; 16]>> for u64x4[src]

impl FromBits<Simd<[u16; 16]>> for f64x4[src]

impl FromBits<Simd<[u16; 16]>> for i128x2[src]

impl FromBits<Simd<[u16; 2]>> for i8x4[src]

impl FromBits<Simd<[u16; 2]>> for u8x4[src]

impl FromBits<Simd<[u16; 2]>> for i16x2[src]

impl FromBits<Simd<[u16; 32]>> for i8x64[src]

impl FromBits<Simd<[u16; 32]>> for u8x64[src]

impl FromBits<Simd<[u16; 32]>> for u128x4[src]

impl FromBits<Simd<[u16; 32]>> for i16x32[src]

impl FromBits<Simd<[u16; 32]>> for i32x16[src]

impl FromBits<Simd<[u16; 32]>> for u32x16[src]

impl FromBits<Simd<[u16; 32]>> for f32x16[src]

impl FromBits<Simd<[u16; 32]>> for i64x8[src]

impl FromBits<Simd<[u16; 32]>> for u64x8[src]

impl FromBits<Simd<[u16; 32]>> for f64x8[src]

impl FromBits<Simd<[u16; 32]>> for i128x4[src]

impl FromBits<Simd<[u16; 4]>> for i8x8[src]

impl FromBits<Simd<[u16; 4]>> for u8x8[src]

impl FromBits<Simd<[u16; 4]>> for i16x4[src]

impl FromBits<Simd<[u16; 4]>> for i32x2[src]

impl FromBits<Simd<[u16; 4]>> for u32x2[src]

impl FromBits<Simd<[u16; 4]>> for f32x2[src]

impl FromBits<Simd<[u16; 4]>> for __m64[src]

impl FromBits<Simd<[u16; 8]>> for i8x16[src]

impl FromBits<Simd<[u16; 8]>> for u8x16[src]

impl FromBits<Simd<[u16; 8]>> for u128x1[src]

impl FromBits<Simd<[u16; 8]>> for __m128[src]

impl FromBits<Simd<[u16; 8]>> for __m128i[src]

impl FromBits<Simd<[u16; 8]>> for __m128d[src]

impl FromBits<Simd<[u16; 8]>> for i16x8[src]

impl FromBits<Simd<[u16; 8]>> for i32x4[src]

impl FromBits<Simd<[u16; 8]>> for u32x4[src]

impl FromBits<Simd<[u16; 8]>> for f32x4[src]

impl FromBits<Simd<[u16; 8]>> for i64x2[src]

impl FromBits<Simd<[u16; 8]>> for u64x2[src]

impl FromBits<Simd<[u16; 8]>> for f64x2[src]

impl FromBits<Simd<[u16; 8]>> for i128x1[src]

impl FromBits<Simd<[u32; 16]>> for i8x64[src]

impl FromBits<Simd<[u32; 16]>> for u8x64[src]

impl FromBits<Simd<[u32; 16]>> for u128x4[src]

impl FromBits<Simd<[u32; 16]>> for i16x32[src]

impl FromBits<Simd<[u32; 16]>> for u16x32[src]

impl FromBits<Simd<[u32; 16]>> for i32x16[src]

impl FromBits<Simd<[u32; 16]>> for f32x16[src]

impl FromBits<Simd<[u32; 16]>> for i64x8[src]

impl FromBits<Simd<[u32; 16]>> for u64x8[src]

impl FromBits<Simd<[u32; 16]>> for f64x8[src]

impl FromBits<Simd<[u32; 16]>> for i128x4[src]

impl FromBits<Simd<[u32; 2]>> for i8x8[src]

impl FromBits<Simd<[u32; 2]>> for u8x8[src]

impl FromBits<Simd<[u32; 2]>> for i16x4[src]

impl FromBits<Simd<[u32; 2]>> for u16x4[src]

impl FromBits<Simd<[u32; 2]>> for i32x2[src]

impl FromBits<Simd<[u32; 2]>> for f32x2[src]

impl FromBits<Simd<[u32; 2]>> for __m64[src]

impl FromBits<Simd<[u32; 4]>> for i8x16[src]

impl FromBits<Simd<[u32; 4]>> for u8x16[src]

impl FromBits<Simd<[u32; 4]>> for u128x1[src]

impl FromBits<Simd<[u32; 4]>> for __m128[src]

impl FromBits<Simd<[u32; 4]>> for __m128i[src]

impl FromBits<Simd<[u32; 4]>> for __m128d[src]

impl FromBits<Simd<[u32; 4]>> for i16x8[src]

impl FromBits<Simd<[u32; 4]>> for u16x8[src]

impl FromBits<Simd<[u32; 4]>> for i32x4[src]

impl FromBits<Simd<[u32; 4]>> for f32x4[src]

impl FromBits<Simd<[u32; 4]>> for i64x2[src]

impl FromBits<Simd<[u32; 4]>> for u64x2[src]

impl FromBits<Simd<[u32; 4]>> for f64x2[src]

impl FromBits<Simd<[u32; 4]>> for i128x1[src]

impl FromBits<Simd<[u32; 8]>> for i8x32[src]

impl FromBits<Simd<[u32; 8]>> for u8x32[src]

impl FromBits<Simd<[u32; 8]>> for u128x2[src]

impl FromBits<Simd<[u32; 8]>> for __m256[src]

impl FromBits<Simd<[u32; 8]>> for __m256i[src]

impl FromBits<Simd<[u32; 8]>> for __m256d[src]

impl FromBits<Simd<[u32; 8]>> for i16x16[src]

impl FromBits<Simd<[u32; 8]>> for u16x16[src]

impl FromBits<Simd<[u32; 8]>> for i32x8[src]

impl FromBits<Simd<[u32; 8]>> for f32x8[src]

impl FromBits<Simd<[u32; 8]>> for i64x4[src]

impl FromBits<Simd<[u32; 8]>> for u64x4[src]

impl FromBits<Simd<[u32; 8]>> for f64x4[src]

impl FromBits<Simd<[u32; 8]>> for i128x2[src]

impl FromBits<Simd<[u64; 2]>> for i8x16[src]

impl FromBits<Simd<[u64; 2]>> for u8x16[src]

impl FromBits<Simd<[u64; 2]>> for u128x1[src]

impl FromBits<Simd<[u64; 2]>> for __m128[src]

impl FromBits<Simd<[u64; 2]>> for __m128i[src]

impl FromBits<Simd<[u64; 2]>> for __m128d[src]

impl FromBits<Simd<[u64; 2]>> for i16x8[src]

impl FromBits<Simd<[u64; 2]>> for u16x8[src]

impl FromBits<Simd<[u64; 2]>> for i32x4[src]

impl FromBits<Simd<[u64; 2]>> for u32x4[src]

impl FromBits<Simd<[u64; 2]>> for f32x4[src]

impl FromBits<Simd<[u64; 2]>> for i64x2[src]

impl FromBits<Simd<[u64; 2]>> for f64x2[src]

impl FromBits<Simd<[u64; 2]>> for i128x1[src]

impl FromBits<Simd<[u64; 4]>> for i8x32[src]

impl FromBits<Simd<[u64; 4]>> for u8x32[src]

impl FromBits<Simd<[u64; 4]>> for u128x2[src]

impl FromBits<Simd<[u64; 4]>> for __m256[src]

impl FromBits<Simd<[u64; 4]>> for __m256i[src]

impl FromBits<Simd<[u64; 4]>> for __m256d[src]

impl FromBits<Simd<[u64; 4]>> for i16x16[src]

impl FromBits<Simd<[u64; 4]>> for u16x16[src]

impl FromBits<Simd<[u64; 4]>> for i32x8[src]

impl FromBits<Simd<[u64; 4]>> for u32x8[src]

impl FromBits<Simd<[u64; 4]>> for f32x8[src]

impl FromBits<Simd<[u64; 4]>> for i64x4[src]

impl FromBits<Simd<[u64; 4]>> for f64x4[src]

impl FromBits<Simd<[u64; 4]>> for i128x2[src]

impl FromBits<Simd<[u64; 8]>> for i8x64[src]

impl FromBits<Simd<[u64; 8]>> for u8x64[src]

impl FromBits<Simd<[u64; 8]>> for u128x4[src]

impl FromBits<Simd<[u64; 8]>> for i16x32[src]

impl FromBits<Simd<[u64; 8]>> for u16x32[src]

impl FromBits<Simd<[u64; 8]>> for i32x16[src]

impl FromBits<Simd<[u64; 8]>> for u32x16[src]

impl FromBits<Simd<[u64; 8]>> for f32x16[src]

impl FromBits<Simd<[u64; 8]>> for i64x8[src]

impl FromBits<Simd<[u64; 8]>> for f64x8[src]

impl FromBits<Simd<[u64; 8]>> for i128x4[src]

impl FromBits<Simd<[u8; 16]>> for i8x16[src]

impl FromBits<Simd<[u8; 16]>> for i16x8[src]

impl FromBits<Simd<[u8; 16]>> for u128x1[src]

impl FromBits<Simd<[u8; 16]>> for __m128[src]

impl FromBits<Simd<[u8; 16]>> for __m128i[src]

impl FromBits<Simd<[u8; 16]>> for __m128d[src]

impl FromBits<Simd<[u8; 16]>> for u16x8[src]

impl FromBits<Simd<[u8; 16]>> for i32x4[src]

impl FromBits<Simd<[u8; 16]>> for u32x4[src]

impl FromBits<Simd<[u8; 16]>> for f32x4[src]

impl FromBits<Simd<[u8; 16]>> for i64x2[src]

impl FromBits<Simd<[u8; 16]>> for u64x2[src]

impl FromBits<Simd<[u8; 16]>> for f64x2[src]

impl FromBits<Simd<[u8; 16]>> for i128x1[src]

impl FromBits<Simd<[u8; 2]>> for i8x2[src]

impl FromBits<Simd<[u8; 32]>> for i8x32[src]

impl FromBits<Simd<[u8; 32]>> for i16x16[src]

impl FromBits<Simd<[u8; 32]>> for u128x2[src]

impl FromBits<Simd<[u8; 32]>> for __m256[src]

impl FromBits<Simd<[u8; 32]>> for __m256i[src]

impl FromBits<Simd<[u8; 32]>> for __m256d[src]

impl FromBits<Simd<[u8; 32]>> for u16x16[src]

impl FromBits<Simd<[u8; 32]>> for i32x8[src]

impl FromBits<Simd<[u8; 32]>> for u32x8[src]

impl FromBits<Simd<[u8; 32]>> for f32x8[src]

impl FromBits<Simd<[u8; 32]>> for i64x4[src]

impl FromBits<Simd<[u8; 32]>> for u64x4[src]

impl FromBits<Simd<[u8; 32]>> for f64x4[src]

impl FromBits<Simd<[u8; 32]>> for i128x2[src]

impl FromBits<Simd<[u8; 4]>> for i8x4[src]

impl FromBits<Simd<[u8; 4]>> for i16x2[src]

impl FromBits<Simd<[u8; 4]>> for u16x2[src]

impl FromBits<Simd<[u8; 64]>> for i8x64[src]

impl FromBits<Simd<[u8; 64]>> for i16x32[src]

impl FromBits<Simd<[u8; 64]>> for u128x4[src]

impl FromBits<Simd<[u8; 64]>> for u16x32[src]

impl FromBits<Simd<[u8; 64]>> for i32x16[src]

impl FromBits<Simd<[u8; 64]>> for u32x16[src]

impl FromBits<Simd<[u8; 64]>> for f32x16[src]

impl FromBits<Simd<[u8; 64]>> for i64x8[src]

impl FromBits<Simd<[u8; 64]>> for u64x8[src]

impl FromBits<Simd<[u8; 64]>> for f64x8[src]

impl FromBits<Simd<[u8; 64]>> for i128x4[src]

impl FromBits<Simd<[u8; 8]>> for i8x8[src]

impl FromBits<Simd<[u8; 8]>> for i16x4[src]

impl FromBits<Simd<[u8; 8]>> for u16x4[src]

impl FromBits<Simd<[u8; 8]>> for i32x2[src]

impl FromBits<Simd<[u8; 8]>> for u32x2[src]

impl FromBits<Simd<[u8; 8]>> for f32x2[src]

impl FromBits<Simd<[u8; 8]>> for __m64[src]

impl FromCast<Simd<[f32; 16]>> for i8x16[src]

impl FromCast<Simd<[f32; 16]>> for u8x16[src]

impl FromCast<Simd<[f32; 16]>> for m8x16[src]

impl FromCast<Simd<[f32; 16]>> for i16x16[src]

impl FromCast<Simd<[f32; 16]>> for u16x16[src]

impl FromCast<Simd<[f32; 16]>> for m16x16[src]

impl FromCast<Simd<[f32; 16]>> for i32x16[src]

impl FromCast<Simd<[f32; 16]>> for u32x16[src]

impl FromCast<Simd<[f32; 16]>> for m32x16[src]

impl FromCast<Simd<[f32; 2]>> for i8x2[src]

impl FromCast<Simd<[f32; 2]>> for u8x2[src]

impl FromCast<Simd<[f32; 2]>> for u64x2[src]

impl FromCast<Simd<[f32; 2]>> for f64x2[src]

impl FromCast<Simd<[f32; 2]>> for m64x2[src]

impl FromCast<Simd<[f32; 2]>> for isizex2[src]

impl FromCast<Simd<[f32; 2]>> for usizex2[src]

impl FromCast<Simd<[f32; 2]>> for msizex2[src]

impl FromCast<Simd<[f32; 2]>> for i128x2[src]

impl FromCast<Simd<[f32; 2]>> for u128x2[src]

impl FromCast<Simd<[f32; 2]>> for m128x2[src]

impl FromCast<Simd<[f32; 2]>> for m8x2[src]

impl FromCast<Simd<[f32; 2]>> for i16x2[src]

impl FromCast<Simd<[f32; 2]>> for u16x2[src]

impl FromCast<Simd<[f32; 2]>> for m16x2[src]

impl FromCast<Simd<[f32; 2]>> for i32x2[src]

impl FromCast<Simd<[f32; 2]>> for u32x2[src]

impl FromCast<Simd<[f32; 2]>> for m32x2[src]

impl FromCast<Simd<[f32; 2]>> for i64x2[src]

impl FromCast<Simd<[f32; 4]>> for i8x4[src]

impl FromCast<Simd<[f32; 4]>> for u8x4[src]

impl FromCast<Simd<[f32; 4]>> for u64x4[src]

impl FromCast<Simd<[f32; 4]>> for f64x4[src]

impl FromCast<Simd<[f32; 4]>> for m64x4[src]

impl FromCast<Simd<[f32; 4]>> for isizex4[src]

impl FromCast<Simd<[f32; 4]>> for usizex4[src]

impl FromCast<Simd<[f32; 4]>> for msizex4[src]

impl FromCast<Simd<[f32; 4]>> for i128x4[src]

impl FromCast<Simd<[f32; 4]>> for u128x4[src]

impl FromCast<Simd<[f32; 4]>> for m128x4[src]

impl FromCast<Simd<[f32; 4]>> for m8x4[src]

impl FromCast<Simd<[f32; 4]>> for i16x4[src]

impl FromCast<Simd<[f32; 4]>> for u16x4[src]

impl FromCast<Simd<[f32; 4]>> for m16x4[src]

impl FromCast<Simd<[f32; 4]>> for i32x4[src]

impl FromCast<Simd<[f32; 4]>> for u32x4[src]

impl FromCast<Simd<[f32; 4]>> for m32x4[src]

impl FromCast<Simd<[f32; 4]>> for i64x4[src]

impl FromCast<Simd<[f32; 8]>> for i8x8[src]

impl FromCast<Simd<[f32; 8]>> for u8x8[src]

impl FromCast<Simd<[f32; 8]>> for u64x8[src]

impl FromCast<Simd<[f32; 8]>> for f64x8[src]

impl FromCast<Simd<[f32; 8]>> for m64x8[src]

impl FromCast<Simd<[f32; 8]>> for isizex8[src]

impl FromCast<Simd<[f32; 8]>> for usizex8[src]

impl FromCast<Simd<[f32; 8]>> for msizex8[src]

impl FromCast<Simd<[f32; 8]>> for m8x8[src]

impl FromCast<Simd<[f32; 8]>> for i16x8[src]

impl FromCast<Simd<[f32; 8]>> for u16x8[src]

impl FromCast<Simd<[f32; 8]>> for m16x8[src]

impl FromCast<Simd<[f32; 8]>> for i32x8[src]

impl FromCast<Simd<[f32; 8]>> for u32x8[src]

impl FromCast<Simd<[f32; 8]>> for m32x8[src]

impl FromCast<Simd<[f32; 8]>> for i64x8[src]

impl FromCast<Simd<[f64; 2]>> for i8x2[src]

impl FromCast<Simd<[f64; 2]>> for u8x2[src]

impl FromCast<Simd<[f64; 2]>> for i64x2[src]

impl FromCast<Simd<[f64; 2]>> for u64x2[src]

impl FromCast<Simd<[f64; 2]>> for m64x2[src]

impl FromCast<Simd<[f64; 2]>> for isizex2[src]

impl FromCast<Simd<[f64; 2]>> for usizex2[src]

impl FromCast<Simd<[f64; 2]>> for msizex2[src]

impl FromCast<Simd<[f64; 2]>> for i128x2[src]

impl FromCast<Simd<[f64; 2]>> for u128x2[src]

impl FromCast<Simd<[f64; 2]>> for m128x2[src]

impl FromCast<Simd<[f64; 2]>> for m8x2[src]

impl FromCast<Simd<[f64; 2]>> for i16x2[src]

impl FromCast<Simd<[f64; 2]>> for u16x2[src]

impl FromCast<Simd<[f64; 2]>> for m16x2[src]

impl FromCast<Simd<[f64; 2]>> for i32x2[src]

impl FromCast<Simd<[f64; 2]>> for u32x2[src]

impl FromCast<Simd<[f64; 2]>> for f32x2[src]

impl FromCast<Simd<[f64; 2]>> for m32x2[src]

impl FromCast<Simd<[f64; 4]>> for i8x4[src]

impl FromCast<Simd<[f64; 4]>> for u8x4[src]

impl FromCast<Simd<[f64; 4]>> for i64x4[src]

impl FromCast<Simd<[f64; 4]>> for u64x4[src]

impl FromCast<Simd<[f64; 4]>> for m64x4[src]

impl FromCast<Simd<[f64; 4]>> for isizex4[src]

impl FromCast<Simd<[f64; 4]>> for usizex4[src]

impl FromCast<Simd<[f64; 4]>> for msizex4[src]

impl FromCast<Simd<[f64; 4]>> for i128x4[src]

impl FromCast<Simd<[f64; 4]>> for u128x4[src]

impl FromCast<Simd<[f64; 4]>> for m128x4[src]

impl FromCast<Simd<[f64; 4]>> for m8x4[src]

impl FromCast<Simd<[f64; 4]>> for i16x4[src]

impl FromCast<Simd<[f64; 4]>> for u16x4[src]

impl FromCast<Simd<[f64; 4]>> for m16x4[src]

impl FromCast<Simd<[f64; 4]>> for i32x4[src]

impl FromCast<Simd<[f64; 4]>> for u32x4[src]

impl FromCast<Simd<[f64; 4]>> for f32x4[src]

impl FromCast<Simd<[f64; 4]>> for m32x4[src]

impl FromCast<Simd<[f64; 8]>> for i8x8[src]

impl FromCast<Simd<[f64; 8]>> for u8x8[src]

impl FromCast<Simd<[f64; 8]>> for i64x8[src]

impl FromCast<Simd<[f64; 8]>> for u64x8[src]

impl FromCast<Simd<[f64; 8]>> for m64x8[src]

impl FromCast<Simd<[f64; 8]>> for isizex8[src]

impl FromCast<Simd<[f64; 8]>> for usizex8[src]

impl FromCast<Simd<[f64; 8]>> for msizex8[src]

impl FromCast<Simd<[f64; 8]>> for m8x8[src]

impl FromCast<Simd<[f64; 8]>> for i16x8[src]

impl FromCast<Simd<[f64; 8]>> for u16x8[src]

impl FromCast<Simd<[f64; 8]>> for m16x8[src]

impl FromCast<Simd<[f64; 8]>> for i32x8[src]

impl FromCast<Simd<[f64; 8]>> for u32x8[src]

impl FromCast<Simd<[f64; 8]>> for f32x8[src]

impl FromCast<Simd<[f64; 8]>> for m32x8[src]

impl FromCast<Simd<[i128; 1]>> for u128x1[src]

impl FromCast<Simd<[i128; 1]>> for m128x1[src]

impl FromCast<Simd<[i128; 2]>> for i8x2[src]

impl FromCast<Simd<[i128; 2]>> for u8x2[src]

impl FromCast<Simd<[i128; 2]>> for i64x2[src]

impl FromCast<Simd<[i128; 2]>> for u64x2[src]

impl FromCast<Simd<[i128; 2]>> for f64x2[src]

impl FromCast<Simd<[i128; 2]>> for m64x2[src]

impl FromCast<Simd<[i128; 2]>> for isizex2[src]

impl FromCast<Simd<[i128; 2]>> for usizex2[src]

impl FromCast<Simd<[i128; 2]>> for msizex2[src]

impl FromCast<Simd<[i128; 2]>> for u128x2[src]

impl FromCast<Simd<[i128; 2]>> for m128x2[src]

impl FromCast<Simd<[i128; 2]>> for m8x2[src]

impl FromCast<Simd<[i128; 2]>> for i16x2[src]

impl FromCast<Simd<[i128; 2]>> for u16x2[src]

impl FromCast<Simd<[i128; 2]>> for m16x2[src]

impl FromCast<Simd<[i128; 2]>> for i32x2[src]

impl FromCast<Simd<[i128; 2]>> for u32x2[src]

impl FromCast<Simd<[i128; 2]>> for f32x2[src]

impl FromCast<Simd<[i128; 2]>> for m32x2[src]

impl FromCast<Simd<[i128; 4]>> for i8x4[src]

impl FromCast<Simd<[i128; 4]>> for u8x4[src]

impl FromCast<Simd<[i128; 4]>> for i64x4[src]

impl FromCast<Simd<[i128; 4]>> for u64x4[src]

impl FromCast<Simd<[i128; 4]>> for f64x4[src]

impl FromCast<Simd<[i128; 4]>> for m64x4[src]

impl FromCast<Simd<[i128; 4]>> for isizex4[src]

impl FromCast<Simd<[i128; 4]>> for usizex4[src]

impl FromCast<Simd<[i128; 4]>> for msizex4[src]

impl FromCast<Simd<[i128; 4]>> for u128x4[src]

impl FromCast<Simd<[i128; 4]>> for m128x4[src]

impl FromCast<Simd<[i128; 4]>> for m8x4[src]

impl FromCast<Simd<[i128; 4]>> for i16x4[src]

impl FromCast<Simd<[i128; 4]>> for u16x4[src]

impl FromCast<Simd<[i128; 4]>> for m16x4[src]

impl FromCast<Simd<[i128; 4]>> for i32x4[src]

impl FromCast<Simd<[i128; 4]>> for u32x4[src]

impl FromCast<Simd<[i128; 4]>> for f32x4[src]

impl FromCast<Simd<[i128; 4]>> for m32x4[src]

impl FromCast<Simd<[i16; 16]>> for i8x16[src]

impl FromCast<Simd<[i16; 16]>> for u8x16[src]

impl FromCast<Simd<[i16; 16]>> for m8x16[src]

impl FromCast<Simd<[i16; 16]>> for u16x16[src]

impl FromCast<Simd<[i16; 16]>> for m16x16[src]

impl FromCast<Simd<[i16; 16]>> for i32x16[src]

impl FromCast<Simd<[i16; 16]>> for u32x16[src]

impl FromCast<Simd<[i16; 16]>> for f32x16[src]

impl FromCast<Simd<[i16; 16]>> for m32x16[src]

impl FromCast<Simd<[i16; 2]>> for i8x2[src]

impl FromCast<Simd<[i16; 2]>> for u8x2[src]

impl FromCast<Simd<[i16; 2]>> for u64x2[src]

impl FromCast<Simd<[i16; 2]>> for f64x2[src]

impl FromCast<Simd<[i16; 2]>> for m64x2[src]

impl FromCast<Simd<[i16; 2]>> for isizex2[src]

impl FromCast<Simd<[i16; 2]>> for usizex2[src]

impl FromCast<Simd<[i16; 2]>> for msizex2[src]

impl FromCast<Simd<[i16; 2]>> for i128x2[src]

impl FromCast<Simd<[i16; 2]>> for u128x2[src]

impl FromCast<Simd<[i16; 2]>> for m128x2[src]

impl FromCast<Simd<[i16; 2]>> for m8x2[src]

impl FromCast<Simd<[i16; 2]>> for u16x2[src]

impl FromCast<Simd<[i16; 2]>> for m16x2[src]

impl FromCast<Simd<[i16; 2]>> for i32x2[src]

impl FromCast<Simd<[i16; 2]>> for u32x2[src]

impl FromCast<Simd<[i16; 2]>> for f32x2[src]

impl FromCast<Simd<[i16; 2]>> for m32x2[src]

impl FromCast<Simd<[i16; 2]>> for i64x2[src]

impl FromCast<Simd<[i16; 32]>> for i8x32[src]

impl FromCast<Simd<[i16; 32]>> for u8x32[src]

impl FromCast<Simd<[i16; 32]>> for m8x32[src]

impl FromCast<Simd<[i16; 32]>> for u16x32[src]

impl FromCast<Simd<[i16; 32]>> for m16x32[src]

impl FromCast<Simd<[i16; 4]>> for i8x4[src]

impl FromCast<Simd<[i16; 4]>> for u8x4[src]

impl FromCast<Simd<[i16; 4]>> for u64x4[src]

impl FromCast<Simd<[i16; 4]>> for f64x4[src]

impl FromCast<Simd<[i16; 4]>> for m64x4[src]

impl FromCast<Simd<[i16; 4]>> for isizex4[src]

impl FromCast<Simd<[i16; 4]>> for usizex4[src]

impl FromCast<Simd<[i16; 4]>> for msizex4[src]

impl FromCast<Simd<[i16; 4]>> for i128x4[src]

impl FromCast<Simd<[i16; 4]>> for u128x4[src]

impl FromCast<Simd<[i16; 4]>> for m128x4[src]

impl FromCast<Simd<[i16; 4]>> for m8x4[src]

impl FromCast<Simd<[i16; 4]>> for u16x4[src]

impl FromCast<Simd<[i16; 4]>> for m16x4[src]

impl FromCast<Simd<[i16; 4]>> for i32x4[src]

impl FromCast<Simd<[i16; 4]>> for u32x4[src]

impl FromCast<Simd<[i16; 4]>> for f32x4[src]

impl FromCast<Simd<[i16; 4]>> for m32x4[src]

impl FromCast<Simd<[i16; 4]>> for i64x4[src]

impl FromCast<Simd<[i16; 8]>> for i8x8[src]

impl FromCast<Simd<[i16; 8]>> for u8x8[src]

impl FromCast<Simd<[i16; 8]>> for u64x8[src]

impl FromCast<Simd<[i16; 8]>> for f64x8[src]

impl FromCast<Simd<[i16; 8]>> for m64x8[src]

impl FromCast<Simd<[i16; 8]>> for isizex8[src]

impl FromCast<Simd<[i16; 8]>> for usizex8[src]

impl FromCast<Simd<[i16; 8]>> for msizex8[src]

impl FromCast<Simd<[i16; 8]>> for m8x8[src]

impl FromCast<Simd<[i16; 8]>> for u16x8[src]

impl FromCast<Simd<[i16; 8]>> for m16x8[src]

impl FromCast<Simd<[i16; 8]>> for i32x8[src]

impl FromCast<Simd<[i16; 8]>> for u32x8[src]

impl FromCast<Simd<[i16; 8]>> for f32x8[src]

impl FromCast<Simd<[i16; 8]>> for m32x8[src]

impl FromCast<Simd<[i16; 8]>> for i64x8[src]

impl FromCast<Simd<[i32; 16]>> for i8x16[src]

impl FromCast<Simd<[i32; 16]>> for u8x16[src]

impl FromCast<Simd<[i32; 16]>> for m8x16[src]

impl FromCast<Simd<[i32; 16]>> for i16x16[src]

impl FromCast<Simd<[i32; 16]>> for u16x16[src]

impl FromCast<Simd<[i32; 16]>> for m16x16[src]

impl FromCast<Simd<[i32; 16]>> for u32x16[src]

impl FromCast<Simd<[i32; 16]>> for f32x16[src]

impl FromCast<Simd<[i32; 16]>> for m32x16[src]

impl FromCast<Simd<[i32; 2]>> for i8x2[src]

impl FromCast<Simd<[i32; 2]>> for u8x2[src]

impl FromCast<Simd<[i32; 2]>> for u64x2[src]

impl FromCast<Simd<[i32; 2]>> for f64x2[src]

impl FromCast<Simd<[i32; 2]>> for m64x2[src]

impl FromCast<Simd<[i32; 2]>> for isizex2[src]

impl FromCast<Simd<[i32; 2]>> for usizex2[src]

impl FromCast<Simd<[i32; 2]>> for msizex2[src]

impl FromCast<Simd<[i32; 2]>> for i128x2[src]

impl FromCast<Simd<[i32; 2]>> for u128x2[src]

impl FromCast<Simd<[i32; 2]>> for m128x2[src]

impl FromCast<Simd<[i32; 2]>> for m8x2[src]

impl FromCast<Simd<[i32; 2]>> for i16x2[src]

impl FromCast<Simd<[i32; 2]>> for u16x2[src]

impl FromCast<Simd<[i32; 2]>> for m16x2[src]

impl FromCast<Simd<[i32; 2]>> for u32x2[src]

impl FromCast<Simd<[i32; 2]>> for f32x2[src]

impl FromCast<Simd<[i32; 2]>> for m32x2[src]

impl FromCast<Simd<[i32; 2]>> for i64x2[src]

impl FromCast<Simd<[i32; 4]>> for i8x4[src]

impl FromCast<Simd<[i32; 4]>> for u8x4[src]

impl FromCast<Simd<[i32; 4]>> for u64x4[src]

impl FromCast<Simd<[i32; 4]>> for f64x4[src]

impl FromCast<Simd<[i32; 4]>> for m64x4[src]

impl FromCast<Simd<[i32; 4]>> for isizex4[src]

impl FromCast<Simd<[i32; 4]>> for usizex4[src]

impl FromCast<Simd<[i32; 4]>> for msizex4[src]

impl FromCast<Simd<[i32; 4]>> for i128x4[src]

impl FromCast<Simd<[i32; 4]>> for u128x4[src]

impl FromCast<Simd<[i32; 4]>> for m128x4[src]

impl FromCast<Simd<[i32; 4]>> for m8x4[src]

impl FromCast<Simd<[i32; 4]>> for i16x4[src]

impl FromCast<Simd<[i32; 4]>> for u16x4[src]

impl FromCast<Simd<[i32; 4]>> for m16x4[src]

impl FromCast<Simd<[i32; 4]>> for u32x4[src]

impl FromCast<Simd<[i32; 4]>> for f32x4[src]

impl FromCast<Simd<[i32; 4]>> for m32x4[src]

impl FromCast<Simd<[i32; 4]>> for i64x4[src]

impl FromCast<Simd<[i32; 8]>> for i8x8[src]

impl FromCast<Simd<[i32; 8]>> for u8x8[src]

impl FromCast<Simd<[i32; 8]>> for u64x8[src]

impl FromCast<Simd<[i32; 8]>> for f64x8[src]

impl FromCast<Simd<[i32; 8]>> for m64x8[src]

impl FromCast<Simd<[i32; 8]>> for isizex8[src]

impl FromCast<Simd<[i32; 8]>> for usizex8[src]

impl FromCast<Simd<[i32; 8]>> for msizex8[src]

impl FromCast<Simd<[i32; 8]>> for m8x8[src]

impl FromCast<Simd<[i32; 8]>> for i16x8[src]

impl FromCast<Simd<[i32; 8]>> for u16x8[src]

impl FromCast<Simd<[i32; 8]>> for m16x8[src]

impl FromCast<Simd<[i32; 8]>> for u32x8[src]

impl FromCast<Simd<[i32; 8]>> for f32x8[src]

impl FromCast<Simd<[i32; 8]>> for m32x8[src]

impl FromCast<Simd<[i32; 8]>> for i64x8[src]

impl FromCast<Simd<[i64; 2]>> for i8x2[src]

impl FromCast<Simd<[i64; 2]>> for u8x2[src]

impl FromCast<Simd<[i64; 2]>> for u64x2[src]

impl FromCast<Simd<[i64; 2]>> for f64x2[src]

impl FromCast<Simd<[i64; 2]>> for m64x2[src]

impl FromCast<Simd<[i64; 2]>> for isizex2[src]

impl FromCast<Simd<[i64; 2]>> for usizex2[src]

impl FromCast<Simd<[i64; 2]>> for msizex2[src]

impl FromCast<Simd<[i64; 2]>> for i128x2[src]

impl FromCast<Simd<[i64; 2]>> for u128x2[src]

impl FromCast<Simd<[i64; 2]>> for m128x2[src]

impl FromCast<Simd<[i64; 2]>> for m8x2[src]

impl FromCast<Simd<[i64; 2]>> for i16x2[src]

impl FromCast<Simd<[i64; 2]>> for u16x2[src]

impl FromCast<Simd<[i64; 2]>> for m16x2[src]

impl FromCast<Simd<[i64; 2]>> for i32x2[src]

impl FromCast<Simd<[i64; 2]>> for u32x2[src]

impl FromCast<Simd<[i64; 2]>> for f32x2[src]

impl FromCast<Simd<[i64; 2]>> for m32x2[src]

impl FromCast<Simd<[i64; 4]>> for i8x4[src]

impl FromCast<Simd<[i64; 4]>> for u8x4[src]

impl FromCast<Simd<[i64; 4]>> for u64x4[src]

impl FromCast<Simd<[i64; 4]>> for f64x4[src]

impl FromCast<Simd<[i64; 4]>> for m64x4[src]

impl FromCast<Simd<[i64; 4]>> for isizex4[src]

impl FromCast<Simd<[i64; 4]>> for usizex4[src]

impl FromCast<Simd<[i64; 4]>> for msizex4[src]

impl FromCast<Simd<[i64; 4]>> for i128x4[src]

impl FromCast<Simd<[i64; 4]>> for u128x4[src]

impl FromCast<Simd<[i64; 4]>> for m128x4[src]

impl FromCast<Simd<[i64; 4]>> for m8x4[src]

impl FromCast<Simd<[i64; 4]>> for i16x4[src]

impl FromCast<Simd<[i64; 4]>> for u16x4[src]

impl FromCast<Simd<[i64; 4]>> for m16x4[src]

impl FromCast<Simd<[i64; 4]>> for i32x4[src]

impl FromCast<Simd<[i64; 4]>> for u32x4[src]

impl FromCast<Simd<[i64; 4]>> for f32x4[src]

impl FromCast<Simd<[i64; 4]>> for m32x4[src]

impl FromCast<Simd<[i64; 8]>> for i8x8[src]

impl FromCast<Simd<[i64; 8]>> for u8x8[src]

impl FromCast<Simd<[i64; 8]>> for u64x8[src]

impl FromCast<Simd<[i64; 8]>> for f64x8[src]

impl FromCast<Simd<[i64; 8]>> for m64x8[src]

impl FromCast<Simd<[i64; 8]>> for isizex8[src]

impl FromCast<Simd<[i64; 8]>> for usizex8[src]

impl FromCast<Simd<[i64; 8]>> for msizex8[src]

impl FromCast<Simd<[i64; 8]>> for m8x8[src]

impl FromCast<Simd<[i64; 8]>> for i16x8[src]

impl FromCast<Simd<[i64; 8]>> for u16x8[src]

impl FromCast<Simd<[i64; 8]>> for m16x8[src]

impl FromCast<Simd<[i64; 8]>> for i32x8[src]

impl FromCast<Simd<[i64; 8]>> for u32x8[src]

impl FromCast<Simd<[i64; 8]>> for f32x8[src]

impl FromCast<Simd<[i64; 8]>> for m32x8[src]

impl FromCast<Simd<[i8; 16]>> for u8x16[src]

impl FromCast<Simd<[i8; 16]>> for m8x16[src]

impl FromCast<Simd<[i8; 16]>> for i16x16[src]

impl FromCast<Simd<[i8; 16]>> for u16x16[src]

impl FromCast<Simd<[i8; 16]>> for m16x16[src]

impl FromCast<Simd<[i8; 16]>> for i32x16[src]

impl FromCast<Simd<[i8; 16]>> for u32x16[src]

impl FromCast<Simd<[i8; 16]>> for f32x16[src]

impl FromCast<Simd<[i8; 16]>> for m32x16[src]

impl FromCast<Simd<[i8; 2]>> for u8x2[src]

impl FromCast<Simd<[i8; 2]>> for m8x2[src]

impl FromCast<Simd<[i8; 2]>> for u64x2[src]

impl FromCast<Simd<[i8; 2]>> for f64x2[src]

impl FromCast<Simd<[i8; 2]>> for m64x2[src]

impl FromCast<Simd<[i8; 2]>> for isizex2[src]

impl FromCast<Simd<[i8; 2]>> for usizex2[src]

impl FromCast<Simd<[i8; 2]>> for msizex2[src]

impl FromCast<Simd<[i8; 2]>> for i128x2[src]

impl FromCast<Simd<[i8; 2]>> for u128x2[src]

impl FromCast<Simd<[i8; 2]>> for m128x2[src]

impl FromCast<Simd<[i8; 2]>> for i16x2[src]

impl FromCast<Simd<[i8; 2]>> for u16x2[src]

impl FromCast<Simd<[i8; 2]>> for m16x2[src]

impl FromCast<Simd<[i8; 2]>> for i32x2[src]

impl FromCast<Simd<[i8; 2]>> for u32x2[src]

impl FromCast<Simd<[i8; 2]>> for f32x2[src]

impl FromCast<Simd<[i8; 2]>> for m32x2[src]

impl FromCast<Simd<[i8; 2]>> for i64x2[src]

impl FromCast<Simd<[i8; 32]>> for u8x32[src]

impl FromCast<Simd<[i8; 32]>> for m8x32[src]

impl FromCast<Simd<[i8; 32]>> for i16x32[src]

impl FromCast<Simd<[i8; 32]>> for u16x32[src]

impl FromCast<Simd<[i8; 32]>> for m16x32[src]

impl FromCast<Simd<[i8; 4]>> for u8x4[src]

impl FromCast<Simd<[i8; 4]>> for m8x4[src]

impl FromCast<Simd<[i8; 4]>> for u64x4[src]

impl FromCast<Simd<[i8; 4]>> for f64x4[src]

impl FromCast<Simd<[i8; 4]>> for m64x4[src]

impl FromCast<Simd<[i8; 4]>> for isizex4[src]

impl FromCast<Simd<[i8; 4]>> for usizex4[src]

impl FromCast<Simd<[i8; 4]>> for msizex4[src]

impl FromCast<Simd<[i8; 4]>> for i128x4[src]

impl FromCast<Simd<[i8; 4]>> for u128x4[src]

impl FromCast<Simd<[i8; 4]>> for m128x4[src]

impl FromCast<Simd<[i8; 4]>> for i16x4[src]

impl FromCast<Simd<[i8; 4]>> for u16x4[src]

impl FromCast<Simd<[i8; 4]>> for m16x4[src]

impl FromCast<Simd<[i8; 4]>> for i32x4[src]

impl FromCast<Simd<[i8; 4]>> for u32x4[src]

impl FromCast<Simd<[i8; 4]>> for f32x4[src]

impl FromCast<Simd<[i8; 4]>> for m32x4[src]

impl FromCast<Simd<[i8; 4]>> for i64x4[src]

impl FromCast<Simd<[i8; 64]>> for u8x64[src]

impl FromCast<Simd<[i8; 64]>> for m8x64[src]

impl FromCast<Simd<[i8; 8]>> for u8x8[src]

impl FromCast<Simd<[i8; 8]>> for m8x8[src]

impl FromCast<Simd<[i8; 8]>> for u64x8[src]

impl FromCast<Simd<[i8; 8]>> for f64x8[src]

impl FromCast<Simd<[i8; 8]>> for m64x8[src]

impl FromCast<Simd<[i8; 8]>> for isizex8[src]

impl FromCast<Simd<[i8; 8]>> for usizex8[src]

impl FromCast<Simd<[i8; 8]>> for msizex8[src]

impl FromCast<Simd<[i8; 8]>> for i16x8[src]

impl FromCast<Simd<[i8; 8]>> for u16x8[src]

impl FromCast<Simd<[i8; 8]>> for m16x8[src]

impl FromCast<Simd<[i8; 8]>> for i32x8[src]

impl FromCast<Simd<[i8; 8]>> for u32x8[src]

impl FromCast<Simd<[i8; 8]>> for f32x8[src]

impl FromCast<Simd<[i8; 8]>> for m32x8[src]

impl FromCast<Simd<[i8; 8]>> for i64x8[src]

impl FromCast<Simd<[isize; 2]>> for i8x2[src]

impl FromCast<Simd<[isize; 2]>> for u8x2[src]

impl FromCast<Simd<[isize; 2]>> for i64x2[src]

impl FromCast<Simd<[isize; 2]>> for u64x2[src]

impl FromCast<Simd<[isize; 2]>> for f64x2[src]

impl FromCast<Simd<[isize; 2]>> for m64x2[src]

impl FromCast<Simd<[isize; 2]>> for usizex2[src]

impl FromCast<Simd<[isize; 2]>> for msizex2[src]

impl FromCast<Simd<[isize; 2]>> for i128x2[src]

impl FromCast<Simd<[isize; 2]>> for u128x2[src]

impl FromCast<Simd<[isize; 2]>> for m128x2[src]

impl FromCast<Simd<[isize; 2]>> for m8x2[src]

impl FromCast<Simd<[isize; 2]>> for i16x2[src]

impl FromCast<Simd<[isize; 2]>> for u16x2[src]

impl FromCast<Simd<[isize; 2]>> for m16x2[src]

impl FromCast<Simd<[isize; 2]>> for i32x2[src]

impl FromCast<Simd<[isize; 2]>> for u32x2[src]

impl FromCast<Simd<[isize; 2]>> for f32x2[src]

impl FromCast<Simd<[isize; 2]>> for m32x2[src]

impl FromCast<Simd<[isize; 4]>> for i8x4[src]

impl FromCast<Simd<[isize; 4]>> for u8x4[src]

impl FromCast<Simd<[isize; 4]>> for i64x4[src]

impl FromCast<Simd<[isize; 4]>> for u64x4[src]

impl FromCast<Simd<[isize; 4]>> for f64x4[src]

impl FromCast<Simd<[isize; 4]>> for m64x4[src]

impl FromCast<Simd<[isize; 4]>> for usizex4[src]

impl FromCast<Simd<[isize; 4]>> for msizex4[src]

impl FromCast<Simd<[isize; 4]>> for i128x4[src]

impl FromCast<Simd<[isize; 4]>> for u128x4[src]

impl FromCast<Simd<[isize; 4]>> for m128x4[src]

impl FromCast<Simd<[isize; 4]>> for m8x4[src]

impl FromCast<Simd<[isize; 4]>> for i16x4[src]

impl FromCast<Simd<[isize; 4]>> for u16x4[src]

impl FromCast<Simd<[isize; 4]>> for m16x4[src]

impl FromCast<Simd<[isize; 4]>> for i32x4[src]

impl FromCast<Simd<[isize; 4]>> for u32x4[src]

impl FromCast<Simd<[isize; 4]>> for f32x4[src]

impl FromCast<Simd<[isize; 4]>> for m32x4[src]

impl FromCast<Simd<[isize; 8]>> for i8x8[src]

impl FromCast<Simd<[isize; 8]>> for u8x8[src]

impl FromCast<Simd<[isize; 8]>> for i64x8[src]

impl FromCast<Simd<[isize; 8]>> for u64x8[src]

impl FromCast<Simd<[isize; 8]>> for f64x8[src]

impl FromCast<Simd<[isize; 8]>> for m64x8[src]

impl FromCast<Simd<[isize; 8]>> for usizex8[src]

impl FromCast<Simd<[isize; 8]>> for msizex8[src]

impl FromCast<Simd<[isize; 8]>> for m8x8[src]

impl FromCast<Simd<[isize; 8]>> for i16x8[src]

impl FromCast<Simd<[isize; 8]>> for u16x8[src]

impl FromCast<Simd<[isize; 8]>> for m16x8[src]

impl FromCast<Simd<[isize; 8]>> for i32x8[src]

impl FromCast<Simd<[isize; 8]>> for u32x8[src]

impl FromCast<Simd<[isize; 8]>> for f32x8[src]

impl FromCast<Simd<[isize; 8]>> for m32x8[src]

impl FromCast<Simd<[m128; 1]>> for i128x1[src]

impl FromCast<Simd<[m128; 1]>> for u128x1[src]

impl FromCast<Simd<[m128; 2]>> for i8x2[src]

impl FromCast<Simd<[m128; 2]>> for u8x2[src]

impl FromCast<Simd<[m128; 2]>> for i64x2[src]

impl FromCast<Simd<[m128; 2]>> for u64x2[src]

impl FromCast<Simd<[m128; 2]>> for f64x2[src]

impl FromCast<Simd<[m128; 2]>> for m64x2[src]

impl FromCast<Simd<[m128; 2]>> for isizex2[src]

impl FromCast<Simd<[m128; 2]>> for usizex2[src]

impl FromCast<Simd<[m128; 2]>> for msizex2[src]

impl FromCast<Simd<[m128; 2]>> for i128x2[src]

impl FromCast<Simd<[m128; 2]>> for u128x2[src]

impl FromCast<Simd<[m128; 2]>> for m8x2[src]

impl FromCast<Simd<[m128; 2]>> for i16x2[src]

impl FromCast<Simd<[m128; 2]>> for u16x2[src]

impl FromCast<Simd<[m128; 2]>> for m16x2[src]

impl FromCast<Simd<[m128; 2]>> for i32x2[src]

impl FromCast<Simd<[m128; 2]>> for u32x2[src]

impl FromCast<Simd<[m128; 2]>> for f32x2[src]

impl FromCast<Simd<[m128; 2]>> for m32x2[src]

impl FromCast<Simd<[m128; 4]>> for i8x4[src]

impl FromCast<Simd<[m128; 4]>> for u8x4[src]

impl FromCast<Simd<[m128; 4]>> for i64x4[src]

impl FromCast<Simd<[m128; 4]>> for u64x4[src]

impl FromCast<Simd<[m128; 4]>> for f64x4[src]

impl FromCast<Simd<[m128; 4]>> for m64x4[src]

impl FromCast<Simd<[m128; 4]>> for isizex4[src]

impl FromCast<Simd<[m128; 4]>> for usizex4[src]

impl FromCast<Simd<[m128; 4]>> for msizex4[src]

impl FromCast<Simd<[m128; 4]>> for i128x4[src]

impl FromCast<Simd<[m128; 4]>> for u128x4[src]

impl FromCast<Simd<[m128; 4]>> for m8x4[src]

impl FromCast<Simd<[m128; 4]>> for i16x4[src]

impl FromCast<Simd<[m128; 4]>> for u16x4[src]

impl FromCast<Simd<[m128; 4]>> for m16x4[src]

impl FromCast<Simd<[m128; 4]>> for i32x4[src]

impl FromCast<Simd<[m128; 4]>> for u32x4[src]

impl FromCast<Simd<[m128; 4]>> for f32x4[src]

impl FromCast<Simd<[m128; 4]>> for m32x4[src]

impl FromCast<Simd<[m16; 16]>> for i8x16[src]

impl FromCast<Simd<[m16; 16]>> for u8x16[src]

impl FromCast<Simd<[m16; 16]>> for m8x16[src]

impl FromCast<Simd<[m16; 16]>> for i16x16[src]

impl FromCast<Simd<[m16; 16]>> for u16x16[src]

impl FromCast<Simd<[m16; 16]>> for i32x16[src]

impl FromCast<Simd<[m16; 16]>> for u32x16[src]

impl FromCast<Simd<[m16; 16]>> for f32x16[src]

impl FromCast<Simd<[m16; 16]>> for m32x16[src]

impl FromCast<Simd<[m16; 2]>> for i8x2[src]

impl FromCast<Simd<[m16; 2]>> for u8x2[src]

impl FromCast<Simd<[m16; 2]>> for u64x2[src]

impl FromCast<Simd<[m16; 2]>> for f64x2[src]

impl FromCast<Simd<[m16; 2]>> for m64x2[src]

impl FromCast<Simd<[m16; 2]>> for isizex2[src]

impl FromCast<Simd<[m16; 2]>> for usizex2[src]

impl FromCast<Simd<[m16; 2]>> for msizex2[src]

impl FromCast<Simd<[m16; 2]>> for i128x2[src]

impl FromCast<Simd<[m16; 2]>> for u128x2[src]

impl FromCast<Simd<[m16; 2]>> for m128x2[src]

impl FromCast<Simd<[m16; 2]>> for m8x2[src]

impl FromCast<Simd<[m16; 2]>> for i16x2[src]

impl FromCast<Simd<[m16; 2]>> for u16x2[src]

impl FromCast<Simd<[m16; 2]>> for i32x2[src]

impl FromCast<Simd<[m16; 2]>> for u32x2[src]

impl FromCast<Simd<[m16; 2]>> for f32x2[src]

impl FromCast<Simd<[m16; 2]>> for m32x2[src]

impl FromCast<Simd<[m16; 2]>> for i64x2[src]

impl FromCast<Simd<[m16; 32]>> for i8x32[src]

impl FromCast<Simd<[m16; 32]>> for u8x32[src]

impl FromCast<Simd<[m16; 32]>> for m8x32[src]

impl FromCast<Simd<[m16; 32]>> for i16x32[src]

impl FromCast<Simd<[m16; 32]>> for u16x32[src]

impl FromCast<Simd<[m16; 4]>> for i8x4[src]

impl FromCast<Simd<[m16; 4]>> for u8x4[src]

impl FromCast<Simd<[m16; 4]>> for u64x4[src]

impl FromCast<Simd<[m16; 4]>> for f64x4[src]

impl FromCast<Simd<[m16; 4]>> for m64x4[src]

impl FromCast<Simd<[m16; 4]>> for isizex4[src]

impl FromCast<Simd<[m16; 4]>> for usizex4[src]

impl FromCast<Simd<[m16; 4]>> for msizex4[src]

impl FromCast<Simd<[m16; 4]>> for i128x4[src]

impl FromCast<Simd<[m16; 4]>> for u128x4[src]

impl FromCast<Simd<[m16; 4]>> for m128x4[src]

impl FromCast<Simd<[m16; 4]>> for m8x4[src]

impl FromCast<Simd<[m16; 4]>> for i16x4[src]

impl FromCast<Simd<[m16; 4]>> for u16x4[src]

impl FromCast<Simd<[m16; 4]>> for i32x4[src]

impl FromCast<Simd<[m16; 4]>> for u32x4[src]

impl FromCast<Simd<[m16; 4]>> for f32x4[src]

impl FromCast<Simd<[m16; 4]>> for m32x4[src]

impl FromCast<Simd<[m16; 4]>> for i64x4[src]

impl FromCast<Simd<[m16; 8]>> for i8x8[src]

impl FromCast<Simd<[m16; 8]>> for u8x8[src]

impl FromCast<Simd<[m16; 8]>> for u64x8[src]

impl FromCast<Simd<[m16; 8]>> for f64x8[src]

impl FromCast<Simd<[m16; 8]>> for m64x8[src]

impl FromCast<Simd<[m16; 8]>> for isizex8[src]

impl FromCast<Simd<[m16; 8]>> for usizex8[src]

impl FromCast<Simd<[m16; 8]>> for msizex8[src]

impl FromCast<Simd<[m16; 8]>> for m8x8[src]

impl FromCast<Simd<[m16; 8]>> for i16x8[src]

impl FromCast<Simd<[m16; 8]>> for u16x8[src]

impl FromCast<Simd<[m16; 8]>> for i32x8[src]

impl FromCast<Simd<[m16; 8]>> for u32x8[src]

impl FromCast<Simd<[m16; 8]>> for f32x8[src]

impl FromCast<Simd<[m16; 8]>> for m32x8[src]

impl FromCast<Simd<[m16; 8]>> for i64x8[src]

impl FromCast<Simd<[m32; 16]>> for i8x16[src]

impl FromCast<Simd<[m32; 16]>> for u8x16[src]

impl FromCast<Simd<[m32; 16]>> for m8x16[src]

impl FromCast<Simd<[m32; 16]>> for i16x16[src]

impl FromCast<Simd<[m32; 16]>> for u16x16[src]

impl FromCast<Simd<[m32; 16]>> for m16x16[src]

impl FromCast<Simd<[m32; 16]>> for i32x16[src]

impl FromCast<Simd<[m32; 16]>> for u32x16[src]

impl FromCast<Simd<[m32; 16]>> for f32x16[src]

impl FromCast<Simd<[m32; 2]>> for i8x2[src]

impl FromCast<Simd<[m32; 2]>> for u8x2[src]

impl FromCast<Simd<[m32; 2]>> for u64x2[src]

impl FromCast<Simd<[m32; 2]>> for f64x2[src]

impl FromCast<Simd<[m32; 2]>> for m64x2[src]

impl FromCast<Simd<[m32; 2]>> for isizex2[src]

impl FromCast<Simd<[m32; 2]>> for usizex2[src]

impl FromCast<Simd<[m32; 2]>> for msizex2[src]

impl FromCast<Simd<[m32; 2]>> for i128x2[src]

impl FromCast<Simd<[m32; 2]>> for u128x2[src]

impl FromCast<Simd<[m32; 2]>> for m128x2[src]

impl FromCast<Simd<[m32; 2]>> for m8x2[src]

impl FromCast<Simd<[m32; 2]>> for i16x2[src]

impl FromCast<Simd<[m32; 2]>> for u16x2[src]

impl FromCast<Simd<[m32; 2]>> for m16x2[src]

impl FromCast<Simd<[m32; 2]>> for i32x2[src]

impl FromCast<Simd<[m32; 2]>> for u32x2[src]

impl FromCast<Simd<[m32; 2]>> for f32x2[src]

impl FromCast<Simd<[m32; 2]>> for i64x2[src]

impl FromCast<Simd<[m32; 4]>> for i8x4[src]

impl FromCast<Simd<[m32; 4]>> for u8x4[src]

impl FromCast<Simd<[m32; 4]>> for u64x4[src]

impl FromCast<Simd<[m32; 4]>> for f64x4[src]

impl FromCast<Simd<[m32; 4]>> for m64x4[src]

impl FromCast<Simd<[m32; 4]>> for isizex4[src]

impl FromCast<Simd<[m32; 4]>> for usizex4[src]

impl FromCast<Simd<[m32; 4]>> for msizex4[src]

impl FromCast<Simd<[m32; 4]>> for i128x4[src]

impl FromCast<Simd<[m32; 4]>> for u128x4[src]

impl FromCast<Simd<[m32; 4]>> for m128x4[src]

impl FromCast<Simd<[m32; 4]>> for m8x4[src]

impl FromCast<Simd<[m32; 4]>> for i16x4[src]

impl FromCast<Simd<[m32; 4]>> for u16x4[src]

impl FromCast<Simd<[m32; 4]>> for m16x4[src]

impl FromCast<Simd<[m32; 4]>> for i32x4[src]

impl FromCast<Simd<[m32; 4]>> for u32x4[src]

impl FromCast<Simd<[m32; 4]>> for f32x4[src]

impl FromCast<Simd<[m32; 4]>> for i64x4[src]

impl FromCast<Simd<[m32; 8]>> for i8x8[src]

impl FromCast<Simd<[m32; 8]>> for u8x8[src]

impl FromCast<Simd<[m32; 8]>> for u64x8[src]

impl FromCast<Simd<[m32; 8]>> for f64x8[src]

impl FromCast<Simd<[m32; 8]>> for m64x8[src]

impl FromCast<Simd<[m32; 8]>> for isizex8[src]

impl FromCast<Simd<[m32; 8]>> for usizex8[src]

impl FromCast<Simd<[m32; 8]>> for msizex8[src]

impl FromCast<Simd<[m32; 8]>> for m8x8[src]

impl FromCast<Simd<[m32; 8]>> for i16x8[src]

impl FromCast<Simd<[m32; 8]>> for u16x8[src]

impl FromCast<Simd<[m32; 8]>> for m16x8[src]

impl FromCast<Simd<[m32; 8]>> for i32x8[src]

impl FromCast<Simd<[m32; 8]>> for u32x8[src]

impl FromCast<Simd<[m32; 8]>> for f32x8[src]

impl FromCast<Simd<[m32; 8]>> for i64x8[src]

impl FromCast<Simd<[m64; 2]>> for i8x2[src]

impl FromCast<Simd<[m64; 2]>> for u8x2[src]

impl FromCast<Simd<[m64; 2]>> for i64x2[src]

impl FromCast<Simd<[m64; 2]>> for u64x2[src]

impl FromCast<Simd<[m64; 2]>> for f64x2[src]

impl FromCast<Simd<[m64; 2]>> for isizex2[src]

impl FromCast<Simd<[m64; 2]>> for usizex2[src]

impl FromCast<Simd<[m64; 2]>> for msizex2[src]

impl FromCast<Simd<[m64; 2]>> for i128x2[src]

impl FromCast<Simd<[m64; 2]>> for u128x2[src]

impl FromCast<Simd<[m64; 2]>> for m128x2[src]

impl FromCast<Simd<[m64; 2]>> for m8x2[src]

impl FromCast<Simd<[m64; 2]>> for i16x2[src]

impl FromCast<Simd<[m64; 2]>> for u16x2[src]

impl FromCast<Simd<[m64; 2]>> for m16x2[src]

impl FromCast<Simd<[m64; 2]>> for i32x2[src]

impl FromCast<Simd<[m64; 2]>> for u32x2[src]

impl FromCast<Simd<[m64; 2]>> for f32x2[src]

impl FromCast<Simd<[m64; 2]>> for m32x2[src]

impl FromCast<Simd<[m64; 4]>> for i8x4[src]

impl FromCast<Simd<[m64; 4]>> for u8x4[src]

impl FromCast<Simd<[m64; 4]>> for i64x4[src]

impl FromCast<Simd<[m64; 4]>> for u64x4[src]

impl FromCast<Simd<[m64; 4]>> for f64x4[src]

impl FromCast<Simd<[m64; 4]>> for isizex4[src]

impl FromCast<Simd<[m64; 4]>> for usizex4[src]

impl FromCast<Simd<[m64; 4]>> for msizex4[src]

impl FromCast<Simd<[m64; 4]>> for i128x4[src]

impl FromCast<Simd<[m64; 4]>> for u128x4[src]

impl FromCast<Simd<[m64; 4]>> for m128x4[src]

impl FromCast<Simd<[m64; 4]>> for m8x4[src]

impl FromCast<Simd<[m64; 4]>> for i16x4[src]

impl FromCast<Simd<[m64; 4]>> for u16x4[src]

impl FromCast<Simd<[m64; 4]>> for m16x4[src]

impl FromCast<Simd<[m64; 4]>> for i32x4[src]

impl FromCast<Simd<[m64; 4]>> for u32x4[src]

impl FromCast<Simd<[m64; 4]>> for f32x4[src]

impl FromCast<Simd<[m64; 4]>> for m32x4[src]

impl FromCast<Simd<[m64; 8]>> for i8x8[src]

impl FromCast<Simd<[m64; 8]>> for u8x8[src]

impl FromCast<Simd<[m64; 8]>> for i64x8[src]

impl FromCast<Simd<[m64; 8]>> for u64x8[src]

impl FromCast<Simd<[m64; 8]>> for f64x8[src]

impl FromCast<Simd<[m64; 8]>> for isizex8[src]

impl FromCast<Simd<[m64; 8]>> for usizex8[src]

impl FromCast<Simd<[m64; 8]>> for msizex8[src]

impl FromCast<Simd<[m64; 8]>> for m8x8[src]

impl FromCast<Simd<[m64; 8]>> for i16x8[src]

impl FromCast<Simd<[m64; 8]>> for u16x8[src]

impl FromCast<Simd<[m64; 8]>> for m16x8[src]

impl FromCast<Simd<[m64; 8]>> for i32x8[src]

impl FromCast<Simd<[m64; 8]>> for u32x8[src]

impl FromCast<Simd<[m64; 8]>> for f32x8[src]

impl FromCast<Simd<[m64; 8]>> for m32x8[src]

impl FromCast<Simd<[m8; 16]>> for i8x16[src]

impl FromCast<Simd<[m8; 16]>> for u8x16[src]

impl FromCast<Simd<[m8; 16]>> for i16x16[src]

impl FromCast<Simd<[m8; 16]>> for u16x16[src]

impl FromCast<Simd<[m8; 16]>> for m16x16[src]

impl FromCast<Simd<[m8; 16]>> for i32x16[src]

impl FromCast<Simd<[m8; 16]>> for u32x16[src]

impl FromCast<Simd<[m8; 16]>> for f32x16[src]

impl FromCast<Simd<[m8; 16]>> for m32x16[src]

impl FromCast<Simd<[m8; 2]>> for i8x2[src]

impl FromCast<Simd<[m8; 2]>> for u8x2[src]

impl FromCast<Simd<[m8; 2]>> for u64x2[src]

impl FromCast<Simd<[m8; 2]>> for f64x2[src]

impl FromCast<Simd<[m8; 2]>> for m64x2[src]

impl FromCast<Simd<[m8; 2]>> for isizex2[src]

impl FromCast<Simd<[m8; 2]>> for usizex2[src]

impl FromCast<Simd<[m8; 2]>> for msizex2[src]

impl FromCast<Simd<[m8; 2]>> for i128x2[src]

impl FromCast<Simd<[m8; 2]>> for u128x2[src]

impl FromCast<Simd<[m8; 2]>> for m128x2[src]

impl FromCast<Simd<[m8; 2]>> for i16x2[src]

impl FromCast<Simd<[m8; 2]>> for u16x2[src]

impl FromCast<Simd<[m8; 2]>> for m16x2[src]

impl FromCast<Simd<[m8; 2]>> for i32x2[src]

impl FromCast<Simd<[m8; 2]>> for u32x2[src]

impl FromCast<Simd<[m8; 2]>> for f32x2[src]

impl FromCast<Simd<[m8; 2]>> for m32x2[src]

impl FromCast<Simd<[m8; 2]>> for i64x2[src]

impl FromCast<Simd<[m8; 32]>> for i8x32[src]

impl FromCast<Simd<[m8; 32]>> for u8x32[src]

impl FromCast<Simd<[m8; 32]>> for i16x32[src]

impl FromCast<Simd<[m8; 32]>> for u16x32[src]

impl FromCast<Simd<[m8; 32]>> for m16x32[src]

impl FromCast<Simd<[m8; 4]>> for i8x4[src]

impl FromCast<Simd<[m8; 4]>> for u8x4[src]

impl FromCast<Simd<[m8; 4]>> for u64x4[src]

impl FromCast<Simd<[m8; 4]>> for f64x4[src]

impl FromCast<Simd<[m8; 4]>> for m64x4[src]

impl FromCast<Simd<[m8; 4]>> for isizex4[src]

impl FromCast<Simd<[m8; 4]>> for usizex4[src]

impl FromCast<Simd<[m8; 4]>> for msizex4[src]

impl FromCast<Simd<[m8; 4]>> for i128x4[src]

impl FromCast<Simd<[m8; 4]>> for u128x4[src]

impl FromCast<Simd<[m8; 4]>> for m128x4[src]

impl FromCast<Simd<[m8; 4]>> for i16x4[src]

impl FromCast<Simd<[m8; 4]>> for u16x4[src]

impl FromCast<Simd<[m8; 4]>> for m16x4[src]

impl FromCast<Simd<[m8; 4]>> for i32x4[src]

impl FromCast<Simd<[m8; 4]>> for u32x4[src]

impl FromCast<Simd<[m8; 4]>> for f32x4[src]

impl FromCast<Simd<[m8; 4]>> for m32x4[src]

impl FromCast<Simd<[m8; 4]>> for i64x4[src]

impl FromCast<Simd<[m8; 64]>> for i8x64[src]

impl FromCast<Simd<[m8; 64]>> for u8x64[src]

impl FromCast<Simd<[m8; 8]>> for i8x8[src]

impl FromCast<Simd<[m8; 8]>> for u8x8[src]

impl FromCast<Simd<[m8; 8]>> for u64x8[src]

impl FromCast<Simd<[m8; 8]>> for f64x8[src]

impl FromCast<Simd<[m8; 8]>> for m64x8[src]

impl FromCast<Simd<[m8; 8]>> for isizex8[src]

impl FromCast<Simd<[m8; 8]>> for usizex8[src]

impl FromCast<Simd<[m8; 8]>> for msizex8[src]

impl FromCast<Simd<[m8; 8]>> for i16x8[src]

impl FromCast<Simd<[m8; 8]>> for u16x8[src]

impl FromCast<Simd<[m8; 8]>> for m16x8[src]

impl FromCast<Simd<[m8; 8]>> for i32x8[src]

impl FromCast<Simd<[m8; 8]>> for u32x8[src]

impl FromCast<Simd<[m8; 8]>> for f32x8[src]

impl FromCast<Simd<[m8; 8]>> for m32x8[src]

impl FromCast<Simd<[m8; 8]>> for i64x8[src]

impl FromCast<Simd<[msize; 2]>> for i8x2[src]

impl FromCast<Simd<[msize; 2]>> for u8x2[src]

impl FromCast<Simd<[msize; 2]>> for i64x2[src]

impl FromCast<Simd<[msize; 2]>> for u64x2[src]

impl FromCast<Simd<[msize; 2]>> for f64x2[src]

impl FromCast<Simd<[msize; 2]>> for m64x2[src]

impl FromCast<Simd<[msize; 2]>> for isizex2[src]

impl FromCast<Simd<[msize; 2]>> for usizex2[src]

impl FromCast<Simd<[msize; 2]>> for i128x2[src]

impl FromCast<Simd<[msize; 2]>> for u128x2[src]

impl FromCast<Simd<[msize; 2]>> for m128x2[src]

impl FromCast<Simd<[msize; 2]>> for m8x2[src]

impl FromCast<Simd<[msize; 2]>> for i16x2[src]

impl FromCast<Simd<[msize; 2]>> for u16x2[src]

impl FromCast<Simd<[msize; 2]>> for m16x2[src]

impl FromCast<Simd<[msize; 2]>> for i32x2[src]

impl FromCast<Simd<[msize; 2]>> for u32x2[src]

impl FromCast<Simd<[msize; 2]>> for f32x2[src]

impl FromCast<Simd<[msize; 2]>> for m32x2[src]

impl FromCast<Simd<[msize; 4]>> for i8x4[src]

impl FromCast<Simd<[msize; 4]>> for u8x4[src]

impl FromCast<Simd<[msize; 4]>> for i64x4[src]

impl FromCast<Simd<[msize; 4]>> for u64x4[src]

impl FromCast<Simd<[msize; 4]>> for f64x4[src]

impl FromCast<Simd<[msize; 4]>> for m64x4[src]

impl FromCast<Simd<[msize; 4]>> for isizex4[src]

impl FromCast<Simd<[msize; 4]>> for usizex4[src]

impl FromCast<Simd<[msize; 4]>> for i128x4[src]

impl FromCast<Simd<[msize; 4]>> for u128x4[src]

impl FromCast<Simd<[msize; 4]>> for m128x4[src]

impl FromCast<Simd<[msize; 4]>> for m8x4[src]

impl FromCast<Simd<[msize; 4]>> for i16x4[src]

impl FromCast<Simd<[msize; 4]>> for u16x4[src]

impl FromCast<Simd<[msize; 4]>> for m16x4[src]

impl FromCast<Simd<[msize; 4]>> for i32x4[src]

impl FromCast<Simd<[msize; 4]>> for u32x4[src]

impl FromCast<Simd<[msize; 4]>> for f32x4[src]

impl FromCast<Simd<[msize; 4]>> for m32x4[src]

impl FromCast<Simd<[msize; 8]>> for i8x8[src]

impl FromCast<Simd<[msize; 8]>> for u8x8[src]

impl FromCast<Simd<[msize; 8]>> for i64x8[src]

impl FromCast<Simd<[msize; 8]>> for u64x8[src]

impl FromCast<Simd<[msize; 8]>> for f64x8[src]

impl FromCast<Simd<[msize; 8]>> for m64x8[src]

impl FromCast<Simd<[msize; 8]>> for isizex8[src]

impl FromCast<Simd<[msize; 8]>> for usizex8[src]

impl FromCast<Simd<[msize; 8]>> for m8x8[src]

impl FromCast<Simd<[msize; 8]>> for i16x8[src]

impl FromCast<Simd<[msize; 8]>> for u16x8[src]

impl FromCast<Simd<[msize; 8]>> for m16x8[src]

impl FromCast<Simd<[msize; 8]>> for i32x8[src]

impl FromCast<Simd<[msize; 8]>> for u32x8[src]

impl FromCast<Simd<[msize; 8]>> for f32x8[src]

impl FromCast<Simd<[msize; 8]>> for m32x8[src]

impl FromCast<Simd<[u128; 1]>> for i128x1[src]

impl FromCast<Simd<[u128; 1]>> for m128x1[src]

impl FromCast<Simd<[u128; 2]>> for i8x2[src]

impl FromCast<Simd<[u128; 2]>> for u8x2[src]

impl FromCast<Simd<[u128; 2]>> for i64x2[src]

impl FromCast<Simd<[u128; 2]>> for u64x2[src]

impl FromCast<Simd<[u128; 2]>> for f64x2[src]

impl FromCast<Simd<[u128; 2]>> for m64x2[src]

impl FromCast<Simd<[u128; 2]>> for isizex2[src]

impl FromCast<Simd<[u128; 2]>> for usizex2[src]

impl FromCast<Simd<[u128; 2]>> for msizex2[src]

impl FromCast<Simd<[u128; 2]>> for i128x2[src]

impl FromCast<Simd<[u128; 2]>> for m128x2[src]

impl FromCast<Simd<[u128; 2]>> for m8x2[src]

impl FromCast<Simd<[u128; 2]>> for i16x2[src]

impl FromCast<Simd<[u128; 2]>> for u16x2[src]

impl FromCast<Simd<[u128; 2]>> for m16x2[src]

impl FromCast<Simd<[u128; 2]>> for i32x2[src]

impl FromCast<Simd<[u128; 2]>> for u32x2[src]

impl FromCast<Simd<[u128; 2]>> for f32x2[src]

impl FromCast<Simd<[u128; 2]>> for m32x2[src]

impl FromCast<Simd<[u128; 4]>> for i8x4[src]

impl FromCast<Simd<[u128; 4]>> for u8x4[src]

impl FromCast<Simd<[u128; 4]>> for i64x4[src]

impl FromCast<Simd<[u128; 4]>> for u64x4[src]

impl FromCast<Simd<[u128; 4]>> for f64x4[src]

impl FromCast<Simd<[u128; 4]>> for m64x4[src]

impl FromCast<Simd<[u128; 4]>> for isizex4[src]

impl FromCast<Simd<[u128; 4]>> for usizex4[src]

impl FromCast<Simd<[u128; 4]>> for msizex4[src]

impl FromCast<Simd<[u128; 4]>> for i128x4[src]

impl FromCast<Simd<[u128; 4]>> for m128x4[src]

impl FromCast<Simd<[u128; 4]>> for m8x4[src]

impl FromCast<Simd<[u128; 4]>> for i16x4[src]

impl FromCast<Simd<[u128; 4]>> for u16x4[src]

impl FromCast<Simd<[u128; 4]>> for m16x4[src]

impl FromCast<Simd<[u128; 4]>> for i32x4[src]

impl FromCast<Simd<[u128; 4]>> for u32x4[src]

impl FromCast<Simd<[u128; 4]>> for f32x4[src]

impl FromCast<Simd<[u128; 4]>> for m32x4[src]

impl FromCast<Simd<[u16; 16]>> for i8x16[src]

impl FromCast<Simd<[u16; 16]>> for u8x16[src]

impl FromCast<Simd<[u16; 16]>> for m8x16[src]

impl FromCast<Simd<[u16; 16]>> for i16x16[src]

impl FromCast<Simd<[u16; 16]>> for m16x16[src]

impl FromCast<Simd<[u16; 16]>> for i32x16[src]

impl FromCast<Simd<[u16; 16]>> for u32x16[src]

impl FromCast<Simd<[u16; 16]>> for f32x16[src]

impl FromCast<Simd<[u16; 16]>> for m32x16[src]

impl FromCast<Simd<[u16; 2]>> for i8x2[src]

impl FromCast<Simd<[u16; 2]>> for u8x2[src]

impl FromCast<Simd<[u16; 2]>> for u64x2[src]

impl FromCast<Simd<[u16; 2]>> for f64x2[src]

impl FromCast<Simd<[u16; 2]>> for m64x2[src]

impl FromCast<Simd<[u16; 2]>> for isizex2[src]

impl FromCast<Simd<[u16; 2]>> for usizex2[src]

impl FromCast<Simd<[u16; 2]>> for msizex2[src]

impl FromCast<Simd<[u16; 2]>> for i128x2[src]

impl FromCast<Simd<[u16; 2]>> for u128x2[src]

impl FromCast<Simd<[u16; 2]>> for m128x2[src]

impl FromCast<Simd<[u16; 2]>> for m8x2[src]

impl FromCast<Simd<[u16; 2]>> for i16x2[src]

impl FromCast<Simd<[u16; 2]>> for m16x2[src]

impl FromCast<Simd<[u16; 2]>> for i32x2[src]

impl FromCast<Simd<[u16; 2]>> for u32x2[src]

impl FromCast<Simd<[u16; 2]>> for f32x2[src]

impl FromCast<Simd<[u16; 2]>> for m32x2[src]

impl FromCast<Simd<[u16; 2]>> for i64x2[src]

impl FromCast<Simd<[u16; 32]>> for i8x32[src]

impl FromCast<Simd<[u16; 32]>> for u8x32[src]

impl FromCast<Simd<[u16; 32]>> for m8x32[src]

impl FromCast<Simd<[u16; 32]>> for i16x32[src]

impl FromCast<Simd<[u16; 32]>> for m16x32[src]

impl FromCast<Simd<[u16; 4]>> for i8x4[src]

impl FromCast<Simd<[u16; 4]>> for u8x4[src]

impl FromCast<Simd<[u16; 4]>> for u64x4[src]

impl FromCast<Simd<[u16; 4]>> for f64x4[src]

impl FromCast<Simd<[u16; 4]>> for m64x4[src]

impl FromCast<Simd<[u16; 4]>> for isizex4[src]

impl FromCast<Simd<[u16; 4]>> for usizex4[src]

impl FromCast<Simd<[u16; 4]>> for msizex4[src]

impl FromCast<Simd<[u16; 4]>> for i128x4[src]

impl FromCast<Simd<[u16; 4]>> for u128x4[src]

impl FromCast<Simd<[u16; 4]>> for m128x4[src]

impl FromCast<Simd<[u16; 4]>> for m8x4[src]

impl FromCast<Simd<[u16; 4]>> for i16x4[src]

impl FromCast<Simd<[u16; 4]>> for m16x4[src]

impl FromCast<Simd<[u16; 4]>> for i32x4[src]

impl FromCast<Simd<[u16; 4]>> for u32x4[src]

impl FromCast<Simd<[u16; 4]>> for f32x4[src]

impl FromCast<Simd<[u16; 4]>> for m32x4[src]

impl FromCast<Simd<[u16; 4]>> for i64x4[src]

impl FromCast<Simd<[u16; 8]>> for i8x8[src]

impl FromCast<Simd<[u16; 8]>> for u8x8[src]

impl FromCast<Simd<[u16; 8]>> for u64x8[src]

impl FromCast<Simd<[u16; 8]>> for f64x8[src]

impl FromCast<Simd<[u16; 8]>> for m64x8[src]

impl FromCast<Simd<[u16; 8]>> for isizex8[src]

impl FromCast<Simd<[u16; 8]>> for usizex8[src]

impl FromCast<Simd<[u16; 8]>> for msizex8[src]

impl FromCast<Simd<[u16; 8]>> for m8x8[src]

impl FromCast<Simd<[u16; 8]>> for i16x8[src]

impl FromCast<Simd<[u16; 8]>> for m16x8[src]

impl FromCast<Simd<[u16; 8]>> for i32x8[src]

impl FromCast<Simd<[u16; 8]>> for u32x8[src]

impl FromCast<Simd<[u16; 8]>> for f32x8[src]

impl FromCast<Simd<[u16; 8]>> for m32x8[src]

impl FromCast<Simd<[u16; 8]>> for i64x8[src]

impl FromCast<Simd<[u32; 16]>> for i8x16[src]

impl FromCast<Simd<[u32; 16]>> for u8x16[src]

impl FromCast<Simd<[u32; 16]>> for m8x16[src]

impl FromCast<Simd<[u32; 16]>> for i16x16[src]

impl FromCast<Simd<[u32; 16]>> for u16x16[src]

impl FromCast<Simd<[u32; 16]>> for m16x16[src]

impl FromCast<Simd<[u32; 16]>> for i32x16[src]

impl FromCast<Simd<[u32; 16]>> for f32x16[src]

impl FromCast<Simd<[u32; 16]>> for m32x16[src]

impl FromCast<Simd<[u32; 2]>> for i8x2[src]

impl FromCast<Simd<[u32; 2]>> for u8x2[src]

impl FromCast<Simd<[u32; 2]>> for u64x2[src]

impl FromCast<Simd<[u32; 2]>> for f64x2[src]

impl FromCast<Simd<[u32; 2]>> for m64x2[src]

impl FromCast<Simd<[u32; 2]>> for isizex2[src]

impl FromCast<Simd<[u32; 2]>> for usizex2[src]

impl FromCast<Simd<[u32; 2]>> for msizex2[src]

impl FromCast<Simd<[u32; 2]>> for i128x2[src]

impl FromCast<Simd<[u32; 2]>> for u128x2[src]

impl FromCast<Simd<[u32; 2]>> for m128x2[src]

impl FromCast<Simd<[u32; 2]>> for m8x2[src]

impl FromCast<Simd<[u32; 2]>> for i16x2[src]

impl FromCast<Simd<[u32; 2]>> for u16x2[src]

impl FromCast<Simd<[u32; 2]>> for m16x2[src]

impl FromCast<Simd<[u32; 2]>> for i32x2[src]

impl FromCast<Simd<[u32; 2]>> for f32x2[src]

impl FromCast<Simd<[u32; 2]>> for m32x2[src]

impl FromCast<Simd<[u32; 2]>> for i64x2[src]

impl FromCast<Simd<[u32; 4]>> for i8x4[src]

impl FromCast<Simd<[u32; 4]>> for u8x4[src]

impl FromCast<Simd<[u32; 4]>> for u64x4[src]

impl FromCast<Simd<[u32; 4]>> for f64x4[src]

impl FromCast<Simd<[u32; 4]>> for m64x4[src]

impl FromCast<Simd<[u32; 4]>> for isizex4[src]

impl FromCast<Simd<[u32; 4]>> for usizex4[src]

impl FromCast<Simd<[u32; 4]>> for msizex4[src]

impl FromCast<Simd<[u32; 4]>> for i128x4[src]

impl FromCast<Simd<[u32; 4]>> for u128x4[src]

impl FromCast<Simd<[u32; 4]>> for m128x4[src]

impl FromCast<Simd<[u32; 4]>> for m8x4[src]

impl FromCast<Simd<[u32; 4]>> for i16x4[src]

impl FromCast<Simd<[u32; 4]>> for u16x4[src]

impl FromCast<Simd<[u32; 4]>> for m16x4[src]

impl FromCast<Simd<[u32; 4]>> for i32x4[src]

impl FromCast<Simd<[u32; 4]>> for f32x4[src]

impl FromCast<Simd<[u32; 4]>> for m32x4[src]

impl FromCast<Simd<[u32; 4]>> for i64x4[src]

impl FromCast<Simd<[u32; 8]>> for i8x8[src]

impl FromCast<Simd<[u32; 8]>> for u8x8[src]

impl FromCast<Simd<[u32; 8]>> for u64x8[src]

impl FromCast<Simd<[u32; 8]>> for f64x8[src]

impl FromCast<Simd<[u32; 8]>> for m64x8[src]

impl FromCast<Simd<[u32; 8]>> for isizex8[src]

impl FromCast<Simd<[u32; 8]>> for usizex8[src]

impl FromCast<Simd<[u32; 8]>> for msizex8[src]

impl FromCast<Simd<[u32; 8]>> for m8x8[src]

impl FromCast<Simd<[u32; 8]>> for i16x8[src]

impl FromCast<Simd<[u32; 8]>> for u16x8[src]

impl FromCast<Simd<[u32; 8]>> for m16x8[src]

impl FromCast<Simd<[u32; 8]>> for i32x8[src]

impl FromCast<Simd<[u32; 8]>> for f32x8[src]

impl FromCast<Simd<[u32; 8]>> for m32x8[src]

impl FromCast<Simd<[u32; 8]>> for i64x8[src]

impl FromCast<Simd<[u64; 2]>> for i8x2[src]

impl FromCast<Simd<[u64; 2]>> for u8x2[src]

impl FromCast<Simd<[u64; 2]>> for i64x2[src]

impl FromCast<Simd<[u64; 2]>> for f64x2[src]

impl FromCast<Simd<[u64; 2]>> for m64x2[src]

impl FromCast<Simd<[u64; 2]>> for isizex2[src]

impl FromCast<Simd<[u64; 2]>> for usizex2[src]

impl FromCast<Simd<[u64; 2]>> for msizex2[src]

impl FromCast<Simd<[u64; 2]>> for i128x2[src]

impl FromCast<Simd<[u64; 2]>> for u128x2[src]

impl FromCast<Simd<[u64; 2]>> for m128x2[src]

impl FromCast<Simd<[u64; 2]>> for m8x2[src]

impl FromCast<Simd<[u64; 2]>> for i16x2[src]

impl FromCast<Simd<[u64; 2]>> for u16x2[src]

impl FromCast<Simd<[u64; 2]>> for m16x2[src]

impl FromCast<Simd<[u64; 2]>> for i32x2[src]

impl FromCast<Simd<[u64; 2]>> for u32x2[src]

impl FromCast<Simd<[u64; 2]>> for f32x2[src]

impl FromCast<Simd<[u64; 2]>> for m32x2[src]

impl FromCast<Simd<[u64; 4]>> for i8x4[src]

impl FromCast<Simd<[u64; 4]>> for u8x4[src]

impl FromCast<Simd<[u64; 4]>> for i64x4[src]

impl FromCast<Simd<[u64; 4]>> for f64x4[src]

impl FromCast<Simd<[u64; 4]>> for m64x4[src]

impl FromCast<Simd<[u64; 4]>> for isizex4[src]

impl FromCast<Simd<[u64; 4]>> for usizex4[src]

impl FromCast<Simd<[u64; 4]>> for msizex4[src]

impl FromCast<Simd<[u64; 4]>> for i128x4[src]

impl FromCast<Simd<[u64; 4]>> for u128x4[src]

impl FromCast<Simd<[u64; 4]>> for m128x4[src]

impl FromCast<Simd<[u64; 4]>> for m8x4[src]

impl FromCast<Simd<[u64; 4]>> for i16x4[src]

impl FromCast<Simd<[u64; 4]>> for u16x4[src]

impl FromCast<Simd<[u64; 4]>> for m16x4[src]

impl FromCast<Simd<[u64; 4]>> for i32x4[src]

impl FromCast<Simd<[u64; 4]>> for u32x4[src]

impl FromCast<Simd<[u64; 4]>> for f32x4[src]

impl FromCast<Simd<[u64; 4]>> for m32x4[src]

impl FromCast<Simd<[u64; 8]>> for i8x8[src]

impl FromCast<Simd<[u64; 8]>> for u8x8[src]

impl FromCast<Simd<[u64; 8]>> for i64x8[src]

impl FromCast<Simd<[u64; 8]>> for f64x8[src]

impl FromCast<Simd<[u64; 8]>> for m64x8[src]

impl FromCast<Simd<[u64; 8]>> for isizex8[src]

impl FromCast<Simd<[u64; 8]>> for usizex8[src]

impl FromCast<Simd<[u64; 8]>> for msizex8[src]

impl FromCast<Simd<[u64; 8]>> for m8x8[src]

impl FromCast<Simd<[u64; 8]>> for i16x8[src]

impl FromCast<Simd<[u64; 8]>> for u16x8[src]

impl FromCast<Simd<[u64; 8]>> for m16x8[src]

impl FromCast<Simd<[u64; 8]>> for i32x8[src]

impl FromCast<Simd<[u64; 8]>> for u32x8[src]

impl FromCast<Simd<[u64; 8]>> for f32x8[src]

impl FromCast<Simd<[u64; 8]>> for m32x8[src]

impl FromCast<Simd<[u8; 16]>> for i8x16[src]

impl FromCast<Simd<[u8; 16]>> for m8x16[src]

impl FromCast<Simd<[u8; 16]>> for i16x16[src]

impl FromCast<Simd<[u8; 16]>> for u16x16[src]

impl FromCast<Simd<[u8; 16]>> for m16x16[src]

impl FromCast<Simd<[u8; 16]>> for i32x16[src]

impl FromCast<Simd<[u8; 16]>> for u32x16[src]

impl FromCast<Simd<[u8; 16]>> for f32x16[src]

impl FromCast<Simd<[u8; 16]>> for m32x16[src]

impl FromCast<Simd<[u8; 2]>> for i8x2[src]

impl FromCast<Simd<[u8; 2]>> for m8x2[src]

impl FromCast<Simd<[u8; 2]>> for u64x2[src]

impl FromCast<Simd<[u8; 2]>> for f64x2[src]

impl FromCast<Simd<[u8; 2]>> for m64x2[src]

impl FromCast<Simd<[u8; 2]>> for isizex2[src]

impl FromCast<Simd<[u8; 2]>> for usizex2[src]

impl FromCast<Simd<[u8; 2]>> for msizex2[src]

impl FromCast<Simd<[u8; 2]>> for i128x2[src]

impl FromCast<Simd<[u8; 2]>> for u128x2[src]

impl FromCast<Simd<[u8; 2]>> for m128x2[src]

impl FromCast<Simd<[u8; 2]>> for i16x2[src]

impl FromCast<Simd<[u8; 2]>> for u16x2[src]

impl FromCast<Simd<[u8; 2]>> for m16x2[src]

impl FromCast<Simd<[u8; 2]>> for i32x2[src]

impl FromCast<Simd<[u8; 2]>> for u32x2[src]

impl FromCast<Simd<[u8; 2]>> for f32x2[src]

impl FromCast<Simd<[u8; 2]>> for m32x2[src]

impl FromCast<Simd<[u8; 2]>> for i64x2[src]

impl FromCast<Simd<[u8; 32]>> for i8x32[src]

impl FromCast<Simd<[u8; 32]>> for m8x32[src]

impl FromCast<Simd<[u8; 32]>> for i16x32[src]

impl FromCast<Simd<[u8; 32]>> for u16x32[src]

impl FromCast<Simd<[u8; 32]>> for m16x32[src]

impl FromCast<Simd<[u8; 4]>> for i8x4[src]

impl FromCast<Simd<[u8; 4]>> for m8x4[src]

impl FromCast<Simd<[u8; 4]>> for u64x4[src]

impl FromCast<Simd<[u8; 4]>> for f64x4[src]

impl FromCast<Simd<[u8; 4]>> for m64x4[src]

impl FromCast<Simd<[u8; 4]>> for isizex4[src]

impl FromCast<Simd<[u8; 4]>> for usizex4[src]

impl FromCast<Simd<[u8; 4]>> for msizex4[src]

impl FromCast<Simd<[u8; 4]>> for i128x4[src]

impl FromCast<Simd<[u8; 4]>> for u128x4[src]

impl FromCast<Simd<[u8; 4]>> for m128x4[src]

impl FromCast<Simd<[u8; 4]>> for i16x4[src]

impl FromCast<Simd<[u8; 4]>> for u16x4[src]

impl FromCast<Simd<[u8; 4]>> for m16x4[src]

impl FromCast<Simd<[u8; 4]>> for i32x4[src]

impl FromCast<Simd<[u8; 4]>> for u32x4[src]

impl FromCast<Simd<[u8; 4]>> for f32x4[src]

impl FromCast<Simd<[u8; 4]>> for m32x4[src]

impl FromCast<Simd<[u8; 4]>> for i64x4[src]

impl FromCast<Simd<[u8; 64]>> for i8x64[src]

impl FromCast<Simd<[u8; 64]>> for m8x64[src]

impl FromCast<Simd<[u8; 8]>> for i8x8[src]

impl FromCast<Simd<[u8; 8]>> for m8x8[src]

impl FromCast<Simd<[u8; 8]>> for u64x8[src]

impl FromCast<Simd<[u8; 8]>> for f64x8[src]

impl FromCast<Simd<[u8; 8]>> for m64x8[src]

impl FromCast<Simd<[u8; 8]>> for isizex8[src]

impl FromCast<Simd<[u8; 8]>> for usizex8[src]

impl FromCast<Simd<[u8; 8]>> for msizex8[src]

impl FromCast<Simd<[u8; 8]>> for i16x8[src]

impl FromCast<Simd<[u8; 8]>> for u16x8[src]

impl FromCast<Simd<[u8; 8]>> for m16x8[src]

impl FromCast<Simd<[u8; 8]>> for i32x8[src]

impl FromCast<Simd<[u8; 8]>> for u32x8[src]

impl FromCast<Simd<[u8; 8]>> for f32x8[src]

impl FromCast<Simd<[u8; 8]>> for m32x8[src]

impl FromCast<Simd<[u8; 8]>> for i64x8[src]

impl FromCast<Simd<[usize; 2]>> for i8x2[src]

impl FromCast<Simd<[usize; 2]>> for u8x2[src]

impl FromCast<Simd<[usize; 2]>> for i64x2[src]

impl FromCast<Simd<[usize; 2]>> for u64x2[src]

impl FromCast<Simd<[usize; 2]>> for f64x2[src]

impl FromCast<Simd<[usize; 2]>> for m64x2[src]

impl FromCast<Simd<[usize; 2]>> for isizex2[src]

impl FromCast<Simd<[usize; 2]>> for msizex2[src]

impl FromCast<Simd<[usize; 2]>> for i128x2[src]

impl FromCast<Simd<[usize; 2]>> for u128x2[src]

impl FromCast<Simd<[usize; 2]>> for m128x2[src]

impl FromCast<Simd<[usize; 2]>> for m8x2[src]

impl FromCast<Simd<[usize; 2]>> for i16x2[src]

impl FromCast<Simd<[usize; 2]>> for u16x2[src]

impl FromCast<Simd<[usize; 2]>> for m16x2[src]

impl FromCast<Simd<[usize; 2]>> for i32x2[src]

impl FromCast<Simd<[usize; 2]>> for u32x2[src]

impl FromCast<Simd<[usize; 2]>> for f32x2[src]

impl FromCast<Simd<[usize; 2]>> for m32x2[src]

impl FromCast<Simd<[usize; 4]>> for i8x4[src]

impl FromCast<Simd<[usize; 4]>> for u8x4[src]

impl FromCast<Simd<[usize; 4]>> for i64x4[src]

impl FromCast<Simd<[usize; 4]>> for u64x4[src]

impl FromCast<Simd<[usize; 4]>> for f64x4[src]

impl FromCast<Simd<[usize; 4]>> for m64x4[src]

impl FromCast<Simd<[usize; 4]>> for isizex4[src]

impl FromCast<Simd<[usize; 4]>> for msizex4[src]

impl FromCast<Simd<[usize; 4]>> for i128x4[src]

impl FromCast<Simd<[usize; 4]>> for u128x4[src]

impl FromCast<Simd<[usize; 4]>> for m128x4[src]

impl FromCast<Simd<[usize; 4]>> for m8x4[src]

impl FromCast<Simd<[usize; 4]>> for i16x4[src]

impl FromCast<Simd<[usize; 4]>> for u16x4[src]

impl FromCast<Simd<[usize; 4]>> for m16x4[src]

impl FromCast<Simd<[usize; 4]>> for i32x4[src]

impl FromCast<Simd<[usize; 4]>> for u32x4[src]

impl FromCast<Simd<[usize; 4]>> for f32x4[src]

impl FromCast<Simd<[usize; 4]>> for m32x4[src]

impl FromCast<Simd<[usize; 8]>> for i8x8[src]

impl FromCast<Simd<[usize; 8]>> for u8x8[src]

impl FromCast<Simd<[usize; 8]>> for i64x8[src]

impl FromCast<Simd<[usize; 8]>> for u64x8[src]

impl FromCast<Simd<[usize; 8]>> for f64x8[src]

impl FromCast<Simd<[usize; 8]>> for m64x8[src]

impl FromCast<Simd<[usize; 8]>> for isizex8[src]

impl FromCast<Simd<[usize; 8]>> for msizex8[src]

impl FromCast<Simd<[usize; 8]>> for m8x8[src]

impl FromCast<Simd<[usize; 8]>> for i16x8[src]

impl FromCast<Simd<[usize; 8]>> for u16x8[src]

impl FromCast<Simd<[usize; 8]>> for m16x8[src]

impl FromCast<Simd<[usize; 8]>> for i32x8[src]

impl FromCast<Simd<[usize; 8]>> for u32x8[src]

impl FromCast<Simd<[usize; 8]>> for f32x8[src]

impl FromCast<Simd<[usize; 8]>> for m32x8[src]

impl Mul<Simd<[f32; 16]>> for f32x16[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[f32; 16]>> for f32[src]

type Output = f32x16

The resulting type after applying the * operator.

+

impl Mul<Simd<[f32; 2]>> for f32x2[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[f32; 2]>> for f32[src]

type Output = f32x2

The resulting type after applying the * operator.

+

impl Mul<Simd<[f32; 4]>> for f32x4[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[f32; 4]>> for f32[src]

type Output = f32x4

The resulting type after applying the * operator.

+

impl Mul<Simd<[f32; 8]>> for f32x8[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[f32; 8]>> for f32[src]

type Output = f32x8

The resulting type after applying the * operator.

+

impl Mul<Simd<[f64; 2]>> for f64x2[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[f64; 2]>> for f64[src]

type Output = f64x2

The resulting type after applying the * operator.

+

impl Mul<Simd<[f64; 4]>> for f64x4[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[f64; 4]>> for f64[src]

type Output = f64x4

The resulting type after applying the * operator.

+

impl Mul<Simd<[f64; 8]>> for f64x8[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[f64; 8]>> for f64[src]

type Output = f64x8

The resulting type after applying the * operator.

+

impl Mul<Simd<[i128; 1]>> for i128x1[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[i128; 1]>> for i128[src]

type Output = i128x1

The resulting type after applying the * operator.

+

impl Mul<Simd<[i128; 2]>> for i128x2[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[i128; 2]>> for i128[src]

type Output = i128x2

The resulting type after applying the * operator.

+

impl Mul<Simd<[i128; 4]>> for i128x4[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[i128; 4]>> for i128[src]

type Output = i128x4

The resulting type after applying the * operator.

+

impl Mul<Simd<[i16; 16]>> for i16x16[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[i16; 16]>> for i16[src]

type Output = i16x16

The resulting type after applying the * operator.

+

impl Mul<Simd<[i16; 2]>> for i16x2[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[i16; 2]>> for i16[src]

type Output = i16x2

The resulting type after applying the * operator.

+

impl Mul<Simd<[i16; 32]>> for i16x32[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[i16; 32]>> for i16[src]

type Output = i16x32

The resulting type after applying the * operator.

+

impl Mul<Simd<[i16; 4]>> for i16x4[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[i16; 4]>> for i16[src]

type Output = i16x4

The resulting type after applying the * operator.

+

impl Mul<Simd<[i16; 8]>> for i16x8[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[i16; 8]>> for i16[src]

type Output = i16x8

The resulting type after applying the * operator.

+

impl Mul<Simd<[i32; 16]>> for i32x16[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[i32; 16]>> for i32[src]

type Output = i32x16

The resulting type after applying the * operator.

+

impl Mul<Simd<[i32; 2]>> for i32x2[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[i32; 2]>> for i32[src]

type Output = i32x2

The resulting type after applying the * operator.

+

impl Mul<Simd<[i32; 4]>> for i32x4[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[i32; 4]>> for i32[src]

type Output = i32x4

The resulting type after applying the * operator.

+

impl Mul<Simd<[i32; 8]>> for i32x8[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[i32; 8]>> for i32[src]

type Output = i32x8

The resulting type after applying the * operator.

+

impl Mul<Simd<[i64; 2]>> for i64x2[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[i64; 2]>> for i64[src]

type Output = i64x2

The resulting type after applying the * operator.

+

impl Mul<Simd<[i64; 4]>> for i64x4[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[i64; 4]>> for i64[src]

type Output = i64x4

The resulting type after applying the * operator.

+

impl Mul<Simd<[i64; 8]>> for i64x8[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[i64; 8]>> for i64[src]

type Output = i64x8

The resulting type after applying the * operator.

+

impl Mul<Simd<[i8; 16]>> for i8x16[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[i8; 16]>> for i8[src]

type Output = i8x16

The resulting type after applying the * operator.

+

impl Mul<Simd<[i8; 2]>> for i8x2[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[i8; 2]>> for i8[src]

type Output = i8x2

The resulting type after applying the * operator.

+

impl Mul<Simd<[i8; 32]>> for i8x32[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[i8; 32]>> for i8[src]

type Output = i8x32

The resulting type after applying the * operator.

+

impl Mul<Simd<[i8; 4]>> for i8x4[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[i8; 4]>> for i8[src]

type Output = i8x4

The resulting type after applying the * operator.

+

impl Mul<Simd<[i8; 64]>> for i8x64[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[i8; 64]>> for i8[src]

type Output = i8x64

The resulting type after applying the * operator.

+

impl Mul<Simd<[i8; 8]>> for i8x8[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[i8; 8]>> for i8[src]

type Output = i8x8

The resulting type after applying the * operator.

+

impl Mul<Simd<[isize; 2]>> for isizex2[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[isize; 2]>> for isize[src]

type Output = isizex2

The resulting type after applying the * operator.

+

impl Mul<Simd<[isize; 4]>> for isizex4[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[isize; 4]>> for isize[src]

type Output = isizex4

The resulting type after applying the * operator.

+

impl Mul<Simd<[isize; 8]>> for isizex8[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[isize; 8]>> for isize[src]

type Output = isizex8

The resulting type after applying the * operator.

+

impl Mul<Simd<[u128; 1]>> for u128x1[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[u128; 1]>> for u128[src]

type Output = u128x1

The resulting type after applying the * operator.

+

impl Mul<Simd<[u128; 2]>> for u128x2[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[u128; 2]>> for u128[src]

type Output = u128x2

The resulting type after applying the * operator.

+

impl Mul<Simd<[u128; 4]>> for u128x4[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[u128; 4]>> for u128[src]

type Output = u128x4

The resulting type after applying the * operator.

+

impl Mul<Simd<[u16; 16]>> for u16x16[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[u16; 16]>> for u16[src]

type Output = u16x16

The resulting type after applying the * operator.

+

impl Mul<Simd<[u16; 2]>> for u16x2[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[u16; 2]>> for u16[src]

type Output = u16x2

The resulting type after applying the * operator.

+

impl Mul<Simd<[u16; 32]>> for u16x32[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[u16; 32]>> for u16[src]

type Output = u16x32

The resulting type after applying the * operator.

+

impl Mul<Simd<[u16; 4]>> for u16x4[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[u16; 4]>> for u16[src]

type Output = u16x4

The resulting type after applying the * operator.

+

impl Mul<Simd<[u16; 8]>> for u16x8[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[u16; 8]>> for u16[src]

type Output = u16x8

The resulting type after applying the * operator.

+

impl Mul<Simd<[u32; 16]>> for u32x16[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[u32; 16]>> for u32[src]

type Output = u32x16

The resulting type after applying the * operator.

+

impl Mul<Simd<[u32; 2]>> for u32x2[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[u32; 2]>> for u32[src]

type Output = u32x2

The resulting type after applying the * operator.

+

impl Mul<Simd<[u32; 4]>> for u32x4[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[u32; 4]>> for u32[src]

type Output = u32x4

The resulting type after applying the * operator.

+

impl Mul<Simd<[u32; 8]>> for u32x8[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[u32; 8]>> for u32[src]

type Output = u32x8

The resulting type after applying the * operator.

+

impl Mul<Simd<[u64; 2]>> for u64x2[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[u64; 2]>> for u64[src]

type Output = u64x2

The resulting type after applying the * operator.

+

impl Mul<Simd<[u64; 4]>> for u64x4[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[u64; 4]>> for u64[src]

type Output = u64x4

The resulting type after applying the * operator.

+

impl Mul<Simd<[u64; 8]>> for u64x8[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[u64; 8]>> for u64[src]

type Output = u64x8

The resulting type after applying the * operator.

+

impl Mul<Simd<[u8; 16]>> for u8x16[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[u8; 16]>> for u8[src]

type Output = u8x16

The resulting type after applying the * operator.

+

impl Mul<Simd<[u8; 2]>> for u8x2[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[u8; 2]>> for u8[src]

type Output = u8x2

The resulting type after applying the * operator.

+

impl Mul<Simd<[u8; 32]>> for u8x32[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[u8; 32]>> for u8[src]

type Output = u8x32

The resulting type after applying the * operator.

+

impl Mul<Simd<[u8; 4]>> for u8x4[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[u8; 4]>> for u8[src]

type Output = u8x4

The resulting type after applying the * operator.

+

impl Mul<Simd<[u8; 64]>> for u8x64[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[u8; 64]>> for u8[src]

type Output = u8x64

The resulting type after applying the * operator.

+

impl Mul<Simd<[u8; 8]>> for u8x8[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[u8; 8]>> for u8[src]

type Output = u8x8

The resulting type after applying the * operator.

+

impl Mul<Simd<[usize; 2]>> for usizex2[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[usize; 2]>> for usize[src]

type Output = usizex2

The resulting type after applying the * operator.

+

impl Mul<Simd<[usize; 4]>> for usizex4[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[usize; 4]>> for usize[src]

type Output = usizex4

The resulting type after applying the * operator.

+

impl Mul<Simd<[usize; 8]>> for usizex8[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<Simd<[usize; 8]>> for usize[src]

type Output = usizex8

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[f32; 16]>> for f32x16[src]

impl MulAssign<Simd<[f32; 2]>> for f32x2[src]

impl MulAssign<Simd<[f32; 4]>> for f32x4[src]

impl MulAssign<Simd<[f32; 8]>> for f32x8[src]

impl MulAssign<Simd<[f64; 2]>> for f64x2[src]

impl MulAssign<Simd<[f64; 4]>> for f64x4[src]

impl MulAssign<Simd<[f64; 8]>> for f64x8[src]

impl MulAssign<Simd<[i128; 1]>> for i128x1[src]

impl MulAssign<Simd<[i128; 2]>> for i128x2[src]

impl MulAssign<Simd<[i128; 4]>> for i128x4[src]

impl MulAssign<Simd<[i16; 16]>> for i16x16[src]

impl MulAssign<Simd<[i16; 2]>> for i16x2[src]

impl MulAssign<Simd<[i16; 32]>> for i16x32[src]

impl MulAssign<Simd<[i16; 4]>> for i16x4[src]

impl MulAssign<Simd<[i16; 8]>> for i16x8[src]

impl MulAssign<Simd<[i32; 16]>> for i32x16[src]

impl MulAssign<Simd<[i32; 2]>> for i32x2[src]

impl MulAssign<Simd<[i32; 4]>> for i32x4[src]

impl MulAssign<Simd<[i32; 8]>> for i32x8[src]

impl MulAssign<Simd<[i64; 2]>> for i64x2[src]

impl MulAssign<Simd<[i64; 4]>> for i64x4[src]

impl MulAssign<Simd<[i64; 8]>> for i64x8[src]

impl MulAssign<Simd<[i8; 16]>> for i8x16[src]

impl MulAssign<Simd<[i8; 2]>> for i8x2[src]

impl MulAssign<Simd<[i8; 32]>> for i8x32[src]

impl MulAssign<Simd<[i8; 4]>> for i8x4[src]

impl MulAssign<Simd<[i8; 64]>> for i8x64[src]

impl MulAssign<Simd<[i8; 8]>> for i8x8[src]

impl MulAssign<Simd<[isize; 2]>> for isizex2[src]

impl MulAssign<Simd<[isize; 4]>> for isizex4[src]

impl MulAssign<Simd<[isize; 8]>> for isizex8[src]

impl MulAssign<Simd<[u128; 1]>> for u128x1[src]

impl MulAssign<Simd<[u128; 2]>> for u128x2[src]

impl MulAssign<Simd<[u128; 4]>> for u128x4[src]

impl MulAssign<Simd<[u16; 16]>> for u16x16[src]

impl MulAssign<Simd<[u16; 2]>> for u16x2[src]

impl MulAssign<Simd<[u16; 32]>> for u16x32[src]

impl MulAssign<Simd<[u16; 4]>> for u16x4[src]

impl MulAssign<Simd<[u16; 8]>> for u16x8[src]

impl MulAssign<Simd<[u32; 16]>> for u32x16[src]

impl MulAssign<Simd<[u32; 2]>> for u32x2[src]

impl MulAssign<Simd<[u32; 4]>> for u32x4[src]

impl MulAssign<Simd<[u32; 8]>> for u32x8[src]

impl MulAssign<Simd<[u64; 2]>> for u64x2[src]

impl MulAssign<Simd<[u64; 4]>> for u64x4[src]

impl MulAssign<Simd<[u64; 8]>> for u64x8[src]

impl MulAssign<Simd<[u8; 16]>> for u8x16[src]

impl MulAssign<Simd<[u8; 2]>> for u8x2[src]

impl MulAssign<Simd<[u8; 32]>> for u8x32[src]

impl MulAssign<Simd<[u8; 4]>> for u8x4[src]

impl MulAssign<Simd<[u8; 64]>> for u8x64[src]

impl MulAssign<Simd<[u8; 8]>> for u8x8[src]

impl MulAssign<Simd<[usize; 2]>> for usizex2[src]

impl MulAssign<Simd<[usize; 4]>> for usizex4[src]

impl MulAssign<Simd<[usize; 8]>> for usizex8[src]

impl<T> PartialEq<Simd<[*const T; 2]>> for cptrx2<T>[src]

impl<T> PartialEq<Simd<[*const T; 4]>> for cptrx4<T>[src]

impl<T> PartialEq<Simd<[*const T; 8]>> for cptrx8<T>[src]

impl<T> PartialEq<Simd<[*mut T; 2]>> for mptrx2<T>[src]

impl<T> PartialEq<Simd<[*mut T; 4]>> for mptrx4<T>[src]

impl<T> PartialEq<Simd<[*mut T; 8]>> for mptrx8<T>[src]

impl PartialEq<Simd<[f32; 16]>> for f32x16[src]

impl PartialEq<Simd<[f32; 2]>> for f32x2[src]

impl PartialEq<Simd<[f32; 4]>> for f32x4[src]

impl PartialEq<Simd<[f32; 8]>> for f32x8[src]

impl PartialEq<Simd<[f64; 2]>> for f64x2[src]

impl PartialEq<Simd<[f64; 4]>> for f64x4[src]

impl PartialEq<Simd<[f64; 8]>> for f64x8[src]

impl PartialEq<Simd<[i128; 1]>> for i128x1[src]

impl PartialEq<Simd<[i128; 2]>> for i128x2[src]

impl PartialEq<Simd<[i128; 4]>> for i128x4[src]

impl PartialEq<Simd<[i16; 16]>> for i16x16[src]

impl PartialEq<Simd<[i16; 2]>> for i16x2[src]

impl PartialEq<Simd<[i16; 32]>> for i16x32[src]

impl PartialEq<Simd<[i16; 4]>> for i16x4[src]

impl PartialEq<Simd<[i16; 8]>> for i16x8[src]

impl PartialEq<Simd<[i32; 16]>> for i32x16[src]

impl PartialEq<Simd<[i32; 2]>> for i32x2[src]

impl PartialEq<Simd<[i32; 4]>> for i32x4[src]

impl PartialEq<Simd<[i32; 8]>> for i32x8[src]

impl PartialEq<Simd<[i64; 2]>> for i64x2[src]

impl PartialEq<Simd<[i64; 4]>> for i64x4[src]

impl PartialEq<Simd<[i64; 8]>> for i64x8[src]

impl PartialEq<Simd<[i8; 16]>> for i8x16[src]

impl PartialEq<Simd<[i8; 2]>> for i8x2[src]

impl PartialEq<Simd<[i8; 32]>> for i8x32[src]

impl PartialEq<Simd<[i8; 4]>> for i8x4[src]

impl PartialEq<Simd<[i8; 64]>> for i8x64[src]

impl PartialEq<Simd<[i8; 8]>> for i8x8[src]

impl PartialEq<Simd<[isize; 2]>> for isizex2[src]

impl PartialEq<Simd<[isize; 4]>> for isizex4[src]

impl PartialEq<Simd<[isize; 8]>> for isizex8[src]

impl PartialEq<Simd<[m128; 1]>> for m128x1[src]

impl PartialEq<Simd<[m128; 2]>> for m128x2[src]

impl PartialEq<Simd<[m128; 4]>> for m128x4[src]

impl PartialEq<Simd<[m16; 16]>> for m16x16[src]

impl PartialEq<Simd<[m16; 2]>> for m16x2[src]

impl PartialEq<Simd<[m16; 32]>> for m16x32[src]

impl PartialEq<Simd<[m16; 4]>> for m16x4[src]

impl PartialEq<Simd<[m16; 8]>> for m16x8[src]

impl PartialEq<Simd<[m32; 16]>> for m32x16[src]

impl PartialEq<Simd<[m32; 2]>> for m32x2[src]

impl PartialEq<Simd<[m32; 4]>> for m32x4[src]

impl PartialEq<Simd<[m32; 8]>> for m32x8[src]

impl PartialEq<Simd<[m64; 2]>> for m64x2[src]

impl PartialEq<Simd<[m64; 4]>> for m64x4[src]

impl PartialEq<Simd<[m64; 8]>> for m64x8[src]

impl PartialEq<Simd<[m8; 16]>> for m8x16[src]

impl PartialEq<Simd<[m8; 2]>> for m8x2[src]

impl PartialEq<Simd<[m8; 32]>> for m8x32[src]

impl PartialEq<Simd<[m8; 4]>> for m8x4[src]

impl PartialEq<Simd<[m8; 64]>> for m8x64[src]

impl PartialEq<Simd<[m8; 8]>> for m8x8[src]

impl PartialEq<Simd<[msize; 2]>> for msizex2[src]

impl PartialEq<Simd<[msize; 4]>> for msizex4[src]

impl PartialEq<Simd<[msize; 8]>> for msizex8[src]

impl PartialEq<Simd<[u128; 1]>> for u128x1[src]

impl PartialEq<Simd<[u128; 2]>> for u128x2[src]

impl PartialEq<Simd<[u128; 4]>> for u128x4[src]

impl PartialEq<Simd<[u16; 16]>> for u16x16[src]

impl PartialEq<Simd<[u16; 2]>> for u16x2[src]

impl PartialEq<Simd<[u16; 32]>> for u16x32[src]

impl PartialEq<Simd<[u16; 4]>> for u16x4[src]

impl PartialEq<Simd<[u16; 8]>> for u16x8[src]

impl PartialEq<Simd<[u32; 16]>> for u32x16[src]

impl PartialEq<Simd<[u32; 2]>> for u32x2[src]

impl PartialEq<Simd<[u32; 4]>> for u32x4[src]

impl PartialEq<Simd<[u32; 8]>> for u32x8[src]

impl PartialEq<Simd<[u64; 2]>> for u64x2[src]

impl PartialEq<Simd<[u64; 4]>> for u64x4[src]

impl PartialEq<Simd<[u64; 8]>> for u64x8[src]

impl PartialEq<Simd<[u8; 16]>> for u8x16[src]

impl PartialEq<Simd<[u8; 2]>> for u8x2[src]

impl PartialEq<Simd<[u8; 32]>> for u8x32[src]

impl PartialEq<Simd<[u8; 4]>> for u8x4[src]

impl PartialEq<Simd<[u8; 64]>> for u8x64[src]

impl PartialEq<Simd<[u8; 8]>> for u8x8[src]

impl PartialEq<Simd<[usize; 2]>> for usizex2[src]

impl PartialEq<Simd<[usize; 4]>> for usizex4[src]

impl PartialEq<Simd<[usize; 8]>> for usizex8[src]

impl<'a> Product<&'a Simd<[f32; 16]>> for f32x16[src]

impl<'a> Product<&'a Simd<[f32; 2]>> for f32x2[src]

impl<'a> Product<&'a Simd<[f32; 4]>> for f32x4[src]

impl<'a> Product<&'a Simd<[f32; 8]>> for f32x8[src]

impl<'a> Product<&'a Simd<[f64; 2]>> for f64x2[src]

impl<'a> Product<&'a Simd<[f64; 4]>> for f64x4[src]

impl<'a> Product<&'a Simd<[f64; 8]>> for f64x8[src]

impl<'a> Product<&'a Simd<[i128; 1]>> for i128x1[src]

impl<'a> Product<&'a Simd<[i128; 2]>> for i128x2[src]

impl<'a> Product<&'a Simd<[i128; 4]>> for i128x4[src]

impl<'a> Product<&'a Simd<[i16; 16]>> for i16x16[src]

impl<'a> Product<&'a Simd<[i16; 2]>> for i16x2[src]

impl<'a> Product<&'a Simd<[i16; 32]>> for i16x32[src]

impl<'a> Product<&'a Simd<[i16; 4]>> for i16x4[src]

impl<'a> Product<&'a Simd<[i16; 8]>> for i16x8[src]

impl<'a> Product<&'a Simd<[i32; 16]>> for i32x16[src]

impl<'a> Product<&'a Simd<[i32; 2]>> for i32x2[src]

impl<'a> Product<&'a Simd<[i32; 4]>> for i32x4[src]

impl<'a> Product<&'a Simd<[i32; 8]>> for i32x8[src]

impl<'a> Product<&'a Simd<[i64; 2]>> for i64x2[src]

impl<'a> Product<&'a Simd<[i64; 4]>> for i64x4[src]

impl<'a> Product<&'a Simd<[i64; 8]>> for i64x8[src]

impl<'a> Product<&'a Simd<[i8; 16]>> for i8x16[src]

impl<'a> Product<&'a Simd<[i8; 2]>> for i8x2[src]

impl<'a> Product<&'a Simd<[i8; 32]>> for i8x32[src]

impl<'a> Product<&'a Simd<[i8; 4]>> for i8x4[src]

impl<'a> Product<&'a Simd<[i8; 64]>> for i8x64[src]

impl<'a> Product<&'a Simd<[i8; 8]>> for i8x8[src]

impl<'a> Product<&'a Simd<[isize; 2]>> for isizex2[src]

impl<'a> Product<&'a Simd<[isize; 4]>> for isizex4[src]

impl<'a> Product<&'a Simd<[isize; 8]>> for isizex8[src]

impl<'a> Product<&'a Simd<[u128; 1]>> for u128x1[src]

impl<'a> Product<&'a Simd<[u128; 2]>> for u128x2[src]

impl<'a> Product<&'a Simd<[u128; 4]>> for u128x4[src]

impl<'a> Product<&'a Simd<[u16; 16]>> for u16x16[src]

impl<'a> Product<&'a Simd<[u16; 2]>> for u16x2[src]

impl<'a> Product<&'a Simd<[u16; 32]>> for u16x32[src]

impl<'a> Product<&'a Simd<[u16; 4]>> for u16x4[src]

impl<'a> Product<&'a Simd<[u16; 8]>> for u16x8[src]

impl<'a> Product<&'a Simd<[u32; 16]>> for u32x16[src]

impl<'a> Product<&'a Simd<[u32; 2]>> for u32x2[src]

impl<'a> Product<&'a Simd<[u32; 4]>> for u32x4[src]

impl<'a> Product<&'a Simd<[u32; 8]>> for u32x8[src]

impl<'a> Product<&'a Simd<[u64; 2]>> for u64x2[src]

impl<'a> Product<&'a Simd<[u64; 4]>> for u64x4[src]

impl<'a> Product<&'a Simd<[u64; 8]>> for u64x8[src]

impl<'a> Product<&'a Simd<[u8; 16]>> for u8x16[src]

impl<'a> Product<&'a Simd<[u8; 2]>> for u8x2[src]

impl<'a> Product<&'a Simd<[u8; 32]>> for u8x32[src]

impl<'a> Product<&'a Simd<[u8; 4]>> for u8x4[src]

impl<'a> Product<&'a Simd<[u8; 64]>> for u8x64[src]

impl<'a> Product<&'a Simd<[u8; 8]>> for u8x8[src]

impl<'a> Product<&'a Simd<[usize; 2]>> for usizex2[src]

impl<'a> Product<&'a Simd<[usize; 4]>> for usizex4[src]

impl<'a> Product<&'a Simd<[usize; 8]>> for usizex8[src]

impl Product<Simd<[f32; 16]>> for f32x16[src]

impl Product<Simd<[f32; 2]>> for f32x2[src]

impl Product<Simd<[f32; 4]>> for f32x4[src]

impl Product<Simd<[f32; 8]>> for f32x8[src]

impl Product<Simd<[f64; 2]>> for f64x2[src]

impl Product<Simd<[f64; 4]>> for f64x4[src]

impl Product<Simd<[f64; 8]>> for f64x8[src]

impl Product<Simd<[i128; 1]>> for i128x1[src]

impl Product<Simd<[i128; 2]>> for i128x2[src]

impl Product<Simd<[i128; 4]>> for i128x4[src]

impl Product<Simd<[i16; 16]>> for i16x16[src]

impl Product<Simd<[i16; 2]>> for i16x2[src]

impl Product<Simd<[i16; 32]>> for i16x32[src]

impl Product<Simd<[i16; 4]>> for i16x4[src]

impl Product<Simd<[i16; 8]>> for i16x8[src]

impl Product<Simd<[i32; 16]>> for i32x16[src]

impl Product<Simd<[i32; 2]>> for i32x2[src]

impl Product<Simd<[i32; 4]>> for i32x4[src]

impl Product<Simd<[i32; 8]>> for i32x8[src]

impl Product<Simd<[i64; 2]>> for i64x2[src]

impl Product<Simd<[i64; 4]>> for i64x4[src]

impl Product<Simd<[i64; 8]>> for i64x8[src]

impl Product<Simd<[i8; 16]>> for i8x16[src]

impl Product<Simd<[i8; 2]>> for i8x2[src]

impl Product<Simd<[i8; 32]>> for i8x32[src]

impl Product<Simd<[i8; 4]>> for i8x4[src]

impl Product<Simd<[i8; 64]>> for i8x64[src]

impl Product<Simd<[i8; 8]>> for i8x8[src]

impl Product<Simd<[isize; 2]>> for isizex2[src]

impl Product<Simd<[isize; 4]>> for isizex4[src]

impl Product<Simd<[isize; 8]>> for isizex8[src]

impl Product<Simd<[u128; 1]>> for u128x1[src]

impl Product<Simd<[u128; 2]>> for u128x2[src]

impl Product<Simd<[u128; 4]>> for u128x4[src]

impl Product<Simd<[u16; 16]>> for u16x16[src]

impl Product<Simd<[u16; 2]>> for u16x2[src]

impl Product<Simd<[u16; 32]>> for u16x32[src]

impl Product<Simd<[u16; 4]>> for u16x4[src]

impl Product<Simd<[u16; 8]>> for u16x8[src]

impl Product<Simd<[u32; 16]>> for u32x16[src]

impl Product<Simd<[u32; 2]>> for u32x2[src]

impl Product<Simd<[u32; 4]>> for u32x4[src]

impl Product<Simd<[u32; 8]>> for u32x8[src]

impl Product<Simd<[u64; 2]>> for u64x2[src]

impl Product<Simd<[u64; 4]>> for u64x4[src]

impl Product<Simd<[u64; 8]>> for u64x8[src]

impl Product<Simd<[u8; 16]>> for u8x16[src]

impl Product<Simd<[u8; 2]>> for u8x2[src]

impl Product<Simd<[u8; 32]>> for u8x32[src]

impl Product<Simd<[u8; 4]>> for u8x4[src]

impl Product<Simd<[u8; 64]>> for u8x64[src]

impl Product<Simd<[u8; 8]>> for u8x8[src]

impl Product<Simd<[usize; 2]>> for usizex2[src]

impl Product<Simd<[usize; 4]>> for usizex4[src]

impl Product<Simd<[usize; 8]>> for usizex8[src]

impl Rem<Simd<[f32; 16]>> for f32x16[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[f32; 16]>> for f32[src]

type Output = f32x16

The resulting type after applying the % operator.

+

impl Rem<Simd<[f32; 2]>> for f32x2[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[f32; 2]>> for f32[src]

type Output = f32x2

The resulting type after applying the % operator.

+

impl Rem<Simd<[f32; 4]>> for f32x4[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[f32; 4]>> for f32[src]

type Output = f32x4

The resulting type after applying the % operator.

+

impl Rem<Simd<[f32; 8]>> for f32x8[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[f32; 8]>> for f32[src]

type Output = f32x8

The resulting type after applying the % operator.

+

impl Rem<Simd<[f64; 2]>> for f64x2[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[f64; 2]>> for f64[src]

type Output = f64x2

The resulting type after applying the % operator.

+

impl Rem<Simd<[f64; 4]>> for f64x4[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[f64; 4]>> for f64[src]

type Output = f64x4

The resulting type after applying the % operator.

+

impl Rem<Simd<[f64; 8]>> for f64x8[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[f64; 8]>> for f64[src]

type Output = f64x8

The resulting type after applying the % operator.

+

impl Rem<Simd<[i128; 1]>> for i128x1[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[i128; 1]>> for i128[src]

type Output = i128x1

The resulting type after applying the % operator.

+

impl Rem<Simd<[i128; 2]>> for i128x2[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[i128; 2]>> for i128[src]

type Output = i128x2

The resulting type after applying the % operator.

+

impl Rem<Simd<[i128; 4]>> for i128x4[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[i128; 4]>> for i128[src]

type Output = i128x4

The resulting type after applying the % operator.

+

impl Rem<Simd<[i16; 16]>> for i16x16[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[i16; 16]>> for i16[src]

type Output = i16x16

The resulting type after applying the % operator.

+

impl Rem<Simd<[i16; 2]>> for i16x2[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[i16; 2]>> for i16[src]

type Output = i16x2

The resulting type after applying the % operator.

+

impl Rem<Simd<[i16; 32]>> for i16x32[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[i16; 32]>> for i16[src]

type Output = i16x32

The resulting type after applying the % operator.

+

impl Rem<Simd<[i16; 4]>> for i16x4[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[i16; 4]>> for i16[src]

type Output = i16x4

The resulting type after applying the % operator.

+

impl Rem<Simd<[i16; 8]>> for i16x8[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[i16; 8]>> for i16[src]

type Output = i16x8

The resulting type after applying the % operator.

+

impl Rem<Simd<[i32; 16]>> for i32x16[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[i32; 16]>> for i32[src]

type Output = i32x16

The resulting type after applying the % operator.

+

impl Rem<Simd<[i32; 2]>> for i32x2[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[i32; 2]>> for i32[src]

type Output = i32x2

The resulting type after applying the % operator.

+

impl Rem<Simd<[i32; 4]>> for i32x4[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[i32; 4]>> for i32[src]

type Output = i32x4

The resulting type after applying the % operator.

+

impl Rem<Simd<[i32; 8]>> for i32x8[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[i32; 8]>> for i32[src]

type Output = i32x8

The resulting type after applying the % operator.

+

impl Rem<Simd<[i64; 2]>> for i64x2[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[i64; 2]>> for i64[src]

type Output = i64x2

The resulting type after applying the % operator.

+

impl Rem<Simd<[i64; 4]>> for i64x4[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[i64; 4]>> for i64[src]

type Output = i64x4

The resulting type after applying the % operator.

+

impl Rem<Simd<[i64; 8]>> for i64x8[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[i64; 8]>> for i64[src]

type Output = i64x8

The resulting type after applying the % operator.

+

impl Rem<Simd<[i8; 16]>> for i8x16[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[i8; 16]>> for i8[src]

type Output = i8x16

The resulting type after applying the % operator.

+

impl Rem<Simd<[i8; 2]>> for i8x2[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[i8; 2]>> for i8[src]

type Output = i8x2

The resulting type after applying the % operator.

+

impl Rem<Simd<[i8; 32]>> for i8x32[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[i8; 32]>> for i8[src]

type Output = i8x32

The resulting type after applying the % operator.

+

impl Rem<Simd<[i8; 4]>> for i8x4[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[i8; 4]>> for i8[src]

type Output = i8x4

The resulting type after applying the % operator.

+

impl Rem<Simd<[i8; 64]>> for i8x64[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[i8; 64]>> for i8[src]

type Output = i8x64

The resulting type after applying the % operator.

+

impl Rem<Simd<[i8; 8]>> for i8x8[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[i8; 8]>> for i8[src]

type Output = i8x8

The resulting type after applying the % operator.

+

impl Rem<Simd<[isize; 2]>> for isizex2[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[isize; 2]>> for isize[src]

type Output = isizex2

The resulting type after applying the % operator.

+

impl Rem<Simd<[isize; 4]>> for isizex4[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[isize; 4]>> for isize[src]

type Output = isizex4

The resulting type after applying the % operator.

+

impl Rem<Simd<[isize; 8]>> for isizex8[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[isize; 8]>> for isize[src]

type Output = isizex8

The resulting type after applying the % operator.

+

impl Rem<Simd<[u128; 1]>> for u128x1[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[u128; 1]>> for u128[src]

type Output = u128x1

The resulting type after applying the % operator.

+

impl Rem<Simd<[u128; 2]>> for u128x2[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[u128; 2]>> for u128[src]

type Output = u128x2

The resulting type after applying the % operator.

+

impl Rem<Simd<[u128; 4]>> for u128x4[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[u128; 4]>> for u128[src]

type Output = u128x4

The resulting type after applying the % operator.

+

impl Rem<Simd<[u16; 16]>> for u16x16[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[u16; 16]>> for u16[src]

type Output = u16x16

The resulting type after applying the % operator.

+

impl Rem<Simd<[u16; 2]>> for u16x2[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[u16; 2]>> for u16[src]

type Output = u16x2

The resulting type after applying the % operator.

+

impl Rem<Simd<[u16; 32]>> for u16x32[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[u16; 32]>> for u16[src]

type Output = u16x32

The resulting type after applying the % operator.

+

impl Rem<Simd<[u16; 4]>> for u16x4[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[u16; 4]>> for u16[src]

type Output = u16x4

The resulting type after applying the % operator.

+

impl Rem<Simd<[u16; 8]>> for u16x8[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[u16; 8]>> for u16[src]

type Output = u16x8

The resulting type after applying the % operator.

+

impl Rem<Simd<[u32; 16]>> for u32x16[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[u32; 16]>> for u32[src]

type Output = u32x16

The resulting type after applying the % operator.

+

impl Rem<Simd<[u32; 2]>> for u32x2[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[u32; 2]>> for u32[src]

type Output = u32x2

The resulting type after applying the % operator.

+

impl Rem<Simd<[u32; 4]>> for u32x4[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[u32; 4]>> for u32[src]

type Output = u32x4

The resulting type after applying the % operator.

+

impl Rem<Simd<[u32; 8]>> for u32x8[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[u32; 8]>> for u32[src]

type Output = u32x8

The resulting type after applying the % operator.

+

impl Rem<Simd<[u64; 2]>> for u64x2[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[u64; 2]>> for u64[src]

type Output = u64x2

The resulting type after applying the % operator.

+

impl Rem<Simd<[u64; 4]>> for u64x4[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[u64; 4]>> for u64[src]

type Output = u64x4

The resulting type after applying the % operator.

+

impl Rem<Simd<[u64; 8]>> for u64x8[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[u64; 8]>> for u64[src]

type Output = u64x8

The resulting type after applying the % operator.

+

impl Rem<Simd<[u8; 16]>> for u8x16[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[u8; 16]>> for u8[src]

type Output = u8x16

The resulting type after applying the % operator.

+

impl Rem<Simd<[u8; 2]>> for u8x2[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[u8; 2]>> for u8[src]

type Output = u8x2

The resulting type after applying the % operator.

+

impl Rem<Simd<[u8; 32]>> for u8x32[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[u8; 32]>> for u8[src]

type Output = u8x32

The resulting type after applying the % operator.

+

impl Rem<Simd<[u8; 4]>> for u8x4[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[u8; 4]>> for u8[src]

type Output = u8x4

The resulting type after applying the % operator.

+

impl Rem<Simd<[u8; 64]>> for u8x64[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[u8; 64]>> for u8[src]

type Output = u8x64

The resulting type after applying the % operator.

+

impl Rem<Simd<[u8; 8]>> for u8x8[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[u8; 8]>> for u8[src]

type Output = u8x8

The resulting type after applying the % operator.

+

impl Rem<Simd<[usize; 2]>> for usizex2[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[usize; 2]>> for usize[src]

type Output = usizex2

The resulting type after applying the % operator.

+

impl Rem<Simd<[usize; 4]>> for usizex4[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[usize; 4]>> for usize[src]

type Output = usizex4

The resulting type after applying the % operator.

+

impl Rem<Simd<[usize; 8]>> for usizex8[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<Simd<[usize; 8]>> for usize[src]

type Output = usizex8

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[f32; 16]>> for f32x16[src]

impl RemAssign<Simd<[f32; 2]>> for f32x2[src]

impl RemAssign<Simd<[f32; 4]>> for f32x4[src]

impl RemAssign<Simd<[f32; 8]>> for f32x8[src]

impl RemAssign<Simd<[f64; 2]>> for f64x2[src]

impl RemAssign<Simd<[f64; 4]>> for f64x4[src]

impl RemAssign<Simd<[f64; 8]>> for f64x8[src]

impl RemAssign<Simd<[i128; 1]>> for i128x1[src]

impl RemAssign<Simd<[i128; 2]>> for i128x2[src]

impl RemAssign<Simd<[i128; 4]>> for i128x4[src]

impl RemAssign<Simd<[i16; 16]>> for i16x16[src]

impl RemAssign<Simd<[i16; 2]>> for i16x2[src]

impl RemAssign<Simd<[i16; 32]>> for i16x32[src]

impl RemAssign<Simd<[i16; 4]>> for i16x4[src]

impl RemAssign<Simd<[i16; 8]>> for i16x8[src]

impl RemAssign<Simd<[i32; 16]>> for i32x16[src]

impl RemAssign<Simd<[i32; 2]>> for i32x2[src]

impl RemAssign<Simd<[i32; 4]>> for i32x4[src]

impl RemAssign<Simd<[i32; 8]>> for i32x8[src]

impl RemAssign<Simd<[i64; 2]>> for i64x2[src]

impl RemAssign<Simd<[i64; 4]>> for i64x4[src]

impl RemAssign<Simd<[i64; 8]>> for i64x8[src]

impl RemAssign<Simd<[i8; 16]>> for i8x16[src]

impl RemAssign<Simd<[i8; 2]>> for i8x2[src]

impl RemAssign<Simd<[i8; 32]>> for i8x32[src]

impl RemAssign<Simd<[i8; 4]>> for i8x4[src]

impl RemAssign<Simd<[i8; 64]>> for i8x64[src]

impl RemAssign<Simd<[i8; 8]>> for i8x8[src]

impl RemAssign<Simd<[isize; 2]>> for isizex2[src]

impl RemAssign<Simd<[isize; 4]>> for isizex4[src]

impl RemAssign<Simd<[isize; 8]>> for isizex8[src]

impl RemAssign<Simd<[u128; 1]>> for u128x1[src]

impl RemAssign<Simd<[u128; 2]>> for u128x2[src]

impl RemAssign<Simd<[u128; 4]>> for u128x4[src]

impl RemAssign<Simd<[u16; 16]>> for u16x16[src]

impl RemAssign<Simd<[u16; 2]>> for u16x2[src]

impl RemAssign<Simd<[u16; 32]>> for u16x32[src]

impl RemAssign<Simd<[u16; 4]>> for u16x4[src]

impl RemAssign<Simd<[u16; 8]>> for u16x8[src]

impl RemAssign<Simd<[u32; 16]>> for u32x16[src]

impl RemAssign<Simd<[u32; 2]>> for u32x2[src]

impl RemAssign<Simd<[u32; 4]>> for u32x4[src]

impl RemAssign<Simd<[u32; 8]>> for u32x8[src]

impl RemAssign<Simd<[u64; 2]>> for u64x2[src]

impl RemAssign<Simd<[u64; 4]>> for u64x4[src]

impl RemAssign<Simd<[u64; 8]>> for u64x8[src]

impl RemAssign<Simd<[u8; 16]>> for u8x16[src]

impl RemAssign<Simd<[u8; 2]>> for u8x2[src]

impl RemAssign<Simd<[u8; 32]>> for u8x32[src]

impl RemAssign<Simd<[u8; 4]>> for u8x4[src]

impl RemAssign<Simd<[u8; 64]>> for u8x64[src]

impl RemAssign<Simd<[u8; 8]>> for u8x8[src]

impl RemAssign<Simd<[usize; 2]>> for usizex2[src]

impl RemAssign<Simd<[usize; 4]>> for usizex4[src]

impl RemAssign<Simd<[usize; 8]>> for usizex8[src]

impl Shl<Simd<[i128; 1]>> for i128x1[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<Simd<[i128; 2]>> for i128x2[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<Simd<[i128; 4]>> for i128x4[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<Simd<[i16; 16]>> for i16x16[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<Simd<[i16; 2]>> for i16x2[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<Simd<[i16; 32]>> for i16x32[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<Simd<[i16; 4]>> for i16x4[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<Simd<[i16; 8]>> for i16x8[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<Simd<[i32; 16]>> for i32x16[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<Simd<[i32; 2]>> for i32x2[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<Simd<[i32; 4]>> for i32x4[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<Simd<[i32; 8]>> for i32x8[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<Simd<[i64; 2]>> for i64x2[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<Simd<[i64; 4]>> for i64x4[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<Simd<[i64; 8]>> for i64x8[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<Simd<[i8; 16]>> for i8x16[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<Simd<[i8; 2]>> for i8x2[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<Simd<[i8; 32]>> for i8x32[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<Simd<[i8; 4]>> for i8x4[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<Simd<[i8; 64]>> for i8x64[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<Simd<[i8; 8]>> for i8x8[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<Simd<[isize; 2]>> for isizex2[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<Simd<[isize; 4]>> for isizex4[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<Simd<[isize; 8]>> for isizex8[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<Simd<[u128; 1]>> for u128x1[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<Simd<[u128; 2]>> for u128x2[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<Simd<[u128; 4]>> for u128x4[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<Simd<[u16; 16]>> for u16x16[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<Simd<[u16; 2]>> for u16x2[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<Simd<[u16; 32]>> for u16x32[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<Simd<[u16; 4]>> for u16x4[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<Simd<[u16; 8]>> for u16x8[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<Simd<[u32; 16]>> for u32x16[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<Simd<[u32; 2]>> for u32x2[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<Simd<[u32; 4]>> for u32x4[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<Simd<[u32; 8]>> for u32x8[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<Simd<[u64; 2]>> for u64x2[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<Simd<[u64; 4]>> for u64x4[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<Simd<[u64; 8]>> for u64x8[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<Simd<[u8; 16]>> for u8x16[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<Simd<[u8; 2]>> for u8x2[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<Simd<[u8; 32]>> for u8x32[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<Simd<[u8; 4]>> for u8x4[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<Simd<[u8; 64]>> for u8x64[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<Simd<[u8; 8]>> for u8x8[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<Simd<[usize; 2]>> for usizex2[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<Simd<[usize; 4]>> for usizex4[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<Simd<[usize; 8]>> for usizex8[src]

type Output = Self

The resulting type after applying the << operator.

+

impl ShlAssign<Simd<[i128; 1]>> for i128x1[src]

impl ShlAssign<Simd<[i128; 2]>> for i128x2[src]

impl ShlAssign<Simd<[i128; 4]>> for i128x4[src]

impl ShlAssign<Simd<[i16; 16]>> for i16x16[src]

impl ShlAssign<Simd<[i16; 2]>> for i16x2[src]

impl ShlAssign<Simd<[i16; 32]>> for i16x32[src]

impl ShlAssign<Simd<[i16; 4]>> for i16x4[src]

impl ShlAssign<Simd<[i16; 8]>> for i16x8[src]

impl ShlAssign<Simd<[i32; 16]>> for i32x16[src]

impl ShlAssign<Simd<[i32; 2]>> for i32x2[src]

impl ShlAssign<Simd<[i32; 4]>> for i32x4[src]

impl ShlAssign<Simd<[i32; 8]>> for i32x8[src]

impl ShlAssign<Simd<[i64; 2]>> for i64x2[src]

impl ShlAssign<Simd<[i64; 4]>> for i64x4[src]

impl ShlAssign<Simd<[i64; 8]>> for i64x8[src]

impl ShlAssign<Simd<[i8; 16]>> for i8x16[src]

impl ShlAssign<Simd<[i8; 2]>> for i8x2[src]

impl ShlAssign<Simd<[i8; 32]>> for i8x32[src]

impl ShlAssign<Simd<[i8; 4]>> for i8x4[src]

impl ShlAssign<Simd<[i8; 64]>> for i8x64[src]

impl ShlAssign<Simd<[i8; 8]>> for i8x8[src]

impl ShlAssign<Simd<[isize; 2]>> for isizex2[src]

impl ShlAssign<Simd<[isize; 4]>> for isizex4[src]

impl ShlAssign<Simd<[isize; 8]>> for isizex8[src]

impl ShlAssign<Simd<[u128; 1]>> for u128x1[src]

impl ShlAssign<Simd<[u128; 2]>> for u128x2[src]

impl ShlAssign<Simd<[u128; 4]>> for u128x4[src]

impl ShlAssign<Simd<[u16; 16]>> for u16x16[src]

impl ShlAssign<Simd<[u16; 2]>> for u16x2[src]

impl ShlAssign<Simd<[u16; 32]>> for u16x32[src]

impl ShlAssign<Simd<[u16; 4]>> for u16x4[src]

impl ShlAssign<Simd<[u16; 8]>> for u16x8[src]

impl ShlAssign<Simd<[u32; 16]>> for u32x16[src]

impl ShlAssign<Simd<[u32; 2]>> for u32x2[src]

impl ShlAssign<Simd<[u32; 4]>> for u32x4[src]

impl ShlAssign<Simd<[u32; 8]>> for u32x8[src]

impl ShlAssign<Simd<[u64; 2]>> for u64x2[src]

impl ShlAssign<Simd<[u64; 4]>> for u64x4[src]

impl ShlAssign<Simd<[u64; 8]>> for u64x8[src]

impl ShlAssign<Simd<[u8; 16]>> for u8x16[src]

impl ShlAssign<Simd<[u8; 2]>> for u8x2[src]

impl ShlAssign<Simd<[u8; 32]>> for u8x32[src]

impl ShlAssign<Simd<[u8; 4]>> for u8x4[src]

impl ShlAssign<Simd<[u8; 64]>> for u8x64[src]

impl ShlAssign<Simd<[u8; 8]>> for u8x8[src]

impl ShlAssign<Simd<[usize; 2]>> for usizex2[src]

impl ShlAssign<Simd<[usize; 4]>> for usizex4[src]

impl ShlAssign<Simd<[usize; 8]>> for usizex8[src]

impl Shr<Simd<[i128; 1]>> for i128x1[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<Simd<[i128; 2]>> for i128x2[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<Simd<[i128; 4]>> for i128x4[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<Simd<[i16; 16]>> for i16x16[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<Simd<[i16; 2]>> for i16x2[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<Simd<[i16; 32]>> for i16x32[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<Simd<[i16; 4]>> for i16x4[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<Simd<[i16; 8]>> for i16x8[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<Simd<[i32; 16]>> for i32x16[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<Simd<[i32; 2]>> for i32x2[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<Simd<[i32; 4]>> for i32x4[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<Simd<[i32; 8]>> for i32x8[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<Simd<[i64; 2]>> for i64x2[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<Simd<[i64; 4]>> for i64x4[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<Simd<[i64; 8]>> for i64x8[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<Simd<[i8; 16]>> for i8x16[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<Simd<[i8; 2]>> for i8x2[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<Simd<[i8; 32]>> for i8x32[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<Simd<[i8; 4]>> for i8x4[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<Simd<[i8; 64]>> for i8x64[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<Simd<[i8; 8]>> for i8x8[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<Simd<[isize; 2]>> for isizex2[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<Simd<[isize; 4]>> for isizex4[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<Simd<[isize; 8]>> for isizex8[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<Simd<[u128; 1]>> for u128x1[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<Simd<[u128; 2]>> for u128x2[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<Simd<[u128; 4]>> for u128x4[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<Simd<[u16; 16]>> for u16x16[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<Simd<[u16; 2]>> for u16x2[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<Simd<[u16; 32]>> for u16x32[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<Simd<[u16; 4]>> for u16x4[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<Simd<[u16; 8]>> for u16x8[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<Simd<[u32; 16]>> for u32x16[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<Simd<[u32; 2]>> for u32x2[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<Simd<[u32; 4]>> for u32x4[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<Simd<[u32; 8]>> for u32x8[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<Simd<[u64; 2]>> for u64x2[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<Simd<[u64; 4]>> for u64x4[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<Simd<[u64; 8]>> for u64x8[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<Simd<[u8; 16]>> for u8x16[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<Simd<[u8; 2]>> for u8x2[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<Simd<[u8; 32]>> for u8x32[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<Simd<[u8; 4]>> for u8x4[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<Simd<[u8; 64]>> for u8x64[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<Simd<[u8; 8]>> for u8x8[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<Simd<[usize; 2]>> for usizex2[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<Simd<[usize; 4]>> for usizex4[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<Simd<[usize; 8]>> for usizex8[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl ShrAssign<Simd<[i128; 1]>> for i128x1[src]

impl ShrAssign<Simd<[i128; 2]>> for i128x2[src]

impl ShrAssign<Simd<[i128; 4]>> for i128x4[src]

impl ShrAssign<Simd<[i16; 16]>> for i16x16[src]

impl ShrAssign<Simd<[i16; 2]>> for i16x2[src]

impl ShrAssign<Simd<[i16; 32]>> for i16x32[src]

impl ShrAssign<Simd<[i16; 4]>> for i16x4[src]

impl ShrAssign<Simd<[i16; 8]>> for i16x8[src]

impl ShrAssign<Simd<[i32; 16]>> for i32x16[src]

impl ShrAssign<Simd<[i32; 2]>> for i32x2[src]

impl ShrAssign<Simd<[i32; 4]>> for i32x4[src]

impl ShrAssign<Simd<[i32; 8]>> for i32x8[src]

impl ShrAssign<Simd<[i64; 2]>> for i64x2[src]

impl ShrAssign<Simd<[i64; 4]>> for i64x4[src]

impl ShrAssign<Simd<[i64; 8]>> for i64x8[src]

impl ShrAssign<Simd<[i8; 16]>> for i8x16[src]

impl ShrAssign<Simd<[i8; 2]>> for i8x2[src]

impl ShrAssign<Simd<[i8; 32]>> for i8x32[src]

impl ShrAssign<Simd<[i8; 4]>> for i8x4[src]

impl ShrAssign<Simd<[i8; 64]>> for i8x64[src]

impl ShrAssign<Simd<[i8; 8]>> for i8x8[src]

impl ShrAssign<Simd<[isize; 2]>> for isizex2[src]

impl ShrAssign<Simd<[isize; 4]>> for isizex4[src]

impl ShrAssign<Simd<[isize; 8]>> for isizex8[src]

impl ShrAssign<Simd<[u128; 1]>> for u128x1[src]

impl ShrAssign<Simd<[u128; 2]>> for u128x2[src]

impl ShrAssign<Simd<[u128; 4]>> for u128x4[src]

impl ShrAssign<Simd<[u16; 16]>> for u16x16[src]

impl ShrAssign<Simd<[u16; 2]>> for u16x2[src]

impl ShrAssign<Simd<[u16; 32]>> for u16x32[src]

impl ShrAssign<Simd<[u16; 4]>> for u16x4[src]

impl ShrAssign<Simd<[u16; 8]>> for u16x8[src]

impl ShrAssign<Simd<[u32; 16]>> for u32x16[src]

impl ShrAssign<Simd<[u32; 2]>> for u32x2[src]

impl ShrAssign<Simd<[u32; 4]>> for u32x4[src]

impl ShrAssign<Simd<[u32; 8]>> for u32x8[src]

impl ShrAssign<Simd<[u64; 2]>> for u64x2[src]

impl ShrAssign<Simd<[u64; 4]>> for u64x4[src]

impl ShrAssign<Simd<[u64; 8]>> for u64x8[src]

impl ShrAssign<Simd<[u8; 16]>> for u8x16[src]

impl ShrAssign<Simd<[u8; 2]>> for u8x2[src]

impl ShrAssign<Simd<[u8; 32]>> for u8x32[src]

impl ShrAssign<Simd<[u8; 4]>> for u8x4[src]

impl ShrAssign<Simd<[u8; 64]>> for u8x64[src]

impl ShrAssign<Simd<[u8; 8]>> for u8x8[src]

impl ShrAssign<Simd<[usize; 2]>> for usizex2[src]

impl ShrAssign<Simd<[usize; 4]>> for usizex4[src]

impl ShrAssign<Simd<[usize; 8]>> for usizex8[src]

impl Sub<Simd<[f32; 16]>> for f32x16[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[f32; 16]>> for f32[src]

type Output = f32x16

The resulting type after applying the - operator.

+

impl Sub<Simd<[f32; 2]>> for f32x2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[f32; 2]>> for f32[src]

type Output = f32x2

The resulting type after applying the - operator.

+

impl Sub<Simd<[f32; 4]>> for f32x4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[f32; 4]>> for f32[src]

type Output = f32x4

The resulting type after applying the - operator.

+

impl Sub<Simd<[f32; 8]>> for f32x8[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[f32; 8]>> for f32[src]

type Output = f32x8

The resulting type after applying the - operator.

+

impl Sub<Simd<[f64; 2]>> for f64x2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[f64; 2]>> for f64[src]

type Output = f64x2

The resulting type after applying the - operator.

+

impl Sub<Simd<[f64; 4]>> for f64x4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[f64; 4]>> for f64[src]

type Output = f64x4

The resulting type after applying the - operator.

+

impl Sub<Simd<[f64; 8]>> for f64x8[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[f64; 8]>> for f64[src]

type Output = f64x8

The resulting type after applying the - operator.

+

impl Sub<Simd<[i128; 1]>> for i128x1[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[i128; 1]>> for i128[src]

type Output = i128x1

The resulting type after applying the - operator.

+

impl Sub<Simd<[i128; 2]>> for i128x2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[i128; 2]>> for i128[src]

type Output = i128x2

The resulting type after applying the - operator.

+

impl Sub<Simd<[i128; 4]>> for i128x4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[i128; 4]>> for i128[src]

type Output = i128x4

The resulting type after applying the - operator.

+

impl Sub<Simd<[i16; 16]>> for i16x16[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[i16; 16]>> for i16[src]

type Output = i16x16

The resulting type after applying the - operator.

+

impl Sub<Simd<[i16; 2]>> for i16x2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[i16; 2]>> for i16[src]

type Output = i16x2

The resulting type after applying the - operator.

+

impl Sub<Simd<[i16; 32]>> for i16x32[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[i16; 32]>> for i16[src]

type Output = i16x32

The resulting type after applying the - operator.

+

impl Sub<Simd<[i16; 4]>> for i16x4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[i16; 4]>> for i16[src]

type Output = i16x4

The resulting type after applying the - operator.

+

impl Sub<Simd<[i16; 8]>> for i16x8[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[i16; 8]>> for i16[src]

type Output = i16x8

The resulting type after applying the - operator.

+

impl Sub<Simd<[i32; 16]>> for i32x16[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[i32; 16]>> for i32[src]

type Output = i32x16

The resulting type after applying the - operator.

+

impl Sub<Simd<[i32; 2]>> for i32x2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[i32; 2]>> for i32[src]

type Output = i32x2

The resulting type after applying the - operator.

+

impl Sub<Simd<[i32; 4]>> for i32x4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[i32; 4]>> for i32[src]

type Output = i32x4

The resulting type after applying the - operator.

+

impl Sub<Simd<[i32; 8]>> for i32x8[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[i32; 8]>> for i32[src]

type Output = i32x8

The resulting type after applying the - operator.

+

impl Sub<Simd<[i64; 2]>> for i64x2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[i64; 2]>> for i64[src]

type Output = i64x2

The resulting type after applying the - operator.

+

impl Sub<Simd<[i64; 4]>> for i64x4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[i64; 4]>> for i64[src]

type Output = i64x4

The resulting type after applying the - operator.

+

impl Sub<Simd<[i64; 8]>> for i64x8[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[i64; 8]>> for i64[src]

type Output = i64x8

The resulting type after applying the - operator.

+

impl Sub<Simd<[i8; 16]>> for i8x16[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[i8; 16]>> for i8[src]

type Output = i8x16

The resulting type after applying the - operator.

+

impl Sub<Simd<[i8; 2]>> for i8x2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[i8; 2]>> for i8[src]

type Output = i8x2

The resulting type after applying the - operator.

+

impl Sub<Simd<[i8; 32]>> for i8x32[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[i8; 32]>> for i8[src]

type Output = i8x32

The resulting type after applying the - operator.

+

impl Sub<Simd<[i8; 4]>> for i8x4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[i8; 4]>> for i8[src]

type Output = i8x4

The resulting type after applying the - operator.

+

impl Sub<Simd<[i8; 64]>> for i8x64[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[i8; 64]>> for i8[src]

type Output = i8x64

The resulting type after applying the - operator.

+

impl Sub<Simd<[i8; 8]>> for i8x8[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[i8; 8]>> for i8[src]

type Output = i8x8

The resulting type after applying the - operator.

+

impl Sub<Simd<[isize; 2]>> for isizex2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[isize; 2]>> for isize[src]

type Output = isizex2

The resulting type after applying the - operator.

+

impl Sub<Simd<[isize; 4]>> for isizex4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[isize; 4]>> for isize[src]

type Output = isizex4

The resulting type after applying the - operator.

+

impl Sub<Simd<[isize; 8]>> for isizex8[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[isize; 8]>> for isize[src]

type Output = isizex8

The resulting type after applying the - operator.

+

impl Sub<Simd<[u128; 1]>> for u128x1[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[u128; 1]>> for u128[src]

type Output = u128x1

The resulting type after applying the - operator.

+

impl Sub<Simd<[u128; 2]>> for u128x2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[u128; 2]>> for u128[src]

type Output = u128x2

The resulting type after applying the - operator.

+

impl Sub<Simd<[u128; 4]>> for u128x4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[u128; 4]>> for u128[src]

type Output = u128x4

The resulting type after applying the - operator.

+

impl Sub<Simd<[u16; 16]>> for u16x16[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[u16; 16]>> for u16[src]

type Output = u16x16

The resulting type after applying the - operator.

+

impl Sub<Simd<[u16; 2]>> for u16x2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[u16; 2]>> for u16[src]

type Output = u16x2

The resulting type after applying the - operator.

+

impl Sub<Simd<[u16; 32]>> for u16x32[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[u16; 32]>> for u16[src]

type Output = u16x32

The resulting type after applying the - operator.

+

impl Sub<Simd<[u16; 4]>> for u16x4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[u16; 4]>> for u16[src]

type Output = u16x4

The resulting type after applying the - operator.

+

impl Sub<Simd<[u16; 8]>> for u16x8[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[u16; 8]>> for u16[src]

type Output = u16x8

The resulting type after applying the - operator.

+

impl Sub<Simd<[u32; 16]>> for u32x16[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[u32; 16]>> for u32[src]

type Output = u32x16

The resulting type after applying the - operator.

+

impl Sub<Simd<[u32; 2]>> for u32x2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[u32; 2]>> for u32[src]

type Output = u32x2

The resulting type after applying the - operator.

+

impl Sub<Simd<[u32; 4]>> for u32x4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[u32; 4]>> for u32[src]

type Output = u32x4

The resulting type after applying the - operator.

+

impl Sub<Simd<[u32; 8]>> for u32x8[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[u32; 8]>> for u32[src]

type Output = u32x8

The resulting type after applying the - operator.

+

impl Sub<Simd<[u64; 2]>> for u64x2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[u64; 2]>> for u64[src]

type Output = u64x2

The resulting type after applying the - operator.

+

impl Sub<Simd<[u64; 4]>> for u64x4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[u64; 4]>> for u64[src]

type Output = u64x4

The resulting type after applying the - operator.

+

impl Sub<Simd<[u64; 8]>> for u64x8[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[u64; 8]>> for u64[src]

type Output = u64x8

The resulting type after applying the - operator.

+

impl Sub<Simd<[u8; 16]>> for u8x16[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[u8; 16]>> for u8[src]

type Output = u8x16

The resulting type after applying the - operator.

+

impl Sub<Simd<[u8; 2]>> for u8x2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[u8; 2]>> for u8[src]

type Output = u8x2

The resulting type after applying the - operator.

+

impl Sub<Simd<[u8; 32]>> for u8x32[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[u8; 32]>> for u8[src]

type Output = u8x32

The resulting type after applying the - operator.

+

impl Sub<Simd<[u8; 4]>> for u8x4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[u8; 4]>> for u8[src]

type Output = u8x4

The resulting type after applying the - operator.

+

impl Sub<Simd<[u8; 64]>> for u8x64[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[u8; 64]>> for u8[src]

type Output = u8x64

The resulting type after applying the - operator.

+

impl Sub<Simd<[u8; 8]>> for u8x8[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[u8; 8]>> for u8[src]

type Output = u8x8

The resulting type after applying the - operator.

+

impl Sub<Simd<[usize; 2]>> for usizex2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[usize; 2]>> for usize[src]

type Output = usizex2

The resulting type after applying the - operator.

+

impl Sub<Simd<[usize; 4]>> for usizex4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[usize; 4]>> for usize[src]

type Output = usizex4

The resulting type after applying the - operator.

+

impl Sub<Simd<[usize; 8]>> for usizex8[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<Simd<[usize; 8]>> for usize[src]

type Output = usizex8

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[f32; 16]>> for f32x16[src]

impl SubAssign<Simd<[f32; 2]>> for f32x2[src]

impl SubAssign<Simd<[f32; 4]>> for f32x4[src]

impl SubAssign<Simd<[f32; 8]>> for f32x8[src]

impl SubAssign<Simd<[f64; 2]>> for f64x2[src]

impl SubAssign<Simd<[f64; 4]>> for f64x4[src]

impl SubAssign<Simd<[f64; 8]>> for f64x8[src]

impl SubAssign<Simd<[i128; 1]>> for i128x1[src]

impl SubAssign<Simd<[i128; 2]>> for i128x2[src]

impl SubAssign<Simd<[i128; 4]>> for i128x4[src]

impl SubAssign<Simd<[i16; 16]>> for i16x16[src]

impl SubAssign<Simd<[i16; 2]>> for i16x2[src]

impl SubAssign<Simd<[i16; 32]>> for i16x32[src]

impl SubAssign<Simd<[i16; 4]>> for i16x4[src]

impl SubAssign<Simd<[i16; 8]>> for i16x8[src]

impl SubAssign<Simd<[i32; 16]>> for i32x16[src]

impl SubAssign<Simd<[i32; 2]>> for i32x2[src]

impl SubAssign<Simd<[i32; 4]>> for i32x4[src]

impl SubAssign<Simd<[i32; 8]>> for i32x8[src]

impl SubAssign<Simd<[i64; 2]>> for i64x2[src]

impl SubAssign<Simd<[i64; 4]>> for i64x4[src]

impl SubAssign<Simd<[i64; 8]>> for i64x8[src]

impl SubAssign<Simd<[i8; 16]>> for i8x16[src]

impl SubAssign<Simd<[i8; 2]>> for i8x2[src]

impl SubAssign<Simd<[i8; 32]>> for i8x32[src]

impl SubAssign<Simd<[i8; 4]>> for i8x4[src]

impl SubAssign<Simd<[i8; 64]>> for i8x64[src]

impl SubAssign<Simd<[i8; 8]>> for i8x8[src]

impl SubAssign<Simd<[isize; 2]>> for isizex2[src]

impl SubAssign<Simd<[isize; 4]>> for isizex4[src]

impl SubAssign<Simd<[isize; 8]>> for isizex8[src]

impl SubAssign<Simd<[u128; 1]>> for u128x1[src]

impl SubAssign<Simd<[u128; 2]>> for u128x2[src]

impl SubAssign<Simd<[u128; 4]>> for u128x4[src]

impl SubAssign<Simd<[u16; 16]>> for u16x16[src]

impl SubAssign<Simd<[u16; 2]>> for u16x2[src]

impl SubAssign<Simd<[u16; 32]>> for u16x32[src]

impl SubAssign<Simd<[u16; 4]>> for u16x4[src]

impl SubAssign<Simd<[u16; 8]>> for u16x8[src]

impl SubAssign<Simd<[u32; 16]>> for u32x16[src]

impl SubAssign<Simd<[u32; 2]>> for u32x2[src]

impl SubAssign<Simd<[u32; 4]>> for u32x4[src]

impl SubAssign<Simd<[u32; 8]>> for u32x8[src]

impl SubAssign<Simd<[u64; 2]>> for u64x2[src]

impl SubAssign<Simd<[u64; 4]>> for u64x4[src]

impl SubAssign<Simd<[u64; 8]>> for u64x8[src]

impl SubAssign<Simd<[u8; 16]>> for u8x16[src]

impl SubAssign<Simd<[u8; 2]>> for u8x2[src]

impl SubAssign<Simd<[u8; 32]>> for u8x32[src]

impl SubAssign<Simd<[u8; 4]>> for u8x4[src]

impl SubAssign<Simd<[u8; 64]>> for u8x64[src]

impl SubAssign<Simd<[u8; 8]>> for u8x8[src]

impl SubAssign<Simd<[usize; 2]>> for usizex2[src]

impl SubAssign<Simd<[usize; 4]>> for usizex4[src]

impl SubAssign<Simd<[usize; 8]>> for usizex8[src]

impl<'a> Sum<&'a Simd<[f32; 16]>> for f32x16[src]

impl<'a> Sum<&'a Simd<[f32; 2]>> for f32x2[src]

impl<'a> Sum<&'a Simd<[f32; 4]>> for f32x4[src]

impl<'a> Sum<&'a Simd<[f32; 8]>> for f32x8[src]

impl<'a> Sum<&'a Simd<[f64; 2]>> for f64x2[src]

impl<'a> Sum<&'a Simd<[f64; 4]>> for f64x4[src]

impl<'a> Sum<&'a Simd<[f64; 8]>> for f64x8[src]

impl<'a> Sum<&'a Simd<[i128; 1]>> for i128x1[src]

impl<'a> Sum<&'a Simd<[i128; 2]>> for i128x2[src]

impl<'a> Sum<&'a Simd<[i128; 4]>> for i128x4[src]

impl<'a> Sum<&'a Simd<[i16; 16]>> for i16x16[src]

impl<'a> Sum<&'a Simd<[i16; 2]>> for i16x2[src]

impl<'a> Sum<&'a Simd<[i16; 32]>> for i16x32[src]

impl<'a> Sum<&'a Simd<[i16; 4]>> for i16x4[src]

impl<'a> Sum<&'a Simd<[i16; 8]>> for i16x8[src]

impl<'a> Sum<&'a Simd<[i32; 16]>> for i32x16[src]

impl<'a> Sum<&'a Simd<[i32; 2]>> for i32x2[src]

impl<'a> Sum<&'a Simd<[i32; 4]>> for i32x4[src]

impl<'a> Sum<&'a Simd<[i32; 8]>> for i32x8[src]

impl<'a> Sum<&'a Simd<[i64; 2]>> for i64x2[src]

impl<'a> Sum<&'a Simd<[i64; 4]>> for i64x4[src]

impl<'a> Sum<&'a Simd<[i64; 8]>> for i64x8[src]

impl<'a> Sum<&'a Simd<[i8; 16]>> for i8x16[src]

impl<'a> Sum<&'a Simd<[i8; 2]>> for i8x2[src]

impl<'a> Sum<&'a Simd<[i8; 32]>> for i8x32[src]

impl<'a> Sum<&'a Simd<[i8; 4]>> for i8x4[src]

impl<'a> Sum<&'a Simd<[i8; 64]>> for i8x64[src]

impl<'a> Sum<&'a Simd<[i8; 8]>> for i8x8[src]

impl<'a> Sum<&'a Simd<[isize; 2]>> for isizex2[src]

impl<'a> Sum<&'a Simd<[isize; 4]>> for isizex4[src]

impl<'a> Sum<&'a Simd<[isize; 8]>> for isizex8[src]

impl<'a> Sum<&'a Simd<[u128; 1]>> for u128x1[src]

impl<'a> Sum<&'a Simd<[u128; 2]>> for u128x2[src]

impl<'a> Sum<&'a Simd<[u128; 4]>> for u128x4[src]

impl<'a> Sum<&'a Simd<[u16; 16]>> for u16x16[src]

impl<'a> Sum<&'a Simd<[u16; 2]>> for u16x2[src]

impl<'a> Sum<&'a Simd<[u16; 32]>> for u16x32[src]

impl<'a> Sum<&'a Simd<[u16; 4]>> for u16x4[src]

impl<'a> Sum<&'a Simd<[u16; 8]>> for u16x8[src]

impl<'a> Sum<&'a Simd<[u32; 16]>> for u32x16[src]

impl<'a> Sum<&'a Simd<[u32; 2]>> for u32x2[src]

impl<'a> Sum<&'a Simd<[u32; 4]>> for u32x4[src]

impl<'a> Sum<&'a Simd<[u32; 8]>> for u32x8[src]

impl<'a> Sum<&'a Simd<[u64; 2]>> for u64x2[src]

impl<'a> Sum<&'a Simd<[u64; 4]>> for u64x4[src]

impl<'a> Sum<&'a Simd<[u64; 8]>> for u64x8[src]

impl<'a> Sum<&'a Simd<[u8; 16]>> for u8x16[src]

impl<'a> Sum<&'a Simd<[u8; 2]>> for u8x2[src]

impl<'a> Sum<&'a Simd<[u8; 32]>> for u8x32[src]

impl<'a> Sum<&'a Simd<[u8; 4]>> for u8x4[src]

impl<'a> Sum<&'a Simd<[u8; 64]>> for u8x64[src]

impl<'a> Sum<&'a Simd<[u8; 8]>> for u8x8[src]

impl<'a> Sum<&'a Simd<[usize; 2]>> for usizex2[src]

impl<'a> Sum<&'a Simd<[usize; 4]>> for usizex4[src]

impl<'a> Sum<&'a Simd<[usize; 8]>> for usizex8[src]

impl Sum<Simd<[f32; 16]>> for f32x16[src]

impl Sum<Simd<[f32; 2]>> for f32x2[src]

impl Sum<Simd<[f32; 4]>> for f32x4[src]

impl Sum<Simd<[f32; 8]>> for f32x8[src]

impl Sum<Simd<[f64; 2]>> for f64x2[src]

impl Sum<Simd<[f64; 4]>> for f64x4[src]

impl Sum<Simd<[f64; 8]>> for f64x8[src]

impl Sum<Simd<[i128; 1]>> for i128x1[src]

impl Sum<Simd<[i128; 2]>> for i128x2[src]

impl Sum<Simd<[i128; 4]>> for i128x4[src]

impl Sum<Simd<[i16; 16]>> for i16x16[src]

impl Sum<Simd<[i16; 2]>> for i16x2[src]

impl Sum<Simd<[i16; 32]>> for i16x32[src]

impl Sum<Simd<[i16; 4]>> for i16x4[src]

impl Sum<Simd<[i16; 8]>> for i16x8[src]

impl Sum<Simd<[i32; 16]>> for i32x16[src]

impl Sum<Simd<[i32; 2]>> for i32x2[src]

impl Sum<Simd<[i32; 4]>> for i32x4[src]

impl Sum<Simd<[i32; 8]>> for i32x8[src]

impl Sum<Simd<[i64; 2]>> for i64x2[src]

impl Sum<Simd<[i64; 4]>> for i64x4[src]

impl Sum<Simd<[i64; 8]>> for i64x8[src]

impl Sum<Simd<[i8; 16]>> for i8x16[src]

impl Sum<Simd<[i8; 2]>> for i8x2[src]

impl Sum<Simd<[i8; 32]>> for i8x32[src]

impl Sum<Simd<[i8; 4]>> for i8x4[src]

impl Sum<Simd<[i8; 64]>> for i8x64[src]

impl Sum<Simd<[i8; 8]>> for i8x8[src]

impl Sum<Simd<[isize; 2]>> for isizex2[src]

impl Sum<Simd<[isize; 4]>> for isizex4[src]

impl Sum<Simd<[isize; 8]>> for isizex8[src]

impl Sum<Simd<[u128; 1]>> for u128x1[src]

impl Sum<Simd<[u128; 2]>> for u128x2[src]

impl Sum<Simd<[u128; 4]>> for u128x4[src]

impl Sum<Simd<[u16; 16]>> for u16x16[src]

impl Sum<Simd<[u16; 2]>> for u16x2[src]

impl Sum<Simd<[u16; 32]>> for u16x32[src]

impl Sum<Simd<[u16; 4]>> for u16x4[src]

impl Sum<Simd<[u16; 8]>> for u16x8[src]

impl Sum<Simd<[u32; 16]>> for u32x16[src]

impl Sum<Simd<[u32; 2]>> for u32x2[src]

impl Sum<Simd<[u32; 4]>> for u32x4[src]

impl Sum<Simd<[u32; 8]>> for u32x8[src]

impl Sum<Simd<[u64; 2]>> for u64x2[src]

impl Sum<Simd<[u64; 4]>> for u64x4[src]

impl Sum<Simd<[u64; 8]>> for u64x8[src]

impl Sum<Simd<[u8; 16]>> for u8x16[src]

impl Sum<Simd<[u8; 2]>> for u8x2[src]

impl Sum<Simd<[u8; 32]>> for u8x32[src]

impl Sum<Simd<[u8; 4]>> for u8x4[src]

impl Sum<Simd<[u8; 64]>> for u8x64[src]

impl Sum<Simd<[u8; 8]>> for u8x8[src]

impl Sum<Simd<[usize; 2]>> for usizex2[src]

impl Sum<Simd<[usize; 4]>> for usizex4[src]

impl Sum<Simd<[usize; 8]>> for usizex8[src]

Auto Trait Implementations

impl<A> Send for Simd<A> where
    <A as SimdArray>::Tuple: Send, 

impl<A> Sync for Simd<A> where
    <A as SimdArray>::Tuple: Sync, 

impl<A> Unpin for Simd<A> where
    <A as SimdArray>::Tuple: Unpin, 

Blanket Implementations

impl<T> Any for T where
    T: 'static + ?Sized, [src]

impl<T> Borrow<T> for T where
    T: ?Sized, [src]

impl<T> BorrowMut<T> for T where
    T: ?Sized, [src]

impl<T> From<T> for T[src]

impl<T, U> Into<U> for T where
    U: From<T>, [src]

impl<T, U> TryFrom<U> for T where
    U: Into<T>, [src]

type Error = Infallible

The type returned in the event of a conversion error.

+

impl<T, U> TryInto<U> for T where
    U: TryFrom<T>, [src]

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.

+
\ No newline at end of file diff --git a/packed_simd/struct.m128.html b/packed_simd/struct.m128.html new file mode 100644 index 000000000..f836438aa --- /dev/null +++ b/packed_simd/struct.m128.html @@ -0,0 +1,30 @@ +packed_simd::m128 - Rust

[−][src]Struct packed_simd::m128

pub struct m128(_);

128-bit wide mask.

+

Implementations

impl m128[src]

pub fn new(x: bool) -> Self[src]

Instantiate a mask with value

+

pub fn test(&self) -> bool[src]

Test if the mask is set

+

Trait Implementations

impl Clone for m128[src]

impl Copy for m128[src]

impl Debug for m128[src]

impl Default for m128[src]

impl Eq for m128[src]

impl Hash for m128[src]

impl Mask for m128[src]

impl Ord for m128[src]

impl PartialEq<m128> for m128[src]

impl PartialOrd<m128> for m128[src]

Auto Trait Implementations

impl Send for m128

impl Sync for m128

impl Unpin for m128

Blanket Implementations

impl<T> Any for T where
    T: 'static + ?Sized, [src]

impl<T> Borrow<T> for T where
    T: ?Sized, [src]

impl<T> BorrowMut<T> for T where
    T: ?Sized, [src]

impl<T> From<T> for T[src]

impl<T, U> Into<U> for T where
    U: From<T>, [src]

impl<T, U> TryFrom<U> for T where
    U: Into<T>, [src]

type Error = Infallible

The type returned in the event of a conversion error.

+

impl<T, U> TryInto<U> for T where
    U: TryFrom<T>, [src]

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.

+
\ No newline at end of file diff --git a/packed_simd/struct.m16.html b/packed_simd/struct.m16.html new file mode 100644 index 000000000..e45ef81ee --- /dev/null +++ b/packed_simd/struct.m16.html @@ -0,0 +1,30 @@ +packed_simd::m16 - Rust

[−][src]Struct packed_simd::m16

pub struct m16(_);

16-bit wide mask.

+

Implementations

impl m16[src]

pub fn new(x: bool) -> Self[src]

Instantiate a mask with value

+

pub fn test(&self) -> bool[src]

Test if the mask is set

+

Trait Implementations

impl Clone for m16[src]

impl Copy for m16[src]

impl Debug for m16[src]

impl Default for m16[src]

impl Eq for m16[src]

impl Hash for m16[src]

impl Mask for m16[src]

impl Ord for m16[src]

impl PartialEq<m16> for m16[src]

impl PartialOrd<m16> for m16[src]

Auto Trait Implementations

impl Send for m16

impl Sync for m16

impl Unpin for m16

Blanket Implementations

impl<T> Any for T where
    T: 'static + ?Sized, [src]

impl<T> Borrow<T> for T where
    T: ?Sized, [src]

impl<T> BorrowMut<T> for T where
    T: ?Sized, [src]

impl<T> From<T> for T[src]

impl<T, U> Into<U> for T where
    U: From<T>, [src]

impl<T, U> TryFrom<U> for T where
    U: Into<T>, [src]

type Error = Infallible

The type returned in the event of a conversion error.

+

impl<T, U> TryInto<U> for T where
    U: TryFrom<T>, [src]

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.

+
\ No newline at end of file diff --git a/packed_simd/struct.m32.html b/packed_simd/struct.m32.html new file mode 100644 index 000000000..3276f8906 --- /dev/null +++ b/packed_simd/struct.m32.html @@ -0,0 +1,30 @@ +packed_simd::m32 - Rust

[−][src]Struct packed_simd::m32

pub struct m32(_);

32-bit wide mask.

+

Implementations

impl m32[src]

pub fn new(x: bool) -> Self[src]

Instantiate a mask with value

+

pub fn test(&self) -> bool[src]

Test if the mask is set

+

Trait Implementations

impl Clone for m32[src]

impl Copy for m32[src]

impl Debug for m32[src]

impl Default for m32[src]

impl Eq for m32[src]

impl Hash for m32[src]

impl Mask for m32[src]

impl Ord for m32[src]

impl PartialEq<m32> for m32[src]

impl PartialOrd<m32> for m32[src]

Auto Trait Implementations

impl Send for m32

impl Sync for m32

impl Unpin for m32

Blanket Implementations

impl<T> Any for T where
    T: 'static + ?Sized, [src]

impl<T> Borrow<T> for T where
    T: ?Sized, [src]

impl<T> BorrowMut<T> for T where
    T: ?Sized, [src]

impl<T> From<T> for T[src]

impl<T, U> Into<U> for T where
    U: From<T>, [src]

impl<T, U> TryFrom<U> for T where
    U: Into<T>, [src]

type Error = Infallible

The type returned in the event of a conversion error.

+

impl<T, U> TryInto<U> for T where
    U: TryFrom<T>, [src]

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.

+
\ No newline at end of file diff --git a/packed_simd/struct.m64.html b/packed_simd/struct.m64.html new file mode 100644 index 000000000..5c81abf47 --- /dev/null +++ b/packed_simd/struct.m64.html @@ -0,0 +1,30 @@ +packed_simd::m64 - Rust

[−][src]Struct packed_simd::m64

pub struct m64(_);

64-bit wide mask.

+

Implementations

impl m64[src]

pub fn new(x: bool) -> Self[src]

Instantiate a mask with value

+

pub fn test(&self) -> bool[src]

Test if the mask is set

+

Trait Implementations

impl Clone for m64[src]

impl Copy for m64[src]

impl Debug for m64[src]

impl Default for m64[src]

impl Eq for m64[src]

impl Hash for m64[src]

impl Mask for m64[src]

impl Ord for m64[src]

impl PartialEq<m64> for m64[src]

impl PartialOrd<m64> for m64[src]

Auto Trait Implementations

impl Send for m64

impl Sync for m64

impl Unpin for m64

Blanket Implementations

impl<T> Any for T where
    T: 'static + ?Sized, [src]

impl<T> Borrow<T> for T where
    T: ?Sized, [src]

impl<T> BorrowMut<T> for T where
    T: ?Sized, [src]

impl<T> From<T> for T[src]

impl<T, U> Into<U> for T where
    U: From<T>, [src]

impl<T, U> TryFrom<U> for T where
    U: Into<T>, [src]

type Error = Infallible

The type returned in the event of a conversion error.

+

impl<T, U> TryInto<U> for T where
    U: TryFrom<T>, [src]

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.

+
\ No newline at end of file diff --git a/packed_simd/struct.m8.html b/packed_simd/struct.m8.html new file mode 100644 index 000000000..fbf4fd8b4 --- /dev/null +++ b/packed_simd/struct.m8.html @@ -0,0 +1,30 @@ +packed_simd::m8 - Rust

[−][src]Struct packed_simd::m8

pub struct m8(_);

8-bit wide mask.

+

Implementations

impl m8[src]

pub fn new(x: bool) -> Self[src]

Instantiate a mask with value

+

pub fn test(&self) -> bool[src]

Test if the mask is set

+

Trait Implementations

impl Clone for m8[src]

impl Copy for m8[src]

impl Debug for m8[src]

impl Default for m8[src]

impl Eq for m8[src]

impl Hash for m8[src]

impl Mask for m8[src]

impl Ord for m8[src]

impl PartialEq<m8> for m8[src]

impl PartialOrd<m8> for m8[src]

Auto Trait Implementations

impl Send for m8

impl Sync for m8

impl Unpin for m8

Blanket Implementations

impl<T> Any for T where
    T: 'static + ?Sized, [src]

impl<T> Borrow<T> for T where
    T: ?Sized, [src]

impl<T> BorrowMut<T> for T where
    T: ?Sized, [src]

impl<T> From<T> for T[src]

impl<T, U> Into<U> for T where
    U: From<T>, [src]

impl<T, U> TryFrom<U> for T where
    U: Into<T>, [src]

type Error = Infallible

The type returned in the event of a conversion error.

+

impl<T, U> TryInto<U> for T where
    U: TryFrom<T>, [src]

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.

+
\ No newline at end of file diff --git a/packed_simd/struct.msize.html b/packed_simd/struct.msize.html new file mode 100644 index 000000000..4c99b6227 --- /dev/null +++ b/packed_simd/struct.msize.html @@ -0,0 +1,30 @@ +packed_simd::msize - Rust

[−][src]Struct packed_simd::msize

pub struct msize(_);

isize-wide mask.

+

Implementations

impl msize[src]

pub fn new(x: bool) -> Self[src]

Instantiate a mask with value

+

pub fn test(&self) -> bool[src]

Test if the mask is set

+

Trait Implementations

impl Clone for msize[src]

impl Copy for msize[src]

impl Debug for msize[src]

impl Default for msize[src]

impl Eq for msize[src]

impl Hash for msize[src]

impl Mask for msize[src]

impl Ord for msize[src]

impl PartialEq<msize> for msize[src]

impl PartialOrd<msize> for msize[src]

Auto Trait Implementations

impl Send for msize

impl Sync for msize

impl Unpin for msize

Blanket Implementations

impl<T> Any for T where
    T: 'static + ?Sized, [src]

impl<T> Borrow<T> for T where
    T: ?Sized, [src]

impl<T> BorrowMut<T> for T where
    T: ?Sized, [src]

impl<T> From<T> for T[src]

impl<T, U> Into<U> for T where
    U: From<T>, [src]

impl<T, U> TryFrom<U> for T where
    U: Into<T>, [src]

type Error = Infallible

The type returned in the event of a conversion error.

+

impl<T, U> TryInto<U> for T where
    U: TryFrom<T>, [src]

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.

+
\ No newline at end of file diff --git a/packed_simd/trait.Cast.html b/packed_simd/trait.Cast.html new file mode 100644 index 000000000..d83fe4ab9 --- /dev/null +++ b/packed_simd/trait.Cast.html @@ -0,0 +1,44 @@ +packed_simd::Cast - Rust

[−][src]Trait packed_simd::Cast

pub trait Cast<T>: Sized {
+    fn cast(self) -> T;
+}

Numeric cast from Self to T.

+
+

Note: This is a temporary workaround until the conversion traits +specified > in RFC2484 are implemented.

+
+

Numeric cast between vectors with the same number of lanes, such that:

+
    +
  • +

    casting integer vectors whose lane types have the same size (e.g. i32xN +-> u32xN) is a no-op,

    +
    • +
  • +

    casting from a larger integer to a smaller integer (e.g. u32xN -> +u8xN) will truncate,

    +
    • +
  • +

    casting from a smaller integer to a larger integer (e.g. u8xN -> +u32xN) will:

    +
      +
    • zero-extend if the source is unsigned, or
      • +
    • sign-extend if the source is signed,
      • +
    +
    • +
  • +

    casting from a float to an integer will round the float towards zero,

    +
    • +
  • +

    casting from an integer to float will produce the floating point +representation of the integer, rounding to nearest, ties to even,

    +
    • +
  • +

    casting from an f32 to an f64 is perfect and lossless,

    +
    • +
  • +

    casting from an f64 to an f32 rounds to nearest, ties to even.

    +
    • +
+
+

Required methods

fn cast(self) -> T

Numeric cast from self to T.

+
Loading content... +

Implementors

impl<T, U> Cast<U> for T where
    U: FromCast<T>, [src]

FromCast implies Cast.

+
Loading content...
\ No newline at end of file diff --git a/packed_simd/trait.FromBits.html b/packed_simd/trait.FromBits.html new file mode 100644 index 000000000..1c5e67053 --- /dev/null +++ b/packed_simd/trait.FromBits.html @@ -0,0 +1,9 @@ +packed_simd::FromBits - Rust

[−][src]Trait packed_simd::FromBits

pub trait FromBits<T>: Sized {
+    fn from_bits(t: T) -> Self;
+}

Safe lossless bitwise conversion from T to Self.

+
+

Required methods

fn from_bits(t: T) -> Self

Safe lossless bitwise transmute from T to Self.

+
Loading content... +

Implementations on Foreign Types

impl FromBits<Simd<[i8; 8]>> for __m64[src]

impl FromBits<Simd<[u8; 8]>> for __m64[src]

impl FromBits<Simd<[m8; 8]>> for __m64[src]

impl FromBits<Simd<[i16; 4]>> for __m64[src]

impl FromBits<Simd<[u16; 4]>> for __m64[src]

impl FromBits<Simd<[m16; 4]>> for __m64[src]

impl FromBits<Simd<[i32; 2]>> for __m64[src]

impl FromBits<Simd<[u32; 2]>> for __m64[src]

impl FromBits<Simd<[f32; 2]>> for __m64[src]

impl FromBits<Simd<[m32; 2]>> for __m64[src]

impl FromBits<Simd<[i8; 16]>> for __m128[src]

impl FromBits<Simd<[u8; 16]>> for __m128[src]

impl FromBits<Simd<[m8; 16]>> for __m128[src]

impl FromBits<Simd<[i16; 8]>> for __m128[src]

impl FromBits<Simd<[u16; 8]>> for __m128[src]

impl FromBits<Simd<[m16; 8]>> for __m128[src]

impl FromBits<Simd<[i32; 4]>> for __m128[src]

impl FromBits<Simd<[u32; 4]>> for __m128[src]

impl FromBits<Simd<[f32; 4]>> for __m128[src]

impl FromBits<Simd<[m32; 4]>> for __m128[src]

impl FromBits<Simd<[i64; 2]>> for __m128[src]

impl FromBits<Simd<[u64; 2]>> for __m128[src]

impl FromBits<Simd<[f64; 2]>> for __m128[src]

impl FromBits<Simd<[m64; 2]>> for __m128[src]

impl FromBits<Simd<[i128; 1]>> for __m128[src]

impl FromBits<Simd<[u128; 1]>> for __m128[src]

impl FromBits<Simd<[m128; 1]>> for __m128[src]

impl FromBits<Simd<[i8; 16]>> for __m128i[src]

impl FromBits<Simd<[u8; 16]>> for __m128i[src]

impl FromBits<Simd<[m8; 16]>> for __m128i[src]

impl FromBits<Simd<[i16; 8]>> for __m128i[src]

impl FromBits<Simd<[u16; 8]>> for __m128i[src]

impl FromBits<Simd<[m16; 8]>> for __m128i[src]

impl FromBits<Simd<[i32; 4]>> for __m128i[src]

impl FromBits<Simd<[u32; 4]>> for __m128i[src]

impl FromBits<Simd<[f32; 4]>> for __m128i[src]

impl FromBits<Simd<[m32; 4]>> for __m128i[src]

impl FromBits<Simd<[i64; 2]>> for __m128i[src]

impl FromBits<Simd<[u64; 2]>> for __m128i[src]

impl FromBits<Simd<[f64; 2]>> for __m128i[src]

impl FromBits<Simd<[m64; 2]>> for __m128i[src]

impl FromBits<Simd<[i128; 1]>> for __m128i[src]

impl FromBits<Simd<[u128; 1]>> for __m128i[src]

impl FromBits<Simd<[m128; 1]>> for __m128i[src]

impl FromBits<Simd<[i8; 16]>> for __m128d[src]

impl FromBits<Simd<[u8; 16]>> for __m128d[src]

impl FromBits<Simd<[m8; 16]>> for __m128d[src]

impl FromBits<Simd<[i16; 8]>> for __m128d[src]

impl FromBits<Simd<[u16; 8]>> for __m128d[src]

impl FromBits<Simd<[m16; 8]>> for __m128d[src]

impl FromBits<Simd<[i32; 4]>> for __m128d[src]

impl FromBits<Simd<[u32; 4]>> for __m128d[src]

impl FromBits<Simd<[f32; 4]>> for __m128d[src]

impl FromBits<Simd<[m32; 4]>> for __m128d[src]

impl FromBits<Simd<[i64; 2]>> for __m128d[src]

impl FromBits<Simd<[u64; 2]>> for __m128d[src]

impl FromBits<Simd<[f64; 2]>> for __m128d[src]

impl FromBits<Simd<[m64; 2]>> for __m128d[src]

impl FromBits<Simd<[i128; 1]>> for __m128d[src]

impl FromBits<Simd<[u128; 1]>> for __m128d[src]

impl FromBits<Simd<[m128; 1]>> for __m128d[src]

impl FromBits<Simd<[i8; 32]>> for __m256[src]

impl FromBits<Simd<[u8; 32]>> for __m256[src]

impl FromBits<Simd<[m8; 32]>> for __m256[src]

impl FromBits<Simd<[i16; 16]>> for __m256[src]

impl FromBits<Simd<[u16; 16]>> for __m256[src]

impl FromBits<Simd<[m16; 16]>> for __m256[src]

impl FromBits<Simd<[i32; 8]>> for __m256[src]

impl FromBits<Simd<[u32; 8]>> for __m256[src]

impl FromBits<Simd<[f32; 8]>> for __m256[src]

impl FromBits<Simd<[m32; 8]>> for __m256[src]

impl FromBits<Simd<[i64; 4]>> for __m256[src]

impl FromBits<Simd<[u64; 4]>> for __m256[src]

impl FromBits<Simd<[f64; 4]>> for __m256[src]

impl FromBits<Simd<[m64; 4]>> for __m256[src]

impl FromBits<Simd<[i128; 2]>> for __m256[src]

impl FromBits<Simd<[u128; 2]>> for __m256[src]

impl FromBits<Simd<[m128; 2]>> for __m256[src]

impl FromBits<Simd<[i8; 32]>> for __m256i[src]

impl FromBits<Simd<[u8; 32]>> for __m256i[src]

impl FromBits<Simd<[m8; 32]>> for __m256i[src]

impl FromBits<Simd<[i16; 16]>> for __m256i[src]

impl FromBits<Simd<[u16; 16]>> for __m256i[src]

impl FromBits<Simd<[m16; 16]>> for __m256i[src]

impl FromBits<Simd<[i32; 8]>> for __m256i[src]

impl FromBits<Simd<[u32; 8]>> for __m256i[src]

impl FromBits<Simd<[f32; 8]>> for __m256i[src]

impl FromBits<Simd<[m32; 8]>> for __m256i[src]

impl FromBits<Simd<[i64; 4]>> for __m256i[src]

impl FromBits<Simd<[u64; 4]>> for __m256i[src]

impl FromBits<Simd<[f64; 4]>> for __m256i[src]

impl FromBits<Simd<[m64; 4]>> for __m256i[src]

impl FromBits<Simd<[i128; 2]>> for __m256i[src]

impl FromBits<Simd<[u128; 2]>> for __m256i[src]

impl FromBits<Simd<[m128; 2]>> for __m256i[src]

impl FromBits<Simd<[i8; 32]>> for __m256d[src]

impl FromBits<Simd<[u8; 32]>> for __m256d[src]

impl FromBits<Simd<[m8; 32]>> for __m256d[src]

impl FromBits<Simd<[i16; 16]>> for __m256d[src]

impl FromBits<Simd<[u16; 16]>> for __m256d[src]

impl FromBits<Simd<[m16; 16]>> for __m256d[src]

impl FromBits<Simd<[i32; 8]>> for __m256d[src]

impl FromBits<Simd<[u32; 8]>> for __m256d[src]

impl FromBits<Simd<[f32; 8]>> for __m256d[src]

impl FromBits<Simd<[m32; 8]>> for __m256d[src]

impl FromBits<Simd<[i64; 4]>> for __m256d[src]

impl FromBits<Simd<[u64; 4]>> for __m256d[src]

impl FromBits<Simd<[f64; 4]>> for __m256d[src]

impl FromBits<Simd<[m64; 4]>> for __m256d[src]

impl FromBits<Simd<[i128; 2]>> for __m256d[src]

impl FromBits<Simd<[u128; 2]>> for __m256d[src]

impl FromBits<Simd<[m128; 2]>> for __m256d[src]

Loading content... +

Implementors

impl FromBits<Simd<[m128; 1]>> for f32x4[src]

impl FromBits<Simd<[m128; 1]>> for f64x2[src]

impl FromBits<Simd<[m128; 1]>> for i128x1[src]

impl FromBits<Simd<[m128; 1]>> for i16x8[src]

impl FromBits<Simd<[m128; 1]>> for i32x4[src]

impl FromBits<Simd<[m128; 1]>> for i64x2[src]

impl FromBits<Simd<[m128; 1]>> for i8x16[src]

impl FromBits<Simd<[m128; 1]>> for m16x8[src]

impl FromBits<Simd<[m128; 1]>> for m32x4[src]

impl FromBits<Simd<[m128; 1]>> for m64x2[src]

impl FromBits<Simd<[m128; 1]>> for m8x16[src]

impl FromBits<Simd<[m128; 1]>> for u128x1[src]

impl FromBits<Simd<[m128; 1]>> for u16x8[src]

impl FromBits<Simd<[m128; 1]>> for u32x4[src]

impl FromBits<Simd<[m128; 1]>> for u64x2[src]

impl FromBits<Simd<[m128; 1]>> for u8x16[src]

impl FromBits<Simd<[m128; 2]>> for f32x8[src]

impl FromBits<Simd<[m128; 2]>> for f64x4[src]

impl FromBits<Simd<[m128; 2]>> for i128x2[src]

impl FromBits<Simd<[m128; 2]>> for i16x16[src]

impl FromBits<Simd<[m128; 2]>> for i32x8[src]

impl FromBits<Simd<[m128; 2]>> for i64x4[src]

impl FromBits<Simd<[m128; 2]>> for i8x32[src]

impl FromBits<Simd<[m128; 2]>> for m16x16[src]

impl FromBits<Simd<[m128; 2]>> for m32x8[src]

impl FromBits<Simd<[m128; 2]>> for m64x4[src]

impl FromBits<Simd<[m128; 2]>> for m8x32[src]

impl FromBits<Simd<[m128; 2]>> for u128x2[src]

impl FromBits<Simd<[m128; 2]>> for u16x16[src]

impl FromBits<Simd<[m128; 2]>> for u32x8[src]

impl FromBits<Simd<[m128; 2]>> for u64x4[src]

impl FromBits<Simd<[m128; 2]>> for u8x32[src]

impl FromBits<Simd<[m128; 4]>> for f32x16[src]

impl FromBits<Simd<[m128; 4]>> for f64x8[src]

impl FromBits<Simd<[m128; 4]>> for i128x4[src]

impl FromBits<Simd<[m128; 4]>> for i16x32[src]

impl FromBits<Simd<[m128; 4]>> for i32x16[src]

impl FromBits<Simd<[m128; 4]>> for i64x8[src]

impl FromBits<Simd<[m128; 4]>> for i8x64[src]

impl FromBits<Simd<[m128; 4]>> for m16x32[src]

impl FromBits<Simd<[m128; 4]>> for m32x16[src]

impl FromBits<Simd<[m128; 4]>> for m64x8[src]

impl FromBits<Simd<[m128; 4]>> for m8x64[src]

impl FromBits<Simd<[m128; 4]>> for u128x4[src]

impl FromBits<Simd<[m128; 4]>> for u16x32[src]

impl FromBits<Simd<[m128; 4]>> for u32x16[src]

impl FromBits<Simd<[m128; 4]>> for u64x8[src]

impl FromBits<Simd<[m128; 4]>> for u8x64[src]

impl FromBits<Simd<[m16; 16]>> for f32x8[src]

impl FromBits<Simd<[m16; 16]>> for f64x4[src]

impl FromBits<Simd<[m16; 16]>> for i128x2[src]

impl FromBits<Simd<[m16; 16]>> for i16x16[src]

impl FromBits<Simd<[m16; 16]>> for i32x8[src]

impl FromBits<Simd<[m16; 16]>> for i64x4[src]

impl FromBits<Simd<[m16; 16]>> for i8x32[src]

impl FromBits<Simd<[m16; 16]>> for m8x32[src]

impl FromBits<Simd<[m16; 16]>> for u128x2[src]

impl FromBits<Simd<[m16; 16]>> for u16x16[src]

impl FromBits<Simd<[m16; 16]>> for u32x8[src]

impl FromBits<Simd<[m16; 16]>> for u64x4[src]

impl FromBits<Simd<[m16; 16]>> for u8x32[src]

impl FromBits<Simd<[m16; 2]>> for i16x2[src]

impl FromBits<Simd<[m16; 2]>> for i8x4[src]

impl FromBits<Simd<[m16; 2]>> for m8x4[src]

impl FromBits<Simd<[m16; 2]>> for u16x2[src]

impl FromBits<Simd<[m16; 2]>> for u8x4[src]

impl FromBits<Simd<[m16; 32]>> for f32x16[src]

impl FromBits<Simd<[m16; 32]>> for f64x8[src]

impl FromBits<Simd<[m16; 32]>> for i128x4[src]

impl FromBits<Simd<[m16; 32]>> for i16x32[src]

impl FromBits<Simd<[m16; 32]>> for i32x16[src]

impl FromBits<Simd<[m16; 32]>> for i64x8[src]

impl FromBits<Simd<[m16; 32]>> for i8x64[src]

impl FromBits<Simd<[m16; 32]>> for m8x64[src]

impl FromBits<Simd<[m16; 32]>> for u128x4[src]

impl FromBits<Simd<[m16; 32]>> for u16x32[src]

impl FromBits<Simd<[m16; 32]>> for u32x16[src]

impl FromBits<Simd<[m16; 32]>> for u64x8[src]

impl FromBits<Simd<[m16; 32]>> for u8x64[src]

impl FromBits<Simd<[m16; 4]>> for f32x2[src]

impl FromBits<Simd<[m16; 4]>> for i16x4[src]

impl FromBits<Simd<[m16; 4]>> for i32x2[src]

impl FromBits<Simd<[m16; 4]>> for i8x8[src]

impl FromBits<Simd<[m16; 4]>> for m8x8[src]

impl FromBits<Simd<[m16; 4]>> for u16x4[src]

impl FromBits<Simd<[m16; 4]>> for u32x2[src]

impl FromBits<Simd<[m16; 4]>> for u8x8[src]

impl FromBits<Simd<[m16; 8]>> for f32x4[src]

impl FromBits<Simd<[m16; 8]>> for f64x2[src]

impl FromBits<Simd<[m16; 8]>> for i128x1[src]

impl FromBits<Simd<[m16; 8]>> for i16x8[src]

impl FromBits<Simd<[m16; 8]>> for i32x4[src]

impl FromBits<Simd<[m16; 8]>> for i64x2[src]

impl FromBits<Simd<[m16; 8]>> for i8x16[src]

impl FromBits<Simd<[m16; 8]>> for m8x16[src]

impl FromBits<Simd<[m16; 8]>> for u128x1[src]

impl FromBits<Simd<[m16; 8]>> for u16x8[src]

impl FromBits<Simd<[m16; 8]>> for u32x4[src]

impl FromBits<Simd<[m16; 8]>> for u64x2[src]

impl FromBits<Simd<[m16; 8]>> for u8x16[src]

impl FromBits<Simd<[m32; 16]>> for f32x16[src]

impl FromBits<Simd<[m32; 16]>> for f64x8[src]

impl FromBits<Simd<[m32; 16]>> for i128x4[src]

impl FromBits<Simd<[m32; 16]>> for i16x32[src]

impl FromBits<Simd<[m32; 16]>> for i32x16[src]

impl FromBits<Simd<[m32; 16]>> for i64x8[src]

impl FromBits<Simd<[m32; 16]>> for i8x64[src]

impl FromBits<Simd<[m32; 16]>> for m16x32[src]

impl FromBits<Simd<[m32; 16]>> for m8x64[src]

impl FromBits<Simd<[m32; 16]>> for u128x4[src]

impl FromBits<Simd<[m32; 16]>> for u16x32[src]

impl FromBits<Simd<[m32; 16]>> for u32x16[src]

impl FromBits<Simd<[m32; 16]>> for u64x8[src]

impl FromBits<Simd<[m32; 16]>> for u8x64[src]

impl FromBits<Simd<[m32; 2]>> for f32x2[src]

impl FromBits<Simd<[m32; 2]>> for i16x4[src]

impl FromBits<Simd<[m32; 2]>> for i32x2[src]

impl FromBits<Simd<[m32; 2]>> for i8x8[src]

impl FromBits<Simd<[m32; 2]>> for m16x4[src]

impl FromBits<Simd<[m32; 2]>> for m8x8[src]

impl FromBits<Simd<[m32; 2]>> for u16x4[src]

impl FromBits<Simd<[m32; 2]>> for u32x2[src]

impl FromBits<Simd<[m32; 2]>> for u8x8[src]

impl FromBits<Simd<[m32; 4]>> for f32x4[src]

impl FromBits<Simd<[m32; 4]>> for f64x2[src]

impl FromBits<Simd<[m32; 4]>> for i128x1[src]

impl FromBits<Simd<[m32; 4]>> for i16x8[src]

impl FromBits<Simd<[m32; 4]>> for i32x4[src]

impl FromBits<Simd<[m32; 4]>> for i64x2[src]

impl FromBits<Simd<[m32; 4]>> for i8x16[src]

impl FromBits<Simd<[m32; 4]>> for m16x8[src]

impl FromBits<Simd<[m32; 4]>> for m8x16[src]

impl FromBits<Simd<[m32; 4]>> for u128x1[src]

impl FromBits<Simd<[m32; 4]>> for u16x8[src]

impl FromBits<Simd<[m32; 4]>> for u32x4[src]

impl FromBits<Simd<[m32; 4]>> for u64x2[src]

impl FromBits<Simd<[m32; 4]>> for u8x16[src]

impl FromBits<Simd<[m32; 8]>> for f32x8[src]

impl FromBits<Simd<[m32; 8]>> for f64x4[src]

impl FromBits<Simd<[m32; 8]>> for i128x2[src]

impl FromBits<Simd<[m32; 8]>> for i16x16[src]

impl FromBits<Simd<[m32; 8]>> for i32x8[src]

impl FromBits<Simd<[m32; 8]>> for i64x4[src]

impl FromBits<Simd<[m32; 8]>> for i8x32[src]

impl FromBits<Simd<[m32; 8]>> for m16x16[src]

impl FromBits<Simd<[m32; 8]>> for m8x32[src]

impl FromBits<Simd<[m32; 8]>> for u128x2[src]

impl FromBits<Simd<[m32; 8]>> for u16x16[src]

impl FromBits<Simd<[m32; 8]>> for u32x8[src]

impl FromBits<Simd<[m32; 8]>> for u64x4[src]

impl FromBits<Simd<[m32; 8]>> for u8x32[src]

impl FromBits<Simd<[m64; 2]>> for f32x4[src]

impl FromBits<Simd<[m64; 2]>> for f64x2[src]

impl FromBits<Simd<[m64; 2]>> for i128x1[src]

impl FromBits<Simd<[m64; 2]>> for i16x8[src]

impl FromBits<Simd<[m64; 2]>> for i32x4[src]

impl FromBits<Simd<[m64; 2]>> for i64x2[src]

impl FromBits<Simd<[m64; 2]>> for i8x16[src]

impl FromBits<Simd<[m64; 2]>> for m16x8[src]

impl FromBits<Simd<[m64; 2]>> for m32x4[src]

impl FromBits<Simd<[m64; 2]>> for m8x16[src]

impl FromBits<Simd<[m64; 2]>> for u128x1[src]

impl FromBits<Simd<[m64; 2]>> for u16x8[src]

impl FromBits<Simd<[m64; 2]>> for u32x4[src]

impl FromBits<Simd<[m64; 2]>> for u64x2[src]

impl FromBits<Simd<[m64; 2]>> for u8x16[src]

impl FromBits<Simd<[m64; 4]>> for f32x8[src]

impl FromBits<Simd<[m64; 4]>> for f64x4[src]

impl FromBits<Simd<[m64; 4]>> for i128x2[src]

impl FromBits<Simd<[m64; 4]>> for i16x16[src]

impl FromBits<Simd<[m64; 4]>> for i32x8[src]

impl FromBits<Simd<[m64; 4]>> for i64x4[src]

impl FromBits<Simd<[m64; 4]>> for i8x32[src]

impl FromBits<Simd<[m64; 4]>> for m16x16[src]

impl FromBits<Simd<[m64; 4]>> for m32x8[src]

impl FromBits<Simd<[m64; 4]>> for m8x32[src]

impl FromBits<Simd<[m64; 4]>> for u128x2[src]

impl FromBits<Simd<[m64; 4]>> for u16x16[src]

impl FromBits<Simd<[m64; 4]>> for u32x8[src]

impl FromBits<Simd<[m64; 4]>> for u64x4[src]

impl FromBits<Simd<[m64; 4]>> for u8x32[src]

impl FromBits<Simd<[m64; 8]>> for f32x16[src]

impl FromBits<Simd<[m64; 8]>> for f64x8[src]

impl FromBits<Simd<[m64; 8]>> for i128x4[src]

impl FromBits<Simd<[m64; 8]>> for i16x32[src]

impl FromBits<Simd<[m64; 8]>> for i32x16[src]

impl FromBits<Simd<[m64; 8]>> for i64x8[src]

impl FromBits<Simd<[m64; 8]>> for i8x64[src]

impl FromBits<Simd<[m64; 8]>> for m16x32[src]

impl FromBits<Simd<[m64; 8]>> for m32x16[src]

impl FromBits<Simd<[m64; 8]>> for m8x64[src]

impl FromBits<Simd<[m64; 8]>> for u128x4[src]

impl FromBits<Simd<[m64; 8]>> for u16x32[src]

impl FromBits<Simd<[m64; 8]>> for u32x16[src]

impl FromBits<Simd<[m64; 8]>> for u64x8[src]

impl FromBits<Simd<[m64; 8]>> for u8x64[src]

impl FromBits<Simd<[m8; 16]>> for f32x4[src]

impl FromBits<Simd<[m8; 16]>> for f64x2[src]

impl FromBits<Simd<[m8; 16]>> for i128x1[src]

impl FromBits<Simd<[m8; 16]>> for i16x8[src]

impl FromBits<Simd<[m8; 16]>> for i32x4[src]

impl FromBits<Simd<[m8; 16]>> for i64x2[src]

impl FromBits<Simd<[m8; 16]>> for i8x16[src]

impl FromBits<Simd<[m8; 16]>> for u128x1[src]

impl FromBits<Simd<[m8; 16]>> for u16x8[src]

impl FromBits<Simd<[m8; 16]>> for u32x4[src]

impl FromBits<Simd<[m8; 16]>> for u64x2[src]

impl FromBits<Simd<[m8; 16]>> for u8x16[src]

impl FromBits<Simd<[m8; 2]>> for i8x2[src]

impl FromBits<Simd<[m8; 2]>> for u8x2[src]

impl FromBits<Simd<[m8; 32]>> for f32x8[src]

impl FromBits<Simd<[m8; 32]>> for f64x4[src]

impl FromBits<Simd<[m8; 32]>> for i128x2[src]

impl FromBits<Simd<[m8; 32]>> for i16x16[src]

impl FromBits<Simd<[m8; 32]>> for i32x8[src]

impl FromBits<Simd<[m8; 32]>> for i64x4[src]

impl FromBits<Simd<[m8; 32]>> for i8x32[src]

impl FromBits<Simd<[m8; 32]>> for u128x2[src]

impl FromBits<Simd<[m8; 32]>> for u16x16[src]

impl FromBits<Simd<[m8; 32]>> for u32x8[src]

impl FromBits<Simd<[m8; 32]>> for u64x4[src]

impl FromBits<Simd<[m8; 32]>> for u8x32[src]

impl FromBits<Simd<[m8; 4]>> for i16x2[src]

impl FromBits<Simd<[m8; 4]>> for i8x4[src]

impl FromBits<Simd<[m8; 4]>> for u16x2[src]

impl FromBits<Simd<[m8; 4]>> for u8x4[src]

impl FromBits<Simd<[m8; 64]>> for f32x16[src]

impl FromBits<Simd<[m8; 64]>> for f64x8[src]

impl FromBits<Simd<[m8; 64]>> for i128x4[src]

impl FromBits<Simd<[m8; 64]>> for i16x32[src]

impl FromBits<Simd<[m8; 64]>> for i32x16[src]

impl FromBits<Simd<[m8; 64]>> for i64x8[src]

impl FromBits<Simd<[m8; 64]>> for i8x64[src]

impl FromBits<Simd<[m8; 64]>> for u128x4[src]

impl FromBits<Simd<[m8; 64]>> for u16x32[src]

impl FromBits<Simd<[m8; 64]>> for u32x16[src]

impl FromBits<Simd<[m8; 64]>> for u64x8[src]

impl FromBits<Simd<[m8; 64]>> for u8x64[src]

impl FromBits<Simd<[m8; 8]>> for f32x2[src]

impl FromBits<Simd<[m8; 8]>> for i16x4[src]

impl FromBits<Simd<[m8; 8]>> for i32x2[src]

impl FromBits<Simd<[m8; 8]>> for i8x8[src]

impl FromBits<Simd<[m8; 8]>> for u16x4[src]

impl FromBits<Simd<[m8; 8]>> for u32x2[src]

impl FromBits<Simd<[m8; 8]>> for u8x8[src]

impl FromBits<Simd<[f32; 16]>> for f64x8[src]

impl FromBits<Simd<[f32; 16]>> for i128x4[src]

impl FromBits<Simd<[f32; 16]>> for i16x32[src]

impl FromBits<Simd<[f32; 16]>> for i32x16[src]

impl FromBits<Simd<[f32; 16]>> for i64x8[src]

impl FromBits<Simd<[f32; 16]>> for i8x64[src]

impl FromBits<Simd<[f32; 16]>> for u128x4[src]

impl FromBits<Simd<[f32; 16]>> for u16x32[src]

impl FromBits<Simd<[f32; 16]>> for u32x16[src]

impl FromBits<Simd<[f32; 16]>> for u64x8[src]

impl FromBits<Simd<[f32; 16]>> for u8x64[src]

impl FromBits<Simd<[f32; 2]>> for i16x4[src]

impl FromBits<Simd<[f32; 2]>> for i32x2[src]

impl FromBits<Simd<[f32; 2]>> for i8x8[src]

impl FromBits<Simd<[f32; 2]>> for u16x4[src]

impl FromBits<Simd<[f32; 2]>> for u32x2[src]

impl FromBits<Simd<[f32; 2]>> for u8x8[src]

impl FromBits<Simd<[f32; 4]>> for f64x2[src]

impl FromBits<Simd<[f32; 4]>> for i128x1[src]

impl FromBits<Simd<[f32; 4]>> for i16x8[src]

impl FromBits<Simd<[f32; 4]>> for i32x4[src]

impl FromBits<Simd<[f32; 4]>> for i64x2[src]

impl FromBits<Simd<[f32; 4]>> for i8x16[src]

impl FromBits<Simd<[f32; 4]>> for u128x1[src]

impl FromBits<Simd<[f32; 4]>> for u16x8[src]

impl FromBits<Simd<[f32; 4]>> for u32x4[src]

impl FromBits<Simd<[f32; 4]>> for u64x2[src]

impl FromBits<Simd<[f32; 4]>> for u8x16[src]

impl FromBits<Simd<[f32; 8]>> for f64x4[src]

impl FromBits<Simd<[f32; 8]>> for i128x2[src]

impl FromBits<Simd<[f32; 8]>> for i16x16[src]

impl FromBits<Simd<[f32; 8]>> for i32x8[src]

impl FromBits<Simd<[f32; 8]>> for i64x4[src]

impl FromBits<Simd<[f32; 8]>> for i8x32[src]

impl FromBits<Simd<[f32; 8]>> for u128x2[src]

impl FromBits<Simd<[f32; 8]>> for u16x16[src]

impl FromBits<Simd<[f32; 8]>> for u32x8[src]

impl FromBits<Simd<[f32; 8]>> for u64x4[src]

impl FromBits<Simd<[f32; 8]>> for u8x32[src]

impl FromBits<Simd<[f64; 2]>> for f32x4[src]

impl FromBits<Simd<[f64; 2]>> for i128x1[src]

impl FromBits<Simd<[f64; 2]>> for i16x8[src]

impl FromBits<Simd<[f64; 2]>> for i32x4[src]

impl FromBits<Simd<[f64; 2]>> for i64x2[src]

impl FromBits<Simd<[f64; 2]>> for i8x16[src]

impl FromBits<Simd<[f64; 2]>> for u128x1[src]

impl FromBits<Simd<[f64; 2]>> for u16x8[src]

impl FromBits<Simd<[f64; 2]>> for u32x4[src]

impl FromBits<Simd<[f64; 2]>> for u64x2[src]

impl FromBits<Simd<[f64; 2]>> for u8x16[src]

impl FromBits<Simd<[f64; 4]>> for f32x8[src]

impl FromBits<Simd<[f64; 4]>> for i128x2[src]

impl FromBits<Simd<[f64; 4]>> for i16x16[src]

impl FromBits<Simd<[f64; 4]>> for i32x8[src]

impl FromBits<Simd<[f64; 4]>> for i64x4[src]

impl FromBits<Simd<[f64; 4]>> for i8x32[src]

impl FromBits<Simd<[f64; 4]>> for u128x2[src]

impl FromBits<Simd<[f64; 4]>> for u16x16[src]

impl FromBits<Simd<[f64; 4]>> for u32x8[src]

impl FromBits<Simd<[f64; 4]>> for u64x4[src]

impl FromBits<Simd<[f64; 4]>> for u8x32[src]

impl FromBits<Simd<[f64; 8]>> for f32x16[src]

impl FromBits<Simd<[f64; 8]>> for i128x4[src]

impl FromBits<Simd<[f64; 8]>> for i16x32[src]

impl FromBits<Simd<[f64; 8]>> for i32x16[src]

impl FromBits<Simd<[f64; 8]>> for i64x8[src]

impl FromBits<Simd<[f64; 8]>> for i8x64[src]

impl FromBits<Simd<[f64; 8]>> for u128x4[src]

impl FromBits<Simd<[f64; 8]>> for u16x32[src]

impl FromBits<Simd<[f64; 8]>> for u32x16[src]

impl FromBits<Simd<[f64; 8]>> for u64x8[src]

impl FromBits<Simd<[f64; 8]>> for u8x64[src]

impl FromBits<Simd<[i128; 1]>> for f32x4[src]

impl FromBits<Simd<[i128; 1]>> for f64x2[src]

impl FromBits<Simd<[i128; 1]>> for i16x8[src]

impl FromBits<Simd<[i128; 1]>> for i32x4[src]

impl FromBits<Simd<[i128; 1]>> for i64x2[src]

impl FromBits<Simd<[i128; 1]>> for i8x16[src]

impl FromBits<Simd<[i128; 1]>> for u128x1[src]

impl FromBits<Simd<[i128; 1]>> for u16x8[src]

impl FromBits<Simd<[i128; 1]>> for u32x4[src]

impl FromBits<Simd<[i128; 1]>> for u64x2[src]

impl FromBits<Simd<[i128; 1]>> for u8x16[src]

impl FromBits<Simd<[i128; 2]>> for f32x8[src]

impl FromBits<Simd<[i128; 2]>> for f64x4[src]

impl FromBits<Simd<[i128; 2]>> for i16x16[src]

impl FromBits<Simd<[i128; 2]>> for i32x8[src]

impl FromBits<Simd<[i128; 2]>> for i64x4[src]

impl FromBits<Simd<[i128; 2]>> for i8x32[src]

impl FromBits<Simd<[i128; 2]>> for u128x2[src]

impl FromBits<Simd<[i128; 2]>> for u16x16[src]

impl FromBits<Simd<[i128; 2]>> for u32x8[src]

impl FromBits<Simd<[i128; 2]>> for u64x4[src]

impl FromBits<Simd<[i128; 2]>> for u8x32[src]

impl FromBits<Simd<[i128; 4]>> for f32x16[src]

impl FromBits<Simd<[i128; 4]>> for f64x8[src]

impl FromBits<Simd<[i128; 4]>> for i16x32[src]

impl FromBits<Simd<[i128; 4]>> for i32x16[src]

impl FromBits<Simd<[i128; 4]>> for i64x8[src]

impl FromBits<Simd<[i128; 4]>> for i8x64[src]

impl FromBits<Simd<[i128; 4]>> for u128x4[src]

impl FromBits<Simd<[i128; 4]>> for u16x32[src]

impl FromBits<Simd<[i128; 4]>> for u32x16[src]

impl FromBits<Simd<[i128; 4]>> for u64x8[src]

impl FromBits<Simd<[i128; 4]>> for u8x64[src]

impl FromBits<Simd<[i16; 16]>> for f32x8[src]

impl FromBits<Simd<[i16; 16]>> for f64x4[src]

impl FromBits<Simd<[i16; 16]>> for i128x2[src]

impl FromBits<Simd<[i16; 16]>> for i32x8[src]

impl FromBits<Simd<[i16; 16]>> for i64x4[src]

impl FromBits<Simd<[i16; 16]>> for i8x32[src]

impl FromBits<Simd<[i16; 16]>> for u128x2[src]

impl FromBits<Simd<[i16; 16]>> for u16x16[src]

impl FromBits<Simd<[i16; 16]>> for u32x8[src]

impl FromBits<Simd<[i16; 16]>> for u64x4[src]

impl FromBits<Simd<[i16; 16]>> for u8x32[src]

impl FromBits<Simd<[i16; 2]>> for i8x4[src]

impl FromBits<Simd<[i16; 2]>> for u16x2[src]

impl FromBits<Simd<[i16; 2]>> for u8x4[src]

impl FromBits<Simd<[i16; 32]>> for f32x16[src]

impl FromBits<Simd<[i16; 32]>> for f64x8[src]

impl FromBits<Simd<[i16; 32]>> for i128x4[src]

impl FromBits<Simd<[i16; 32]>> for i32x16[src]

impl FromBits<Simd<[i16; 32]>> for i64x8[src]

impl FromBits<Simd<[i16; 32]>> for i8x64[src]

impl FromBits<Simd<[i16; 32]>> for u128x4[src]

impl FromBits<Simd<[i16; 32]>> for u16x32[src]

impl FromBits<Simd<[i16; 32]>> for u32x16[src]

impl FromBits<Simd<[i16; 32]>> for u64x8[src]

impl FromBits<Simd<[i16; 32]>> for u8x64[src]

impl FromBits<Simd<[i16; 4]>> for f32x2[src]

impl FromBits<Simd<[i16; 4]>> for i32x2[src]

impl FromBits<Simd<[i16; 4]>> for i8x8[src]

impl FromBits<Simd<[i16; 4]>> for u16x4[src]

impl FromBits<Simd<[i16; 4]>> for u32x2[src]

impl FromBits<Simd<[i16; 4]>> for u8x8[src]

impl FromBits<Simd<[i16; 8]>> for f32x4[src]

impl FromBits<Simd<[i16; 8]>> for f64x2[src]

impl FromBits<Simd<[i16; 8]>> for i128x1[src]

impl FromBits<Simd<[i16; 8]>> for i32x4[src]

impl FromBits<Simd<[i16; 8]>> for i64x2[src]

impl FromBits<Simd<[i16; 8]>> for i8x16[src]

impl FromBits<Simd<[i16; 8]>> for u128x1[src]

impl FromBits<Simd<[i16; 8]>> for u16x8[src]

impl FromBits<Simd<[i16; 8]>> for u32x4[src]

impl FromBits<Simd<[i16; 8]>> for u64x2[src]

impl FromBits<Simd<[i16; 8]>> for u8x16[src]

impl FromBits<Simd<[i32; 16]>> for f32x16[src]

impl FromBits<Simd<[i32; 16]>> for f64x8[src]

impl FromBits<Simd<[i32; 16]>> for i128x4[src]

impl FromBits<Simd<[i32; 16]>> for i16x32[src]

impl FromBits<Simd<[i32; 16]>> for i64x8[src]

impl FromBits<Simd<[i32; 16]>> for i8x64[src]

impl FromBits<Simd<[i32; 16]>> for u128x4[src]

impl FromBits<Simd<[i32; 16]>> for u16x32[src]

impl FromBits<Simd<[i32; 16]>> for u32x16[src]

impl FromBits<Simd<[i32; 16]>> for u64x8[src]

impl FromBits<Simd<[i32; 16]>> for u8x64[src]

impl FromBits<Simd<[i32; 2]>> for f32x2[src]

impl FromBits<Simd<[i32; 2]>> for i16x4[src]

impl FromBits<Simd<[i32; 2]>> for i8x8[src]

impl FromBits<Simd<[i32; 2]>> for u16x4[src]

impl FromBits<Simd<[i32; 2]>> for u32x2[src]

impl FromBits<Simd<[i32; 2]>> for u8x8[src]

impl FromBits<Simd<[i32; 4]>> for f32x4[src]

impl FromBits<Simd<[i32; 4]>> for f64x2[src]

impl FromBits<Simd<[i32; 4]>> for i128x1[src]

impl FromBits<Simd<[i32; 4]>> for i16x8[src]

impl FromBits<Simd<[i32; 4]>> for i64x2[src]

impl FromBits<Simd<[i32; 4]>> for i8x16[src]

impl FromBits<Simd<[i32; 4]>> for u128x1[src]

impl FromBits<Simd<[i32; 4]>> for u16x8[src]

impl FromBits<Simd<[i32; 4]>> for u32x4[src]

impl FromBits<Simd<[i32; 4]>> for u64x2[src]

impl FromBits<Simd<[i32; 4]>> for u8x16[src]

impl FromBits<Simd<[i32; 8]>> for f32x8[src]

impl FromBits<Simd<[i32; 8]>> for f64x4[src]

impl FromBits<Simd<[i32; 8]>> for i128x2[src]

impl FromBits<Simd<[i32; 8]>> for i16x16[src]

impl FromBits<Simd<[i32; 8]>> for i64x4[src]

impl FromBits<Simd<[i32; 8]>> for i8x32[src]

impl FromBits<Simd<[i32; 8]>> for u128x2[src]

impl FromBits<Simd<[i32; 8]>> for u16x16[src]

impl FromBits<Simd<[i32; 8]>> for u32x8[src]

impl FromBits<Simd<[i32; 8]>> for u64x4[src]

impl FromBits<Simd<[i32; 8]>> for u8x32[src]

impl FromBits<Simd<[i64; 2]>> for f32x4[src]

impl FromBits<Simd<[i64; 2]>> for f64x2[src]

impl FromBits<Simd<[i64; 2]>> for i128x1[src]

impl FromBits<Simd<[i64; 2]>> for i16x8[src]

impl FromBits<Simd<[i64; 2]>> for i32x4[src]

impl FromBits<Simd<[i64; 2]>> for i8x16[src]

impl FromBits<Simd<[i64; 2]>> for u128x1[src]

impl FromBits<Simd<[i64; 2]>> for u16x8[src]

impl FromBits<Simd<[i64; 2]>> for u32x4[src]

impl FromBits<Simd<[i64; 2]>> for u64x2[src]

impl FromBits<Simd<[i64; 2]>> for u8x16[src]

impl FromBits<Simd<[i64; 4]>> for f32x8[src]

impl FromBits<Simd<[i64; 4]>> for f64x4[src]

impl FromBits<Simd<[i64; 4]>> for i128x2[src]

impl FromBits<Simd<[i64; 4]>> for i16x16[src]

impl FromBits<Simd<[i64; 4]>> for i32x8[src]

impl FromBits<Simd<[i64; 4]>> for i8x32[src]

impl FromBits<Simd<[i64; 4]>> for u128x2[src]

impl FromBits<Simd<[i64; 4]>> for u16x16[src]

impl FromBits<Simd<[i64; 4]>> for u32x8[src]

impl FromBits<Simd<[i64; 4]>> for u64x4[src]

impl FromBits<Simd<[i64; 4]>> for u8x32[src]

impl FromBits<Simd<[i64; 8]>> for f32x16[src]

impl FromBits<Simd<[i64; 8]>> for f64x8[src]

impl FromBits<Simd<[i64; 8]>> for i128x4[src]

impl FromBits<Simd<[i64; 8]>> for i16x32[src]

impl FromBits<Simd<[i64; 8]>> for i32x16[src]

impl FromBits<Simd<[i64; 8]>> for i8x64[src]

impl FromBits<Simd<[i64; 8]>> for u128x4[src]

impl FromBits<Simd<[i64; 8]>> for u16x32[src]

impl FromBits<Simd<[i64; 8]>> for u32x16[src]

impl FromBits<Simd<[i64; 8]>> for u64x8[src]

impl FromBits<Simd<[i64; 8]>> for u8x64[src]

impl FromBits<Simd<[i8; 16]>> for f32x4[src]

impl FromBits<Simd<[i8; 16]>> for f64x2[src]

impl FromBits<Simd<[i8; 16]>> for i128x1[src]

impl FromBits<Simd<[i8; 16]>> for i16x8[src]

impl FromBits<Simd<[i8; 16]>> for i32x4[src]

impl FromBits<Simd<[i8; 16]>> for i64x2[src]

impl FromBits<Simd<[i8; 16]>> for u128x1[src]

impl FromBits<Simd<[i8; 16]>> for u16x8[src]

impl FromBits<Simd<[i8; 16]>> for u32x4[src]

impl FromBits<Simd<[i8; 16]>> for u64x2[src]

impl FromBits<Simd<[i8; 16]>> for u8x16[src]

impl FromBits<Simd<[i8; 2]>> for u8x2[src]

impl FromBits<Simd<[i8; 32]>> for f32x8[src]

impl FromBits<Simd<[i8; 32]>> for f64x4[src]

impl FromBits<Simd<[i8; 32]>> for i128x2[src]

impl FromBits<Simd<[i8; 32]>> for i16x16[src]

impl FromBits<Simd<[i8; 32]>> for i32x8[src]

impl FromBits<Simd<[i8; 32]>> for i64x4[src]

impl FromBits<Simd<[i8; 32]>> for u128x2[src]

impl FromBits<Simd<[i8; 32]>> for u16x16[src]

impl FromBits<Simd<[i8; 32]>> for u32x8[src]

impl FromBits<Simd<[i8; 32]>> for u64x4[src]

impl FromBits<Simd<[i8; 32]>> for u8x32[src]

impl FromBits<Simd<[i8; 4]>> for i16x2[src]

impl FromBits<Simd<[i8; 4]>> for u16x2[src]

impl FromBits<Simd<[i8; 4]>> for u8x4[src]

impl FromBits<Simd<[i8; 64]>> for f32x16[src]

impl FromBits<Simd<[i8; 64]>> for f64x8[src]

impl FromBits<Simd<[i8; 64]>> for i128x4[src]

impl FromBits<Simd<[i8; 64]>> for i16x32[src]

impl FromBits<Simd<[i8; 64]>> for i32x16[src]

impl FromBits<Simd<[i8; 64]>> for i64x8[src]

impl FromBits<Simd<[i8; 64]>> for u128x4[src]

impl FromBits<Simd<[i8; 64]>> for u16x32[src]

impl FromBits<Simd<[i8; 64]>> for u32x16[src]

impl FromBits<Simd<[i8; 64]>> for u64x8[src]

impl FromBits<Simd<[i8; 64]>> for u8x64[src]

impl FromBits<Simd<[i8; 8]>> for f32x2[src]

impl FromBits<Simd<[i8; 8]>> for i16x4[src]

impl FromBits<Simd<[i8; 8]>> for i32x2[src]

impl FromBits<Simd<[i8; 8]>> for u16x4[src]

impl FromBits<Simd<[i8; 8]>> for u32x2[src]

impl FromBits<Simd<[i8; 8]>> for u8x8[src]

impl FromBits<Simd<[u128; 1]>> for f32x4[src]

impl FromBits<Simd<[u128; 1]>> for f64x2[src]

impl FromBits<Simd<[u128; 1]>> for i128x1[src]

impl FromBits<Simd<[u128; 1]>> for i16x8[src]

impl FromBits<Simd<[u128; 1]>> for i32x4[src]

impl FromBits<Simd<[u128; 1]>> for i64x2[src]

impl FromBits<Simd<[u128; 1]>> for i8x16[src]

impl FromBits<Simd<[u128; 1]>> for u16x8[src]

impl FromBits<Simd<[u128; 1]>> for u32x4[src]

impl FromBits<Simd<[u128; 1]>> for u64x2[src]

impl FromBits<Simd<[u128; 1]>> for u8x16[src]

impl FromBits<Simd<[u128; 2]>> for f32x8[src]

impl FromBits<Simd<[u128; 2]>> for f64x4[src]

impl FromBits<Simd<[u128; 2]>> for i128x2[src]

impl FromBits<Simd<[u128; 2]>> for i16x16[src]

impl FromBits<Simd<[u128; 2]>> for i32x8[src]

impl FromBits<Simd<[u128; 2]>> for i64x4[src]

impl FromBits<Simd<[u128; 2]>> for i8x32[src]

impl FromBits<Simd<[u128; 2]>> for u16x16[src]

impl FromBits<Simd<[u128; 2]>> for u32x8[src]

impl FromBits<Simd<[u128; 2]>> for u64x4[src]

impl FromBits<Simd<[u128; 2]>> for u8x32[src]

impl FromBits<Simd<[u128; 4]>> for f32x16[src]

impl FromBits<Simd<[u128; 4]>> for f64x8[src]

impl FromBits<Simd<[u128; 4]>> for i128x4[src]

impl FromBits<Simd<[u128; 4]>> for i16x32[src]

impl FromBits<Simd<[u128; 4]>> for i32x16[src]

impl FromBits<Simd<[u128; 4]>> for i64x8[src]

impl FromBits<Simd<[u128; 4]>> for i8x64[src]

impl FromBits<Simd<[u128; 4]>> for u16x32[src]

impl FromBits<Simd<[u128; 4]>> for u32x16[src]

impl FromBits<Simd<[u128; 4]>> for u64x8[src]

impl FromBits<Simd<[u128; 4]>> for u8x64[src]

impl FromBits<Simd<[u16; 16]>> for f32x8[src]

impl FromBits<Simd<[u16; 16]>> for f64x4[src]

impl FromBits<Simd<[u16; 16]>> for i128x2[src]

impl FromBits<Simd<[u16; 16]>> for i16x16[src]

impl FromBits<Simd<[u16; 16]>> for i32x8[src]

impl FromBits<Simd<[u16; 16]>> for i64x4[src]

impl FromBits<Simd<[u16; 16]>> for i8x32[src]

impl FromBits<Simd<[u16; 16]>> for u128x2[src]

impl FromBits<Simd<[u16; 16]>> for u32x8[src]

impl FromBits<Simd<[u16; 16]>> for u64x4[src]

impl FromBits<Simd<[u16; 16]>> for u8x32[src]

impl FromBits<Simd<[u16; 2]>> for i16x2[src]

impl FromBits<Simd<[u16; 2]>> for i8x4[src]

impl FromBits<Simd<[u16; 2]>> for u8x4[src]

impl FromBits<Simd<[u16; 32]>> for f32x16[src]

impl FromBits<Simd<[u16; 32]>> for f64x8[src]

impl FromBits<Simd<[u16; 32]>> for i128x4[src]

impl FromBits<Simd<[u16; 32]>> for i16x32[src]

impl FromBits<Simd<[u16; 32]>> for i32x16[src]

impl FromBits<Simd<[u16; 32]>> for i64x8[src]

impl FromBits<Simd<[u16; 32]>> for i8x64[src]

impl FromBits<Simd<[u16; 32]>> for u128x4[src]

impl FromBits<Simd<[u16; 32]>> for u32x16[src]

impl FromBits<Simd<[u16; 32]>> for u64x8[src]

impl FromBits<Simd<[u16; 32]>> for u8x64[src]

impl FromBits<Simd<[u16; 4]>> for f32x2[src]

impl FromBits<Simd<[u16; 4]>> for i16x4[src]

impl FromBits<Simd<[u16; 4]>> for i32x2[src]

impl FromBits<Simd<[u16; 4]>> for i8x8[src]

impl FromBits<Simd<[u16; 4]>> for u32x2[src]

impl FromBits<Simd<[u16; 4]>> for u8x8[src]

impl FromBits<Simd<[u16; 8]>> for f32x4[src]

impl FromBits<Simd<[u16; 8]>> for f64x2[src]

impl FromBits<Simd<[u16; 8]>> for i128x1[src]

impl FromBits<Simd<[u16; 8]>> for i16x8[src]

impl FromBits<Simd<[u16; 8]>> for i32x4[src]

impl FromBits<Simd<[u16; 8]>> for i64x2[src]

impl FromBits<Simd<[u16; 8]>> for i8x16[src]

impl FromBits<Simd<[u16; 8]>> for u128x1[src]

impl FromBits<Simd<[u16; 8]>> for u32x4[src]

impl FromBits<Simd<[u16; 8]>> for u64x2[src]

impl FromBits<Simd<[u16; 8]>> for u8x16[src]

impl FromBits<Simd<[u32; 16]>> for f32x16[src]

impl FromBits<Simd<[u32; 16]>> for f64x8[src]

impl FromBits<Simd<[u32; 16]>> for i128x4[src]

impl FromBits<Simd<[u32; 16]>> for i16x32[src]

impl FromBits<Simd<[u32; 16]>> for i32x16[src]

impl FromBits<Simd<[u32; 16]>> for i64x8[src]

impl FromBits<Simd<[u32; 16]>> for i8x64[src]

impl FromBits<Simd<[u32; 16]>> for u128x4[src]

impl FromBits<Simd<[u32; 16]>> for u16x32[src]

impl FromBits<Simd<[u32; 16]>> for u64x8[src]

impl FromBits<Simd<[u32; 16]>> for u8x64[src]

impl FromBits<Simd<[u32; 2]>> for f32x2[src]

impl FromBits<Simd<[u32; 2]>> for i16x4[src]

impl FromBits<Simd<[u32; 2]>> for i32x2[src]

impl FromBits<Simd<[u32; 2]>> for i8x8[src]

impl FromBits<Simd<[u32; 2]>> for u16x4[src]

impl FromBits<Simd<[u32; 2]>> for u8x8[src]

impl FromBits<Simd<[u32; 4]>> for f32x4[src]

impl FromBits<Simd<[u32; 4]>> for f64x2[src]

impl FromBits<Simd<[u32; 4]>> for i128x1[src]

impl FromBits<Simd<[u32; 4]>> for i16x8[src]

impl FromBits<Simd<[u32; 4]>> for i32x4[src]

impl FromBits<Simd<[u32; 4]>> for i64x2[src]

impl FromBits<Simd<[u32; 4]>> for i8x16[src]

impl FromBits<Simd<[u32; 4]>> for u128x1[src]

impl FromBits<Simd<[u32; 4]>> for u16x8[src]

impl FromBits<Simd<[u32; 4]>> for u64x2[src]

impl FromBits<Simd<[u32; 4]>> for u8x16[src]

impl FromBits<Simd<[u32; 8]>> for f32x8[src]

impl FromBits<Simd<[u32; 8]>> for f64x4[src]

impl FromBits<Simd<[u32; 8]>> for i128x2[src]

impl FromBits<Simd<[u32; 8]>> for i16x16[src]

impl FromBits<Simd<[u32; 8]>> for i32x8[src]

impl FromBits<Simd<[u32; 8]>> for i64x4[src]

impl FromBits<Simd<[u32; 8]>> for i8x32[src]

impl FromBits<Simd<[u32; 8]>> for u128x2[src]

impl FromBits<Simd<[u32; 8]>> for u16x16[src]

impl FromBits<Simd<[u32; 8]>> for u64x4[src]

impl FromBits<Simd<[u32; 8]>> for u8x32[src]

impl FromBits<Simd<[u64; 2]>> for f32x4[src]

impl FromBits<Simd<[u64; 2]>> for f64x2[src]

impl FromBits<Simd<[u64; 2]>> for i128x1[src]

impl FromBits<Simd<[u64; 2]>> for i16x8[src]

impl FromBits<Simd<[u64; 2]>> for i32x4[src]

impl FromBits<Simd<[u64; 2]>> for i64x2[src]

impl FromBits<Simd<[u64; 2]>> for i8x16[src]

impl FromBits<Simd<[u64; 2]>> for u128x1[src]

impl FromBits<Simd<[u64; 2]>> for u16x8[src]

impl FromBits<Simd<[u64; 2]>> for u32x4[src]

impl FromBits<Simd<[u64; 2]>> for u8x16[src]

impl FromBits<Simd<[u64; 4]>> for f32x8[src]

impl FromBits<Simd<[u64; 4]>> for f64x4[src]

impl FromBits<Simd<[u64; 4]>> for i128x2[src]

impl FromBits<Simd<[u64; 4]>> for i16x16[src]

impl FromBits<Simd<[u64; 4]>> for i32x8[src]

impl FromBits<Simd<[u64; 4]>> for i64x4[src]

impl FromBits<Simd<[u64; 4]>> for i8x32[src]

impl FromBits<Simd<[u64; 4]>> for u128x2[src]

impl FromBits<Simd<[u64; 4]>> for u16x16[src]

impl FromBits<Simd<[u64; 4]>> for u32x8[src]

impl FromBits<Simd<[u64; 4]>> for u8x32[src]

impl FromBits<Simd<[u64; 8]>> for f32x16[src]

impl FromBits<Simd<[u64; 8]>> for f64x8[src]

impl FromBits<Simd<[u64; 8]>> for i128x4[src]

impl FromBits<Simd<[u64; 8]>> for i16x32[src]

impl FromBits<Simd<[u64; 8]>> for i32x16[src]

impl FromBits<Simd<[u64; 8]>> for i64x8[src]

impl FromBits<Simd<[u64; 8]>> for i8x64[src]

impl FromBits<Simd<[u64; 8]>> for u128x4[src]

impl FromBits<Simd<[u64; 8]>> for u16x32[src]

impl FromBits<Simd<[u64; 8]>> for u32x16[src]

impl FromBits<Simd<[u64; 8]>> for u8x64[src]

impl FromBits<Simd<[u8; 16]>> for f32x4[src]

impl FromBits<Simd<[u8; 16]>> for f64x2[src]

impl FromBits<Simd<[u8; 16]>> for i128x1[src]

impl FromBits<Simd<[u8; 16]>> for i16x8[src]

impl FromBits<Simd<[u8; 16]>> for i32x4[src]

impl FromBits<Simd<[u8; 16]>> for i64x2[src]

impl FromBits<Simd<[u8; 16]>> for i8x16[src]

impl FromBits<Simd<[u8; 16]>> for u128x1[src]

impl FromBits<Simd<[u8; 16]>> for u16x8[src]

impl FromBits<Simd<[u8; 16]>> for u32x4[src]

impl FromBits<Simd<[u8; 16]>> for u64x2[src]

impl FromBits<Simd<[u8; 2]>> for i8x2[src]

impl FromBits<Simd<[u8; 32]>> for f32x8[src]

impl FromBits<Simd<[u8; 32]>> for f64x4[src]

impl FromBits<Simd<[u8; 32]>> for i128x2[src]

impl FromBits<Simd<[u8; 32]>> for i16x16[src]

impl FromBits<Simd<[u8; 32]>> for i32x8[src]

impl FromBits<Simd<[u8; 32]>> for i64x4[src]

impl FromBits<Simd<[u8; 32]>> for i8x32[src]

impl FromBits<Simd<[u8; 32]>> for u128x2[src]

impl FromBits<Simd<[u8; 32]>> for u16x16[src]

impl FromBits<Simd<[u8; 32]>> for u32x8[src]

impl FromBits<Simd<[u8; 32]>> for u64x4[src]

impl FromBits<Simd<[u8; 4]>> for i16x2[src]

impl FromBits<Simd<[u8; 4]>> for i8x4[src]

impl FromBits<Simd<[u8; 4]>> for u16x2[src]

impl FromBits<Simd<[u8; 64]>> for f32x16[src]

impl FromBits<Simd<[u8; 64]>> for f64x8[src]

impl FromBits<Simd<[u8; 64]>> for i128x4[src]

impl FromBits<Simd<[u8; 64]>> for i16x32[src]

impl FromBits<Simd<[u8; 64]>> for i32x16[src]

impl FromBits<Simd<[u8; 64]>> for i64x8[src]

impl FromBits<Simd<[u8; 64]>> for i8x64[src]

impl FromBits<Simd<[u8; 64]>> for u128x4[src]

impl FromBits<Simd<[u8; 64]>> for u16x32[src]

impl FromBits<Simd<[u8; 64]>> for u32x16[src]

impl FromBits<Simd<[u8; 64]>> for u64x8[src]

impl FromBits<Simd<[u8; 8]>> for f32x2[src]

impl FromBits<Simd<[u8; 8]>> for i16x4[src]

impl FromBits<Simd<[u8; 8]>> for i32x2[src]

impl FromBits<Simd<[u8; 8]>> for i8x8[src]

impl FromBits<Simd<[u8; 8]>> for u16x4[src]

impl FromBits<Simd<[u8; 8]>> for u32x2[src]

impl FromBits<__m128> for f32x4[src]

impl FromBits<__m128> for f64x2[src]

impl FromBits<__m128> for i128x1[src]

impl FromBits<__m128> for i16x8[src]

impl FromBits<__m128> for i32x4[src]

impl FromBits<__m128> for i64x2[src]

impl FromBits<__m128> for i8x16[src]

impl FromBits<__m128> for u128x1[src]

impl FromBits<__m128> for u16x8[src]

impl FromBits<__m128> for u32x4[src]

impl FromBits<__m128> for u64x2[src]

impl FromBits<__m128> for u8x16[src]

impl FromBits<__m128d> for f32x4[src]

impl FromBits<__m128d> for f64x2[src]

impl FromBits<__m128d> for i128x1[src]

impl FromBits<__m128d> for i16x8[src]

impl FromBits<__m128d> for i32x4[src]

impl FromBits<__m128d> for i64x2[src]

impl FromBits<__m128d> for i8x16[src]

impl FromBits<__m128d> for u128x1[src]

impl FromBits<__m128d> for u16x8[src]

impl FromBits<__m128d> for u32x4[src]

impl FromBits<__m128d> for u64x2[src]

impl FromBits<__m128d> for u8x16[src]

impl FromBits<__m128i> for f32x4[src]

impl FromBits<__m128i> for f64x2[src]

impl FromBits<__m128i> for i128x1[src]

impl FromBits<__m128i> for i16x8[src]

impl FromBits<__m128i> for i32x4[src]

impl FromBits<__m128i> for i64x2[src]

impl FromBits<__m128i> for i8x16[src]

impl FromBits<__m128i> for u128x1[src]

impl FromBits<__m128i> for u16x8[src]

impl FromBits<__m128i> for u32x4[src]

impl FromBits<__m128i> for u64x2[src]

impl FromBits<__m128i> for u8x16[src]

impl FromBits<__m256> for f32x8[src]

impl FromBits<__m256> for f64x4[src]

impl FromBits<__m256> for i128x2[src]

impl FromBits<__m256> for i16x16[src]

impl FromBits<__m256> for i32x8[src]

impl FromBits<__m256> for i64x4[src]

impl FromBits<__m256> for i8x32[src]

impl FromBits<__m256> for u128x2[src]

impl FromBits<__m256> for u16x16[src]

impl FromBits<__m256> for u32x8[src]

impl FromBits<__m256> for u64x4[src]

impl FromBits<__m256> for u8x32[src]

impl FromBits<__m256d> for f32x8[src]

impl FromBits<__m256d> for f64x4[src]

impl FromBits<__m256d> for i128x2[src]

impl FromBits<__m256d> for i16x16[src]

impl FromBits<__m256d> for i32x8[src]

impl FromBits<__m256d> for i64x4[src]

impl FromBits<__m256d> for i8x32[src]

impl FromBits<__m256d> for u128x2[src]

impl FromBits<__m256d> for u16x16[src]

impl FromBits<__m256d> for u32x8[src]

impl FromBits<__m256d> for u64x4[src]

impl FromBits<__m256d> for u8x32[src]

impl FromBits<__m256i> for f32x8[src]

impl FromBits<__m256i> for f64x4[src]

impl FromBits<__m256i> for i128x2[src]

impl FromBits<__m256i> for i16x16[src]

impl FromBits<__m256i> for i32x8[src]

impl FromBits<__m256i> for i64x4[src]

impl FromBits<__m256i> for i8x32[src]

impl FromBits<__m256i> for u128x2[src]

impl FromBits<__m256i> for u16x16[src]

impl FromBits<__m256i> for u32x8[src]

impl FromBits<__m256i> for u64x4[src]

impl FromBits<__m256i> for u8x32[src]

impl FromBits<__m64> for f32x2[src]

impl FromBits<__m64> for i16x4[src]

impl FromBits<__m64> for i32x2[src]

impl FromBits<__m64> for i8x8[src]

impl FromBits<__m64> for u16x4[src]

impl FromBits<__m64> for u32x2[src]

impl FromBits<__m64> for u8x8[src]

impl<T> FromBits<T> for T[src]

FromBits and IntoBits are reflexive

+
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\ No newline at end of file diff --git a/packed_simd/trait.FromCast.html b/packed_simd/trait.FromCast.html new file mode 100644 index 000000000..3aef9394a --- /dev/null +++ b/packed_simd/trait.FromCast.html @@ -0,0 +1,44 @@ +packed_simd::FromCast - Rust

[−][src]Trait packed_simd::FromCast

pub trait FromCast<T>: Sized {
+    fn from_cast(_: T) -> Self;
+}

Numeric cast from T to Self.

+
+

Note: This is a temporary workaround until the conversion traits +specified > in RFC2484 are implemented.

+
+

Numeric cast between vectors with the same number of lanes, such that:

+
    +
  • +

    casting integer vectors whose lane types have the same size (e.g. i32xN +-> u32xN) is a no-op,

    +
    • +
  • +

    casting from a larger integer to a smaller integer (e.g. u32xN -> +u8xN) will truncate,

    +
    • +
  • +

    casting from a smaller integer to a larger integer (e.g. u8xN -> +u32xN) will:

    +
      +
    • zero-extend if the source is unsigned, or
      • +
    • sign-extend if the source is signed,
      • +
    +
    • +
  • +

    casting from a float to an integer will round the float towards zero,

    +
    • +
  • +

    casting from an integer to float will produce the floating point +representation of the integer, rounding to nearest, ties to even,

    +
    • +
  • +

    casting from an f32 to an f64 is perfect and lossless,

    +
    • +
  • +

    casting from an f64 to an f32 rounds to nearest, ties to even.

    +
    • +
+
+

Required methods

fn from_cast(_: T) -> Self

Numeric cast from T to Self.

+
Loading content... +

Implementors

impl FromCast<Simd<[m128; 1]>> for i128x1[src]

impl FromCast<Simd<[m128; 1]>> for u128x1[src]

impl FromCast<Simd<[m128; 2]>> for f32x2[src]

impl FromCast<Simd<[m128; 2]>> for f64x2[src]

impl FromCast<Simd<[m128; 2]>> for i128x2[src]

impl FromCast<Simd<[m128; 2]>> for i16x2[src]

impl FromCast<Simd<[m128; 2]>> for i32x2[src]

impl FromCast<Simd<[m128; 2]>> for i64x2[src]

impl FromCast<Simd<[m128; 2]>> for i8x2[src]

impl FromCast<Simd<[m128; 2]>> for isizex2[src]

impl FromCast<Simd<[m128; 2]>> for m16x2[src]

impl FromCast<Simd<[m128; 2]>> for m32x2[src]

impl FromCast<Simd<[m128; 2]>> for m64x2[src]

impl FromCast<Simd<[m128; 2]>> for m8x2[src]

impl FromCast<Simd<[m128; 2]>> for msizex2[src]

impl FromCast<Simd<[m128; 2]>> for u128x2[src]

impl FromCast<Simd<[m128; 2]>> for u16x2[src]

impl FromCast<Simd<[m128; 2]>> for u32x2[src]

impl FromCast<Simd<[m128; 2]>> for u64x2[src]

impl FromCast<Simd<[m128; 2]>> for u8x2[src]

impl FromCast<Simd<[m128; 2]>> for usizex2[src]

impl FromCast<Simd<[m128; 4]>> for f32x4[src]

impl FromCast<Simd<[m128; 4]>> for f64x4[src]

impl FromCast<Simd<[m128; 4]>> for i128x4[src]

impl FromCast<Simd<[m128; 4]>> for i16x4[src]

impl FromCast<Simd<[m128; 4]>> for i32x4[src]

impl FromCast<Simd<[m128; 4]>> for i64x4[src]

impl FromCast<Simd<[m128; 4]>> for i8x4[src]

impl FromCast<Simd<[m128; 4]>> for isizex4[src]

impl FromCast<Simd<[m128; 4]>> for m16x4[src]

impl FromCast<Simd<[m128; 4]>> for m32x4[src]

impl FromCast<Simd<[m128; 4]>> for m64x4[src]

impl FromCast<Simd<[m128; 4]>> for m8x4[src]

impl FromCast<Simd<[m128; 4]>> for msizex4[src]

impl FromCast<Simd<[m128; 4]>> for u128x4[src]

impl FromCast<Simd<[m128; 4]>> for u16x4[src]

impl FromCast<Simd<[m128; 4]>> for u32x4[src]

impl FromCast<Simd<[m128; 4]>> for u64x4[src]

impl FromCast<Simd<[m128; 4]>> for u8x4[src]

impl FromCast<Simd<[m128; 4]>> for usizex4[src]

impl FromCast<Simd<[m16; 16]>> for f32x16[src]

impl FromCast<Simd<[m16; 16]>> for i16x16[src]

impl FromCast<Simd<[m16; 16]>> for i32x16[src]

impl FromCast<Simd<[m16; 16]>> for i8x16[src]

impl FromCast<Simd<[m16; 16]>> for m32x16[src]

impl FromCast<Simd<[m16; 16]>> for m8x16[src]

impl FromCast<Simd<[m16; 16]>> for u16x16[src]

impl FromCast<Simd<[m16; 16]>> for u32x16[src]

impl FromCast<Simd<[m16; 16]>> for u8x16[src]

impl FromCast<Simd<[m16; 2]>> for f32x2[src]

impl FromCast<Simd<[m16; 2]>> for f64x2[src]

impl FromCast<Simd<[m16; 2]>> for i128x2[src]

impl FromCast<Simd<[m16; 2]>> for i16x2[src]

impl FromCast<Simd<[m16; 2]>> for i32x2[src]

impl FromCast<Simd<[m16; 2]>> for i64x2[src]

impl FromCast<Simd<[m16; 2]>> for i8x2[src]

impl FromCast<Simd<[m16; 2]>> for isizex2[src]

impl FromCast<Simd<[m16; 2]>> for m128x2[src]

impl FromCast<Simd<[m16; 2]>> for m32x2[src]

impl FromCast<Simd<[m16; 2]>> for m64x2[src]

impl FromCast<Simd<[m16; 2]>> for m8x2[src]

impl FromCast<Simd<[m16; 2]>> for msizex2[src]

impl FromCast<Simd<[m16; 2]>> for u128x2[src]

impl FromCast<Simd<[m16; 2]>> for u16x2[src]

impl FromCast<Simd<[m16; 2]>> for u32x2[src]

impl FromCast<Simd<[m16; 2]>> for u64x2[src]

impl FromCast<Simd<[m16; 2]>> for u8x2[src]

impl FromCast<Simd<[m16; 2]>> for usizex2[src]

impl FromCast<Simd<[m16; 32]>> for i16x32[src]

impl FromCast<Simd<[m16; 32]>> for i8x32[src]

impl FromCast<Simd<[m16; 32]>> for m8x32[src]

impl FromCast<Simd<[m16; 32]>> for u16x32[src]

impl FromCast<Simd<[m16; 32]>> for u8x32[src]

impl FromCast<Simd<[m16; 4]>> for f32x4[src]

impl FromCast<Simd<[m16; 4]>> for f64x4[src]

impl FromCast<Simd<[m16; 4]>> for i128x4[src]

impl FromCast<Simd<[m16; 4]>> for i16x4[src]

impl FromCast<Simd<[m16; 4]>> for i32x4[src]

impl FromCast<Simd<[m16; 4]>> for i64x4[src]

impl FromCast<Simd<[m16; 4]>> for i8x4[src]

impl FromCast<Simd<[m16; 4]>> for isizex4[src]

impl FromCast<Simd<[m16; 4]>> for m128x4[src]

impl FromCast<Simd<[m16; 4]>> for m32x4[src]

impl FromCast<Simd<[m16; 4]>> for m64x4[src]

impl FromCast<Simd<[m16; 4]>> for m8x4[src]

impl FromCast<Simd<[m16; 4]>> for msizex4[src]

impl FromCast<Simd<[m16; 4]>> for u128x4[src]

impl FromCast<Simd<[m16; 4]>> for u16x4[src]

impl FromCast<Simd<[m16; 4]>> for u32x4[src]

impl FromCast<Simd<[m16; 4]>> for u64x4[src]

impl FromCast<Simd<[m16; 4]>> for u8x4[src]

impl FromCast<Simd<[m16; 4]>> for usizex4[src]

impl FromCast<Simd<[m16; 8]>> for f32x8[src]

impl FromCast<Simd<[m16; 8]>> for f64x8[src]

impl FromCast<Simd<[m16; 8]>> for i16x8[src]

impl FromCast<Simd<[m16; 8]>> for i32x8[src]

impl FromCast<Simd<[m16; 8]>> for i64x8[src]

impl FromCast<Simd<[m16; 8]>> for i8x8[src]

impl FromCast<Simd<[m16; 8]>> for isizex8[src]

impl FromCast<Simd<[m16; 8]>> for m32x8[src]

impl FromCast<Simd<[m16; 8]>> for m64x8[src]

impl FromCast<Simd<[m16; 8]>> for m8x8[src]

impl FromCast<Simd<[m16; 8]>> for msizex8[src]

impl FromCast<Simd<[m16; 8]>> for u16x8[src]

impl FromCast<Simd<[m16; 8]>> for u32x8[src]

impl FromCast<Simd<[m16; 8]>> for u64x8[src]

impl FromCast<Simd<[m16; 8]>> for u8x8[src]

impl FromCast<Simd<[m16; 8]>> for usizex8[src]

impl FromCast<Simd<[m32; 16]>> for f32x16[src]

impl FromCast<Simd<[m32; 16]>> for i16x16[src]

impl FromCast<Simd<[m32; 16]>> for i32x16[src]

impl FromCast<Simd<[m32; 16]>> for i8x16[src]

impl FromCast<Simd<[m32; 16]>> for m16x16[src]

impl FromCast<Simd<[m32; 16]>> for m8x16[src]

impl FromCast<Simd<[m32; 16]>> for u16x16[src]

impl FromCast<Simd<[m32; 16]>> for u32x16[src]

impl FromCast<Simd<[m32; 16]>> for u8x16[src]

impl FromCast<Simd<[m32; 2]>> for f32x2[src]

impl FromCast<Simd<[m32; 2]>> for f64x2[src]

impl FromCast<Simd<[m32; 2]>> for i128x2[src]

impl FromCast<Simd<[m32; 2]>> for i16x2[src]

impl FromCast<Simd<[m32; 2]>> for i32x2[src]

impl FromCast<Simd<[m32; 2]>> for i64x2[src]

impl FromCast<Simd<[m32; 2]>> for i8x2[src]

impl FromCast<Simd<[m32; 2]>> for isizex2[src]

impl FromCast<Simd<[m32; 2]>> for m128x2[src]

impl FromCast<Simd<[m32; 2]>> for m16x2[src]

impl FromCast<Simd<[m32; 2]>> for m64x2[src]

impl FromCast<Simd<[m32; 2]>> for m8x2[src]

impl FromCast<Simd<[m32; 2]>> for msizex2[src]

impl FromCast<Simd<[m32; 2]>> for u128x2[src]

impl FromCast<Simd<[m32; 2]>> for u16x2[src]

impl FromCast<Simd<[m32; 2]>> for u32x2[src]

impl FromCast<Simd<[m32; 2]>> for u64x2[src]

impl FromCast<Simd<[m32; 2]>> for u8x2[src]

impl FromCast<Simd<[m32; 2]>> for usizex2[src]

impl FromCast<Simd<[m32; 4]>> for f32x4[src]

impl FromCast<Simd<[m32; 4]>> for f64x4[src]

impl FromCast<Simd<[m32; 4]>> for i128x4[src]

impl FromCast<Simd<[m32; 4]>> for i16x4[src]

impl FromCast<Simd<[m32; 4]>> for i32x4[src]

impl FromCast<Simd<[m32; 4]>> for i64x4[src]

impl FromCast<Simd<[m32; 4]>> for i8x4[src]

impl FromCast<Simd<[m32; 4]>> for isizex4[src]

impl FromCast<Simd<[m32; 4]>> for m128x4[src]

impl FromCast<Simd<[m32; 4]>> for m16x4[src]

impl FromCast<Simd<[m32; 4]>> for m64x4[src]

impl FromCast<Simd<[m32; 4]>> for m8x4[src]

impl FromCast<Simd<[m32; 4]>> for msizex4[src]

impl FromCast<Simd<[m32; 4]>> for u128x4[src]

impl FromCast<Simd<[m32; 4]>> for u16x4[src]

impl FromCast<Simd<[m32; 4]>> for u32x4[src]

impl FromCast<Simd<[m32; 4]>> for u64x4[src]

impl FromCast<Simd<[m32; 4]>> for u8x4[src]

impl FromCast<Simd<[m32; 4]>> for usizex4[src]

impl FromCast<Simd<[m32; 8]>> for f32x8[src]

impl FromCast<Simd<[m32; 8]>> for f64x8[src]

impl FromCast<Simd<[m32; 8]>> for i16x8[src]

impl FromCast<Simd<[m32; 8]>> for i32x8[src]

impl FromCast<Simd<[m32; 8]>> for i64x8[src]

impl FromCast<Simd<[m32; 8]>> for i8x8[src]

impl FromCast<Simd<[m32; 8]>> for isizex8[src]

impl FromCast<Simd<[m32; 8]>> for m16x8[src]

impl FromCast<Simd<[m32; 8]>> for m64x8[src]

impl FromCast<Simd<[m32; 8]>> for m8x8[src]

impl FromCast<Simd<[m32; 8]>> for msizex8[src]

impl FromCast<Simd<[m32; 8]>> for u16x8[src]

impl FromCast<Simd<[m32; 8]>> for u32x8[src]

impl FromCast<Simd<[m32; 8]>> for u64x8[src]

impl FromCast<Simd<[m32; 8]>> for u8x8[src]

impl FromCast<Simd<[m32; 8]>> for usizex8[src]

impl FromCast<Simd<[m64; 2]>> for f32x2[src]

impl FromCast<Simd<[m64; 2]>> for f64x2[src]

impl FromCast<Simd<[m64; 2]>> for i128x2[src]

impl FromCast<Simd<[m64; 2]>> for i16x2[src]

impl FromCast<Simd<[m64; 2]>> for i32x2[src]

impl FromCast<Simd<[m64; 2]>> for i64x2[src]

impl FromCast<Simd<[m64; 2]>> for i8x2[src]

impl FromCast<Simd<[m64; 2]>> for isizex2[src]

impl FromCast<Simd<[m64; 2]>> for m128x2[src]

impl FromCast<Simd<[m64; 2]>> for m16x2[src]

impl FromCast<Simd<[m64; 2]>> for m32x2[src]

impl FromCast<Simd<[m64; 2]>> for m8x2[src]

impl FromCast<Simd<[m64; 2]>> for msizex2[src]

impl FromCast<Simd<[m64; 2]>> for u128x2[src]

impl FromCast<Simd<[m64; 2]>> for u16x2[src]

impl FromCast<Simd<[m64; 2]>> for u32x2[src]

impl FromCast<Simd<[m64; 2]>> for u64x2[src]

impl FromCast<Simd<[m64; 2]>> for u8x2[src]

impl FromCast<Simd<[m64; 2]>> for usizex2[src]

impl FromCast<Simd<[m64; 4]>> for f32x4[src]

impl FromCast<Simd<[m64; 4]>> for f64x4[src]

impl FromCast<Simd<[m64; 4]>> for i128x4[src]

impl FromCast<Simd<[m64; 4]>> for i16x4[src]

impl FromCast<Simd<[m64; 4]>> for i32x4[src]

impl FromCast<Simd<[m64; 4]>> for i64x4[src]

impl FromCast<Simd<[m64; 4]>> for i8x4[src]

impl FromCast<Simd<[m64; 4]>> for isizex4[src]

impl FromCast<Simd<[m64; 4]>> for m128x4[src]

impl FromCast<Simd<[m64; 4]>> for m16x4[src]

impl FromCast<Simd<[m64; 4]>> for m32x4[src]

impl FromCast<Simd<[m64; 4]>> for m8x4[src]

impl FromCast<Simd<[m64; 4]>> for msizex4[src]

impl FromCast<Simd<[m64; 4]>> for u128x4[src]

impl FromCast<Simd<[m64; 4]>> for u16x4[src]

impl FromCast<Simd<[m64; 4]>> for u32x4[src]

impl FromCast<Simd<[m64; 4]>> for u64x4[src]

impl FromCast<Simd<[m64; 4]>> for u8x4[src]

impl FromCast<Simd<[m64; 4]>> for usizex4[src]

impl FromCast<Simd<[m64; 8]>> for f32x8[src]

impl FromCast<Simd<[m64; 8]>> for f64x8[src]

impl FromCast<Simd<[m64; 8]>> for i16x8[src]

impl FromCast<Simd<[m64; 8]>> for i32x8[src]

impl FromCast<Simd<[m64; 8]>> for i64x8[src]

impl FromCast<Simd<[m64; 8]>> for i8x8[src]

impl FromCast<Simd<[m64; 8]>> for isizex8[src]

impl FromCast<Simd<[m64; 8]>> for m16x8[src]

impl FromCast<Simd<[m64; 8]>> for m32x8[src]

impl FromCast<Simd<[m64; 8]>> for m8x8[src]

impl FromCast<Simd<[m64; 8]>> for msizex8[src]

impl FromCast<Simd<[m64; 8]>> for u16x8[src]

impl FromCast<Simd<[m64; 8]>> for u32x8[src]

impl FromCast<Simd<[m64; 8]>> for u64x8[src]

impl FromCast<Simd<[m64; 8]>> for u8x8[src]

impl FromCast<Simd<[m64; 8]>> for usizex8[src]

impl FromCast<Simd<[m8; 16]>> for f32x16[src]

impl FromCast<Simd<[m8; 16]>> for i16x16[src]

impl FromCast<Simd<[m8; 16]>> for i32x16[src]

impl FromCast<Simd<[m8; 16]>> for i8x16[src]

impl FromCast<Simd<[m8; 16]>> for m16x16[src]

impl FromCast<Simd<[m8; 16]>> for m32x16[src]

impl FromCast<Simd<[m8; 16]>> for u16x16[src]

impl FromCast<Simd<[m8; 16]>> for u32x16[src]

impl FromCast<Simd<[m8; 16]>> for u8x16[src]

impl FromCast<Simd<[m8; 2]>> for f32x2[src]

impl FromCast<Simd<[m8; 2]>> for f64x2[src]

impl FromCast<Simd<[m8; 2]>> for i128x2[src]

impl FromCast<Simd<[m8; 2]>> for i16x2[src]

impl FromCast<Simd<[m8; 2]>> for i32x2[src]

impl FromCast<Simd<[m8; 2]>> for i64x2[src]

impl FromCast<Simd<[m8; 2]>> for i8x2[src]

impl FromCast<Simd<[m8; 2]>> for isizex2[src]

impl FromCast<Simd<[m8; 2]>> for m128x2[src]

impl FromCast<Simd<[m8; 2]>> for m16x2[src]

impl FromCast<Simd<[m8; 2]>> for m32x2[src]

impl FromCast<Simd<[m8; 2]>> for m64x2[src]

impl FromCast<Simd<[m8; 2]>> for msizex2[src]

impl FromCast<Simd<[m8; 2]>> for u128x2[src]

impl FromCast<Simd<[m8; 2]>> for u16x2[src]

impl FromCast<Simd<[m8; 2]>> for u32x2[src]

impl FromCast<Simd<[m8; 2]>> for u64x2[src]

impl FromCast<Simd<[m8; 2]>> for u8x2[src]

impl FromCast<Simd<[m8; 2]>> for usizex2[src]

impl FromCast<Simd<[m8; 32]>> for i16x32[src]

impl FromCast<Simd<[m8; 32]>> for i8x32[src]

impl FromCast<Simd<[m8; 32]>> for m16x32[src]

impl FromCast<Simd<[m8; 32]>> for u16x32[src]

impl FromCast<Simd<[m8; 32]>> for u8x32[src]

impl FromCast<Simd<[m8; 4]>> for f32x4[src]

impl FromCast<Simd<[m8; 4]>> for f64x4[src]

impl FromCast<Simd<[m8; 4]>> for i128x4[src]

impl FromCast<Simd<[m8; 4]>> for i16x4[src]

impl FromCast<Simd<[m8; 4]>> for i32x4[src]

impl FromCast<Simd<[m8; 4]>> for i64x4[src]

impl FromCast<Simd<[m8; 4]>> for i8x4[src]

impl FromCast<Simd<[m8; 4]>> for isizex4[src]

impl FromCast<Simd<[m8; 4]>> for m128x4[src]

impl FromCast<Simd<[m8; 4]>> for m16x4[src]

impl FromCast<Simd<[m8; 4]>> for m32x4[src]

impl FromCast<Simd<[m8; 4]>> for m64x4[src]

impl FromCast<Simd<[m8; 4]>> for msizex4[src]

impl FromCast<Simd<[m8; 4]>> for u128x4[src]

impl FromCast<Simd<[m8; 4]>> for u16x4[src]

impl FromCast<Simd<[m8; 4]>> for u32x4[src]

impl FromCast<Simd<[m8; 4]>> for u64x4[src]

impl FromCast<Simd<[m8; 4]>> for u8x4[src]

impl FromCast<Simd<[m8; 4]>> for usizex4[src]

impl FromCast<Simd<[m8; 64]>> for i8x64[src]

impl FromCast<Simd<[m8; 64]>> for u8x64[src]

impl FromCast<Simd<[m8; 8]>> for f32x8[src]

impl FromCast<Simd<[m8; 8]>> for f64x8[src]

impl FromCast<Simd<[m8; 8]>> for i16x8[src]

impl FromCast<Simd<[m8; 8]>> for i32x8[src]

impl FromCast<Simd<[m8; 8]>> for i64x8[src]

impl FromCast<Simd<[m8; 8]>> for i8x8[src]

impl FromCast<Simd<[m8; 8]>> for isizex8[src]

impl FromCast<Simd<[m8; 8]>> for m16x8[src]

impl FromCast<Simd<[m8; 8]>> for m32x8[src]

impl FromCast<Simd<[m8; 8]>> for m64x8[src]

impl FromCast<Simd<[m8; 8]>> for msizex8[src]

impl FromCast<Simd<[m8; 8]>> for u16x8[src]

impl FromCast<Simd<[m8; 8]>> for u32x8[src]

impl FromCast<Simd<[m8; 8]>> for u64x8[src]

impl FromCast<Simd<[m8; 8]>> for u8x8[src]

impl FromCast<Simd<[m8; 8]>> for usizex8[src]

impl FromCast<Simd<[msize; 2]>> for f32x2[src]

impl FromCast<Simd<[msize; 2]>> for f64x2[src]

impl FromCast<Simd<[msize; 2]>> for i128x2[src]

impl FromCast<Simd<[msize; 2]>> for i16x2[src]

impl FromCast<Simd<[msize; 2]>> for i32x2[src]

impl FromCast<Simd<[msize; 2]>> for i64x2[src]

impl FromCast<Simd<[msize; 2]>> for i8x2[src]

impl FromCast<Simd<[msize; 2]>> for isizex2[src]

impl FromCast<Simd<[msize; 2]>> for m128x2[src]

impl FromCast<Simd<[msize; 2]>> for m16x2[src]

impl FromCast<Simd<[msize; 2]>> for m32x2[src]

impl FromCast<Simd<[msize; 2]>> for m64x2[src]

impl FromCast<Simd<[msize; 2]>> for m8x2[src]

impl FromCast<Simd<[msize; 2]>> for u128x2[src]

impl FromCast<Simd<[msize; 2]>> for u16x2[src]

impl FromCast<Simd<[msize; 2]>> for u32x2[src]

impl FromCast<Simd<[msize; 2]>> for u64x2[src]

impl FromCast<Simd<[msize; 2]>> for u8x2[src]

impl FromCast<Simd<[msize; 2]>> for usizex2[src]

impl FromCast<Simd<[msize; 4]>> for f32x4[src]

impl FromCast<Simd<[msize; 4]>> for f64x4[src]

impl FromCast<Simd<[msize; 4]>> for i128x4[src]

impl FromCast<Simd<[msize; 4]>> for i16x4[src]

impl FromCast<Simd<[msize; 4]>> for i32x4[src]

impl FromCast<Simd<[msize; 4]>> for i64x4[src]

impl FromCast<Simd<[msize; 4]>> for i8x4[src]

impl FromCast<Simd<[msize; 4]>> for isizex4[src]

impl FromCast<Simd<[msize; 4]>> for m128x4[src]

impl FromCast<Simd<[msize; 4]>> for m16x4[src]

impl FromCast<Simd<[msize; 4]>> for m32x4[src]

impl FromCast<Simd<[msize; 4]>> for m64x4[src]

impl FromCast<Simd<[msize; 4]>> for m8x4[src]

impl FromCast<Simd<[msize; 4]>> for u128x4[src]

impl FromCast<Simd<[msize; 4]>> for u16x4[src]

impl FromCast<Simd<[msize; 4]>> for u32x4[src]

impl FromCast<Simd<[msize; 4]>> for u64x4[src]

impl FromCast<Simd<[msize; 4]>> for u8x4[src]

impl FromCast<Simd<[msize; 4]>> for usizex4[src]

impl FromCast<Simd<[msize; 8]>> for f32x8[src]

impl FromCast<Simd<[msize; 8]>> for f64x8[src]

impl FromCast<Simd<[msize; 8]>> for i16x8[src]

impl FromCast<Simd<[msize; 8]>> for i32x8[src]

impl FromCast<Simd<[msize; 8]>> for i64x8[src]

impl FromCast<Simd<[msize; 8]>> for i8x8[src]

impl FromCast<Simd<[msize; 8]>> for isizex8[src]

impl FromCast<Simd<[msize; 8]>> for m16x8[src]

impl FromCast<Simd<[msize; 8]>> for m32x8[src]

impl FromCast<Simd<[msize; 8]>> for m64x8[src]

impl FromCast<Simd<[msize; 8]>> for m8x8[src]

impl FromCast<Simd<[msize; 8]>> for u16x8[src]

impl FromCast<Simd<[msize; 8]>> for u32x8[src]

impl FromCast<Simd<[msize; 8]>> for u64x8[src]

impl FromCast<Simd<[msize; 8]>> for u8x8[src]

impl FromCast<Simd<[msize; 8]>> for usizex8[src]

impl FromCast<Simd<[f32; 16]>> for i16x16[src]

impl FromCast<Simd<[f32; 16]>> for i32x16[src]

impl FromCast<Simd<[f32; 16]>> for i8x16[src]

impl FromCast<Simd<[f32; 16]>> for m16x16[src]

impl FromCast<Simd<[f32; 16]>> for m32x16[src]

impl FromCast<Simd<[f32; 16]>> for m8x16[src]

impl FromCast<Simd<[f32; 16]>> for u16x16[src]

impl FromCast<Simd<[f32; 16]>> for u32x16[src]

impl FromCast<Simd<[f32; 16]>> for u8x16[src]

impl FromCast<Simd<[f32; 2]>> for f64x2[src]

impl FromCast<Simd<[f32; 2]>> for i128x2[src]

impl FromCast<Simd<[f32; 2]>> for i16x2[src]

impl FromCast<Simd<[f32; 2]>> for i32x2[src]

impl FromCast<Simd<[f32; 2]>> for i64x2[src]

impl FromCast<Simd<[f32; 2]>> for i8x2[src]

impl FromCast<Simd<[f32; 2]>> for isizex2[src]

impl FromCast<Simd<[f32; 2]>> for m128x2[src]

impl FromCast<Simd<[f32; 2]>> for m16x2[src]

impl FromCast<Simd<[f32; 2]>> for m32x2[src]

impl FromCast<Simd<[f32; 2]>> for m64x2[src]

impl FromCast<Simd<[f32; 2]>> for m8x2[src]

impl FromCast<Simd<[f32; 2]>> for msizex2[src]

impl FromCast<Simd<[f32; 2]>> for u128x2[src]

impl FromCast<Simd<[f32; 2]>> for u16x2[src]

impl FromCast<Simd<[f32; 2]>> for u32x2[src]

impl FromCast<Simd<[f32; 2]>> for u64x2[src]

impl FromCast<Simd<[f32; 2]>> for u8x2[src]

impl FromCast<Simd<[f32; 2]>> for usizex2[src]

impl FromCast<Simd<[f32; 4]>> for f64x4[src]

impl FromCast<Simd<[f32; 4]>> for i128x4[src]

impl FromCast<Simd<[f32; 4]>> for i16x4[src]

impl FromCast<Simd<[f32; 4]>> for i32x4[src]

impl FromCast<Simd<[f32; 4]>> for i64x4[src]

impl FromCast<Simd<[f32; 4]>> for i8x4[src]

impl FromCast<Simd<[f32; 4]>> for isizex4[src]

impl FromCast<Simd<[f32; 4]>> for m128x4[src]

impl FromCast<Simd<[f32; 4]>> for m16x4[src]

impl FromCast<Simd<[f32; 4]>> for m32x4[src]

impl FromCast<Simd<[f32; 4]>> for m64x4[src]

impl FromCast<Simd<[f32; 4]>> for m8x4[src]

impl FromCast<Simd<[f32; 4]>> for msizex4[src]

impl FromCast<Simd<[f32; 4]>> for u128x4[src]

impl FromCast<Simd<[f32; 4]>> for u16x4[src]

impl FromCast<Simd<[f32; 4]>> for u32x4[src]

impl FromCast<Simd<[f32; 4]>> for u64x4[src]

impl FromCast<Simd<[f32; 4]>> for u8x4[src]

impl FromCast<Simd<[f32; 4]>> for usizex4[src]

impl FromCast<Simd<[f32; 8]>> for f64x8[src]

impl FromCast<Simd<[f32; 8]>> for i16x8[src]

impl FromCast<Simd<[f32; 8]>> for i32x8[src]

impl FromCast<Simd<[f32; 8]>> for i64x8[src]

impl FromCast<Simd<[f32; 8]>> for i8x8[src]

impl FromCast<Simd<[f32; 8]>> for isizex8[src]

impl FromCast<Simd<[f32; 8]>> for m16x8[src]

impl FromCast<Simd<[f32; 8]>> for m32x8[src]

impl FromCast<Simd<[f32; 8]>> for m64x8[src]

impl FromCast<Simd<[f32; 8]>> for m8x8[src]

impl FromCast<Simd<[f32; 8]>> for msizex8[src]

impl FromCast<Simd<[f32; 8]>> for u16x8[src]

impl FromCast<Simd<[f32; 8]>> for u32x8[src]

impl FromCast<Simd<[f32; 8]>> for u64x8[src]

impl FromCast<Simd<[f32; 8]>> for u8x8[src]

impl FromCast<Simd<[f32; 8]>> for usizex8[src]

impl FromCast<Simd<[f64; 2]>> for f32x2[src]

impl FromCast<Simd<[f64; 2]>> for i128x2[src]

impl FromCast<Simd<[f64; 2]>> for i16x2[src]

impl FromCast<Simd<[f64; 2]>> for i32x2[src]

impl FromCast<Simd<[f64; 2]>> for i64x2[src]

impl FromCast<Simd<[f64; 2]>> for i8x2[src]

impl FromCast<Simd<[f64; 2]>> for isizex2[src]

impl FromCast<Simd<[f64; 2]>> for m128x2[src]

impl FromCast<Simd<[f64; 2]>> for m16x2[src]

impl FromCast<Simd<[f64; 2]>> for m32x2[src]

impl FromCast<Simd<[f64; 2]>> for m64x2[src]

impl FromCast<Simd<[f64; 2]>> for m8x2[src]

impl FromCast<Simd<[f64; 2]>> for msizex2[src]

impl FromCast<Simd<[f64; 2]>> for u128x2[src]

impl FromCast<Simd<[f64; 2]>> for u16x2[src]

impl FromCast<Simd<[f64; 2]>> for u32x2[src]

impl FromCast<Simd<[f64; 2]>> for u64x2[src]

impl FromCast<Simd<[f64; 2]>> for u8x2[src]

impl FromCast<Simd<[f64; 2]>> for usizex2[src]

impl FromCast<Simd<[f64; 4]>> for f32x4[src]

impl FromCast<Simd<[f64; 4]>> for i128x4[src]

impl FromCast<Simd<[f64; 4]>> for i16x4[src]

impl FromCast<Simd<[f64; 4]>> for i32x4[src]

impl FromCast<Simd<[f64; 4]>> for i64x4[src]

impl FromCast<Simd<[f64; 4]>> for i8x4[src]

impl FromCast<Simd<[f64; 4]>> for isizex4[src]

impl FromCast<Simd<[f64; 4]>> for m128x4[src]

impl FromCast<Simd<[f64; 4]>> for m16x4[src]

impl FromCast<Simd<[f64; 4]>> for m32x4[src]

impl FromCast<Simd<[f64; 4]>> for m64x4[src]

impl FromCast<Simd<[f64; 4]>> for m8x4[src]

impl FromCast<Simd<[f64; 4]>> for msizex4[src]

impl FromCast<Simd<[f64; 4]>> for u128x4[src]

impl FromCast<Simd<[f64; 4]>> for u16x4[src]

impl FromCast<Simd<[f64; 4]>> for u32x4[src]

impl FromCast<Simd<[f64; 4]>> for u64x4[src]

impl FromCast<Simd<[f64; 4]>> for u8x4[src]

impl FromCast<Simd<[f64; 4]>> for usizex4[src]

impl FromCast<Simd<[f64; 8]>> for f32x8[src]

impl FromCast<Simd<[f64; 8]>> for i16x8[src]

impl FromCast<Simd<[f64; 8]>> for i32x8[src]

impl FromCast<Simd<[f64; 8]>> for i64x8[src]

impl FromCast<Simd<[f64; 8]>> for i8x8[src]

impl FromCast<Simd<[f64; 8]>> for isizex8[src]

impl FromCast<Simd<[f64; 8]>> for m16x8[src]

impl FromCast<Simd<[f64; 8]>> for m32x8[src]

impl FromCast<Simd<[f64; 8]>> for m64x8[src]

impl FromCast<Simd<[f64; 8]>> for m8x8[src]

impl FromCast<Simd<[f64; 8]>> for msizex8[src]

impl FromCast<Simd<[f64; 8]>> for u16x8[src]

impl FromCast<Simd<[f64; 8]>> for u32x8[src]

impl FromCast<Simd<[f64; 8]>> for u64x8[src]

impl FromCast<Simd<[f64; 8]>> for u8x8[src]

impl FromCast<Simd<[f64; 8]>> for usizex8[src]

impl FromCast<Simd<[i128; 1]>> for m128x1[src]

impl FromCast<Simd<[i128; 1]>> for u128x1[src]

impl FromCast<Simd<[i128; 2]>> for f32x2[src]

impl FromCast<Simd<[i128; 2]>> for f64x2[src]

impl FromCast<Simd<[i128; 2]>> for i16x2[src]

impl FromCast<Simd<[i128; 2]>> for i32x2[src]

impl FromCast<Simd<[i128; 2]>> for i64x2[src]

impl FromCast<Simd<[i128; 2]>> for i8x2[src]

impl FromCast<Simd<[i128; 2]>> for isizex2[src]

impl FromCast<Simd<[i128; 2]>> for m128x2[src]

impl FromCast<Simd<[i128; 2]>> for m16x2[src]

impl FromCast<Simd<[i128; 2]>> for m32x2[src]

impl FromCast<Simd<[i128; 2]>> for m64x2[src]

impl FromCast<Simd<[i128; 2]>> for m8x2[src]

impl FromCast<Simd<[i128; 2]>> for msizex2[src]

impl FromCast<Simd<[i128; 2]>> for u128x2[src]

impl FromCast<Simd<[i128; 2]>> for u16x2[src]

impl FromCast<Simd<[i128; 2]>> for u32x2[src]

impl FromCast<Simd<[i128; 2]>> for u64x2[src]

impl FromCast<Simd<[i128; 2]>> for u8x2[src]

impl FromCast<Simd<[i128; 2]>> for usizex2[src]

impl FromCast<Simd<[i128; 4]>> for f32x4[src]

impl FromCast<Simd<[i128; 4]>> for f64x4[src]

impl FromCast<Simd<[i128; 4]>> for i16x4[src]

impl FromCast<Simd<[i128; 4]>> for i32x4[src]

impl FromCast<Simd<[i128; 4]>> for i64x4[src]

impl FromCast<Simd<[i128; 4]>> for i8x4[src]

impl FromCast<Simd<[i128; 4]>> for isizex4[src]

impl FromCast<Simd<[i128; 4]>> for m128x4[src]

impl FromCast<Simd<[i128; 4]>> for m16x4[src]

impl FromCast<Simd<[i128; 4]>> for m32x4[src]

impl FromCast<Simd<[i128; 4]>> for m64x4[src]

impl FromCast<Simd<[i128; 4]>> for m8x4[src]

impl FromCast<Simd<[i128; 4]>> for msizex4[src]

impl FromCast<Simd<[i128; 4]>> for u128x4[src]

impl FromCast<Simd<[i128; 4]>> for u16x4[src]

impl FromCast<Simd<[i128; 4]>> for u32x4[src]

impl FromCast<Simd<[i128; 4]>> for u64x4[src]

impl FromCast<Simd<[i128; 4]>> for u8x4[src]

impl FromCast<Simd<[i128; 4]>> for usizex4[src]

impl FromCast<Simd<[i16; 16]>> for f32x16[src]

impl FromCast<Simd<[i16; 16]>> for i32x16[src]

impl FromCast<Simd<[i16; 16]>> for i8x16[src]

impl FromCast<Simd<[i16; 16]>> for m16x16[src]

impl FromCast<Simd<[i16; 16]>> for m32x16[src]

impl FromCast<Simd<[i16; 16]>> for m8x16[src]

impl FromCast<Simd<[i16; 16]>> for u16x16[src]

impl FromCast<Simd<[i16; 16]>> for u32x16[src]

impl FromCast<Simd<[i16; 16]>> for u8x16[src]

impl FromCast<Simd<[i16; 2]>> for f32x2[src]

impl FromCast<Simd<[i16; 2]>> for f64x2[src]

impl FromCast<Simd<[i16; 2]>> for i128x2[src]

impl FromCast<Simd<[i16; 2]>> for i32x2[src]

impl FromCast<Simd<[i16; 2]>> for i64x2[src]

impl FromCast<Simd<[i16; 2]>> for i8x2[src]

impl FromCast<Simd<[i16; 2]>> for isizex2[src]

impl FromCast<Simd<[i16; 2]>> for m128x2[src]

impl FromCast<Simd<[i16; 2]>> for m16x2[src]

impl FromCast<Simd<[i16; 2]>> for m32x2[src]

impl FromCast<Simd<[i16; 2]>> for m64x2[src]

impl FromCast<Simd<[i16; 2]>> for m8x2[src]

impl FromCast<Simd<[i16; 2]>> for msizex2[src]

impl FromCast<Simd<[i16; 2]>> for u128x2[src]

impl FromCast<Simd<[i16; 2]>> for u16x2[src]

impl FromCast<Simd<[i16; 2]>> for u32x2[src]

impl FromCast<Simd<[i16; 2]>> for u64x2[src]

impl FromCast<Simd<[i16; 2]>> for u8x2[src]

impl FromCast<Simd<[i16; 2]>> for usizex2[src]

impl FromCast<Simd<[i16; 32]>> for i8x32[src]

impl FromCast<Simd<[i16; 32]>> for m16x32[src]

impl FromCast<Simd<[i16; 32]>> for m8x32[src]

impl FromCast<Simd<[i16; 32]>> for u16x32[src]

impl FromCast<Simd<[i16; 32]>> for u8x32[src]

impl FromCast<Simd<[i16; 4]>> for f32x4[src]

impl FromCast<Simd<[i16; 4]>> for f64x4[src]

impl FromCast<Simd<[i16; 4]>> for i128x4[src]

impl FromCast<Simd<[i16; 4]>> for i32x4[src]

impl FromCast<Simd<[i16; 4]>> for i64x4[src]

impl FromCast<Simd<[i16; 4]>> for i8x4[src]

impl FromCast<Simd<[i16; 4]>> for isizex4[src]

impl FromCast<Simd<[i16; 4]>> for m128x4[src]

impl FromCast<Simd<[i16; 4]>> for m16x4[src]

impl FromCast<Simd<[i16; 4]>> for m32x4[src]

impl FromCast<Simd<[i16; 4]>> for m64x4[src]

impl FromCast<Simd<[i16; 4]>> for m8x4[src]

impl FromCast<Simd<[i16; 4]>> for msizex4[src]

impl FromCast<Simd<[i16; 4]>> for u128x4[src]

impl FromCast<Simd<[i16; 4]>> for u16x4[src]

impl FromCast<Simd<[i16; 4]>> for u32x4[src]

impl FromCast<Simd<[i16; 4]>> for u64x4[src]

impl FromCast<Simd<[i16; 4]>> for u8x4[src]

impl FromCast<Simd<[i16; 4]>> for usizex4[src]

impl FromCast<Simd<[i16; 8]>> for f32x8[src]

impl FromCast<Simd<[i16; 8]>> for f64x8[src]

impl FromCast<Simd<[i16; 8]>> for i32x8[src]

impl FromCast<Simd<[i16; 8]>> for i64x8[src]

impl FromCast<Simd<[i16; 8]>> for i8x8[src]

impl FromCast<Simd<[i16; 8]>> for isizex8[src]

impl FromCast<Simd<[i16; 8]>> for m16x8[src]

impl FromCast<Simd<[i16; 8]>> for m32x8[src]

impl FromCast<Simd<[i16; 8]>> for m64x8[src]

impl FromCast<Simd<[i16; 8]>> for m8x8[src]

impl FromCast<Simd<[i16; 8]>> for msizex8[src]

impl FromCast<Simd<[i16; 8]>> for u16x8[src]

impl FromCast<Simd<[i16; 8]>> for u32x8[src]

impl FromCast<Simd<[i16; 8]>> for u64x8[src]

impl FromCast<Simd<[i16; 8]>> for u8x8[src]

impl FromCast<Simd<[i16; 8]>> for usizex8[src]

impl FromCast<Simd<[i32; 16]>> for f32x16[src]

impl FromCast<Simd<[i32; 16]>> for i16x16[src]

impl FromCast<Simd<[i32; 16]>> for i8x16[src]

impl FromCast<Simd<[i32; 16]>> for m16x16[src]

impl FromCast<Simd<[i32; 16]>> for m32x16[src]

impl FromCast<Simd<[i32; 16]>> for m8x16[src]

impl FromCast<Simd<[i32; 16]>> for u16x16[src]

impl FromCast<Simd<[i32; 16]>> for u32x16[src]

impl FromCast<Simd<[i32; 16]>> for u8x16[src]

impl FromCast<Simd<[i32; 2]>> for f32x2[src]

impl FromCast<Simd<[i32; 2]>> for f64x2[src]

impl FromCast<Simd<[i32; 2]>> for i128x2[src]

impl FromCast<Simd<[i32; 2]>> for i16x2[src]

impl FromCast<Simd<[i32; 2]>> for i64x2[src]

impl FromCast<Simd<[i32; 2]>> for i8x2[src]

impl FromCast<Simd<[i32; 2]>> for isizex2[src]

impl FromCast<Simd<[i32; 2]>> for m128x2[src]

impl FromCast<Simd<[i32; 2]>> for m16x2[src]

impl FromCast<Simd<[i32; 2]>> for m32x2[src]

impl FromCast<Simd<[i32; 2]>> for m64x2[src]

impl FromCast<Simd<[i32; 2]>> for m8x2[src]

impl FromCast<Simd<[i32; 2]>> for msizex2[src]

impl FromCast<Simd<[i32; 2]>> for u128x2[src]

impl FromCast<Simd<[i32; 2]>> for u16x2[src]

impl FromCast<Simd<[i32; 2]>> for u32x2[src]

impl FromCast<Simd<[i32; 2]>> for u64x2[src]

impl FromCast<Simd<[i32; 2]>> for u8x2[src]

impl FromCast<Simd<[i32; 2]>> for usizex2[src]

impl FromCast<Simd<[i32; 4]>> for f32x4[src]

impl FromCast<Simd<[i32; 4]>> for f64x4[src]

impl FromCast<Simd<[i32; 4]>> for i128x4[src]

impl FromCast<Simd<[i32; 4]>> for i16x4[src]

impl FromCast<Simd<[i32; 4]>> for i64x4[src]

impl FromCast<Simd<[i32; 4]>> for i8x4[src]

impl FromCast<Simd<[i32; 4]>> for isizex4[src]

impl FromCast<Simd<[i32; 4]>> for m128x4[src]

impl FromCast<Simd<[i32; 4]>> for m16x4[src]

impl FromCast<Simd<[i32; 4]>> for m32x4[src]

impl FromCast<Simd<[i32; 4]>> for m64x4[src]

impl FromCast<Simd<[i32; 4]>> for m8x4[src]

impl FromCast<Simd<[i32; 4]>> for msizex4[src]

impl FromCast<Simd<[i32; 4]>> for u128x4[src]

impl FromCast<Simd<[i32; 4]>> for u16x4[src]

impl FromCast<Simd<[i32; 4]>> for u32x4[src]

impl FromCast<Simd<[i32; 4]>> for u64x4[src]

impl FromCast<Simd<[i32; 4]>> for u8x4[src]

impl FromCast<Simd<[i32; 4]>> for usizex4[src]

impl FromCast<Simd<[i32; 8]>> for f32x8[src]

impl FromCast<Simd<[i32; 8]>> for f64x8[src]

impl FromCast<Simd<[i32; 8]>> for i16x8[src]

impl FromCast<Simd<[i32; 8]>> for i64x8[src]

impl FromCast<Simd<[i32; 8]>> for i8x8[src]

impl FromCast<Simd<[i32; 8]>> for isizex8[src]

impl FromCast<Simd<[i32; 8]>> for m16x8[src]

impl FromCast<Simd<[i32; 8]>> for m32x8[src]

impl FromCast<Simd<[i32; 8]>> for m64x8[src]

impl FromCast<Simd<[i32; 8]>> for m8x8[src]

impl FromCast<Simd<[i32; 8]>> for msizex8[src]

impl FromCast<Simd<[i32; 8]>> for u16x8[src]

impl FromCast<Simd<[i32; 8]>> for u32x8[src]

impl FromCast<Simd<[i32; 8]>> for u64x8[src]

impl FromCast<Simd<[i32; 8]>> for u8x8[src]

impl FromCast<Simd<[i32; 8]>> for usizex8[src]

impl FromCast<Simd<[i64; 2]>> for f32x2[src]

impl FromCast<Simd<[i64; 2]>> for f64x2[src]

impl FromCast<Simd<[i64; 2]>> for i128x2[src]

impl FromCast<Simd<[i64; 2]>> for i16x2[src]

impl FromCast<Simd<[i64; 2]>> for i32x2[src]

impl FromCast<Simd<[i64; 2]>> for i8x2[src]

impl FromCast<Simd<[i64; 2]>> for isizex2[src]

impl FromCast<Simd<[i64; 2]>> for m128x2[src]

impl FromCast<Simd<[i64; 2]>> for m16x2[src]

impl FromCast<Simd<[i64; 2]>> for m32x2[src]

impl FromCast<Simd<[i64; 2]>> for m64x2[src]

impl FromCast<Simd<[i64; 2]>> for m8x2[src]

impl FromCast<Simd<[i64; 2]>> for msizex2[src]

impl FromCast<Simd<[i64; 2]>> for u128x2[src]

impl FromCast<Simd<[i64; 2]>> for u16x2[src]

impl FromCast<Simd<[i64; 2]>> for u32x2[src]

impl FromCast<Simd<[i64; 2]>> for u64x2[src]

impl FromCast<Simd<[i64; 2]>> for u8x2[src]

impl FromCast<Simd<[i64; 2]>> for usizex2[src]

impl FromCast<Simd<[i64; 4]>> for f32x4[src]

impl FromCast<Simd<[i64; 4]>> for f64x4[src]

impl FromCast<Simd<[i64; 4]>> for i128x4[src]

impl FromCast<Simd<[i64; 4]>> for i16x4[src]

impl FromCast<Simd<[i64; 4]>> for i32x4[src]

impl FromCast<Simd<[i64; 4]>> for i8x4[src]

impl FromCast<Simd<[i64; 4]>> for isizex4[src]

impl FromCast<Simd<[i64; 4]>> for m128x4[src]

impl FromCast<Simd<[i64; 4]>> for m16x4[src]

impl FromCast<Simd<[i64; 4]>> for m32x4[src]

impl FromCast<Simd<[i64; 4]>> for m64x4[src]

impl FromCast<Simd<[i64; 4]>> for m8x4[src]

impl FromCast<Simd<[i64; 4]>> for msizex4[src]

impl FromCast<Simd<[i64; 4]>> for u128x4[src]

impl FromCast<Simd<[i64; 4]>> for u16x4[src]

impl FromCast<Simd<[i64; 4]>> for u32x4[src]

impl FromCast<Simd<[i64; 4]>> for u64x4[src]

impl FromCast<Simd<[i64; 4]>> for u8x4[src]

impl FromCast<Simd<[i64; 4]>> for usizex4[src]

impl FromCast<Simd<[i64; 8]>> for f32x8[src]

impl FromCast<Simd<[i64; 8]>> for f64x8[src]

impl FromCast<Simd<[i64; 8]>> for i16x8[src]

impl FromCast<Simd<[i64; 8]>> for i32x8[src]

impl FromCast<Simd<[i64; 8]>> for i8x8[src]

impl FromCast<Simd<[i64; 8]>> for isizex8[src]

impl FromCast<Simd<[i64; 8]>> for m16x8[src]

impl FromCast<Simd<[i64; 8]>> for m32x8[src]

impl FromCast<Simd<[i64; 8]>> for m64x8[src]

impl FromCast<Simd<[i64; 8]>> for m8x8[src]

impl FromCast<Simd<[i64; 8]>> for msizex8[src]

impl FromCast<Simd<[i64; 8]>> for u16x8[src]

impl FromCast<Simd<[i64; 8]>> for u32x8[src]

impl FromCast<Simd<[i64; 8]>> for u64x8[src]

impl FromCast<Simd<[i64; 8]>> for u8x8[src]

impl FromCast<Simd<[i64; 8]>> for usizex8[src]

impl FromCast<Simd<[i8; 16]>> for f32x16[src]

impl FromCast<Simd<[i8; 16]>> for i16x16[src]

impl FromCast<Simd<[i8; 16]>> for i32x16[src]

impl FromCast<Simd<[i8; 16]>> for m16x16[src]

impl FromCast<Simd<[i8; 16]>> for m32x16[src]

impl FromCast<Simd<[i8; 16]>> for m8x16[src]

impl FromCast<Simd<[i8; 16]>> for u16x16[src]

impl FromCast<Simd<[i8; 16]>> for u32x16[src]

impl FromCast<Simd<[i8; 16]>> for u8x16[src]

impl FromCast<Simd<[i8; 2]>> for f32x2[src]

impl FromCast<Simd<[i8; 2]>> for f64x2[src]

impl FromCast<Simd<[i8; 2]>> for i128x2[src]

impl FromCast<Simd<[i8; 2]>> for i16x2[src]

impl FromCast<Simd<[i8; 2]>> for i32x2[src]

impl FromCast<Simd<[i8; 2]>> for i64x2[src]

impl FromCast<Simd<[i8; 2]>> for isizex2[src]

impl FromCast<Simd<[i8; 2]>> for m128x2[src]

impl FromCast<Simd<[i8; 2]>> for m16x2[src]

impl FromCast<Simd<[i8; 2]>> for m32x2[src]

impl FromCast<Simd<[i8; 2]>> for m64x2[src]

impl FromCast<Simd<[i8; 2]>> for m8x2[src]

impl FromCast<Simd<[i8; 2]>> for msizex2[src]

impl FromCast<Simd<[i8; 2]>> for u128x2[src]

impl FromCast<Simd<[i8; 2]>> for u16x2[src]

impl FromCast<Simd<[i8; 2]>> for u32x2[src]

impl FromCast<Simd<[i8; 2]>> for u64x2[src]

impl FromCast<Simd<[i8; 2]>> for u8x2[src]

impl FromCast<Simd<[i8; 2]>> for usizex2[src]

impl FromCast<Simd<[i8; 32]>> for i16x32[src]

impl FromCast<Simd<[i8; 32]>> for m16x32[src]

impl FromCast<Simd<[i8; 32]>> for m8x32[src]

impl FromCast<Simd<[i8; 32]>> for u16x32[src]

impl FromCast<Simd<[i8; 32]>> for u8x32[src]

impl FromCast<Simd<[i8; 4]>> for f32x4[src]

impl FromCast<Simd<[i8; 4]>> for f64x4[src]

impl FromCast<Simd<[i8; 4]>> for i128x4[src]

impl FromCast<Simd<[i8; 4]>> for i16x4[src]

impl FromCast<Simd<[i8; 4]>> for i32x4[src]

impl FromCast<Simd<[i8; 4]>> for i64x4[src]

impl FromCast<Simd<[i8; 4]>> for isizex4[src]

impl FromCast<Simd<[i8; 4]>> for m128x4[src]

impl FromCast<Simd<[i8; 4]>> for m16x4[src]

impl FromCast<Simd<[i8; 4]>> for m32x4[src]

impl FromCast<Simd<[i8; 4]>> for m64x4[src]

impl FromCast<Simd<[i8; 4]>> for m8x4[src]

impl FromCast<Simd<[i8; 4]>> for msizex4[src]

impl FromCast<Simd<[i8; 4]>> for u128x4[src]

impl FromCast<Simd<[i8; 4]>> for u16x4[src]

impl FromCast<Simd<[i8; 4]>> for u32x4[src]

impl FromCast<Simd<[i8; 4]>> for u64x4[src]

impl FromCast<Simd<[i8; 4]>> for u8x4[src]

impl FromCast<Simd<[i8; 4]>> for usizex4[src]

impl FromCast<Simd<[i8; 64]>> for m8x64[src]

impl FromCast<Simd<[i8; 64]>> for u8x64[src]

impl FromCast<Simd<[i8; 8]>> for f32x8[src]

impl FromCast<Simd<[i8; 8]>> for f64x8[src]

impl FromCast<Simd<[i8; 8]>> for i16x8[src]

impl FromCast<Simd<[i8; 8]>> for i32x8[src]

impl FromCast<Simd<[i8; 8]>> for i64x8[src]

impl FromCast<Simd<[i8; 8]>> for isizex8[src]

impl FromCast<Simd<[i8; 8]>> for m16x8[src]

impl FromCast<Simd<[i8; 8]>> for m32x8[src]

impl FromCast<Simd<[i8; 8]>> for m64x8[src]

impl FromCast<Simd<[i8; 8]>> for m8x8[src]

impl FromCast<Simd<[i8; 8]>> for msizex8[src]

impl FromCast<Simd<[i8; 8]>> for u16x8[src]

impl FromCast<Simd<[i8; 8]>> for u32x8[src]

impl FromCast<Simd<[i8; 8]>> for u64x8[src]

impl FromCast<Simd<[i8; 8]>> for u8x8[src]

impl FromCast<Simd<[i8; 8]>> for usizex8[src]

impl FromCast<Simd<[isize; 2]>> for f32x2[src]

impl FromCast<Simd<[isize; 2]>> for f64x2[src]

impl FromCast<Simd<[isize; 2]>> for i128x2[src]

impl FromCast<Simd<[isize; 2]>> for i16x2[src]

impl FromCast<Simd<[isize; 2]>> for i32x2[src]

impl FromCast<Simd<[isize; 2]>> for i64x2[src]

impl FromCast<Simd<[isize; 2]>> for i8x2[src]

impl FromCast<Simd<[isize; 2]>> for m128x2[src]

impl FromCast<Simd<[isize; 2]>> for m16x2[src]

impl FromCast<Simd<[isize; 2]>> for m32x2[src]

impl FromCast<Simd<[isize; 2]>> for m64x2[src]

impl FromCast<Simd<[isize; 2]>> for m8x2[src]

impl FromCast<Simd<[isize; 2]>> for msizex2[src]

impl FromCast<Simd<[isize; 2]>> for u128x2[src]

impl FromCast<Simd<[isize; 2]>> for u16x2[src]

impl FromCast<Simd<[isize; 2]>> for u32x2[src]

impl FromCast<Simd<[isize; 2]>> for u64x2[src]

impl FromCast<Simd<[isize; 2]>> for u8x2[src]

impl FromCast<Simd<[isize; 2]>> for usizex2[src]

impl FromCast<Simd<[isize; 4]>> for f32x4[src]

impl FromCast<Simd<[isize; 4]>> for f64x4[src]

impl FromCast<Simd<[isize; 4]>> for i128x4[src]

impl FromCast<Simd<[isize; 4]>> for i16x4[src]

impl FromCast<Simd<[isize; 4]>> for i32x4[src]

impl FromCast<Simd<[isize; 4]>> for i64x4[src]

impl FromCast<Simd<[isize; 4]>> for i8x4[src]

impl FromCast<Simd<[isize; 4]>> for m128x4[src]

impl FromCast<Simd<[isize; 4]>> for m16x4[src]

impl FromCast<Simd<[isize; 4]>> for m32x4[src]

impl FromCast<Simd<[isize; 4]>> for m64x4[src]

impl FromCast<Simd<[isize; 4]>> for m8x4[src]

impl FromCast<Simd<[isize; 4]>> for msizex4[src]

impl FromCast<Simd<[isize; 4]>> for u128x4[src]

impl FromCast<Simd<[isize; 4]>> for u16x4[src]

impl FromCast<Simd<[isize; 4]>> for u32x4[src]

impl FromCast<Simd<[isize; 4]>> for u64x4[src]

impl FromCast<Simd<[isize; 4]>> for u8x4[src]

impl FromCast<Simd<[isize; 4]>> for usizex4[src]

impl FromCast<Simd<[isize; 8]>> for f32x8[src]

impl FromCast<Simd<[isize; 8]>> for f64x8[src]

impl FromCast<Simd<[isize; 8]>> for i16x8[src]

impl FromCast<Simd<[isize; 8]>> for i32x8[src]

impl FromCast<Simd<[isize; 8]>> for i64x8[src]

impl FromCast<Simd<[isize; 8]>> for i8x8[src]

impl FromCast<Simd<[isize; 8]>> for m16x8[src]

impl FromCast<Simd<[isize; 8]>> for m32x8[src]

impl FromCast<Simd<[isize; 8]>> for m64x8[src]

impl FromCast<Simd<[isize; 8]>> for m8x8[src]

impl FromCast<Simd<[isize; 8]>> for msizex8[src]

impl FromCast<Simd<[isize; 8]>> for u16x8[src]

impl FromCast<Simd<[isize; 8]>> for u32x8[src]

impl FromCast<Simd<[isize; 8]>> for u64x8[src]

impl FromCast<Simd<[isize; 8]>> for u8x8[src]

impl FromCast<Simd<[isize; 8]>> for usizex8[src]

impl FromCast<Simd<[u128; 1]>> for i128x1[src]

impl FromCast<Simd<[u128; 1]>> for m128x1[src]

impl FromCast<Simd<[u128; 2]>> for f32x2[src]

impl FromCast<Simd<[u128; 2]>> for f64x2[src]

impl FromCast<Simd<[u128; 2]>> for i128x2[src]

impl FromCast<Simd<[u128; 2]>> for i16x2[src]

impl FromCast<Simd<[u128; 2]>> for i32x2[src]

impl FromCast<Simd<[u128; 2]>> for i64x2[src]

impl FromCast<Simd<[u128; 2]>> for i8x2[src]

impl FromCast<Simd<[u128; 2]>> for isizex2[src]

impl FromCast<Simd<[u128; 2]>> for m128x2[src]

impl FromCast<Simd<[u128; 2]>> for m16x2[src]

impl FromCast<Simd<[u128; 2]>> for m32x2[src]

impl FromCast<Simd<[u128; 2]>> for m64x2[src]

impl FromCast<Simd<[u128; 2]>> for m8x2[src]

impl FromCast<Simd<[u128; 2]>> for msizex2[src]

impl FromCast<Simd<[u128; 2]>> for u16x2[src]

impl FromCast<Simd<[u128; 2]>> for u32x2[src]

impl FromCast<Simd<[u128; 2]>> for u64x2[src]

impl FromCast<Simd<[u128; 2]>> for u8x2[src]

impl FromCast<Simd<[u128; 2]>> for usizex2[src]

impl FromCast<Simd<[u128; 4]>> for f32x4[src]

impl FromCast<Simd<[u128; 4]>> for f64x4[src]

impl FromCast<Simd<[u128; 4]>> for i128x4[src]

impl FromCast<Simd<[u128; 4]>> for i16x4[src]

impl FromCast<Simd<[u128; 4]>> for i32x4[src]

impl FromCast<Simd<[u128; 4]>> for i64x4[src]

impl FromCast<Simd<[u128; 4]>> for i8x4[src]

impl FromCast<Simd<[u128; 4]>> for isizex4[src]

impl FromCast<Simd<[u128; 4]>> for m128x4[src]

impl FromCast<Simd<[u128; 4]>> for m16x4[src]

impl FromCast<Simd<[u128; 4]>> for m32x4[src]

impl FromCast<Simd<[u128; 4]>> for m64x4[src]

impl FromCast<Simd<[u128; 4]>> for m8x4[src]

impl FromCast<Simd<[u128; 4]>> for msizex4[src]

impl FromCast<Simd<[u128; 4]>> for u16x4[src]

impl FromCast<Simd<[u128; 4]>> for u32x4[src]

impl FromCast<Simd<[u128; 4]>> for u64x4[src]

impl FromCast<Simd<[u128; 4]>> for u8x4[src]

impl FromCast<Simd<[u128; 4]>> for usizex4[src]

impl FromCast<Simd<[u16; 16]>> for f32x16[src]

impl FromCast<Simd<[u16; 16]>> for i16x16[src]

impl FromCast<Simd<[u16; 16]>> for i32x16[src]

impl FromCast<Simd<[u16; 16]>> for i8x16[src]

impl FromCast<Simd<[u16; 16]>> for m16x16[src]

impl FromCast<Simd<[u16; 16]>> for m32x16[src]

impl FromCast<Simd<[u16; 16]>> for m8x16[src]

impl FromCast<Simd<[u16; 16]>> for u32x16[src]

impl FromCast<Simd<[u16; 16]>> for u8x16[src]

impl FromCast<Simd<[u16; 2]>> for f32x2[src]

impl FromCast<Simd<[u16; 2]>> for f64x2[src]

impl FromCast<Simd<[u16; 2]>> for i128x2[src]

impl FromCast<Simd<[u16; 2]>> for i16x2[src]

impl FromCast<Simd<[u16; 2]>> for i32x2[src]

impl FromCast<Simd<[u16; 2]>> for i64x2[src]

impl FromCast<Simd<[u16; 2]>> for i8x2[src]

impl FromCast<Simd<[u16; 2]>> for isizex2[src]

impl FromCast<Simd<[u16; 2]>> for m128x2[src]

impl FromCast<Simd<[u16; 2]>> for m16x2[src]

impl FromCast<Simd<[u16; 2]>> for m32x2[src]

impl FromCast<Simd<[u16; 2]>> for m64x2[src]

impl FromCast<Simd<[u16; 2]>> for m8x2[src]

impl FromCast<Simd<[u16; 2]>> for msizex2[src]

impl FromCast<Simd<[u16; 2]>> for u128x2[src]

impl FromCast<Simd<[u16; 2]>> for u32x2[src]

impl FromCast<Simd<[u16; 2]>> for u64x2[src]

impl FromCast<Simd<[u16; 2]>> for u8x2[src]

impl FromCast<Simd<[u16; 2]>> for usizex2[src]

impl FromCast<Simd<[u16; 32]>> for i16x32[src]

impl FromCast<Simd<[u16; 32]>> for i8x32[src]

impl FromCast<Simd<[u16; 32]>> for m16x32[src]

impl FromCast<Simd<[u16; 32]>> for m8x32[src]

impl FromCast<Simd<[u16; 32]>> for u8x32[src]

impl FromCast<Simd<[u16; 4]>> for f32x4[src]

impl FromCast<Simd<[u16; 4]>> for f64x4[src]

impl FromCast<Simd<[u16; 4]>> for i128x4[src]

impl FromCast<Simd<[u16; 4]>> for i16x4[src]

impl FromCast<Simd<[u16; 4]>> for i32x4[src]

impl FromCast<Simd<[u16; 4]>> for i64x4[src]

impl FromCast<Simd<[u16; 4]>> for i8x4[src]

impl FromCast<Simd<[u16; 4]>> for isizex4[src]

impl FromCast<Simd<[u16; 4]>> for m128x4[src]

impl FromCast<Simd<[u16; 4]>> for m16x4[src]

impl FromCast<Simd<[u16; 4]>> for m32x4[src]

impl FromCast<Simd<[u16; 4]>> for m64x4[src]

impl FromCast<Simd<[u16; 4]>> for m8x4[src]

impl FromCast<Simd<[u16; 4]>> for msizex4[src]

impl FromCast<Simd<[u16; 4]>> for u128x4[src]

impl FromCast<Simd<[u16; 4]>> for u32x4[src]

impl FromCast<Simd<[u16; 4]>> for u64x4[src]

impl FromCast<Simd<[u16; 4]>> for u8x4[src]

impl FromCast<Simd<[u16; 4]>> for usizex4[src]

impl FromCast<Simd<[u16; 8]>> for f32x8[src]

impl FromCast<Simd<[u16; 8]>> for f64x8[src]

impl FromCast<Simd<[u16; 8]>> for i16x8[src]

impl FromCast<Simd<[u16; 8]>> for i32x8[src]

impl FromCast<Simd<[u16; 8]>> for i64x8[src]

impl FromCast<Simd<[u16; 8]>> for i8x8[src]

impl FromCast<Simd<[u16; 8]>> for isizex8[src]

impl FromCast<Simd<[u16; 8]>> for m16x8[src]

impl FromCast<Simd<[u16; 8]>> for m32x8[src]

impl FromCast<Simd<[u16; 8]>> for m64x8[src]

impl FromCast<Simd<[u16; 8]>> for m8x8[src]

impl FromCast<Simd<[u16; 8]>> for msizex8[src]

impl FromCast<Simd<[u16; 8]>> for u32x8[src]

impl FromCast<Simd<[u16; 8]>> for u64x8[src]

impl FromCast<Simd<[u16; 8]>> for u8x8[src]

impl FromCast<Simd<[u16; 8]>> for usizex8[src]

impl FromCast<Simd<[u32; 16]>> for f32x16[src]

impl FromCast<Simd<[u32; 16]>> for i16x16[src]

impl FromCast<Simd<[u32; 16]>> for i32x16[src]

impl FromCast<Simd<[u32; 16]>> for i8x16[src]

impl FromCast<Simd<[u32; 16]>> for m16x16[src]

impl FromCast<Simd<[u32; 16]>> for m32x16[src]

impl FromCast<Simd<[u32; 16]>> for m8x16[src]

impl FromCast<Simd<[u32; 16]>> for u16x16[src]

impl FromCast<Simd<[u32; 16]>> for u8x16[src]

impl FromCast<Simd<[u32; 2]>> for f32x2[src]

impl FromCast<Simd<[u32; 2]>> for f64x2[src]

impl FromCast<Simd<[u32; 2]>> for i128x2[src]

impl FromCast<Simd<[u32; 2]>> for i16x2[src]

impl FromCast<Simd<[u32; 2]>> for i32x2[src]

impl FromCast<Simd<[u32; 2]>> for i64x2[src]

impl FromCast<Simd<[u32; 2]>> for i8x2[src]

impl FromCast<Simd<[u32; 2]>> for isizex2[src]

impl FromCast<Simd<[u32; 2]>> for m128x2[src]

impl FromCast<Simd<[u32; 2]>> for m16x2[src]

impl FromCast<Simd<[u32; 2]>> for m32x2[src]

impl FromCast<Simd<[u32; 2]>> for m64x2[src]

impl FromCast<Simd<[u32; 2]>> for m8x2[src]

impl FromCast<Simd<[u32; 2]>> for msizex2[src]

impl FromCast<Simd<[u32; 2]>> for u128x2[src]

impl FromCast<Simd<[u32; 2]>> for u16x2[src]

impl FromCast<Simd<[u32; 2]>> for u64x2[src]

impl FromCast<Simd<[u32; 2]>> for u8x2[src]

impl FromCast<Simd<[u32; 2]>> for usizex2[src]

impl FromCast<Simd<[u32; 4]>> for f32x4[src]

impl FromCast<Simd<[u32; 4]>> for f64x4[src]

impl FromCast<Simd<[u32; 4]>> for i128x4[src]

impl FromCast<Simd<[u32; 4]>> for i16x4[src]

impl FromCast<Simd<[u32; 4]>> for i32x4[src]

impl FromCast<Simd<[u32; 4]>> for i64x4[src]

impl FromCast<Simd<[u32; 4]>> for i8x4[src]

impl FromCast<Simd<[u32; 4]>> for isizex4[src]

impl FromCast<Simd<[u32; 4]>> for m128x4[src]

impl FromCast<Simd<[u32; 4]>> for m16x4[src]

impl FromCast<Simd<[u32; 4]>> for m32x4[src]

impl FromCast<Simd<[u32; 4]>> for m64x4[src]

impl FromCast<Simd<[u32; 4]>> for m8x4[src]

impl FromCast<Simd<[u32; 4]>> for msizex4[src]

impl FromCast<Simd<[u32; 4]>> for u128x4[src]

impl FromCast<Simd<[u32; 4]>> for u16x4[src]

impl FromCast<Simd<[u32; 4]>> for u64x4[src]

impl FromCast<Simd<[u32; 4]>> for u8x4[src]

impl FromCast<Simd<[u32; 4]>> for usizex4[src]

impl FromCast<Simd<[u32; 8]>> for f32x8[src]

impl FromCast<Simd<[u32; 8]>> for f64x8[src]

impl FromCast<Simd<[u32; 8]>> for i16x8[src]

impl FromCast<Simd<[u32; 8]>> for i32x8[src]

impl FromCast<Simd<[u32; 8]>> for i64x8[src]

impl FromCast<Simd<[u32; 8]>> for i8x8[src]

impl FromCast<Simd<[u32; 8]>> for isizex8[src]

impl FromCast<Simd<[u32; 8]>> for m16x8[src]

impl FromCast<Simd<[u32; 8]>> for m32x8[src]

impl FromCast<Simd<[u32; 8]>> for m64x8[src]

impl FromCast<Simd<[u32; 8]>> for m8x8[src]

impl FromCast<Simd<[u32; 8]>> for msizex8[src]

impl FromCast<Simd<[u32; 8]>> for u16x8[src]

impl FromCast<Simd<[u32; 8]>> for u64x8[src]

impl FromCast<Simd<[u32; 8]>> for u8x8[src]

impl FromCast<Simd<[u32; 8]>> for usizex8[src]

impl FromCast<Simd<[u64; 2]>> for f32x2[src]

impl FromCast<Simd<[u64; 2]>> for f64x2[src]

impl FromCast<Simd<[u64; 2]>> for i128x2[src]

impl FromCast<Simd<[u64; 2]>> for i16x2[src]

impl FromCast<Simd<[u64; 2]>> for i32x2[src]

impl FromCast<Simd<[u64; 2]>> for i64x2[src]

impl FromCast<Simd<[u64; 2]>> for i8x2[src]

impl FromCast<Simd<[u64; 2]>> for isizex2[src]

impl FromCast<Simd<[u64; 2]>> for m128x2[src]

impl FromCast<Simd<[u64; 2]>> for m16x2[src]

impl FromCast<Simd<[u64; 2]>> for m32x2[src]

impl FromCast<Simd<[u64; 2]>> for m64x2[src]

impl FromCast<Simd<[u64; 2]>> for m8x2[src]

impl FromCast<Simd<[u64; 2]>> for msizex2[src]

impl FromCast<Simd<[u64; 2]>> for u128x2[src]

impl FromCast<Simd<[u64; 2]>> for u16x2[src]

impl FromCast<Simd<[u64; 2]>> for u32x2[src]

impl FromCast<Simd<[u64; 2]>> for u8x2[src]

impl FromCast<Simd<[u64; 2]>> for usizex2[src]

impl FromCast<Simd<[u64; 4]>> for f32x4[src]

impl FromCast<Simd<[u64; 4]>> for f64x4[src]

impl FromCast<Simd<[u64; 4]>> for i128x4[src]

impl FromCast<Simd<[u64; 4]>> for i16x4[src]

impl FromCast<Simd<[u64; 4]>> for i32x4[src]

impl FromCast<Simd<[u64; 4]>> for i64x4[src]

impl FromCast<Simd<[u64; 4]>> for i8x4[src]

impl FromCast<Simd<[u64; 4]>> for isizex4[src]

impl FromCast<Simd<[u64; 4]>> for m128x4[src]

impl FromCast<Simd<[u64; 4]>> for m16x4[src]

impl FromCast<Simd<[u64; 4]>> for m32x4[src]

impl FromCast<Simd<[u64; 4]>> for m64x4[src]

impl FromCast<Simd<[u64; 4]>> for m8x4[src]

impl FromCast<Simd<[u64; 4]>> for msizex4[src]

impl FromCast<Simd<[u64; 4]>> for u128x4[src]

impl FromCast<Simd<[u64; 4]>> for u16x4[src]

impl FromCast<Simd<[u64; 4]>> for u32x4[src]

impl FromCast<Simd<[u64; 4]>> for u8x4[src]

impl FromCast<Simd<[u64; 4]>> for usizex4[src]

impl FromCast<Simd<[u64; 8]>> for f32x8[src]

impl FromCast<Simd<[u64; 8]>> for f64x8[src]

impl FromCast<Simd<[u64; 8]>> for i16x8[src]

impl FromCast<Simd<[u64; 8]>> for i32x8[src]

impl FromCast<Simd<[u64; 8]>> for i64x8[src]

impl FromCast<Simd<[u64; 8]>> for i8x8[src]

impl FromCast<Simd<[u64; 8]>> for isizex8[src]

impl FromCast<Simd<[u64; 8]>> for m16x8[src]

impl FromCast<Simd<[u64; 8]>> for m32x8[src]

impl FromCast<Simd<[u64; 8]>> for m64x8[src]

impl FromCast<Simd<[u64; 8]>> for m8x8[src]

impl FromCast<Simd<[u64; 8]>> for msizex8[src]

impl FromCast<Simd<[u64; 8]>> for u16x8[src]

impl FromCast<Simd<[u64; 8]>> for u32x8[src]

impl FromCast<Simd<[u64; 8]>> for u8x8[src]

impl FromCast<Simd<[u64; 8]>> for usizex8[src]

impl FromCast<Simd<[u8; 16]>> for f32x16[src]

impl FromCast<Simd<[u8; 16]>> for i16x16[src]

impl FromCast<Simd<[u8; 16]>> for i32x16[src]

impl FromCast<Simd<[u8; 16]>> for i8x16[src]

impl FromCast<Simd<[u8; 16]>> for m16x16[src]

impl FromCast<Simd<[u8; 16]>> for m32x16[src]

impl FromCast<Simd<[u8; 16]>> for m8x16[src]

impl FromCast<Simd<[u8; 16]>> for u16x16[src]

impl FromCast<Simd<[u8; 16]>> for u32x16[src]

impl FromCast<Simd<[u8; 2]>> for f32x2[src]

impl FromCast<Simd<[u8; 2]>> for f64x2[src]

impl FromCast<Simd<[u8; 2]>> for i128x2[src]

impl FromCast<Simd<[u8; 2]>> for i16x2[src]

impl FromCast<Simd<[u8; 2]>> for i32x2[src]

impl FromCast<Simd<[u8; 2]>> for i64x2[src]

impl FromCast<Simd<[u8; 2]>> for i8x2[src]

impl FromCast<Simd<[u8; 2]>> for isizex2[src]

impl FromCast<Simd<[u8; 2]>> for m128x2[src]

impl FromCast<Simd<[u8; 2]>> for m16x2[src]

impl FromCast<Simd<[u8; 2]>> for m32x2[src]

impl FromCast<Simd<[u8; 2]>> for m64x2[src]

impl FromCast<Simd<[u8; 2]>> for m8x2[src]

impl FromCast<Simd<[u8; 2]>> for msizex2[src]

impl FromCast<Simd<[u8; 2]>> for u128x2[src]

impl FromCast<Simd<[u8; 2]>> for u16x2[src]

impl FromCast<Simd<[u8; 2]>> for u32x2[src]

impl FromCast<Simd<[u8; 2]>> for u64x2[src]

impl FromCast<Simd<[u8; 2]>> for usizex2[src]

impl FromCast<Simd<[u8; 32]>> for i16x32[src]

impl FromCast<Simd<[u8; 32]>> for i8x32[src]

impl FromCast<Simd<[u8; 32]>> for m16x32[src]

impl FromCast<Simd<[u8; 32]>> for m8x32[src]

impl FromCast<Simd<[u8; 32]>> for u16x32[src]

impl FromCast<Simd<[u8; 4]>> for f32x4[src]

impl FromCast<Simd<[u8; 4]>> for f64x4[src]

impl FromCast<Simd<[u8; 4]>> for i128x4[src]

impl FromCast<Simd<[u8; 4]>> for i16x4[src]

impl FromCast<Simd<[u8; 4]>> for i32x4[src]

impl FromCast<Simd<[u8; 4]>> for i64x4[src]

impl FromCast<Simd<[u8; 4]>> for i8x4[src]

impl FromCast<Simd<[u8; 4]>> for isizex4[src]

impl FromCast<Simd<[u8; 4]>> for m128x4[src]

impl FromCast<Simd<[u8; 4]>> for m16x4[src]

impl FromCast<Simd<[u8; 4]>> for m32x4[src]

impl FromCast<Simd<[u8; 4]>> for m64x4[src]

impl FromCast<Simd<[u8; 4]>> for m8x4[src]

impl FromCast<Simd<[u8; 4]>> for msizex4[src]

impl FromCast<Simd<[u8; 4]>> for u128x4[src]

impl FromCast<Simd<[u8; 4]>> for u16x4[src]

impl FromCast<Simd<[u8; 4]>> for u32x4[src]

impl FromCast<Simd<[u8; 4]>> for u64x4[src]

impl FromCast<Simd<[u8; 4]>> for usizex4[src]

impl FromCast<Simd<[u8; 64]>> for i8x64[src]

impl FromCast<Simd<[u8; 64]>> for m8x64[src]

impl FromCast<Simd<[u8; 8]>> for f32x8[src]

impl FromCast<Simd<[u8; 8]>> for f64x8[src]

impl FromCast<Simd<[u8; 8]>> for i16x8[src]

impl FromCast<Simd<[u8; 8]>> for i32x8[src]

impl FromCast<Simd<[u8; 8]>> for i64x8[src]

impl FromCast<Simd<[u8; 8]>> for i8x8[src]

impl FromCast<Simd<[u8; 8]>> for isizex8[src]

impl FromCast<Simd<[u8; 8]>> for m16x8[src]

impl FromCast<Simd<[u8; 8]>> for m32x8[src]

impl FromCast<Simd<[u8; 8]>> for m64x8[src]

impl FromCast<Simd<[u8; 8]>> for m8x8[src]

impl FromCast<Simd<[u8; 8]>> for msizex8[src]

impl FromCast<Simd<[u8; 8]>> for u16x8[src]

impl FromCast<Simd<[u8; 8]>> for u32x8[src]

impl FromCast<Simd<[u8; 8]>> for u64x8[src]

impl FromCast<Simd<[u8; 8]>> for usizex8[src]

impl FromCast<Simd<[usize; 2]>> for f32x2[src]

impl FromCast<Simd<[usize; 2]>> for f64x2[src]

impl FromCast<Simd<[usize; 2]>> for i128x2[src]

impl FromCast<Simd<[usize; 2]>> for i16x2[src]

impl FromCast<Simd<[usize; 2]>> for i32x2[src]

impl FromCast<Simd<[usize; 2]>> for i64x2[src]

impl FromCast<Simd<[usize; 2]>> for i8x2[src]

impl FromCast<Simd<[usize; 2]>> for isizex2[src]

impl FromCast<Simd<[usize; 2]>> for m128x2[src]

impl FromCast<Simd<[usize; 2]>> for m16x2[src]

impl FromCast<Simd<[usize; 2]>> for m32x2[src]

impl FromCast<Simd<[usize; 2]>> for m64x2[src]

impl FromCast<Simd<[usize; 2]>> for m8x2[src]

impl FromCast<Simd<[usize; 2]>> for msizex2[src]

impl FromCast<Simd<[usize; 2]>> for u128x2[src]

impl FromCast<Simd<[usize; 2]>> for u16x2[src]

impl FromCast<Simd<[usize; 2]>> for u32x2[src]

impl FromCast<Simd<[usize; 2]>> for u64x2[src]

impl FromCast<Simd<[usize; 2]>> for u8x2[src]

impl FromCast<Simd<[usize; 4]>> for f32x4[src]

impl FromCast<Simd<[usize; 4]>> for f64x4[src]

impl FromCast<Simd<[usize; 4]>> for i128x4[src]

impl FromCast<Simd<[usize; 4]>> for i16x4[src]

impl FromCast<Simd<[usize; 4]>> for i32x4[src]

impl FromCast<Simd<[usize; 4]>> for i64x4[src]

impl FromCast<Simd<[usize; 4]>> for i8x4[src]

impl FromCast<Simd<[usize; 4]>> for isizex4[src]

impl FromCast<Simd<[usize; 4]>> for m128x4[src]

impl FromCast<Simd<[usize; 4]>> for m16x4[src]

impl FromCast<Simd<[usize; 4]>> for m32x4[src]

impl FromCast<Simd<[usize; 4]>> for m64x4[src]

impl FromCast<Simd<[usize; 4]>> for m8x4[src]

impl FromCast<Simd<[usize; 4]>> for msizex4[src]

impl FromCast<Simd<[usize; 4]>> for u128x4[src]

impl FromCast<Simd<[usize; 4]>> for u16x4[src]

impl FromCast<Simd<[usize; 4]>> for u32x4[src]

impl FromCast<Simd<[usize; 4]>> for u64x4[src]

impl FromCast<Simd<[usize; 4]>> for u8x4[src]

impl FromCast<Simd<[usize; 8]>> for f32x8[src]

impl FromCast<Simd<[usize; 8]>> for f64x8[src]

impl FromCast<Simd<[usize; 8]>> for i16x8[src]

impl FromCast<Simd<[usize; 8]>> for i32x8[src]

impl FromCast<Simd<[usize; 8]>> for i64x8[src]

impl FromCast<Simd<[usize; 8]>> for i8x8[src]

impl FromCast<Simd<[usize; 8]>> for isizex8[src]

impl FromCast<Simd<[usize; 8]>> for m16x8[src]

impl FromCast<Simd<[usize; 8]>> for m32x8[src]

impl FromCast<Simd<[usize; 8]>> for m64x8[src]

impl FromCast<Simd<[usize; 8]>> for m8x8[src]

impl FromCast<Simd<[usize; 8]>> for msizex8[src]

impl FromCast<Simd<[usize; 8]>> for u16x8[src]

impl FromCast<Simd<[usize; 8]>> for u32x8[src]

impl FromCast<Simd<[usize; 8]>> for u64x8[src]

impl FromCast<Simd<[usize; 8]>> for u8x8[src]

impl<T> FromCast<T> for T[src]

FromCast and Cast are reflexive

+
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\ No newline at end of file diff --git a/packed_simd/trait.IntoBits.html b/packed_simd/trait.IntoBits.html new file mode 100644 index 000000000..f966a1726 --- /dev/null +++ b/packed_simd/trait.IntoBits.html @@ -0,0 +1,8 @@ +packed_simd::IntoBits - Rust

[−][src]Trait packed_simd::IntoBits

pub trait IntoBits<T>: Sized {
+    fn into_bits(self) -> T;
+}

Safe lossless bitwise conversion from Self to T.

+
+

Required methods

fn into_bits(self) -> T

Safe lossless bitwise transmute from self to T.

+
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Implementors

impl<T, U> IntoBits<U> for T where
    U: FromBits<T>, [src]

FromBits implies IntoBits.

+
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\ No newline at end of file diff --git a/packed_simd/trait.Mask.html b/packed_simd/trait.Mask.html new file mode 100644 index 000000000..b6e4f4835 --- /dev/null +++ b/packed_simd/trait.Mask.html @@ -0,0 +1,6 @@ +packed_simd::Mask - Rust

[−][src]Trait packed_simd::Mask

pub trait Mask: Seal {
+    fn test(&self) -> bool;
+}

This trait is implemented by all mask types

+
+

Required methods

fn test(&self) -> bool

Loading content... +

Implementors

impl Mask for m128[src]

impl Mask for m16[src]

impl Mask for m32[src]

impl Mask for m64[src]

impl Mask for m8[src]

impl Mask for msize[src]

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\ No newline at end of file diff --git a/packed_simd/trait.SimdArray.html b/packed_simd/trait.SimdArray.html new file mode 100644 index 000000000..643ebf99b --- /dev/null +++ b/packed_simd/trait.SimdArray.html @@ -0,0 +1,15 @@ +packed_simd::SimdArray - Rust

[−][src]Trait packed_simd::SimdArray

pub trait SimdArray: Seal {
+    type Tuple: Copy + Clone;
+    type T;
+    type NT;
+
+    const N: usize;
+}

Trait implemented by arrays that can be SIMD types.

+
+

Associated Types

type Tuple: Copy + Clone

The type of the #[repr(simd)] type.

+

type T

The element type of the vector.

+

type NT

The type: [u32; Self::N].

+
Loading content... +

Associated Constants

const N: usize

The number of elements in the array.

+
Loading content... +

Implementors

impl SimdArray for [m128; 1][src]

type Tuple = m128x1

type T = m128

type NT = [u32; 1]

impl SimdArray for [m128; 2][src]

type Tuple = m128x2

type T = m128

type NT = [u32; 2]

impl SimdArray for [m128; 4][src]

type Tuple = m128x4

type T = m128

type NT = [u32; 4]

impl SimdArray for [m16; 2][src]

type Tuple = m16x2

type T = m16

type NT = [u32; 2]

impl SimdArray for [m16; 4][src]

type Tuple = m16x4

type T = m16

type NT = [u32; 4]

impl SimdArray for [m16; 8][src]

type Tuple = m16x8

type T = m16

type NT = [u32; 8]

impl SimdArray for [m16; 16][src]

type Tuple = m16x16

type T = m16

type NT = [u32; 16]

impl SimdArray for [m16; 32][src]

type Tuple = m16x32

type T = m16

type NT = [u32; 32]

impl SimdArray for [m32; 2][src]

type Tuple = m32x2

type T = m32

type NT = [u32; 2]

impl SimdArray for [m32; 4][src]

type Tuple = m32x4

type T = m32

type NT = [u32; 4]

impl SimdArray for [m32; 8][src]

type Tuple = m32x8

type T = m32

type NT = [u32; 8]

impl SimdArray for [m32; 16][src]

type Tuple = m32x16

type T = m32

type NT = [u32; 16]

impl SimdArray for [m64; 1][src]

type Tuple = m64x1

type T = m64

type NT = [u32; 1]

impl SimdArray for [m64; 2][src]

type Tuple = m64x2

type T = m64

type NT = [u32; 2]

impl SimdArray for [m64; 4][src]

type Tuple = m64x4

type T = m64

type NT = [u32; 4]

impl SimdArray for [m64; 8][src]

type Tuple = m64x8

type T = m64

type NT = [u32; 8]

impl SimdArray for [m8; 2][src]

type Tuple = m8x2

type T = m8

type NT = [u32; 2]

impl SimdArray for [m8; 4][src]

type Tuple = m8x4

type T = m8

type NT = [u32; 4]

impl SimdArray for [m8; 8][src]

type Tuple = m8x8

type T = m8

type NT = [u32; 8]

impl SimdArray for [m8; 16][src]

type Tuple = m8x16

type T = m8

type NT = [u32; 16]

impl SimdArray for [m8; 32][src]

type Tuple = m8x32

type T = m8

type NT = [u32; 32]

impl SimdArray for [m8; 64][src]

type Tuple = m8x64

type T = m8

type NT = [u32; 64]

impl SimdArray for [msize; 2][src]

type Tuple = msizex2

type T = msize

type NT = [u32; 2]

impl SimdArray for [msize; 4][src]

type Tuple = msizex4

type T = msize

type NT = [u32; 4]

impl SimdArray for [msize; 8][src]

type Tuple = msizex8

type T = msize

type NT = [u32; 8]

impl SimdArray for [f32; 2][src]

type Tuple = f32x2

type T = f32

type NT = [u32; 2]

impl SimdArray for [f32; 4][src]

type Tuple = f32x4

type T = f32

type NT = [u32; 4]

impl SimdArray for [f32; 8][src]

type Tuple = f32x8

type T = f32

type NT = [u32; 8]

impl SimdArray for [f32; 16][src]

type Tuple = f32x16

type T = f32

type NT = [u32; 16]

impl SimdArray for [f64; 1][src]

type Tuple = f64x1

type T = f64

type NT = [u32; 1]

impl SimdArray for [f64; 2][src]

type Tuple = f64x2

type T = f64

type NT = [u32; 2]

impl SimdArray for [f64; 4][src]

type Tuple = f64x4

type T = f64

type NT = [u32; 4]

impl SimdArray for [f64; 8][src]

type Tuple = f64x8

type T = f64

type NT = [u32; 8]

impl SimdArray for [i128; 1][src]

type Tuple = i128x1

type T = i128

type NT = [u32; 1]

impl SimdArray for [i128; 2][src]

type Tuple = i128x2

type T = i128

type NT = [u32; 2]

impl SimdArray for [i128; 4][src]

type Tuple = i128x4

type T = i128

type NT = [u32; 4]

impl SimdArray for [i16; 2][src]

type Tuple = i16x2

type T = i16

type NT = [u32; 2]

impl SimdArray for [i16; 4][src]

type Tuple = i16x4

type T = i16

type NT = [u32; 4]

impl SimdArray for [i16; 8][src]

type Tuple = i16x8

type T = i16

type NT = [u32; 8]

impl SimdArray for [i16; 16][src]

type Tuple = i16x16

type T = i16

type NT = [u32; 16]

impl SimdArray for [i16; 32][src]

type Tuple = i16x32

type T = i16

type NT = [u32; 32]

impl SimdArray for [i32; 2][src]

type Tuple = i32x2

type T = i32

type NT = [u32; 2]

impl SimdArray for [i32; 4][src]

type Tuple = i32x4

type T = i32

type NT = [u32; 4]

impl SimdArray for [i32; 8][src]

type Tuple = i32x8

type T = i32

type NT = [u32; 8]

impl SimdArray for [i32; 16][src]

type Tuple = i32x16

type T = i32

type NT = [u32; 16]

impl SimdArray for [i64; 1][src]

type Tuple = i64x1

type T = i64

type NT = [u32; 1]

impl SimdArray for [i64; 2][src]

type Tuple = i64x2

type T = i64

type NT = [u32; 2]

impl SimdArray for [i64; 4][src]

type Tuple = i64x4

type T = i64

type NT = [u32; 4]

impl SimdArray for [i64; 8][src]

type Tuple = i64x8

type T = i64

type NT = [u32; 8]

impl SimdArray for [i8; 2][src]

type Tuple = i8x2

type T = i8

type NT = [u32; 2]

impl SimdArray for [i8; 4][src]

type Tuple = i8x4

type T = i8

type NT = [u32; 4]

impl SimdArray for [i8; 8][src]

type Tuple = i8x8

type T = i8

type NT = [u32; 8]

impl SimdArray for [i8; 16][src]

type Tuple = i8x16

type T = i8

type NT = [u32; 16]

impl SimdArray for [i8; 32][src]

type Tuple = i8x32

type T = i8

type NT = [u32; 32]

impl SimdArray for [i8; 64][src]

type Tuple = i8x64

type T = i8

type NT = [u32; 64]

impl SimdArray for [isize; 2][src]

type Tuple = isizex2

type T = isize

type NT = [u32; 2]

impl SimdArray for [isize; 4][src]

type Tuple = isizex4

type T = isize

type NT = [u32; 4]

impl SimdArray for [isize; 8][src]

type Tuple = isizex8

type T = isize

type NT = [u32; 8]

impl SimdArray for [u128; 1][src]

type Tuple = u128x1

type T = u128

type NT = [u32; 1]

impl SimdArray for [u128; 2][src]

type Tuple = u128x2

type T = u128

type NT = [u32; 2]

impl SimdArray for [u128; 4][src]

type Tuple = u128x4

type T = u128

type NT = [u32; 4]

impl SimdArray for [u16; 2][src]

type Tuple = u16x2

type T = u16

type NT = [u32; 2]

impl SimdArray for [u16; 4][src]

type Tuple = u16x4

type T = u16

type NT = [u32; 4]

impl SimdArray for [u16; 8][src]

type Tuple = u16x8

type T = u16

type NT = [u32; 8]

impl SimdArray for [u16; 16][src]

type Tuple = u16x16

type T = u16

type NT = [u32; 16]

impl SimdArray for [u16; 32][src]

type Tuple = u16x32

type T = u16

type NT = [u32; 32]

impl SimdArray for [u32; 2][src]

type Tuple = u32x2

type T = u32

type NT = [u32; 2]

impl SimdArray for [u32; 4][src]

type Tuple = u32x4

type T = u32

type NT = [u32; 4]

impl SimdArray for [u32; 8][src]

type Tuple = u32x8

type T = u32

type NT = [u32; 8]

impl SimdArray for [u32; 16][src]

type Tuple = u32x16

type T = u32

type NT = [u32; 16]

impl SimdArray for [u64; 1][src]

type Tuple = u64x1

type T = u64

type NT = [u32; 1]

impl SimdArray for [u64; 2][src]

type Tuple = u64x2

type T = u64

type NT = [u32; 2]

impl SimdArray for [u64; 4][src]

type Tuple = u64x4

type T = u64

type NT = [u32; 4]

impl SimdArray for [u64; 8][src]

type Tuple = u64x8

type T = u64

type NT = [u32; 8]

impl SimdArray for [u8; 2][src]

type Tuple = u8x2

type T = u8

type NT = [u32; 2]

impl SimdArray for [u8; 4][src]

type Tuple = u8x4

type T = u8

type NT = [u32; 4]

impl SimdArray for [u8; 8][src]

type Tuple = u8x8

type T = u8

type NT = [u32; 8]

impl SimdArray for [u8; 16][src]

type Tuple = u8x16

type T = u8

type NT = [u32; 16]

impl SimdArray for [u8; 32][src]

type Tuple = u8x32

type T = u8

type NT = [u32; 32]

impl SimdArray for [u8; 64][src]

type Tuple = u8x64

type T = u8

type NT = [u32; 64]

impl SimdArray for [usize; 2][src]

type Tuple = usizex2

type T = usize

type NT = [u32; 2]

impl SimdArray for [usize; 4][src]

type Tuple = usizex4

type T = usize

type NT = [u32; 4]

impl SimdArray for [usize; 8][src]

type Tuple = usizex8

type T = usize

type NT = [u32; 8]

impl<T> SimdArray for [*const T; 2][src]

type Tuple = cptrx2<*const T>

type T = *const T

type NT = [u32; 2]

impl<T> SimdArray for [*const T; 4][src]

type Tuple = cptrx4<*const T>

type T = *const T

type NT = [u32; 4]

impl<T> SimdArray for [*const T; 8][src]

type Tuple = cptrx8<*const T>

type T = *const T

type NT = [u32; 8]

impl<T> SimdArray for [*mut T; 2][src]

type Tuple = mptrx2<*mut T>

type T = *mut T

type NT = [u32; 2]

impl<T> SimdArray for [*mut T; 4][src]

type Tuple = mptrx4<*mut T>

type T = *mut T

type NT = [u32; 4]

impl<T> SimdArray for [*mut T; 8][src]

type Tuple = mptrx8<*mut T>

type T = *mut T

type NT = [u32; 8]

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\ No newline at end of file diff --git a/packed_simd/trait.SimdVector.html b/packed_simd/trait.SimdVector.html new file mode 100644 index 000000000..1d9af5beb --- /dev/null +++ b/packed_simd/trait.SimdVector.html @@ -0,0 +1,13 @@ +packed_simd::SimdVector - Rust

[−][src]Trait packed_simd::SimdVector

pub trait SimdVector: Seal {
+    type Element;
+    type LanesType;
+
+    const LANES: usize;
+}

This trait is implemented by all SIMD vector types.

+
+

Associated Types

type Element

Element type of the SIMD vector

+

type LanesType

The type: [u32; Self::N].

+
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Associated Constants

const LANES: usize

The number of elements in the SIMD vector.

+
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Implementors

impl Simd for f32x16[src]

type Element = f32

type LanesType = [u32; 16]

impl Simd for f32x2[src]

type Element = f32

type LanesType = [u32; 2]

impl Simd for f32x4[src]

type Element = f32

type LanesType = [u32; 4]

impl Simd for f32x8[src]

type Element = f32

type LanesType = [u32; 8]

impl Simd for f64x2[src]

type Element = f64

type LanesType = [u32; 2]

impl Simd for f64x4[src]

type Element = f64

type LanesType = [u32; 4]

impl Simd for f64x8[src]

type Element = f64

type LanesType = [u32; 8]

impl Simd for i128x1[src]

type Element = i128

type LanesType = [u32; 1]

impl Simd for i128x2[src]

type Element = i128

type LanesType = [u32; 2]

impl Simd for i128x4[src]

type Element = i128

type LanesType = [u32; 4]

impl Simd for i16x16[src]

type Element = i16

type LanesType = [u32; 16]

impl Simd for i16x2[src]

type Element = i16

type LanesType = [u32; 2]

impl Simd for i16x32[src]

type Element = i16

type LanesType = [u32; 32]

impl Simd for i16x4[src]

type Element = i16

type LanesType = [u32; 4]

impl Simd for i16x8[src]

type Element = i16

type LanesType = [u32; 8]

impl Simd for i32x16[src]

type Element = i32

type LanesType = [u32; 16]

impl Simd for i32x2[src]

type Element = i32

type LanesType = [u32; 2]

impl Simd for i32x4[src]

type Element = i32

type LanesType = [u32; 4]

impl Simd for i32x8[src]

type Element = i32

type LanesType = [u32; 8]

impl Simd for i64x2[src]

type Element = i64

type LanesType = [u32; 2]

impl Simd for i64x4[src]

type Element = i64

type LanesType = [u32; 4]

impl Simd for i64x8[src]

type Element = i64

type LanesType = [u32; 8]

impl Simd for i8x16[src]

type Element = i8

type LanesType = [u32; 16]

impl Simd for i8x2[src]

type Element = i8

type LanesType = [u32; 2]

impl Simd for i8x32[src]

type Element = i8

type LanesType = [u32; 32]

impl Simd for i8x4[src]

type Element = i8

type LanesType = [u32; 4]

impl Simd for i8x64[src]

type Element = i8

type LanesType = [u32; 64]

impl Simd for i8x8[src]

type Element = i8

type LanesType = [u32; 8]

impl Simd for isizex2[src]

type Element = isize

type LanesType = [u32; 2]

impl Simd for isizex4[src]

type Element = isize

type LanesType = [u32; 4]

impl Simd for isizex8[src]

type Element = isize

type LanesType = [u32; 8]

impl Simd for m128x1[src]

type Element = m128

type LanesType = [u32; 1]

impl Simd for m128x2[src]

type Element = m128

type LanesType = [u32; 2]

impl Simd for m128x4[src]

type Element = m128

type LanesType = [u32; 4]

impl Simd for m16x16[src]

type Element = m16

type LanesType = [u32; 16]

impl Simd for m16x2[src]

type Element = m16

type LanesType = [u32; 2]

impl Simd for m16x32[src]

type Element = m16

type LanesType = [u32; 32]

impl Simd for m16x4[src]

type Element = m16

type LanesType = [u32; 4]

impl Simd for m16x8[src]

type Element = m16

type LanesType = [u32; 8]

impl Simd for m32x16[src]

type Element = m32

type LanesType = [u32; 16]

impl Simd for m32x2[src]

type Element = m32

type LanesType = [u32; 2]

impl Simd for m32x4[src]

type Element = m32

type LanesType = [u32; 4]

impl Simd for m32x8[src]

type Element = m32

type LanesType = [u32; 8]

impl Simd for m64x2[src]

type Element = m64

type LanesType = [u32; 2]

impl Simd for m64x4[src]

type Element = m64

type LanesType = [u32; 4]

impl Simd for m64x8[src]

type Element = m64

type LanesType = [u32; 8]

impl Simd for m8x16[src]

type Element = m8

type LanesType = [u32; 16]

impl Simd for m8x2[src]

type Element = m8

type LanesType = [u32; 2]

impl Simd for m8x32[src]

type Element = m8

type LanesType = [u32; 32]

impl Simd for m8x4[src]

type Element = m8

type LanesType = [u32; 4]

impl Simd for m8x64[src]

type Element = m8

type LanesType = [u32; 64]

impl Simd for m8x8[src]

type Element = m8

type LanesType = [u32; 8]

impl Simd for msizex2[src]

type Element = msize

type LanesType = [u32; 2]

impl Simd for msizex4[src]

type Element = msize

type LanesType = [u32; 4]

impl Simd for msizex8[src]

type Element = msize

type LanesType = [u32; 8]

impl Simd for u128x1[src]

type Element = u128

type LanesType = [u32; 1]

impl Simd for u128x2[src]

type Element = u128

type LanesType = [u32; 2]

impl Simd for u128x4[src]

type Element = u128

type LanesType = [u32; 4]

impl Simd for u16x16[src]

type Element = u16

type LanesType = [u32; 16]

impl Simd for u16x2[src]

type Element = u16

type LanesType = [u32; 2]

impl Simd for u16x32[src]

type Element = u16

type LanesType = [u32; 32]

impl Simd for u16x4[src]

type Element = u16

type LanesType = [u32; 4]

impl Simd for u16x8[src]

type Element = u16

type LanesType = [u32; 8]

impl Simd for u32x16[src]

type Element = u32

type LanesType = [u32; 16]

impl Simd for u32x2[src]

type Element = u32

type LanesType = [u32; 2]

impl Simd for u32x4[src]

type Element = u32

type LanesType = [u32; 4]

impl Simd for u32x8[src]

type Element = u32

type LanesType = [u32; 8]

impl Simd for u64x2[src]

type Element = u64

type LanesType = [u32; 2]

impl Simd for u64x4[src]

type Element = u64

type LanesType = [u32; 4]

impl Simd for u64x8[src]

type Element = u64

type LanesType = [u32; 8]

impl Simd for u8x16[src]

type Element = u8

type LanesType = [u32; 16]

impl Simd for u8x2[src]

type Element = u8

type LanesType = [u32; 2]

impl Simd for u8x32[src]

type Element = u8

type LanesType = [u32; 32]

impl Simd for u8x4[src]

type Element = u8

type LanesType = [u32; 4]

impl Simd for u8x64[src]

type Element = u8

type LanesType = [u32; 64]

impl Simd for u8x8[src]

type Element = u8

type LanesType = [u32; 8]

impl Simd for usizex2[src]

type Element = usize

type LanesType = [u32; 2]

impl Simd for usizex4[src]

type Element = usize

type LanesType = [u32; 4]

impl Simd for usizex8[src]

type Element = usize

type LanesType = [u32; 8]

impl<T> Simd for cptrx2<T>[src]

type Element = *const T

type LanesType = [u32; 2]

impl<T> Simd for cptrx4<T>[src]

type Element = *const T

type LanesType = [u32; 4]

impl<T> Simd for cptrx8<T>[src]

type Element = *const T

type LanesType = [u32; 8]

impl<T> Simd for mptrx2<T>[src]

type Element = *mut T

type LanesType = [u32; 2]

impl<T> Simd for mptrx4<T>[src]

type Element = *mut T

type LanesType = [u32; 4]

impl<T> Simd for mptrx8<T>[src]

type Element = *mut T

type LanesType = [u32; 8]

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\ No newline at end of file diff --git a/packed_simd/type.cptrx2.html b/packed_simd/type.cptrx2.html new file mode 100644 index 000000000..a95b6d421 --- /dev/null +++ b/packed_simd/type.cptrx2.html @@ -0,0 +1,274 @@ +packed_simd::cptrx2 - Rust

[−][src]Type Definition packed_simd::cptrx2

type cptrx2<T> = Simd<[*const T; 2]>;

A vector with 2 *const T lanes

+

Implementations

impl<T> cptrx2<T>[src]

pub const fn new(x0: *const T, x1: *const T) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: *const T) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub const fn null() -> Self[src]

Constructs a new instance with each element initialized to +null.

+

pub fn is_null(self) -> msizex2[src]

Returns a mask that selects those lanes that contain null +pointers.

+

pub fn extract(self, index: usize) -> *const T[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> *const T[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: *const T) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: *const T) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl<T> cptrx2<T>[src]

pub fn eq(self, other: Self) -> msizex2[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> msizex2[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> msizex2[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> msizex2[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> msizex2[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> msizex2[src]

Lane-wise greater-than-or-equals comparison.

+

impl<T> cptrx2<T>[src]

pub fn from_slice_aligned(slice: &[*const T]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[*const T]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[*const T]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[*const T]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl<T> cptrx2<T>[src]

pub fn write_to_slice_aligned(self, slice: &mut [*const T])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [*const T])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [*const T])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [*const T])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl<T> cptrx2<T>[src]

pub unsafe fn offset(self, count: isizex2) -> Self[src]

Calculates the offset from a pointer.

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

If any of the following conditions are violated, the result is +Undefined Behavior:

+
    +
  • +

    Both the starting and resulting pointer must be either in +bounds or one byte past the end of an allocated object.

    +
    • +
  • +

    The computed offset, in bytes, cannot overflow an isize.

    +
    • +
  • +

    The offset being in bounds cannot rely on "wrapping around" +the address space. That is, the infinite-precision sum, in bytes +must fit in a usize.

    +
    • +
+

The compiler and standard library generally tries to ensure +allocations never reach a size where an offset is a concern. For +instance, Vec and Box ensure they never allocate more than +isize::MAX bytes, so vec.as_ptr().offset(vec.len() as isize) +is always safe.

+

Most platforms fundamentally can't even construct such an +allocation. For instance, no known 64-bit platform can ever +serve a request for 263 bytes due to page-table limitations or +splitting the address space. However, some 32-bit and 16-bit +platforms may successfully serve a request for more than +isize::MAX bytes with things like Physical Address Extension. +As such, memory acquired directly from allocators or memory +mapped files may be too large to handle with this function.

+

Consider using wrapping_offset instead if these constraints +are difficult to satisfy. The only advantage of this method is +that it enables more aggressive compiler optimizations.

+

pub fn wrapping_offset(self, count: isizex2) -> Self[src]

Calculates the offset from a pointer using wrapping arithmetic.

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

The resulting pointer does not need to be in bounds, but it is +potentially hazardous to dereference (which requires unsafe).

+

Always use .offset(count) instead when possible, because +offset allows the compiler to optimize better.

+

pub unsafe fn offset_from(self, origin: Self) -> isizex2[src]

Calculates the distance between two pointers.

+

The returned value is in units of T: the distance in bytes is +divided by mem::size_of::<T>().

+

This function is the inverse of offset.

+

Safety

+

If any of the following conditions are violated, the result is +Undefined Behavior:

+
    +
  • +

    Both the starting and other pointer must be either in bounds +or one byte past the end of the same allocated object.

    +
    • +
  • +

    The distance between the pointers, in bytes, cannot overflow +an isize.

    +
    • +
  • +

    The distance between the pointers, in bytes, must be an exact +multiple of the size of T.

    +
    • +
  • +

    The distance being in bounds cannot rely on "wrapping around" +the address space.

    +
    • +
+

The compiler and standard library generally try to ensure +allocations never reach a size where an offset is a concern. For +instance, Vec and Box ensure they never allocate more than +isize::MAX bytes, so ptr_into_vec.offset_from(vec.as_ptr()) +is always safe.

+

Most platforms fundamentally can't even construct such an +allocation. For instance, no known 64-bit platform can ever +serve a request for 263 bytes due to page-table limitations or +splitting the address space. However, some 32-bit and 16-bit +platforms may successfully serve a request for more than +isize::MAX bytes with things like Physical Address Extension. +As such, memory acquired directly from allocators or memory +mapped files may be too large to handle with this function.

+

Consider using wrapping_offset_from instead if these constraints +are difficult to satisfy. The only advantage of this method is +that it enables more aggressive compiler optimizations.

+

pub fn wrapping_offset_from(self, origin: Self) -> isizex2[src]

Calculates the distance between two pointers.

+

The returned value is in units of T: the distance in bytes is +divided by mem::size_of::<T>().

+

If the address different between the two pointers is not a +multiple of mem::size_of::<T>() then the result of the +division is rounded towards zero.

+

Though this method is safe for any two pointers, note that its +result will be mostly useless if the two pointers aren't into +the same allocated object, for example if they point to two +different local variables.

+

pub unsafe fn add(self, count: usizex2) -> Self[src]

Calculates the offset from a pointer (convenience for +.offset(count as isize)).

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

If any of the following conditions are violated, the result is +Undefined Behavior:

+
    +
  • +

    Both the starting and resulting pointer must be either in +bounds or one byte past the end of an allocated object.

    +
    • +
  • +

    The computed offset, in bytes, cannot overflow an isize.

    +
    • +
  • +

    The offset being in bounds cannot rely on "wrapping around" +the address space. That is, the infinite-precision sum must fit +in a usize.

    +
    • +
+

The compiler and standard library generally tries to ensure +allocations never reach a size where an offset is a concern. For +instance, Vec and Box ensure they never allocate more than +isize::MAX bytes, so vec.as_ptr().add(vec.len()) is always +safe.

+

Most platforms fundamentally can't even construct such an +allocation. For instance, no known 64-bit platform can ever +serve a request for 263 bytes due to page-table limitations or +splitting the address space. However, some 32-bit and 16-bit +platforms may successfully serve a request for more than +isize::MAX bytes with things like Physical Address Extension. +As such, memory acquired directly from allocators or memory +mapped files may be too large to handle with this function.

+

Consider using wrapping_offset instead if these constraints +are difficult to satisfy. The only advantage of this method is +that it enables more aggressive compiler optimizations.

+

pub unsafe fn sub(self, count: usizex2) -> Self[src]

Calculates the offset from a pointer (convenience for +.offset((count as isize).wrapping_neg())).

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

If any of the following conditions are violated, the result is +Undefined Behavior:

+
    +
  • +

    Both the starting and resulting pointer must be either in +bounds or one byte past the end of an allocated object.

    +
    • +
  • +

    The computed offset cannot exceed isize::MAX bytes.

    +
    • +
  • +

    The offset being in bounds cannot rely on "wrapping around" +the address space. That is, the infinite-precision sum must fit +in a usize.

    +
    • +
+

The compiler and standard library generally tries to ensure +allocations never reach a size where an offset is a concern. For +instance, Vec and Box ensure they never allocate more than +isize::MAX bytes, so +vec.as_ptr().add(vec.len()).sub(vec.len()) is always safe.

+

Most platforms fundamentally can't even construct such an +allocation. For instance, no known 64-bit platform can ever +serve a request for 263 bytes due to page-table +limitations or splitting the address space. However, some 32-bit +and 16-bit platforms may successfully serve a request for more +than isize::MAX bytes with things like Physical Address +Extension. As such, memory acquired directly from allocators or +memory mapped files may be too large to handle with this +function.

+

Consider using wrapping_offset instead if these constraints +are difficult to satisfy. The only advantage of this method is +that it enables more aggressive compiler optimizations.

+

pub fn wrapping_add(self, count: usizex2) -> Self[src]

Calculates the offset from a pointer using wrapping arithmetic. +(convenience for .wrapping_offset(count as isize))

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

The resulting pointer does not need to be in bounds, but it is +potentially hazardous to dereference (which requires unsafe).

+

Always use .add(count) instead when possible, because add +allows the compiler to optimize better.

+

pub fn wrapping_sub(self, count: usizex2) -> Self[src]

Calculates the offset from a pointer using wrapping arithmetic. +(convenience for .wrapping_offset((count as isize).wrapping_sub()))

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

The resulting pointer does not need to be in bounds, but it is +potentially hazardous to dereference (which requires unsafe).

+

Always use .sub(count) instead when possible, because sub +allows the compiler to optimize better.

+

impl<T> cptrx2<T>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl<T> cptrx2<T> where
    [T; 2]: SimdArray, [src]

pub unsafe fn read<M>(
    self,
    mask: Simd<[M; 2]>,
    value: Simd<[T; 2]>
) -> Simd<[T; 2]> where
    M: Mask,
    [M; 2]: SimdArray, [src]

Reads selected vector elements from memory.

+

Instantiates a new vector by reading the values from self for +those lanes whose mask is true, and using the elements of +value otherwise.

+

No memory is accessed for those lanes of self whose mask is +false.

+

Safety

+

This method is unsafe because it dereferences raw pointers. The +pointers must be aligned to mem::align_of::<T>().

+

Trait Implementations

impl<T> Debug for cptrx2<T>[src]

impl<T> Default for cptrx2<T>[src]

impl<T> Eq for cptrx2<T>[src]

impl<T> From<[*const T; 2]> for cptrx2<T>[src]

impl<T> Hash for cptrx2<T>[src]

impl<T> Into<[*const T; 2]> for cptrx2<T>[src]

impl<T> PartialEq<Simd<[*const T; 2]>> for cptrx2<T>[src]

impl<T> Simd for cptrx2<T>[src]

type Element = *const T

Element type of the SIMD vector

+

type LanesType = [u32; 2]

The type: [u32; Self::N].

+
\ No newline at end of file diff --git a/packed_simd/type.cptrx4.html b/packed_simd/type.cptrx4.html new file mode 100644 index 000000000..5fa171caf --- /dev/null +++ b/packed_simd/type.cptrx4.html @@ -0,0 +1,274 @@ +packed_simd::cptrx4 - Rust

[−][src]Type Definition packed_simd::cptrx4

type cptrx4<T> = Simd<[*const T; 4]>;

A vector with 4 *const T lanes

+

Implementations

impl<T> cptrx4<T>[src]

pub const fn new(x0: *const T, x1: *const T, x2: *const T, x3: *const T) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: *const T) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub const fn null() -> Self[src]

Constructs a new instance with each element initialized to +null.

+

pub fn is_null(self) -> msizex4[src]

Returns a mask that selects those lanes that contain null +pointers.

+

pub fn extract(self, index: usize) -> *const T[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> *const T[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: *const T) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: *const T) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl<T> cptrx4<T>[src]

pub fn eq(self, other: Self) -> msizex4[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> msizex4[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> msizex4[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> msizex4[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> msizex4[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> msizex4[src]

Lane-wise greater-than-or-equals comparison.

+

impl<T> cptrx4<T>[src]

pub fn from_slice_aligned(slice: &[*const T]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[*const T]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[*const T]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[*const T]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl<T> cptrx4<T>[src]

pub fn write_to_slice_aligned(self, slice: &mut [*const T])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [*const T])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [*const T])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [*const T])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl<T> cptrx4<T>[src]

pub unsafe fn offset(self, count: isizex4) -> Self[src]

Calculates the offset from a pointer.

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

If any of the following conditions are violated, the result is +Undefined Behavior:

+
    +
  • +

    Both the starting and resulting pointer must be either in +bounds or one byte past the end of an allocated object.

    +
    • +
  • +

    The computed offset, in bytes, cannot overflow an isize.

    +
    • +
  • +

    The offset being in bounds cannot rely on "wrapping around" +the address space. That is, the infinite-precision sum, in bytes +must fit in a usize.

    +
    • +
+

The compiler and standard library generally tries to ensure +allocations never reach a size where an offset is a concern. For +instance, Vec and Box ensure they never allocate more than +isize::MAX bytes, so vec.as_ptr().offset(vec.len() as isize) +is always safe.

+

Most platforms fundamentally can't even construct such an +allocation. For instance, no known 64-bit platform can ever +serve a request for 263 bytes due to page-table limitations or +splitting the address space. However, some 32-bit and 16-bit +platforms may successfully serve a request for more than +isize::MAX bytes with things like Physical Address Extension. +As such, memory acquired directly from allocators or memory +mapped files may be too large to handle with this function.

+

Consider using wrapping_offset instead if these constraints +are difficult to satisfy. The only advantage of this method is +that it enables more aggressive compiler optimizations.

+

pub fn wrapping_offset(self, count: isizex4) -> Self[src]

Calculates the offset from a pointer using wrapping arithmetic.

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

The resulting pointer does not need to be in bounds, but it is +potentially hazardous to dereference (which requires unsafe).

+

Always use .offset(count) instead when possible, because +offset allows the compiler to optimize better.

+

pub unsafe fn offset_from(self, origin: Self) -> isizex4[src]

Calculates the distance between two pointers.

+

The returned value is in units of T: the distance in bytes is +divided by mem::size_of::<T>().

+

This function is the inverse of offset.

+

Safety

+

If any of the following conditions are violated, the result is +Undefined Behavior:

+
    +
  • +

    Both the starting and other pointer must be either in bounds +or one byte past the end of the same allocated object.

    +
    • +
  • +

    The distance between the pointers, in bytes, cannot overflow +an isize.

    +
    • +
  • +

    The distance between the pointers, in bytes, must be an exact +multiple of the size of T.

    +
    • +
  • +

    The distance being in bounds cannot rely on "wrapping around" +the address space.

    +
    • +
+

The compiler and standard library generally try to ensure +allocations never reach a size where an offset is a concern. For +instance, Vec and Box ensure they never allocate more than +isize::MAX bytes, so ptr_into_vec.offset_from(vec.as_ptr()) +is always safe.

+

Most platforms fundamentally can't even construct such an +allocation. For instance, no known 64-bit platform can ever +serve a request for 263 bytes due to page-table limitations or +splitting the address space. However, some 32-bit and 16-bit +platforms may successfully serve a request for more than +isize::MAX bytes with things like Physical Address Extension. +As such, memory acquired directly from allocators or memory +mapped files may be too large to handle with this function.

+

Consider using wrapping_offset_from instead if these constraints +are difficult to satisfy. The only advantage of this method is +that it enables more aggressive compiler optimizations.

+

pub fn wrapping_offset_from(self, origin: Self) -> isizex4[src]

Calculates the distance between two pointers.

+

The returned value is in units of T: the distance in bytes is +divided by mem::size_of::<T>().

+

If the address different between the two pointers is not a +multiple of mem::size_of::<T>() then the result of the +division is rounded towards zero.

+

Though this method is safe for any two pointers, note that its +result will be mostly useless if the two pointers aren't into +the same allocated object, for example if they point to two +different local variables.

+

pub unsafe fn add(self, count: usizex4) -> Self[src]

Calculates the offset from a pointer (convenience for +.offset(count as isize)).

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

If any of the following conditions are violated, the result is +Undefined Behavior:

+
    +
  • +

    Both the starting and resulting pointer must be either in +bounds or one byte past the end of an allocated object.

    +
    • +
  • +

    The computed offset, in bytes, cannot overflow an isize.

    +
    • +
  • +

    The offset being in bounds cannot rely on "wrapping around" +the address space. That is, the infinite-precision sum must fit +in a usize.

    +
    • +
+

The compiler and standard library generally tries to ensure +allocations never reach a size where an offset is a concern. For +instance, Vec and Box ensure they never allocate more than +isize::MAX bytes, so vec.as_ptr().add(vec.len()) is always +safe.

+

Most platforms fundamentally can't even construct such an +allocation. For instance, no known 64-bit platform can ever +serve a request for 263 bytes due to page-table limitations or +splitting the address space. However, some 32-bit and 16-bit +platforms may successfully serve a request for more than +isize::MAX bytes with things like Physical Address Extension. +As such, memory acquired directly from allocators or memory +mapped files may be too large to handle with this function.

+

Consider using wrapping_offset instead if these constraints +are difficult to satisfy. The only advantage of this method is +that it enables more aggressive compiler optimizations.

+

pub unsafe fn sub(self, count: usizex4) -> Self[src]

Calculates the offset from a pointer (convenience for +.offset((count as isize).wrapping_neg())).

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

If any of the following conditions are violated, the result is +Undefined Behavior:

+
    +
  • +

    Both the starting and resulting pointer must be either in +bounds or one byte past the end of an allocated object.

    +
    • +
  • +

    The computed offset cannot exceed isize::MAX bytes.

    +
    • +
  • +

    The offset being in bounds cannot rely on "wrapping around" +the address space. That is, the infinite-precision sum must fit +in a usize.

    +
    • +
+

The compiler and standard library generally tries to ensure +allocations never reach a size where an offset is a concern. For +instance, Vec and Box ensure they never allocate more than +isize::MAX bytes, so +vec.as_ptr().add(vec.len()).sub(vec.len()) is always safe.

+

Most platforms fundamentally can't even construct such an +allocation. For instance, no known 64-bit platform can ever +serve a request for 263 bytes due to page-table +limitations or splitting the address space. However, some 32-bit +and 16-bit platforms may successfully serve a request for more +than isize::MAX bytes with things like Physical Address +Extension. As such, memory acquired directly from allocators or +memory mapped files may be too large to handle with this +function.

+

Consider using wrapping_offset instead if these constraints +are difficult to satisfy. The only advantage of this method is +that it enables more aggressive compiler optimizations.

+

pub fn wrapping_add(self, count: usizex4) -> Self[src]

Calculates the offset from a pointer using wrapping arithmetic. +(convenience for .wrapping_offset(count as isize))

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

The resulting pointer does not need to be in bounds, but it is +potentially hazardous to dereference (which requires unsafe).

+

Always use .add(count) instead when possible, because add +allows the compiler to optimize better.

+

pub fn wrapping_sub(self, count: usizex4) -> Self[src]

Calculates the offset from a pointer using wrapping arithmetic. +(convenience for .wrapping_offset((count as isize).wrapping_sub()))

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

The resulting pointer does not need to be in bounds, but it is +potentially hazardous to dereference (which requires unsafe).

+

Always use .sub(count) instead when possible, because sub +allows the compiler to optimize better.

+

impl<T> cptrx4<T>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl<T> cptrx4<T> where
    [T; 4]: SimdArray, [src]

pub unsafe fn read<M>(
    self,
    mask: Simd<[M; 4]>,
    value: Simd<[T; 4]>
) -> Simd<[T; 4]> where
    M: Mask,
    [M; 4]: SimdArray, [src]

Reads selected vector elements from memory.

+

Instantiates a new vector by reading the values from self for +those lanes whose mask is true, and using the elements of +value otherwise.

+

No memory is accessed for those lanes of self whose mask is +false.

+

Safety

+

This method is unsafe because it dereferences raw pointers. The +pointers must be aligned to mem::align_of::<T>().

+

Trait Implementations

impl<T> Debug for cptrx4<T>[src]

impl<T> Default for cptrx4<T>[src]

impl<T> Eq for cptrx4<T>[src]

impl<T> From<[*const T; 4]> for cptrx4<T>[src]

impl<T> Hash for cptrx4<T>[src]

impl<T> Into<[*const T; 4]> for cptrx4<T>[src]

impl<T> PartialEq<Simd<[*const T; 4]>> for cptrx4<T>[src]

impl<T> Simd for cptrx4<T>[src]

type Element = *const T

Element type of the SIMD vector

+

type LanesType = [u32; 4]

The type: [u32; Self::N].

+
\ No newline at end of file diff --git a/packed_simd/type.cptrx8.html b/packed_simd/type.cptrx8.html new file mode 100644 index 000000000..b544f3270 --- /dev/null +++ b/packed_simd/type.cptrx8.html @@ -0,0 +1,274 @@ +packed_simd::cptrx8 - Rust

[−][src]Type Definition packed_simd::cptrx8

type cptrx8<T> = Simd<[*const T; 8]>;

A vector with 8 *const T lanes

+

Implementations

impl<T> cptrx8<T>[src]

pub const fn new(
    x0: *const T,
    x1: *const T,
    x2: *const T,
    x3: *const T,
    x4: *const T,
    x5: *const T,
    x6: *const T,
    x7: *const T
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: *const T) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub const fn null() -> Self[src]

Constructs a new instance with each element initialized to +null.

+

pub fn is_null(self) -> msizex8[src]

Returns a mask that selects those lanes that contain null +pointers.

+

pub fn extract(self, index: usize) -> *const T[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> *const T[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: *const T) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: *const T) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl<T> cptrx8<T>[src]

pub fn eq(self, other: Self) -> msizex8[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> msizex8[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> msizex8[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> msizex8[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> msizex8[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> msizex8[src]

Lane-wise greater-than-or-equals comparison.

+

impl<T> cptrx8<T>[src]

pub fn from_slice_aligned(slice: &[*const T]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[*const T]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[*const T]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[*const T]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl<T> cptrx8<T>[src]

pub fn write_to_slice_aligned(self, slice: &mut [*const T])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [*const T])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [*const T])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [*const T])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl<T> cptrx8<T>[src]

pub unsafe fn offset(self, count: isizex8) -> Self[src]

Calculates the offset from a pointer.

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

If any of the following conditions are violated, the result is +Undefined Behavior:

+
    +
  • +

    Both the starting and resulting pointer must be either in +bounds or one byte past the end of an allocated object.

    +
    • +
  • +

    The computed offset, in bytes, cannot overflow an isize.

    +
    • +
  • +

    The offset being in bounds cannot rely on "wrapping around" +the address space. That is, the infinite-precision sum, in bytes +must fit in a usize.

    +
    • +
+

The compiler and standard library generally tries to ensure +allocations never reach a size where an offset is a concern. For +instance, Vec and Box ensure they never allocate more than +isize::MAX bytes, so vec.as_ptr().offset(vec.len() as isize) +is always safe.

+

Most platforms fundamentally can't even construct such an +allocation. For instance, no known 64-bit platform can ever +serve a request for 263 bytes due to page-table limitations or +splitting the address space. However, some 32-bit and 16-bit +platforms may successfully serve a request for more than +isize::MAX bytes with things like Physical Address Extension. +As such, memory acquired directly from allocators or memory +mapped files may be too large to handle with this function.

+

Consider using wrapping_offset instead if these constraints +are difficult to satisfy. The only advantage of this method is +that it enables more aggressive compiler optimizations.

+

pub fn wrapping_offset(self, count: isizex8) -> Self[src]

Calculates the offset from a pointer using wrapping arithmetic.

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

The resulting pointer does not need to be in bounds, but it is +potentially hazardous to dereference (which requires unsafe).

+

Always use .offset(count) instead when possible, because +offset allows the compiler to optimize better.

+

pub unsafe fn offset_from(self, origin: Self) -> isizex8[src]

Calculates the distance between two pointers.

+

The returned value is in units of T: the distance in bytes is +divided by mem::size_of::<T>().

+

This function is the inverse of offset.

+

Safety

+

If any of the following conditions are violated, the result is +Undefined Behavior:

+
    +
  • +

    Both the starting and other pointer must be either in bounds +or one byte past the end of the same allocated object.

    +
    • +
  • +

    The distance between the pointers, in bytes, cannot overflow +an isize.

    +
    • +
  • +

    The distance between the pointers, in bytes, must be an exact +multiple of the size of T.

    +
    • +
  • +

    The distance being in bounds cannot rely on "wrapping around" +the address space.

    +
    • +
+

The compiler and standard library generally try to ensure +allocations never reach a size where an offset is a concern. For +instance, Vec and Box ensure they never allocate more than +isize::MAX bytes, so ptr_into_vec.offset_from(vec.as_ptr()) +is always safe.

+

Most platforms fundamentally can't even construct such an +allocation. For instance, no known 64-bit platform can ever +serve a request for 263 bytes due to page-table limitations or +splitting the address space. However, some 32-bit and 16-bit +platforms may successfully serve a request for more than +isize::MAX bytes with things like Physical Address Extension. +As such, memory acquired directly from allocators or memory +mapped files may be too large to handle with this function.

+

Consider using wrapping_offset_from instead if these constraints +are difficult to satisfy. The only advantage of this method is +that it enables more aggressive compiler optimizations.

+

pub fn wrapping_offset_from(self, origin: Self) -> isizex8[src]

Calculates the distance between two pointers.

+

The returned value is in units of T: the distance in bytes is +divided by mem::size_of::<T>().

+

If the address different between the two pointers is not a +multiple of mem::size_of::<T>() then the result of the +division is rounded towards zero.

+

Though this method is safe for any two pointers, note that its +result will be mostly useless if the two pointers aren't into +the same allocated object, for example if they point to two +different local variables.

+

pub unsafe fn add(self, count: usizex8) -> Self[src]

Calculates the offset from a pointer (convenience for +.offset(count as isize)).

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

If any of the following conditions are violated, the result is +Undefined Behavior:

+
    +
  • +

    Both the starting and resulting pointer must be either in +bounds or one byte past the end of an allocated object.

    +
    • +
  • +

    The computed offset, in bytes, cannot overflow an isize.

    +
    • +
  • +

    The offset being in bounds cannot rely on "wrapping around" +the address space. That is, the infinite-precision sum must fit +in a usize.

    +
    • +
+

The compiler and standard library generally tries to ensure +allocations never reach a size where an offset is a concern. For +instance, Vec and Box ensure they never allocate more than +isize::MAX bytes, so vec.as_ptr().add(vec.len()) is always +safe.

+

Most platforms fundamentally can't even construct such an +allocation. For instance, no known 64-bit platform can ever +serve a request for 263 bytes due to page-table limitations or +splitting the address space. However, some 32-bit and 16-bit +platforms may successfully serve a request for more than +isize::MAX bytes with things like Physical Address Extension. +As such, memory acquired directly from allocators or memory +mapped files may be too large to handle with this function.

+

Consider using wrapping_offset instead if these constraints +are difficult to satisfy. The only advantage of this method is +that it enables more aggressive compiler optimizations.

+

pub unsafe fn sub(self, count: usizex8) -> Self[src]

Calculates the offset from a pointer (convenience for +.offset((count as isize).wrapping_neg())).

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

If any of the following conditions are violated, the result is +Undefined Behavior:

+
    +
  • +

    Both the starting and resulting pointer must be either in +bounds or one byte past the end of an allocated object.

    +
    • +
  • +

    The computed offset cannot exceed isize::MAX bytes.

    +
    • +
  • +

    The offset being in bounds cannot rely on "wrapping around" +the address space. That is, the infinite-precision sum must fit +in a usize.

    +
    • +
+

The compiler and standard library generally tries to ensure +allocations never reach a size where an offset is a concern. For +instance, Vec and Box ensure they never allocate more than +isize::MAX bytes, so +vec.as_ptr().add(vec.len()).sub(vec.len()) is always safe.

+

Most platforms fundamentally can't even construct such an +allocation. For instance, no known 64-bit platform can ever +serve a request for 263 bytes due to page-table +limitations or splitting the address space. However, some 32-bit +and 16-bit platforms may successfully serve a request for more +than isize::MAX bytes with things like Physical Address +Extension. As such, memory acquired directly from allocators or +memory mapped files may be too large to handle with this +function.

+

Consider using wrapping_offset instead if these constraints +are difficult to satisfy. The only advantage of this method is +that it enables more aggressive compiler optimizations.

+

pub fn wrapping_add(self, count: usizex8) -> Self[src]

Calculates the offset from a pointer using wrapping arithmetic. +(convenience for .wrapping_offset(count as isize))

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

The resulting pointer does not need to be in bounds, but it is +potentially hazardous to dereference (which requires unsafe).

+

Always use .add(count) instead when possible, because add +allows the compiler to optimize better.

+

pub fn wrapping_sub(self, count: usizex8) -> Self[src]

Calculates the offset from a pointer using wrapping arithmetic. +(convenience for .wrapping_offset((count as isize).wrapping_sub()))

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

The resulting pointer does not need to be in bounds, but it is +potentially hazardous to dereference (which requires unsafe).

+

Always use .sub(count) instead when possible, because sub +allows the compiler to optimize better.

+

impl<T> cptrx8<T>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl<T> cptrx8<T> where
    [T; 8]: SimdArray, [src]

pub unsafe fn read<M>(
    self,
    mask: Simd<[M; 8]>,
    value: Simd<[T; 8]>
) -> Simd<[T; 8]> where
    M: Mask,
    [M; 8]: SimdArray, [src]

Reads selected vector elements from memory.

+

Instantiates a new vector by reading the values from self for +those lanes whose mask is true, and using the elements of +value otherwise.

+

No memory is accessed for those lanes of self whose mask is +false.

+

Safety

+

This method is unsafe because it dereferences raw pointers. The +pointers must be aligned to mem::align_of::<T>().

+

Trait Implementations

impl<T> Debug for cptrx8<T>[src]

impl<T> Default for cptrx8<T>[src]

impl<T> Eq for cptrx8<T>[src]

impl<T> From<[*const T; 8]> for cptrx8<T>[src]

impl<T> Hash for cptrx8<T>[src]

impl<T> Into<[*const T; 8]> for cptrx8<T>[src]

impl<T> PartialEq<Simd<[*const T; 8]>> for cptrx8<T>[src]

impl<T> Simd for cptrx8<T>[src]

type Element = *const T

Element type of the SIMD vector

+

type LanesType = [u32; 8]

The type: [u32; Self::N].

+
\ No newline at end of file diff --git a/packed_simd/type.f32x16.html b/packed_simd/type.f32x16.html new file mode 100644 index 000000000..ea988a1a5 --- /dev/null +++ b/packed_simd/type.f32x16.html @@ -0,0 +1,204 @@ +packed_simd::f32x16 - Rust

[−][src]Type Definition packed_simd::f32x16

type f32x16 = Simd<[f32; 16]>;

A 512-bit vector with 16 f32 lanes.

+

Implementations

impl f32x16[src]

pub const fn new(
    x0: f32,
    x1: f32,
    x2: f32,
    x3: f32,
    x4: f32,
    x5: f32,
    x6: f32,
    x7: f32,
    x8: f32,
    x9: f32,
    x10: f32,
    x11: f32,
    x12: f32,
    x13: f32,
    x14: f32,
    x15: f32
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: f32) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> f32[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> f32[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: f32) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: f32) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl f32x16[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl f32x16[src]

pub fn sum(self) -> f32[src]

Horizontal sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If one of the vector element is NaN the reduction returns +NaN. The resulting NaN is not required to be equal to any +of the NaNs in the vector.

+

pub fn product(self) -> f32[src]

Horizontal product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If one of the vector element is NaN the reduction returns +NaN. The resulting NaN is not required to be equal to any +of the NaNs in the vector.

+

impl f32x16[src]

pub fn max_element(self) -> f32[src]

Largest vector element value.

+

pub fn min_element(self) -> f32[src]

Smallest vector element value.

+

impl f32x16[src]

pub fn from_slice_aligned(slice: &[f32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[f32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[f32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[f32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl f32x16[src]

pub fn write_to_slice_aligned(self, slice: &mut [f32])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [f32])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [f32])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [f32])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl f32x16[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl f32x16[src]

pub const EPSILON: f32x16[src]

Machine epsilon value.

+

pub const MIN: f32x16[src]

Smallest finite value.

+

pub const MIN_POSITIVE: f32x16[src]

Smallest positive normal value.

+

pub const MAX: f32x16[src]

Largest finite value.

+

pub const NAN: f32x16[src]

Not a Number (NaN).

+

pub const INFINITY: f32x16[src]

Infinity (∞).

+

pub const NEG_INFINITY: f32x16[src]

Negative infinity (-∞).

+

pub const PI: f32x16[src]

Archimedes' constant (π)

+

pub const FRAC_PI_2: f32x16[src]

π/2

+

pub const FRAC_PI_3: f32x16[src]

π/3

+

pub const FRAC_PI_4: f32x16[src]

π/4

+

pub const FRAC_PI_6: f32x16[src]

π/6

+

pub const FRAC_PI_8: f32x16[src]

π/8

+

pub const FRAC_1_PI: f32x16[src]

1/π

+

pub const FRAC_2_PI: f32x16[src]

2/π

+

pub const FRAC_2_SQRT_PI: f32x16[src]

2/sqrt(π)

+

pub const SQRT_2: f32x16[src]

sqrt(2)

+

pub const FRAC_1_SQRT_2: f32x16[src]

1/sqrt(2)

+

pub const E: f32x16[src]

Euler's number (e)

+

pub const LOG2_E: f32x16[src]

log2(e)

+

pub const LOG10_E: f32x16[src]

log10(e)

+

pub const LN_2: f32x16[src]

ln(2)

+

pub const LN_10: f32x16[src]

ln(10)

+

impl f32x16[src]

pub fn is_nan(self) -> m32x16[src]

pub fn is_infinite(self) -> m32x16[src]

pub fn is_finite(self) -> m32x16[src]

impl f32x16[src]

pub fn abs(self) -> Self[src]

Absolute value.

+

impl f32x16[src]

pub fn cos(self) -> Self[src]

Cosine.

+

pub fn cos_pi(self) -> Self[src]

Cosine of self * PI.

+

impl f32x16[src]

pub fn exp(self) -> Self[src]

Returns the exponential function of self: e^(self).

+

impl f32x16[src]

pub fn ln(self) -> Self[src]

Returns the natural logarithm of self.

+

impl f32x16[src]

pub fn mul_add(self, y: Self, z: Self) -> Self[src]

Fused multiply add: self * y + z

+

impl f32x16[src]

pub fn mul_adde(self, y: Self, z: Self) -> Self[src]

Fused multiply add estimate: ~= self * y + z

+

While fused multiply-add (fma) has infinite precision, +mul_adde has at worst the same precision of a multiply followed by an add. +This might be more efficient on architectures that do not have an fma instruction.

+

impl f32x16[src]

pub fn powf(self, x: Self) -> Self[src]

Raises self number to the floating point power of x.

+

impl f32x16[src]

pub fn recpre(self) -> Self[src]

Reciprocal estimate: ~= 1. / self.

+

FIXME: The precision of the estimate is currently unspecified.

+

impl f32x16[src]

pub fn rsqrte(self) -> Self[src]

Reciprocal square-root estimate: ~= 1. / self.sqrt().

+

FIXME: The precision of the estimate is currently unspecified.

+

impl f32x16[src]

pub fn sin(self) -> Self[src]

Sine.

+

pub fn sin_pi(self) -> Self[src]

Sine of self * PI.

+

pub fn sin_cos_pi(self) -> (Self, Self)[src]

Sine and cosine of self * PI.

+

impl f32x16[src]

pub fn sqrt(self) -> Self[src]

impl f32x16[src]

pub fn sqrte(self) -> Self[src]

Square-root estimate.

+

FIXME: The precision of the estimate is currently unspecified.

+

impl f32x16[src]

pub fn tanh(self) -> Self[src]

Tanh.

+

impl f32x16[src]

pub fn eq(self, other: Self) -> m32x16[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m32x16[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m32x16[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m32x16[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m32x16[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m32x16[src]

Lane-wise greater-than-or-equals comparison.

+

Trait Implementations

impl Add<Simd<[f32; 16]>> for f32x16[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<f32> for f32x16[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[f32; 16]>> for f32x16[src]

impl AddAssign<f32> for f32x16[src]

impl Debug for f32x16[src]

impl Default for f32x16[src]

impl Div<Simd<[f32; 16]>> for f32x16[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<f32> for f32x16[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[f32; 16]>> for f32x16[src]

impl DivAssign<f32> for f32x16[src]

impl From<[f32; 16]> for f32x16[src]

impl From<Simd<[i16; 16]>> for f32x16[src]

impl From<Simd<[i8; 16]>> for f32x16[src]

impl From<Simd<[u16; 16]>> for f32x16[src]

impl From<Simd<[u8; 16]>> for f32x16[src]

impl FromBits<Simd<[f64; 8]>> for f32x16[src]

impl FromBits<Simd<[i128; 4]>> for f32x16[src]

impl FromBits<Simd<[i16; 32]>> for f32x16[src]

impl FromBits<Simd<[i32; 16]>> for f32x16[src]

impl FromBits<Simd<[i64; 8]>> for f32x16[src]

impl FromBits<Simd<[i8; 64]>> for f32x16[src]

impl FromBits<Simd<[m128; 4]>> for f32x16[src]

impl FromBits<Simd<[m16; 32]>> for f32x16[src]

impl FromBits<Simd<[m32; 16]>> for f32x16[src]

impl FromBits<Simd<[m64; 8]>> for f32x16[src]

impl FromBits<Simd<[m8; 64]>> for f32x16[src]

impl FromBits<Simd<[u128; 4]>> for f32x16[src]

impl FromBits<Simd<[u16; 32]>> for f32x16[src]

impl FromBits<Simd<[u32; 16]>> for f32x16[src]

impl FromBits<Simd<[u64; 8]>> for f32x16[src]

impl FromBits<Simd<[u8; 64]>> for f32x16[src]

impl FromCast<Simd<[i16; 16]>> for f32x16[src]

impl FromCast<Simd<[i32; 16]>> for f32x16[src]

impl FromCast<Simd<[i8; 16]>> for f32x16[src]

impl FromCast<Simd<[m16; 16]>> for f32x16[src]

impl FromCast<Simd<[m32; 16]>> for f32x16[src]

impl FromCast<Simd<[m8; 16]>> for f32x16[src]

impl FromCast<Simd<[u16; 16]>> for f32x16[src]

impl FromCast<Simd<[u32; 16]>> for f32x16[src]

impl FromCast<Simd<[u8; 16]>> for f32x16[src]

impl Mul<Simd<[f32; 16]>> for f32x16[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<f32> for f32x16[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[f32; 16]>> for f32x16[src]

impl MulAssign<f32> for f32x16[src]

impl Neg for f32x16[src]

type Output = Self

The resulting type after applying the - operator.

+

impl PartialEq<Simd<[f32; 16]>> for f32x16[src]

impl<'a> Product<&'a Simd<[f32; 16]>> for f32x16[src]

impl Product<Simd<[f32; 16]>> for f32x16[src]

impl Rem<Simd<[f32; 16]>> for f32x16[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<f32> for f32x16[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[f32; 16]>> for f32x16[src]

impl RemAssign<f32> for f32x16[src]

impl Simd for f32x16[src]

type Element = f32

Element type of the SIMD vector

+

type LanesType = [u32; 16]

The type: [u32; Self::N].

+

impl Sub<Simd<[f32; 16]>> for f32x16[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<f32> for f32x16[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[f32; 16]>> for f32x16[src]

impl SubAssign<f32> for f32x16[src]

impl<'a> Sum<&'a Simd<[f32; 16]>> for f32x16[src]

impl Sum<Simd<[f32; 16]>> for f32x16[src]

\ No newline at end of file diff --git a/packed_simd/type.f32x2.html b/packed_simd/type.f32x2.html new file mode 100644 index 000000000..ff7656a55 --- /dev/null +++ b/packed_simd/type.f32x2.html @@ -0,0 +1,208 @@ +packed_simd::f32x2 - Rust

[−][src]Type Definition packed_simd::f32x2

type f32x2 = Simd<[f32; 2]>;

A 64-bit vector with 2 f32 lanes.

+

Implementations

impl f32x2[src]

pub const fn new(x0: f32, x1: f32) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: f32) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> f32[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> f32[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: f32) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: f32) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl f32x2[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl f32x2[src]

pub fn sum(self) -> f32[src]

Horizontal sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If one of the vector element is NaN the reduction returns +NaN. The resulting NaN is not required to be equal to any +of the NaNs in the vector.

+

pub fn product(self) -> f32[src]

Horizontal product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If one of the vector element is NaN the reduction returns +NaN. The resulting NaN is not required to be equal to any +of the NaNs in the vector.

+

impl f32x2[src]

pub fn max_element(self) -> f32[src]

Largest vector element value.

+

pub fn min_element(self) -> f32[src]

Smallest vector element value.

+

impl f32x2[src]

pub fn from_slice_aligned(slice: &[f32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[f32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[f32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[f32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl f32x2[src]

pub fn write_to_slice_aligned(self, slice: &mut [f32])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [f32])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [f32])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [f32])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl f32x2[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl f32x2[src]

pub const EPSILON: f32x2[src]

Machine epsilon value.

+

pub const MIN: f32x2[src]

Smallest finite value.

+

pub const MIN_POSITIVE: f32x2[src]

Smallest positive normal value.

+

pub const MAX: f32x2[src]

Largest finite value.

+

pub const NAN: f32x2[src]

Not a Number (NaN).

+

pub const INFINITY: f32x2[src]

Infinity (∞).

+

pub const NEG_INFINITY: f32x2[src]

Negative infinity (-∞).

+

pub const PI: f32x2[src]

Archimedes' constant (π)

+

pub const FRAC_PI_2: f32x2[src]

π/2

+

pub const FRAC_PI_3: f32x2[src]

π/3

+

pub const FRAC_PI_4: f32x2[src]

π/4

+

pub const FRAC_PI_6: f32x2[src]

π/6

+

pub const FRAC_PI_8: f32x2[src]

π/8

+

pub const FRAC_1_PI: f32x2[src]

1/π

+

pub const FRAC_2_PI: f32x2[src]

2/π

+

pub const FRAC_2_SQRT_PI: f32x2[src]

2/sqrt(π)

+

pub const SQRT_2: f32x2[src]

sqrt(2)

+

pub const FRAC_1_SQRT_2: f32x2[src]

1/sqrt(2)

+

pub const E: f32x2[src]

Euler's number (e)

+

pub const LOG2_E: f32x2[src]

log2(e)

+

pub const LOG10_E: f32x2[src]

log10(e)

+

pub const LN_2: f32x2[src]

ln(2)

+

pub const LN_10: f32x2[src]

ln(10)

+

impl f32x2[src]

pub fn is_nan(self) -> m32x2[src]

pub fn is_infinite(self) -> m32x2[src]

pub fn is_finite(self) -> m32x2[src]

impl f32x2[src]

pub fn abs(self) -> Self[src]

Absolute value.

+

impl f32x2[src]

pub fn cos(self) -> Self[src]

Cosine.

+

pub fn cos_pi(self) -> Self[src]

Cosine of self * PI.

+

impl f32x2[src]

pub fn exp(self) -> Self[src]

Returns the exponential function of self: e^(self).

+

impl f32x2[src]

pub fn ln(self) -> Self[src]

Returns the natural logarithm of self.

+

impl f32x2[src]

pub fn mul_add(self, y: Self, z: Self) -> Self[src]

Fused multiply add: self * y + z

+

impl f32x2[src]

pub fn mul_adde(self, y: Self, z: Self) -> Self[src]

Fused multiply add estimate: ~= self * y + z

+

While fused multiply-add (fma) has infinite precision, +mul_adde has at worst the same precision of a multiply followed by an add. +This might be more efficient on architectures that do not have an fma instruction.

+

impl f32x2[src]

pub fn powf(self, x: Self) -> Self[src]

Raises self number to the floating point power of x.

+

impl f32x2[src]

pub fn recpre(self) -> Self[src]

Reciprocal estimate: ~= 1. / self.

+

FIXME: The precision of the estimate is currently unspecified.

+

impl f32x2[src]

pub fn rsqrte(self) -> Self[src]

Reciprocal square-root estimate: ~= 1. / self.sqrt().

+

FIXME: The precision of the estimate is currently unspecified.

+

impl f32x2[src]

pub fn sin(self) -> Self[src]

Sine.

+

pub fn sin_pi(self) -> Self[src]

Sine of self * PI.

+

pub fn sin_cos_pi(self) -> (Self, Self)[src]

Sine and cosine of self * PI.

+

impl f32x2[src]

pub fn sqrt(self) -> Self[src]

impl f32x2[src]

pub fn sqrte(self) -> Self[src]

Square-root estimate.

+

FIXME: The precision of the estimate is currently unspecified.

+

impl f32x2[src]

pub fn tanh(self) -> Self[src]

Tanh.

+

impl f32x2[src]

pub fn eq(self, other: Self) -> m32x2[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m32x2[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m32x2[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m32x2[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m32x2[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m32x2[src]

Lane-wise greater-than-or-equals comparison.

+

Trait Implementations

impl Add<Simd<[f32; 2]>> for f32x2[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<f32> for f32x2[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[f32; 2]>> for f32x2[src]

impl AddAssign<f32> for f32x2[src]

impl Debug for f32x2[src]

impl Default for f32x2[src]

impl Div<Simd<[f32; 2]>> for f32x2[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<f32> for f32x2[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[f32; 2]>> for f32x2[src]

impl DivAssign<f32> for f32x2[src]

impl From<[f32; 2]> for f32x2[src]

impl From<Simd<[i16; 2]>> for f32x2[src]

impl From<Simd<[i8; 2]>> for f32x2[src]

impl From<Simd<[u16; 2]>> for f32x2[src]

impl From<Simd<[u8; 2]>> for f32x2[src]

impl FromBits<Simd<[i16; 4]>> for f32x2[src]

impl FromBits<Simd<[i32; 2]>> for f32x2[src]

impl FromBits<Simd<[i8; 8]>> for f32x2[src]

impl FromBits<Simd<[m16; 4]>> for f32x2[src]

impl FromBits<Simd<[m32; 2]>> for f32x2[src]

impl FromBits<Simd<[m8; 8]>> for f32x2[src]

impl FromBits<Simd<[u16; 4]>> for f32x2[src]

impl FromBits<Simd<[u32; 2]>> for f32x2[src]

impl FromBits<Simd<[u8; 8]>> for f32x2[src]

impl FromBits<__m64> for f32x2[src]

impl FromCast<Simd<[f64; 2]>> for f32x2[src]

impl FromCast<Simd<[i128; 2]>> for f32x2[src]

impl FromCast<Simd<[i16; 2]>> for f32x2[src]

impl FromCast<Simd<[i32; 2]>> for f32x2[src]

impl FromCast<Simd<[i64; 2]>> for f32x2[src]

impl FromCast<Simd<[i8; 2]>> for f32x2[src]

impl FromCast<Simd<[isize; 2]>> for f32x2[src]

impl FromCast<Simd<[m128; 2]>> for f32x2[src]

impl FromCast<Simd<[m16; 2]>> for f32x2[src]

impl FromCast<Simd<[m32; 2]>> for f32x2[src]

impl FromCast<Simd<[m64; 2]>> for f32x2[src]

impl FromCast<Simd<[m8; 2]>> for f32x2[src]

impl FromCast<Simd<[msize; 2]>> for f32x2[src]

impl FromCast<Simd<[u128; 2]>> for f32x2[src]

impl FromCast<Simd<[u16; 2]>> for f32x2[src]

impl FromCast<Simd<[u32; 2]>> for f32x2[src]

impl FromCast<Simd<[u64; 2]>> for f32x2[src]

impl FromCast<Simd<[u8; 2]>> for f32x2[src]

impl FromCast<Simd<[usize; 2]>> for f32x2[src]

impl Mul<Simd<[f32; 2]>> for f32x2[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<f32> for f32x2[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[f32; 2]>> for f32x2[src]

impl MulAssign<f32> for f32x2[src]

impl Neg for f32x2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl PartialEq<Simd<[f32; 2]>> for f32x2[src]

impl<'a> Product<&'a Simd<[f32; 2]>> for f32x2[src]

impl Product<Simd<[f32; 2]>> for f32x2[src]

impl Rem<Simd<[f32; 2]>> for f32x2[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<f32> for f32x2[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[f32; 2]>> for f32x2[src]

impl RemAssign<f32> for f32x2[src]

impl Simd for f32x2[src]

type Element = f32

Element type of the SIMD vector

+

type LanesType = [u32; 2]

The type: [u32; Self::N].

+

impl Sub<Simd<[f32; 2]>> for f32x2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<f32> for f32x2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[f32; 2]>> for f32x2[src]

impl SubAssign<f32> for f32x2[src]

impl<'a> Sum<&'a Simd<[f32; 2]>> for f32x2[src]

impl Sum<Simd<[f32; 2]>> for f32x2[src]

\ No newline at end of file diff --git a/packed_simd/type.f32x4.html b/packed_simd/type.f32x4.html new file mode 100644 index 000000000..ce72bd64d --- /dev/null +++ b/packed_simd/type.f32x4.html @@ -0,0 +1,217 @@ +packed_simd::f32x4 - Rust

[−][src]Type Definition packed_simd::f32x4

type f32x4 = Simd<[f32; 4]>;

A 128-bit vector with 4 f32 lanes.

+

Implementations

impl f32x4[src]

pub const fn new(x0: f32, x1: f32, x2: f32, x3: f32) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: f32) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> f32[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> f32[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: f32) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: f32) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl f32x4[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl f32x4[src]

pub fn sum(self) -> f32[src]

Horizontal sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If one of the vector element is NaN the reduction returns +NaN. The resulting NaN is not required to be equal to any +of the NaNs in the vector.

+

pub fn product(self) -> f32[src]

Horizontal product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If one of the vector element is NaN the reduction returns +NaN. The resulting NaN is not required to be equal to any +of the NaNs in the vector.

+

impl f32x4[src]

pub fn max_element(self) -> f32[src]

Largest vector element value.

+

pub fn min_element(self) -> f32[src]

Smallest vector element value.

+

impl f32x4[src]

pub fn from_slice_aligned(slice: &[f32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[f32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[f32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[f32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl f32x4[src]

pub fn write_to_slice_aligned(self, slice: &mut [f32])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [f32])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [f32])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [f32])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl f32x4[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl f32x4[src]

pub const EPSILON: f32x4[src]

Machine epsilon value.

+

pub const MIN: f32x4[src]

Smallest finite value.

+

pub const MIN_POSITIVE: f32x4[src]

Smallest positive normal value.

+

pub const MAX: f32x4[src]

Largest finite value.

+

pub const NAN: f32x4[src]

Not a Number (NaN).

+

pub const INFINITY: f32x4[src]

Infinity (∞).

+

pub const NEG_INFINITY: f32x4[src]

Negative infinity (-∞).

+

pub const PI: f32x4[src]

Archimedes' constant (π)

+

pub const FRAC_PI_2: f32x4[src]

π/2

+

pub const FRAC_PI_3: f32x4[src]

π/3

+

pub const FRAC_PI_4: f32x4[src]

π/4

+

pub const FRAC_PI_6: f32x4[src]

π/6

+

pub const FRAC_PI_8: f32x4[src]

π/8

+

pub const FRAC_1_PI: f32x4[src]

1/π

+

pub const FRAC_2_PI: f32x4[src]

2/π

+

pub const FRAC_2_SQRT_PI: f32x4[src]

2/sqrt(π)

+

pub const SQRT_2: f32x4[src]

sqrt(2)

+

pub const FRAC_1_SQRT_2: f32x4[src]

1/sqrt(2)

+

pub const E: f32x4[src]

Euler's number (e)

+

pub const LOG2_E: f32x4[src]

log2(e)

+

pub const LOG10_E: f32x4[src]

log10(e)

+

pub const LN_2: f32x4[src]

ln(2)

+

pub const LN_10: f32x4[src]

ln(10)

+

impl f32x4[src]

pub fn is_nan(self) -> m32x4[src]

pub fn is_infinite(self) -> m32x4[src]

pub fn is_finite(self) -> m32x4[src]

impl f32x4[src]

pub fn abs(self) -> Self[src]

Absolute value.

+

impl f32x4[src]

pub fn cos(self) -> Self[src]

Cosine.

+

pub fn cos_pi(self) -> Self[src]

Cosine of self * PI.

+

impl f32x4[src]

pub fn exp(self) -> Self[src]

Returns the exponential function of self: e^(self).

+

impl f32x4[src]

pub fn ln(self) -> Self[src]

Returns the natural logarithm of self.

+

impl f32x4[src]

pub fn mul_add(self, y: Self, z: Self) -> Self[src]

Fused multiply add: self * y + z

+

impl f32x4[src]

pub fn mul_adde(self, y: Self, z: Self) -> Self[src]

Fused multiply add estimate: ~= self * y + z

+

While fused multiply-add (fma) has infinite precision, +mul_adde has at worst the same precision of a multiply followed by an add. +This might be more efficient on architectures that do not have an fma instruction.

+

impl f32x4[src]

pub fn powf(self, x: Self) -> Self[src]

Raises self number to the floating point power of x.

+

impl f32x4[src]

pub fn recpre(self) -> Self[src]

Reciprocal estimate: ~= 1. / self.

+

FIXME: The precision of the estimate is currently unspecified.

+

impl f32x4[src]

pub fn rsqrte(self) -> Self[src]

Reciprocal square-root estimate: ~= 1. / self.sqrt().

+

FIXME: The precision of the estimate is currently unspecified.

+

impl f32x4[src]

pub fn sin(self) -> Self[src]

Sine.

+

pub fn sin_pi(self) -> Self[src]

Sine of self * PI.

+

pub fn sin_cos_pi(self) -> (Self, Self)[src]

Sine and cosine of self * PI.

+

impl f32x4[src]

pub fn sqrt(self) -> Self[src]

impl f32x4[src]

pub fn sqrte(self) -> Self[src]

Square-root estimate.

+

FIXME: The precision of the estimate is currently unspecified.

+

impl f32x4[src]

pub fn tanh(self) -> Self[src]

Tanh.

+

impl f32x4[src]

pub fn eq(self, other: Self) -> m32x4[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m32x4[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m32x4[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m32x4[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m32x4[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m32x4[src]

Lane-wise greater-than-or-equals comparison.

+

Trait Implementations

impl Add<Simd<[f32; 4]>> for f32x4[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<f32> for f32x4[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[f32; 4]>> for f32x4[src]

impl AddAssign<f32> for f32x4[src]

impl Debug for f32x4[src]

impl Default for f32x4[src]

impl Div<Simd<[f32; 4]>> for f32x4[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<f32> for f32x4[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[f32; 4]>> for f32x4[src]

impl DivAssign<f32> for f32x4[src]

impl From<[f32; 4]> for f32x4[src]

impl From<Simd<[i16; 4]>> for f32x4[src]

impl From<Simd<[i8; 4]>> for f32x4[src]

impl From<Simd<[u16; 4]>> for f32x4[src]

impl From<Simd<[u8; 4]>> for f32x4[src]

impl FromBits<Simd<[f64; 2]>> for f32x4[src]

impl FromBits<Simd<[i128; 1]>> for f32x4[src]

impl FromBits<Simd<[i16; 8]>> for f32x4[src]

impl FromBits<Simd<[i32; 4]>> for f32x4[src]

impl FromBits<Simd<[i64; 2]>> for f32x4[src]

impl FromBits<Simd<[i8; 16]>> for f32x4[src]

impl FromBits<Simd<[m128; 1]>> for f32x4[src]

impl FromBits<Simd<[m16; 8]>> for f32x4[src]

impl FromBits<Simd<[m32; 4]>> for f32x4[src]

impl FromBits<Simd<[m64; 2]>> for f32x4[src]

impl FromBits<Simd<[m8; 16]>> for f32x4[src]

impl FromBits<Simd<[u128; 1]>> for f32x4[src]

impl FromBits<Simd<[u16; 8]>> for f32x4[src]

impl FromBits<Simd<[u32; 4]>> for f32x4[src]

impl FromBits<Simd<[u64; 2]>> for f32x4[src]

impl FromBits<Simd<[u8; 16]>> for f32x4[src]

impl FromBits<__m128> for f32x4[src]

impl FromBits<__m128d> for f32x4[src]

impl FromBits<__m128i> for f32x4[src]

impl FromCast<Simd<[f64; 4]>> for f32x4[src]

impl FromCast<Simd<[i128; 4]>> for f32x4[src]

impl FromCast<Simd<[i16; 4]>> for f32x4[src]

impl FromCast<Simd<[i32; 4]>> for f32x4[src]

impl FromCast<Simd<[i64; 4]>> for f32x4[src]

impl FromCast<Simd<[i8; 4]>> for f32x4[src]

impl FromCast<Simd<[isize; 4]>> for f32x4[src]

impl FromCast<Simd<[m128; 4]>> for f32x4[src]

impl FromCast<Simd<[m16; 4]>> for f32x4[src]

impl FromCast<Simd<[m32; 4]>> for f32x4[src]

impl FromCast<Simd<[m64; 4]>> for f32x4[src]

impl FromCast<Simd<[m8; 4]>> for f32x4[src]

impl FromCast<Simd<[msize; 4]>> for f32x4[src]

impl FromCast<Simd<[u128; 4]>> for f32x4[src]

impl FromCast<Simd<[u16; 4]>> for f32x4[src]

impl FromCast<Simd<[u32; 4]>> for f32x4[src]

impl FromCast<Simd<[u64; 4]>> for f32x4[src]

impl FromCast<Simd<[u8; 4]>> for f32x4[src]

impl FromCast<Simd<[usize; 4]>> for f32x4[src]

impl Mul<Simd<[f32; 4]>> for f32x4[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<f32> for f32x4[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[f32; 4]>> for f32x4[src]

impl MulAssign<f32> for f32x4[src]

impl Neg for f32x4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl PartialEq<Simd<[f32; 4]>> for f32x4[src]

impl<'a> Product<&'a Simd<[f32; 4]>> for f32x4[src]

impl Product<Simd<[f32; 4]>> for f32x4[src]

impl Rem<Simd<[f32; 4]>> for f32x4[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<f32> for f32x4[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[f32; 4]>> for f32x4[src]

impl RemAssign<f32> for f32x4[src]

impl Simd for f32x4[src]

type Element = f32

Element type of the SIMD vector

+

type LanesType = [u32; 4]

The type: [u32; Self::N].

+

impl Sub<Simd<[f32; 4]>> for f32x4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<f32> for f32x4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[f32; 4]>> for f32x4[src]

impl SubAssign<f32> for f32x4[src]

impl<'a> Sum<&'a Simd<[f32; 4]>> for f32x4[src]

impl Sum<Simd<[f32; 4]>> for f32x4[src]

\ No newline at end of file diff --git a/packed_simd/type.f32x8.html b/packed_simd/type.f32x8.html new file mode 100644 index 000000000..cbd2e9fc8 --- /dev/null +++ b/packed_simd/type.f32x8.html @@ -0,0 +1,214 @@ +packed_simd::f32x8 - Rust

[−][src]Type Definition packed_simd::f32x8

type f32x8 = Simd<[f32; 8]>;

A 256-bit vector with 8 f32 lanes.

+

Implementations

impl f32x8[src]

pub const fn new(
    x0: f32,
    x1: f32,
    x2: f32,
    x3: f32,
    x4: f32,
    x5: f32,
    x6: f32,
    x7: f32
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: f32) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> f32[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> f32[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: f32) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: f32) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl f32x8[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl f32x8[src]

pub fn sum(self) -> f32[src]

Horizontal sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If one of the vector element is NaN the reduction returns +NaN. The resulting NaN is not required to be equal to any +of the NaNs in the vector.

+

pub fn product(self) -> f32[src]

Horizontal product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If one of the vector element is NaN the reduction returns +NaN. The resulting NaN is not required to be equal to any +of the NaNs in the vector.

+

impl f32x8[src]

pub fn max_element(self) -> f32[src]

Largest vector element value.

+

pub fn min_element(self) -> f32[src]

Smallest vector element value.

+

impl f32x8[src]

pub fn from_slice_aligned(slice: &[f32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[f32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[f32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[f32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl f32x8[src]

pub fn write_to_slice_aligned(self, slice: &mut [f32])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [f32])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [f32])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [f32])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl f32x8[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl f32x8[src]

pub const EPSILON: f32x8[src]

Machine epsilon value.

+

pub const MIN: f32x8[src]

Smallest finite value.

+

pub const MIN_POSITIVE: f32x8[src]

Smallest positive normal value.

+

pub const MAX: f32x8[src]

Largest finite value.

+

pub const NAN: f32x8[src]

Not a Number (NaN).

+

pub const INFINITY: f32x8[src]

Infinity (∞).

+

pub const NEG_INFINITY: f32x8[src]

Negative infinity (-∞).

+

pub const PI: f32x8[src]

Archimedes' constant (π)

+

pub const FRAC_PI_2: f32x8[src]

π/2

+

pub const FRAC_PI_3: f32x8[src]

π/3

+

pub const FRAC_PI_4: f32x8[src]

π/4

+

pub const FRAC_PI_6: f32x8[src]

π/6

+

pub const FRAC_PI_8: f32x8[src]

π/8

+

pub const FRAC_1_PI: f32x8[src]

1/π

+

pub const FRAC_2_PI: f32x8[src]

2/π

+

pub const FRAC_2_SQRT_PI: f32x8[src]

2/sqrt(π)

+

pub const SQRT_2: f32x8[src]

sqrt(2)

+

pub const FRAC_1_SQRT_2: f32x8[src]

1/sqrt(2)

+

pub const E: f32x8[src]

Euler's number (e)

+

pub const LOG2_E: f32x8[src]

log2(e)

+

pub const LOG10_E: f32x8[src]

log10(e)

+

pub const LN_2: f32x8[src]

ln(2)

+

pub const LN_10: f32x8[src]

ln(10)

+

impl f32x8[src]

pub fn is_nan(self) -> m32x8[src]

pub fn is_infinite(self) -> m32x8[src]

pub fn is_finite(self) -> m32x8[src]

impl f32x8[src]

pub fn abs(self) -> Self[src]

Absolute value.

+

impl f32x8[src]

pub fn cos(self) -> Self[src]

Cosine.

+

pub fn cos_pi(self) -> Self[src]

Cosine of self * PI.

+

impl f32x8[src]

pub fn exp(self) -> Self[src]

Returns the exponential function of self: e^(self).

+

impl f32x8[src]

pub fn ln(self) -> Self[src]

Returns the natural logarithm of self.

+

impl f32x8[src]

pub fn mul_add(self, y: Self, z: Self) -> Self[src]

Fused multiply add: self * y + z

+

impl f32x8[src]

pub fn mul_adde(self, y: Self, z: Self) -> Self[src]

Fused multiply add estimate: ~= self * y + z

+

While fused multiply-add (fma) has infinite precision, +mul_adde has at worst the same precision of a multiply followed by an add. +This might be more efficient on architectures that do not have an fma instruction.

+

impl f32x8[src]

pub fn powf(self, x: Self) -> Self[src]

Raises self number to the floating point power of x.

+

impl f32x8[src]

pub fn recpre(self) -> Self[src]

Reciprocal estimate: ~= 1. / self.

+

FIXME: The precision of the estimate is currently unspecified.

+

impl f32x8[src]

pub fn rsqrte(self) -> Self[src]

Reciprocal square-root estimate: ~= 1. / self.sqrt().

+

FIXME: The precision of the estimate is currently unspecified.

+

impl f32x8[src]

pub fn sin(self) -> Self[src]

Sine.

+

pub fn sin_pi(self) -> Self[src]

Sine of self * PI.

+

pub fn sin_cos_pi(self) -> (Self, Self)[src]

Sine and cosine of self * PI.

+

impl f32x8[src]

pub fn sqrt(self) -> Self[src]

impl f32x8[src]

pub fn sqrte(self) -> Self[src]

Square-root estimate.

+

FIXME: The precision of the estimate is currently unspecified.

+

impl f32x8[src]

pub fn tanh(self) -> Self[src]

Tanh.

+

impl f32x8[src]

pub fn eq(self, other: Self) -> m32x8[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m32x8[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m32x8[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m32x8[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m32x8[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m32x8[src]

Lane-wise greater-than-or-equals comparison.

+

Trait Implementations

impl Add<Simd<[f32; 8]>> for f32x8[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<f32> for f32x8[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[f32; 8]>> for f32x8[src]

impl AddAssign<f32> for f32x8[src]

impl Debug for f32x8[src]

impl Default for f32x8[src]

impl Div<Simd<[f32; 8]>> for f32x8[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<f32> for f32x8[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[f32; 8]>> for f32x8[src]

impl DivAssign<f32> for f32x8[src]

impl From<[f32; 8]> for f32x8[src]

impl From<Simd<[i16; 8]>> for f32x8[src]

impl From<Simd<[i8; 8]>> for f32x8[src]

impl From<Simd<[u16; 8]>> for f32x8[src]

impl From<Simd<[u8; 8]>> for f32x8[src]

impl FromBits<Simd<[f64; 4]>> for f32x8[src]

impl FromBits<Simd<[i128; 2]>> for f32x8[src]

impl FromBits<Simd<[i16; 16]>> for f32x8[src]

impl FromBits<Simd<[i32; 8]>> for f32x8[src]

impl FromBits<Simd<[i64; 4]>> for f32x8[src]

impl FromBits<Simd<[i8; 32]>> for f32x8[src]

impl FromBits<Simd<[m128; 2]>> for f32x8[src]

impl FromBits<Simd<[m16; 16]>> for f32x8[src]

impl FromBits<Simd<[m32; 8]>> for f32x8[src]

impl FromBits<Simd<[m64; 4]>> for f32x8[src]

impl FromBits<Simd<[m8; 32]>> for f32x8[src]

impl FromBits<Simd<[u128; 2]>> for f32x8[src]

impl FromBits<Simd<[u16; 16]>> for f32x8[src]

impl FromBits<Simd<[u32; 8]>> for f32x8[src]

impl FromBits<Simd<[u64; 4]>> for f32x8[src]

impl FromBits<Simd<[u8; 32]>> for f32x8[src]

impl FromBits<__m256> for f32x8[src]

impl FromBits<__m256d> for f32x8[src]

impl FromBits<__m256i> for f32x8[src]

impl FromCast<Simd<[f64; 8]>> for f32x8[src]

impl FromCast<Simd<[i16; 8]>> for f32x8[src]

impl FromCast<Simd<[i32; 8]>> for f32x8[src]

impl FromCast<Simd<[i64; 8]>> for f32x8[src]

impl FromCast<Simd<[i8; 8]>> for f32x8[src]

impl FromCast<Simd<[isize; 8]>> for f32x8[src]

impl FromCast<Simd<[m16; 8]>> for f32x8[src]

impl FromCast<Simd<[m32; 8]>> for f32x8[src]

impl FromCast<Simd<[m64; 8]>> for f32x8[src]

impl FromCast<Simd<[m8; 8]>> for f32x8[src]

impl FromCast<Simd<[msize; 8]>> for f32x8[src]

impl FromCast<Simd<[u16; 8]>> for f32x8[src]

impl FromCast<Simd<[u32; 8]>> for f32x8[src]

impl FromCast<Simd<[u64; 8]>> for f32x8[src]

impl FromCast<Simd<[u8; 8]>> for f32x8[src]

impl FromCast<Simd<[usize; 8]>> for f32x8[src]

impl Mul<Simd<[f32; 8]>> for f32x8[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<f32> for f32x8[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[f32; 8]>> for f32x8[src]

impl MulAssign<f32> for f32x8[src]

impl Neg for f32x8[src]

type Output = Self

The resulting type after applying the - operator.

+

impl PartialEq<Simd<[f32; 8]>> for f32x8[src]

impl<'a> Product<&'a Simd<[f32; 8]>> for f32x8[src]

impl Product<Simd<[f32; 8]>> for f32x8[src]

impl Rem<Simd<[f32; 8]>> for f32x8[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<f32> for f32x8[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[f32; 8]>> for f32x8[src]

impl RemAssign<f32> for f32x8[src]

impl Simd for f32x8[src]

type Element = f32

Element type of the SIMD vector

+

type LanesType = [u32; 8]

The type: [u32; Self::N].

+

impl Sub<Simd<[f32; 8]>> for f32x8[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<f32> for f32x8[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[f32; 8]>> for f32x8[src]

impl SubAssign<f32> for f32x8[src]

impl<'a> Sum<&'a Simd<[f32; 8]>> for f32x8[src]

impl Sum<Simd<[f32; 8]>> for f32x8[src]

\ No newline at end of file diff --git a/packed_simd/type.f64x2.html b/packed_simd/type.f64x2.html new file mode 100644 index 000000000..41dd555f7 --- /dev/null +++ b/packed_simd/type.f64x2.html @@ -0,0 +1,220 @@ +packed_simd::f64x2 - Rust

[−][src]Type Definition packed_simd::f64x2

type f64x2 = Simd<[f64; 2]>;

A 128-bit vector with 2 f64 lanes.

+

Implementations

impl f64x2[src]

pub const fn new(x0: f64, x1: f64) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: f64) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> f64[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> f64[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: f64) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: f64) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl f64x2[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl f64x2[src]

pub fn sum(self) -> f64[src]

Horizontal sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If one of the vector element is NaN the reduction returns +NaN. The resulting NaN is not required to be equal to any +of the NaNs in the vector.

+

pub fn product(self) -> f64[src]

Horizontal product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If one of the vector element is NaN the reduction returns +NaN. The resulting NaN is not required to be equal to any +of the NaNs in the vector.

+

impl f64x2[src]

pub fn max_element(self) -> f64[src]

Largest vector element value.

+

pub fn min_element(self) -> f64[src]

Smallest vector element value.

+

impl f64x2[src]

pub fn from_slice_aligned(slice: &[f64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[f64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[f64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[f64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl f64x2[src]

pub fn write_to_slice_aligned(self, slice: &mut [f64])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [f64])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [f64])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [f64])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl f64x2[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl f64x2[src]

pub const EPSILON: f64x2[src]

Machine epsilon value.

+

pub const MIN: f64x2[src]

Smallest finite value.

+

pub const MIN_POSITIVE: f64x2[src]

Smallest positive normal value.

+

pub const MAX: f64x2[src]

Largest finite value.

+

pub const NAN: f64x2[src]

Not a Number (NaN).

+

pub const INFINITY: f64x2[src]

Infinity (∞).

+

pub const NEG_INFINITY: f64x2[src]

Negative infinity (-∞).

+

pub const PI: f64x2[src]

Archimedes' constant (π)

+

pub const FRAC_PI_2: f64x2[src]

π/2

+

pub const FRAC_PI_3: f64x2[src]

π/3

+

pub const FRAC_PI_4: f64x2[src]

π/4

+

pub const FRAC_PI_6: f64x2[src]

π/6

+

pub const FRAC_PI_8: f64x2[src]

π/8

+

pub const FRAC_1_PI: f64x2[src]

1/π

+

pub const FRAC_2_PI: f64x2[src]

2/π

+

pub const FRAC_2_SQRT_PI: f64x2[src]

2/sqrt(π)

+

pub const SQRT_2: f64x2[src]

sqrt(2)

+

pub const FRAC_1_SQRT_2: f64x2[src]

1/sqrt(2)

+

pub const E: f64x2[src]

Euler's number (e)

+

pub const LOG2_E: f64x2[src]

log2(e)

+

pub const LOG10_E: f64x2[src]

log10(e)

+

pub const LN_2: f64x2[src]

ln(2)

+

pub const LN_10: f64x2[src]

ln(10)

+

impl f64x2[src]

pub fn is_nan(self) -> m64x2[src]

pub fn is_infinite(self) -> m64x2[src]

pub fn is_finite(self) -> m64x2[src]

impl f64x2[src]

pub fn abs(self) -> Self[src]

Absolute value.

+

impl f64x2[src]

pub fn cos(self) -> Self[src]

Cosine.

+

pub fn cos_pi(self) -> Self[src]

Cosine of self * PI.

+

impl f64x2[src]

pub fn exp(self) -> Self[src]

Returns the exponential function of self: e^(self).

+

impl f64x2[src]

pub fn ln(self) -> Self[src]

Returns the natural logarithm of self.

+

impl f64x2[src]

pub fn mul_add(self, y: Self, z: Self) -> Self[src]

Fused multiply add: self * y + z

+

impl f64x2[src]

pub fn mul_adde(self, y: Self, z: Self) -> Self[src]

Fused multiply add estimate: ~= self * y + z

+

While fused multiply-add (fma) has infinite precision, +mul_adde has at worst the same precision of a multiply followed by an add. +This might be more efficient on architectures that do not have an fma instruction.

+

impl f64x2[src]

pub fn powf(self, x: Self) -> Self[src]

Raises self number to the floating point power of x.

+

impl f64x2[src]

pub fn recpre(self) -> Self[src]

Reciprocal estimate: ~= 1. / self.

+

FIXME: The precision of the estimate is currently unspecified.

+

impl f64x2[src]

pub fn rsqrte(self) -> Self[src]

Reciprocal square-root estimate: ~= 1. / self.sqrt().

+

FIXME: The precision of the estimate is currently unspecified.

+

impl f64x2[src]

pub fn sin(self) -> Self[src]

Sine.

+

pub fn sin_pi(self) -> Self[src]

Sine of self * PI.

+

pub fn sin_cos_pi(self) -> (Self, Self)[src]

Sine and cosine of self * PI.

+

impl f64x2[src]

pub fn sqrt(self) -> Self[src]

impl f64x2[src]

pub fn sqrte(self) -> Self[src]

Square-root estimate.

+

FIXME: The precision of the estimate is currently unspecified.

+

impl f64x2[src]

pub fn tanh(self) -> Self[src]

Tanh.

+

impl f64x2[src]

pub fn eq(self, other: Self) -> m64x2[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m64x2[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m64x2[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m64x2[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m64x2[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m64x2[src]

Lane-wise greater-than-or-equals comparison.

+

Trait Implementations

impl Add<Simd<[f64; 2]>> for f64x2[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<f64> for f64x2[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[f64; 2]>> for f64x2[src]

impl AddAssign<f64> for f64x2[src]

impl Debug for f64x2[src]

impl Default for f64x2[src]

impl Div<Simd<[f64; 2]>> for f64x2[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<f64> for f64x2[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[f64; 2]>> for f64x2[src]

impl DivAssign<f64> for f64x2[src]

impl From<[f64; 2]> for f64x2[src]

impl From<Simd<[f32; 2]>> for f64x2[src]

impl From<Simd<[i16; 2]>> for f64x2[src]

impl From<Simd<[i32; 2]>> for f64x2[src]

impl From<Simd<[i8; 2]>> for f64x2[src]

impl From<Simd<[u16; 2]>> for f64x2[src]

impl From<Simd<[u32; 2]>> for f64x2[src]

impl From<Simd<[u8; 2]>> for f64x2[src]

impl FromBits<Simd<[f32; 4]>> for f64x2[src]

impl FromBits<Simd<[i128; 1]>> for f64x2[src]

impl FromBits<Simd<[i16; 8]>> for f64x2[src]

impl FromBits<Simd<[i32; 4]>> for f64x2[src]

impl FromBits<Simd<[i64; 2]>> for f64x2[src]

impl FromBits<Simd<[i8; 16]>> for f64x2[src]

impl FromBits<Simd<[m128; 1]>> for f64x2[src]

impl FromBits<Simd<[m16; 8]>> for f64x2[src]

impl FromBits<Simd<[m32; 4]>> for f64x2[src]

impl FromBits<Simd<[m64; 2]>> for f64x2[src]

impl FromBits<Simd<[m8; 16]>> for f64x2[src]

impl FromBits<Simd<[u128; 1]>> for f64x2[src]

impl FromBits<Simd<[u16; 8]>> for f64x2[src]

impl FromBits<Simd<[u32; 4]>> for f64x2[src]

impl FromBits<Simd<[u64; 2]>> for f64x2[src]

impl FromBits<Simd<[u8; 16]>> for f64x2[src]

impl FromBits<__m128> for f64x2[src]

impl FromBits<__m128d> for f64x2[src]

impl FromBits<__m128i> for f64x2[src]

impl FromCast<Simd<[f32; 2]>> for f64x2[src]

impl FromCast<Simd<[i128; 2]>> for f64x2[src]

impl FromCast<Simd<[i16; 2]>> for f64x2[src]

impl FromCast<Simd<[i32; 2]>> for f64x2[src]

impl FromCast<Simd<[i64; 2]>> for f64x2[src]

impl FromCast<Simd<[i8; 2]>> for f64x2[src]

impl FromCast<Simd<[isize; 2]>> for f64x2[src]

impl FromCast<Simd<[m128; 2]>> for f64x2[src]

impl FromCast<Simd<[m16; 2]>> for f64x2[src]

impl FromCast<Simd<[m32; 2]>> for f64x2[src]

impl FromCast<Simd<[m64; 2]>> for f64x2[src]

impl FromCast<Simd<[m8; 2]>> for f64x2[src]

impl FromCast<Simd<[msize; 2]>> for f64x2[src]

impl FromCast<Simd<[u128; 2]>> for f64x2[src]

impl FromCast<Simd<[u16; 2]>> for f64x2[src]

impl FromCast<Simd<[u32; 2]>> for f64x2[src]

impl FromCast<Simd<[u64; 2]>> for f64x2[src]

impl FromCast<Simd<[u8; 2]>> for f64x2[src]

impl FromCast<Simd<[usize; 2]>> for f64x2[src]

impl Mul<Simd<[f64; 2]>> for f64x2[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<f64> for f64x2[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[f64; 2]>> for f64x2[src]

impl MulAssign<f64> for f64x2[src]

impl Neg for f64x2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl PartialEq<Simd<[f64; 2]>> for f64x2[src]

impl<'a> Product<&'a Simd<[f64; 2]>> for f64x2[src]

impl Product<Simd<[f64; 2]>> for f64x2[src]

impl Rem<Simd<[f64; 2]>> for f64x2[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<f64> for f64x2[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[f64; 2]>> for f64x2[src]

impl RemAssign<f64> for f64x2[src]

impl Simd for f64x2[src]

type Element = f64

Element type of the SIMD vector

+

type LanesType = [u32; 2]

The type: [u32; Self::N].

+

impl Sub<Simd<[f64; 2]>> for f64x2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<f64> for f64x2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[f64; 2]>> for f64x2[src]

impl SubAssign<f64> for f64x2[src]

impl<'a> Sum<&'a Simd<[f64; 2]>> for f64x2[src]

impl Sum<Simd<[f64; 2]>> for f64x2[src]

\ No newline at end of file diff --git a/packed_simd/type.f64x4.html b/packed_simd/type.f64x4.html new file mode 100644 index 000000000..4ffa39674 --- /dev/null +++ b/packed_simd/type.f64x4.html @@ -0,0 +1,220 @@ +packed_simd::f64x4 - Rust

[−][src]Type Definition packed_simd::f64x4

type f64x4 = Simd<[f64; 4]>;

A 256-bit vector with 4 f64 lanes.

+

Implementations

impl f64x4[src]

pub const fn new(x0: f64, x1: f64, x2: f64, x3: f64) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: f64) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> f64[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> f64[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: f64) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: f64) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl f64x4[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl f64x4[src]

pub fn sum(self) -> f64[src]

Horizontal sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If one of the vector element is NaN the reduction returns +NaN. The resulting NaN is not required to be equal to any +of the NaNs in the vector.

+

pub fn product(self) -> f64[src]

Horizontal product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If one of the vector element is NaN the reduction returns +NaN. The resulting NaN is not required to be equal to any +of the NaNs in the vector.

+

impl f64x4[src]

pub fn max_element(self) -> f64[src]

Largest vector element value.

+

pub fn min_element(self) -> f64[src]

Smallest vector element value.

+

impl f64x4[src]

pub fn from_slice_aligned(slice: &[f64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[f64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[f64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[f64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl f64x4[src]

pub fn write_to_slice_aligned(self, slice: &mut [f64])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [f64])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [f64])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [f64])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl f64x4[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl f64x4[src]

pub const EPSILON: f64x4[src]

Machine epsilon value.

+

pub const MIN: f64x4[src]

Smallest finite value.

+

pub const MIN_POSITIVE: f64x4[src]

Smallest positive normal value.

+

pub const MAX: f64x4[src]

Largest finite value.

+

pub const NAN: f64x4[src]

Not a Number (NaN).

+

pub const INFINITY: f64x4[src]

Infinity (∞).

+

pub const NEG_INFINITY: f64x4[src]

Negative infinity (-∞).

+

pub const PI: f64x4[src]

Archimedes' constant (π)

+

pub const FRAC_PI_2: f64x4[src]

π/2

+

pub const FRAC_PI_3: f64x4[src]

π/3

+

pub const FRAC_PI_4: f64x4[src]

π/4

+

pub const FRAC_PI_6: f64x4[src]

π/6

+

pub const FRAC_PI_8: f64x4[src]

π/8

+

pub const FRAC_1_PI: f64x4[src]

1/π

+

pub const FRAC_2_PI: f64x4[src]

2/π

+

pub const FRAC_2_SQRT_PI: f64x4[src]

2/sqrt(π)

+

pub const SQRT_2: f64x4[src]

sqrt(2)

+

pub const FRAC_1_SQRT_2: f64x4[src]

1/sqrt(2)

+

pub const E: f64x4[src]

Euler's number (e)

+

pub const LOG2_E: f64x4[src]

log2(e)

+

pub const LOG10_E: f64x4[src]

log10(e)

+

pub const LN_2: f64x4[src]

ln(2)

+

pub const LN_10: f64x4[src]

ln(10)

+

impl f64x4[src]

pub fn is_nan(self) -> m64x4[src]

pub fn is_infinite(self) -> m64x4[src]

pub fn is_finite(self) -> m64x4[src]

impl f64x4[src]

pub fn abs(self) -> Self[src]

Absolute value.

+

impl f64x4[src]

pub fn cos(self) -> Self[src]

Cosine.

+

pub fn cos_pi(self) -> Self[src]

Cosine of self * PI.

+

impl f64x4[src]

pub fn exp(self) -> Self[src]

Returns the exponential function of self: e^(self).

+

impl f64x4[src]

pub fn ln(self) -> Self[src]

Returns the natural logarithm of self.

+

impl f64x4[src]

pub fn mul_add(self, y: Self, z: Self) -> Self[src]

Fused multiply add: self * y + z

+

impl f64x4[src]

pub fn mul_adde(self, y: Self, z: Self) -> Self[src]

Fused multiply add estimate: ~= self * y + z

+

While fused multiply-add (fma) has infinite precision, +mul_adde has at worst the same precision of a multiply followed by an add. +This might be more efficient on architectures that do not have an fma instruction.

+

impl f64x4[src]

pub fn powf(self, x: Self) -> Self[src]

Raises self number to the floating point power of x.

+

impl f64x4[src]

pub fn recpre(self) -> Self[src]

Reciprocal estimate: ~= 1. / self.

+

FIXME: The precision of the estimate is currently unspecified.

+

impl f64x4[src]

pub fn rsqrte(self) -> Self[src]

Reciprocal square-root estimate: ~= 1. / self.sqrt().

+

FIXME: The precision of the estimate is currently unspecified.

+

impl f64x4[src]

pub fn sin(self) -> Self[src]

Sine.

+

pub fn sin_pi(self) -> Self[src]

Sine of self * PI.

+

pub fn sin_cos_pi(self) -> (Self, Self)[src]

Sine and cosine of self * PI.

+

impl f64x4[src]

pub fn sqrt(self) -> Self[src]

impl f64x4[src]

pub fn sqrte(self) -> Self[src]

Square-root estimate.

+

FIXME: The precision of the estimate is currently unspecified.

+

impl f64x4[src]

pub fn tanh(self) -> Self[src]

Tanh.

+

impl f64x4[src]

pub fn eq(self, other: Self) -> m64x4[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m64x4[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m64x4[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m64x4[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m64x4[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m64x4[src]

Lane-wise greater-than-or-equals comparison.

+

Trait Implementations

impl Add<Simd<[f64; 4]>> for f64x4[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<f64> for f64x4[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[f64; 4]>> for f64x4[src]

impl AddAssign<f64> for f64x4[src]

impl Debug for f64x4[src]

impl Default for f64x4[src]

impl Div<Simd<[f64; 4]>> for f64x4[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<f64> for f64x4[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[f64; 4]>> for f64x4[src]

impl DivAssign<f64> for f64x4[src]

impl From<[f64; 4]> for f64x4[src]

impl From<Simd<[f32; 4]>> for f64x4[src]

impl From<Simd<[i16; 4]>> for f64x4[src]

impl From<Simd<[i32; 4]>> for f64x4[src]

impl From<Simd<[i8; 4]>> for f64x4[src]

impl From<Simd<[u16; 4]>> for f64x4[src]

impl From<Simd<[u32; 4]>> for f64x4[src]

impl From<Simd<[u8; 4]>> for f64x4[src]

impl FromBits<Simd<[f32; 8]>> for f64x4[src]

impl FromBits<Simd<[i128; 2]>> for f64x4[src]

impl FromBits<Simd<[i16; 16]>> for f64x4[src]

impl FromBits<Simd<[i32; 8]>> for f64x4[src]

impl FromBits<Simd<[i64; 4]>> for f64x4[src]

impl FromBits<Simd<[i8; 32]>> for f64x4[src]

impl FromBits<Simd<[m128; 2]>> for f64x4[src]

impl FromBits<Simd<[m16; 16]>> for f64x4[src]

impl FromBits<Simd<[m32; 8]>> for f64x4[src]

impl FromBits<Simd<[m64; 4]>> for f64x4[src]

impl FromBits<Simd<[m8; 32]>> for f64x4[src]

impl FromBits<Simd<[u128; 2]>> for f64x4[src]

impl FromBits<Simd<[u16; 16]>> for f64x4[src]

impl FromBits<Simd<[u32; 8]>> for f64x4[src]

impl FromBits<Simd<[u64; 4]>> for f64x4[src]

impl FromBits<Simd<[u8; 32]>> for f64x4[src]

impl FromBits<__m256> for f64x4[src]

impl FromBits<__m256d> for f64x4[src]

impl FromBits<__m256i> for f64x4[src]

impl FromCast<Simd<[f32; 4]>> for f64x4[src]

impl FromCast<Simd<[i128; 4]>> for f64x4[src]

impl FromCast<Simd<[i16; 4]>> for f64x4[src]

impl FromCast<Simd<[i32; 4]>> for f64x4[src]

impl FromCast<Simd<[i64; 4]>> for f64x4[src]

impl FromCast<Simd<[i8; 4]>> for f64x4[src]

impl FromCast<Simd<[isize; 4]>> for f64x4[src]

impl FromCast<Simd<[m128; 4]>> for f64x4[src]

impl FromCast<Simd<[m16; 4]>> for f64x4[src]

impl FromCast<Simd<[m32; 4]>> for f64x4[src]

impl FromCast<Simd<[m64; 4]>> for f64x4[src]

impl FromCast<Simd<[m8; 4]>> for f64x4[src]

impl FromCast<Simd<[msize; 4]>> for f64x4[src]

impl FromCast<Simd<[u128; 4]>> for f64x4[src]

impl FromCast<Simd<[u16; 4]>> for f64x4[src]

impl FromCast<Simd<[u32; 4]>> for f64x4[src]

impl FromCast<Simd<[u64; 4]>> for f64x4[src]

impl FromCast<Simd<[u8; 4]>> for f64x4[src]

impl FromCast<Simd<[usize; 4]>> for f64x4[src]

impl Mul<Simd<[f64; 4]>> for f64x4[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<f64> for f64x4[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[f64; 4]>> for f64x4[src]

impl MulAssign<f64> for f64x4[src]

impl Neg for f64x4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl PartialEq<Simd<[f64; 4]>> for f64x4[src]

impl<'a> Product<&'a Simd<[f64; 4]>> for f64x4[src]

impl Product<Simd<[f64; 4]>> for f64x4[src]

impl Rem<Simd<[f64; 4]>> for f64x4[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<f64> for f64x4[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[f64; 4]>> for f64x4[src]

impl RemAssign<f64> for f64x4[src]

impl Simd for f64x4[src]

type Element = f64

Element type of the SIMD vector

+

type LanesType = [u32; 4]

The type: [u32; Self::N].

+

impl Sub<Simd<[f64; 4]>> for f64x4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<f64> for f64x4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[f64; 4]>> for f64x4[src]

impl SubAssign<f64> for f64x4[src]

impl<'a> Sum<&'a Simd<[f64; 4]>> for f64x4[src]

impl Sum<Simd<[f64; 4]>> for f64x4[src]

\ No newline at end of file diff --git a/packed_simd/type.f64x8.html b/packed_simd/type.f64x8.html new file mode 100644 index 000000000..993f7e72a --- /dev/null +++ b/packed_simd/type.f64x8.html @@ -0,0 +1,214 @@ +packed_simd::f64x8 - Rust

[−][src]Type Definition packed_simd::f64x8

type f64x8 = Simd<[f64; 8]>;

A 512-bit vector with 8 f64 lanes.

+

Implementations

impl f64x8[src]

pub const fn new(
    x0: f64,
    x1: f64,
    x2: f64,
    x3: f64,
    x4: f64,
    x5: f64,
    x6: f64,
    x7: f64
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: f64) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> f64[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> f64[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: f64) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: f64) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl f64x8[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl f64x8[src]

pub fn sum(self) -> f64[src]

Horizontal sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If one of the vector element is NaN the reduction returns +NaN. The resulting NaN is not required to be equal to any +of the NaNs in the vector.

+

pub fn product(self) -> f64[src]

Horizontal product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If one of the vector element is NaN the reduction returns +NaN. The resulting NaN is not required to be equal to any +of the NaNs in the vector.

+

impl f64x8[src]

pub fn max_element(self) -> f64[src]

Largest vector element value.

+

pub fn min_element(self) -> f64[src]

Smallest vector element value.

+

impl f64x8[src]

pub fn from_slice_aligned(slice: &[f64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[f64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[f64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[f64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl f64x8[src]

pub fn write_to_slice_aligned(self, slice: &mut [f64])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [f64])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [f64])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [f64])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl f64x8[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl f64x8[src]

pub const EPSILON: f64x8[src]

Machine epsilon value.

+

pub const MIN: f64x8[src]

Smallest finite value.

+

pub const MIN_POSITIVE: f64x8[src]

Smallest positive normal value.

+

pub const MAX: f64x8[src]

Largest finite value.

+

pub const NAN: f64x8[src]

Not a Number (NaN).

+

pub const INFINITY: f64x8[src]

Infinity (∞).

+

pub const NEG_INFINITY: f64x8[src]

Negative infinity (-∞).

+

pub const PI: f64x8[src]

Archimedes' constant (π)

+

pub const FRAC_PI_2: f64x8[src]

π/2

+

pub const FRAC_PI_3: f64x8[src]

π/3

+

pub const FRAC_PI_4: f64x8[src]

π/4

+

pub const FRAC_PI_6: f64x8[src]

π/6

+

pub const FRAC_PI_8: f64x8[src]

π/8

+

pub const FRAC_1_PI: f64x8[src]

1/π

+

pub const FRAC_2_PI: f64x8[src]

2/π

+

pub const FRAC_2_SQRT_PI: f64x8[src]

2/sqrt(π)

+

pub const SQRT_2: f64x8[src]

sqrt(2)

+

pub const FRAC_1_SQRT_2: f64x8[src]

1/sqrt(2)

+

pub const E: f64x8[src]

Euler's number (e)

+

pub const LOG2_E: f64x8[src]

log2(e)

+

pub const LOG10_E: f64x8[src]

log10(e)

+

pub const LN_2: f64x8[src]

ln(2)

+

pub const LN_10: f64x8[src]

ln(10)

+

impl f64x8[src]

pub fn is_nan(self) -> m64x8[src]

pub fn is_infinite(self) -> m64x8[src]

pub fn is_finite(self) -> m64x8[src]

impl f64x8[src]

pub fn abs(self) -> Self[src]

Absolute value.

+

impl f64x8[src]

pub fn cos(self) -> Self[src]

Cosine.

+

pub fn cos_pi(self) -> Self[src]

Cosine of self * PI.

+

impl f64x8[src]

pub fn exp(self) -> Self[src]

Returns the exponential function of self: e^(self).

+

impl f64x8[src]

pub fn ln(self) -> Self[src]

Returns the natural logarithm of self.

+

impl f64x8[src]

pub fn mul_add(self, y: Self, z: Self) -> Self[src]

Fused multiply add: self * y + z

+

impl f64x8[src]

pub fn mul_adde(self, y: Self, z: Self) -> Self[src]

Fused multiply add estimate: ~= self * y + z

+

While fused multiply-add (fma) has infinite precision, +mul_adde has at worst the same precision of a multiply followed by an add. +This might be more efficient on architectures that do not have an fma instruction.

+

impl f64x8[src]

pub fn powf(self, x: Self) -> Self[src]

Raises self number to the floating point power of x.

+

impl f64x8[src]

pub fn recpre(self) -> Self[src]

Reciprocal estimate: ~= 1. / self.

+

FIXME: The precision of the estimate is currently unspecified.

+

impl f64x8[src]

pub fn rsqrte(self) -> Self[src]

Reciprocal square-root estimate: ~= 1. / self.sqrt().

+

FIXME: The precision of the estimate is currently unspecified.

+

impl f64x8[src]

pub fn sin(self) -> Self[src]

Sine.

+

pub fn sin_pi(self) -> Self[src]

Sine of self * PI.

+

pub fn sin_cos_pi(self) -> (Self, Self)[src]

Sine and cosine of self * PI.

+

impl f64x8[src]

pub fn sqrt(self) -> Self[src]

impl f64x8[src]

pub fn sqrte(self) -> Self[src]

Square-root estimate.

+

FIXME: The precision of the estimate is currently unspecified.

+

impl f64x8[src]

pub fn tanh(self) -> Self[src]

Tanh.

+

impl f64x8[src]

pub fn eq(self, other: Self) -> m64x8[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m64x8[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m64x8[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m64x8[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m64x8[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m64x8[src]

Lane-wise greater-than-or-equals comparison.

+

Trait Implementations

impl Add<Simd<[f64; 8]>> for f64x8[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<f64> for f64x8[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[f64; 8]>> for f64x8[src]

impl AddAssign<f64> for f64x8[src]

impl Debug for f64x8[src]

impl Default for f64x8[src]

impl Div<Simd<[f64; 8]>> for f64x8[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<f64> for f64x8[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[f64; 8]>> for f64x8[src]

impl DivAssign<f64> for f64x8[src]

impl From<[f64; 8]> for f64x8[src]

impl From<Simd<[f32; 8]>> for f64x8[src]

impl From<Simd<[i16; 8]>> for f64x8[src]

impl From<Simd<[i32; 8]>> for f64x8[src]

impl From<Simd<[i8; 8]>> for f64x8[src]

impl From<Simd<[u16; 8]>> for f64x8[src]

impl From<Simd<[u32; 8]>> for f64x8[src]

impl From<Simd<[u8; 8]>> for f64x8[src]

impl FromBits<Simd<[f32; 16]>> for f64x8[src]

impl FromBits<Simd<[i128; 4]>> for f64x8[src]

impl FromBits<Simd<[i16; 32]>> for f64x8[src]

impl FromBits<Simd<[i32; 16]>> for f64x8[src]

impl FromBits<Simd<[i64; 8]>> for f64x8[src]

impl FromBits<Simd<[i8; 64]>> for f64x8[src]

impl FromBits<Simd<[m128; 4]>> for f64x8[src]

impl FromBits<Simd<[m16; 32]>> for f64x8[src]

impl FromBits<Simd<[m32; 16]>> for f64x8[src]

impl FromBits<Simd<[m64; 8]>> for f64x8[src]

impl FromBits<Simd<[m8; 64]>> for f64x8[src]

impl FromBits<Simd<[u128; 4]>> for f64x8[src]

impl FromBits<Simd<[u16; 32]>> for f64x8[src]

impl FromBits<Simd<[u32; 16]>> for f64x8[src]

impl FromBits<Simd<[u64; 8]>> for f64x8[src]

impl FromBits<Simd<[u8; 64]>> for f64x8[src]

impl FromCast<Simd<[f32; 8]>> for f64x8[src]

impl FromCast<Simd<[i16; 8]>> for f64x8[src]

impl FromCast<Simd<[i32; 8]>> for f64x8[src]

impl FromCast<Simd<[i64; 8]>> for f64x8[src]

impl FromCast<Simd<[i8; 8]>> for f64x8[src]

impl FromCast<Simd<[isize; 8]>> for f64x8[src]

impl FromCast<Simd<[m16; 8]>> for f64x8[src]

impl FromCast<Simd<[m32; 8]>> for f64x8[src]

impl FromCast<Simd<[m64; 8]>> for f64x8[src]

impl FromCast<Simd<[m8; 8]>> for f64x8[src]

impl FromCast<Simd<[msize; 8]>> for f64x8[src]

impl FromCast<Simd<[u16; 8]>> for f64x8[src]

impl FromCast<Simd<[u32; 8]>> for f64x8[src]

impl FromCast<Simd<[u64; 8]>> for f64x8[src]

impl FromCast<Simd<[u8; 8]>> for f64x8[src]

impl FromCast<Simd<[usize; 8]>> for f64x8[src]

impl Mul<Simd<[f64; 8]>> for f64x8[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<f64> for f64x8[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[f64; 8]>> for f64x8[src]

impl MulAssign<f64> for f64x8[src]

impl Neg for f64x8[src]

type Output = Self

The resulting type after applying the - operator.

+

impl PartialEq<Simd<[f64; 8]>> for f64x8[src]

impl<'a> Product<&'a Simd<[f64; 8]>> for f64x8[src]

impl Product<Simd<[f64; 8]>> for f64x8[src]

impl Rem<Simd<[f64; 8]>> for f64x8[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<f64> for f64x8[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[f64; 8]>> for f64x8[src]

impl RemAssign<f64> for f64x8[src]

impl Simd for f64x8[src]

type Element = f64

Element type of the SIMD vector

+

type LanesType = [u32; 8]

The type: [u32; Self::N].

+

impl Sub<Simd<[f64; 8]>> for f64x8[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<f64> for f64x8[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[f64; 8]>> for f64x8[src]

impl SubAssign<f64> for f64x8[src]

impl<'a> Sum<&'a Simd<[f64; 8]>> for f64x8[src]

impl Sum<Simd<[f64; 8]>> for f64x8[src]

\ No newline at end of file diff --git a/packed_simd/type.i128x1.html b/packed_simd/type.i128x1.html new file mode 100644 index 000000000..787d1581e --- /dev/null +++ b/packed_simd/type.i128x1.html @@ -0,0 +1,233 @@ +packed_simd::i128x1 - Rust

[−][src]Type Definition packed_simd::i128x1

type i128x1 = Simd<[i128; 1]>;

A 128-bit vector with 1 i128 lane.

+

Implementations

impl i128x1[src]

pub const fn new(x0: i128) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: i128) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> i128[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> i128[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: i128) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: i128) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl i128x1[src]

pub fn rotate_left(self, n: i128x1) -> i128x1[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: i128x1) -> i128x1[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl i128x1[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl i128x1[src]

pub fn wrapping_sum(self) -> i128[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> i128[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl i128x1[src]

pub fn max_element(self) -> i128[src]

Largest vector element value.

+

pub fn min_element(self) -> i128[src]

Smallest vector element value.

+

impl i128x1[src]

pub fn and(self) -> i128[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> i128[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> i128[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl i128x1[src]

pub fn from_slice_aligned(slice: &[i128]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[i128]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[i128]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[i128]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl i128x1[src]

pub fn write_to_slice_aligned(self, slice: &mut [i128])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [i128])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [i128])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [i128])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl i128x1[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl i128x1[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl i128x1[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl i128x1[src]

pub fn eq(self, other: Self) -> m128x1[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m128x1[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m128x1[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m128x1[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m128x1[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m128x1[src]

Lane-wise greater-than-or-equals comparison.

+

impl i128x1[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<i128x1>[src]

Returns a wrapper that implements PartialOrd.

+

impl i128x1[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<i128x1>[src]

Returns a wrapper that implements Ord.

+

impl i128x1[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl Add<Simd<[i128; 1]>> for i128x1[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<i128> for i128x1[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[i128; 1]>> for i128x1[src]

impl AddAssign<i128> for i128x1[src]

impl Binary for i128x1[src]

impl BitAnd<Simd<[i128; 1]>> for i128x1[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<i128> for i128x1[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[i128; 1]>> for i128x1[src]

impl BitAndAssign<i128> for i128x1[src]

impl BitOr<Simd<[i128; 1]>> for i128x1[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<i128> for i128x1[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[i128; 1]>> for i128x1[src]

impl BitOrAssign<i128> for i128x1[src]

impl BitXor<Simd<[i128; 1]>> for i128x1[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<i128> for i128x1[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[i128; 1]>> for i128x1[src]

impl BitXorAssign<i128> for i128x1[src]

impl Debug for i128x1[src]

impl Default for i128x1[src]

impl Div<Simd<[i128; 1]>> for i128x1[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<i128> for i128x1[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[i128; 1]>> for i128x1[src]

impl DivAssign<i128> for i128x1[src]

impl Eq for i128x1[src]

impl From<[i128; 1]> for i128x1[src]

impl FromBits<Simd<[f32; 4]>> for i128x1[src]

impl FromBits<Simd<[f64; 2]>> for i128x1[src]

impl FromBits<Simd<[i16; 8]>> for i128x1[src]

impl FromBits<Simd<[i32; 4]>> for i128x1[src]

impl FromBits<Simd<[i64; 2]>> for i128x1[src]

impl FromBits<Simd<[i8; 16]>> for i128x1[src]

impl FromBits<Simd<[m128; 1]>> for i128x1[src]

impl FromBits<Simd<[m16; 8]>> for i128x1[src]

impl FromBits<Simd<[m32; 4]>> for i128x1[src]

impl FromBits<Simd<[m64; 2]>> for i128x1[src]

impl FromBits<Simd<[m8; 16]>> for i128x1[src]

impl FromBits<Simd<[u128; 1]>> for i128x1[src]

impl FromBits<Simd<[u16; 8]>> for i128x1[src]

impl FromBits<Simd<[u32; 4]>> for i128x1[src]

impl FromBits<Simd<[u64; 2]>> for i128x1[src]

impl FromBits<Simd<[u8; 16]>> for i128x1[src]

impl FromBits<__m128> for i128x1[src]

impl FromBits<__m128d> for i128x1[src]

impl FromBits<__m128i> for i128x1[src]

impl FromCast<Simd<[m128; 1]>> for i128x1[src]

impl FromCast<Simd<[u128; 1]>> for i128x1[src]

impl Hash for i128x1[src]

impl LowerHex for i128x1[src]

impl Mul<Simd<[i128; 1]>> for i128x1[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<i128> for i128x1[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[i128; 1]>> for i128x1[src]

impl MulAssign<i128> for i128x1[src]

impl Neg for i128x1[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Not for i128x1[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl Octal for i128x1[src]

impl PartialEq<Simd<[i128; 1]>> for i128x1[src]

impl<'a> Product<&'a Simd<[i128; 1]>> for i128x1[src]

impl Product<Simd<[i128; 1]>> for i128x1[src]

impl Rem<Simd<[i128; 1]>> for i128x1[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<i128> for i128x1[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[i128; 1]>> for i128x1[src]

impl RemAssign<i128> for i128x1[src]

impl Shl<Simd<[i128; 1]>> for i128x1[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<u32> for i128x1[src]

type Output = Self

The resulting type after applying the << operator.

+

impl ShlAssign<Simd<[i128; 1]>> for i128x1[src]

impl ShlAssign<u32> for i128x1[src]

impl Shr<Simd<[i128; 1]>> for i128x1[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<u32> for i128x1[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl ShrAssign<Simd<[i128; 1]>> for i128x1[src]

impl ShrAssign<u32> for i128x1[src]

impl Simd for i128x1[src]

type Element = i128

Element type of the SIMD vector

+

type LanesType = [u32; 1]

The type: [u32; Self::N].

+

impl Sub<Simd<[i128; 1]>> for i128x1[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<i128> for i128x1[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[i128; 1]>> for i128x1[src]

impl SubAssign<i128> for i128x1[src]

impl<'a> Sum<&'a Simd<[i128; 1]>> for i128x1[src]

impl Sum<Simd<[i128; 1]>> for i128x1[src]

impl UpperHex for i128x1[src]

\ No newline at end of file diff --git a/packed_simd/type.i128x2.html b/packed_simd/type.i128x2.html new file mode 100644 index 000000000..67661af4a --- /dev/null +++ b/packed_simd/type.i128x2.html @@ -0,0 +1,258 @@ +packed_simd::i128x2 - Rust

[−][src]Type Definition packed_simd::i128x2

type i128x2 = Simd<[i128; 2]>;

A 256-bit vector with 2 i128 lanes.

+

Implementations

impl i128x2[src]

pub const fn new(x0: i128, x1: i128) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: i128) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> i128[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> i128[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: i128) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: i128) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl i128x2[src]

pub fn rotate_left(self, n: i128x2) -> i128x2[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: i128x2) -> i128x2[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl i128x2[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl i128x2[src]

pub fn wrapping_sum(self) -> i128[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> i128[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl i128x2[src]

pub fn max_element(self) -> i128[src]

Largest vector element value.

+

pub fn min_element(self) -> i128[src]

Smallest vector element value.

+

impl i128x2[src]

pub fn and(self) -> i128[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> i128[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> i128[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl i128x2[src]

pub fn from_slice_aligned(slice: &[i128]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[i128]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[i128]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[i128]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl i128x2[src]

pub fn write_to_slice_aligned(self, slice: &mut [i128])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [i128])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [i128])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [i128])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl i128x2[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl i128x2[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl i128x2[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl i128x2[src]

pub fn eq(self, other: Self) -> m128x2[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m128x2[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m128x2[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m128x2[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m128x2[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m128x2[src]

Lane-wise greater-than-or-equals comparison.

+

impl i128x2[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<i128x2>[src]

Returns a wrapper that implements PartialOrd.

+

impl i128x2[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<i128x2>[src]

Returns a wrapper that implements Ord.

+

impl i128x2[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl Add<Simd<[i128; 2]>> for i128x2[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<i128> for i128x2[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[i128; 2]>> for i128x2[src]

impl AddAssign<i128> for i128x2[src]

impl Binary for i128x2[src]

impl BitAnd<Simd<[i128; 2]>> for i128x2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<i128> for i128x2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[i128; 2]>> for i128x2[src]

impl BitAndAssign<i128> for i128x2[src]

impl BitOr<Simd<[i128; 2]>> for i128x2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<i128> for i128x2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[i128; 2]>> for i128x2[src]

impl BitOrAssign<i128> for i128x2[src]

impl BitXor<Simd<[i128; 2]>> for i128x2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<i128> for i128x2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[i128; 2]>> for i128x2[src]

impl BitXorAssign<i128> for i128x2[src]

impl Debug for i128x2[src]

impl Default for i128x2[src]

impl Div<Simd<[i128; 2]>> for i128x2[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<i128> for i128x2[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[i128; 2]>> for i128x2[src]

impl DivAssign<i128> for i128x2[src]

impl Eq for i128x2[src]

impl From<[i128; 2]> for i128x2[src]

impl From<Simd<[i16; 2]>> for i128x2[src]

impl From<Simd<[i32; 2]>> for i128x2[src]

impl From<Simd<[i64; 2]>> for i128x2[src]

impl From<Simd<[i8; 2]>> for i128x2[src]

impl From<Simd<[u16; 2]>> for i128x2[src]

impl From<Simd<[u32; 2]>> for i128x2[src]

impl From<Simd<[u64; 2]>> for i128x2[src]

impl From<Simd<[u8; 2]>> for i128x2[src]

impl FromBits<Simd<[f32; 8]>> for i128x2[src]

impl FromBits<Simd<[f64; 4]>> for i128x2[src]

impl FromBits<Simd<[i16; 16]>> for i128x2[src]

impl FromBits<Simd<[i32; 8]>> for i128x2[src]

impl FromBits<Simd<[i64; 4]>> for i128x2[src]

impl FromBits<Simd<[i8; 32]>> for i128x2[src]

impl FromBits<Simd<[m128; 2]>> for i128x2[src]

impl FromBits<Simd<[m16; 16]>> for i128x2[src]

impl FromBits<Simd<[m32; 8]>> for i128x2[src]

impl FromBits<Simd<[m64; 4]>> for i128x2[src]

impl FromBits<Simd<[m8; 32]>> for i128x2[src]

impl FromBits<Simd<[u128; 2]>> for i128x2[src]

impl FromBits<Simd<[u16; 16]>> for i128x2[src]

impl FromBits<Simd<[u32; 8]>> for i128x2[src]

impl FromBits<Simd<[u64; 4]>> for i128x2[src]

impl FromBits<Simd<[u8; 32]>> for i128x2[src]

impl FromBits<__m256> for i128x2[src]

impl FromBits<__m256d> for i128x2[src]

impl FromBits<__m256i> for i128x2[src]

impl FromCast<Simd<[f32; 2]>> for i128x2[src]

impl FromCast<Simd<[f64; 2]>> for i128x2[src]

impl FromCast<Simd<[i16; 2]>> for i128x2[src]

impl FromCast<Simd<[i32; 2]>> for i128x2[src]

impl FromCast<Simd<[i64; 2]>> for i128x2[src]

impl FromCast<Simd<[i8; 2]>> for i128x2[src]

impl FromCast<Simd<[isize; 2]>> for i128x2[src]

impl FromCast<Simd<[m128; 2]>> for i128x2[src]

impl FromCast<Simd<[m16; 2]>> for i128x2[src]

impl FromCast<Simd<[m32; 2]>> for i128x2[src]

impl FromCast<Simd<[m64; 2]>> for i128x2[src]

impl FromCast<Simd<[m8; 2]>> for i128x2[src]

impl FromCast<Simd<[msize; 2]>> for i128x2[src]

impl FromCast<Simd<[u128; 2]>> for i128x2[src]

impl FromCast<Simd<[u16; 2]>> for i128x2[src]

impl FromCast<Simd<[u32; 2]>> for i128x2[src]

impl FromCast<Simd<[u64; 2]>> for i128x2[src]

impl FromCast<Simd<[u8; 2]>> for i128x2[src]

impl FromCast<Simd<[usize; 2]>> for i128x2[src]

impl Hash for i128x2[src]

impl LowerHex for i128x2[src]

impl Mul<Simd<[i128; 2]>> for i128x2[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<i128> for i128x2[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[i128; 2]>> for i128x2[src]

impl MulAssign<i128> for i128x2[src]

impl Neg for i128x2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Not for i128x2[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl Octal for i128x2[src]

impl PartialEq<Simd<[i128; 2]>> for i128x2[src]

impl<'a> Product<&'a Simd<[i128; 2]>> for i128x2[src]

impl Product<Simd<[i128; 2]>> for i128x2[src]

impl Rem<Simd<[i128; 2]>> for i128x2[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<i128> for i128x2[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[i128; 2]>> for i128x2[src]

impl RemAssign<i128> for i128x2[src]

impl Shl<Simd<[i128; 2]>> for i128x2[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<u32> for i128x2[src]

type Output = Self

The resulting type after applying the << operator.

+

impl ShlAssign<Simd<[i128; 2]>> for i128x2[src]

impl ShlAssign<u32> for i128x2[src]

impl Shr<Simd<[i128; 2]>> for i128x2[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<u32> for i128x2[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl ShrAssign<Simd<[i128; 2]>> for i128x2[src]

impl ShrAssign<u32> for i128x2[src]

impl Simd for i128x2[src]

type Element = i128

Element type of the SIMD vector

+

type LanesType = [u32; 2]

The type: [u32; Self::N].

+

impl Sub<Simd<[i128; 2]>> for i128x2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<i128> for i128x2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[i128; 2]>> for i128x2[src]

impl SubAssign<i128> for i128x2[src]

impl<'a> Sum<&'a Simd<[i128; 2]>> for i128x2[src]

impl Sum<Simd<[i128; 2]>> for i128x2[src]

impl UpperHex for i128x2[src]

\ No newline at end of file diff --git a/packed_simd/type.i128x4.html b/packed_simd/type.i128x4.html new file mode 100644 index 000000000..a2cfeecac --- /dev/null +++ b/packed_simd/type.i128x4.html @@ -0,0 +1,255 @@ +packed_simd::i128x4 - Rust

[−][src]Type Definition packed_simd::i128x4

type i128x4 = Simd<[i128; 4]>;

A 512-bit vector with 4 i128 lanes.

+

Implementations

impl i128x4[src]

pub const fn new(x0: i128, x1: i128, x2: i128, x3: i128) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: i128) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> i128[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> i128[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: i128) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: i128) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl i128x4[src]

pub fn rotate_left(self, n: i128x4) -> i128x4[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: i128x4) -> i128x4[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl i128x4[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl i128x4[src]

pub fn wrapping_sum(self) -> i128[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> i128[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl i128x4[src]

pub fn max_element(self) -> i128[src]

Largest vector element value.

+

pub fn min_element(self) -> i128[src]

Smallest vector element value.

+

impl i128x4[src]

pub fn and(self) -> i128[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> i128[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> i128[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl i128x4[src]

pub fn from_slice_aligned(slice: &[i128]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[i128]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[i128]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[i128]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl i128x4[src]

pub fn write_to_slice_aligned(self, slice: &mut [i128])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [i128])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [i128])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [i128])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl i128x4[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl i128x4[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl i128x4[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl i128x4[src]

pub fn eq(self, other: Self) -> m128x4[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m128x4[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m128x4[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m128x4[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m128x4[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m128x4[src]

Lane-wise greater-than-or-equals comparison.

+

impl i128x4[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<i128x4>[src]

Returns a wrapper that implements PartialOrd.

+

impl i128x4[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<i128x4>[src]

Returns a wrapper that implements Ord.

+

impl i128x4[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl Add<Simd<[i128; 4]>> for i128x4[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<i128> for i128x4[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[i128; 4]>> for i128x4[src]

impl AddAssign<i128> for i128x4[src]

impl Binary for i128x4[src]

impl BitAnd<Simd<[i128; 4]>> for i128x4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<i128> for i128x4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[i128; 4]>> for i128x4[src]

impl BitAndAssign<i128> for i128x4[src]

impl BitOr<Simd<[i128; 4]>> for i128x4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<i128> for i128x4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[i128; 4]>> for i128x4[src]

impl BitOrAssign<i128> for i128x4[src]

impl BitXor<Simd<[i128; 4]>> for i128x4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<i128> for i128x4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[i128; 4]>> for i128x4[src]

impl BitXorAssign<i128> for i128x4[src]

impl Debug for i128x4[src]

impl Default for i128x4[src]

impl Div<Simd<[i128; 4]>> for i128x4[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<i128> for i128x4[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[i128; 4]>> for i128x4[src]

impl DivAssign<i128> for i128x4[src]

impl Eq for i128x4[src]

impl From<[i128; 4]> for i128x4[src]

impl From<Simd<[i16; 4]>> for i128x4[src]

impl From<Simd<[i32; 4]>> for i128x4[src]

impl From<Simd<[i64; 4]>> for i128x4[src]

impl From<Simd<[i8; 4]>> for i128x4[src]

impl From<Simd<[u16; 4]>> for i128x4[src]

impl From<Simd<[u32; 4]>> for i128x4[src]

impl From<Simd<[u64; 4]>> for i128x4[src]

impl From<Simd<[u8; 4]>> for i128x4[src]

impl FromBits<Simd<[f32; 16]>> for i128x4[src]

impl FromBits<Simd<[f64; 8]>> for i128x4[src]

impl FromBits<Simd<[i16; 32]>> for i128x4[src]

impl FromBits<Simd<[i32; 16]>> for i128x4[src]

impl FromBits<Simd<[i64; 8]>> for i128x4[src]

impl FromBits<Simd<[i8; 64]>> for i128x4[src]

impl FromBits<Simd<[m128; 4]>> for i128x4[src]

impl FromBits<Simd<[m16; 32]>> for i128x4[src]

impl FromBits<Simd<[m32; 16]>> for i128x4[src]

impl FromBits<Simd<[m64; 8]>> for i128x4[src]

impl FromBits<Simd<[m8; 64]>> for i128x4[src]

impl FromBits<Simd<[u128; 4]>> for i128x4[src]

impl FromBits<Simd<[u16; 32]>> for i128x4[src]

impl FromBits<Simd<[u32; 16]>> for i128x4[src]

impl FromBits<Simd<[u64; 8]>> for i128x4[src]

impl FromBits<Simd<[u8; 64]>> for i128x4[src]

impl FromCast<Simd<[f32; 4]>> for i128x4[src]

impl FromCast<Simd<[f64; 4]>> for i128x4[src]

impl FromCast<Simd<[i16; 4]>> for i128x4[src]

impl FromCast<Simd<[i32; 4]>> for i128x4[src]

impl FromCast<Simd<[i64; 4]>> for i128x4[src]

impl FromCast<Simd<[i8; 4]>> for i128x4[src]

impl FromCast<Simd<[isize; 4]>> for i128x4[src]

impl FromCast<Simd<[m128; 4]>> for i128x4[src]

impl FromCast<Simd<[m16; 4]>> for i128x4[src]

impl FromCast<Simd<[m32; 4]>> for i128x4[src]

impl FromCast<Simd<[m64; 4]>> for i128x4[src]

impl FromCast<Simd<[m8; 4]>> for i128x4[src]

impl FromCast<Simd<[msize; 4]>> for i128x4[src]

impl FromCast<Simd<[u128; 4]>> for i128x4[src]

impl FromCast<Simd<[u16; 4]>> for i128x4[src]

impl FromCast<Simd<[u32; 4]>> for i128x4[src]

impl FromCast<Simd<[u64; 4]>> for i128x4[src]

impl FromCast<Simd<[u8; 4]>> for i128x4[src]

impl FromCast<Simd<[usize; 4]>> for i128x4[src]

impl Hash for i128x4[src]

impl LowerHex for i128x4[src]

impl Mul<Simd<[i128; 4]>> for i128x4[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<i128> for i128x4[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[i128; 4]>> for i128x4[src]

impl MulAssign<i128> for i128x4[src]

impl Neg for i128x4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Not for i128x4[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl Octal for i128x4[src]

impl PartialEq<Simd<[i128; 4]>> for i128x4[src]

impl<'a> Product<&'a Simd<[i128; 4]>> for i128x4[src]

impl Product<Simd<[i128; 4]>> for i128x4[src]

impl Rem<Simd<[i128; 4]>> for i128x4[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<i128> for i128x4[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[i128; 4]>> for i128x4[src]

impl RemAssign<i128> for i128x4[src]

impl Shl<Simd<[i128; 4]>> for i128x4[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<u32> for i128x4[src]

type Output = Self

The resulting type after applying the << operator.

+

impl ShlAssign<Simd<[i128; 4]>> for i128x4[src]

impl ShlAssign<u32> for i128x4[src]

impl Shr<Simd<[i128; 4]>> for i128x4[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<u32> for i128x4[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl ShrAssign<Simd<[i128; 4]>> for i128x4[src]

impl ShrAssign<u32> for i128x4[src]

impl Simd for i128x4[src]

type Element = i128

Element type of the SIMD vector

+

type LanesType = [u32; 4]

The type: [u32; Self::N].

+

impl Sub<Simd<[i128; 4]>> for i128x4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<i128> for i128x4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[i128; 4]>> for i128x4[src]

impl SubAssign<i128> for i128x4[src]

impl<'a> Sum<&'a Simd<[i128; 4]>> for i128x4[src]

impl Sum<Simd<[i128; 4]>> for i128x4[src]

impl UpperHex for i128x4[src]

\ No newline at end of file diff --git a/packed_simd/type.i16x16.html b/packed_simd/type.i16x16.html new file mode 100644 index 000000000..2345e0c28 --- /dev/null +++ b/packed_simd/type.i16x16.html @@ -0,0 +1,242 @@ +packed_simd::i16x16 - Rust

[−][src]Type Definition packed_simd::i16x16

type i16x16 = Simd<[i16; 16]>;

A 256-bit vector with 16 i16 lanes.

+

Implementations

impl i16x16[src]

pub const fn new(
    x0: i16,
    x1: i16,
    x2: i16,
    x3: i16,
    x4: i16,
    x5: i16,
    x6: i16,
    x7: i16,
    x8: i16,
    x9: i16,
    x10: i16,
    x11: i16,
    x12: i16,
    x13: i16,
    x14: i16,
    x15: i16
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: i16) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> i16[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> i16[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: i16) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: i16) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl i16x16[src]

pub fn rotate_left(self, n: i16x16) -> i16x16[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: i16x16) -> i16x16[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl i16x16[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl i16x16[src]

pub fn wrapping_sum(self) -> i16[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> i16[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl i16x16[src]

pub fn max_element(self) -> i16[src]

Largest vector element value.

+

pub fn min_element(self) -> i16[src]

Smallest vector element value.

+

impl i16x16[src]

pub fn and(self) -> i16[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> i16[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> i16[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl i16x16[src]

pub fn from_slice_aligned(slice: &[i16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[i16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[i16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[i16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl i16x16[src]

pub fn write_to_slice_aligned(self, slice: &mut [i16])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [i16])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [i16])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [i16])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl i16x16[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl i16x16[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl i16x16[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl i16x16[src]

pub fn eq(self, other: Self) -> m16x16[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m16x16[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m16x16[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m16x16[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m16x16[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m16x16[src]

Lane-wise greater-than-or-equals comparison.

+

impl i16x16[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<i16x16>[src]

Returns a wrapper that implements PartialOrd.

+

impl i16x16[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<i16x16>[src]

Returns a wrapper that implements Ord.

+

impl i16x16[src]

pub fn bitmask(self) -> u16[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl Add<Simd<[i16; 16]>> for i16x16[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<i16> for i16x16[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[i16; 16]>> for i16x16[src]

impl AddAssign<i16> for i16x16[src]

impl Binary for i16x16[src]

impl BitAnd<Simd<[i16; 16]>> for i16x16[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<i16> for i16x16[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[i16; 16]>> for i16x16[src]

impl BitAndAssign<i16> for i16x16[src]

impl BitOr<Simd<[i16; 16]>> for i16x16[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<i16> for i16x16[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[i16; 16]>> for i16x16[src]

impl BitOrAssign<i16> for i16x16[src]

impl BitXor<Simd<[i16; 16]>> for i16x16[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<i16> for i16x16[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[i16; 16]>> for i16x16[src]

impl BitXorAssign<i16> for i16x16[src]

impl Debug for i16x16[src]

impl Default for i16x16[src]

impl Div<Simd<[i16; 16]>> for i16x16[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<i16> for i16x16[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[i16; 16]>> for i16x16[src]

impl DivAssign<i16> for i16x16[src]

impl Eq for i16x16[src]

impl From<[i16; 16]> for i16x16[src]

impl From<Simd<[i8; 16]>> for i16x16[src]

impl From<Simd<[u8; 16]>> for i16x16[src]

impl FromBits<Simd<[f32; 8]>> for i16x16[src]

impl FromBits<Simd<[f64; 4]>> for i16x16[src]

impl FromBits<Simd<[i128; 2]>> for i16x16[src]

impl FromBits<Simd<[i32; 8]>> for i16x16[src]

impl FromBits<Simd<[i64; 4]>> for i16x16[src]

impl FromBits<Simd<[i8; 32]>> for i16x16[src]

impl FromBits<Simd<[m128; 2]>> for i16x16[src]

impl FromBits<Simd<[m16; 16]>> for i16x16[src]

impl FromBits<Simd<[m32; 8]>> for i16x16[src]

impl FromBits<Simd<[m64; 4]>> for i16x16[src]

impl FromBits<Simd<[m8; 32]>> for i16x16[src]

impl FromBits<Simd<[u128; 2]>> for i16x16[src]

impl FromBits<Simd<[u16; 16]>> for i16x16[src]

impl FromBits<Simd<[u32; 8]>> for i16x16[src]

impl FromBits<Simd<[u64; 4]>> for i16x16[src]

impl FromBits<Simd<[u8; 32]>> for i16x16[src]

impl FromBits<__m256> for i16x16[src]

impl FromBits<__m256d> for i16x16[src]

impl FromBits<__m256i> for i16x16[src]

impl FromCast<Simd<[f32; 16]>> for i16x16[src]

impl FromCast<Simd<[i32; 16]>> for i16x16[src]

impl FromCast<Simd<[i8; 16]>> for i16x16[src]

impl FromCast<Simd<[m16; 16]>> for i16x16[src]

impl FromCast<Simd<[m32; 16]>> for i16x16[src]

impl FromCast<Simd<[m8; 16]>> for i16x16[src]

impl FromCast<Simd<[u16; 16]>> for i16x16[src]

impl FromCast<Simd<[u32; 16]>> for i16x16[src]

impl FromCast<Simd<[u8; 16]>> for i16x16[src]

impl Hash for i16x16[src]

impl LowerHex for i16x16[src]

impl Mul<Simd<[i16; 16]>> for i16x16[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<i16> for i16x16[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[i16; 16]>> for i16x16[src]

impl MulAssign<i16> for i16x16[src]

impl Neg for i16x16[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Not for i16x16[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl Octal for i16x16[src]

impl PartialEq<Simd<[i16; 16]>> for i16x16[src]

impl<'a> Product<&'a Simd<[i16; 16]>> for i16x16[src]

impl Product<Simd<[i16; 16]>> for i16x16[src]

impl Rem<Simd<[i16; 16]>> for i16x16[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<i16> for i16x16[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[i16; 16]>> for i16x16[src]

impl RemAssign<i16> for i16x16[src]

impl Shl<Simd<[i16; 16]>> for i16x16[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<u32> for i16x16[src]

type Output = Self

The resulting type after applying the << operator.

+

impl ShlAssign<Simd<[i16; 16]>> for i16x16[src]

impl ShlAssign<u32> for i16x16[src]

impl Shr<Simd<[i16; 16]>> for i16x16[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<u32> for i16x16[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl ShrAssign<Simd<[i16; 16]>> for i16x16[src]

impl ShrAssign<u32> for i16x16[src]

impl Simd for i16x16[src]

type Element = i16

Element type of the SIMD vector

+

type LanesType = [u32; 16]

The type: [u32; Self::N].

+

impl Sub<Simd<[i16; 16]>> for i16x16[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<i16> for i16x16[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[i16; 16]>> for i16x16[src]

impl SubAssign<i16> for i16x16[src]

impl<'a> Sum<&'a Simd<[i16; 16]>> for i16x16[src]

impl Sum<Simd<[i16; 16]>> for i16x16[src]

impl UpperHex for i16x16[src]

\ No newline at end of file diff --git a/packed_simd/type.i16x2.html b/packed_simd/type.i16x2.html new file mode 100644 index 000000000..979ee9587 --- /dev/null +++ b/packed_simd/type.i16x2.html @@ -0,0 +1,238 @@ +packed_simd::i16x2 - Rust

[−][src]Type Definition packed_simd::i16x2

type i16x2 = Simd<[i16; 2]>;

A 32-bit vector with 2 i16 lanes.

+

Implementations

impl i16x2[src]

pub const fn new(x0: i16, x1: i16) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: i16) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> i16[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> i16[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: i16) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: i16) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl i16x2[src]

pub fn rotate_left(self, n: i16x2) -> i16x2[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: i16x2) -> i16x2[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl i16x2[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl i16x2[src]

pub fn wrapping_sum(self) -> i16[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> i16[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl i16x2[src]

pub fn max_element(self) -> i16[src]

Largest vector element value.

+

pub fn min_element(self) -> i16[src]

Smallest vector element value.

+

impl i16x2[src]

pub fn and(self) -> i16[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> i16[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> i16[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl i16x2[src]

pub fn from_slice_aligned(slice: &[i16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[i16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[i16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[i16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl i16x2[src]

pub fn write_to_slice_aligned(self, slice: &mut [i16])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [i16])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [i16])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [i16])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl i16x2[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl i16x2[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl i16x2[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl i16x2[src]

pub fn eq(self, other: Self) -> m16x2[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m16x2[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m16x2[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m16x2[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m16x2[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m16x2[src]

Lane-wise greater-than-or-equals comparison.

+

impl i16x2[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<i16x2>[src]

Returns a wrapper that implements PartialOrd.

+

impl i16x2[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<i16x2>[src]

Returns a wrapper that implements Ord.

+

impl i16x2[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl Add<Simd<[i16; 2]>> for i16x2[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<i16> for i16x2[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[i16; 2]>> for i16x2[src]

impl AddAssign<i16> for i16x2[src]

impl Binary for i16x2[src]

impl BitAnd<Simd<[i16; 2]>> for i16x2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<i16> for i16x2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[i16; 2]>> for i16x2[src]

impl BitAndAssign<i16> for i16x2[src]

impl BitOr<Simd<[i16; 2]>> for i16x2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<i16> for i16x2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[i16; 2]>> for i16x2[src]

impl BitOrAssign<i16> for i16x2[src]

impl BitXor<Simd<[i16; 2]>> for i16x2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<i16> for i16x2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[i16; 2]>> for i16x2[src]

impl BitXorAssign<i16> for i16x2[src]

impl Debug for i16x2[src]

impl Default for i16x2[src]

impl Div<Simd<[i16; 2]>> for i16x2[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<i16> for i16x2[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[i16; 2]>> for i16x2[src]

impl DivAssign<i16> for i16x2[src]

impl Eq for i16x2[src]

impl From<[i16; 2]> for i16x2[src]

impl From<Simd<[i8; 2]>> for i16x2[src]

impl From<Simd<[u8; 2]>> for i16x2[src]

impl FromBits<Simd<[i8; 4]>> for i16x2[src]

impl FromBits<Simd<[m16; 2]>> for i16x2[src]

impl FromBits<Simd<[m8; 4]>> for i16x2[src]

impl FromBits<Simd<[u16; 2]>> for i16x2[src]

impl FromBits<Simd<[u8; 4]>> for i16x2[src]

impl FromCast<Simd<[f32; 2]>> for i16x2[src]

impl FromCast<Simd<[f64; 2]>> for i16x2[src]

impl FromCast<Simd<[i128; 2]>> for i16x2[src]

impl FromCast<Simd<[i32; 2]>> for i16x2[src]

impl FromCast<Simd<[i64; 2]>> for i16x2[src]

impl FromCast<Simd<[i8; 2]>> for i16x2[src]

impl FromCast<Simd<[isize; 2]>> for i16x2[src]

impl FromCast<Simd<[m128; 2]>> for i16x2[src]

impl FromCast<Simd<[m16; 2]>> for i16x2[src]

impl FromCast<Simd<[m32; 2]>> for i16x2[src]

impl FromCast<Simd<[m64; 2]>> for i16x2[src]

impl FromCast<Simd<[m8; 2]>> for i16x2[src]

impl FromCast<Simd<[msize; 2]>> for i16x2[src]

impl FromCast<Simd<[u128; 2]>> for i16x2[src]

impl FromCast<Simd<[u16; 2]>> for i16x2[src]

impl FromCast<Simd<[u32; 2]>> for i16x2[src]

impl FromCast<Simd<[u64; 2]>> for i16x2[src]

impl FromCast<Simd<[u8; 2]>> for i16x2[src]

impl FromCast<Simd<[usize; 2]>> for i16x2[src]

impl Hash for i16x2[src]

impl LowerHex for i16x2[src]

impl Mul<Simd<[i16; 2]>> for i16x2[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<i16> for i16x2[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[i16; 2]>> for i16x2[src]

impl MulAssign<i16> for i16x2[src]

impl Neg for i16x2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Not for i16x2[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl Octal for i16x2[src]

impl PartialEq<Simd<[i16; 2]>> for i16x2[src]

impl<'a> Product<&'a Simd<[i16; 2]>> for i16x2[src]

impl Product<Simd<[i16; 2]>> for i16x2[src]

impl Rem<Simd<[i16; 2]>> for i16x2[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<i16> for i16x2[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[i16; 2]>> for i16x2[src]

impl RemAssign<i16> for i16x2[src]

impl Shl<Simd<[i16; 2]>> for i16x2[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<u32> for i16x2[src]

type Output = Self

The resulting type after applying the << operator.

+

impl ShlAssign<Simd<[i16; 2]>> for i16x2[src]

impl ShlAssign<u32> for i16x2[src]

impl Shr<Simd<[i16; 2]>> for i16x2[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<u32> for i16x2[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl ShrAssign<Simd<[i16; 2]>> for i16x2[src]

impl ShrAssign<u32> for i16x2[src]

impl Simd for i16x2[src]

type Element = i16

Element type of the SIMD vector

+

type LanesType = [u32; 2]

The type: [u32; Self::N].

+

impl Sub<Simd<[i16; 2]>> for i16x2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<i16> for i16x2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[i16; 2]>> for i16x2[src]

impl SubAssign<i16> for i16x2[src]

impl<'a> Sum<&'a Simd<[i16; 2]>> for i16x2[src]

impl Sum<Simd<[i16; 2]>> for i16x2[src]

impl UpperHex for i16x2[src]

\ No newline at end of file diff --git a/packed_simd/type.i16x32.html b/packed_simd/type.i16x32.html new file mode 100644 index 000000000..5b6465588 --- /dev/null +++ b/packed_simd/type.i16x32.html @@ -0,0 +1,235 @@ +packed_simd::i16x32 - Rust

[−][src]Type Definition packed_simd::i16x32

type i16x32 = Simd<[i16; 32]>;

A 512-bit vector with 32 i16 lanes.

+

Implementations

impl i16x32[src]

pub const fn new(
    x0: i16,
    x1: i16,
    x2: i16,
    x3: i16,
    x4: i16,
    x5: i16,
    x6: i16,
    x7: i16,
    x8: i16,
    x9: i16,
    x10: i16,
    x11: i16,
    x12: i16,
    x13: i16,
    x14: i16,
    x15: i16,
    x16: i16,
    x17: i16,
    x18: i16,
    x19: i16,
    x20: i16,
    x21: i16,
    x22: i16,
    x23: i16,
    x24: i16,
    x25: i16,
    x26: i16,
    x27: i16,
    x28: i16,
    x29: i16,
    x30: i16,
    x31: i16
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: i16) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> i16[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> i16[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: i16) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: i16) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl i16x32[src]

pub fn rotate_left(self, n: i16x32) -> i16x32[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: i16x32) -> i16x32[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl i16x32[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl i16x32[src]

pub fn wrapping_sum(self) -> i16[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> i16[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl i16x32[src]

pub fn max_element(self) -> i16[src]

Largest vector element value.

+

pub fn min_element(self) -> i16[src]

Smallest vector element value.

+

impl i16x32[src]

pub fn and(self) -> i16[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> i16[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> i16[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl i16x32[src]

pub fn from_slice_aligned(slice: &[i16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[i16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[i16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[i16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl i16x32[src]

pub fn write_to_slice_aligned(self, slice: &mut [i16])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [i16])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [i16])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [i16])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl i16x32[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl i16x32[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl i16x32[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl i16x32[src]

pub fn eq(self, other: Self) -> m16x32[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m16x32[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m16x32[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m16x32[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m16x32[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m16x32[src]

Lane-wise greater-than-or-equals comparison.

+

impl i16x32[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<i16x32>[src]

Returns a wrapper that implements PartialOrd.

+

impl i16x32[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<i16x32>[src]

Returns a wrapper that implements Ord.

+

impl i16x32[src]

pub fn bitmask(self) -> u32[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl Add<Simd<[i16; 32]>> for i16x32[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<i16> for i16x32[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[i16; 32]>> for i16x32[src]

impl AddAssign<i16> for i16x32[src]

impl Binary for i16x32[src]

impl BitAnd<Simd<[i16; 32]>> for i16x32[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<i16> for i16x32[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[i16; 32]>> for i16x32[src]

impl BitAndAssign<i16> for i16x32[src]

impl BitOr<Simd<[i16; 32]>> for i16x32[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<i16> for i16x32[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[i16; 32]>> for i16x32[src]

impl BitOrAssign<i16> for i16x32[src]

impl BitXor<Simd<[i16; 32]>> for i16x32[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<i16> for i16x32[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[i16; 32]>> for i16x32[src]

impl BitXorAssign<i16> for i16x32[src]

impl Debug for i16x32[src]

impl Default for i16x32[src]

impl Div<Simd<[i16; 32]>> for i16x32[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<i16> for i16x32[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[i16; 32]>> for i16x32[src]

impl DivAssign<i16> for i16x32[src]

impl Eq for i16x32[src]

impl From<[i16; 32]> for i16x32[src]

impl From<Simd<[i8; 32]>> for i16x32[src]

impl From<Simd<[u8; 32]>> for i16x32[src]

impl FromBits<Simd<[f32; 16]>> for i16x32[src]

impl FromBits<Simd<[f64; 8]>> for i16x32[src]

impl FromBits<Simd<[i128; 4]>> for i16x32[src]

impl FromBits<Simd<[i32; 16]>> for i16x32[src]

impl FromBits<Simd<[i64; 8]>> for i16x32[src]

impl FromBits<Simd<[i8; 64]>> for i16x32[src]

impl FromBits<Simd<[m128; 4]>> for i16x32[src]

impl FromBits<Simd<[m16; 32]>> for i16x32[src]

impl FromBits<Simd<[m32; 16]>> for i16x32[src]

impl FromBits<Simd<[m64; 8]>> for i16x32[src]

impl FromBits<Simd<[m8; 64]>> for i16x32[src]

impl FromBits<Simd<[u128; 4]>> for i16x32[src]

impl FromBits<Simd<[u16; 32]>> for i16x32[src]

impl FromBits<Simd<[u32; 16]>> for i16x32[src]

impl FromBits<Simd<[u64; 8]>> for i16x32[src]

impl FromBits<Simd<[u8; 64]>> for i16x32[src]

impl FromCast<Simd<[i8; 32]>> for i16x32[src]

impl FromCast<Simd<[m16; 32]>> for i16x32[src]

impl FromCast<Simd<[m8; 32]>> for i16x32[src]

impl FromCast<Simd<[u16; 32]>> for i16x32[src]

impl FromCast<Simd<[u8; 32]>> for i16x32[src]

impl Hash for i16x32[src]

impl LowerHex for i16x32[src]

impl Mul<Simd<[i16; 32]>> for i16x32[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<i16> for i16x32[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[i16; 32]>> for i16x32[src]

impl MulAssign<i16> for i16x32[src]

impl Neg for i16x32[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Not for i16x32[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl Octal for i16x32[src]

impl PartialEq<Simd<[i16; 32]>> for i16x32[src]

impl<'a> Product<&'a Simd<[i16; 32]>> for i16x32[src]

impl Product<Simd<[i16; 32]>> for i16x32[src]

impl Rem<Simd<[i16; 32]>> for i16x32[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<i16> for i16x32[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[i16; 32]>> for i16x32[src]

impl RemAssign<i16> for i16x32[src]

impl Shl<Simd<[i16; 32]>> for i16x32[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<u32> for i16x32[src]

type Output = Self

The resulting type after applying the << operator.

+

impl ShlAssign<Simd<[i16; 32]>> for i16x32[src]

impl ShlAssign<u32> for i16x32[src]

impl Shr<Simd<[i16; 32]>> for i16x32[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<u32> for i16x32[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl ShrAssign<Simd<[i16; 32]>> for i16x32[src]

impl ShrAssign<u32> for i16x32[src]

impl Simd for i16x32[src]

type Element = i16

Element type of the SIMD vector

+

type LanesType = [u32; 32]

The type: [u32; Self::N].

+

impl Sub<Simd<[i16; 32]>> for i16x32[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<i16> for i16x32[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[i16; 32]>> for i16x32[src]

impl SubAssign<i16> for i16x32[src]

impl<'a> Sum<&'a Simd<[i16; 32]>> for i16x32[src]

impl Sum<Simd<[i16; 32]>> for i16x32[src]

impl UpperHex for i16x32[src]

\ No newline at end of file diff --git a/packed_simd/type.i16x4.html b/packed_simd/type.i16x4.html new file mode 100644 index 000000000..81a87fecf --- /dev/null +++ b/packed_simd/type.i16x4.html @@ -0,0 +1,243 @@ +packed_simd::i16x4 - Rust

[−][src]Type Definition packed_simd::i16x4

type i16x4 = Simd<[i16; 4]>;

A 64-bit vector with 4 i16 lanes.

+

Implementations

impl i16x4[src]

pub const fn new(x0: i16, x1: i16, x2: i16, x3: i16) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: i16) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> i16[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> i16[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: i16) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: i16) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl i16x4[src]

pub fn rotate_left(self, n: i16x4) -> i16x4[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: i16x4) -> i16x4[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl i16x4[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl i16x4[src]

pub fn wrapping_sum(self) -> i16[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> i16[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl i16x4[src]

pub fn max_element(self) -> i16[src]

Largest vector element value.

+

pub fn min_element(self) -> i16[src]

Smallest vector element value.

+

impl i16x4[src]

pub fn and(self) -> i16[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> i16[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> i16[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl i16x4[src]

pub fn from_slice_aligned(slice: &[i16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[i16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[i16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[i16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl i16x4[src]

pub fn write_to_slice_aligned(self, slice: &mut [i16])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [i16])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [i16])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [i16])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl i16x4[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl i16x4[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl i16x4[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl i16x4[src]

pub fn eq(self, other: Self) -> m16x4[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m16x4[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m16x4[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m16x4[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m16x4[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m16x4[src]

Lane-wise greater-than-or-equals comparison.

+

impl i16x4[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<i16x4>[src]

Returns a wrapper that implements PartialOrd.

+

impl i16x4[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<i16x4>[src]

Returns a wrapper that implements Ord.

+

impl i16x4[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl Add<Simd<[i16; 4]>> for i16x4[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<i16> for i16x4[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[i16; 4]>> for i16x4[src]

impl AddAssign<i16> for i16x4[src]

impl Binary for i16x4[src]

impl BitAnd<Simd<[i16; 4]>> for i16x4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<i16> for i16x4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[i16; 4]>> for i16x4[src]

impl BitAndAssign<i16> for i16x4[src]

impl BitOr<Simd<[i16; 4]>> for i16x4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<i16> for i16x4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[i16; 4]>> for i16x4[src]

impl BitOrAssign<i16> for i16x4[src]

impl BitXor<Simd<[i16; 4]>> for i16x4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<i16> for i16x4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[i16; 4]>> for i16x4[src]

impl BitXorAssign<i16> for i16x4[src]

impl Debug for i16x4[src]

impl Default for i16x4[src]

impl Div<Simd<[i16; 4]>> for i16x4[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<i16> for i16x4[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[i16; 4]>> for i16x4[src]

impl DivAssign<i16> for i16x4[src]

impl Eq for i16x4[src]

impl From<[i16; 4]> for i16x4[src]

impl From<Simd<[i8; 4]>> for i16x4[src]

impl From<Simd<[u8; 4]>> for i16x4[src]

impl FromBits<Simd<[f32; 2]>> for i16x4[src]

impl FromBits<Simd<[i32; 2]>> for i16x4[src]

impl FromBits<Simd<[i8; 8]>> for i16x4[src]

impl FromBits<Simd<[m16; 4]>> for i16x4[src]

impl FromBits<Simd<[m32; 2]>> for i16x4[src]

impl FromBits<Simd<[m8; 8]>> for i16x4[src]

impl FromBits<Simd<[u16; 4]>> for i16x4[src]

impl FromBits<Simd<[u32; 2]>> for i16x4[src]

impl FromBits<Simd<[u8; 8]>> for i16x4[src]

impl FromBits<__m64> for i16x4[src]

impl FromCast<Simd<[f32; 4]>> for i16x4[src]

impl FromCast<Simd<[f64; 4]>> for i16x4[src]

impl FromCast<Simd<[i128; 4]>> for i16x4[src]

impl FromCast<Simd<[i32; 4]>> for i16x4[src]

impl FromCast<Simd<[i64; 4]>> for i16x4[src]

impl FromCast<Simd<[i8; 4]>> for i16x4[src]

impl FromCast<Simd<[isize; 4]>> for i16x4[src]

impl FromCast<Simd<[m128; 4]>> for i16x4[src]

impl FromCast<Simd<[m16; 4]>> for i16x4[src]

impl FromCast<Simd<[m32; 4]>> for i16x4[src]

impl FromCast<Simd<[m64; 4]>> for i16x4[src]

impl FromCast<Simd<[m8; 4]>> for i16x4[src]

impl FromCast<Simd<[msize; 4]>> for i16x4[src]

impl FromCast<Simd<[u128; 4]>> for i16x4[src]

impl FromCast<Simd<[u16; 4]>> for i16x4[src]

impl FromCast<Simd<[u32; 4]>> for i16x4[src]

impl FromCast<Simd<[u64; 4]>> for i16x4[src]

impl FromCast<Simd<[u8; 4]>> for i16x4[src]

impl FromCast<Simd<[usize; 4]>> for i16x4[src]

impl Hash for i16x4[src]

impl LowerHex for i16x4[src]

impl Mul<Simd<[i16; 4]>> for i16x4[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<i16> for i16x4[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[i16; 4]>> for i16x4[src]

impl MulAssign<i16> for i16x4[src]

impl Neg for i16x4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Not for i16x4[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl Octal for i16x4[src]

impl PartialEq<Simd<[i16; 4]>> for i16x4[src]

impl<'a> Product<&'a Simd<[i16; 4]>> for i16x4[src]

impl Product<Simd<[i16; 4]>> for i16x4[src]

impl Rem<Simd<[i16; 4]>> for i16x4[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<i16> for i16x4[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[i16; 4]>> for i16x4[src]

impl RemAssign<i16> for i16x4[src]

impl Shl<Simd<[i16; 4]>> for i16x4[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<u32> for i16x4[src]

type Output = Self

The resulting type after applying the << operator.

+

impl ShlAssign<Simd<[i16; 4]>> for i16x4[src]

impl ShlAssign<u32> for i16x4[src]

impl Shr<Simd<[i16; 4]>> for i16x4[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<u32> for i16x4[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl ShrAssign<Simd<[i16; 4]>> for i16x4[src]

impl ShrAssign<u32> for i16x4[src]

impl Simd for i16x4[src]

type Element = i16

Element type of the SIMD vector

+

type LanesType = [u32; 4]

The type: [u32; Self::N].

+

impl Sub<Simd<[i16; 4]>> for i16x4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<i16> for i16x4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[i16; 4]>> for i16x4[src]

impl SubAssign<i16> for i16x4[src]

impl<'a> Sum<&'a Simd<[i16; 4]>> for i16x4[src]

impl Sum<Simd<[i16; 4]>> for i16x4[src]

impl UpperHex for i16x4[src]

\ No newline at end of file diff --git a/packed_simd/type.i16x8.html b/packed_simd/type.i16x8.html new file mode 100644 index 000000000..3a8366bab --- /dev/null +++ b/packed_simd/type.i16x8.html @@ -0,0 +1,249 @@ +packed_simd::i16x8 - Rust

[−][src]Type Definition packed_simd::i16x8

type i16x8 = Simd<[i16; 8]>;

A 128-bit vector with 8 i16 lanes.

+

Implementations

impl i16x8[src]

pub const fn new(
    x0: i16,
    x1: i16,
    x2: i16,
    x3: i16,
    x4: i16,
    x5: i16,
    x6: i16,
    x7: i16
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: i16) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> i16[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> i16[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: i16) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: i16) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl i16x8[src]

pub fn rotate_left(self, n: i16x8) -> i16x8[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: i16x8) -> i16x8[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl i16x8[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl i16x8[src]

pub fn wrapping_sum(self) -> i16[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> i16[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl i16x8[src]

pub fn max_element(self) -> i16[src]

Largest vector element value.

+

pub fn min_element(self) -> i16[src]

Smallest vector element value.

+

impl i16x8[src]

pub fn and(self) -> i16[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> i16[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> i16[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl i16x8[src]

pub fn from_slice_aligned(slice: &[i16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[i16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[i16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[i16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl i16x8[src]

pub fn write_to_slice_aligned(self, slice: &mut [i16])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [i16])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [i16])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [i16])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl i16x8[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl i16x8[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl i16x8[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl i16x8[src]

pub fn eq(self, other: Self) -> m16x8[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m16x8[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m16x8[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m16x8[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m16x8[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m16x8[src]

Lane-wise greater-than-or-equals comparison.

+

impl i16x8[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<i16x8>[src]

Returns a wrapper that implements PartialOrd.

+

impl i16x8[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<i16x8>[src]

Returns a wrapper that implements Ord.

+

impl i16x8[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl Add<Simd<[i16; 8]>> for i16x8[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<i16> for i16x8[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[i16; 8]>> for i16x8[src]

impl AddAssign<i16> for i16x8[src]

impl Binary for i16x8[src]

impl BitAnd<Simd<[i16; 8]>> for i16x8[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<i16> for i16x8[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[i16; 8]>> for i16x8[src]

impl BitAndAssign<i16> for i16x8[src]

impl BitOr<Simd<[i16; 8]>> for i16x8[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<i16> for i16x8[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[i16; 8]>> for i16x8[src]

impl BitOrAssign<i16> for i16x8[src]

impl BitXor<Simd<[i16; 8]>> for i16x8[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<i16> for i16x8[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[i16; 8]>> for i16x8[src]

impl BitXorAssign<i16> for i16x8[src]

impl Debug for i16x8[src]

impl Default for i16x8[src]

impl Div<Simd<[i16; 8]>> for i16x8[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<i16> for i16x8[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[i16; 8]>> for i16x8[src]

impl DivAssign<i16> for i16x8[src]

impl Eq for i16x8[src]

impl From<[i16; 8]> for i16x8[src]

impl From<Simd<[i8; 8]>> for i16x8[src]

impl From<Simd<[u8; 8]>> for i16x8[src]

impl FromBits<Simd<[f32; 4]>> for i16x8[src]

impl FromBits<Simd<[f64; 2]>> for i16x8[src]

impl FromBits<Simd<[i128; 1]>> for i16x8[src]

impl FromBits<Simd<[i32; 4]>> for i16x8[src]

impl FromBits<Simd<[i64; 2]>> for i16x8[src]

impl FromBits<Simd<[i8; 16]>> for i16x8[src]

impl FromBits<Simd<[m128; 1]>> for i16x8[src]

impl FromBits<Simd<[m16; 8]>> for i16x8[src]

impl FromBits<Simd<[m32; 4]>> for i16x8[src]

impl FromBits<Simd<[m64; 2]>> for i16x8[src]

impl FromBits<Simd<[m8; 16]>> for i16x8[src]

impl FromBits<Simd<[u128; 1]>> for i16x8[src]

impl FromBits<Simd<[u16; 8]>> for i16x8[src]

impl FromBits<Simd<[u32; 4]>> for i16x8[src]

impl FromBits<Simd<[u64; 2]>> for i16x8[src]

impl FromBits<Simd<[u8; 16]>> for i16x8[src]

impl FromBits<__m128> for i16x8[src]

impl FromBits<__m128d> for i16x8[src]

impl FromBits<__m128i> for i16x8[src]

impl FromCast<Simd<[f32; 8]>> for i16x8[src]

impl FromCast<Simd<[f64; 8]>> for i16x8[src]

impl FromCast<Simd<[i32; 8]>> for i16x8[src]

impl FromCast<Simd<[i64; 8]>> for i16x8[src]

impl FromCast<Simd<[i8; 8]>> for i16x8[src]

impl FromCast<Simd<[isize; 8]>> for i16x8[src]

impl FromCast<Simd<[m16; 8]>> for i16x8[src]

impl FromCast<Simd<[m32; 8]>> for i16x8[src]

impl FromCast<Simd<[m64; 8]>> for i16x8[src]

impl FromCast<Simd<[m8; 8]>> for i16x8[src]

impl FromCast<Simd<[msize; 8]>> for i16x8[src]

impl FromCast<Simd<[u16; 8]>> for i16x8[src]

impl FromCast<Simd<[u32; 8]>> for i16x8[src]

impl FromCast<Simd<[u64; 8]>> for i16x8[src]

impl FromCast<Simd<[u8; 8]>> for i16x8[src]

impl FromCast<Simd<[usize; 8]>> for i16x8[src]

impl Hash for i16x8[src]

impl LowerHex for i16x8[src]

impl Mul<Simd<[i16; 8]>> for i16x8[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<i16> for i16x8[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[i16; 8]>> for i16x8[src]

impl MulAssign<i16> for i16x8[src]

impl Neg for i16x8[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Not for i16x8[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl Octal for i16x8[src]

impl PartialEq<Simd<[i16; 8]>> for i16x8[src]

impl<'a> Product<&'a Simd<[i16; 8]>> for i16x8[src]

impl Product<Simd<[i16; 8]>> for i16x8[src]

impl Rem<Simd<[i16; 8]>> for i16x8[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<i16> for i16x8[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[i16; 8]>> for i16x8[src]

impl RemAssign<i16> for i16x8[src]

impl Shl<Simd<[i16; 8]>> for i16x8[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<u32> for i16x8[src]

type Output = Self

The resulting type after applying the << operator.

+

impl ShlAssign<Simd<[i16; 8]>> for i16x8[src]

impl ShlAssign<u32> for i16x8[src]

impl Shr<Simd<[i16; 8]>> for i16x8[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<u32> for i16x8[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl ShrAssign<Simd<[i16; 8]>> for i16x8[src]

impl ShrAssign<u32> for i16x8[src]

impl Simd for i16x8[src]

type Element = i16

Element type of the SIMD vector

+

type LanesType = [u32; 8]

The type: [u32; Self::N].

+

impl Sub<Simd<[i16; 8]>> for i16x8[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<i16> for i16x8[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[i16; 8]>> for i16x8[src]

impl SubAssign<i16> for i16x8[src]

impl<'a> Sum<&'a Simd<[i16; 8]>> for i16x8[src]

impl Sum<Simd<[i16; 8]>> for i16x8[src]

impl UpperHex for i16x8[src]

\ No newline at end of file diff --git a/packed_simd/type.i32x16.html b/packed_simd/type.i32x16.html new file mode 100644 index 000000000..db9d1fc1d --- /dev/null +++ b/packed_simd/type.i32x16.html @@ -0,0 +1,241 @@ +packed_simd::i32x16 - Rust

[−][src]Type Definition packed_simd::i32x16

type i32x16 = Simd<[i32; 16]>;

A 512-bit vector with 16 i32 lanes.

+

Implementations

impl i32x16[src]

pub const fn new(
    x0: i32,
    x1: i32,
    x2: i32,
    x3: i32,
    x4: i32,
    x5: i32,
    x6: i32,
    x7: i32,
    x8: i32,
    x9: i32,
    x10: i32,
    x11: i32,
    x12: i32,
    x13: i32,
    x14: i32,
    x15: i32
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: i32) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> i32[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> i32[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: i32) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: i32) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl i32x16[src]

pub fn rotate_left(self, n: i32x16) -> i32x16[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: i32x16) -> i32x16[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl i32x16[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl i32x16[src]

pub fn wrapping_sum(self) -> i32[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> i32[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl i32x16[src]

pub fn max_element(self) -> i32[src]

Largest vector element value.

+

pub fn min_element(self) -> i32[src]

Smallest vector element value.

+

impl i32x16[src]

pub fn and(self) -> i32[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> i32[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> i32[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl i32x16[src]

pub fn from_slice_aligned(slice: &[i32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[i32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[i32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[i32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl i32x16[src]

pub fn write_to_slice_aligned(self, slice: &mut [i32])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [i32])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [i32])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [i32])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl i32x16[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl i32x16[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl i32x16[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl i32x16[src]

pub fn eq(self, other: Self) -> m32x16[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m32x16[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m32x16[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m32x16[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m32x16[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m32x16[src]

Lane-wise greater-than-or-equals comparison.

+

impl i32x16[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<i32x16>[src]

Returns a wrapper that implements PartialOrd.

+

impl i32x16[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<i32x16>[src]

Returns a wrapper that implements Ord.

+

impl i32x16[src]

pub fn bitmask(self) -> u16[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl Add<Simd<[i32; 16]>> for i32x16[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<i32> for i32x16[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[i32; 16]>> for i32x16[src]

impl AddAssign<i32> for i32x16[src]

impl Binary for i32x16[src]

impl BitAnd<Simd<[i32; 16]>> for i32x16[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<i32> for i32x16[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[i32; 16]>> for i32x16[src]

impl BitAndAssign<i32> for i32x16[src]

impl BitOr<Simd<[i32; 16]>> for i32x16[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<i32> for i32x16[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[i32; 16]>> for i32x16[src]

impl BitOrAssign<i32> for i32x16[src]

impl BitXor<Simd<[i32; 16]>> for i32x16[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<i32> for i32x16[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[i32; 16]>> for i32x16[src]

impl BitXorAssign<i32> for i32x16[src]

impl Debug for i32x16[src]

impl Default for i32x16[src]

impl Div<Simd<[i32; 16]>> for i32x16[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<i32> for i32x16[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[i32; 16]>> for i32x16[src]

impl DivAssign<i32> for i32x16[src]

impl Eq for i32x16[src]

impl From<[i32; 16]> for i32x16[src]

impl From<Simd<[i16; 16]>> for i32x16[src]

impl From<Simd<[i8; 16]>> for i32x16[src]

impl From<Simd<[u16; 16]>> for i32x16[src]

impl From<Simd<[u8; 16]>> for i32x16[src]

impl FromBits<Simd<[f32; 16]>> for i32x16[src]

impl FromBits<Simd<[f64; 8]>> for i32x16[src]

impl FromBits<Simd<[i128; 4]>> for i32x16[src]

impl FromBits<Simd<[i16; 32]>> for i32x16[src]

impl FromBits<Simd<[i64; 8]>> for i32x16[src]

impl FromBits<Simd<[i8; 64]>> for i32x16[src]

impl FromBits<Simd<[m128; 4]>> for i32x16[src]

impl FromBits<Simd<[m16; 32]>> for i32x16[src]

impl FromBits<Simd<[m32; 16]>> for i32x16[src]

impl FromBits<Simd<[m64; 8]>> for i32x16[src]

impl FromBits<Simd<[m8; 64]>> for i32x16[src]

impl FromBits<Simd<[u128; 4]>> for i32x16[src]

impl FromBits<Simd<[u16; 32]>> for i32x16[src]

impl FromBits<Simd<[u32; 16]>> for i32x16[src]

impl FromBits<Simd<[u64; 8]>> for i32x16[src]

impl FromBits<Simd<[u8; 64]>> for i32x16[src]

impl FromCast<Simd<[f32; 16]>> for i32x16[src]

impl FromCast<Simd<[i16; 16]>> for i32x16[src]

impl FromCast<Simd<[i8; 16]>> for i32x16[src]

impl FromCast<Simd<[m16; 16]>> for i32x16[src]

impl FromCast<Simd<[m32; 16]>> for i32x16[src]

impl FromCast<Simd<[m8; 16]>> for i32x16[src]

impl FromCast<Simd<[u16; 16]>> for i32x16[src]

impl FromCast<Simd<[u32; 16]>> for i32x16[src]

impl FromCast<Simd<[u8; 16]>> for i32x16[src]

impl Hash for i32x16[src]

impl LowerHex for i32x16[src]

impl Mul<Simd<[i32; 16]>> for i32x16[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<i32> for i32x16[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[i32; 16]>> for i32x16[src]

impl MulAssign<i32> for i32x16[src]

impl Neg for i32x16[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Not for i32x16[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl Octal for i32x16[src]

impl PartialEq<Simd<[i32; 16]>> for i32x16[src]

impl<'a> Product<&'a Simd<[i32; 16]>> for i32x16[src]

impl Product<Simd<[i32; 16]>> for i32x16[src]

impl Rem<Simd<[i32; 16]>> for i32x16[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<i32> for i32x16[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[i32; 16]>> for i32x16[src]

impl RemAssign<i32> for i32x16[src]

impl Shl<Simd<[i32; 16]>> for i32x16[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<u32> for i32x16[src]

type Output = Self

The resulting type after applying the << operator.

+

impl ShlAssign<Simd<[i32; 16]>> for i32x16[src]

impl ShlAssign<u32> for i32x16[src]

impl Shr<Simd<[i32; 16]>> for i32x16[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<u32> for i32x16[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl ShrAssign<Simd<[i32; 16]>> for i32x16[src]

impl ShrAssign<u32> for i32x16[src]

impl Simd for i32x16[src]

type Element = i32

Element type of the SIMD vector

+

type LanesType = [u32; 16]

The type: [u32; Self::N].

+

impl Sub<Simd<[i32; 16]>> for i32x16[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<i32> for i32x16[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[i32; 16]>> for i32x16[src]

impl SubAssign<i32> for i32x16[src]

impl<'a> Sum<&'a Simd<[i32; 16]>> for i32x16[src]

impl Sum<Simd<[i32; 16]>> for i32x16[src]

impl UpperHex for i32x16[src]

\ No newline at end of file diff --git a/packed_simd/type.i32x2.html b/packed_simd/type.i32x2.html new file mode 100644 index 000000000..1782286c8 --- /dev/null +++ b/packed_simd/type.i32x2.html @@ -0,0 +1,245 @@ +packed_simd::i32x2 - Rust

[−][src]Type Definition packed_simd::i32x2

type i32x2 = Simd<[i32; 2]>;

A 64-bit vector with 2 i32 lanes.

+

Implementations

impl i32x2[src]

pub const fn new(x0: i32, x1: i32) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: i32) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> i32[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> i32[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: i32) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: i32) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl i32x2[src]

pub fn rotate_left(self, n: i32x2) -> i32x2[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: i32x2) -> i32x2[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl i32x2[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl i32x2[src]

pub fn wrapping_sum(self) -> i32[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> i32[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl i32x2[src]

pub fn max_element(self) -> i32[src]

Largest vector element value.

+

pub fn min_element(self) -> i32[src]

Smallest vector element value.

+

impl i32x2[src]

pub fn and(self) -> i32[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> i32[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> i32[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl i32x2[src]

pub fn from_slice_aligned(slice: &[i32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[i32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[i32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[i32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl i32x2[src]

pub fn write_to_slice_aligned(self, slice: &mut [i32])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [i32])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [i32])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [i32])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl i32x2[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl i32x2[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl i32x2[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl i32x2[src]

pub fn eq(self, other: Self) -> m32x2[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m32x2[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m32x2[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m32x2[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m32x2[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m32x2[src]

Lane-wise greater-than-or-equals comparison.

+

impl i32x2[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<i32x2>[src]

Returns a wrapper that implements PartialOrd.

+

impl i32x2[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<i32x2>[src]

Returns a wrapper that implements Ord.

+

impl i32x2[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl Add<Simd<[i32; 2]>> for i32x2[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<i32> for i32x2[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[i32; 2]>> for i32x2[src]

impl AddAssign<i32> for i32x2[src]

impl Binary for i32x2[src]

impl BitAnd<Simd<[i32; 2]>> for i32x2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<i32> for i32x2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[i32; 2]>> for i32x2[src]

impl BitAndAssign<i32> for i32x2[src]

impl BitOr<Simd<[i32; 2]>> for i32x2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<i32> for i32x2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[i32; 2]>> for i32x2[src]

impl BitOrAssign<i32> for i32x2[src]

impl BitXor<Simd<[i32; 2]>> for i32x2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<i32> for i32x2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[i32; 2]>> for i32x2[src]

impl BitXorAssign<i32> for i32x2[src]

impl Debug for i32x2[src]

impl Default for i32x2[src]

impl Div<Simd<[i32; 2]>> for i32x2[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<i32> for i32x2[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[i32; 2]>> for i32x2[src]

impl DivAssign<i32> for i32x2[src]

impl Eq for i32x2[src]

impl From<[i32; 2]> for i32x2[src]

impl From<Simd<[i16; 2]>> for i32x2[src]

impl From<Simd<[i8; 2]>> for i32x2[src]

impl From<Simd<[u16; 2]>> for i32x2[src]

impl From<Simd<[u8; 2]>> for i32x2[src]

impl FromBits<Simd<[f32; 2]>> for i32x2[src]

impl FromBits<Simd<[i16; 4]>> for i32x2[src]

impl FromBits<Simd<[i8; 8]>> for i32x2[src]

impl FromBits<Simd<[m16; 4]>> for i32x2[src]

impl FromBits<Simd<[m32; 2]>> for i32x2[src]

impl FromBits<Simd<[m8; 8]>> for i32x2[src]

impl FromBits<Simd<[u16; 4]>> for i32x2[src]

impl FromBits<Simd<[u32; 2]>> for i32x2[src]

impl FromBits<Simd<[u8; 8]>> for i32x2[src]

impl FromBits<__m64> for i32x2[src]

impl FromCast<Simd<[f32; 2]>> for i32x2[src]

impl FromCast<Simd<[f64; 2]>> for i32x2[src]

impl FromCast<Simd<[i128; 2]>> for i32x2[src]

impl FromCast<Simd<[i16; 2]>> for i32x2[src]

impl FromCast<Simd<[i64; 2]>> for i32x2[src]

impl FromCast<Simd<[i8; 2]>> for i32x2[src]

impl FromCast<Simd<[isize; 2]>> for i32x2[src]

impl FromCast<Simd<[m128; 2]>> for i32x2[src]

impl FromCast<Simd<[m16; 2]>> for i32x2[src]

impl FromCast<Simd<[m32; 2]>> for i32x2[src]

impl FromCast<Simd<[m64; 2]>> for i32x2[src]

impl FromCast<Simd<[m8; 2]>> for i32x2[src]

impl FromCast<Simd<[msize; 2]>> for i32x2[src]

impl FromCast<Simd<[u128; 2]>> for i32x2[src]

impl FromCast<Simd<[u16; 2]>> for i32x2[src]

impl FromCast<Simd<[u32; 2]>> for i32x2[src]

impl FromCast<Simd<[u64; 2]>> for i32x2[src]

impl FromCast<Simd<[u8; 2]>> for i32x2[src]

impl FromCast<Simd<[usize; 2]>> for i32x2[src]

impl Hash for i32x2[src]

impl LowerHex for i32x2[src]

impl Mul<Simd<[i32; 2]>> for i32x2[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<i32> for i32x2[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[i32; 2]>> for i32x2[src]

impl MulAssign<i32> for i32x2[src]

impl Neg for i32x2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Not for i32x2[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl Octal for i32x2[src]

impl PartialEq<Simd<[i32; 2]>> for i32x2[src]

impl<'a> Product<&'a Simd<[i32; 2]>> for i32x2[src]

impl Product<Simd<[i32; 2]>> for i32x2[src]

impl Rem<Simd<[i32; 2]>> for i32x2[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<i32> for i32x2[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[i32; 2]>> for i32x2[src]

impl RemAssign<i32> for i32x2[src]

impl Shl<Simd<[i32; 2]>> for i32x2[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<u32> for i32x2[src]

type Output = Self

The resulting type after applying the << operator.

+

impl ShlAssign<Simd<[i32; 2]>> for i32x2[src]

impl ShlAssign<u32> for i32x2[src]

impl Shr<Simd<[i32; 2]>> for i32x2[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<u32> for i32x2[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl ShrAssign<Simd<[i32; 2]>> for i32x2[src]

impl ShrAssign<u32> for i32x2[src]

impl Simd for i32x2[src]

type Element = i32

Element type of the SIMD vector

+

type LanesType = [u32; 2]

The type: [u32; Self::N].

+

impl Sub<Simd<[i32; 2]>> for i32x2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<i32> for i32x2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[i32; 2]>> for i32x2[src]

impl SubAssign<i32> for i32x2[src]

impl<'a> Sum<&'a Simd<[i32; 2]>> for i32x2[src]

impl Sum<Simd<[i32; 2]>> for i32x2[src]

impl UpperHex for i32x2[src]

\ No newline at end of file diff --git a/packed_simd/type.i32x4.html b/packed_simd/type.i32x4.html new file mode 100644 index 000000000..ebe8c7563 --- /dev/null +++ b/packed_simd/type.i32x4.html @@ -0,0 +1,254 @@ +packed_simd::i32x4 - Rust

[−][src]Type Definition packed_simd::i32x4

type i32x4 = Simd<[i32; 4]>;

A 128-bit vector with 4 i32 lanes.

+

Implementations

impl i32x4[src]

pub const fn new(x0: i32, x1: i32, x2: i32, x3: i32) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: i32) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> i32[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> i32[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: i32) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: i32) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl i32x4[src]

pub fn rotate_left(self, n: i32x4) -> i32x4[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: i32x4) -> i32x4[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl i32x4[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl i32x4[src]

pub fn wrapping_sum(self) -> i32[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> i32[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl i32x4[src]

pub fn max_element(self) -> i32[src]

Largest vector element value.

+

pub fn min_element(self) -> i32[src]

Smallest vector element value.

+

impl i32x4[src]

pub fn and(self) -> i32[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> i32[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> i32[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl i32x4[src]

pub fn from_slice_aligned(slice: &[i32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[i32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[i32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[i32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl i32x4[src]

pub fn write_to_slice_aligned(self, slice: &mut [i32])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [i32])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [i32])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [i32])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl i32x4[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl i32x4[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl i32x4[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl i32x4[src]

pub fn eq(self, other: Self) -> m32x4[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m32x4[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m32x4[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m32x4[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m32x4[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m32x4[src]

Lane-wise greater-than-or-equals comparison.

+

impl i32x4[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<i32x4>[src]

Returns a wrapper that implements PartialOrd.

+

impl i32x4[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<i32x4>[src]

Returns a wrapper that implements Ord.

+

impl i32x4[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl Add<Simd<[i32; 4]>> for i32x4[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<i32> for i32x4[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[i32; 4]>> for i32x4[src]

impl AddAssign<i32> for i32x4[src]

impl Binary for i32x4[src]

impl BitAnd<Simd<[i32; 4]>> for i32x4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<i32> for i32x4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[i32; 4]>> for i32x4[src]

impl BitAndAssign<i32> for i32x4[src]

impl BitOr<Simd<[i32; 4]>> for i32x4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<i32> for i32x4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[i32; 4]>> for i32x4[src]

impl BitOrAssign<i32> for i32x4[src]

impl BitXor<Simd<[i32; 4]>> for i32x4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<i32> for i32x4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[i32; 4]>> for i32x4[src]

impl BitXorAssign<i32> for i32x4[src]

impl Debug for i32x4[src]

impl Default for i32x4[src]

impl Div<Simd<[i32; 4]>> for i32x4[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<i32> for i32x4[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[i32; 4]>> for i32x4[src]

impl DivAssign<i32> for i32x4[src]

impl Eq for i32x4[src]

impl From<[i32; 4]> for i32x4[src]

impl From<Simd<[i16; 4]>> for i32x4[src]

impl From<Simd<[i8; 4]>> for i32x4[src]

impl From<Simd<[u16; 4]>> for i32x4[src]

impl From<Simd<[u8; 4]>> for i32x4[src]

impl FromBits<Simd<[f32; 4]>> for i32x4[src]

impl FromBits<Simd<[f64; 2]>> for i32x4[src]

impl FromBits<Simd<[i128; 1]>> for i32x4[src]

impl FromBits<Simd<[i16; 8]>> for i32x4[src]

impl FromBits<Simd<[i64; 2]>> for i32x4[src]

impl FromBits<Simd<[i8; 16]>> for i32x4[src]

impl FromBits<Simd<[m128; 1]>> for i32x4[src]

impl FromBits<Simd<[m16; 8]>> for i32x4[src]

impl FromBits<Simd<[m32; 4]>> for i32x4[src]

impl FromBits<Simd<[m64; 2]>> for i32x4[src]

impl FromBits<Simd<[m8; 16]>> for i32x4[src]

impl FromBits<Simd<[u128; 1]>> for i32x4[src]

impl FromBits<Simd<[u16; 8]>> for i32x4[src]

impl FromBits<Simd<[u32; 4]>> for i32x4[src]

impl FromBits<Simd<[u64; 2]>> for i32x4[src]

impl FromBits<Simd<[u8; 16]>> for i32x4[src]

impl FromBits<__m128> for i32x4[src]

impl FromBits<__m128d> for i32x4[src]

impl FromBits<__m128i> for i32x4[src]

impl FromCast<Simd<[f32; 4]>> for i32x4[src]

impl FromCast<Simd<[f64; 4]>> for i32x4[src]

impl FromCast<Simd<[i128; 4]>> for i32x4[src]

impl FromCast<Simd<[i16; 4]>> for i32x4[src]

impl FromCast<Simd<[i64; 4]>> for i32x4[src]

impl FromCast<Simd<[i8; 4]>> for i32x4[src]

impl FromCast<Simd<[isize; 4]>> for i32x4[src]

impl FromCast<Simd<[m128; 4]>> for i32x4[src]

impl FromCast<Simd<[m16; 4]>> for i32x4[src]

impl FromCast<Simd<[m32; 4]>> for i32x4[src]

impl FromCast<Simd<[m64; 4]>> for i32x4[src]

impl FromCast<Simd<[m8; 4]>> for i32x4[src]

impl FromCast<Simd<[msize; 4]>> for i32x4[src]

impl FromCast<Simd<[u128; 4]>> for i32x4[src]

impl FromCast<Simd<[u16; 4]>> for i32x4[src]

impl FromCast<Simd<[u32; 4]>> for i32x4[src]

impl FromCast<Simd<[u64; 4]>> for i32x4[src]

impl FromCast<Simd<[u8; 4]>> for i32x4[src]

impl FromCast<Simd<[usize; 4]>> for i32x4[src]

impl Hash for i32x4[src]

impl LowerHex for i32x4[src]

impl Mul<Simd<[i32; 4]>> for i32x4[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<i32> for i32x4[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[i32; 4]>> for i32x4[src]

impl MulAssign<i32> for i32x4[src]

impl Neg for i32x4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Not for i32x4[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl Octal for i32x4[src]

impl PartialEq<Simd<[i32; 4]>> for i32x4[src]

impl<'a> Product<&'a Simd<[i32; 4]>> for i32x4[src]

impl Product<Simd<[i32; 4]>> for i32x4[src]

impl Rem<Simd<[i32; 4]>> for i32x4[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<i32> for i32x4[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[i32; 4]>> for i32x4[src]

impl RemAssign<i32> for i32x4[src]

impl Shl<Simd<[i32; 4]>> for i32x4[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<u32> for i32x4[src]

type Output = Self

The resulting type after applying the << operator.

+

impl ShlAssign<Simd<[i32; 4]>> for i32x4[src]

impl ShlAssign<u32> for i32x4[src]

impl Shr<Simd<[i32; 4]>> for i32x4[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<u32> for i32x4[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl ShrAssign<Simd<[i32; 4]>> for i32x4[src]

impl ShrAssign<u32> for i32x4[src]

impl Simd for i32x4[src]

type Element = i32

Element type of the SIMD vector

+

type LanesType = [u32; 4]

The type: [u32; Self::N].

+

impl Sub<Simd<[i32; 4]>> for i32x4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<i32> for i32x4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[i32; 4]>> for i32x4[src]

impl SubAssign<i32> for i32x4[src]

impl<'a> Sum<&'a Simd<[i32; 4]>> for i32x4[src]

impl Sum<Simd<[i32; 4]>> for i32x4[src]

impl UpperHex for i32x4[src]

\ No newline at end of file diff --git a/packed_simd/type.i32x8.html b/packed_simd/type.i32x8.html new file mode 100644 index 000000000..8e9945c78 --- /dev/null +++ b/packed_simd/type.i32x8.html @@ -0,0 +1,251 @@ +packed_simd::i32x8 - Rust

[−][src]Type Definition packed_simd::i32x8

type i32x8 = Simd<[i32; 8]>;

A 256-bit vector with 8 i32 lanes.

+

Implementations

impl i32x8[src]

pub const fn new(
    x0: i32,
    x1: i32,
    x2: i32,
    x3: i32,
    x4: i32,
    x5: i32,
    x6: i32,
    x7: i32
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: i32) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> i32[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> i32[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: i32) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: i32) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl i32x8[src]

pub fn rotate_left(self, n: i32x8) -> i32x8[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: i32x8) -> i32x8[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl i32x8[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl i32x8[src]

pub fn wrapping_sum(self) -> i32[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> i32[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl i32x8[src]

pub fn max_element(self) -> i32[src]

Largest vector element value.

+

pub fn min_element(self) -> i32[src]

Smallest vector element value.

+

impl i32x8[src]

pub fn and(self) -> i32[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> i32[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> i32[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl i32x8[src]

pub fn from_slice_aligned(slice: &[i32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[i32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[i32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[i32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl i32x8[src]

pub fn write_to_slice_aligned(self, slice: &mut [i32])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [i32])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [i32])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [i32])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl i32x8[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl i32x8[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl i32x8[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl i32x8[src]

pub fn eq(self, other: Self) -> m32x8[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m32x8[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m32x8[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m32x8[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m32x8[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m32x8[src]

Lane-wise greater-than-or-equals comparison.

+

impl i32x8[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<i32x8>[src]

Returns a wrapper that implements PartialOrd.

+

impl i32x8[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<i32x8>[src]

Returns a wrapper that implements Ord.

+

impl i32x8[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl Add<Simd<[i32; 8]>> for i32x8[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<i32> for i32x8[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[i32; 8]>> for i32x8[src]

impl AddAssign<i32> for i32x8[src]

impl Binary for i32x8[src]

impl BitAnd<Simd<[i32; 8]>> for i32x8[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<i32> for i32x8[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[i32; 8]>> for i32x8[src]

impl BitAndAssign<i32> for i32x8[src]

impl BitOr<Simd<[i32; 8]>> for i32x8[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<i32> for i32x8[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[i32; 8]>> for i32x8[src]

impl BitOrAssign<i32> for i32x8[src]

impl BitXor<Simd<[i32; 8]>> for i32x8[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<i32> for i32x8[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[i32; 8]>> for i32x8[src]

impl BitXorAssign<i32> for i32x8[src]

impl Debug for i32x8[src]

impl Default for i32x8[src]

impl Div<Simd<[i32; 8]>> for i32x8[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<i32> for i32x8[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[i32; 8]>> for i32x8[src]

impl DivAssign<i32> for i32x8[src]

impl Eq for i32x8[src]

impl From<[i32; 8]> for i32x8[src]

impl From<Simd<[i16; 8]>> for i32x8[src]

impl From<Simd<[i8; 8]>> for i32x8[src]

impl From<Simd<[u16; 8]>> for i32x8[src]

impl From<Simd<[u8; 8]>> for i32x8[src]

impl FromBits<Simd<[f32; 8]>> for i32x8[src]

impl FromBits<Simd<[f64; 4]>> for i32x8[src]

impl FromBits<Simd<[i128; 2]>> for i32x8[src]

impl FromBits<Simd<[i16; 16]>> for i32x8[src]

impl FromBits<Simd<[i64; 4]>> for i32x8[src]

impl FromBits<Simd<[i8; 32]>> for i32x8[src]

impl FromBits<Simd<[m128; 2]>> for i32x8[src]

impl FromBits<Simd<[m16; 16]>> for i32x8[src]

impl FromBits<Simd<[m32; 8]>> for i32x8[src]

impl FromBits<Simd<[m64; 4]>> for i32x8[src]

impl FromBits<Simd<[m8; 32]>> for i32x8[src]

impl FromBits<Simd<[u128; 2]>> for i32x8[src]

impl FromBits<Simd<[u16; 16]>> for i32x8[src]

impl FromBits<Simd<[u32; 8]>> for i32x8[src]

impl FromBits<Simd<[u64; 4]>> for i32x8[src]

impl FromBits<Simd<[u8; 32]>> for i32x8[src]

impl FromBits<__m256> for i32x8[src]

impl FromBits<__m256d> for i32x8[src]

impl FromBits<__m256i> for i32x8[src]

impl FromCast<Simd<[f32; 8]>> for i32x8[src]

impl FromCast<Simd<[f64; 8]>> for i32x8[src]

impl FromCast<Simd<[i16; 8]>> for i32x8[src]

impl FromCast<Simd<[i64; 8]>> for i32x8[src]

impl FromCast<Simd<[i8; 8]>> for i32x8[src]

impl FromCast<Simd<[isize; 8]>> for i32x8[src]

impl FromCast<Simd<[m16; 8]>> for i32x8[src]

impl FromCast<Simd<[m32; 8]>> for i32x8[src]

impl FromCast<Simd<[m64; 8]>> for i32x8[src]

impl FromCast<Simd<[m8; 8]>> for i32x8[src]

impl FromCast<Simd<[msize; 8]>> for i32x8[src]

impl FromCast<Simd<[u16; 8]>> for i32x8[src]

impl FromCast<Simd<[u32; 8]>> for i32x8[src]

impl FromCast<Simd<[u64; 8]>> for i32x8[src]

impl FromCast<Simd<[u8; 8]>> for i32x8[src]

impl FromCast<Simd<[usize; 8]>> for i32x8[src]

impl Hash for i32x8[src]

impl LowerHex for i32x8[src]

impl Mul<Simd<[i32; 8]>> for i32x8[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<i32> for i32x8[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[i32; 8]>> for i32x8[src]

impl MulAssign<i32> for i32x8[src]

impl Neg for i32x8[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Not for i32x8[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl Octal for i32x8[src]

impl PartialEq<Simd<[i32; 8]>> for i32x8[src]

impl<'a> Product<&'a Simd<[i32; 8]>> for i32x8[src]

impl Product<Simd<[i32; 8]>> for i32x8[src]

impl Rem<Simd<[i32; 8]>> for i32x8[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<i32> for i32x8[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[i32; 8]>> for i32x8[src]

impl RemAssign<i32> for i32x8[src]

impl Shl<Simd<[i32; 8]>> for i32x8[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<u32> for i32x8[src]

type Output = Self

The resulting type after applying the << operator.

+

impl ShlAssign<Simd<[i32; 8]>> for i32x8[src]

impl ShlAssign<u32> for i32x8[src]

impl Shr<Simd<[i32; 8]>> for i32x8[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<u32> for i32x8[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl ShrAssign<Simd<[i32; 8]>> for i32x8[src]

impl ShrAssign<u32> for i32x8[src]

impl Simd for i32x8[src]

type Element = i32

Element type of the SIMD vector

+

type LanesType = [u32; 8]

The type: [u32; Self::N].

+

impl Sub<Simd<[i32; 8]>> for i32x8[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<i32> for i32x8[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[i32; 8]>> for i32x8[src]

impl SubAssign<i32> for i32x8[src]

impl<'a> Sum<&'a Simd<[i32; 8]>> for i32x8[src]

impl Sum<Simd<[i32; 8]>> for i32x8[src]

impl UpperHex for i32x8[src]

\ No newline at end of file diff --git a/packed_simd/type.i64x2.html b/packed_simd/type.i64x2.html new file mode 100644 index 000000000..d2ebecc09 --- /dev/null +++ b/packed_simd/type.i64x2.html @@ -0,0 +1,256 @@ +packed_simd::i64x2 - Rust

[−][src]Type Definition packed_simd::i64x2

type i64x2 = Simd<[i64; 2]>;

A 128-bit vector with 2 i64 lanes.

+

Implementations

impl i64x2[src]

pub const fn new(x0: i64, x1: i64) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: i64) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> i64[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> i64[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: i64) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: i64) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl i64x2[src]

pub fn rotate_left(self, n: i64x2) -> i64x2[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: i64x2) -> i64x2[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl i64x2[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl i64x2[src]

pub fn wrapping_sum(self) -> i64[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> i64[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl i64x2[src]

pub fn max_element(self) -> i64[src]

Largest vector element value.

+

pub fn min_element(self) -> i64[src]

Smallest vector element value.

+

impl i64x2[src]

pub fn and(self) -> i64[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> i64[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> i64[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl i64x2[src]

pub fn from_slice_aligned(slice: &[i64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[i64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[i64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[i64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl i64x2[src]

pub fn write_to_slice_aligned(self, slice: &mut [i64])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [i64])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [i64])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [i64])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl i64x2[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl i64x2[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl i64x2[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl i64x2[src]

pub fn eq(self, other: Self) -> m64x2[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m64x2[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m64x2[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m64x2[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m64x2[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m64x2[src]

Lane-wise greater-than-or-equals comparison.

+

impl i64x2[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<i64x2>[src]

Returns a wrapper that implements PartialOrd.

+

impl i64x2[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<i64x2>[src]

Returns a wrapper that implements Ord.

+

impl i64x2[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl Add<Simd<[i64; 2]>> for i64x2[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<i64> for i64x2[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[i64; 2]>> for i64x2[src]

impl AddAssign<i64> for i64x2[src]

impl Binary for i64x2[src]

impl BitAnd<Simd<[i64; 2]>> for i64x2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<i64> for i64x2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[i64; 2]>> for i64x2[src]

impl BitAndAssign<i64> for i64x2[src]

impl BitOr<Simd<[i64; 2]>> for i64x2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<i64> for i64x2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[i64; 2]>> for i64x2[src]

impl BitOrAssign<i64> for i64x2[src]

impl BitXor<Simd<[i64; 2]>> for i64x2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<i64> for i64x2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[i64; 2]>> for i64x2[src]

impl BitXorAssign<i64> for i64x2[src]

impl Debug for i64x2[src]

impl Default for i64x2[src]

impl Div<Simd<[i64; 2]>> for i64x2[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<i64> for i64x2[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[i64; 2]>> for i64x2[src]

impl DivAssign<i64> for i64x2[src]

impl Eq for i64x2[src]

impl From<[i64; 2]> for i64x2[src]

impl From<Simd<[i16; 2]>> for i64x2[src]

impl From<Simd<[i32; 2]>> for i64x2[src]

impl From<Simd<[i8; 2]>> for i64x2[src]

impl From<Simd<[u16; 2]>> for i64x2[src]

impl From<Simd<[u32; 2]>> for i64x2[src]

impl From<Simd<[u8; 2]>> for i64x2[src]

impl FromBits<Simd<[f32; 4]>> for i64x2[src]

impl FromBits<Simd<[f64; 2]>> for i64x2[src]

impl FromBits<Simd<[i128; 1]>> for i64x2[src]

impl FromBits<Simd<[i16; 8]>> for i64x2[src]

impl FromBits<Simd<[i32; 4]>> for i64x2[src]

impl FromBits<Simd<[i8; 16]>> for i64x2[src]

impl FromBits<Simd<[m128; 1]>> for i64x2[src]

impl FromBits<Simd<[m16; 8]>> for i64x2[src]

impl FromBits<Simd<[m32; 4]>> for i64x2[src]

impl FromBits<Simd<[m64; 2]>> for i64x2[src]

impl FromBits<Simd<[m8; 16]>> for i64x2[src]

impl FromBits<Simd<[u128; 1]>> for i64x2[src]

impl FromBits<Simd<[u16; 8]>> for i64x2[src]

impl FromBits<Simd<[u32; 4]>> for i64x2[src]

impl FromBits<Simd<[u64; 2]>> for i64x2[src]

impl FromBits<Simd<[u8; 16]>> for i64x2[src]

impl FromBits<__m128> for i64x2[src]

impl FromBits<__m128d> for i64x2[src]

impl FromBits<__m128i> for i64x2[src]

impl FromCast<Simd<[f32; 2]>> for i64x2[src]

impl FromCast<Simd<[f64; 2]>> for i64x2[src]

impl FromCast<Simd<[i128; 2]>> for i64x2[src]

impl FromCast<Simd<[i16; 2]>> for i64x2[src]

impl FromCast<Simd<[i32; 2]>> for i64x2[src]

impl FromCast<Simd<[i8; 2]>> for i64x2[src]

impl FromCast<Simd<[isize; 2]>> for i64x2[src]

impl FromCast<Simd<[m128; 2]>> for i64x2[src]

impl FromCast<Simd<[m16; 2]>> for i64x2[src]

impl FromCast<Simd<[m32; 2]>> for i64x2[src]

impl FromCast<Simd<[m64; 2]>> for i64x2[src]

impl FromCast<Simd<[m8; 2]>> for i64x2[src]

impl FromCast<Simd<[msize; 2]>> for i64x2[src]

impl FromCast<Simd<[u128; 2]>> for i64x2[src]

impl FromCast<Simd<[u16; 2]>> for i64x2[src]

impl FromCast<Simd<[u32; 2]>> for i64x2[src]

impl FromCast<Simd<[u64; 2]>> for i64x2[src]

impl FromCast<Simd<[u8; 2]>> for i64x2[src]

impl FromCast<Simd<[usize; 2]>> for i64x2[src]

impl Hash for i64x2[src]

impl LowerHex for i64x2[src]

impl Mul<Simd<[i64; 2]>> for i64x2[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<i64> for i64x2[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[i64; 2]>> for i64x2[src]

impl MulAssign<i64> for i64x2[src]

impl Neg for i64x2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Not for i64x2[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl Octal for i64x2[src]

impl PartialEq<Simd<[i64; 2]>> for i64x2[src]

impl<'a> Product<&'a Simd<[i64; 2]>> for i64x2[src]

impl Product<Simd<[i64; 2]>> for i64x2[src]

impl Rem<Simd<[i64; 2]>> for i64x2[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<i64> for i64x2[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[i64; 2]>> for i64x2[src]

impl RemAssign<i64> for i64x2[src]

impl Shl<Simd<[i64; 2]>> for i64x2[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<u32> for i64x2[src]

type Output = Self

The resulting type after applying the << operator.

+

impl ShlAssign<Simd<[i64; 2]>> for i64x2[src]

impl ShlAssign<u32> for i64x2[src]

impl Shr<Simd<[i64; 2]>> for i64x2[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<u32> for i64x2[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl ShrAssign<Simd<[i64; 2]>> for i64x2[src]

impl ShrAssign<u32> for i64x2[src]

impl Simd for i64x2[src]

type Element = i64

Element type of the SIMD vector

+

type LanesType = [u32; 2]

The type: [u32; Self::N].

+

impl Sub<Simd<[i64; 2]>> for i64x2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<i64> for i64x2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[i64; 2]>> for i64x2[src]

impl SubAssign<i64> for i64x2[src]

impl<'a> Sum<&'a Simd<[i64; 2]>> for i64x2[src]

impl Sum<Simd<[i64; 2]>> for i64x2[src]

impl UpperHex for i64x2[src]

\ No newline at end of file diff --git a/packed_simd/type.i64x4.html b/packed_simd/type.i64x4.html new file mode 100644 index 000000000..33e22a4af --- /dev/null +++ b/packed_simd/type.i64x4.html @@ -0,0 +1,256 @@ +packed_simd::i64x4 - Rust

[−][src]Type Definition packed_simd::i64x4

type i64x4 = Simd<[i64; 4]>;

A 256-bit vector with 4 i64 lanes.

+

Implementations

impl i64x4[src]

pub const fn new(x0: i64, x1: i64, x2: i64, x3: i64) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: i64) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> i64[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> i64[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: i64) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: i64) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl i64x4[src]

pub fn rotate_left(self, n: i64x4) -> i64x4[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: i64x4) -> i64x4[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl i64x4[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl i64x4[src]

pub fn wrapping_sum(self) -> i64[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> i64[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl i64x4[src]

pub fn max_element(self) -> i64[src]

Largest vector element value.

+

pub fn min_element(self) -> i64[src]

Smallest vector element value.

+

impl i64x4[src]

pub fn and(self) -> i64[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> i64[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> i64[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl i64x4[src]

pub fn from_slice_aligned(slice: &[i64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[i64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[i64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[i64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl i64x4[src]

pub fn write_to_slice_aligned(self, slice: &mut [i64])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [i64])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [i64])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [i64])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl i64x4[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl i64x4[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl i64x4[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl i64x4[src]

pub fn eq(self, other: Self) -> m64x4[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m64x4[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m64x4[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m64x4[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m64x4[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m64x4[src]

Lane-wise greater-than-or-equals comparison.

+

impl i64x4[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<i64x4>[src]

Returns a wrapper that implements PartialOrd.

+

impl i64x4[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<i64x4>[src]

Returns a wrapper that implements Ord.

+

impl i64x4[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl Add<Simd<[i64; 4]>> for i64x4[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<i64> for i64x4[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[i64; 4]>> for i64x4[src]

impl AddAssign<i64> for i64x4[src]

impl Binary for i64x4[src]

impl BitAnd<Simd<[i64; 4]>> for i64x4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<i64> for i64x4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[i64; 4]>> for i64x4[src]

impl BitAndAssign<i64> for i64x4[src]

impl BitOr<Simd<[i64; 4]>> for i64x4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<i64> for i64x4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[i64; 4]>> for i64x4[src]

impl BitOrAssign<i64> for i64x4[src]

impl BitXor<Simd<[i64; 4]>> for i64x4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<i64> for i64x4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[i64; 4]>> for i64x4[src]

impl BitXorAssign<i64> for i64x4[src]

impl Debug for i64x4[src]

impl Default for i64x4[src]

impl Div<Simd<[i64; 4]>> for i64x4[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<i64> for i64x4[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[i64; 4]>> for i64x4[src]

impl DivAssign<i64> for i64x4[src]

impl Eq for i64x4[src]

impl From<[i64; 4]> for i64x4[src]

impl From<Simd<[i16; 4]>> for i64x4[src]

impl From<Simd<[i32; 4]>> for i64x4[src]

impl From<Simd<[i8; 4]>> for i64x4[src]

impl From<Simd<[u16; 4]>> for i64x4[src]

impl From<Simd<[u32; 4]>> for i64x4[src]

impl From<Simd<[u8; 4]>> for i64x4[src]

impl FromBits<Simd<[f32; 8]>> for i64x4[src]

impl FromBits<Simd<[f64; 4]>> for i64x4[src]

impl FromBits<Simd<[i128; 2]>> for i64x4[src]

impl FromBits<Simd<[i16; 16]>> for i64x4[src]

impl FromBits<Simd<[i32; 8]>> for i64x4[src]

impl FromBits<Simd<[i8; 32]>> for i64x4[src]

impl FromBits<Simd<[m128; 2]>> for i64x4[src]

impl FromBits<Simd<[m16; 16]>> for i64x4[src]

impl FromBits<Simd<[m32; 8]>> for i64x4[src]

impl FromBits<Simd<[m64; 4]>> for i64x4[src]

impl FromBits<Simd<[m8; 32]>> for i64x4[src]

impl FromBits<Simd<[u128; 2]>> for i64x4[src]

impl FromBits<Simd<[u16; 16]>> for i64x4[src]

impl FromBits<Simd<[u32; 8]>> for i64x4[src]

impl FromBits<Simd<[u64; 4]>> for i64x4[src]

impl FromBits<Simd<[u8; 32]>> for i64x4[src]

impl FromBits<__m256> for i64x4[src]

impl FromBits<__m256d> for i64x4[src]

impl FromBits<__m256i> for i64x4[src]

impl FromCast<Simd<[f32; 4]>> for i64x4[src]

impl FromCast<Simd<[f64; 4]>> for i64x4[src]

impl FromCast<Simd<[i128; 4]>> for i64x4[src]

impl FromCast<Simd<[i16; 4]>> for i64x4[src]

impl FromCast<Simd<[i32; 4]>> for i64x4[src]

impl FromCast<Simd<[i8; 4]>> for i64x4[src]

impl FromCast<Simd<[isize; 4]>> for i64x4[src]

impl FromCast<Simd<[m128; 4]>> for i64x4[src]

impl FromCast<Simd<[m16; 4]>> for i64x4[src]

impl FromCast<Simd<[m32; 4]>> for i64x4[src]

impl FromCast<Simd<[m64; 4]>> for i64x4[src]

impl FromCast<Simd<[m8; 4]>> for i64x4[src]

impl FromCast<Simd<[msize; 4]>> for i64x4[src]

impl FromCast<Simd<[u128; 4]>> for i64x4[src]

impl FromCast<Simd<[u16; 4]>> for i64x4[src]

impl FromCast<Simd<[u32; 4]>> for i64x4[src]

impl FromCast<Simd<[u64; 4]>> for i64x4[src]

impl FromCast<Simd<[u8; 4]>> for i64x4[src]

impl FromCast<Simd<[usize; 4]>> for i64x4[src]

impl Hash for i64x4[src]

impl LowerHex for i64x4[src]

impl Mul<Simd<[i64; 4]>> for i64x4[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<i64> for i64x4[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[i64; 4]>> for i64x4[src]

impl MulAssign<i64> for i64x4[src]

impl Neg for i64x4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Not for i64x4[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl Octal for i64x4[src]

impl PartialEq<Simd<[i64; 4]>> for i64x4[src]

impl<'a> Product<&'a Simd<[i64; 4]>> for i64x4[src]

impl Product<Simd<[i64; 4]>> for i64x4[src]

impl Rem<Simd<[i64; 4]>> for i64x4[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<i64> for i64x4[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[i64; 4]>> for i64x4[src]

impl RemAssign<i64> for i64x4[src]

impl Shl<Simd<[i64; 4]>> for i64x4[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<u32> for i64x4[src]

type Output = Self

The resulting type after applying the << operator.

+

impl ShlAssign<Simd<[i64; 4]>> for i64x4[src]

impl ShlAssign<u32> for i64x4[src]

impl Shr<Simd<[i64; 4]>> for i64x4[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<u32> for i64x4[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl ShrAssign<Simd<[i64; 4]>> for i64x4[src]

impl ShrAssign<u32> for i64x4[src]

impl Simd for i64x4[src]

type Element = i64

Element type of the SIMD vector

+

type LanesType = [u32; 4]

The type: [u32; Self::N].

+

impl Sub<Simd<[i64; 4]>> for i64x4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<i64> for i64x4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[i64; 4]>> for i64x4[src]

impl SubAssign<i64> for i64x4[src]

impl<'a> Sum<&'a Simd<[i64; 4]>> for i64x4[src]

impl Sum<Simd<[i64; 4]>> for i64x4[src]

impl UpperHex for i64x4[src]

\ No newline at end of file diff --git a/packed_simd/type.i64x8.html b/packed_simd/type.i64x8.html new file mode 100644 index 000000000..beb2c4543 --- /dev/null +++ b/packed_simd/type.i64x8.html @@ -0,0 +1,250 @@ +packed_simd::i64x8 - Rust

[−][src]Type Definition packed_simd::i64x8

type i64x8 = Simd<[i64; 8]>;

A 512-bit vector with 8 i64 lanes.

+

Implementations

impl i64x8[src]

pub const fn new(
    x0: i64,
    x1: i64,
    x2: i64,
    x3: i64,
    x4: i64,
    x5: i64,
    x6: i64,
    x7: i64
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: i64) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> i64[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> i64[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: i64) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: i64) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl i64x8[src]

pub fn rotate_left(self, n: i64x8) -> i64x8[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: i64x8) -> i64x8[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl i64x8[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl i64x8[src]

pub fn wrapping_sum(self) -> i64[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> i64[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl i64x8[src]

pub fn max_element(self) -> i64[src]

Largest vector element value.

+

pub fn min_element(self) -> i64[src]

Smallest vector element value.

+

impl i64x8[src]

pub fn and(self) -> i64[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> i64[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> i64[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl i64x8[src]

pub fn from_slice_aligned(slice: &[i64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[i64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[i64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[i64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl i64x8[src]

pub fn write_to_slice_aligned(self, slice: &mut [i64])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [i64])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [i64])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [i64])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl i64x8[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl i64x8[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl i64x8[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl i64x8[src]

pub fn eq(self, other: Self) -> m64x8[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m64x8[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m64x8[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m64x8[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m64x8[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m64x8[src]

Lane-wise greater-than-or-equals comparison.

+

impl i64x8[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<i64x8>[src]

Returns a wrapper that implements PartialOrd.

+

impl i64x8[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<i64x8>[src]

Returns a wrapper that implements Ord.

+

impl i64x8[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl Add<Simd<[i64; 8]>> for i64x8[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<i64> for i64x8[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[i64; 8]>> for i64x8[src]

impl AddAssign<i64> for i64x8[src]

impl Binary for i64x8[src]

impl BitAnd<Simd<[i64; 8]>> for i64x8[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<i64> for i64x8[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[i64; 8]>> for i64x8[src]

impl BitAndAssign<i64> for i64x8[src]

impl BitOr<Simd<[i64; 8]>> for i64x8[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<i64> for i64x8[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[i64; 8]>> for i64x8[src]

impl BitOrAssign<i64> for i64x8[src]

impl BitXor<Simd<[i64; 8]>> for i64x8[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<i64> for i64x8[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[i64; 8]>> for i64x8[src]

impl BitXorAssign<i64> for i64x8[src]

impl Debug for i64x8[src]

impl Default for i64x8[src]

impl Div<Simd<[i64; 8]>> for i64x8[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<i64> for i64x8[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[i64; 8]>> for i64x8[src]

impl DivAssign<i64> for i64x8[src]

impl Eq for i64x8[src]

impl From<[i64; 8]> for i64x8[src]

impl From<Simd<[i16; 8]>> for i64x8[src]

impl From<Simd<[i32; 8]>> for i64x8[src]

impl From<Simd<[i8; 8]>> for i64x8[src]

impl From<Simd<[u16; 8]>> for i64x8[src]

impl From<Simd<[u32; 8]>> for i64x8[src]

impl From<Simd<[u8; 8]>> for i64x8[src]

impl FromBits<Simd<[f32; 16]>> for i64x8[src]

impl FromBits<Simd<[f64; 8]>> for i64x8[src]

impl FromBits<Simd<[i128; 4]>> for i64x8[src]

impl FromBits<Simd<[i16; 32]>> for i64x8[src]

impl FromBits<Simd<[i32; 16]>> for i64x8[src]

impl FromBits<Simd<[i8; 64]>> for i64x8[src]

impl FromBits<Simd<[m128; 4]>> for i64x8[src]

impl FromBits<Simd<[m16; 32]>> for i64x8[src]

impl FromBits<Simd<[m32; 16]>> for i64x8[src]

impl FromBits<Simd<[m64; 8]>> for i64x8[src]

impl FromBits<Simd<[m8; 64]>> for i64x8[src]

impl FromBits<Simd<[u128; 4]>> for i64x8[src]

impl FromBits<Simd<[u16; 32]>> for i64x8[src]

impl FromBits<Simd<[u32; 16]>> for i64x8[src]

impl FromBits<Simd<[u64; 8]>> for i64x8[src]

impl FromBits<Simd<[u8; 64]>> for i64x8[src]

impl FromCast<Simd<[f32; 8]>> for i64x8[src]

impl FromCast<Simd<[f64; 8]>> for i64x8[src]

impl FromCast<Simd<[i16; 8]>> for i64x8[src]

impl FromCast<Simd<[i32; 8]>> for i64x8[src]

impl FromCast<Simd<[i8; 8]>> for i64x8[src]

impl FromCast<Simd<[isize; 8]>> for i64x8[src]

impl FromCast<Simd<[m16; 8]>> for i64x8[src]

impl FromCast<Simd<[m32; 8]>> for i64x8[src]

impl FromCast<Simd<[m64; 8]>> for i64x8[src]

impl FromCast<Simd<[m8; 8]>> for i64x8[src]

impl FromCast<Simd<[msize; 8]>> for i64x8[src]

impl FromCast<Simd<[u16; 8]>> for i64x8[src]

impl FromCast<Simd<[u32; 8]>> for i64x8[src]

impl FromCast<Simd<[u64; 8]>> for i64x8[src]

impl FromCast<Simd<[u8; 8]>> for i64x8[src]

impl FromCast<Simd<[usize; 8]>> for i64x8[src]

impl Hash for i64x8[src]

impl LowerHex for i64x8[src]

impl Mul<Simd<[i64; 8]>> for i64x8[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<i64> for i64x8[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[i64; 8]>> for i64x8[src]

impl MulAssign<i64> for i64x8[src]

impl Neg for i64x8[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Not for i64x8[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl Octal for i64x8[src]

impl PartialEq<Simd<[i64; 8]>> for i64x8[src]

impl<'a> Product<&'a Simd<[i64; 8]>> for i64x8[src]

impl Product<Simd<[i64; 8]>> for i64x8[src]

impl Rem<Simd<[i64; 8]>> for i64x8[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<i64> for i64x8[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[i64; 8]>> for i64x8[src]

impl RemAssign<i64> for i64x8[src]

impl Shl<Simd<[i64; 8]>> for i64x8[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<u32> for i64x8[src]

type Output = Self

The resulting type after applying the << operator.

+

impl ShlAssign<Simd<[i64; 8]>> for i64x8[src]

impl ShlAssign<u32> for i64x8[src]

impl Shr<Simd<[i64; 8]>> for i64x8[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<u32> for i64x8[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl ShrAssign<Simd<[i64; 8]>> for i64x8[src]

impl ShrAssign<u32> for i64x8[src]

impl Simd for i64x8[src]

type Element = i64

Element type of the SIMD vector

+

type LanesType = [u32; 8]

The type: [u32; Self::N].

+

impl Sub<Simd<[i64; 8]>> for i64x8[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<i64> for i64x8[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[i64; 8]>> for i64x8[src]

impl SubAssign<i64> for i64x8[src]

impl<'a> Sum<&'a Simd<[i64; 8]>> for i64x8[src]

impl Sum<Simd<[i64; 8]>> for i64x8[src]

impl UpperHex for i64x8[src]

\ No newline at end of file diff --git a/packed_simd/type.i8x16.html b/packed_simd/type.i8x16.html new file mode 100644 index 000000000..683ac9d01 --- /dev/null +++ b/packed_simd/type.i8x16.html @@ -0,0 +1,240 @@ +packed_simd::i8x16 - Rust

[−][src]Type Definition packed_simd::i8x16

type i8x16 = Simd<[i8; 16]>;

A 128-bit vector with 16 i8 lanes.

+

Implementations

impl i8x16[src]

pub const fn new(
    x0: i8,
    x1: i8,
    x2: i8,
    x3: i8,
    x4: i8,
    x5: i8,
    x6: i8,
    x7: i8,
    x8: i8,
    x9: i8,
    x10: i8,
    x11: i8,
    x12: i8,
    x13: i8,
    x14: i8,
    x15: i8
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: i8) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> i8[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> i8[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: i8) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: i8) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl i8x16[src]

pub fn rotate_left(self, n: i8x16) -> i8x16[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: i8x16) -> i8x16[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl i8x16[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl i8x16[src]

pub fn wrapping_sum(self) -> i8[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> i8[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl i8x16[src]

pub fn max_element(self) -> i8[src]

Largest vector element value.

+

pub fn min_element(self) -> i8[src]

Smallest vector element value.

+

impl i8x16[src]

pub fn and(self) -> i8[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> i8[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> i8[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl i8x16[src]

pub fn from_slice_aligned(slice: &[i8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[i8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[i8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[i8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl i8x16[src]

pub fn write_to_slice_aligned(self, slice: &mut [i8])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [i8])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [i8])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [i8])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl i8x16[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl i8x16[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl i8x16[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl i8x16[src]

pub fn eq(self, other: Self) -> m8x16[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m8x16[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m8x16[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m8x16[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m8x16[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m8x16[src]

Lane-wise greater-than-or-equals comparison.

+

impl i8x16[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<i8x16>[src]

Returns a wrapper that implements PartialOrd.

+

impl i8x16[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<i8x16>[src]

Returns a wrapper that implements Ord.

+

impl i8x16[src]

pub fn bitmask(self) -> u16[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl Add<Simd<[i8; 16]>> for i8x16[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<i8> for i8x16[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[i8; 16]>> for i8x16[src]

impl AddAssign<i8> for i8x16[src]

impl Binary for i8x16[src]

impl BitAnd<Simd<[i8; 16]>> for i8x16[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<i8> for i8x16[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[i8; 16]>> for i8x16[src]

impl BitAndAssign<i8> for i8x16[src]

impl BitOr<Simd<[i8; 16]>> for i8x16[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<i8> for i8x16[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[i8; 16]>> for i8x16[src]

impl BitOrAssign<i8> for i8x16[src]

impl BitXor<Simd<[i8; 16]>> for i8x16[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<i8> for i8x16[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[i8; 16]>> for i8x16[src]

impl BitXorAssign<i8> for i8x16[src]

impl Debug for i8x16[src]

impl Default for i8x16[src]

impl Div<Simd<[i8; 16]>> for i8x16[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<i8> for i8x16[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[i8; 16]>> for i8x16[src]

impl DivAssign<i8> for i8x16[src]

impl Eq for i8x16[src]

impl From<[i8; 16]> for i8x16[src]

impl FromBits<Simd<[f32; 4]>> for i8x16[src]

impl FromBits<Simd<[f64; 2]>> for i8x16[src]

impl FromBits<Simd<[i128; 1]>> for i8x16[src]

impl FromBits<Simd<[i16; 8]>> for i8x16[src]

impl FromBits<Simd<[i32; 4]>> for i8x16[src]

impl FromBits<Simd<[i64; 2]>> for i8x16[src]

impl FromBits<Simd<[m128; 1]>> for i8x16[src]

impl FromBits<Simd<[m16; 8]>> for i8x16[src]

impl FromBits<Simd<[m32; 4]>> for i8x16[src]

impl FromBits<Simd<[m64; 2]>> for i8x16[src]

impl FromBits<Simd<[m8; 16]>> for i8x16[src]

impl FromBits<Simd<[u128; 1]>> for i8x16[src]

impl FromBits<Simd<[u16; 8]>> for i8x16[src]

impl FromBits<Simd<[u32; 4]>> for i8x16[src]

impl FromBits<Simd<[u64; 2]>> for i8x16[src]

impl FromBits<Simd<[u8; 16]>> for i8x16[src]

impl FromBits<__m128> for i8x16[src]

impl FromBits<__m128d> for i8x16[src]

impl FromBits<__m128i> for i8x16[src]

impl FromCast<Simd<[f32; 16]>> for i8x16[src]

impl FromCast<Simd<[i16; 16]>> for i8x16[src]

impl FromCast<Simd<[i32; 16]>> for i8x16[src]

impl FromCast<Simd<[m16; 16]>> for i8x16[src]

impl FromCast<Simd<[m32; 16]>> for i8x16[src]

impl FromCast<Simd<[m8; 16]>> for i8x16[src]

impl FromCast<Simd<[u16; 16]>> for i8x16[src]

impl FromCast<Simd<[u32; 16]>> for i8x16[src]

impl FromCast<Simd<[u8; 16]>> for i8x16[src]

impl Hash for i8x16[src]

impl LowerHex for i8x16[src]

impl Mul<Simd<[i8; 16]>> for i8x16[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<i8> for i8x16[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[i8; 16]>> for i8x16[src]

impl MulAssign<i8> for i8x16[src]

impl Neg for i8x16[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Not for i8x16[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl Octal for i8x16[src]

impl PartialEq<Simd<[i8; 16]>> for i8x16[src]

impl<'a> Product<&'a Simd<[i8; 16]>> for i8x16[src]

impl Product<Simd<[i8; 16]>> for i8x16[src]

impl Rem<Simd<[i8; 16]>> for i8x16[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<i8> for i8x16[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[i8; 16]>> for i8x16[src]

impl RemAssign<i8> for i8x16[src]

impl Shl<Simd<[i8; 16]>> for i8x16[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<u32> for i8x16[src]

type Output = Self

The resulting type after applying the << operator.

+

impl ShlAssign<Simd<[i8; 16]>> for i8x16[src]

impl ShlAssign<u32> for i8x16[src]

impl Shr<Simd<[i8; 16]>> for i8x16[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<u32> for i8x16[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl ShrAssign<Simd<[i8; 16]>> for i8x16[src]

impl ShrAssign<u32> for i8x16[src]

impl Simd for i8x16[src]

type Element = i8

Element type of the SIMD vector

+

type LanesType = [u32; 16]

The type: [u32; Self::N].

+

impl Sub<Simd<[i8; 16]>> for i8x16[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<i8> for i8x16[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[i8; 16]>> for i8x16[src]

impl SubAssign<i8> for i8x16[src]

impl<'a> Sum<&'a Simd<[i8; 16]>> for i8x16[src]

impl Sum<Simd<[i8; 16]>> for i8x16[src]

impl UpperHex for i8x16[src]

\ No newline at end of file diff --git a/packed_simd/type.i8x2.html b/packed_simd/type.i8x2.html new file mode 100644 index 000000000..d8fd5bae7 --- /dev/null +++ b/packed_simd/type.i8x2.html @@ -0,0 +1,233 @@ +packed_simd::i8x2 - Rust

[−][src]Type Definition packed_simd::i8x2

type i8x2 = Simd<[i8; 2]>;

A 16-bit vector with 2 i8 lanes.

+

Implementations

impl i8x2[src]

pub const fn new(x0: i8, x1: i8) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: i8) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> i8[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> i8[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: i8) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: i8) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl i8x2[src]

pub fn rotate_left(self, n: i8x2) -> i8x2[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: i8x2) -> i8x2[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl i8x2[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl i8x2[src]

pub fn wrapping_sum(self) -> i8[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> i8[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl i8x2[src]

pub fn max_element(self) -> i8[src]

Largest vector element value.

+

pub fn min_element(self) -> i8[src]

Smallest vector element value.

+

impl i8x2[src]

pub fn and(self) -> i8[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> i8[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> i8[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl i8x2[src]

pub fn from_slice_aligned(slice: &[i8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[i8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[i8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[i8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl i8x2[src]

pub fn write_to_slice_aligned(self, slice: &mut [i8])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [i8])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [i8])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [i8])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl i8x2[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl i8x2[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl i8x2[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl i8x2[src]

pub fn eq(self, other: Self) -> m8x2[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m8x2[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m8x2[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m8x2[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m8x2[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m8x2[src]

Lane-wise greater-than-or-equals comparison.

+

impl i8x2[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<i8x2>[src]

Returns a wrapper that implements PartialOrd.

+

impl i8x2[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<i8x2>[src]

Returns a wrapper that implements Ord.

+

impl i8x2[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl Add<Simd<[i8; 2]>> for i8x2[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<i8> for i8x2[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[i8; 2]>> for i8x2[src]

impl AddAssign<i8> for i8x2[src]

impl Binary for i8x2[src]

impl BitAnd<Simd<[i8; 2]>> for i8x2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<i8> for i8x2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[i8; 2]>> for i8x2[src]

impl BitAndAssign<i8> for i8x2[src]

impl BitOr<Simd<[i8; 2]>> for i8x2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<i8> for i8x2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[i8; 2]>> for i8x2[src]

impl BitOrAssign<i8> for i8x2[src]

impl BitXor<Simd<[i8; 2]>> for i8x2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<i8> for i8x2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[i8; 2]>> for i8x2[src]

impl BitXorAssign<i8> for i8x2[src]

impl Debug for i8x2[src]

impl Default for i8x2[src]

impl Div<Simd<[i8; 2]>> for i8x2[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<i8> for i8x2[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[i8; 2]>> for i8x2[src]

impl DivAssign<i8> for i8x2[src]

impl Eq for i8x2[src]

impl From<[i8; 2]> for i8x2[src]

impl FromBits<Simd<[m8; 2]>> for i8x2[src]

impl FromBits<Simd<[u8; 2]>> for i8x2[src]

impl FromCast<Simd<[f32; 2]>> for i8x2[src]

impl FromCast<Simd<[f64; 2]>> for i8x2[src]

impl FromCast<Simd<[i128; 2]>> for i8x2[src]

impl FromCast<Simd<[i16; 2]>> for i8x2[src]

impl FromCast<Simd<[i32; 2]>> for i8x2[src]

impl FromCast<Simd<[i64; 2]>> for i8x2[src]

impl FromCast<Simd<[isize; 2]>> for i8x2[src]

impl FromCast<Simd<[m128; 2]>> for i8x2[src]

impl FromCast<Simd<[m16; 2]>> for i8x2[src]

impl FromCast<Simd<[m32; 2]>> for i8x2[src]

impl FromCast<Simd<[m64; 2]>> for i8x2[src]

impl FromCast<Simd<[m8; 2]>> for i8x2[src]

impl FromCast<Simd<[msize; 2]>> for i8x2[src]

impl FromCast<Simd<[u128; 2]>> for i8x2[src]

impl FromCast<Simd<[u16; 2]>> for i8x2[src]

impl FromCast<Simd<[u32; 2]>> for i8x2[src]

impl FromCast<Simd<[u64; 2]>> for i8x2[src]

impl FromCast<Simd<[u8; 2]>> for i8x2[src]

impl FromCast<Simd<[usize; 2]>> for i8x2[src]

impl Hash for i8x2[src]

impl LowerHex for i8x2[src]

impl Mul<Simd<[i8; 2]>> for i8x2[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<i8> for i8x2[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[i8; 2]>> for i8x2[src]

impl MulAssign<i8> for i8x2[src]

impl Neg for i8x2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Not for i8x2[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl Octal for i8x2[src]

impl PartialEq<Simd<[i8; 2]>> for i8x2[src]

impl<'a> Product<&'a Simd<[i8; 2]>> for i8x2[src]

impl Product<Simd<[i8; 2]>> for i8x2[src]

impl Rem<Simd<[i8; 2]>> for i8x2[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<i8> for i8x2[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[i8; 2]>> for i8x2[src]

impl RemAssign<i8> for i8x2[src]

impl Shl<Simd<[i8; 2]>> for i8x2[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<u32> for i8x2[src]

type Output = Self

The resulting type after applying the << operator.

+

impl ShlAssign<Simd<[i8; 2]>> for i8x2[src]

impl ShlAssign<u32> for i8x2[src]

impl Shr<Simd<[i8; 2]>> for i8x2[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<u32> for i8x2[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl ShrAssign<Simd<[i8; 2]>> for i8x2[src]

impl ShrAssign<u32> for i8x2[src]

impl Simd for i8x2[src]

type Element = i8

Element type of the SIMD vector

+

type LanesType = [u32; 2]

The type: [u32; Self::N].

+

impl Sub<Simd<[i8; 2]>> for i8x2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<i8> for i8x2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[i8; 2]>> for i8x2[src]

impl SubAssign<i8> for i8x2[src]

impl<'a> Sum<&'a Simd<[i8; 2]>> for i8x2[src]

impl Sum<Simd<[i8; 2]>> for i8x2[src]

impl UpperHex for i8x2[src]

\ No newline at end of file diff --git a/packed_simd/type.i8x32.html b/packed_simd/type.i8x32.html new file mode 100644 index 000000000..863109b1e --- /dev/null +++ b/packed_simd/type.i8x32.html @@ -0,0 +1,236 @@ +packed_simd::i8x32 - Rust

[−][src]Type Definition packed_simd::i8x32

type i8x32 = Simd<[i8; 32]>;

A 256-bit vector with 32 i8 lanes.

+

Implementations

impl i8x32[src]

pub const fn new(
    x0: i8,
    x1: i8,
    x2: i8,
    x3: i8,
    x4: i8,
    x5: i8,
    x6: i8,
    x7: i8,
    x8: i8,
    x9: i8,
    x10: i8,
    x11: i8,
    x12: i8,
    x13: i8,
    x14: i8,
    x15: i8,
    x16: i8,
    x17: i8,
    x18: i8,
    x19: i8,
    x20: i8,
    x21: i8,
    x22: i8,
    x23: i8,
    x24: i8,
    x25: i8,
    x26: i8,
    x27: i8,
    x28: i8,
    x29: i8,
    x30: i8,
    x31: i8
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: i8) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> i8[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> i8[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: i8) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: i8) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl i8x32[src]

pub fn rotate_left(self, n: i8x32) -> i8x32[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: i8x32) -> i8x32[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl i8x32[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl i8x32[src]

pub fn wrapping_sum(self) -> i8[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> i8[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl i8x32[src]

pub fn max_element(self) -> i8[src]

Largest vector element value.

+

pub fn min_element(self) -> i8[src]

Smallest vector element value.

+

impl i8x32[src]

pub fn and(self) -> i8[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> i8[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> i8[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl i8x32[src]

pub fn from_slice_aligned(slice: &[i8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[i8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[i8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[i8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl i8x32[src]

pub fn write_to_slice_aligned(self, slice: &mut [i8])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [i8])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [i8])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [i8])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl i8x32[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl i8x32[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl i8x32[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl i8x32[src]

pub fn eq(self, other: Self) -> m8x32[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m8x32[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m8x32[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m8x32[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m8x32[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m8x32[src]

Lane-wise greater-than-or-equals comparison.

+

impl i8x32[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<i8x32>[src]

Returns a wrapper that implements PartialOrd.

+

impl i8x32[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<i8x32>[src]

Returns a wrapper that implements Ord.

+

impl i8x32[src]

pub fn bitmask(self) -> u32[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl Add<Simd<[i8; 32]>> for i8x32[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<i8> for i8x32[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[i8; 32]>> for i8x32[src]

impl AddAssign<i8> for i8x32[src]

impl Binary for i8x32[src]

impl BitAnd<Simd<[i8; 32]>> for i8x32[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<i8> for i8x32[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[i8; 32]>> for i8x32[src]

impl BitAndAssign<i8> for i8x32[src]

impl BitOr<Simd<[i8; 32]>> for i8x32[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<i8> for i8x32[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[i8; 32]>> for i8x32[src]

impl BitOrAssign<i8> for i8x32[src]

impl BitXor<Simd<[i8; 32]>> for i8x32[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<i8> for i8x32[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[i8; 32]>> for i8x32[src]

impl BitXorAssign<i8> for i8x32[src]

impl Debug for i8x32[src]

impl Default for i8x32[src]

impl Div<Simd<[i8; 32]>> for i8x32[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<i8> for i8x32[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[i8; 32]>> for i8x32[src]

impl DivAssign<i8> for i8x32[src]

impl Eq for i8x32[src]

impl From<[i8; 32]> for i8x32[src]

impl FromBits<Simd<[f32; 8]>> for i8x32[src]

impl FromBits<Simd<[f64; 4]>> for i8x32[src]

impl FromBits<Simd<[i128; 2]>> for i8x32[src]

impl FromBits<Simd<[i16; 16]>> for i8x32[src]

impl FromBits<Simd<[i32; 8]>> for i8x32[src]

impl FromBits<Simd<[i64; 4]>> for i8x32[src]

impl FromBits<Simd<[m128; 2]>> for i8x32[src]

impl FromBits<Simd<[m16; 16]>> for i8x32[src]

impl FromBits<Simd<[m32; 8]>> for i8x32[src]

impl FromBits<Simd<[m64; 4]>> for i8x32[src]

impl FromBits<Simd<[m8; 32]>> for i8x32[src]

impl FromBits<Simd<[u128; 2]>> for i8x32[src]

impl FromBits<Simd<[u16; 16]>> for i8x32[src]

impl FromBits<Simd<[u32; 8]>> for i8x32[src]

impl FromBits<Simd<[u64; 4]>> for i8x32[src]

impl FromBits<Simd<[u8; 32]>> for i8x32[src]

impl FromBits<__m256> for i8x32[src]

impl FromBits<__m256d> for i8x32[src]

impl FromBits<__m256i> for i8x32[src]

impl FromCast<Simd<[i16; 32]>> for i8x32[src]

impl FromCast<Simd<[m16; 32]>> for i8x32[src]

impl FromCast<Simd<[m8; 32]>> for i8x32[src]

impl FromCast<Simd<[u16; 32]>> for i8x32[src]

impl FromCast<Simd<[u8; 32]>> for i8x32[src]

impl Hash for i8x32[src]

impl LowerHex for i8x32[src]

impl Mul<Simd<[i8; 32]>> for i8x32[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<i8> for i8x32[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[i8; 32]>> for i8x32[src]

impl MulAssign<i8> for i8x32[src]

impl Neg for i8x32[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Not for i8x32[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl Octal for i8x32[src]

impl PartialEq<Simd<[i8; 32]>> for i8x32[src]

impl<'a> Product<&'a Simd<[i8; 32]>> for i8x32[src]

impl Product<Simd<[i8; 32]>> for i8x32[src]

impl Rem<Simd<[i8; 32]>> for i8x32[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<i8> for i8x32[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[i8; 32]>> for i8x32[src]

impl RemAssign<i8> for i8x32[src]

impl Shl<Simd<[i8; 32]>> for i8x32[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<u32> for i8x32[src]

type Output = Self

The resulting type after applying the << operator.

+

impl ShlAssign<Simd<[i8; 32]>> for i8x32[src]

impl ShlAssign<u32> for i8x32[src]

impl Shr<Simd<[i8; 32]>> for i8x32[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<u32> for i8x32[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl ShrAssign<Simd<[i8; 32]>> for i8x32[src]

impl ShrAssign<u32> for i8x32[src]

impl Simd for i8x32[src]

type Element = i8

Element type of the SIMD vector

+

type LanesType = [u32; 32]

The type: [u32; Self::N].

+

impl Sub<Simd<[i8; 32]>> for i8x32[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<i8> for i8x32[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[i8; 32]>> for i8x32[src]

impl SubAssign<i8> for i8x32[src]

impl<'a> Sum<&'a Simd<[i8; 32]>> for i8x32[src]

impl Sum<Simd<[i8; 32]>> for i8x32[src]

impl UpperHex for i8x32[src]

\ No newline at end of file diff --git a/packed_simd/type.i8x4.html b/packed_simd/type.i8x4.html new file mode 100644 index 000000000..f37b8f579 --- /dev/null +++ b/packed_simd/type.i8x4.html @@ -0,0 +1,236 @@ +packed_simd::i8x4 - Rust

[−][src]Type Definition packed_simd::i8x4

type i8x4 = Simd<[i8; 4]>;

A 32-bit vector with 4 i8 lanes.

+

Implementations

impl i8x4[src]

pub const fn new(x0: i8, x1: i8, x2: i8, x3: i8) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: i8) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> i8[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> i8[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: i8) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: i8) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl i8x4[src]

pub fn rotate_left(self, n: i8x4) -> i8x4[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: i8x4) -> i8x4[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl i8x4[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl i8x4[src]

pub fn wrapping_sum(self) -> i8[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> i8[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl i8x4[src]

pub fn max_element(self) -> i8[src]

Largest vector element value.

+

pub fn min_element(self) -> i8[src]

Smallest vector element value.

+

impl i8x4[src]

pub fn and(self) -> i8[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> i8[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> i8[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl i8x4[src]

pub fn from_slice_aligned(slice: &[i8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[i8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[i8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[i8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl i8x4[src]

pub fn write_to_slice_aligned(self, slice: &mut [i8])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [i8])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [i8])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [i8])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl i8x4[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl i8x4[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl i8x4[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl i8x4[src]

pub fn eq(self, other: Self) -> m8x4[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m8x4[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m8x4[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m8x4[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m8x4[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m8x4[src]

Lane-wise greater-than-or-equals comparison.

+

impl i8x4[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<i8x4>[src]

Returns a wrapper that implements PartialOrd.

+

impl i8x4[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<i8x4>[src]

Returns a wrapper that implements Ord.

+

impl i8x4[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl Add<Simd<[i8; 4]>> for i8x4[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<i8> for i8x4[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[i8; 4]>> for i8x4[src]

impl AddAssign<i8> for i8x4[src]

impl Binary for i8x4[src]

impl BitAnd<Simd<[i8; 4]>> for i8x4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<i8> for i8x4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[i8; 4]>> for i8x4[src]

impl BitAndAssign<i8> for i8x4[src]

impl BitOr<Simd<[i8; 4]>> for i8x4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<i8> for i8x4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[i8; 4]>> for i8x4[src]

impl BitOrAssign<i8> for i8x4[src]

impl BitXor<Simd<[i8; 4]>> for i8x4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<i8> for i8x4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[i8; 4]>> for i8x4[src]

impl BitXorAssign<i8> for i8x4[src]

impl Debug for i8x4[src]

impl Default for i8x4[src]

impl Div<Simd<[i8; 4]>> for i8x4[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<i8> for i8x4[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[i8; 4]>> for i8x4[src]

impl DivAssign<i8> for i8x4[src]

impl Eq for i8x4[src]

impl From<[i8; 4]> for i8x4[src]

impl FromBits<Simd<[i16; 2]>> for i8x4[src]

impl FromBits<Simd<[m16; 2]>> for i8x4[src]

impl FromBits<Simd<[m8; 4]>> for i8x4[src]

impl FromBits<Simd<[u16; 2]>> for i8x4[src]

impl FromBits<Simd<[u8; 4]>> for i8x4[src]

impl FromCast<Simd<[f32; 4]>> for i8x4[src]

impl FromCast<Simd<[f64; 4]>> for i8x4[src]

impl FromCast<Simd<[i128; 4]>> for i8x4[src]

impl FromCast<Simd<[i16; 4]>> for i8x4[src]

impl FromCast<Simd<[i32; 4]>> for i8x4[src]

impl FromCast<Simd<[i64; 4]>> for i8x4[src]

impl FromCast<Simd<[isize; 4]>> for i8x4[src]

impl FromCast<Simd<[m128; 4]>> for i8x4[src]

impl FromCast<Simd<[m16; 4]>> for i8x4[src]

impl FromCast<Simd<[m32; 4]>> for i8x4[src]

impl FromCast<Simd<[m64; 4]>> for i8x4[src]

impl FromCast<Simd<[m8; 4]>> for i8x4[src]

impl FromCast<Simd<[msize; 4]>> for i8x4[src]

impl FromCast<Simd<[u128; 4]>> for i8x4[src]

impl FromCast<Simd<[u16; 4]>> for i8x4[src]

impl FromCast<Simd<[u32; 4]>> for i8x4[src]

impl FromCast<Simd<[u64; 4]>> for i8x4[src]

impl FromCast<Simd<[u8; 4]>> for i8x4[src]

impl FromCast<Simd<[usize; 4]>> for i8x4[src]

impl Hash for i8x4[src]

impl LowerHex for i8x4[src]

impl Mul<Simd<[i8; 4]>> for i8x4[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<i8> for i8x4[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[i8; 4]>> for i8x4[src]

impl MulAssign<i8> for i8x4[src]

impl Neg for i8x4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Not for i8x4[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl Octal for i8x4[src]

impl PartialEq<Simd<[i8; 4]>> for i8x4[src]

impl<'a> Product<&'a Simd<[i8; 4]>> for i8x4[src]

impl Product<Simd<[i8; 4]>> for i8x4[src]

impl Rem<Simd<[i8; 4]>> for i8x4[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<i8> for i8x4[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[i8; 4]>> for i8x4[src]

impl RemAssign<i8> for i8x4[src]

impl Shl<Simd<[i8; 4]>> for i8x4[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<u32> for i8x4[src]

type Output = Self

The resulting type after applying the << operator.

+

impl ShlAssign<Simd<[i8; 4]>> for i8x4[src]

impl ShlAssign<u32> for i8x4[src]

impl Shr<Simd<[i8; 4]>> for i8x4[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<u32> for i8x4[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl ShrAssign<Simd<[i8; 4]>> for i8x4[src]

impl ShrAssign<u32> for i8x4[src]

impl Simd for i8x4[src]

type Element = i8

Element type of the SIMD vector

+

type LanesType = [u32; 4]

The type: [u32; Self::N].

+

impl Sub<Simd<[i8; 4]>> for i8x4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<i8> for i8x4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[i8; 4]>> for i8x4[src]

impl SubAssign<i8> for i8x4[src]

impl<'a> Sum<&'a Simd<[i8; 4]>> for i8x4[src]

impl Sum<Simd<[i8; 4]>> for i8x4[src]

impl UpperHex for i8x4[src]

\ No newline at end of file diff --git a/packed_simd/type.i8x64.html b/packed_simd/type.i8x64.html new file mode 100644 index 000000000..0e029f7e4 --- /dev/null +++ b/packed_simd/type.i8x64.html @@ -0,0 +1,230 @@ +packed_simd::i8x64 - Rust

[−][src]Type Definition packed_simd::i8x64

type i8x64 = Simd<[i8; 64]>;

A 512-bit vector with 64 i8 lanes.

+

Implementations

impl i8x64[src]

pub const fn new(
    x0: i8,
    x1: i8,
    x2: i8,
    x3: i8,
    x4: i8,
    x5: i8,
    x6: i8,
    x7: i8,
    x8: i8,
    x9: i8,
    x10: i8,
    x11: i8,
    x12: i8,
    x13: i8,
    x14: i8,
    x15: i8,
    x16: i8,
    x17: i8,
    x18: i8,
    x19: i8,
    x20: i8,
    x21: i8,
    x22: i8,
    x23: i8,
    x24: i8,
    x25: i8,
    x26: i8,
    x27: i8,
    x28: i8,
    x29: i8,
    x30: i8,
    x31: i8,
    x32: i8,
    x33: i8,
    x34: i8,
    x35: i8,
    x36: i8,
    x37: i8,
    x38: i8,
    x39: i8,
    x40: i8,
    x41: i8,
    x42: i8,
    x43: i8,
    x44: i8,
    x45: i8,
    x46: i8,
    x47: i8,
    x48: i8,
    x49: i8,
    x50: i8,
    x51: i8,
    x52: i8,
    x53: i8,
    x54: i8,
    x55: i8,
    x56: i8,
    x57: i8,
    x58: i8,
    x59: i8,
    x60: i8,
    x61: i8,
    x62: i8,
    x63: i8
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: i8) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> i8[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> i8[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: i8) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: i8) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl i8x64[src]

pub fn rotate_left(self, n: i8x64) -> i8x64[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: i8x64) -> i8x64[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl i8x64[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl i8x64[src]

pub fn wrapping_sum(self) -> i8[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> i8[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl i8x64[src]

pub fn max_element(self) -> i8[src]

Largest vector element value.

+

pub fn min_element(self) -> i8[src]

Smallest vector element value.

+

impl i8x64[src]

pub fn and(self) -> i8[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> i8[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> i8[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl i8x64[src]

pub fn from_slice_aligned(slice: &[i8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[i8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[i8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[i8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl i8x64[src]

pub fn write_to_slice_aligned(self, slice: &mut [i8])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [i8])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [i8])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [i8])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl i8x64[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl i8x64[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl i8x64[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl i8x64[src]

pub fn eq(self, other: Self) -> m8x64[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m8x64[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m8x64[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m8x64[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m8x64[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m8x64[src]

Lane-wise greater-than-or-equals comparison.

+

impl i8x64[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<i8x64>[src]

Returns a wrapper that implements PartialOrd.

+

impl i8x64[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<i8x64>[src]

Returns a wrapper that implements Ord.

+

impl i8x64[src]

pub fn bitmask(self) -> u64[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl Add<Simd<[i8; 64]>> for i8x64[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<i8> for i8x64[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[i8; 64]>> for i8x64[src]

impl AddAssign<i8> for i8x64[src]

impl Binary for i8x64[src]

impl BitAnd<Simd<[i8; 64]>> for i8x64[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<i8> for i8x64[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[i8; 64]>> for i8x64[src]

impl BitAndAssign<i8> for i8x64[src]

impl BitOr<Simd<[i8; 64]>> for i8x64[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<i8> for i8x64[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[i8; 64]>> for i8x64[src]

impl BitOrAssign<i8> for i8x64[src]

impl BitXor<Simd<[i8; 64]>> for i8x64[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<i8> for i8x64[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[i8; 64]>> for i8x64[src]

impl BitXorAssign<i8> for i8x64[src]

impl Debug for i8x64[src]

impl Default for i8x64[src]

impl Div<Simd<[i8; 64]>> for i8x64[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<i8> for i8x64[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[i8; 64]>> for i8x64[src]

impl DivAssign<i8> for i8x64[src]

impl Eq for i8x64[src]

impl From<[i8; 64]> for i8x64[src]

impl FromBits<Simd<[f32; 16]>> for i8x64[src]

impl FromBits<Simd<[f64; 8]>> for i8x64[src]

impl FromBits<Simd<[i128; 4]>> for i8x64[src]

impl FromBits<Simd<[i16; 32]>> for i8x64[src]

impl FromBits<Simd<[i32; 16]>> for i8x64[src]

impl FromBits<Simd<[i64; 8]>> for i8x64[src]

impl FromBits<Simd<[m128; 4]>> for i8x64[src]

impl FromBits<Simd<[m16; 32]>> for i8x64[src]

impl FromBits<Simd<[m32; 16]>> for i8x64[src]

impl FromBits<Simd<[m64; 8]>> for i8x64[src]

impl FromBits<Simd<[m8; 64]>> for i8x64[src]

impl FromBits<Simd<[u128; 4]>> for i8x64[src]

impl FromBits<Simd<[u16; 32]>> for i8x64[src]

impl FromBits<Simd<[u32; 16]>> for i8x64[src]

impl FromBits<Simd<[u64; 8]>> for i8x64[src]

impl FromBits<Simd<[u8; 64]>> for i8x64[src]

impl FromCast<Simd<[m8; 64]>> for i8x64[src]

impl FromCast<Simd<[u8; 64]>> for i8x64[src]

impl Hash for i8x64[src]

impl LowerHex for i8x64[src]

impl Mul<Simd<[i8; 64]>> for i8x64[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<i8> for i8x64[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[i8; 64]>> for i8x64[src]

impl MulAssign<i8> for i8x64[src]

impl Neg for i8x64[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Not for i8x64[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl Octal for i8x64[src]

impl PartialEq<Simd<[i8; 64]>> for i8x64[src]

impl<'a> Product<&'a Simd<[i8; 64]>> for i8x64[src]

impl Product<Simd<[i8; 64]>> for i8x64[src]

impl Rem<Simd<[i8; 64]>> for i8x64[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<i8> for i8x64[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[i8; 64]>> for i8x64[src]

impl RemAssign<i8> for i8x64[src]

impl Shl<Simd<[i8; 64]>> for i8x64[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<u32> for i8x64[src]

type Output = Self

The resulting type after applying the << operator.

+

impl ShlAssign<Simd<[i8; 64]>> for i8x64[src]

impl ShlAssign<u32> for i8x64[src]

impl Shr<Simd<[i8; 64]>> for i8x64[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<u32> for i8x64[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl ShrAssign<Simd<[i8; 64]>> for i8x64[src]

impl ShrAssign<u32> for i8x64[src]

impl Simd for i8x64[src]

type Element = i8

Element type of the SIMD vector

+

type LanesType = [u32; 64]

The type: [u32; Self::N].

+

impl Sub<Simd<[i8; 64]>> for i8x64[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<i8> for i8x64[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[i8; 64]>> for i8x64[src]

impl SubAssign<i8> for i8x64[src]

impl<'a> Sum<&'a Simd<[i8; 64]>> for i8x64[src]

impl Sum<Simd<[i8; 64]>> for i8x64[src]

impl UpperHex for i8x64[src]

\ No newline at end of file diff --git a/packed_simd/type.i8x8.html b/packed_simd/type.i8x8.html new file mode 100644 index 000000000..b735490ee --- /dev/null +++ b/packed_simd/type.i8x8.html @@ -0,0 +1,238 @@ +packed_simd::i8x8 - Rust

[−][src]Type Definition packed_simd::i8x8

type i8x8 = Simd<[i8; 8]>;

A 64-bit vector with 8 i8 lanes.

+

Implementations

impl i8x8[src]

pub const fn new(
    x0: i8,
    x1: i8,
    x2: i8,
    x3: i8,
    x4: i8,
    x5: i8,
    x6: i8,
    x7: i8
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: i8) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> i8[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> i8[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: i8) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: i8) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl i8x8[src]

pub fn rotate_left(self, n: i8x8) -> i8x8[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: i8x8) -> i8x8[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl i8x8[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl i8x8[src]

pub fn wrapping_sum(self) -> i8[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> i8[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl i8x8[src]

pub fn max_element(self) -> i8[src]

Largest vector element value.

+

pub fn min_element(self) -> i8[src]

Smallest vector element value.

+

impl i8x8[src]

pub fn and(self) -> i8[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> i8[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> i8[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl i8x8[src]

pub fn from_slice_aligned(slice: &[i8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[i8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[i8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[i8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl i8x8[src]

pub fn write_to_slice_aligned(self, slice: &mut [i8])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [i8])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [i8])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [i8])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl i8x8[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl i8x8[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl i8x8[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl i8x8[src]

pub fn eq(self, other: Self) -> m8x8[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m8x8[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m8x8[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m8x8[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m8x8[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m8x8[src]

Lane-wise greater-than-or-equals comparison.

+

impl i8x8[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<i8x8>[src]

Returns a wrapper that implements PartialOrd.

+

impl i8x8[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<i8x8>[src]

Returns a wrapper that implements Ord.

+

impl i8x8[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl Add<Simd<[i8; 8]>> for i8x8[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<i8> for i8x8[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[i8; 8]>> for i8x8[src]

impl AddAssign<i8> for i8x8[src]

impl Binary for i8x8[src]

impl BitAnd<Simd<[i8; 8]>> for i8x8[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<i8> for i8x8[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[i8; 8]>> for i8x8[src]

impl BitAndAssign<i8> for i8x8[src]

impl BitOr<Simd<[i8; 8]>> for i8x8[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<i8> for i8x8[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[i8; 8]>> for i8x8[src]

impl BitOrAssign<i8> for i8x8[src]

impl BitXor<Simd<[i8; 8]>> for i8x8[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<i8> for i8x8[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[i8; 8]>> for i8x8[src]

impl BitXorAssign<i8> for i8x8[src]

impl Debug for i8x8[src]

impl Default for i8x8[src]

impl Div<Simd<[i8; 8]>> for i8x8[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<i8> for i8x8[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[i8; 8]>> for i8x8[src]

impl DivAssign<i8> for i8x8[src]

impl Eq for i8x8[src]

impl From<[i8; 8]> for i8x8[src]

impl FromBits<Simd<[f32; 2]>> for i8x8[src]

impl FromBits<Simd<[i16; 4]>> for i8x8[src]

impl FromBits<Simd<[i32; 2]>> for i8x8[src]

impl FromBits<Simd<[m16; 4]>> for i8x8[src]

impl FromBits<Simd<[m32; 2]>> for i8x8[src]

impl FromBits<Simd<[m8; 8]>> for i8x8[src]

impl FromBits<Simd<[u16; 4]>> for i8x8[src]

impl FromBits<Simd<[u32; 2]>> for i8x8[src]

impl FromBits<Simd<[u8; 8]>> for i8x8[src]

impl FromBits<__m64> for i8x8[src]

impl FromCast<Simd<[f32; 8]>> for i8x8[src]

impl FromCast<Simd<[f64; 8]>> for i8x8[src]

impl FromCast<Simd<[i16; 8]>> for i8x8[src]

impl FromCast<Simd<[i32; 8]>> for i8x8[src]

impl FromCast<Simd<[i64; 8]>> for i8x8[src]

impl FromCast<Simd<[isize; 8]>> for i8x8[src]

impl FromCast<Simd<[m16; 8]>> for i8x8[src]

impl FromCast<Simd<[m32; 8]>> for i8x8[src]

impl FromCast<Simd<[m64; 8]>> for i8x8[src]

impl FromCast<Simd<[m8; 8]>> for i8x8[src]

impl FromCast<Simd<[msize; 8]>> for i8x8[src]

impl FromCast<Simd<[u16; 8]>> for i8x8[src]

impl FromCast<Simd<[u32; 8]>> for i8x8[src]

impl FromCast<Simd<[u64; 8]>> for i8x8[src]

impl FromCast<Simd<[u8; 8]>> for i8x8[src]

impl FromCast<Simd<[usize; 8]>> for i8x8[src]

impl Hash for i8x8[src]

impl LowerHex for i8x8[src]

impl Mul<Simd<[i8; 8]>> for i8x8[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<i8> for i8x8[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[i8; 8]>> for i8x8[src]

impl MulAssign<i8> for i8x8[src]

impl Neg for i8x8[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Not for i8x8[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl Octal for i8x8[src]

impl PartialEq<Simd<[i8; 8]>> for i8x8[src]

impl<'a> Product<&'a Simd<[i8; 8]>> for i8x8[src]

impl Product<Simd<[i8; 8]>> for i8x8[src]

impl Rem<Simd<[i8; 8]>> for i8x8[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<i8> for i8x8[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[i8; 8]>> for i8x8[src]

impl RemAssign<i8> for i8x8[src]

impl Shl<Simd<[i8; 8]>> for i8x8[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<u32> for i8x8[src]

type Output = Self

The resulting type after applying the << operator.

+

impl ShlAssign<Simd<[i8; 8]>> for i8x8[src]

impl ShlAssign<u32> for i8x8[src]

impl Shr<Simd<[i8; 8]>> for i8x8[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<u32> for i8x8[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl ShrAssign<Simd<[i8; 8]>> for i8x8[src]

impl ShrAssign<u32> for i8x8[src]

impl Simd for i8x8[src]

type Element = i8

Element type of the SIMD vector

+

type LanesType = [u32; 8]

The type: [u32; Self::N].

+

impl Sub<Simd<[i8; 8]>> for i8x8[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<i8> for i8x8[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[i8; 8]>> for i8x8[src]

impl SubAssign<i8> for i8x8[src]

impl<'a> Sum<&'a Simd<[i8; 8]>> for i8x8[src]

impl Sum<Simd<[i8; 8]>> for i8x8[src]

impl UpperHex for i8x8[src]

\ No newline at end of file diff --git a/packed_simd/type.isizex2.html b/packed_simd/type.isizex2.html new file mode 100644 index 000000000..3fbe1bb91 --- /dev/null +++ b/packed_simd/type.isizex2.html @@ -0,0 +1,231 @@ +packed_simd::isizex2 - Rust

[−][src]Type Definition packed_simd::isizex2

type isizex2 = Simd<[isize; 2]>;

A vector with 2 isize lanes.

+

Implementations

impl isizex2[src]

pub const fn new(x0: isize, x1: isize) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: isize) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> isize[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> isize[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: isize) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: isize) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl isizex2[src]

pub fn rotate_left(self, n: isizex2) -> isizex2[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: isizex2) -> isizex2[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl isizex2[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl isizex2[src]

pub fn wrapping_sum(self) -> isize[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> isize[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl isizex2[src]

pub fn max_element(self) -> isize[src]

Largest vector element value.

+

pub fn min_element(self) -> isize[src]

Smallest vector element value.

+

impl isizex2[src]

pub fn and(self) -> isize[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> isize[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> isize[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl isizex2[src]

pub fn from_slice_aligned(slice: &[isize]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[isize]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[isize]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[isize]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl isizex2[src]

pub fn write_to_slice_aligned(self, slice: &mut [isize])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [isize])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [isize])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [isize])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl isizex2[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl isizex2[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl isizex2[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl isizex2[src]

pub fn eq(self, other: Self) -> msizex2[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> msizex2[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> msizex2[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> msizex2[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> msizex2[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> msizex2[src]

Lane-wise greater-than-or-equals comparison.

+

impl isizex2[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<isizex2>[src]

Returns a wrapper that implements PartialOrd.

+

impl isizex2[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<isizex2>[src]

Returns a wrapper that implements Ord.

+

impl isizex2[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl Add<Simd<[isize; 2]>> for isizex2[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<isize> for isizex2[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[isize; 2]>> for isizex2[src]

impl AddAssign<isize> for isizex2[src]

impl Binary for isizex2[src]

impl BitAnd<Simd<[isize; 2]>> for isizex2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<isize> for isizex2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[isize; 2]>> for isizex2[src]

impl BitAndAssign<isize> for isizex2[src]

impl BitOr<Simd<[isize; 2]>> for isizex2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<isize> for isizex2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[isize; 2]>> for isizex2[src]

impl BitOrAssign<isize> for isizex2[src]

impl BitXor<Simd<[isize; 2]>> for isizex2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<isize> for isizex2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[isize; 2]>> for isizex2[src]

impl BitXorAssign<isize> for isizex2[src]

impl Debug for isizex2[src]

impl Default for isizex2[src]

impl Div<Simd<[isize; 2]>> for isizex2[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<isize> for isizex2[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[isize; 2]>> for isizex2[src]

impl DivAssign<isize> for isizex2[src]

impl Eq for isizex2[src]

impl From<[isize; 2]> for isizex2[src]

impl FromCast<Simd<[f32; 2]>> for isizex2[src]

impl FromCast<Simd<[f64; 2]>> for isizex2[src]

impl FromCast<Simd<[i128; 2]>> for isizex2[src]

impl FromCast<Simd<[i16; 2]>> for isizex2[src]

impl FromCast<Simd<[i32; 2]>> for isizex2[src]

impl FromCast<Simd<[i64; 2]>> for isizex2[src]

impl FromCast<Simd<[i8; 2]>> for isizex2[src]

impl FromCast<Simd<[m128; 2]>> for isizex2[src]

impl FromCast<Simd<[m16; 2]>> for isizex2[src]

impl FromCast<Simd<[m32; 2]>> for isizex2[src]

impl FromCast<Simd<[m64; 2]>> for isizex2[src]

impl FromCast<Simd<[m8; 2]>> for isizex2[src]

impl FromCast<Simd<[msize; 2]>> for isizex2[src]

impl FromCast<Simd<[u128; 2]>> for isizex2[src]

impl FromCast<Simd<[u16; 2]>> for isizex2[src]

impl FromCast<Simd<[u32; 2]>> for isizex2[src]

impl FromCast<Simd<[u64; 2]>> for isizex2[src]

impl FromCast<Simd<[u8; 2]>> for isizex2[src]

impl FromCast<Simd<[usize; 2]>> for isizex2[src]

impl Hash for isizex2[src]

impl LowerHex for isizex2[src]

impl Mul<Simd<[isize; 2]>> for isizex2[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<isize> for isizex2[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[isize; 2]>> for isizex2[src]

impl MulAssign<isize> for isizex2[src]

impl Neg for isizex2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Not for isizex2[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl Octal for isizex2[src]

impl PartialEq<Simd<[isize; 2]>> for isizex2[src]

impl<'a> Product<&'a Simd<[isize; 2]>> for isizex2[src]

impl Product<Simd<[isize; 2]>> for isizex2[src]

impl Rem<Simd<[isize; 2]>> for isizex2[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<isize> for isizex2[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[isize; 2]>> for isizex2[src]

impl RemAssign<isize> for isizex2[src]

impl Shl<Simd<[isize; 2]>> for isizex2[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<u32> for isizex2[src]

type Output = Self

The resulting type after applying the << operator.

+

impl ShlAssign<Simd<[isize; 2]>> for isizex2[src]

impl ShlAssign<u32> for isizex2[src]

impl Shr<Simd<[isize; 2]>> for isizex2[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<u32> for isizex2[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl ShrAssign<Simd<[isize; 2]>> for isizex2[src]

impl ShrAssign<u32> for isizex2[src]

impl Simd for isizex2[src]

type Element = isize

Element type of the SIMD vector

+

type LanesType = [u32; 2]

The type: [u32; Self::N].

+

impl Sub<Simd<[isize; 2]>> for isizex2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<isize> for isizex2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[isize; 2]>> for isizex2[src]

impl SubAssign<isize> for isizex2[src]

impl<'a> Sum<&'a Simd<[isize; 2]>> for isizex2[src]

impl Sum<Simd<[isize; 2]>> for isizex2[src]

impl UpperHex for isizex2[src]

\ No newline at end of file diff --git a/packed_simd/type.isizex4.html b/packed_simd/type.isizex4.html new file mode 100644 index 000000000..049542dab --- /dev/null +++ b/packed_simd/type.isizex4.html @@ -0,0 +1,231 @@ +packed_simd::isizex4 - Rust

[−][src]Type Definition packed_simd::isizex4

type isizex4 = Simd<[isize; 4]>;

A vector with 4 isize lanes.

+

Implementations

impl isizex4[src]

pub const fn new(x0: isize, x1: isize, x2: isize, x3: isize) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: isize) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> isize[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> isize[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: isize) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: isize) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl isizex4[src]

pub fn rotate_left(self, n: isizex4) -> isizex4[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: isizex4) -> isizex4[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl isizex4[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl isizex4[src]

pub fn wrapping_sum(self) -> isize[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> isize[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl isizex4[src]

pub fn max_element(self) -> isize[src]

Largest vector element value.

+

pub fn min_element(self) -> isize[src]

Smallest vector element value.

+

impl isizex4[src]

pub fn and(self) -> isize[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> isize[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> isize[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl isizex4[src]

pub fn from_slice_aligned(slice: &[isize]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[isize]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[isize]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[isize]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl isizex4[src]

pub fn write_to_slice_aligned(self, slice: &mut [isize])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [isize])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [isize])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [isize])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl isizex4[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl isizex4[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl isizex4[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl isizex4[src]

pub fn eq(self, other: Self) -> msizex4[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> msizex4[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> msizex4[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> msizex4[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> msizex4[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> msizex4[src]

Lane-wise greater-than-or-equals comparison.

+

impl isizex4[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<isizex4>[src]

Returns a wrapper that implements PartialOrd.

+

impl isizex4[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<isizex4>[src]

Returns a wrapper that implements Ord.

+

impl isizex4[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl Add<Simd<[isize; 4]>> for isizex4[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<isize> for isizex4[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[isize; 4]>> for isizex4[src]

impl AddAssign<isize> for isizex4[src]

impl Binary for isizex4[src]

impl BitAnd<Simd<[isize; 4]>> for isizex4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<isize> for isizex4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[isize; 4]>> for isizex4[src]

impl BitAndAssign<isize> for isizex4[src]

impl BitOr<Simd<[isize; 4]>> for isizex4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<isize> for isizex4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[isize; 4]>> for isizex4[src]

impl BitOrAssign<isize> for isizex4[src]

impl BitXor<Simd<[isize; 4]>> for isizex4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<isize> for isizex4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[isize; 4]>> for isizex4[src]

impl BitXorAssign<isize> for isizex4[src]

impl Debug for isizex4[src]

impl Default for isizex4[src]

impl Div<Simd<[isize; 4]>> for isizex4[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<isize> for isizex4[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[isize; 4]>> for isizex4[src]

impl DivAssign<isize> for isizex4[src]

impl Eq for isizex4[src]

impl From<[isize; 4]> for isizex4[src]

impl FromCast<Simd<[f32; 4]>> for isizex4[src]

impl FromCast<Simd<[f64; 4]>> for isizex4[src]

impl FromCast<Simd<[i128; 4]>> for isizex4[src]

impl FromCast<Simd<[i16; 4]>> for isizex4[src]

impl FromCast<Simd<[i32; 4]>> for isizex4[src]

impl FromCast<Simd<[i64; 4]>> for isizex4[src]

impl FromCast<Simd<[i8; 4]>> for isizex4[src]

impl FromCast<Simd<[m128; 4]>> for isizex4[src]

impl FromCast<Simd<[m16; 4]>> for isizex4[src]

impl FromCast<Simd<[m32; 4]>> for isizex4[src]

impl FromCast<Simd<[m64; 4]>> for isizex4[src]

impl FromCast<Simd<[m8; 4]>> for isizex4[src]

impl FromCast<Simd<[msize; 4]>> for isizex4[src]

impl FromCast<Simd<[u128; 4]>> for isizex4[src]

impl FromCast<Simd<[u16; 4]>> for isizex4[src]

impl FromCast<Simd<[u32; 4]>> for isizex4[src]

impl FromCast<Simd<[u64; 4]>> for isizex4[src]

impl FromCast<Simd<[u8; 4]>> for isizex4[src]

impl FromCast<Simd<[usize; 4]>> for isizex4[src]

impl Hash for isizex4[src]

impl LowerHex for isizex4[src]

impl Mul<Simd<[isize; 4]>> for isizex4[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<isize> for isizex4[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[isize; 4]>> for isizex4[src]

impl MulAssign<isize> for isizex4[src]

impl Neg for isizex4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Not for isizex4[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl Octal for isizex4[src]

impl PartialEq<Simd<[isize; 4]>> for isizex4[src]

impl<'a> Product<&'a Simd<[isize; 4]>> for isizex4[src]

impl Product<Simd<[isize; 4]>> for isizex4[src]

impl Rem<Simd<[isize; 4]>> for isizex4[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<isize> for isizex4[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[isize; 4]>> for isizex4[src]

impl RemAssign<isize> for isizex4[src]

impl Shl<Simd<[isize; 4]>> for isizex4[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<u32> for isizex4[src]

type Output = Self

The resulting type after applying the << operator.

+

impl ShlAssign<Simd<[isize; 4]>> for isizex4[src]

impl ShlAssign<u32> for isizex4[src]

impl Shr<Simd<[isize; 4]>> for isizex4[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<u32> for isizex4[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl ShrAssign<Simd<[isize; 4]>> for isizex4[src]

impl ShrAssign<u32> for isizex4[src]

impl Simd for isizex4[src]

type Element = isize

Element type of the SIMD vector

+

type LanesType = [u32; 4]

The type: [u32; Self::N].

+

impl Sub<Simd<[isize; 4]>> for isizex4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<isize> for isizex4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[isize; 4]>> for isizex4[src]

impl SubAssign<isize> for isizex4[src]

impl<'a> Sum<&'a Simd<[isize; 4]>> for isizex4[src]

impl Sum<Simd<[isize; 4]>> for isizex4[src]

impl UpperHex for isizex4[src]

\ No newline at end of file diff --git a/packed_simd/type.isizex8.html b/packed_simd/type.isizex8.html new file mode 100644 index 000000000..7a6cf1504 --- /dev/null +++ b/packed_simd/type.isizex8.html @@ -0,0 +1,228 @@ +packed_simd::isizex8 - Rust

[−][src]Type Definition packed_simd::isizex8

type isizex8 = Simd<[isize; 8]>;

A vector with 4 isize lanes.

+

Implementations

impl isizex8[src]

pub const fn new(
    x0: isize,
    x1: isize,
    x2: isize,
    x3: isize,
    x4: isize,
    x5: isize,
    x6: isize,
    x7: isize
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: isize) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> isize[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> isize[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: isize) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: isize) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl isizex8[src]

pub fn rotate_left(self, n: isizex8) -> isizex8[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: isizex8) -> isizex8[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl isizex8[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl isizex8[src]

pub fn wrapping_sum(self) -> isize[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> isize[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl isizex8[src]

pub fn max_element(self) -> isize[src]

Largest vector element value.

+

pub fn min_element(self) -> isize[src]

Smallest vector element value.

+

impl isizex8[src]

pub fn and(self) -> isize[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> isize[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> isize[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl isizex8[src]

pub fn from_slice_aligned(slice: &[isize]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[isize]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[isize]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[isize]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl isizex8[src]

pub fn write_to_slice_aligned(self, slice: &mut [isize])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [isize])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [isize])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [isize])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl isizex8[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl isizex8[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl isizex8[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl isizex8[src]

pub fn eq(self, other: Self) -> msizex8[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> msizex8[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> msizex8[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> msizex8[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> msizex8[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> msizex8[src]

Lane-wise greater-than-or-equals comparison.

+

impl isizex8[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<isizex8>[src]

Returns a wrapper that implements PartialOrd.

+

impl isizex8[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<isizex8>[src]

Returns a wrapper that implements Ord.

+

impl isizex8[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl Add<Simd<[isize; 8]>> for isizex8[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<isize> for isizex8[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[isize; 8]>> for isizex8[src]

impl AddAssign<isize> for isizex8[src]

impl Binary for isizex8[src]

impl BitAnd<Simd<[isize; 8]>> for isizex8[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<isize> for isizex8[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[isize; 8]>> for isizex8[src]

impl BitAndAssign<isize> for isizex8[src]

impl BitOr<Simd<[isize; 8]>> for isizex8[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<isize> for isizex8[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[isize; 8]>> for isizex8[src]

impl BitOrAssign<isize> for isizex8[src]

impl BitXor<Simd<[isize; 8]>> for isizex8[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<isize> for isizex8[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[isize; 8]>> for isizex8[src]

impl BitXorAssign<isize> for isizex8[src]

impl Debug for isizex8[src]

impl Default for isizex8[src]

impl Div<Simd<[isize; 8]>> for isizex8[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<isize> for isizex8[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[isize; 8]>> for isizex8[src]

impl DivAssign<isize> for isizex8[src]

impl Eq for isizex8[src]

impl From<[isize; 8]> for isizex8[src]

impl FromCast<Simd<[f32; 8]>> for isizex8[src]

impl FromCast<Simd<[f64; 8]>> for isizex8[src]

impl FromCast<Simd<[i16; 8]>> for isizex8[src]

impl FromCast<Simd<[i32; 8]>> for isizex8[src]

impl FromCast<Simd<[i64; 8]>> for isizex8[src]

impl FromCast<Simd<[i8; 8]>> for isizex8[src]

impl FromCast<Simd<[m16; 8]>> for isizex8[src]

impl FromCast<Simd<[m32; 8]>> for isizex8[src]

impl FromCast<Simd<[m64; 8]>> for isizex8[src]

impl FromCast<Simd<[m8; 8]>> for isizex8[src]

impl FromCast<Simd<[msize; 8]>> for isizex8[src]

impl FromCast<Simd<[u16; 8]>> for isizex8[src]

impl FromCast<Simd<[u32; 8]>> for isizex8[src]

impl FromCast<Simd<[u64; 8]>> for isizex8[src]

impl FromCast<Simd<[u8; 8]>> for isizex8[src]

impl FromCast<Simd<[usize; 8]>> for isizex8[src]

impl Hash for isizex8[src]

impl LowerHex for isizex8[src]

impl Mul<Simd<[isize; 8]>> for isizex8[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<isize> for isizex8[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[isize; 8]>> for isizex8[src]

impl MulAssign<isize> for isizex8[src]

impl Neg for isizex8[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Not for isizex8[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl Octal for isizex8[src]

impl PartialEq<Simd<[isize; 8]>> for isizex8[src]

impl<'a> Product<&'a Simd<[isize; 8]>> for isizex8[src]

impl Product<Simd<[isize; 8]>> for isizex8[src]

impl Rem<Simd<[isize; 8]>> for isizex8[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<isize> for isizex8[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[isize; 8]>> for isizex8[src]

impl RemAssign<isize> for isizex8[src]

impl Shl<Simd<[isize; 8]>> for isizex8[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<u32> for isizex8[src]

type Output = Self

The resulting type after applying the << operator.

+

impl ShlAssign<Simd<[isize; 8]>> for isizex8[src]

impl ShlAssign<u32> for isizex8[src]

impl Shr<Simd<[isize; 8]>> for isizex8[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<u32> for isizex8[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl ShrAssign<Simd<[isize; 8]>> for isizex8[src]

impl ShrAssign<u32> for isizex8[src]

impl Simd for isizex8[src]

type Element = isize

Element type of the SIMD vector

+

type LanesType = [u32; 8]

The type: [u32; Self::N].

+

impl Sub<Simd<[isize; 8]>> for isizex8[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<isize> for isizex8[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[isize; 8]>> for isizex8[src]

impl SubAssign<isize> for isizex8[src]

impl<'a> Sum<&'a Simd<[isize; 8]>> for isizex8[src]

impl Sum<Simd<[isize; 8]>> for isizex8[src]

impl UpperHex for isizex8[src]

\ No newline at end of file diff --git a/packed_simd/type.m128x1.html b/packed_simd/type.m128x1.html new file mode 100644 index 000000000..0f81f00ae --- /dev/null +++ b/packed_simd/type.m128x1.html @@ -0,0 +1,84 @@ +packed_simd::m128x1 - Rust

[−][src]Type Definition packed_simd::m128x1

type m128x1 = Simd<[m128; 1]>;

A 128-bit vector mask with 1 m128 lane.

+

Implementations

impl m128x1[src]

pub const fn new(x0: bool) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: bool) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> bool[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> bool[src]

Extracts the value at index.

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

impl m128x1[src]

pub fn and(self) -> bool[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> bool[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> bool[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl m128x1[src]

pub fn all(self) -> bool[src]

Are all vector lanes true?

+

pub fn any(self) -> bool[src]

Is any vector lane true?

+

pub fn none(self) -> bool[src]

Are all vector lanes false?

+

impl m128x1[src]

pub fn eq(self, other: Self) -> m128x1[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m128x1[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m128x1[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m128x1[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m128x1[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m128x1[src]

Lane-wise greater-than-or-equals comparison.

+

impl m128x1[src]

pub fn select<T>(self, a: Simd<T>, b: Simd<T>) -> Simd<T> where
    T: SimdArray<NT = <[m128; 1] as SimdArray>::NT>, [src]

Selects elements of a and b using mask.

+

The lanes of the result for which the mask is true contain +the values of a. The remaining lanes contain the values of +b.

+

impl m128x1[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<m128x1>[src]

Returns a wrapper that implements PartialOrd.

+

impl m128x1[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<m128x1>[src]

Returns a wrapper that implements Ord.

+

impl m128x1[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl m128x1[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl BitAnd<Simd<[m128; 1]>> for m128x1[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<bool> for m128x1[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[m128; 1]>> for m128x1[src]

impl BitAndAssign<bool> for m128x1[src]

impl BitOr<Simd<[m128; 1]>> for m128x1[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<bool> for m128x1[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[m128; 1]>> for m128x1[src]

impl BitOrAssign<bool> for m128x1[src]

impl BitXor<Simd<[m128; 1]>> for m128x1[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<bool> for m128x1[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[m128; 1]>> for m128x1[src]

impl BitXorAssign<bool> for m128x1[src]

impl Debug for m128x1[src]

impl Default for m128x1[src]

impl Eq for m128x1[src]

impl From<[m128; 1]> for m128x1[src]

impl FromCast<Simd<[i128; 1]>> for m128x1[src]

impl FromCast<Simd<[u128; 1]>> for m128x1[src]

impl Not for m128x1[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl PartialEq<Simd<[m128; 1]>> for m128x1[src]

impl Simd for m128x1[src]

type Element = m128

Element type of the SIMD vector

+

type LanesType = [u32; 1]

The type: [u32; Self::N].

+
\ No newline at end of file diff --git a/packed_simd/type.m128x2.html b/packed_simd/type.m128x2.html new file mode 100644 index 000000000..1c619d494 --- /dev/null +++ b/packed_simd/type.m128x2.html @@ -0,0 +1,105 @@ +packed_simd::m128x2 - Rust

[−][src]Type Definition packed_simd::m128x2

type m128x2 = Simd<[m128; 2]>;

A 256-bit vector mask with 2 m128 lanes.

+

Implementations

impl m128x2[src]

pub const fn new(x0: bool, x1: bool) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: bool) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> bool[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> bool[src]

Extracts the value at index.

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

impl m128x2[src]

pub fn and(self) -> bool[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> bool[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> bool[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl m128x2[src]

pub fn all(self) -> bool[src]

Are all vector lanes true?

+

pub fn any(self) -> bool[src]

Is any vector lane true?

+

pub fn none(self) -> bool[src]

Are all vector lanes false?

+

impl m128x2[src]

pub fn eq(self, other: Self) -> m128x2[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m128x2[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m128x2[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m128x2[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m128x2[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m128x2[src]

Lane-wise greater-than-or-equals comparison.

+

impl m128x2[src]

pub fn select<T>(self, a: Simd<T>, b: Simd<T>) -> Simd<T> where
    T: SimdArray<NT = <[m128; 2] as SimdArray>::NT>, [src]

Selects elements of a and b using mask.

+

The lanes of the result for which the mask is true contain +the values of a. The remaining lanes contain the values of +b.

+

impl m128x2[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<m128x2>[src]

Returns a wrapper that implements PartialOrd.

+

impl m128x2[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<m128x2>[src]

Returns a wrapper that implements Ord.

+

impl m128x2[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl m128x2[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl BitAnd<Simd<[m128; 2]>> for m128x2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<bool> for m128x2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[m128; 2]>> for m128x2[src]

impl BitAndAssign<bool> for m128x2[src]

impl BitOr<Simd<[m128; 2]>> for m128x2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<bool> for m128x2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[m128; 2]>> for m128x2[src]

impl BitOrAssign<bool> for m128x2[src]

impl BitXor<Simd<[m128; 2]>> for m128x2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<bool> for m128x2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[m128; 2]>> for m128x2[src]

impl BitXorAssign<bool> for m128x2[src]

impl Debug for m128x2[src]

impl Default for m128x2[src]

impl Eq for m128x2[src]

impl From<[m128; 2]> for m128x2[src]

impl From<Simd<[m16; 2]>> for m128x2[src]

impl From<Simd<[m32; 2]>> for m128x2[src]

impl From<Simd<[m64; 2]>> for m128x2[src]

impl From<Simd<[m8; 2]>> for m128x2[src]

impl FromCast<Simd<[f32; 2]>> for m128x2[src]

impl FromCast<Simd<[f64; 2]>> for m128x2[src]

impl FromCast<Simd<[i128; 2]>> for m128x2[src]

impl FromCast<Simd<[i16; 2]>> for m128x2[src]

impl FromCast<Simd<[i32; 2]>> for m128x2[src]

impl FromCast<Simd<[i64; 2]>> for m128x2[src]

impl FromCast<Simd<[i8; 2]>> for m128x2[src]

impl FromCast<Simd<[isize; 2]>> for m128x2[src]

impl FromCast<Simd<[m16; 2]>> for m128x2[src]

impl FromCast<Simd<[m32; 2]>> for m128x2[src]

impl FromCast<Simd<[m64; 2]>> for m128x2[src]

impl FromCast<Simd<[m8; 2]>> for m128x2[src]

impl FromCast<Simd<[msize; 2]>> for m128x2[src]

impl FromCast<Simd<[u128; 2]>> for m128x2[src]

impl FromCast<Simd<[u16; 2]>> for m128x2[src]

impl FromCast<Simd<[u32; 2]>> for m128x2[src]

impl FromCast<Simd<[u64; 2]>> for m128x2[src]

impl FromCast<Simd<[u8; 2]>> for m128x2[src]

impl FromCast<Simd<[usize; 2]>> for m128x2[src]

impl Not for m128x2[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl PartialEq<Simd<[m128; 2]>> for m128x2[src]

impl Simd for m128x2[src]

type Element = m128

Element type of the SIMD vector

+

type LanesType = [u32; 2]

The type: [u32; Self::N].

+
\ No newline at end of file diff --git a/packed_simd/type.m128x4.html b/packed_simd/type.m128x4.html new file mode 100644 index 000000000..c8db7fcd6 --- /dev/null +++ b/packed_simd/type.m128x4.html @@ -0,0 +1,105 @@ +packed_simd::m128x4 - Rust

[−][src]Type Definition packed_simd::m128x4

type m128x4 = Simd<[m128; 4]>;

A 512-bit vector mask with 4 m128 lanes.

+

Implementations

impl m128x4[src]

pub const fn new(x0: bool, x1: bool, x2: bool, x3: bool) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: bool) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> bool[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> bool[src]

Extracts the value at index.

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

impl m128x4[src]

pub fn and(self) -> bool[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> bool[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> bool[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl m128x4[src]

pub fn all(self) -> bool[src]

Are all vector lanes true?

+

pub fn any(self) -> bool[src]

Is any vector lane true?

+

pub fn none(self) -> bool[src]

Are all vector lanes false?

+

impl m128x4[src]

pub fn eq(self, other: Self) -> m128x4[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m128x4[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m128x4[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m128x4[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m128x4[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m128x4[src]

Lane-wise greater-than-or-equals comparison.

+

impl m128x4[src]

pub fn select<T>(self, a: Simd<T>, b: Simd<T>) -> Simd<T> where
    T: SimdArray<NT = <[m128; 4] as SimdArray>::NT>, [src]

Selects elements of a and b using mask.

+

The lanes of the result for which the mask is true contain +the values of a. The remaining lanes contain the values of +b.

+

impl m128x4[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<m128x4>[src]

Returns a wrapper that implements PartialOrd.

+

impl m128x4[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<m128x4>[src]

Returns a wrapper that implements Ord.

+

impl m128x4[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl m128x4[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl BitAnd<Simd<[m128; 4]>> for m128x4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<bool> for m128x4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[m128; 4]>> for m128x4[src]

impl BitAndAssign<bool> for m128x4[src]

impl BitOr<Simd<[m128; 4]>> for m128x4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<bool> for m128x4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[m128; 4]>> for m128x4[src]

impl BitOrAssign<bool> for m128x4[src]

impl BitXor<Simd<[m128; 4]>> for m128x4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<bool> for m128x4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[m128; 4]>> for m128x4[src]

impl BitXorAssign<bool> for m128x4[src]

impl Debug for m128x4[src]

impl Default for m128x4[src]

impl Eq for m128x4[src]

impl From<[m128; 4]> for m128x4[src]

impl From<Simd<[m16; 4]>> for m128x4[src]

impl From<Simd<[m32; 4]>> for m128x4[src]

impl From<Simd<[m64; 4]>> for m128x4[src]

impl From<Simd<[m8; 4]>> for m128x4[src]

impl FromCast<Simd<[f32; 4]>> for m128x4[src]

impl FromCast<Simd<[f64; 4]>> for m128x4[src]

impl FromCast<Simd<[i128; 4]>> for m128x4[src]

impl FromCast<Simd<[i16; 4]>> for m128x4[src]

impl FromCast<Simd<[i32; 4]>> for m128x4[src]

impl FromCast<Simd<[i64; 4]>> for m128x4[src]

impl FromCast<Simd<[i8; 4]>> for m128x4[src]

impl FromCast<Simd<[isize; 4]>> for m128x4[src]

impl FromCast<Simd<[m16; 4]>> for m128x4[src]

impl FromCast<Simd<[m32; 4]>> for m128x4[src]

impl FromCast<Simd<[m64; 4]>> for m128x4[src]

impl FromCast<Simd<[m8; 4]>> for m128x4[src]

impl FromCast<Simd<[msize; 4]>> for m128x4[src]

impl FromCast<Simd<[u128; 4]>> for m128x4[src]

impl FromCast<Simd<[u16; 4]>> for m128x4[src]

impl FromCast<Simd<[u32; 4]>> for m128x4[src]

impl FromCast<Simd<[u64; 4]>> for m128x4[src]

impl FromCast<Simd<[u8; 4]>> for m128x4[src]

impl FromCast<Simd<[usize; 4]>> for m128x4[src]

impl Not for m128x4[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl PartialEq<Simd<[m128; 4]>> for m128x4[src]

impl Simd for m128x4[src]

type Element = m128

Element type of the SIMD vector

+

type LanesType = [u32; 4]

The type: [u32; Self::N].

+
\ No newline at end of file diff --git a/packed_simd/type.m16x16.html b/packed_simd/type.m16x16.html new file mode 100644 index 000000000..553e3cceb --- /dev/null +++ b/packed_simd/type.m16x16.html @@ -0,0 +1,95 @@ +packed_simd::m16x16 - Rust

[−][src]Type Definition packed_simd::m16x16

type m16x16 = Simd<[m16; 16]>;

A 256-bit vector mask with 16 m16 lanes.

+

Implementations

impl m16x16[src]

pub const fn new(
    x0: bool,
    x1: bool,
    x2: bool,
    x3: bool,
    x4: bool,
    x5: bool,
    x6: bool,
    x7: bool,
    x8: bool,
    x9: bool,
    x10: bool,
    x11: bool,
    x12: bool,
    x13: bool,
    x14: bool,
    x15: bool
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: bool) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> bool[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> bool[src]

Extracts the value at index.

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

impl m16x16[src]

pub fn and(self) -> bool[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> bool[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> bool[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl m16x16[src]

pub fn all(self) -> bool[src]

Are all vector lanes true?

+

pub fn any(self) -> bool[src]

Is any vector lane true?

+

pub fn none(self) -> bool[src]

Are all vector lanes false?

+

impl m16x16[src]

pub fn eq(self, other: Self) -> m16x16[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m16x16[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m16x16[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m16x16[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m16x16[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m16x16[src]

Lane-wise greater-than-or-equals comparison.

+

impl m16x16[src]

pub fn select<T>(self, a: Simd<T>, b: Simd<T>) -> Simd<T> where
    T: SimdArray<NT = <[m16; 16] as SimdArray>::NT>, [src]

Selects elements of a and b using mask.

+

The lanes of the result for which the mask is true contain +the values of a. The remaining lanes contain the values of +b.

+

impl m16x16[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<m16x16>[src]

Returns a wrapper that implements PartialOrd.

+

impl m16x16[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<m16x16>[src]

Returns a wrapper that implements Ord.

+

impl m16x16[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl m16x16[src]

pub fn bitmask(self) -> u16[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl BitAnd<Simd<[m16; 16]>> for m16x16[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<bool> for m16x16[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[m16; 16]>> for m16x16[src]

impl BitAndAssign<bool> for m16x16[src]

impl BitOr<Simd<[m16; 16]>> for m16x16[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<bool> for m16x16[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[m16; 16]>> for m16x16[src]

impl BitOrAssign<bool> for m16x16[src]

impl BitXor<Simd<[m16; 16]>> for m16x16[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<bool> for m16x16[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[m16; 16]>> for m16x16[src]

impl BitXorAssign<bool> for m16x16[src]

impl Debug for m16x16[src]

impl Default for m16x16[src]

impl Eq for m16x16[src]

impl From<[m16; 16]> for m16x16[src]

impl From<Simd<[m8; 16]>> for m16x16[src]

impl FromBits<Simd<[m128; 2]>> for m16x16[src]

impl FromBits<Simd<[m32; 8]>> for m16x16[src]

impl FromBits<Simd<[m64; 4]>> for m16x16[src]

impl FromCast<Simd<[f32; 16]>> for m16x16[src]

impl FromCast<Simd<[i16; 16]>> for m16x16[src]

impl FromCast<Simd<[i32; 16]>> for m16x16[src]

impl FromCast<Simd<[i8; 16]>> for m16x16[src]

impl FromCast<Simd<[m32; 16]>> for m16x16[src]

impl FromCast<Simd<[m8; 16]>> for m16x16[src]

impl FromCast<Simd<[u16; 16]>> for m16x16[src]

impl FromCast<Simd<[u32; 16]>> for m16x16[src]

impl FromCast<Simd<[u8; 16]>> for m16x16[src]

impl Not for m16x16[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl PartialEq<Simd<[m16; 16]>> for m16x16[src]

impl Simd for m16x16[src]

type Element = m16

Element type of the SIMD vector

+

type LanesType = [u32; 16]

The type: [u32; Self::N].

+
\ No newline at end of file diff --git a/packed_simd/type.m16x2.html b/packed_simd/type.m16x2.html new file mode 100644 index 000000000..184b92060 --- /dev/null +++ b/packed_simd/type.m16x2.html @@ -0,0 +1,105 @@ +packed_simd::m16x2 - Rust

[−][src]Type Definition packed_simd::m16x2

type m16x2 = Simd<[m16; 2]>;

A 32-bit vector mask with 2 m16 lanes.

+

Implementations

impl m16x2[src]

pub const fn new(x0: bool, x1: bool) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: bool) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> bool[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> bool[src]

Extracts the value at index.

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

impl m16x2[src]

pub fn and(self) -> bool[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> bool[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> bool[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl m16x2[src]

pub fn all(self) -> bool[src]

Are all vector lanes true?

+

pub fn any(self) -> bool[src]

Is any vector lane true?

+

pub fn none(self) -> bool[src]

Are all vector lanes false?

+

impl m16x2[src]

pub fn eq(self, other: Self) -> m16x2[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m16x2[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m16x2[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m16x2[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m16x2[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m16x2[src]

Lane-wise greater-than-or-equals comparison.

+

impl m16x2[src]

pub fn select<T>(self, a: Simd<T>, b: Simd<T>) -> Simd<T> where
    T: SimdArray<NT = <[m16; 2] as SimdArray>::NT>, [src]

Selects elements of a and b using mask.

+

The lanes of the result for which the mask is true contain +the values of a. The remaining lanes contain the values of +b.

+

impl m16x2[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<m16x2>[src]

Returns a wrapper that implements PartialOrd.

+

impl m16x2[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<m16x2>[src]

Returns a wrapper that implements Ord.

+

impl m16x2[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl m16x2[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl BitAnd<Simd<[m16; 2]>> for m16x2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<bool> for m16x2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[m16; 2]>> for m16x2[src]

impl BitAndAssign<bool> for m16x2[src]

impl BitOr<Simd<[m16; 2]>> for m16x2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<bool> for m16x2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[m16; 2]>> for m16x2[src]

impl BitOrAssign<bool> for m16x2[src]

impl BitXor<Simd<[m16; 2]>> for m16x2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<bool> for m16x2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[m16; 2]>> for m16x2[src]

impl BitXorAssign<bool> for m16x2[src]

impl Debug for m16x2[src]

impl Default for m16x2[src]

impl Eq for m16x2[src]

impl From<[m16; 2]> for m16x2[src]

impl From<Simd<[m128; 2]>> for m16x2[src]

impl From<Simd<[m32; 2]>> for m16x2[src]

impl From<Simd<[m64; 2]>> for m16x2[src]

impl From<Simd<[m8; 2]>> for m16x2[src]

impl FromCast<Simd<[f32; 2]>> for m16x2[src]

impl FromCast<Simd<[f64; 2]>> for m16x2[src]

impl FromCast<Simd<[i128; 2]>> for m16x2[src]

impl FromCast<Simd<[i16; 2]>> for m16x2[src]

impl FromCast<Simd<[i32; 2]>> for m16x2[src]

impl FromCast<Simd<[i64; 2]>> for m16x2[src]

impl FromCast<Simd<[i8; 2]>> for m16x2[src]

impl FromCast<Simd<[isize; 2]>> for m16x2[src]

impl FromCast<Simd<[m128; 2]>> for m16x2[src]

impl FromCast<Simd<[m32; 2]>> for m16x2[src]

impl FromCast<Simd<[m64; 2]>> for m16x2[src]

impl FromCast<Simd<[m8; 2]>> for m16x2[src]

impl FromCast<Simd<[msize; 2]>> for m16x2[src]

impl FromCast<Simd<[u128; 2]>> for m16x2[src]

impl FromCast<Simd<[u16; 2]>> for m16x2[src]

impl FromCast<Simd<[u32; 2]>> for m16x2[src]

impl FromCast<Simd<[u64; 2]>> for m16x2[src]

impl FromCast<Simd<[u8; 2]>> for m16x2[src]

impl FromCast<Simd<[usize; 2]>> for m16x2[src]

impl Not for m16x2[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl PartialEq<Simd<[m16; 2]>> for m16x2[src]

impl Simd for m16x2[src]

type Element = m16

Element type of the SIMD vector

+

type LanesType = [u32; 2]

The type: [u32; Self::N].

+
\ No newline at end of file diff --git a/packed_simd/type.m16x32.html b/packed_simd/type.m16x32.html new file mode 100644 index 000000000..f8d8ffad9 --- /dev/null +++ b/packed_simd/type.m16x32.html @@ -0,0 +1,91 @@ +packed_simd::m16x32 - Rust

[−][src]Type Definition packed_simd::m16x32

type m16x32 = Simd<[m16; 32]>;

A 512-bit vector mask with 32 m16 lanes.

+

Implementations

impl m16x32[src]

pub const fn new(
    x0: bool,
    x1: bool,
    x2: bool,
    x3: bool,
    x4: bool,
    x5: bool,
    x6: bool,
    x7: bool,
    x8: bool,
    x9: bool,
    x10: bool,
    x11: bool,
    x12: bool,
    x13: bool,
    x14: bool,
    x15: bool,
    x16: bool,
    x17: bool,
    x18: bool,
    x19: bool,
    x20: bool,
    x21: bool,
    x22: bool,
    x23: bool,
    x24: bool,
    x25: bool,
    x26: bool,
    x27: bool,
    x28: bool,
    x29: bool,
    x30: bool,
    x31: bool
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: bool) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> bool[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> bool[src]

Extracts the value at index.

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

impl m16x32[src]

pub fn and(self) -> bool[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> bool[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> bool[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl m16x32[src]

pub fn all(self) -> bool[src]

Are all vector lanes true?

+

pub fn any(self) -> bool[src]

Is any vector lane true?

+

pub fn none(self) -> bool[src]

Are all vector lanes false?

+

impl m16x32[src]

pub fn eq(self, other: Self) -> m16x32[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m16x32[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m16x32[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m16x32[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m16x32[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m16x32[src]

Lane-wise greater-than-or-equals comparison.

+

impl m16x32[src]

pub fn select<T>(self, a: Simd<T>, b: Simd<T>) -> Simd<T> where
    T: SimdArray<NT = <[m16; 32] as SimdArray>::NT>, [src]

Selects elements of a and b using mask.

+

The lanes of the result for which the mask is true contain +the values of a. The remaining lanes contain the values of +b.

+

impl m16x32[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<m16x32>[src]

Returns a wrapper that implements PartialOrd.

+

impl m16x32[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<m16x32>[src]

Returns a wrapper that implements Ord.

+

impl m16x32[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl m16x32[src]

pub fn bitmask(self) -> u32[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl BitAnd<Simd<[m16; 32]>> for m16x32[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<bool> for m16x32[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[m16; 32]>> for m16x32[src]

impl BitAndAssign<bool> for m16x32[src]

impl BitOr<Simd<[m16; 32]>> for m16x32[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<bool> for m16x32[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[m16; 32]>> for m16x32[src]

impl BitOrAssign<bool> for m16x32[src]

impl BitXor<Simd<[m16; 32]>> for m16x32[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<bool> for m16x32[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[m16; 32]>> for m16x32[src]

impl BitXorAssign<bool> for m16x32[src]

impl Debug for m16x32[src]

impl Default for m16x32[src]

impl Eq for m16x32[src]

impl From<[m16; 32]> for m16x32[src]

impl From<Simd<[m8; 32]>> for m16x32[src]

impl FromBits<Simd<[m128; 4]>> for m16x32[src]

impl FromBits<Simd<[m32; 16]>> for m16x32[src]

impl FromBits<Simd<[m64; 8]>> for m16x32[src]

impl FromCast<Simd<[i16; 32]>> for m16x32[src]

impl FromCast<Simd<[i8; 32]>> for m16x32[src]

impl FromCast<Simd<[m8; 32]>> for m16x32[src]

impl FromCast<Simd<[u16; 32]>> for m16x32[src]

impl FromCast<Simd<[u8; 32]>> for m16x32[src]

impl Not for m16x32[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl PartialEq<Simd<[m16; 32]>> for m16x32[src]

impl Simd for m16x32[src]

type Element = m16

Element type of the SIMD vector

+

type LanesType = [u32; 32]

The type: [u32; Self::N].

+
\ No newline at end of file diff --git a/packed_simd/type.m16x4.html b/packed_simd/type.m16x4.html new file mode 100644 index 000000000..c907dcc54 --- /dev/null +++ b/packed_simd/type.m16x4.html @@ -0,0 +1,105 @@ +packed_simd::m16x4 - Rust

[−][src]Type Definition packed_simd::m16x4

type m16x4 = Simd<[m16; 4]>;

A 64-bit vector mask with 4 m16 lanes.

+

Implementations

impl m16x4[src]

pub const fn new(x0: bool, x1: bool, x2: bool, x3: bool) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: bool) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> bool[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> bool[src]

Extracts the value at index.

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

impl m16x4[src]

pub fn and(self) -> bool[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> bool[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> bool[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl m16x4[src]

pub fn all(self) -> bool[src]

Are all vector lanes true?

+

pub fn any(self) -> bool[src]

Is any vector lane true?

+

pub fn none(self) -> bool[src]

Are all vector lanes false?

+

impl m16x4[src]

pub fn eq(self, other: Self) -> m16x4[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m16x4[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m16x4[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m16x4[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m16x4[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m16x4[src]

Lane-wise greater-than-or-equals comparison.

+

impl m16x4[src]

pub fn select<T>(self, a: Simd<T>, b: Simd<T>) -> Simd<T> where
    T: SimdArray<NT = <[m16; 4] as SimdArray>::NT>, [src]

Selects elements of a and b using mask.

+

The lanes of the result for which the mask is true contain +the values of a. The remaining lanes contain the values of +b.

+

impl m16x4[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<m16x4>[src]

Returns a wrapper that implements PartialOrd.

+

impl m16x4[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<m16x4>[src]

Returns a wrapper that implements Ord.

+

impl m16x4[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl m16x4[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl BitAnd<Simd<[m16; 4]>> for m16x4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<bool> for m16x4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[m16; 4]>> for m16x4[src]

impl BitAndAssign<bool> for m16x4[src]

impl BitOr<Simd<[m16; 4]>> for m16x4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<bool> for m16x4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[m16; 4]>> for m16x4[src]

impl BitOrAssign<bool> for m16x4[src]

impl BitXor<Simd<[m16; 4]>> for m16x4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<bool> for m16x4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[m16; 4]>> for m16x4[src]

impl BitXorAssign<bool> for m16x4[src]

impl Debug for m16x4[src]

impl Default for m16x4[src]

impl Eq for m16x4[src]

impl From<[m16; 4]> for m16x4[src]

impl From<Simd<[m32; 4]>> for m16x4[src]

impl From<Simd<[m64; 4]>> for m16x4[src]

impl From<Simd<[m8; 4]>> for m16x4[src]

impl FromBits<Simd<[m32; 2]>> for m16x4[src]

impl FromCast<Simd<[f32; 4]>> for m16x4[src]

impl FromCast<Simd<[f64; 4]>> for m16x4[src]

impl FromCast<Simd<[i128; 4]>> for m16x4[src]

impl FromCast<Simd<[i16; 4]>> for m16x4[src]

impl FromCast<Simd<[i32; 4]>> for m16x4[src]

impl FromCast<Simd<[i64; 4]>> for m16x4[src]

impl FromCast<Simd<[i8; 4]>> for m16x4[src]

impl FromCast<Simd<[isize; 4]>> for m16x4[src]

impl FromCast<Simd<[m128; 4]>> for m16x4[src]

impl FromCast<Simd<[m32; 4]>> for m16x4[src]

impl FromCast<Simd<[m64; 4]>> for m16x4[src]

impl FromCast<Simd<[m8; 4]>> for m16x4[src]

impl FromCast<Simd<[msize; 4]>> for m16x4[src]

impl FromCast<Simd<[u128; 4]>> for m16x4[src]

impl FromCast<Simd<[u16; 4]>> for m16x4[src]

impl FromCast<Simd<[u32; 4]>> for m16x4[src]

impl FromCast<Simd<[u64; 4]>> for m16x4[src]

impl FromCast<Simd<[u8; 4]>> for m16x4[src]

impl FromCast<Simd<[usize; 4]>> for m16x4[src]

impl Not for m16x4[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl PartialEq<Simd<[m16; 4]>> for m16x4[src]

impl Simd for m16x4[src]

type Element = m16

Element type of the SIMD vector

+

type LanesType = [u32; 4]

The type: [u32; Self::N].

+
\ No newline at end of file diff --git a/packed_simd/type.m16x8.html b/packed_simd/type.m16x8.html new file mode 100644 index 000000000..8972628b1 --- /dev/null +++ b/packed_simd/type.m16x8.html @@ -0,0 +1,103 @@ +packed_simd::m16x8 - Rust

[−][src]Type Definition packed_simd::m16x8

type m16x8 = Simd<[m16; 8]>;

A 128-bit vector mask with 8 m16 lanes.

+

Implementations

impl m16x8[src]

pub const fn new(
    x0: bool,
    x1: bool,
    x2: bool,
    x3: bool,
    x4: bool,
    x5: bool,
    x6: bool,
    x7: bool
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: bool) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> bool[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> bool[src]

Extracts the value at index.

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

impl m16x8[src]

pub fn and(self) -> bool[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> bool[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> bool[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl m16x8[src]

pub fn all(self) -> bool[src]

Are all vector lanes true?

+

pub fn any(self) -> bool[src]

Is any vector lane true?

+

pub fn none(self) -> bool[src]

Are all vector lanes false?

+

impl m16x8[src]

pub fn eq(self, other: Self) -> m16x8[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m16x8[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m16x8[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m16x8[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m16x8[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m16x8[src]

Lane-wise greater-than-or-equals comparison.

+

impl m16x8[src]

pub fn select<T>(self, a: Simd<T>, b: Simd<T>) -> Simd<T> where
    T: SimdArray<NT = <[m16; 8] as SimdArray>::NT>, [src]

Selects elements of a and b using mask.

+

The lanes of the result for which the mask is true contain +the values of a. The remaining lanes contain the values of +b.

+

impl m16x8[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<m16x8>[src]

Returns a wrapper that implements PartialOrd.

+

impl m16x8[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<m16x8>[src]

Returns a wrapper that implements Ord.

+

impl m16x8[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl m16x8[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl BitAnd<Simd<[m16; 8]>> for m16x8[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<bool> for m16x8[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[m16; 8]>> for m16x8[src]

impl BitAndAssign<bool> for m16x8[src]

impl BitOr<Simd<[m16; 8]>> for m16x8[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<bool> for m16x8[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[m16; 8]>> for m16x8[src]

impl BitOrAssign<bool> for m16x8[src]

impl BitXor<Simd<[m16; 8]>> for m16x8[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<bool> for m16x8[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[m16; 8]>> for m16x8[src]

impl BitXorAssign<bool> for m16x8[src]

impl Debug for m16x8[src]

impl Default for m16x8[src]

impl Eq for m16x8[src]

impl From<[m16; 8]> for m16x8[src]

impl From<Simd<[m32; 8]>> for m16x8[src]

impl From<Simd<[m8; 8]>> for m16x8[src]

impl FromBits<Simd<[m128; 1]>> for m16x8[src]

impl FromBits<Simd<[m32; 4]>> for m16x8[src]

impl FromBits<Simd<[m64; 2]>> for m16x8[src]

impl FromCast<Simd<[f32; 8]>> for m16x8[src]

impl FromCast<Simd<[f64; 8]>> for m16x8[src]

impl FromCast<Simd<[i16; 8]>> for m16x8[src]

impl FromCast<Simd<[i32; 8]>> for m16x8[src]

impl FromCast<Simd<[i64; 8]>> for m16x8[src]

impl FromCast<Simd<[i8; 8]>> for m16x8[src]

impl FromCast<Simd<[isize; 8]>> for m16x8[src]

impl FromCast<Simd<[m32; 8]>> for m16x8[src]

impl FromCast<Simd<[m64; 8]>> for m16x8[src]

impl FromCast<Simd<[m8; 8]>> for m16x8[src]

impl FromCast<Simd<[msize; 8]>> for m16x8[src]

impl FromCast<Simd<[u16; 8]>> for m16x8[src]

impl FromCast<Simd<[u32; 8]>> for m16x8[src]

impl FromCast<Simd<[u64; 8]>> for m16x8[src]

impl FromCast<Simd<[u8; 8]>> for m16x8[src]

impl FromCast<Simd<[usize; 8]>> for m16x8[src]

impl Not for m16x8[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl PartialEq<Simd<[m16; 8]>> for m16x8[src]

impl Simd for m16x8[src]

type Element = m16

Element type of the SIMD vector

+

type LanesType = [u32; 8]

The type: [u32; Self::N].

+
\ No newline at end of file diff --git a/packed_simd/type.m32x16.html b/packed_simd/type.m32x16.html new file mode 100644 index 000000000..8284e171b --- /dev/null +++ b/packed_simd/type.m32x16.html @@ -0,0 +1,95 @@ +packed_simd::m32x16 - Rust

[−][src]Type Definition packed_simd::m32x16

type m32x16 = Simd<[m32; 16]>;

A 512-bit vector mask with 16 m32 lanes.

+

Implementations

impl m32x16[src]

pub const fn new(
    x0: bool,
    x1: bool,
    x2: bool,
    x3: bool,
    x4: bool,
    x5: bool,
    x6: bool,
    x7: bool,
    x8: bool,
    x9: bool,
    x10: bool,
    x11: bool,
    x12: bool,
    x13: bool,
    x14: bool,
    x15: bool
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: bool) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> bool[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> bool[src]

Extracts the value at index.

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

impl m32x16[src]

pub fn and(self) -> bool[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> bool[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> bool[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl m32x16[src]

pub fn all(self) -> bool[src]

Are all vector lanes true?

+

pub fn any(self) -> bool[src]

Is any vector lane true?

+

pub fn none(self) -> bool[src]

Are all vector lanes false?

+

impl m32x16[src]

pub fn eq(self, other: Self) -> m32x16[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m32x16[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m32x16[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m32x16[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m32x16[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m32x16[src]

Lane-wise greater-than-or-equals comparison.

+

impl m32x16[src]

pub fn select<T>(self, a: Simd<T>, b: Simd<T>) -> Simd<T> where
    T: SimdArray<NT = <[m32; 16] as SimdArray>::NT>, [src]

Selects elements of a and b using mask.

+

The lanes of the result for which the mask is true contain +the values of a. The remaining lanes contain the values of +b.

+

impl m32x16[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<m32x16>[src]

Returns a wrapper that implements PartialOrd.

+

impl m32x16[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<m32x16>[src]

Returns a wrapper that implements Ord.

+

impl m32x16[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl m32x16[src]

pub fn bitmask(self) -> u16[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl BitAnd<Simd<[m32; 16]>> for m32x16[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<bool> for m32x16[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[m32; 16]>> for m32x16[src]

impl BitAndAssign<bool> for m32x16[src]

impl BitOr<Simd<[m32; 16]>> for m32x16[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<bool> for m32x16[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[m32; 16]>> for m32x16[src]

impl BitOrAssign<bool> for m32x16[src]

impl BitXor<Simd<[m32; 16]>> for m32x16[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<bool> for m32x16[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[m32; 16]>> for m32x16[src]

impl BitXorAssign<bool> for m32x16[src]

impl Debug for m32x16[src]

impl Default for m32x16[src]

impl Eq for m32x16[src]

impl From<[m32; 16]> for m32x16[src]

impl From<Simd<[m16; 16]>> for m32x16[src]

impl From<Simd<[m8; 16]>> for m32x16[src]

impl FromBits<Simd<[m128; 4]>> for m32x16[src]

impl FromBits<Simd<[m64; 8]>> for m32x16[src]

impl FromCast<Simd<[f32; 16]>> for m32x16[src]

impl FromCast<Simd<[i16; 16]>> for m32x16[src]

impl FromCast<Simd<[i32; 16]>> for m32x16[src]

impl FromCast<Simd<[i8; 16]>> for m32x16[src]

impl FromCast<Simd<[m16; 16]>> for m32x16[src]

impl FromCast<Simd<[m8; 16]>> for m32x16[src]

impl FromCast<Simd<[u16; 16]>> for m32x16[src]

impl FromCast<Simd<[u32; 16]>> for m32x16[src]

impl FromCast<Simd<[u8; 16]>> for m32x16[src]

impl Not for m32x16[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl PartialEq<Simd<[m32; 16]>> for m32x16[src]

impl Simd for m32x16[src]

type Element = m32

Element type of the SIMD vector

+

type LanesType = [u32; 16]

The type: [u32; Self::N].

+
\ No newline at end of file diff --git a/packed_simd/type.m32x2.html b/packed_simd/type.m32x2.html new file mode 100644 index 000000000..026f6abf7 --- /dev/null +++ b/packed_simd/type.m32x2.html @@ -0,0 +1,105 @@ +packed_simd::m32x2 - Rust

[−][src]Type Definition packed_simd::m32x2

type m32x2 = Simd<[m32; 2]>;

A 64-bit vector mask with 2 m32 lanes.

+

Implementations

impl m32x2[src]

pub const fn new(x0: bool, x1: bool) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: bool) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> bool[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> bool[src]

Extracts the value at index.

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

impl m32x2[src]

pub fn and(self) -> bool[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> bool[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> bool[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl m32x2[src]

pub fn all(self) -> bool[src]

Are all vector lanes true?

+

pub fn any(self) -> bool[src]

Is any vector lane true?

+

pub fn none(self) -> bool[src]

Are all vector lanes false?

+

impl m32x2[src]

pub fn eq(self, other: Self) -> m32x2[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m32x2[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m32x2[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m32x2[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m32x2[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m32x2[src]

Lane-wise greater-than-or-equals comparison.

+

impl m32x2[src]

pub fn select<T>(self, a: Simd<T>, b: Simd<T>) -> Simd<T> where
    T: SimdArray<NT = <[m32; 2] as SimdArray>::NT>, [src]

Selects elements of a and b using mask.

+

The lanes of the result for which the mask is true contain +the values of a. The remaining lanes contain the values of +b.

+

impl m32x2[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<m32x2>[src]

Returns a wrapper that implements PartialOrd.

+

impl m32x2[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<m32x2>[src]

Returns a wrapper that implements Ord.

+

impl m32x2[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl m32x2[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl BitAnd<Simd<[m32; 2]>> for m32x2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<bool> for m32x2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[m32; 2]>> for m32x2[src]

impl BitAndAssign<bool> for m32x2[src]

impl BitOr<Simd<[m32; 2]>> for m32x2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<bool> for m32x2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[m32; 2]>> for m32x2[src]

impl BitOrAssign<bool> for m32x2[src]

impl BitXor<Simd<[m32; 2]>> for m32x2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<bool> for m32x2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[m32; 2]>> for m32x2[src]

impl BitXorAssign<bool> for m32x2[src]

impl Debug for m32x2[src]

impl Default for m32x2[src]

impl Eq for m32x2[src]

impl From<[m32; 2]> for m32x2[src]

impl From<Simd<[m128; 2]>> for m32x2[src]

impl From<Simd<[m16; 2]>> for m32x2[src]

impl From<Simd<[m64; 2]>> for m32x2[src]

impl From<Simd<[m8; 2]>> for m32x2[src]

impl FromCast<Simd<[f32; 2]>> for m32x2[src]

impl FromCast<Simd<[f64; 2]>> for m32x2[src]

impl FromCast<Simd<[i128; 2]>> for m32x2[src]

impl FromCast<Simd<[i16; 2]>> for m32x2[src]

impl FromCast<Simd<[i32; 2]>> for m32x2[src]

impl FromCast<Simd<[i64; 2]>> for m32x2[src]

impl FromCast<Simd<[i8; 2]>> for m32x2[src]

impl FromCast<Simd<[isize; 2]>> for m32x2[src]

impl FromCast<Simd<[m128; 2]>> for m32x2[src]

impl FromCast<Simd<[m16; 2]>> for m32x2[src]

impl FromCast<Simd<[m64; 2]>> for m32x2[src]

impl FromCast<Simd<[m8; 2]>> for m32x2[src]

impl FromCast<Simd<[msize; 2]>> for m32x2[src]

impl FromCast<Simd<[u128; 2]>> for m32x2[src]

impl FromCast<Simd<[u16; 2]>> for m32x2[src]

impl FromCast<Simd<[u32; 2]>> for m32x2[src]

impl FromCast<Simd<[u64; 2]>> for m32x2[src]

impl FromCast<Simd<[u8; 2]>> for m32x2[src]

impl FromCast<Simd<[usize; 2]>> for m32x2[src]

impl Not for m32x2[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl PartialEq<Simd<[m32; 2]>> for m32x2[src]

impl Simd for m32x2[src]

type Element = m32

Element type of the SIMD vector

+

type LanesType = [u32; 2]

The type: [u32; Self::N].

+
\ No newline at end of file diff --git a/packed_simd/type.m32x4.html b/packed_simd/type.m32x4.html new file mode 100644 index 000000000..fe1e8ec81 --- /dev/null +++ b/packed_simd/type.m32x4.html @@ -0,0 +1,106 @@ +packed_simd::m32x4 - Rust

[−][src]Type Definition packed_simd::m32x4

type m32x4 = Simd<[m32; 4]>;

A 128-bit vector mask with 4 m32 lanes.

+

Implementations

impl m32x4[src]

pub const fn new(x0: bool, x1: bool, x2: bool, x3: bool) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: bool) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> bool[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> bool[src]

Extracts the value at index.

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

impl m32x4[src]

pub fn and(self) -> bool[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> bool[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> bool[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl m32x4[src]

pub fn all(self) -> bool[src]

Are all vector lanes true?

+

pub fn any(self) -> bool[src]

Is any vector lane true?

+

pub fn none(self) -> bool[src]

Are all vector lanes false?

+

impl m32x4[src]

pub fn eq(self, other: Self) -> m32x4[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m32x4[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m32x4[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m32x4[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m32x4[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m32x4[src]

Lane-wise greater-than-or-equals comparison.

+

impl m32x4[src]

pub fn select<T>(self, a: Simd<T>, b: Simd<T>) -> Simd<T> where
    T: SimdArray<NT = <[m32; 4] as SimdArray>::NT>, [src]

Selects elements of a and b using mask.

+

The lanes of the result for which the mask is true contain +the values of a. The remaining lanes contain the values of +b.

+

impl m32x4[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<m32x4>[src]

Returns a wrapper that implements PartialOrd.

+

impl m32x4[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<m32x4>[src]

Returns a wrapper that implements Ord.

+

impl m32x4[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl m32x4[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl BitAnd<Simd<[m32; 4]>> for m32x4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<bool> for m32x4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[m32; 4]>> for m32x4[src]

impl BitAndAssign<bool> for m32x4[src]

impl BitOr<Simd<[m32; 4]>> for m32x4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<bool> for m32x4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[m32; 4]>> for m32x4[src]

impl BitOrAssign<bool> for m32x4[src]

impl BitXor<Simd<[m32; 4]>> for m32x4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<bool> for m32x4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[m32; 4]>> for m32x4[src]

impl BitXorAssign<bool> for m32x4[src]

impl Debug for m32x4[src]

impl Default for m32x4[src]

impl Eq for m32x4[src]

impl From<[m32; 4]> for m32x4[src]

impl From<Simd<[m16; 4]>> for m32x4[src]

impl From<Simd<[m64; 4]>> for m32x4[src]

impl From<Simd<[m8; 4]>> for m32x4[src]

impl FromBits<Simd<[m128; 1]>> for m32x4[src]

impl FromBits<Simd<[m64; 2]>> for m32x4[src]

impl FromCast<Simd<[f32; 4]>> for m32x4[src]

impl FromCast<Simd<[f64; 4]>> for m32x4[src]

impl FromCast<Simd<[i128; 4]>> for m32x4[src]

impl FromCast<Simd<[i16; 4]>> for m32x4[src]

impl FromCast<Simd<[i32; 4]>> for m32x4[src]

impl FromCast<Simd<[i64; 4]>> for m32x4[src]

impl FromCast<Simd<[i8; 4]>> for m32x4[src]

impl FromCast<Simd<[isize; 4]>> for m32x4[src]

impl FromCast<Simd<[m128; 4]>> for m32x4[src]

impl FromCast<Simd<[m16; 4]>> for m32x4[src]

impl FromCast<Simd<[m64; 4]>> for m32x4[src]

impl FromCast<Simd<[m8; 4]>> for m32x4[src]

impl FromCast<Simd<[msize; 4]>> for m32x4[src]

impl FromCast<Simd<[u128; 4]>> for m32x4[src]

impl FromCast<Simd<[u16; 4]>> for m32x4[src]

impl FromCast<Simd<[u32; 4]>> for m32x4[src]

impl FromCast<Simd<[u64; 4]>> for m32x4[src]

impl FromCast<Simd<[u8; 4]>> for m32x4[src]

impl FromCast<Simd<[usize; 4]>> for m32x4[src]

impl Not for m32x4[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl PartialEq<Simd<[m32; 4]>> for m32x4[src]

impl Simd for m32x4[src]

type Element = m32

Element type of the SIMD vector

+

type LanesType = [u32; 4]

The type: [u32; Self::N].

+
\ No newline at end of file diff --git a/packed_simd/type.m32x8.html b/packed_simd/type.m32x8.html new file mode 100644 index 000000000..0792cc1b0 --- /dev/null +++ b/packed_simd/type.m32x8.html @@ -0,0 +1,102 @@ +packed_simd::m32x8 - Rust

[−][src]Type Definition packed_simd::m32x8

type m32x8 = Simd<[m32; 8]>;

A 256-bit vector mask with 8 m32 lanes.

+

Implementations

impl m32x8[src]

pub const fn new(
    x0: bool,
    x1: bool,
    x2: bool,
    x3: bool,
    x4: bool,
    x5: bool,
    x6: bool,
    x7: bool
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: bool) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> bool[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> bool[src]

Extracts the value at index.

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

impl m32x8[src]

pub fn and(self) -> bool[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> bool[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> bool[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl m32x8[src]

pub fn all(self) -> bool[src]

Are all vector lanes true?

+

pub fn any(self) -> bool[src]

Is any vector lane true?

+

pub fn none(self) -> bool[src]

Are all vector lanes false?

+

impl m32x8[src]

pub fn eq(self, other: Self) -> m32x8[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m32x8[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m32x8[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m32x8[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m32x8[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m32x8[src]

Lane-wise greater-than-or-equals comparison.

+

impl m32x8[src]

pub fn select<T>(self, a: Simd<T>, b: Simd<T>) -> Simd<T> where
    T: SimdArray<NT = <[m32; 8] as SimdArray>::NT>, [src]

Selects elements of a and b using mask.

+

The lanes of the result for which the mask is true contain +the values of a. The remaining lanes contain the values of +b.

+

impl m32x8[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<m32x8>[src]

Returns a wrapper that implements PartialOrd.

+

impl m32x8[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<m32x8>[src]

Returns a wrapper that implements Ord.

+

impl m32x8[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl m32x8[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl BitAnd<Simd<[m32; 8]>> for m32x8[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<bool> for m32x8[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[m32; 8]>> for m32x8[src]

impl BitAndAssign<bool> for m32x8[src]

impl BitOr<Simd<[m32; 8]>> for m32x8[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<bool> for m32x8[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[m32; 8]>> for m32x8[src]

impl BitOrAssign<bool> for m32x8[src]

impl BitXor<Simd<[m32; 8]>> for m32x8[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<bool> for m32x8[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[m32; 8]>> for m32x8[src]

impl BitXorAssign<bool> for m32x8[src]

impl Debug for m32x8[src]

impl Default for m32x8[src]

impl Eq for m32x8[src]

impl From<[m32; 8]> for m32x8[src]

impl From<Simd<[m16; 8]>> for m32x8[src]

impl From<Simd<[m8; 8]>> for m32x8[src]

impl FromBits<Simd<[m128; 2]>> for m32x8[src]

impl FromBits<Simd<[m64; 4]>> for m32x8[src]

impl FromCast<Simd<[f32; 8]>> for m32x8[src]

impl FromCast<Simd<[f64; 8]>> for m32x8[src]

impl FromCast<Simd<[i16; 8]>> for m32x8[src]

impl FromCast<Simd<[i32; 8]>> for m32x8[src]

impl FromCast<Simd<[i64; 8]>> for m32x8[src]

impl FromCast<Simd<[i8; 8]>> for m32x8[src]

impl FromCast<Simd<[isize; 8]>> for m32x8[src]

impl FromCast<Simd<[m16; 8]>> for m32x8[src]

impl FromCast<Simd<[m64; 8]>> for m32x8[src]

impl FromCast<Simd<[m8; 8]>> for m32x8[src]

impl FromCast<Simd<[msize; 8]>> for m32x8[src]

impl FromCast<Simd<[u16; 8]>> for m32x8[src]

impl FromCast<Simd<[u32; 8]>> for m32x8[src]

impl FromCast<Simd<[u64; 8]>> for m32x8[src]

impl FromCast<Simd<[u8; 8]>> for m32x8[src]

impl FromCast<Simd<[usize; 8]>> for m32x8[src]

impl Not for m32x8[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl PartialEq<Simd<[m32; 8]>> for m32x8[src]

impl Simd for m32x8[src]

type Element = m32

Element type of the SIMD vector

+

type LanesType = [u32; 8]

The type: [u32; Self::N].

+
\ No newline at end of file diff --git a/packed_simd/type.m64x2.html b/packed_simd/type.m64x2.html new file mode 100644 index 000000000..130f8b321 --- /dev/null +++ b/packed_simd/type.m64x2.html @@ -0,0 +1,106 @@ +packed_simd::m64x2 - Rust

[−][src]Type Definition packed_simd::m64x2

type m64x2 = Simd<[m64; 2]>;

A 128-bit vector mask with 2 m64 lanes.

+

Implementations

impl m64x2[src]

pub const fn new(x0: bool, x1: bool) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: bool) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> bool[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> bool[src]

Extracts the value at index.

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

impl m64x2[src]

pub fn and(self) -> bool[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> bool[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> bool[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl m64x2[src]

pub fn all(self) -> bool[src]

Are all vector lanes true?

+

pub fn any(self) -> bool[src]

Is any vector lane true?

+

pub fn none(self) -> bool[src]

Are all vector lanes false?

+

impl m64x2[src]

pub fn eq(self, other: Self) -> m64x2[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m64x2[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m64x2[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m64x2[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m64x2[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m64x2[src]

Lane-wise greater-than-or-equals comparison.

+

impl m64x2[src]

pub fn select<T>(self, a: Simd<T>, b: Simd<T>) -> Simd<T> where
    T: SimdArray<NT = <[m64; 2] as SimdArray>::NT>, [src]

Selects elements of a and b using mask.

+

The lanes of the result for which the mask is true contain +the values of a. The remaining lanes contain the values of +b.

+

impl m64x2[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<m64x2>[src]

Returns a wrapper that implements PartialOrd.

+

impl m64x2[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<m64x2>[src]

Returns a wrapper that implements Ord.

+

impl m64x2[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl m64x2[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl BitAnd<Simd<[m64; 2]>> for m64x2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<bool> for m64x2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[m64; 2]>> for m64x2[src]

impl BitAndAssign<bool> for m64x2[src]

impl BitOr<Simd<[m64; 2]>> for m64x2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<bool> for m64x2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[m64; 2]>> for m64x2[src]

impl BitOrAssign<bool> for m64x2[src]

impl BitXor<Simd<[m64; 2]>> for m64x2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<bool> for m64x2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[m64; 2]>> for m64x2[src]

impl BitXorAssign<bool> for m64x2[src]

impl Debug for m64x2[src]

impl Default for m64x2[src]

impl Eq for m64x2[src]

impl From<[m64; 2]> for m64x2[src]

impl From<Simd<[m128; 2]>> for m64x2[src]

impl From<Simd<[m16; 2]>> for m64x2[src]

impl From<Simd<[m32; 2]>> for m64x2[src]

impl From<Simd<[m8; 2]>> for m64x2[src]

impl FromBits<Simd<[m128; 1]>> for m64x2[src]

impl FromCast<Simd<[f32; 2]>> for m64x2[src]

impl FromCast<Simd<[f64; 2]>> for m64x2[src]

impl FromCast<Simd<[i128; 2]>> for m64x2[src]

impl FromCast<Simd<[i16; 2]>> for m64x2[src]

impl FromCast<Simd<[i32; 2]>> for m64x2[src]

impl FromCast<Simd<[i64; 2]>> for m64x2[src]

impl FromCast<Simd<[i8; 2]>> for m64x2[src]

impl FromCast<Simd<[isize; 2]>> for m64x2[src]

impl FromCast<Simd<[m128; 2]>> for m64x2[src]

impl FromCast<Simd<[m16; 2]>> for m64x2[src]

impl FromCast<Simd<[m32; 2]>> for m64x2[src]

impl FromCast<Simd<[m8; 2]>> for m64x2[src]

impl FromCast<Simd<[msize; 2]>> for m64x2[src]

impl FromCast<Simd<[u128; 2]>> for m64x2[src]

impl FromCast<Simd<[u16; 2]>> for m64x2[src]

impl FromCast<Simd<[u32; 2]>> for m64x2[src]

impl FromCast<Simd<[u64; 2]>> for m64x2[src]

impl FromCast<Simd<[u8; 2]>> for m64x2[src]

impl FromCast<Simd<[usize; 2]>> for m64x2[src]

impl Not for m64x2[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl PartialEq<Simd<[m64; 2]>> for m64x2[src]

impl Simd for m64x2[src]

type Element = m64

Element type of the SIMD vector

+

type LanesType = [u32; 2]

The type: [u32; Self::N].

+
\ No newline at end of file diff --git a/packed_simd/type.m64x4.html b/packed_simd/type.m64x4.html new file mode 100644 index 000000000..85868b759 --- /dev/null +++ b/packed_simd/type.m64x4.html @@ -0,0 +1,105 @@ +packed_simd::m64x4 - Rust

[−][src]Type Definition packed_simd::m64x4

type m64x4 = Simd<[m64; 4]>;

A 256-bit vector mask with 4 m64 lanes.

+

Implementations

impl m64x4[src]

pub const fn new(x0: bool, x1: bool, x2: bool, x3: bool) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: bool) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> bool[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> bool[src]

Extracts the value at index.

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

impl m64x4[src]

pub fn and(self) -> bool[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> bool[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> bool[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl m64x4[src]

pub fn all(self) -> bool[src]

Are all vector lanes true?

+

pub fn any(self) -> bool[src]

Is any vector lane true?

+

pub fn none(self) -> bool[src]

Are all vector lanes false?

+

impl m64x4[src]

pub fn eq(self, other: Self) -> m64x4[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m64x4[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m64x4[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m64x4[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m64x4[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m64x4[src]

Lane-wise greater-than-or-equals comparison.

+

impl m64x4[src]

pub fn select<T>(self, a: Simd<T>, b: Simd<T>) -> Simd<T> where
    T: SimdArray<NT = <[m64; 4] as SimdArray>::NT>, [src]

Selects elements of a and b using mask.

+

The lanes of the result for which the mask is true contain +the values of a. The remaining lanes contain the values of +b.

+

impl m64x4[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<m64x4>[src]

Returns a wrapper that implements PartialOrd.

+

impl m64x4[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<m64x4>[src]

Returns a wrapper that implements Ord.

+

impl m64x4[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl m64x4[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl BitAnd<Simd<[m64; 4]>> for m64x4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<bool> for m64x4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[m64; 4]>> for m64x4[src]

impl BitAndAssign<bool> for m64x4[src]

impl BitOr<Simd<[m64; 4]>> for m64x4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<bool> for m64x4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[m64; 4]>> for m64x4[src]

impl BitOrAssign<bool> for m64x4[src]

impl BitXor<Simd<[m64; 4]>> for m64x4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<bool> for m64x4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[m64; 4]>> for m64x4[src]

impl BitXorAssign<bool> for m64x4[src]

impl Debug for m64x4[src]

impl Default for m64x4[src]

impl Eq for m64x4[src]

impl From<[m64; 4]> for m64x4[src]

impl From<Simd<[m16; 4]>> for m64x4[src]

impl From<Simd<[m32; 4]>> for m64x4[src]

impl From<Simd<[m8; 4]>> for m64x4[src]

impl FromBits<Simd<[m128; 2]>> for m64x4[src]

impl FromCast<Simd<[f32; 4]>> for m64x4[src]

impl FromCast<Simd<[f64; 4]>> for m64x4[src]

impl FromCast<Simd<[i128; 4]>> for m64x4[src]

impl FromCast<Simd<[i16; 4]>> for m64x4[src]

impl FromCast<Simd<[i32; 4]>> for m64x4[src]

impl FromCast<Simd<[i64; 4]>> for m64x4[src]

impl FromCast<Simd<[i8; 4]>> for m64x4[src]

impl FromCast<Simd<[isize; 4]>> for m64x4[src]

impl FromCast<Simd<[m128; 4]>> for m64x4[src]

impl FromCast<Simd<[m16; 4]>> for m64x4[src]

impl FromCast<Simd<[m32; 4]>> for m64x4[src]

impl FromCast<Simd<[m8; 4]>> for m64x4[src]

impl FromCast<Simd<[msize; 4]>> for m64x4[src]

impl FromCast<Simd<[u128; 4]>> for m64x4[src]

impl FromCast<Simd<[u16; 4]>> for m64x4[src]

impl FromCast<Simd<[u32; 4]>> for m64x4[src]

impl FromCast<Simd<[u64; 4]>> for m64x4[src]

impl FromCast<Simd<[u8; 4]>> for m64x4[src]

impl FromCast<Simd<[usize; 4]>> for m64x4[src]

impl Not for m64x4[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl PartialEq<Simd<[m64; 4]>> for m64x4[src]

impl Simd for m64x4[src]

type Element = m64

Element type of the SIMD vector

+

type LanesType = [u32; 4]

The type: [u32; Self::N].

+
\ No newline at end of file diff --git a/packed_simd/type.m64x8.html b/packed_simd/type.m64x8.html new file mode 100644 index 000000000..400e7d6e2 --- /dev/null +++ b/packed_simd/type.m64x8.html @@ -0,0 +1,102 @@ +packed_simd::m64x8 - Rust

[−][src]Type Definition packed_simd::m64x8

type m64x8 = Simd<[m64; 8]>;

A 512-bit vector mask with 8 m64 lanes.

+

Implementations

impl m64x8[src]

pub const fn new(
    x0: bool,
    x1: bool,
    x2: bool,
    x3: bool,
    x4: bool,
    x5: bool,
    x6: bool,
    x7: bool
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: bool) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> bool[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> bool[src]

Extracts the value at index.

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

impl m64x8[src]

pub fn and(self) -> bool[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> bool[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> bool[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl m64x8[src]

pub fn all(self) -> bool[src]

Are all vector lanes true?

+

pub fn any(self) -> bool[src]

Is any vector lane true?

+

pub fn none(self) -> bool[src]

Are all vector lanes false?

+

impl m64x8[src]

pub fn eq(self, other: Self) -> m64x8[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m64x8[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m64x8[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m64x8[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m64x8[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m64x8[src]

Lane-wise greater-than-or-equals comparison.

+

impl m64x8[src]

pub fn select<T>(self, a: Simd<T>, b: Simd<T>) -> Simd<T> where
    T: SimdArray<NT = <[m64; 8] as SimdArray>::NT>, [src]

Selects elements of a and b using mask.

+

The lanes of the result for which the mask is true contain +the values of a. The remaining lanes contain the values of +b.

+

impl m64x8[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<m64x8>[src]

Returns a wrapper that implements PartialOrd.

+

impl m64x8[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<m64x8>[src]

Returns a wrapper that implements Ord.

+

impl m64x8[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl m64x8[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl BitAnd<Simd<[m64; 8]>> for m64x8[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<bool> for m64x8[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[m64; 8]>> for m64x8[src]

impl BitAndAssign<bool> for m64x8[src]

impl BitOr<Simd<[m64; 8]>> for m64x8[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<bool> for m64x8[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[m64; 8]>> for m64x8[src]

impl BitOrAssign<bool> for m64x8[src]

impl BitXor<Simd<[m64; 8]>> for m64x8[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<bool> for m64x8[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[m64; 8]>> for m64x8[src]

impl BitXorAssign<bool> for m64x8[src]

impl Debug for m64x8[src]

impl Default for m64x8[src]

impl Eq for m64x8[src]

impl From<[m64; 8]> for m64x8[src]

impl From<Simd<[m16; 8]>> for m64x8[src]

impl From<Simd<[m32; 8]>> for m64x8[src]

impl From<Simd<[m8; 8]>> for m64x8[src]

impl FromBits<Simd<[m128; 4]>> for m64x8[src]

impl FromCast<Simd<[f32; 8]>> for m64x8[src]

impl FromCast<Simd<[f64; 8]>> for m64x8[src]

impl FromCast<Simd<[i16; 8]>> for m64x8[src]

impl FromCast<Simd<[i32; 8]>> for m64x8[src]

impl FromCast<Simd<[i64; 8]>> for m64x8[src]

impl FromCast<Simd<[i8; 8]>> for m64x8[src]

impl FromCast<Simd<[isize; 8]>> for m64x8[src]

impl FromCast<Simd<[m16; 8]>> for m64x8[src]

impl FromCast<Simd<[m32; 8]>> for m64x8[src]

impl FromCast<Simd<[m8; 8]>> for m64x8[src]

impl FromCast<Simd<[msize; 8]>> for m64x8[src]

impl FromCast<Simd<[u16; 8]>> for m64x8[src]

impl FromCast<Simd<[u32; 8]>> for m64x8[src]

impl FromCast<Simd<[u64; 8]>> for m64x8[src]

impl FromCast<Simd<[u8; 8]>> for m64x8[src]

impl FromCast<Simd<[usize; 8]>> for m64x8[src]

impl Not for m64x8[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl PartialEq<Simd<[m64; 8]>> for m64x8[src]

impl Simd for m64x8[src]

type Element = m64

Element type of the SIMD vector

+

type LanesType = [u32; 8]

The type: [u32; Self::N].

+
\ No newline at end of file diff --git a/packed_simd/type.m8x16.html b/packed_simd/type.m8x16.html new file mode 100644 index 000000000..616874e65 --- /dev/null +++ b/packed_simd/type.m8x16.html @@ -0,0 +1,96 @@ +packed_simd::m8x16 - Rust

[−][src]Type Definition packed_simd::m8x16

type m8x16 = Simd<[m8; 16]>;

A 128-bit vector mask with 16 m8 lanes.

+

Implementations

impl m8x16[src]

pub const fn new(
    x0: bool,
    x1: bool,
    x2: bool,
    x3: bool,
    x4: bool,
    x5: bool,
    x6: bool,
    x7: bool,
    x8: bool,
    x9: bool,
    x10: bool,
    x11: bool,
    x12: bool,
    x13: bool,
    x14: bool,
    x15: bool
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: bool) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> bool[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> bool[src]

Extracts the value at index.

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

impl m8x16[src]

pub fn and(self) -> bool[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> bool[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> bool[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl m8x16[src]

pub fn all(self) -> bool[src]

Are all vector lanes true?

+

pub fn any(self) -> bool[src]

Is any vector lane true?

+

pub fn none(self) -> bool[src]

Are all vector lanes false?

+

impl m8x16[src]

pub fn eq(self, other: Self) -> m8x16[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m8x16[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m8x16[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m8x16[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m8x16[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m8x16[src]

Lane-wise greater-than-or-equals comparison.

+

impl m8x16[src]

pub fn select<T>(self, a: Simd<T>, b: Simd<T>) -> Simd<T> where
    T: SimdArray<NT = <[m8; 16] as SimdArray>::NT>, [src]

Selects elements of a and b using mask.

+

The lanes of the result for which the mask is true contain +the values of a. The remaining lanes contain the values of +b.

+

impl m8x16[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<m8x16>[src]

Returns a wrapper that implements PartialOrd.

+

impl m8x16[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<m8x16>[src]

Returns a wrapper that implements Ord.

+

impl m8x16[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl m8x16[src]

pub fn bitmask(self) -> u16[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl BitAnd<Simd<[m8; 16]>> for m8x16[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<bool> for m8x16[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[m8; 16]>> for m8x16[src]

impl BitAndAssign<bool> for m8x16[src]

impl BitOr<Simd<[m8; 16]>> for m8x16[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<bool> for m8x16[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[m8; 16]>> for m8x16[src]

impl BitOrAssign<bool> for m8x16[src]

impl BitXor<Simd<[m8; 16]>> for m8x16[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<bool> for m8x16[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[m8; 16]>> for m8x16[src]

impl BitXorAssign<bool> for m8x16[src]

impl Debug for m8x16[src]

impl Default for m8x16[src]

impl Eq for m8x16[src]

impl From<[m8; 16]> for m8x16[src]

impl From<Simd<[m16; 16]>> for m8x16[src]

impl FromBits<Simd<[m128; 1]>> for m8x16[src]

impl FromBits<Simd<[m16; 8]>> for m8x16[src]

impl FromBits<Simd<[m32; 4]>> for m8x16[src]

impl FromBits<Simd<[m64; 2]>> for m8x16[src]

impl FromCast<Simd<[f32; 16]>> for m8x16[src]

impl FromCast<Simd<[i16; 16]>> for m8x16[src]

impl FromCast<Simd<[i32; 16]>> for m8x16[src]

impl FromCast<Simd<[i8; 16]>> for m8x16[src]

impl FromCast<Simd<[m16; 16]>> for m8x16[src]

impl FromCast<Simd<[m32; 16]>> for m8x16[src]

impl FromCast<Simd<[u16; 16]>> for m8x16[src]

impl FromCast<Simd<[u32; 16]>> for m8x16[src]

impl FromCast<Simd<[u8; 16]>> for m8x16[src]

impl Not for m8x16[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl PartialEq<Simd<[m8; 16]>> for m8x16[src]

impl Simd for m8x16[src]

type Element = m8

Element type of the SIMD vector

+

type LanesType = [u32; 16]

The type: [u32; Self::N].

+
\ No newline at end of file diff --git a/packed_simd/type.m8x2.html b/packed_simd/type.m8x2.html new file mode 100644 index 000000000..2423e8c79 --- /dev/null +++ b/packed_simd/type.m8x2.html @@ -0,0 +1,105 @@ +packed_simd::m8x2 - Rust

[−][src]Type Definition packed_simd::m8x2

type m8x2 = Simd<[m8; 2]>;

A 16-bit vector mask with 2 m8 lanes.

+

Implementations

impl m8x2[src]

pub const fn new(x0: bool, x1: bool) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: bool) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> bool[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> bool[src]

Extracts the value at index.

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

impl m8x2[src]

pub fn and(self) -> bool[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> bool[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> bool[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl m8x2[src]

pub fn all(self) -> bool[src]

Are all vector lanes true?

+

pub fn any(self) -> bool[src]

Is any vector lane true?

+

pub fn none(self) -> bool[src]

Are all vector lanes false?

+

impl m8x2[src]

pub fn eq(self, other: Self) -> m8x2[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m8x2[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m8x2[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m8x2[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m8x2[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m8x2[src]

Lane-wise greater-than-or-equals comparison.

+

impl m8x2[src]

pub fn select<T>(self, a: Simd<T>, b: Simd<T>) -> Simd<T> where
    T: SimdArray<NT = <[m8; 2] as SimdArray>::NT>, [src]

Selects elements of a and b using mask.

+

The lanes of the result for which the mask is true contain +the values of a. The remaining lanes contain the values of +b.

+

impl m8x2[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<m8x2>[src]

Returns a wrapper that implements PartialOrd.

+

impl m8x2[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<m8x2>[src]

Returns a wrapper that implements Ord.

+

impl m8x2[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl m8x2[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl BitAnd<Simd<[m8; 2]>> for m8x2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<bool> for m8x2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[m8; 2]>> for m8x2[src]

impl BitAndAssign<bool> for m8x2[src]

impl BitOr<Simd<[m8; 2]>> for m8x2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<bool> for m8x2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[m8; 2]>> for m8x2[src]

impl BitOrAssign<bool> for m8x2[src]

impl BitXor<Simd<[m8; 2]>> for m8x2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<bool> for m8x2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[m8; 2]>> for m8x2[src]

impl BitXorAssign<bool> for m8x2[src]

impl Debug for m8x2[src]

impl Default for m8x2[src]

impl Eq for m8x2[src]

impl From<[m8; 2]> for m8x2[src]

impl From<Simd<[m128; 2]>> for m8x2[src]

impl From<Simd<[m16; 2]>> for m8x2[src]

impl From<Simd<[m32; 2]>> for m8x2[src]

impl From<Simd<[m64; 2]>> for m8x2[src]

impl FromCast<Simd<[f32; 2]>> for m8x2[src]

impl FromCast<Simd<[f64; 2]>> for m8x2[src]

impl FromCast<Simd<[i128; 2]>> for m8x2[src]

impl FromCast<Simd<[i16; 2]>> for m8x2[src]

impl FromCast<Simd<[i32; 2]>> for m8x2[src]

impl FromCast<Simd<[i64; 2]>> for m8x2[src]

impl FromCast<Simd<[i8; 2]>> for m8x2[src]

impl FromCast<Simd<[isize; 2]>> for m8x2[src]

impl FromCast<Simd<[m128; 2]>> for m8x2[src]

impl FromCast<Simd<[m16; 2]>> for m8x2[src]

impl FromCast<Simd<[m32; 2]>> for m8x2[src]

impl FromCast<Simd<[m64; 2]>> for m8x2[src]

impl FromCast<Simd<[msize; 2]>> for m8x2[src]

impl FromCast<Simd<[u128; 2]>> for m8x2[src]

impl FromCast<Simd<[u16; 2]>> for m8x2[src]

impl FromCast<Simd<[u32; 2]>> for m8x2[src]

impl FromCast<Simd<[u64; 2]>> for m8x2[src]

impl FromCast<Simd<[u8; 2]>> for m8x2[src]

impl FromCast<Simd<[usize; 2]>> for m8x2[src]

impl Not for m8x2[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl PartialEq<Simd<[m8; 2]>> for m8x2[src]

impl Simd for m8x2[src]

type Element = m8

Element type of the SIMD vector

+

type LanesType = [u32; 2]

The type: [u32; Self::N].

+
\ No newline at end of file diff --git a/packed_simd/type.m8x32.html b/packed_simd/type.m8x32.html new file mode 100644 index 000000000..5329067b6 --- /dev/null +++ b/packed_simd/type.m8x32.html @@ -0,0 +1,91 @@ +packed_simd::m8x32 - Rust

[−][src]Type Definition packed_simd::m8x32

type m8x32 = Simd<[m8; 32]>;

A 256-bit vector mask with 32 m8 lanes.

+

Implementations

impl m8x32[src]

pub const fn new(
    x0: bool,
    x1: bool,
    x2: bool,
    x3: bool,
    x4: bool,
    x5: bool,
    x6: bool,
    x7: bool,
    x8: bool,
    x9: bool,
    x10: bool,
    x11: bool,
    x12: bool,
    x13: bool,
    x14: bool,
    x15: bool,
    x16: bool,
    x17: bool,
    x18: bool,
    x19: bool,
    x20: bool,
    x21: bool,
    x22: bool,
    x23: bool,
    x24: bool,
    x25: bool,
    x26: bool,
    x27: bool,
    x28: bool,
    x29: bool,
    x30: bool,
    x31: bool
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: bool) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> bool[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> bool[src]

Extracts the value at index.

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

impl m8x32[src]

pub fn and(self) -> bool[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> bool[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> bool[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl m8x32[src]

pub fn all(self) -> bool[src]

Are all vector lanes true?

+

pub fn any(self) -> bool[src]

Is any vector lane true?

+

pub fn none(self) -> bool[src]

Are all vector lanes false?

+

impl m8x32[src]

pub fn eq(self, other: Self) -> m8x32[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m8x32[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m8x32[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m8x32[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m8x32[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m8x32[src]

Lane-wise greater-than-or-equals comparison.

+

impl m8x32[src]

pub fn select<T>(self, a: Simd<T>, b: Simd<T>) -> Simd<T> where
    T: SimdArray<NT = <[m8; 32] as SimdArray>::NT>, [src]

Selects elements of a and b using mask.

+

The lanes of the result for which the mask is true contain +the values of a. The remaining lanes contain the values of +b.

+

impl m8x32[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<m8x32>[src]

Returns a wrapper that implements PartialOrd.

+

impl m8x32[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<m8x32>[src]

Returns a wrapper that implements Ord.

+

impl m8x32[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl m8x32[src]

pub fn bitmask(self) -> u32[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl BitAnd<Simd<[m8; 32]>> for m8x32[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<bool> for m8x32[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[m8; 32]>> for m8x32[src]

impl BitAndAssign<bool> for m8x32[src]

impl BitOr<Simd<[m8; 32]>> for m8x32[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<bool> for m8x32[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[m8; 32]>> for m8x32[src]

impl BitOrAssign<bool> for m8x32[src]

impl BitXor<Simd<[m8; 32]>> for m8x32[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<bool> for m8x32[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[m8; 32]>> for m8x32[src]

impl BitXorAssign<bool> for m8x32[src]

impl Debug for m8x32[src]

impl Default for m8x32[src]

impl Eq for m8x32[src]

impl From<[m8; 32]> for m8x32[src]

impl FromBits<Simd<[m128; 2]>> for m8x32[src]

impl FromBits<Simd<[m16; 16]>> for m8x32[src]

impl FromBits<Simd<[m32; 8]>> for m8x32[src]

impl FromBits<Simd<[m64; 4]>> for m8x32[src]

impl FromCast<Simd<[i16; 32]>> for m8x32[src]

impl FromCast<Simd<[i8; 32]>> for m8x32[src]

impl FromCast<Simd<[m16; 32]>> for m8x32[src]

impl FromCast<Simd<[u16; 32]>> for m8x32[src]

impl FromCast<Simd<[u8; 32]>> for m8x32[src]

impl Not for m8x32[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl PartialEq<Simd<[m8; 32]>> for m8x32[src]

impl Simd for m8x32[src]

type Element = m8

Element type of the SIMD vector

+

type LanesType = [u32; 32]

The type: [u32; Self::N].

+
\ No newline at end of file diff --git a/packed_simd/type.m8x4.html b/packed_simd/type.m8x4.html new file mode 100644 index 000000000..7f4d01c83 --- /dev/null +++ b/packed_simd/type.m8x4.html @@ -0,0 +1,105 @@ +packed_simd::m8x4 - Rust

[−][src]Type Definition packed_simd::m8x4

type m8x4 = Simd<[m8; 4]>;

A 32-bit vector mask with 4 m8 lanes.

+

Implementations

impl m8x4[src]

pub const fn new(x0: bool, x1: bool, x2: bool, x3: bool) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: bool) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> bool[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> bool[src]

Extracts the value at index.

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

impl m8x4[src]

pub fn and(self) -> bool[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> bool[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> bool[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl m8x4[src]

pub fn all(self) -> bool[src]

Are all vector lanes true?

+

pub fn any(self) -> bool[src]

Is any vector lane true?

+

pub fn none(self) -> bool[src]

Are all vector lanes false?

+

impl m8x4[src]

pub fn eq(self, other: Self) -> m8x4[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m8x4[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m8x4[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m8x4[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m8x4[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m8x4[src]

Lane-wise greater-than-or-equals comparison.

+

impl m8x4[src]

pub fn select<T>(self, a: Simd<T>, b: Simd<T>) -> Simd<T> where
    T: SimdArray<NT = <[m8; 4] as SimdArray>::NT>, [src]

Selects elements of a and b using mask.

+

The lanes of the result for which the mask is true contain +the values of a. The remaining lanes contain the values of +b.

+

impl m8x4[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<m8x4>[src]

Returns a wrapper that implements PartialOrd.

+

impl m8x4[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<m8x4>[src]

Returns a wrapper that implements Ord.

+

impl m8x4[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl m8x4[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl BitAnd<Simd<[m8; 4]>> for m8x4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<bool> for m8x4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[m8; 4]>> for m8x4[src]

impl BitAndAssign<bool> for m8x4[src]

impl BitOr<Simd<[m8; 4]>> for m8x4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<bool> for m8x4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[m8; 4]>> for m8x4[src]

impl BitOrAssign<bool> for m8x4[src]

impl BitXor<Simd<[m8; 4]>> for m8x4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<bool> for m8x4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[m8; 4]>> for m8x4[src]

impl BitXorAssign<bool> for m8x4[src]

impl Debug for m8x4[src]

impl Default for m8x4[src]

impl Eq for m8x4[src]

impl From<[m8; 4]> for m8x4[src]

impl From<Simd<[m16; 4]>> for m8x4[src]

impl From<Simd<[m32; 4]>> for m8x4[src]

impl From<Simd<[m64; 4]>> for m8x4[src]

impl FromBits<Simd<[m16; 2]>> for m8x4[src]

impl FromCast<Simd<[f32; 4]>> for m8x4[src]

impl FromCast<Simd<[f64; 4]>> for m8x4[src]

impl FromCast<Simd<[i128; 4]>> for m8x4[src]

impl FromCast<Simd<[i16; 4]>> for m8x4[src]

impl FromCast<Simd<[i32; 4]>> for m8x4[src]

impl FromCast<Simd<[i64; 4]>> for m8x4[src]

impl FromCast<Simd<[i8; 4]>> for m8x4[src]

impl FromCast<Simd<[isize; 4]>> for m8x4[src]

impl FromCast<Simd<[m128; 4]>> for m8x4[src]

impl FromCast<Simd<[m16; 4]>> for m8x4[src]

impl FromCast<Simd<[m32; 4]>> for m8x4[src]

impl FromCast<Simd<[m64; 4]>> for m8x4[src]

impl FromCast<Simd<[msize; 4]>> for m8x4[src]

impl FromCast<Simd<[u128; 4]>> for m8x4[src]

impl FromCast<Simd<[u16; 4]>> for m8x4[src]

impl FromCast<Simd<[u32; 4]>> for m8x4[src]

impl FromCast<Simd<[u64; 4]>> for m8x4[src]

impl FromCast<Simd<[u8; 4]>> for m8x4[src]

impl FromCast<Simd<[usize; 4]>> for m8x4[src]

impl Not for m8x4[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl PartialEq<Simd<[m8; 4]>> for m8x4[src]

impl Simd for m8x4[src]

type Element = m8

Element type of the SIMD vector

+

type LanesType = [u32; 4]

The type: [u32; Self::N].

+
\ No newline at end of file diff --git a/packed_simd/type.m8x64.html b/packed_simd/type.m8x64.html new file mode 100644 index 000000000..2974d9f50 --- /dev/null +++ b/packed_simd/type.m8x64.html @@ -0,0 +1,88 @@ +packed_simd::m8x64 - Rust

[−][src]Type Definition packed_simd::m8x64

type m8x64 = Simd<[m8; 64]>;

A 512-bit vector mask with 64 m8 lanes.

+

Implementations

impl m8x64[src]

pub const fn new(
    x0: bool,
    x1: bool,
    x2: bool,
    x3: bool,
    x4: bool,
    x5: bool,
    x6: bool,
    x7: bool,
    x8: bool,
    x9: bool,
    x10: bool,
    x11: bool,
    x12: bool,
    x13: bool,
    x14: bool,
    x15: bool,
    x16: bool,
    x17: bool,
    x18: bool,
    x19: bool,
    x20: bool,
    x21: bool,
    x22: bool,
    x23: bool,
    x24: bool,
    x25: bool,
    x26: bool,
    x27: bool,
    x28: bool,
    x29: bool,
    x30: bool,
    x31: bool,
    x32: bool,
    x33: bool,
    x34: bool,
    x35: bool,
    x36: bool,
    x37: bool,
    x38: bool,
    x39: bool,
    x40: bool,
    x41: bool,
    x42: bool,
    x43: bool,
    x44: bool,
    x45: bool,
    x46: bool,
    x47: bool,
    x48: bool,
    x49: bool,
    x50: bool,
    x51: bool,
    x52: bool,
    x53: bool,
    x54: bool,
    x55: bool,
    x56: bool,
    x57: bool,
    x58: bool,
    x59: bool,
    x60: bool,
    x61: bool,
    x62: bool,
    x63: bool
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: bool) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> bool[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> bool[src]

Extracts the value at index.

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

impl m8x64[src]

pub fn and(self) -> bool[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> bool[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> bool[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl m8x64[src]

pub fn all(self) -> bool[src]

Are all vector lanes true?

+

pub fn any(self) -> bool[src]

Is any vector lane true?

+

pub fn none(self) -> bool[src]

Are all vector lanes false?

+

impl m8x64[src]

pub fn eq(self, other: Self) -> m8x64[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m8x64[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m8x64[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m8x64[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m8x64[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m8x64[src]

Lane-wise greater-than-or-equals comparison.

+

impl m8x64[src]

pub fn select<T>(self, a: Simd<T>, b: Simd<T>) -> Simd<T> where
    T: SimdArray<NT = <[m8; 64] as SimdArray>::NT>, [src]

Selects elements of a and b using mask.

+

The lanes of the result for which the mask is true contain +the values of a. The remaining lanes contain the values of +b.

+

impl m8x64[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<m8x64>[src]

Returns a wrapper that implements PartialOrd.

+

impl m8x64[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<m8x64>[src]

Returns a wrapper that implements Ord.

+

impl m8x64[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl m8x64[src]

pub fn bitmask(self) -> u64[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl BitAnd<Simd<[m8; 64]>> for m8x64[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<bool> for m8x64[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[m8; 64]>> for m8x64[src]

impl BitAndAssign<bool> for m8x64[src]

impl BitOr<Simd<[m8; 64]>> for m8x64[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<bool> for m8x64[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[m8; 64]>> for m8x64[src]

impl BitOrAssign<bool> for m8x64[src]

impl BitXor<Simd<[m8; 64]>> for m8x64[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<bool> for m8x64[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[m8; 64]>> for m8x64[src]

impl BitXorAssign<bool> for m8x64[src]

impl Debug for m8x64[src]

impl Default for m8x64[src]

impl Eq for m8x64[src]

impl From<[m8; 64]> for m8x64[src]

impl FromBits<Simd<[m128; 4]>> for m8x64[src]

impl FromBits<Simd<[m16; 32]>> for m8x64[src]

impl FromBits<Simd<[m32; 16]>> for m8x64[src]

impl FromBits<Simd<[m64; 8]>> for m8x64[src]

impl FromCast<Simd<[i8; 64]>> for m8x64[src]

impl FromCast<Simd<[u8; 64]>> for m8x64[src]

impl Not for m8x64[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl PartialEq<Simd<[m8; 64]>> for m8x64[src]

impl Simd for m8x64[src]

type Element = m8

Element type of the SIMD vector

+

type LanesType = [u32; 64]

The type: [u32; Self::N].

+
\ No newline at end of file diff --git a/packed_simd/type.m8x8.html b/packed_simd/type.m8x8.html new file mode 100644 index 000000000..26ed77278 --- /dev/null +++ b/packed_simd/type.m8x8.html @@ -0,0 +1,102 @@ +packed_simd::m8x8 - Rust

[−][src]Type Definition packed_simd::m8x8

type m8x8 = Simd<[m8; 8]>;

A 64-bit vector mask with 8 m8 lanes.

+

Implementations

impl m8x8[src]

pub const fn new(
    x0: bool,
    x1: bool,
    x2: bool,
    x3: bool,
    x4: bool,
    x5: bool,
    x6: bool,
    x7: bool
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: bool) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> bool[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> bool[src]

Extracts the value at index.

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

impl m8x8[src]

pub fn and(self) -> bool[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> bool[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> bool[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl m8x8[src]

pub fn all(self) -> bool[src]

Are all vector lanes true?

+

pub fn any(self) -> bool[src]

Is any vector lane true?

+

pub fn none(self) -> bool[src]

Are all vector lanes false?

+

impl m8x8[src]

pub fn eq(self, other: Self) -> m8x8[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m8x8[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m8x8[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m8x8[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m8x8[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m8x8[src]

Lane-wise greater-than-or-equals comparison.

+

impl m8x8[src]

pub fn select<T>(self, a: Simd<T>, b: Simd<T>) -> Simd<T> where
    T: SimdArray<NT = <[m8; 8] as SimdArray>::NT>, [src]

Selects elements of a and b using mask.

+

The lanes of the result for which the mask is true contain +the values of a. The remaining lanes contain the values of +b.

+

impl m8x8[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<m8x8>[src]

Returns a wrapper that implements PartialOrd.

+

impl m8x8[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<m8x8>[src]

Returns a wrapper that implements Ord.

+

impl m8x8[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl m8x8[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl BitAnd<Simd<[m8; 8]>> for m8x8[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<bool> for m8x8[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[m8; 8]>> for m8x8[src]

impl BitAndAssign<bool> for m8x8[src]

impl BitOr<Simd<[m8; 8]>> for m8x8[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<bool> for m8x8[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[m8; 8]>> for m8x8[src]

impl BitOrAssign<bool> for m8x8[src]

impl BitXor<Simd<[m8; 8]>> for m8x8[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<bool> for m8x8[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[m8; 8]>> for m8x8[src]

impl BitXorAssign<bool> for m8x8[src]

impl Debug for m8x8[src]

impl Default for m8x8[src]

impl Eq for m8x8[src]

impl From<[m8; 8]> for m8x8[src]

impl From<Simd<[m16; 8]>> for m8x8[src]

impl From<Simd<[m32; 8]>> for m8x8[src]

impl FromBits<Simd<[m16; 4]>> for m8x8[src]

impl FromBits<Simd<[m32; 2]>> for m8x8[src]

impl FromCast<Simd<[f32; 8]>> for m8x8[src]

impl FromCast<Simd<[f64; 8]>> for m8x8[src]

impl FromCast<Simd<[i16; 8]>> for m8x8[src]

impl FromCast<Simd<[i32; 8]>> for m8x8[src]

impl FromCast<Simd<[i64; 8]>> for m8x8[src]

impl FromCast<Simd<[i8; 8]>> for m8x8[src]

impl FromCast<Simd<[isize; 8]>> for m8x8[src]

impl FromCast<Simd<[m16; 8]>> for m8x8[src]

impl FromCast<Simd<[m32; 8]>> for m8x8[src]

impl FromCast<Simd<[m64; 8]>> for m8x8[src]

impl FromCast<Simd<[msize; 8]>> for m8x8[src]

impl FromCast<Simd<[u16; 8]>> for m8x8[src]

impl FromCast<Simd<[u32; 8]>> for m8x8[src]

impl FromCast<Simd<[u64; 8]>> for m8x8[src]

impl FromCast<Simd<[u8; 8]>> for m8x8[src]

impl FromCast<Simd<[usize; 8]>> for m8x8[src]

impl Not for m8x8[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl PartialEq<Simd<[m8; 8]>> for m8x8[src]

impl Simd for m8x8[src]

type Element = m8

Element type of the SIMD vector

+

type LanesType = [u32; 8]

The type: [u32; Self::N].

+
\ No newline at end of file diff --git a/packed_simd/type.mptrx2.html b/packed_simd/type.mptrx2.html new file mode 100644 index 000000000..eb4825051 --- /dev/null +++ b/packed_simd/type.mptrx2.html @@ -0,0 +1,284 @@ +packed_simd::mptrx2 - Rust

[−][src]Type Definition packed_simd::mptrx2

type mptrx2<T> = Simd<[*mut T; 2]>;

A vector with 2 *mut T lanes

+

Implementations

impl<T> mptrx2<T>[src]

pub const fn new(x0: *mut T, x1: *mut T) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: *mut T) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub const fn null() -> Self[src]

Constructs a new instance with each element initialized to +null.

+

pub fn is_null(self) -> msizex2[src]

Returns a mask that selects those lanes that contain null +pointers.

+

pub fn extract(self, index: usize) -> *mut T[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> *mut T[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: *mut T) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: *mut T) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl<T> mptrx2<T>[src]

pub fn eq(self, other: Self) -> msizex2[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> msizex2[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> msizex2[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> msizex2[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> msizex2[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> msizex2[src]

Lane-wise greater-than-or-equals comparison.

+

impl<T> mptrx2<T>[src]

pub fn from_slice_aligned(slice: &[*mut T]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[*mut T]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[*mut T]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[*mut T]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl<T> mptrx2<T>[src]

pub fn write_to_slice_aligned(self, slice: &mut [*mut T])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [*mut T])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [*mut T])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [*mut T])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl<T> mptrx2<T>[src]

pub unsafe fn offset(self, count: isizex2) -> Self[src]

Calculates the offset from a pointer.

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

If any of the following conditions are violated, the result is +Undefined Behavior:

+
    +
  • +

    Both the starting and resulting pointer must be either in +bounds or one byte past the end of an allocated object.

    +
    • +
  • +

    The computed offset, in bytes, cannot overflow an isize.

    +
    • +
  • +

    The offset being in bounds cannot rely on "wrapping around" +the address space. That is, the infinite-precision sum, in bytes +must fit in a usize.

    +
    • +
+

The compiler and standard library generally tries to ensure +allocations never reach a size where an offset is a concern. For +instance, Vec and Box ensure they never allocate more than +isize::MAX bytes, so vec.as_ptr().offset(vec.len() as isize) +is always safe.

+

Most platforms fundamentally can't even construct such an +allocation. For instance, no known 64-bit platform can ever +serve a request for 263 bytes due to page-table limitations or +splitting the address space. However, some 32-bit and 16-bit +platforms may successfully serve a request for more than +isize::MAX bytes with things like Physical Address Extension. +As such, memory acquired directly from allocators or memory +mapped files may be too large to handle with this function.

+

Consider using wrapping_offset instead if these constraints +are difficult to satisfy. The only advantage of this method is +that it enables more aggressive compiler optimizations.

+

pub fn wrapping_offset(self, count: isizex2) -> Self[src]

Calculates the offset from a pointer using wrapping arithmetic.

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

The resulting pointer does not need to be in bounds, but it is +potentially hazardous to dereference (which requires unsafe).

+

Always use .offset(count) instead when possible, because +offset allows the compiler to optimize better.

+

pub unsafe fn offset_from(self, origin: Self) -> isizex2[src]

Calculates the distance between two pointers.

+

The returned value is in units of T: the distance in bytes is +divided by mem::size_of::<T>().

+

This function is the inverse of offset.

+

Safety

+

If any of the following conditions are violated, the result is +Undefined Behavior:

+
    +
  • +

    Both the starting and other pointer must be either in bounds +or one byte past the end of the same allocated object.

    +
    • +
  • +

    The distance between the pointers, in bytes, cannot overflow +an isize.

    +
    • +
  • +

    The distance between the pointers, in bytes, must be an exact +multiple of the size of T.

    +
    • +
  • +

    The distance being in bounds cannot rely on "wrapping around" +the address space.

    +
    • +
+

The compiler and standard library generally try to ensure +allocations never reach a size where an offset is a concern. For +instance, Vec and Box ensure they never allocate more than +isize::MAX bytes, so ptr_into_vec.offset_from(vec.as_ptr()) +is always safe.

+

Most platforms fundamentally can't even construct such an +allocation. For instance, no known 64-bit platform can ever +serve a request for 263 bytes due to page-table limitations or +splitting the address space. However, some 32-bit and 16-bit +platforms may successfully serve a request for more than +isize::MAX bytes with things like Physical Address Extension. +As such, memory acquired directly from allocators or memory +mapped files may be too large to handle with this function.

+

Consider using wrapping_offset_from instead if these constraints +are difficult to satisfy. The only advantage of this method is +that it enables more aggressive compiler optimizations.

+

pub fn wrapping_offset_from(self, origin: Self) -> isizex2[src]

Calculates the distance between two pointers.

+

The returned value is in units of T: the distance in bytes is +divided by mem::size_of::<T>().

+

If the address different between the two pointers is not a +multiple of mem::size_of::<T>() then the result of the +division is rounded towards zero.

+

Though this method is safe for any two pointers, note that its +result will be mostly useless if the two pointers aren't into +the same allocated object, for example if they point to two +different local variables.

+

pub unsafe fn add(self, count: usizex2) -> Self[src]

Calculates the offset from a pointer (convenience for +.offset(count as isize)).

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

If any of the following conditions are violated, the result is +Undefined Behavior:

+
    +
  • +

    Both the starting and resulting pointer must be either in +bounds or one byte past the end of an allocated object.

    +
    • +
  • +

    The computed offset, in bytes, cannot overflow an isize.

    +
    • +
  • +

    The offset being in bounds cannot rely on "wrapping around" +the address space. That is, the infinite-precision sum must fit +in a usize.

    +
    • +
+

The compiler and standard library generally tries to ensure +allocations never reach a size where an offset is a concern. For +instance, Vec and Box ensure they never allocate more than +isize::MAX bytes, so vec.as_ptr().add(vec.len()) is always +safe.

+

Most platforms fundamentally can't even construct such an +allocation. For instance, no known 64-bit platform can ever +serve a request for 263 bytes due to page-table limitations or +splitting the address space. However, some 32-bit and 16-bit +platforms may successfully serve a request for more than +isize::MAX bytes with things like Physical Address Extension. +As such, memory acquired directly from allocators or memory +mapped files may be too large to handle with this function.

+

Consider using wrapping_offset instead if these constraints +are difficult to satisfy. The only advantage of this method is +that it enables more aggressive compiler optimizations.

+

pub unsafe fn sub(self, count: usizex2) -> Self[src]

Calculates the offset from a pointer (convenience for +.offset((count as isize).wrapping_neg())).

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

If any of the following conditions are violated, the result is +Undefined Behavior:

+
    +
  • +

    Both the starting and resulting pointer must be either in +bounds or one byte past the end of an allocated object.

    +
    • +
  • +

    The computed offset cannot exceed isize::MAX bytes.

    +
    • +
  • +

    The offset being in bounds cannot rely on "wrapping around" +the address space. That is, the infinite-precision sum must fit +in a usize.

    +
    • +
+

The compiler and standard library generally tries to ensure +allocations never reach a size where an offset is a concern. For +instance, Vec and Box ensure they never allocate more than +isize::MAX bytes, so +vec.as_ptr().add(vec.len()).sub(vec.len()) is always safe.

+

Most platforms fundamentally can't even construct such an +allocation. For instance, no known 64-bit platform can ever +serve a request for 263 bytes due to page-table +limitations or splitting the address space. However, some 32-bit +and 16-bit platforms may successfully serve a request for more +than isize::MAX bytes with things like Physical Address +Extension. As such, memory acquired directly from allocators or +memory mapped files may be too large to handle with this +function.

+

Consider using wrapping_offset instead if these constraints +are difficult to satisfy. The only advantage of this method is +that it enables more aggressive compiler optimizations.

+

pub fn wrapping_add(self, count: usizex2) -> Self[src]

Calculates the offset from a pointer using wrapping arithmetic. +(convenience for .wrapping_offset(count as isize))

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

The resulting pointer does not need to be in bounds, but it is +potentially hazardous to dereference (which requires unsafe).

+

Always use .add(count) instead when possible, because add +allows the compiler to optimize better.

+

pub fn wrapping_sub(self, count: usizex2) -> Self[src]

Calculates the offset from a pointer using wrapping arithmetic. +(convenience for .wrapping_offset((count as isize).wrapping_sub()))

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

The resulting pointer does not need to be in bounds, but it is +potentially hazardous to dereference (which requires unsafe).

+

Always use .sub(count) instead when possible, because sub +allows the compiler to optimize better.

+

impl<T> mptrx2<T>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl<T> mptrx2<T> where
    [T; 2]: SimdArray, [src]

pub unsafe fn read<M>(
    self,
    mask: Simd<[M; 2]>,
    value: Simd<[T; 2]>
) -> Simd<[T; 2]> where
    M: Mask,
    [M; 2]: SimdArray, [src]

Reads selected vector elements from memory.

+

Instantiates a new vector by reading the values from self for +those lanes whose mask is true, and using the elements of +value otherwise.

+

No memory is accessed for those lanes of self whose mask is +false.

+

Safety

+

This method is unsafe because it dereferences raw pointers. The +pointers must be aligned to mem::align_of::<T>().

+

impl<T> mptrx2<T> where
    [T; 2]: SimdArray, [src]

pub unsafe fn write<M>(self, mask: Simd<[M; 2]>, value: Simd<[T; 2]>) where
    M: Mask,
    [M; 2]: SimdArray, [src]

Writes selected vector elements to memory.

+

Writes the lanes of values for which the mask is true to +their corresponding memory addresses in self.

+

No memory is accessed for those lanes of self whose mask is +false.

+

Overlapping memory addresses of self are written to in order +from the lest-significant to the most-significant element.

+

Safety

+

This method is unsafe because it dereferences raw pointers. The +pointers must be aligned to mem::align_of::<T>().

+

Trait Implementations

impl<T> Debug for mptrx2<T>[src]

impl<T> Default for mptrx2<T>[src]

impl<T> Eq for mptrx2<T>[src]

impl<T> From<[*mut T; 2]> for mptrx2<T>[src]

impl<T> Hash for mptrx2<T>[src]

impl<T> Into<[*mut T; 2]> for mptrx2<T>[src]

impl<T> PartialEq<Simd<[*mut T; 2]>> for mptrx2<T>[src]

impl<T> Simd for mptrx2<T>[src]

type Element = *mut T

Element type of the SIMD vector

+

type LanesType = [u32; 2]

The type: [u32; Self::N].

+
\ No newline at end of file diff --git a/packed_simd/type.mptrx4.html b/packed_simd/type.mptrx4.html new file mode 100644 index 000000000..77201519f --- /dev/null +++ b/packed_simd/type.mptrx4.html @@ -0,0 +1,284 @@ +packed_simd::mptrx4 - Rust

[−][src]Type Definition packed_simd::mptrx4

type mptrx4<T> = Simd<[*mut T; 4]>;

A vector with 4 *mut T lanes

+

Implementations

impl<T> mptrx4<T>[src]

pub const fn new(x0: *mut T, x1: *mut T, x2: *mut T, x3: *mut T) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: *mut T) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub const fn null() -> Self[src]

Constructs a new instance with each element initialized to +null.

+

pub fn is_null(self) -> msizex4[src]

Returns a mask that selects those lanes that contain null +pointers.

+

pub fn extract(self, index: usize) -> *mut T[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> *mut T[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: *mut T) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: *mut T) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl<T> mptrx4<T>[src]

pub fn eq(self, other: Self) -> msizex4[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> msizex4[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> msizex4[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> msizex4[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> msizex4[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> msizex4[src]

Lane-wise greater-than-or-equals comparison.

+

impl<T> mptrx4<T>[src]

pub fn from_slice_aligned(slice: &[*mut T]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[*mut T]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[*mut T]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[*mut T]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl<T> mptrx4<T>[src]

pub fn write_to_slice_aligned(self, slice: &mut [*mut T])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [*mut T])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [*mut T])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [*mut T])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl<T> mptrx4<T>[src]

pub unsafe fn offset(self, count: isizex4) -> Self[src]

Calculates the offset from a pointer.

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

If any of the following conditions are violated, the result is +Undefined Behavior:

+
    +
  • +

    Both the starting and resulting pointer must be either in +bounds or one byte past the end of an allocated object.

    +
    • +
  • +

    The computed offset, in bytes, cannot overflow an isize.

    +
    • +
  • +

    The offset being in bounds cannot rely on "wrapping around" +the address space. That is, the infinite-precision sum, in bytes +must fit in a usize.

    +
    • +
+

The compiler and standard library generally tries to ensure +allocations never reach a size where an offset is a concern. For +instance, Vec and Box ensure they never allocate more than +isize::MAX bytes, so vec.as_ptr().offset(vec.len() as isize) +is always safe.

+

Most platforms fundamentally can't even construct such an +allocation. For instance, no known 64-bit platform can ever +serve a request for 263 bytes due to page-table limitations or +splitting the address space. However, some 32-bit and 16-bit +platforms may successfully serve a request for more than +isize::MAX bytes with things like Physical Address Extension. +As such, memory acquired directly from allocators or memory +mapped files may be too large to handle with this function.

+

Consider using wrapping_offset instead if these constraints +are difficult to satisfy. The only advantage of this method is +that it enables more aggressive compiler optimizations.

+

pub fn wrapping_offset(self, count: isizex4) -> Self[src]

Calculates the offset from a pointer using wrapping arithmetic.

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

The resulting pointer does not need to be in bounds, but it is +potentially hazardous to dereference (which requires unsafe).

+

Always use .offset(count) instead when possible, because +offset allows the compiler to optimize better.

+

pub unsafe fn offset_from(self, origin: Self) -> isizex4[src]

Calculates the distance between two pointers.

+

The returned value is in units of T: the distance in bytes is +divided by mem::size_of::<T>().

+

This function is the inverse of offset.

+

Safety

+

If any of the following conditions are violated, the result is +Undefined Behavior:

+
    +
  • +

    Both the starting and other pointer must be either in bounds +or one byte past the end of the same allocated object.

    +
    • +
  • +

    The distance between the pointers, in bytes, cannot overflow +an isize.

    +
    • +
  • +

    The distance between the pointers, in bytes, must be an exact +multiple of the size of T.

    +
    • +
  • +

    The distance being in bounds cannot rely on "wrapping around" +the address space.

    +
    • +
+

The compiler and standard library generally try to ensure +allocations never reach a size where an offset is a concern. For +instance, Vec and Box ensure they never allocate more than +isize::MAX bytes, so ptr_into_vec.offset_from(vec.as_ptr()) +is always safe.

+

Most platforms fundamentally can't even construct such an +allocation. For instance, no known 64-bit platform can ever +serve a request for 263 bytes due to page-table limitations or +splitting the address space. However, some 32-bit and 16-bit +platforms may successfully serve a request for more than +isize::MAX bytes with things like Physical Address Extension. +As such, memory acquired directly from allocators or memory +mapped files may be too large to handle with this function.

+

Consider using wrapping_offset_from instead if these constraints +are difficult to satisfy. The only advantage of this method is +that it enables more aggressive compiler optimizations.

+

pub fn wrapping_offset_from(self, origin: Self) -> isizex4[src]

Calculates the distance between two pointers.

+

The returned value is in units of T: the distance in bytes is +divided by mem::size_of::<T>().

+

If the address different between the two pointers is not a +multiple of mem::size_of::<T>() then the result of the +division is rounded towards zero.

+

Though this method is safe for any two pointers, note that its +result will be mostly useless if the two pointers aren't into +the same allocated object, for example if they point to two +different local variables.

+

pub unsafe fn add(self, count: usizex4) -> Self[src]

Calculates the offset from a pointer (convenience for +.offset(count as isize)).

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

If any of the following conditions are violated, the result is +Undefined Behavior:

+
    +
  • +

    Both the starting and resulting pointer must be either in +bounds or one byte past the end of an allocated object.

    +
    • +
  • +

    The computed offset, in bytes, cannot overflow an isize.

    +
    • +
  • +

    The offset being in bounds cannot rely on "wrapping around" +the address space. That is, the infinite-precision sum must fit +in a usize.

    +
    • +
+

The compiler and standard library generally tries to ensure +allocations never reach a size where an offset is a concern. For +instance, Vec and Box ensure they never allocate more than +isize::MAX bytes, so vec.as_ptr().add(vec.len()) is always +safe.

+

Most platforms fundamentally can't even construct such an +allocation. For instance, no known 64-bit platform can ever +serve a request for 263 bytes due to page-table limitations or +splitting the address space. However, some 32-bit and 16-bit +platforms may successfully serve a request for more than +isize::MAX bytes with things like Physical Address Extension. +As such, memory acquired directly from allocators or memory +mapped files may be too large to handle with this function.

+

Consider using wrapping_offset instead if these constraints +are difficult to satisfy. The only advantage of this method is +that it enables more aggressive compiler optimizations.

+

pub unsafe fn sub(self, count: usizex4) -> Self[src]

Calculates the offset from a pointer (convenience for +.offset((count as isize).wrapping_neg())).

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

If any of the following conditions are violated, the result is +Undefined Behavior:

+
    +
  • +

    Both the starting and resulting pointer must be either in +bounds or one byte past the end of an allocated object.

    +
    • +
  • +

    The computed offset cannot exceed isize::MAX bytes.

    +
    • +
  • +

    The offset being in bounds cannot rely on "wrapping around" +the address space. That is, the infinite-precision sum must fit +in a usize.

    +
    • +
+

The compiler and standard library generally tries to ensure +allocations never reach a size where an offset is a concern. For +instance, Vec and Box ensure they never allocate more than +isize::MAX bytes, so +vec.as_ptr().add(vec.len()).sub(vec.len()) is always safe.

+

Most platforms fundamentally can't even construct such an +allocation. For instance, no known 64-bit platform can ever +serve a request for 263 bytes due to page-table +limitations or splitting the address space. However, some 32-bit +and 16-bit platforms may successfully serve a request for more +than isize::MAX bytes with things like Physical Address +Extension. As such, memory acquired directly from allocators or +memory mapped files may be too large to handle with this +function.

+

Consider using wrapping_offset instead if these constraints +are difficult to satisfy. The only advantage of this method is +that it enables more aggressive compiler optimizations.

+

pub fn wrapping_add(self, count: usizex4) -> Self[src]

Calculates the offset from a pointer using wrapping arithmetic. +(convenience for .wrapping_offset(count as isize))

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

The resulting pointer does not need to be in bounds, but it is +potentially hazardous to dereference (which requires unsafe).

+

Always use .add(count) instead when possible, because add +allows the compiler to optimize better.

+

pub fn wrapping_sub(self, count: usizex4) -> Self[src]

Calculates the offset from a pointer using wrapping arithmetic. +(convenience for .wrapping_offset((count as isize).wrapping_sub()))

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

The resulting pointer does not need to be in bounds, but it is +potentially hazardous to dereference (which requires unsafe).

+

Always use .sub(count) instead when possible, because sub +allows the compiler to optimize better.

+

impl<T> mptrx4<T>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl<T> mptrx4<T> where
    [T; 4]: SimdArray, [src]

pub unsafe fn read<M>(
    self,
    mask: Simd<[M; 4]>,
    value: Simd<[T; 4]>
) -> Simd<[T; 4]> where
    M: Mask,
    [M; 4]: SimdArray, [src]

Reads selected vector elements from memory.

+

Instantiates a new vector by reading the values from self for +those lanes whose mask is true, and using the elements of +value otherwise.

+

No memory is accessed for those lanes of self whose mask is +false.

+

Safety

+

This method is unsafe because it dereferences raw pointers. The +pointers must be aligned to mem::align_of::<T>().

+

impl<T> mptrx4<T> where
    [T; 4]: SimdArray, [src]

pub unsafe fn write<M>(self, mask: Simd<[M; 4]>, value: Simd<[T; 4]>) where
    M: Mask,
    [M; 4]: SimdArray, [src]

Writes selected vector elements to memory.

+

Writes the lanes of values for which the mask is true to +their corresponding memory addresses in self.

+

No memory is accessed for those lanes of self whose mask is +false.

+

Overlapping memory addresses of self are written to in order +from the lest-significant to the most-significant element.

+

Safety

+

This method is unsafe because it dereferences raw pointers. The +pointers must be aligned to mem::align_of::<T>().

+

Trait Implementations

impl<T> Debug for mptrx4<T>[src]

impl<T> Default for mptrx4<T>[src]

impl<T> Eq for mptrx4<T>[src]

impl<T> From<[*mut T; 4]> for mptrx4<T>[src]

impl<T> Hash for mptrx4<T>[src]

impl<T> Into<[*mut T; 4]> for mptrx4<T>[src]

impl<T> PartialEq<Simd<[*mut T; 4]>> for mptrx4<T>[src]

impl<T> Simd for mptrx4<T>[src]

type Element = *mut T

Element type of the SIMD vector

+

type LanesType = [u32; 4]

The type: [u32; Self::N].

+
\ No newline at end of file diff --git a/packed_simd/type.mptrx8.html b/packed_simd/type.mptrx8.html new file mode 100644 index 000000000..e5c6510de --- /dev/null +++ b/packed_simd/type.mptrx8.html @@ -0,0 +1,284 @@ +packed_simd::mptrx8 - Rust

[−][src]Type Definition packed_simd::mptrx8

type mptrx8<T> = Simd<[*mut T; 8]>;

A vector with 8 *mut T lanes

+

Implementations

impl<T> mptrx8<T>[src]

pub const fn new(
    x0: *mut T,
    x1: *mut T,
    x2: *mut T,
    x3: *mut T,
    x4: *mut T,
    x5: *mut T,
    x6: *mut T,
    x7: *mut T
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: *mut T) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub const fn null() -> Self[src]

Constructs a new instance with each element initialized to +null.

+

pub fn is_null(self) -> msizex8[src]

Returns a mask that selects those lanes that contain null +pointers.

+

pub fn extract(self, index: usize) -> *mut T[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> *mut T[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: *mut T) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: *mut T) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl<T> mptrx8<T>[src]

pub fn eq(self, other: Self) -> msizex8[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> msizex8[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> msizex8[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> msizex8[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> msizex8[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> msizex8[src]

Lane-wise greater-than-or-equals comparison.

+

impl<T> mptrx8<T>[src]

pub fn from_slice_aligned(slice: &[*mut T]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[*mut T]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[*mut T]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[*mut T]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl<T> mptrx8<T>[src]

pub fn write_to_slice_aligned(self, slice: &mut [*mut T])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [*mut T])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [*mut T])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [*mut T])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl<T> mptrx8<T>[src]

pub unsafe fn offset(self, count: isizex8) -> Self[src]

Calculates the offset from a pointer.

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

If any of the following conditions are violated, the result is +Undefined Behavior:

+
    +
  • +

    Both the starting and resulting pointer must be either in +bounds or one byte past the end of an allocated object.

    +
    • +
  • +

    The computed offset, in bytes, cannot overflow an isize.

    +
    • +
  • +

    The offset being in bounds cannot rely on "wrapping around" +the address space. That is, the infinite-precision sum, in bytes +must fit in a usize.

    +
    • +
+

The compiler and standard library generally tries to ensure +allocations never reach a size where an offset is a concern. For +instance, Vec and Box ensure they never allocate more than +isize::MAX bytes, so vec.as_ptr().offset(vec.len() as isize) +is always safe.

+

Most platforms fundamentally can't even construct such an +allocation. For instance, no known 64-bit platform can ever +serve a request for 263 bytes due to page-table limitations or +splitting the address space. However, some 32-bit and 16-bit +platforms may successfully serve a request for more than +isize::MAX bytes with things like Physical Address Extension. +As such, memory acquired directly from allocators or memory +mapped files may be too large to handle with this function.

+

Consider using wrapping_offset instead if these constraints +are difficult to satisfy. The only advantage of this method is +that it enables more aggressive compiler optimizations.

+

pub fn wrapping_offset(self, count: isizex8) -> Self[src]

Calculates the offset from a pointer using wrapping arithmetic.

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

The resulting pointer does not need to be in bounds, but it is +potentially hazardous to dereference (which requires unsafe).

+

Always use .offset(count) instead when possible, because +offset allows the compiler to optimize better.

+

pub unsafe fn offset_from(self, origin: Self) -> isizex8[src]

Calculates the distance between two pointers.

+

The returned value is in units of T: the distance in bytes is +divided by mem::size_of::<T>().

+

This function is the inverse of offset.

+

Safety

+

If any of the following conditions are violated, the result is +Undefined Behavior:

+
    +
  • +

    Both the starting and other pointer must be either in bounds +or one byte past the end of the same allocated object.

    +
    • +
  • +

    The distance between the pointers, in bytes, cannot overflow +an isize.

    +
    • +
  • +

    The distance between the pointers, in bytes, must be an exact +multiple of the size of T.

    +
    • +
  • +

    The distance being in bounds cannot rely on "wrapping around" +the address space.

    +
    • +
+

The compiler and standard library generally try to ensure +allocations never reach a size where an offset is a concern. For +instance, Vec and Box ensure they never allocate more than +isize::MAX bytes, so ptr_into_vec.offset_from(vec.as_ptr()) +is always safe.

+

Most platforms fundamentally can't even construct such an +allocation. For instance, no known 64-bit platform can ever +serve a request for 263 bytes due to page-table limitations or +splitting the address space. However, some 32-bit and 16-bit +platforms may successfully serve a request for more than +isize::MAX bytes with things like Physical Address Extension. +As such, memory acquired directly from allocators or memory +mapped files may be too large to handle with this function.

+

Consider using wrapping_offset_from instead if these constraints +are difficult to satisfy. The only advantage of this method is +that it enables more aggressive compiler optimizations.

+

pub fn wrapping_offset_from(self, origin: Self) -> isizex8[src]

Calculates the distance between two pointers.

+

The returned value is in units of T: the distance in bytes is +divided by mem::size_of::<T>().

+

If the address different between the two pointers is not a +multiple of mem::size_of::<T>() then the result of the +division is rounded towards zero.

+

Though this method is safe for any two pointers, note that its +result will be mostly useless if the two pointers aren't into +the same allocated object, for example if they point to two +different local variables.

+

pub unsafe fn add(self, count: usizex8) -> Self[src]

Calculates the offset from a pointer (convenience for +.offset(count as isize)).

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

If any of the following conditions are violated, the result is +Undefined Behavior:

+
    +
  • +

    Both the starting and resulting pointer must be either in +bounds or one byte past the end of an allocated object.

    +
    • +
  • +

    The computed offset, in bytes, cannot overflow an isize.

    +
    • +
  • +

    The offset being in bounds cannot rely on "wrapping around" +the address space. That is, the infinite-precision sum must fit +in a usize.

    +
    • +
+

The compiler and standard library generally tries to ensure +allocations never reach a size where an offset is a concern. For +instance, Vec and Box ensure they never allocate more than +isize::MAX bytes, so vec.as_ptr().add(vec.len()) is always +safe.

+

Most platforms fundamentally can't even construct such an +allocation. For instance, no known 64-bit platform can ever +serve a request for 263 bytes due to page-table limitations or +splitting the address space. However, some 32-bit and 16-bit +platforms may successfully serve a request for more than +isize::MAX bytes with things like Physical Address Extension. +As such, memory acquired directly from allocators or memory +mapped files may be too large to handle with this function.

+

Consider using wrapping_offset instead if these constraints +are difficult to satisfy. The only advantage of this method is +that it enables more aggressive compiler optimizations.

+

pub unsafe fn sub(self, count: usizex8) -> Self[src]

Calculates the offset from a pointer (convenience for +.offset((count as isize).wrapping_neg())).

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

If any of the following conditions are violated, the result is +Undefined Behavior:

+
    +
  • +

    Both the starting and resulting pointer must be either in +bounds or one byte past the end of an allocated object.

    +
    • +
  • +

    The computed offset cannot exceed isize::MAX bytes.

    +
    • +
  • +

    The offset being in bounds cannot rely on "wrapping around" +the address space. That is, the infinite-precision sum must fit +in a usize.

    +
    • +
+

The compiler and standard library generally tries to ensure +allocations never reach a size where an offset is a concern. For +instance, Vec and Box ensure they never allocate more than +isize::MAX bytes, so +vec.as_ptr().add(vec.len()).sub(vec.len()) is always safe.

+

Most platforms fundamentally can't even construct such an +allocation. For instance, no known 64-bit platform can ever +serve a request for 263 bytes due to page-table +limitations or splitting the address space. However, some 32-bit +and 16-bit platforms may successfully serve a request for more +than isize::MAX bytes with things like Physical Address +Extension. As such, memory acquired directly from allocators or +memory mapped files may be too large to handle with this +function.

+

Consider using wrapping_offset instead if these constraints +are difficult to satisfy. The only advantage of this method is +that it enables more aggressive compiler optimizations.

+

pub fn wrapping_add(self, count: usizex8) -> Self[src]

Calculates the offset from a pointer using wrapping arithmetic. +(convenience for .wrapping_offset(count as isize))

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

The resulting pointer does not need to be in bounds, but it is +potentially hazardous to dereference (which requires unsafe).

+

Always use .add(count) instead when possible, because add +allows the compiler to optimize better.

+

pub fn wrapping_sub(self, count: usizex8) -> Self[src]

Calculates the offset from a pointer using wrapping arithmetic. +(convenience for .wrapping_offset((count as isize).wrapping_sub()))

+

count is in units of T; e.g. a count of 3 represents a +pointer offset of 3 * size_of::<T>() bytes.

+

Safety

+

The resulting pointer does not need to be in bounds, but it is +potentially hazardous to dereference (which requires unsafe).

+

Always use .sub(count) instead when possible, because sub +allows the compiler to optimize better.

+

impl<T> mptrx8<T>[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl<T> mptrx8<T> where
    [T; 8]: SimdArray, [src]

pub unsafe fn read<M>(
    self,
    mask: Simd<[M; 8]>,
    value: Simd<[T; 8]>
) -> Simd<[T; 8]> where
    M: Mask,
    [M; 8]: SimdArray, [src]

Reads selected vector elements from memory.

+

Instantiates a new vector by reading the values from self for +those lanes whose mask is true, and using the elements of +value otherwise.

+

No memory is accessed for those lanes of self whose mask is +false.

+

Safety

+

This method is unsafe because it dereferences raw pointers. The +pointers must be aligned to mem::align_of::<T>().

+

impl<T> mptrx8<T> where
    [T; 8]: SimdArray, [src]

pub unsafe fn write<M>(self, mask: Simd<[M; 8]>, value: Simd<[T; 8]>) where
    M: Mask,
    [M; 8]: SimdArray, [src]

Writes selected vector elements to memory.

+

Writes the lanes of values for which the mask is true to +their corresponding memory addresses in self.

+

No memory is accessed for those lanes of self whose mask is +false.

+

Overlapping memory addresses of self are written to in order +from the lest-significant to the most-significant element.

+

Safety

+

This method is unsafe because it dereferences raw pointers. The +pointers must be aligned to mem::align_of::<T>().

+

Trait Implementations

impl<T> Debug for mptrx8<T>[src]

impl<T> Default for mptrx8<T>[src]

impl<T> Eq for mptrx8<T>[src]

impl<T> From<[*mut T; 8]> for mptrx8<T>[src]

impl<T> Hash for mptrx8<T>[src]

impl<T> Into<[*mut T; 8]> for mptrx8<T>[src]

impl<T> PartialEq<Simd<[*mut T; 8]>> for mptrx8<T>[src]

impl<T> Simd for mptrx8<T>[src]

type Element = *mut T

Element type of the SIMD vector

+

type LanesType = [u32; 8]

The type: [u32; Self::N].

+
\ No newline at end of file diff --git a/packed_simd/type.msizex2.html b/packed_simd/type.msizex2.html new file mode 100644 index 000000000..f247c4ee3 --- /dev/null +++ b/packed_simd/type.msizex2.html @@ -0,0 +1,101 @@ +packed_simd::msizex2 - Rust

[−][src]Type Definition packed_simd::msizex2

type msizex2 = Simd<[msize; 2]>;

A vector mask with 2 msize lanes.

+

Implementations

impl msizex2[src]

pub const fn new(x0: bool, x1: bool) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: bool) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> bool[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> bool[src]

Extracts the value at index.

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

impl msizex2[src]

pub fn and(self) -> bool[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> bool[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> bool[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl msizex2[src]

pub fn all(self) -> bool[src]

Are all vector lanes true?

+

pub fn any(self) -> bool[src]

Is any vector lane true?

+

pub fn none(self) -> bool[src]

Are all vector lanes false?

+

impl msizex2[src]

pub fn eq(self, other: Self) -> msizex2[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> msizex2[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> msizex2[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> msizex2[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> msizex2[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> msizex2[src]

Lane-wise greater-than-or-equals comparison.

+

impl msizex2[src]

pub fn select<T>(self, a: Simd<T>, b: Simd<T>) -> Simd<T> where
    T: SimdArray<NT = <[msize; 2] as SimdArray>::NT>, [src]

Selects elements of a and b using mask.

+

The lanes of the result for which the mask is true contain +the values of a. The remaining lanes contain the values of +b.

+

impl msizex2[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<msizex2>[src]

Returns a wrapper that implements PartialOrd.

+

impl msizex2[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<msizex2>[src]

Returns a wrapper that implements Ord.

+

impl msizex2[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl msizex2[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl BitAnd<Simd<[msize; 2]>> for msizex2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<bool> for msizex2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[msize; 2]>> for msizex2[src]

impl BitAndAssign<bool> for msizex2[src]

impl BitOr<Simd<[msize; 2]>> for msizex2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<bool> for msizex2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[msize; 2]>> for msizex2[src]

impl BitOrAssign<bool> for msizex2[src]

impl BitXor<Simd<[msize; 2]>> for msizex2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<bool> for msizex2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[msize; 2]>> for msizex2[src]

impl BitXorAssign<bool> for msizex2[src]

impl Debug for msizex2[src]

impl Default for msizex2[src]

impl Eq for msizex2[src]

impl From<[msize; 2]> for msizex2[src]

impl FromCast<Simd<[f32; 2]>> for msizex2[src]

impl FromCast<Simd<[f64; 2]>> for msizex2[src]

impl FromCast<Simd<[i128; 2]>> for msizex2[src]

impl FromCast<Simd<[i16; 2]>> for msizex2[src]

impl FromCast<Simd<[i32; 2]>> for msizex2[src]

impl FromCast<Simd<[i64; 2]>> for msizex2[src]

impl FromCast<Simd<[i8; 2]>> for msizex2[src]

impl FromCast<Simd<[isize; 2]>> for msizex2[src]

impl FromCast<Simd<[m128; 2]>> for msizex2[src]

impl FromCast<Simd<[m16; 2]>> for msizex2[src]

impl FromCast<Simd<[m32; 2]>> for msizex2[src]

impl FromCast<Simd<[m64; 2]>> for msizex2[src]

impl FromCast<Simd<[m8; 2]>> for msizex2[src]

impl FromCast<Simd<[u128; 2]>> for msizex2[src]

impl FromCast<Simd<[u16; 2]>> for msizex2[src]

impl FromCast<Simd<[u32; 2]>> for msizex2[src]

impl FromCast<Simd<[u64; 2]>> for msizex2[src]

impl FromCast<Simd<[u8; 2]>> for msizex2[src]

impl FromCast<Simd<[usize; 2]>> for msizex2[src]

impl Not for msizex2[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl PartialEq<Simd<[msize; 2]>> for msizex2[src]

impl Simd for msizex2[src]

type Element = msize

Element type of the SIMD vector

+

type LanesType = [u32; 2]

The type: [u32; Self::N].

+
\ No newline at end of file diff --git a/packed_simd/type.msizex4.html b/packed_simd/type.msizex4.html new file mode 100644 index 000000000..679b0338a --- /dev/null +++ b/packed_simd/type.msizex4.html @@ -0,0 +1,101 @@ +packed_simd::msizex4 - Rust

[−][src]Type Definition packed_simd::msizex4

type msizex4 = Simd<[msize; 4]>;

A vector mask with 4 msize lanes.

+

Implementations

impl msizex4[src]

pub const fn new(x0: bool, x1: bool, x2: bool, x3: bool) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: bool) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> bool[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> bool[src]

Extracts the value at index.

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

impl msizex4[src]

pub fn and(self) -> bool[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> bool[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> bool[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl msizex4[src]

pub fn all(self) -> bool[src]

Are all vector lanes true?

+

pub fn any(self) -> bool[src]

Is any vector lane true?

+

pub fn none(self) -> bool[src]

Are all vector lanes false?

+

impl msizex4[src]

pub fn eq(self, other: Self) -> msizex4[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> msizex4[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> msizex4[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> msizex4[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> msizex4[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> msizex4[src]

Lane-wise greater-than-or-equals comparison.

+

impl msizex4[src]

pub fn select<T>(self, a: Simd<T>, b: Simd<T>) -> Simd<T> where
    T: SimdArray<NT = <[msize; 4] as SimdArray>::NT>, [src]

Selects elements of a and b using mask.

+

The lanes of the result for which the mask is true contain +the values of a. The remaining lanes contain the values of +b.

+

impl msizex4[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<msizex4>[src]

Returns a wrapper that implements PartialOrd.

+

impl msizex4[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<msizex4>[src]

Returns a wrapper that implements Ord.

+

impl msizex4[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl msizex4[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl BitAnd<Simd<[msize; 4]>> for msizex4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<bool> for msizex4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[msize; 4]>> for msizex4[src]

impl BitAndAssign<bool> for msizex4[src]

impl BitOr<Simd<[msize; 4]>> for msizex4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<bool> for msizex4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[msize; 4]>> for msizex4[src]

impl BitOrAssign<bool> for msizex4[src]

impl BitXor<Simd<[msize; 4]>> for msizex4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<bool> for msizex4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[msize; 4]>> for msizex4[src]

impl BitXorAssign<bool> for msizex4[src]

impl Debug for msizex4[src]

impl Default for msizex4[src]

impl Eq for msizex4[src]

impl From<[msize; 4]> for msizex4[src]

impl FromCast<Simd<[f32; 4]>> for msizex4[src]

impl FromCast<Simd<[f64; 4]>> for msizex4[src]

impl FromCast<Simd<[i128; 4]>> for msizex4[src]

impl FromCast<Simd<[i16; 4]>> for msizex4[src]

impl FromCast<Simd<[i32; 4]>> for msizex4[src]

impl FromCast<Simd<[i64; 4]>> for msizex4[src]

impl FromCast<Simd<[i8; 4]>> for msizex4[src]

impl FromCast<Simd<[isize; 4]>> for msizex4[src]

impl FromCast<Simd<[m128; 4]>> for msizex4[src]

impl FromCast<Simd<[m16; 4]>> for msizex4[src]

impl FromCast<Simd<[m32; 4]>> for msizex4[src]

impl FromCast<Simd<[m64; 4]>> for msizex4[src]

impl FromCast<Simd<[m8; 4]>> for msizex4[src]

impl FromCast<Simd<[u128; 4]>> for msizex4[src]

impl FromCast<Simd<[u16; 4]>> for msizex4[src]

impl FromCast<Simd<[u32; 4]>> for msizex4[src]

impl FromCast<Simd<[u64; 4]>> for msizex4[src]

impl FromCast<Simd<[u8; 4]>> for msizex4[src]

impl FromCast<Simd<[usize; 4]>> for msizex4[src]

impl Not for msizex4[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl PartialEq<Simd<[msize; 4]>> for msizex4[src]

impl Simd for msizex4[src]

type Element = msize

Element type of the SIMD vector

+

type LanesType = [u32; 4]

The type: [u32; Self::N].

+
\ No newline at end of file diff --git a/packed_simd/type.msizex8.html b/packed_simd/type.msizex8.html new file mode 100644 index 000000000..82845f24c --- /dev/null +++ b/packed_simd/type.msizex8.html @@ -0,0 +1,98 @@ +packed_simd::msizex8 - Rust

[−][src]Type Definition packed_simd::msizex8

type msizex8 = Simd<[msize; 8]>;

A vector mask with 8 msize lanes.

+

Implementations

impl msizex8[src]

pub const fn new(
    x0: bool,
    x1: bool,
    x2: bool,
    x3: bool,
    x4: bool,
    x5: bool,
    x6: bool,
    x7: bool
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: bool) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> bool[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> bool[src]

Extracts the value at index.

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: bool) -> Self[src]

Returns a new vector where the value at index is replaced by +new_value.

+

Panics

+

If index >= Self::lanes().

+

impl msizex8[src]

pub fn and(self) -> bool[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> bool[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> bool[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl msizex8[src]

pub fn all(self) -> bool[src]

Are all vector lanes true?

+

pub fn any(self) -> bool[src]

Is any vector lane true?

+

pub fn none(self) -> bool[src]

Are all vector lanes false?

+

impl msizex8[src]

pub fn eq(self, other: Self) -> msizex8[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> msizex8[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> msizex8[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> msizex8[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> msizex8[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> msizex8[src]

Lane-wise greater-than-or-equals comparison.

+

impl msizex8[src]

pub fn select<T>(self, a: Simd<T>, b: Simd<T>) -> Simd<T> where
    T: SimdArray<NT = <[msize; 8] as SimdArray>::NT>, [src]

Selects elements of a and b using mask.

+

The lanes of the result for which the mask is true contain +the values of a. The remaining lanes contain the values of +b.

+

impl msizex8[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<msizex8>[src]

Returns a wrapper that implements PartialOrd.

+

impl msizex8[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<msizex8>[src]

Returns a wrapper that implements Ord.

+

impl msizex8[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl msizex8[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl BitAnd<Simd<[msize; 8]>> for msizex8[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<bool> for msizex8[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[msize; 8]>> for msizex8[src]

impl BitAndAssign<bool> for msizex8[src]

impl BitOr<Simd<[msize; 8]>> for msizex8[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<bool> for msizex8[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[msize; 8]>> for msizex8[src]

impl BitOrAssign<bool> for msizex8[src]

impl BitXor<Simd<[msize; 8]>> for msizex8[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<bool> for msizex8[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[msize; 8]>> for msizex8[src]

impl BitXorAssign<bool> for msizex8[src]

impl Debug for msizex8[src]

impl Default for msizex8[src]

impl Eq for msizex8[src]

impl From<[msize; 8]> for msizex8[src]

impl FromCast<Simd<[f32; 8]>> for msizex8[src]

impl FromCast<Simd<[f64; 8]>> for msizex8[src]

impl FromCast<Simd<[i16; 8]>> for msizex8[src]

impl FromCast<Simd<[i32; 8]>> for msizex8[src]

impl FromCast<Simd<[i64; 8]>> for msizex8[src]

impl FromCast<Simd<[i8; 8]>> for msizex8[src]

impl FromCast<Simd<[isize; 8]>> for msizex8[src]

impl FromCast<Simd<[m16; 8]>> for msizex8[src]

impl FromCast<Simd<[m32; 8]>> for msizex8[src]

impl FromCast<Simd<[m64; 8]>> for msizex8[src]

impl FromCast<Simd<[m8; 8]>> for msizex8[src]

impl FromCast<Simd<[u16; 8]>> for msizex8[src]

impl FromCast<Simd<[u32; 8]>> for msizex8[src]

impl FromCast<Simd<[u64; 8]>> for msizex8[src]

impl FromCast<Simd<[u8; 8]>> for msizex8[src]

impl FromCast<Simd<[usize; 8]>> for msizex8[src]

impl Not for msizex8[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl PartialEq<Simd<[msize; 8]>> for msizex8[src]

impl Simd for msizex8[src]

type Element = msize

Element type of the SIMD vector

+

type LanesType = [u32; 8]

The type: [u32; Self::N].

+
\ No newline at end of file diff --git a/packed_simd/type.u128x1.html b/packed_simd/type.u128x1.html new file mode 100644 index 000000000..6f365debd --- /dev/null +++ b/packed_simd/type.u128x1.html @@ -0,0 +1,231 @@ +packed_simd::u128x1 - Rust

[−][src]Type Definition packed_simd::u128x1

type u128x1 = Simd<[u128; 1]>;

A 128-bit vector with 1 u128 lane.

+

Implementations

impl u128x1[src]

pub const fn new(x0: u128) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: u128) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> u128[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> u128[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: u128) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: u128) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl u128x1[src]

pub fn rotate_left(self, n: u128x1) -> u128x1[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: u128x1) -> u128x1[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl u128x1[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl u128x1[src]

pub fn wrapping_sum(self) -> u128[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> u128[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl u128x1[src]

pub fn max_element(self) -> u128[src]

Largest vector element value.

+

pub fn min_element(self) -> u128[src]

Smallest vector element value.

+

impl u128x1[src]

pub fn and(self) -> u128[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> u128[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> u128[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl u128x1[src]

pub fn from_slice_aligned(slice: &[u128]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[u128]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[u128]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[u128]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl u128x1[src]

pub fn write_to_slice_aligned(self, slice: &mut [u128])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [u128])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [u128])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [u128])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl u128x1[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl u128x1[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl u128x1[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl u128x1[src]

pub fn eq(self, other: Self) -> m128x1[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m128x1[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m128x1[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m128x1[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m128x1[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m128x1[src]

Lane-wise greater-than-or-equals comparison.

+

impl u128x1[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<u128x1>[src]

Returns a wrapper that implements PartialOrd.

+

impl u128x1[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<u128x1>[src]

Returns a wrapper that implements Ord.

+

impl u128x1[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl Add<Simd<[u128; 1]>> for u128x1[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<u128> for u128x1[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[u128; 1]>> for u128x1[src]

impl AddAssign<u128> for u128x1[src]

impl Binary for u128x1[src]

impl BitAnd<Simd<[u128; 1]>> for u128x1[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<u128> for u128x1[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[u128; 1]>> for u128x1[src]

impl BitAndAssign<u128> for u128x1[src]

impl BitOr<Simd<[u128; 1]>> for u128x1[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<u128> for u128x1[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[u128; 1]>> for u128x1[src]

impl BitOrAssign<u128> for u128x1[src]

impl BitXor<Simd<[u128; 1]>> for u128x1[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<u128> for u128x1[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[u128; 1]>> for u128x1[src]

impl BitXorAssign<u128> for u128x1[src]

impl Debug for u128x1[src]

impl Default for u128x1[src]

impl Div<Simd<[u128; 1]>> for u128x1[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<u128> for u128x1[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[u128; 1]>> for u128x1[src]

impl DivAssign<u128> for u128x1[src]

impl Eq for u128x1[src]

impl From<[u128; 1]> for u128x1[src]

impl FromBits<Simd<[f32; 4]>> for u128x1[src]

impl FromBits<Simd<[f64; 2]>> for u128x1[src]

impl FromBits<Simd<[i128; 1]>> for u128x1[src]

impl FromBits<Simd<[i16; 8]>> for u128x1[src]

impl FromBits<Simd<[i32; 4]>> for u128x1[src]

impl FromBits<Simd<[i64; 2]>> for u128x1[src]

impl FromBits<Simd<[i8; 16]>> for u128x1[src]

impl FromBits<Simd<[m128; 1]>> for u128x1[src]

impl FromBits<Simd<[m16; 8]>> for u128x1[src]

impl FromBits<Simd<[m32; 4]>> for u128x1[src]

impl FromBits<Simd<[m64; 2]>> for u128x1[src]

impl FromBits<Simd<[m8; 16]>> for u128x1[src]

impl FromBits<Simd<[u16; 8]>> for u128x1[src]

impl FromBits<Simd<[u32; 4]>> for u128x1[src]

impl FromBits<Simd<[u64; 2]>> for u128x1[src]

impl FromBits<Simd<[u8; 16]>> for u128x1[src]

impl FromBits<__m128> for u128x1[src]

impl FromBits<__m128d> for u128x1[src]

impl FromBits<__m128i> for u128x1[src]

impl FromCast<Simd<[i128; 1]>> for u128x1[src]

impl FromCast<Simd<[m128; 1]>> for u128x1[src]

impl Hash for u128x1[src]

impl LowerHex for u128x1[src]

impl Mul<Simd<[u128; 1]>> for u128x1[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<u128> for u128x1[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[u128; 1]>> for u128x1[src]

impl MulAssign<u128> for u128x1[src]

impl Not for u128x1[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl Octal for u128x1[src]

impl PartialEq<Simd<[u128; 1]>> for u128x1[src]

impl<'a> Product<&'a Simd<[u128; 1]>> for u128x1[src]

impl Product<Simd<[u128; 1]>> for u128x1[src]

impl Rem<Simd<[u128; 1]>> for u128x1[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<u128> for u128x1[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[u128; 1]>> for u128x1[src]

impl RemAssign<u128> for u128x1[src]

impl Shl<Simd<[u128; 1]>> for u128x1[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<u32> for u128x1[src]

type Output = Self

The resulting type after applying the << operator.

+

impl ShlAssign<Simd<[u128; 1]>> for u128x1[src]

impl ShlAssign<u32> for u128x1[src]

impl Shr<Simd<[u128; 1]>> for u128x1[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<u32> for u128x1[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl ShrAssign<Simd<[u128; 1]>> for u128x1[src]

impl ShrAssign<u32> for u128x1[src]

impl Simd for u128x1[src]

type Element = u128

Element type of the SIMD vector

+

type LanesType = [u32; 1]

The type: [u32; Self::N].

+

impl Sub<Simd<[u128; 1]>> for u128x1[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<u128> for u128x1[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[u128; 1]>> for u128x1[src]

impl SubAssign<u128> for u128x1[src]

impl<'a> Sum<&'a Simd<[u128; 1]>> for u128x1[src]

impl Sum<Simd<[u128; 1]>> for u128x1[src]

impl UpperHex for u128x1[src]

\ No newline at end of file diff --git a/packed_simd/type.u128x2.html b/packed_simd/type.u128x2.html new file mode 100644 index 000000000..5126e20eb --- /dev/null +++ b/packed_simd/type.u128x2.html @@ -0,0 +1,252 @@ +packed_simd::u128x2 - Rust

[−][src]Type Definition packed_simd::u128x2

type u128x2 = Simd<[u128; 2]>;

A 256-bit vector with 2 u128 lanes.

+

Implementations

impl u128x2[src]

pub const fn new(x0: u128, x1: u128) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: u128) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> u128[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> u128[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: u128) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: u128) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl u128x2[src]

pub fn rotate_left(self, n: u128x2) -> u128x2[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: u128x2) -> u128x2[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl u128x2[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl u128x2[src]

pub fn wrapping_sum(self) -> u128[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> u128[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl u128x2[src]

pub fn max_element(self) -> u128[src]

Largest vector element value.

+

pub fn min_element(self) -> u128[src]

Smallest vector element value.

+

impl u128x2[src]

pub fn and(self) -> u128[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> u128[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> u128[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl u128x2[src]

pub fn from_slice_aligned(slice: &[u128]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[u128]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[u128]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[u128]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl u128x2[src]

pub fn write_to_slice_aligned(self, slice: &mut [u128])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [u128])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [u128])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [u128])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl u128x2[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl u128x2[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl u128x2[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl u128x2[src]

pub fn eq(self, other: Self) -> m128x2[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m128x2[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m128x2[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m128x2[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m128x2[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m128x2[src]

Lane-wise greater-than-or-equals comparison.

+

impl u128x2[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<u128x2>[src]

Returns a wrapper that implements PartialOrd.

+

impl u128x2[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<u128x2>[src]

Returns a wrapper that implements Ord.

+

impl u128x2[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl Add<Simd<[u128; 2]>> for u128x2[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<u128> for u128x2[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[u128; 2]>> for u128x2[src]

impl AddAssign<u128> for u128x2[src]

impl Binary for u128x2[src]

impl BitAnd<Simd<[u128; 2]>> for u128x2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<u128> for u128x2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[u128; 2]>> for u128x2[src]

impl BitAndAssign<u128> for u128x2[src]

impl BitOr<Simd<[u128; 2]>> for u128x2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<u128> for u128x2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[u128; 2]>> for u128x2[src]

impl BitOrAssign<u128> for u128x2[src]

impl BitXor<Simd<[u128; 2]>> for u128x2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<u128> for u128x2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[u128; 2]>> for u128x2[src]

impl BitXorAssign<u128> for u128x2[src]

impl Debug for u128x2[src]

impl Default for u128x2[src]

impl Div<Simd<[u128; 2]>> for u128x2[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<u128> for u128x2[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[u128; 2]>> for u128x2[src]

impl DivAssign<u128> for u128x2[src]

impl Eq for u128x2[src]

impl From<[u128; 2]> for u128x2[src]

impl From<Simd<[u16; 2]>> for u128x2[src]

impl From<Simd<[u32; 2]>> for u128x2[src]

impl From<Simd<[u64; 2]>> for u128x2[src]

impl From<Simd<[u8; 2]>> for u128x2[src]

impl FromBits<Simd<[f32; 8]>> for u128x2[src]

impl FromBits<Simd<[f64; 4]>> for u128x2[src]

impl FromBits<Simd<[i128; 2]>> for u128x2[src]

impl FromBits<Simd<[i16; 16]>> for u128x2[src]

impl FromBits<Simd<[i32; 8]>> for u128x2[src]

impl FromBits<Simd<[i64; 4]>> for u128x2[src]

impl FromBits<Simd<[i8; 32]>> for u128x2[src]

impl FromBits<Simd<[m128; 2]>> for u128x2[src]

impl FromBits<Simd<[m16; 16]>> for u128x2[src]

impl FromBits<Simd<[m32; 8]>> for u128x2[src]

impl FromBits<Simd<[m64; 4]>> for u128x2[src]

impl FromBits<Simd<[m8; 32]>> for u128x2[src]

impl FromBits<Simd<[u16; 16]>> for u128x2[src]

impl FromBits<Simd<[u32; 8]>> for u128x2[src]

impl FromBits<Simd<[u64; 4]>> for u128x2[src]

impl FromBits<Simd<[u8; 32]>> for u128x2[src]

impl FromBits<__m256> for u128x2[src]

impl FromBits<__m256d> for u128x2[src]

impl FromBits<__m256i> for u128x2[src]

impl FromCast<Simd<[f32; 2]>> for u128x2[src]

impl FromCast<Simd<[f64; 2]>> for u128x2[src]

impl FromCast<Simd<[i128; 2]>> for u128x2[src]

impl FromCast<Simd<[i16; 2]>> for u128x2[src]

impl FromCast<Simd<[i32; 2]>> for u128x2[src]

impl FromCast<Simd<[i64; 2]>> for u128x2[src]

impl FromCast<Simd<[i8; 2]>> for u128x2[src]

impl FromCast<Simd<[isize; 2]>> for u128x2[src]

impl FromCast<Simd<[m128; 2]>> for u128x2[src]

impl FromCast<Simd<[m16; 2]>> for u128x2[src]

impl FromCast<Simd<[m32; 2]>> for u128x2[src]

impl FromCast<Simd<[m64; 2]>> for u128x2[src]

impl FromCast<Simd<[m8; 2]>> for u128x2[src]

impl FromCast<Simd<[msize; 2]>> for u128x2[src]

impl FromCast<Simd<[u16; 2]>> for u128x2[src]

impl FromCast<Simd<[u32; 2]>> for u128x2[src]

impl FromCast<Simd<[u64; 2]>> for u128x2[src]

impl FromCast<Simd<[u8; 2]>> for u128x2[src]

impl FromCast<Simd<[usize; 2]>> for u128x2[src]

impl Hash for u128x2[src]

impl LowerHex for u128x2[src]

impl Mul<Simd<[u128; 2]>> for u128x2[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<u128> for u128x2[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[u128; 2]>> for u128x2[src]

impl MulAssign<u128> for u128x2[src]

impl Not for u128x2[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl Octal for u128x2[src]

impl PartialEq<Simd<[u128; 2]>> for u128x2[src]

impl<'a> Product<&'a Simd<[u128; 2]>> for u128x2[src]

impl Product<Simd<[u128; 2]>> for u128x2[src]

impl Rem<Simd<[u128; 2]>> for u128x2[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<u128> for u128x2[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[u128; 2]>> for u128x2[src]

impl RemAssign<u128> for u128x2[src]

impl Shl<Simd<[u128; 2]>> for u128x2[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<u32> for u128x2[src]

type Output = Self

The resulting type after applying the << operator.

+

impl ShlAssign<Simd<[u128; 2]>> for u128x2[src]

impl ShlAssign<u32> for u128x2[src]

impl Shr<Simd<[u128; 2]>> for u128x2[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<u32> for u128x2[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl ShrAssign<Simd<[u128; 2]>> for u128x2[src]

impl ShrAssign<u32> for u128x2[src]

impl Simd for u128x2[src]

type Element = u128

Element type of the SIMD vector

+

type LanesType = [u32; 2]

The type: [u32; Self::N].

+

impl Sub<Simd<[u128; 2]>> for u128x2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<u128> for u128x2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[u128; 2]>> for u128x2[src]

impl SubAssign<u128> for u128x2[src]

impl<'a> Sum<&'a Simd<[u128; 2]>> for u128x2[src]

impl Sum<Simd<[u128; 2]>> for u128x2[src]

impl UpperHex for u128x2[src]

\ No newline at end of file diff --git a/packed_simd/type.u128x4.html b/packed_simd/type.u128x4.html new file mode 100644 index 000000000..bd27f4daa --- /dev/null +++ b/packed_simd/type.u128x4.html @@ -0,0 +1,249 @@ +packed_simd::u128x4 - Rust

[−][src]Type Definition packed_simd::u128x4

type u128x4 = Simd<[u128; 4]>;

A 512-bit vector with 4 u128 lanes.

+

Implementations

impl u128x4[src]

pub const fn new(x0: u128, x1: u128, x2: u128, x3: u128) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: u128) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> u128[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> u128[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: u128) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: u128) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl u128x4[src]

pub fn rotate_left(self, n: u128x4) -> u128x4[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: u128x4) -> u128x4[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl u128x4[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl u128x4[src]

pub fn wrapping_sum(self) -> u128[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> u128[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl u128x4[src]

pub fn max_element(self) -> u128[src]

Largest vector element value.

+

pub fn min_element(self) -> u128[src]

Smallest vector element value.

+

impl u128x4[src]

pub fn and(self) -> u128[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> u128[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> u128[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl u128x4[src]

pub fn from_slice_aligned(slice: &[u128]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[u128]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[u128]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[u128]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl u128x4[src]

pub fn write_to_slice_aligned(self, slice: &mut [u128])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [u128])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [u128])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [u128])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl u128x4[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl u128x4[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl u128x4[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl u128x4[src]

pub fn eq(self, other: Self) -> m128x4[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m128x4[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m128x4[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m128x4[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m128x4[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m128x4[src]

Lane-wise greater-than-or-equals comparison.

+

impl u128x4[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<u128x4>[src]

Returns a wrapper that implements PartialOrd.

+

impl u128x4[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<u128x4>[src]

Returns a wrapper that implements Ord.

+

impl u128x4[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl Add<Simd<[u128; 4]>> for u128x4[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<u128> for u128x4[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[u128; 4]>> for u128x4[src]

impl AddAssign<u128> for u128x4[src]

impl Binary for u128x4[src]

impl BitAnd<Simd<[u128; 4]>> for u128x4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<u128> for u128x4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[u128; 4]>> for u128x4[src]

impl BitAndAssign<u128> for u128x4[src]

impl BitOr<Simd<[u128; 4]>> for u128x4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<u128> for u128x4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[u128; 4]>> for u128x4[src]

impl BitOrAssign<u128> for u128x4[src]

impl BitXor<Simd<[u128; 4]>> for u128x4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<u128> for u128x4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[u128; 4]>> for u128x4[src]

impl BitXorAssign<u128> for u128x4[src]

impl Debug for u128x4[src]

impl Default for u128x4[src]

impl Div<Simd<[u128; 4]>> for u128x4[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<u128> for u128x4[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[u128; 4]>> for u128x4[src]

impl DivAssign<u128> for u128x4[src]

impl Eq for u128x4[src]

impl From<[u128; 4]> for u128x4[src]

impl From<Simd<[u16; 4]>> for u128x4[src]

impl From<Simd<[u32; 4]>> for u128x4[src]

impl From<Simd<[u64; 4]>> for u128x4[src]

impl From<Simd<[u8; 4]>> for u128x4[src]

impl FromBits<Simd<[f32; 16]>> for u128x4[src]

impl FromBits<Simd<[f64; 8]>> for u128x4[src]

impl FromBits<Simd<[i128; 4]>> for u128x4[src]

impl FromBits<Simd<[i16; 32]>> for u128x4[src]

impl FromBits<Simd<[i32; 16]>> for u128x4[src]

impl FromBits<Simd<[i64; 8]>> for u128x4[src]

impl FromBits<Simd<[i8; 64]>> for u128x4[src]

impl FromBits<Simd<[m128; 4]>> for u128x4[src]

impl FromBits<Simd<[m16; 32]>> for u128x4[src]

impl FromBits<Simd<[m32; 16]>> for u128x4[src]

impl FromBits<Simd<[m64; 8]>> for u128x4[src]

impl FromBits<Simd<[m8; 64]>> for u128x4[src]

impl FromBits<Simd<[u16; 32]>> for u128x4[src]

impl FromBits<Simd<[u32; 16]>> for u128x4[src]

impl FromBits<Simd<[u64; 8]>> for u128x4[src]

impl FromBits<Simd<[u8; 64]>> for u128x4[src]

impl FromCast<Simd<[f32; 4]>> for u128x4[src]

impl FromCast<Simd<[f64; 4]>> for u128x4[src]

impl FromCast<Simd<[i128; 4]>> for u128x4[src]

impl FromCast<Simd<[i16; 4]>> for u128x4[src]

impl FromCast<Simd<[i32; 4]>> for u128x4[src]

impl FromCast<Simd<[i64; 4]>> for u128x4[src]

impl FromCast<Simd<[i8; 4]>> for u128x4[src]

impl FromCast<Simd<[isize; 4]>> for u128x4[src]

impl FromCast<Simd<[m128; 4]>> for u128x4[src]

impl FromCast<Simd<[m16; 4]>> for u128x4[src]

impl FromCast<Simd<[m32; 4]>> for u128x4[src]

impl FromCast<Simd<[m64; 4]>> for u128x4[src]

impl FromCast<Simd<[m8; 4]>> for u128x4[src]

impl FromCast<Simd<[msize; 4]>> for u128x4[src]

impl FromCast<Simd<[u16; 4]>> for u128x4[src]

impl FromCast<Simd<[u32; 4]>> for u128x4[src]

impl FromCast<Simd<[u64; 4]>> for u128x4[src]

impl FromCast<Simd<[u8; 4]>> for u128x4[src]

impl FromCast<Simd<[usize; 4]>> for u128x4[src]

impl Hash for u128x4[src]

impl LowerHex for u128x4[src]

impl Mul<Simd<[u128; 4]>> for u128x4[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<u128> for u128x4[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[u128; 4]>> for u128x4[src]

impl MulAssign<u128> for u128x4[src]

impl Not for u128x4[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl Octal for u128x4[src]

impl PartialEq<Simd<[u128; 4]>> for u128x4[src]

impl<'a> Product<&'a Simd<[u128; 4]>> for u128x4[src]

impl Product<Simd<[u128; 4]>> for u128x4[src]

impl Rem<Simd<[u128; 4]>> for u128x4[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<u128> for u128x4[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[u128; 4]>> for u128x4[src]

impl RemAssign<u128> for u128x4[src]

impl Shl<Simd<[u128; 4]>> for u128x4[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<u32> for u128x4[src]

type Output = Self

The resulting type after applying the << operator.

+

impl ShlAssign<Simd<[u128; 4]>> for u128x4[src]

impl ShlAssign<u32> for u128x4[src]

impl Shr<Simd<[u128; 4]>> for u128x4[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<u32> for u128x4[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl ShrAssign<Simd<[u128; 4]>> for u128x4[src]

impl ShrAssign<u32> for u128x4[src]

impl Simd for u128x4[src]

type Element = u128

Element type of the SIMD vector

+

type LanesType = [u32; 4]

The type: [u32; Self::N].

+

impl Sub<Simd<[u128; 4]>> for u128x4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<u128> for u128x4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[u128; 4]>> for u128x4[src]

impl SubAssign<u128> for u128x4[src]

impl<'a> Sum<&'a Simd<[u128; 4]>> for u128x4[src]

impl Sum<Simd<[u128; 4]>> for u128x4[src]

impl UpperHex for u128x4[src]

\ No newline at end of file diff --git a/packed_simd/type.u16x16.html b/packed_simd/type.u16x16.html new file mode 100644 index 000000000..642f43961 --- /dev/null +++ b/packed_simd/type.u16x16.html @@ -0,0 +1,239 @@ +packed_simd::u16x16 - Rust

[−][src]Type Definition packed_simd::u16x16

type u16x16 = Simd<[u16; 16]>;

A 256-bit vector with 16 u16 lanes.

+

Implementations

impl u16x16[src]

pub const fn new(
    x0: u16,
    x1: u16,
    x2: u16,
    x3: u16,
    x4: u16,
    x5: u16,
    x6: u16,
    x7: u16,
    x8: u16,
    x9: u16,
    x10: u16,
    x11: u16,
    x12: u16,
    x13: u16,
    x14: u16,
    x15: u16
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: u16) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> u16[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> u16[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: u16) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: u16) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl u16x16[src]

pub fn rotate_left(self, n: u16x16) -> u16x16[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: u16x16) -> u16x16[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl u16x16[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl u16x16[src]

pub fn wrapping_sum(self) -> u16[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> u16[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl u16x16[src]

pub fn max_element(self) -> u16[src]

Largest vector element value.

+

pub fn min_element(self) -> u16[src]

Smallest vector element value.

+

impl u16x16[src]

pub fn and(self) -> u16[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> u16[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> u16[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl u16x16[src]

pub fn from_slice_aligned(slice: &[u16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[u16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[u16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[u16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl u16x16[src]

pub fn write_to_slice_aligned(self, slice: &mut [u16])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [u16])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [u16])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [u16])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl u16x16[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl u16x16[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl u16x16[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl u16x16[src]

pub fn eq(self, other: Self) -> m16x16[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m16x16[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m16x16[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m16x16[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m16x16[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m16x16[src]

Lane-wise greater-than-or-equals comparison.

+

impl u16x16[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<u16x16>[src]

Returns a wrapper that implements PartialOrd.

+

impl u16x16[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<u16x16>[src]

Returns a wrapper that implements Ord.

+

impl u16x16[src]

pub fn bitmask(self) -> u16[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl Add<Simd<[u16; 16]>> for u16x16[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<u16> for u16x16[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[u16; 16]>> for u16x16[src]

impl AddAssign<u16> for u16x16[src]

impl Binary for u16x16[src]

impl BitAnd<Simd<[u16; 16]>> for u16x16[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<u16> for u16x16[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[u16; 16]>> for u16x16[src]

impl BitAndAssign<u16> for u16x16[src]

impl BitOr<Simd<[u16; 16]>> for u16x16[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<u16> for u16x16[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[u16; 16]>> for u16x16[src]

impl BitOrAssign<u16> for u16x16[src]

impl BitXor<Simd<[u16; 16]>> for u16x16[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<u16> for u16x16[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[u16; 16]>> for u16x16[src]

impl BitXorAssign<u16> for u16x16[src]

impl Debug for u16x16[src]

impl Default for u16x16[src]

impl Div<Simd<[u16; 16]>> for u16x16[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<u16> for u16x16[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[u16; 16]>> for u16x16[src]

impl DivAssign<u16> for u16x16[src]

impl Eq for u16x16[src]

impl From<[u16; 16]> for u16x16[src]

impl From<Simd<[u8; 16]>> for u16x16[src]

impl FromBits<Simd<[f32; 8]>> for u16x16[src]

impl FromBits<Simd<[f64; 4]>> for u16x16[src]

impl FromBits<Simd<[i128; 2]>> for u16x16[src]

impl FromBits<Simd<[i16; 16]>> for u16x16[src]

impl FromBits<Simd<[i32; 8]>> for u16x16[src]

impl FromBits<Simd<[i64; 4]>> for u16x16[src]

impl FromBits<Simd<[i8; 32]>> for u16x16[src]

impl FromBits<Simd<[m128; 2]>> for u16x16[src]

impl FromBits<Simd<[m16; 16]>> for u16x16[src]

impl FromBits<Simd<[m32; 8]>> for u16x16[src]

impl FromBits<Simd<[m64; 4]>> for u16x16[src]

impl FromBits<Simd<[m8; 32]>> for u16x16[src]

impl FromBits<Simd<[u128; 2]>> for u16x16[src]

impl FromBits<Simd<[u32; 8]>> for u16x16[src]

impl FromBits<Simd<[u64; 4]>> for u16x16[src]

impl FromBits<Simd<[u8; 32]>> for u16x16[src]

impl FromBits<__m256> for u16x16[src]

impl FromBits<__m256d> for u16x16[src]

impl FromBits<__m256i> for u16x16[src]

impl FromCast<Simd<[f32; 16]>> for u16x16[src]

impl FromCast<Simd<[i16; 16]>> for u16x16[src]

impl FromCast<Simd<[i32; 16]>> for u16x16[src]

impl FromCast<Simd<[i8; 16]>> for u16x16[src]

impl FromCast<Simd<[m16; 16]>> for u16x16[src]

impl FromCast<Simd<[m32; 16]>> for u16x16[src]

impl FromCast<Simd<[m8; 16]>> for u16x16[src]

impl FromCast<Simd<[u32; 16]>> for u16x16[src]

impl FromCast<Simd<[u8; 16]>> for u16x16[src]

impl Hash for u16x16[src]

impl LowerHex for u16x16[src]

impl Mul<Simd<[u16; 16]>> for u16x16[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<u16> for u16x16[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[u16; 16]>> for u16x16[src]

impl MulAssign<u16> for u16x16[src]

impl Not for u16x16[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl Octal for u16x16[src]

impl PartialEq<Simd<[u16; 16]>> for u16x16[src]

impl<'a> Product<&'a Simd<[u16; 16]>> for u16x16[src]

impl Product<Simd<[u16; 16]>> for u16x16[src]

impl Rem<Simd<[u16; 16]>> for u16x16[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<u16> for u16x16[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[u16; 16]>> for u16x16[src]

impl RemAssign<u16> for u16x16[src]

impl Shl<Simd<[u16; 16]>> for u16x16[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<u32> for u16x16[src]

type Output = Self

The resulting type after applying the << operator.

+

impl ShlAssign<Simd<[u16; 16]>> for u16x16[src]

impl ShlAssign<u32> for u16x16[src]

impl Shr<Simd<[u16; 16]>> for u16x16[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<u32> for u16x16[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl ShrAssign<Simd<[u16; 16]>> for u16x16[src]

impl ShrAssign<u32> for u16x16[src]

impl Simd for u16x16[src]

type Element = u16

Element type of the SIMD vector

+

type LanesType = [u32; 16]

The type: [u32; Self::N].

+

impl Sub<Simd<[u16; 16]>> for u16x16[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<u16> for u16x16[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[u16; 16]>> for u16x16[src]

impl SubAssign<u16> for u16x16[src]

impl<'a> Sum<&'a Simd<[u16; 16]>> for u16x16[src]

impl Sum<Simd<[u16; 16]>> for u16x16[src]

impl UpperHex for u16x16[src]

\ No newline at end of file diff --git a/packed_simd/type.u16x2.html b/packed_simd/type.u16x2.html new file mode 100644 index 000000000..0dace6ddc --- /dev/null +++ b/packed_simd/type.u16x2.html @@ -0,0 +1,235 @@ +packed_simd::u16x2 - Rust

[−][src]Type Definition packed_simd::u16x2

type u16x2 = Simd<[u16; 2]>;

A 32-bit vector with 2 u16 lanes.

+

Implementations

impl u16x2[src]

pub const fn new(x0: u16, x1: u16) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: u16) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> u16[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> u16[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: u16) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: u16) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl u16x2[src]

pub fn rotate_left(self, n: u16x2) -> u16x2[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: u16x2) -> u16x2[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl u16x2[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl u16x2[src]

pub fn wrapping_sum(self) -> u16[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> u16[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl u16x2[src]

pub fn max_element(self) -> u16[src]

Largest vector element value.

+

pub fn min_element(self) -> u16[src]

Smallest vector element value.

+

impl u16x2[src]

pub fn and(self) -> u16[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> u16[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> u16[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl u16x2[src]

pub fn from_slice_aligned(slice: &[u16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[u16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[u16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[u16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl u16x2[src]

pub fn write_to_slice_aligned(self, slice: &mut [u16])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [u16])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [u16])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [u16])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl u16x2[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl u16x2[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl u16x2[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl u16x2[src]

pub fn eq(self, other: Self) -> m16x2[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m16x2[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m16x2[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m16x2[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m16x2[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m16x2[src]

Lane-wise greater-than-or-equals comparison.

+

impl u16x2[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<u16x2>[src]

Returns a wrapper that implements PartialOrd.

+

impl u16x2[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<u16x2>[src]

Returns a wrapper that implements Ord.

+

impl u16x2[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl Add<Simd<[u16; 2]>> for u16x2[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<u16> for u16x2[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[u16; 2]>> for u16x2[src]

impl AddAssign<u16> for u16x2[src]

impl Binary for u16x2[src]

impl BitAnd<Simd<[u16; 2]>> for u16x2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<u16> for u16x2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[u16; 2]>> for u16x2[src]

impl BitAndAssign<u16> for u16x2[src]

impl BitOr<Simd<[u16; 2]>> for u16x2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<u16> for u16x2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[u16; 2]>> for u16x2[src]

impl BitOrAssign<u16> for u16x2[src]

impl BitXor<Simd<[u16; 2]>> for u16x2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<u16> for u16x2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[u16; 2]>> for u16x2[src]

impl BitXorAssign<u16> for u16x2[src]

impl Debug for u16x2[src]

impl Default for u16x2[src]

impl Div<Simd<[u16; 2]>> for u16x2[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<u16> for u16x2[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[u16; 2]>> for u16x2[src]

impl DivAssign<u16> for u16x2[src]

impl Eq for u16x2[src]

impl From<[u16; 2]> for u16x2[src]

impl From<Simd<[u8; 2]>> for u16x2[src]

impl FromBits<Simd<[i16; 2]>> for u16x2[src]

impl FromBits<Simd<[i8; 4]>> for u16x2[src]

impl FromBits<Simd<[m16; 2]>> for u16x2[src]

impl FromBits<Simd<[m8; 4]>> for u16x2[src]

impl FromBits<Simd<[u8; 4]>> for u16x2[src]

impl FromCast<Simd<[f32; 2]>> for u16x2[src]

impl FromCast<Simd<[f64; 2]>> for u16x2[src]

impl FromCast<Simd<[i128; 2]>> for u16x2[src]

impl FromCast<Simd<[i16; 2]>> for u16x2[src]

impl FromCast<Simd<[i32; 2]>> for u16x2[src]

impl FromCast<Simd<[i64; 2]>> for u16x2[src]

impl FromCast<Simd<[i8; 2]>> for u16x2[src]

impl FromCast<Simd<[isize; 2]>> for u16x2[src]

impl FromCast<Simd<[m128; 2]>> for u16x2[src]

impl FromCast<Simd<[m16; 2]>> for u16x2[src]

impl FromCast<Simd<[m32; 2]>> for u16x2[src]

impl FromCast<Simd<[m64; 2]>> for u16x2[src]

impl FromCast<Simd<[m8; 2]>> for u16x2[src]

impl FromCast<Simd<[msize; 2]>> for u16x2[src]

impl FromCast<Simd<[u128; 2]>> for u16x2[src]

impl FromCast<Simd<[u32; 2]>> for u16x2[src]

impl FromCast<Simd<[u64; 2]>> for u16x2[src]

impl FromCast<Simd<[u8; 2]>> for u16x2[src]

impl FromCast<Simd<[usize; 2]>> for u16x2[src]

impl Hash for u16x2[src]

impl LowerHex for u16x2[src]

impl Mul<Simd<[u16; 2]>> for u16x2[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<u16> for u16x2[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[u16; 2]>> for u16x2[src]

impl MulAssign<u16> for u16x2[src]

impl Not for u16x2[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl Octal for u16x2[src]

impl PartialEq<Simd<[u16; 2]>> for u16x2[src]

impl<'a> Product<&'a Simd<[u16; 2]>> for u16x2[src]

impl Product<Simd<[u16; 2]>> for u16x2[src]

impl Rem<Simd<[u16; 2]>> for u16x2[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<u16> for u16x2[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[u16; 2]>> for u16x2[src]

impl RemAssign<u16> for u16x2[src]

impl Shl<Simd<[u16; 2]>> for u16x2[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<u32> for u16x2[src]

type Output = Self

The resulting type after applying the << operator.

+

impl ShlAssign<Simd<[u16; 2]>> for u16x2[src]

impl ShlAssign<u32> for u16x2[src]

impl Shr<Simd<[u16; 2]>> for u16x2[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<u32> for u16x2[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl ShrAssign<Simd<[u16; 2]>> for u16x2[src]

impl ShrAssign<u32> for u16x2[src]

impl Simd for u16x2[src]

type Element = u16

Element type of the SIMD vector

+

type LanesType = [u32; 2]

The type: [u32; Self::N].

+

impl Sub<Simd<[u16; 2]>> for u16x2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<u16> for u16x2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[u16; 2]>> for u16x2[src]

impl SubAssign<u16> for u16x2[src]

impl<'a> Sum<&'a Simd<[u16; 2]>> for u16x2[src]

impl Sum<Simd<[u16; 2]>> for u16x2[src]

impl UpperHex for u16x2[src]

\ No newline at end of file diff --git a/packed_simd/type.u16x32.html b/packed_simd/type.u16x32.html new file mode 100644 index 000000000..342d27fe7 --- /dev/null +++ b/packed_simd/type.u16x32.html @@ -0,0 +1,232 @@ +packed_simd::u16x32 - Rust

[−][src]Type Definition packed_simd::u16x32

type u16x32 = Simd<[u16; 32]>;

A 512-bit vector with 32 u16 lanes.

+

Implementations

impl u16x32[src]

pub const fn new(
    x0: u16,
    x1: u16,
    x2: u16,
    x3: u16,
    x4: u16,
    x5: u16,
    x6: u16,
    x7: u16,
    x8: u16,
    x9: u16,
    x10: u16,
    x11: u16,
    x12: u16,
    x13: u16,
    x14: u16,
    x15: u16,
    x16: u16,
    x17: u16,
    x18: u16,
    x19: u16,
    x20: u16,
    x21: u16,
    x22: u16,
    x23: u16,
    x24: u16,
    x25: u16,
    x26: u16,
    x27: u16,
    x28: u16,
    x29: u16,
    x30: u16,
    x31: u16
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: u16) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> u16[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> u16[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: u16) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: u16) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl u16x32[src]

pub fn rotate_left(self, n: u16x32) -> u16x32[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: u16x32) -> u16x32[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl u16x32[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl u16x32[src]

pub fn wrapping_sum(self) -> u16[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> u16[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl u16x32[src]

pub fn max_element(self) -> u16[src]

Largest vector element value.

+

pub fn min_element(self) -> u16[src]

Smallest vector element value.

+

impl u16x32[src]

pub fn and(self) -> u16[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> u16[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> u16[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl u16x32[src]

pub fn from_slice_aligned(slice: &[u16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[u16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[u16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[u16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl u16x32[src]

pub fn write_to_slice_aligned(self, slice: &mut [u16])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [u16])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [u16])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [u16])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl u16x32[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl u16x32[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl u16x32[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl u16x32[src]

pub fn eq(self, other: Self) -> m16x32[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m16x32[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m16x32[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m16x32[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m16x32[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m16x32[src]

Lane-wise greater-than-or-equals comparison.

+

impl u16x32[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<u16x32>[src]

Returns a wrapper that implements PartialOrd.

+

impl u16x32[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<u16x32>[src]

Returns a wrapper that implements Ord.

+

impl u16x32[src]

pub fn bitmask(self) -> u32[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl Add<Simd<[u16; 32]>> for u16x32[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<u16> for u16x32[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[u16; 32]>> for u16x32[src]

impl AddAssign<u16> for u16x32[src]

impl Binary for u16x32[src]

impl BitAnd<Simd<[u16; 32]>> for u16x32[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<u16> for u16x32[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[u16; 32]>> for u16x32[src]

impl BitAndAssign<u16> for u16x32[src]

impl BitOr<Simd<[u16; 32]>> for u16x32[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<u16> for u16x32[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[u16; 32]>> for u16x32[src]

impl BitOrAssign<u16> for u16x32[src]

impl BitXor<Simd<[u16; 32]>> for u16x32[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<u16> for u16x32[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[u16; 32]>> for u16x32[src]

impl BitXorAssign<u16> for u16x32[src]

impl Debug for u16x32[src]

impl Default for u16x32[src]

impl Div<Simd<[u16; 32]>> for u16x32[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<u16> for u16x32[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[u16; 32]>> for u16x32[src]

impl DivAssign<u16> for u16x32[src]

impl Eq for u16x32[src]

impl From<[u16; 32]> for u16x32[src]

impl From<Simd<[u8; 32]>> for u16x32[src]

impl FromBits<Simd<[f32; 16]>> for u16x32[src]

impl FromBits<Simd<[f64; 8]>> for u16x32[src]

impl FromBits<Simd<[i128; 4]>> for u16x32[src]

impl FromBits<Simd<[i16; 32]>> for u16x32[src]

impl FromBits<Simd<[i32; 16]>> for u16x32[src]

impl FromBits<Simd<[i64; 8]>> for u16x32[src]

impl FromBits<Simd<[i8; 64]>> for u16x32[src]

impl FromBits<Simd<[m128; 4]>> for u16x32[src]

impl FromBits<Simd<[m16; 32]>> for u16x32[src]

impl FromBits<Simd<[m32; 16]>> for u16x32[src]

impl FromBits<Simd<[m64; 8]>> for u16x32[src]

impl FromBits<Simd<[m8; 64]>> for u16x32[src]

impl FromBits<Simd<[u128; 4]>> for u16x32[src]

impl FromBits<Simd<[u32; 16]>> for u16x32[src]

impl FromBits<Simd<[u64; 8]>> for u16x32[src]

impl FromBits<Simd<[u8; 64]>> for u16x32[src]

impl FromCast<Simd<[i16; 32]>> for u16x32[src]

impl FromCast<Simd<[i8; 32]>> for u16x32[src]

impl FromCast<Simd<[m16; 32]>> for u16x32[src]

impl FromCast<Simd<[m8; 32]>> for u16x32[src]

impl FromCast<Simd<[u8; 32]>> for u16x32[src]

impl Hash for u16x32[src]

impl LowerHex for u16x32[src]

impl Mul<Simd<[u16; 32]>> for u16x32[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<u16> for u16x32[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[u16; 32]>> for u16x32[src]

impl MulAssign<u16> for u16x32[src]

impl Not for u16x32[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl Octal for u16x32[src]

impl PartialEq<Simd<[u16; 32]>> for u16x32[src]

impl<'a> Product<&'a Simd<[u16; 32]>> for u16x32[src]

impl Product<Simd<[u16; 32]>> for u16x32[src]

impl Rem<Simd<[u16; 32]>> for u16x32[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<u16> for u16x32[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[u16; 32]>> for u16x32[src]

impl RemAssign<u16> for u16x32[src]

impl Shl<Simd<[u16; 32]>> for u16x32[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<u32> for u16x32[src]

type Output = Self

The resulting type after applying the << operator.

+

impl ShlAssign<Simd<[u16; 32]>> for u16x32[src]

impl ShlAssign<u32> for u16x32[src]

impl Shr<Simd<[u16; 32]>> for u16x32[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<u32> for u16x32[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl ShrAssign<Simd<[u16; 32]>> for u16x32[src]

impl ShrAssign<u32> for u16x32[src]

impl Simd for u16x32[src]

type Element = u16

Element type of the SIMD vector

+

type LanesType = [u32; 32]

The type: [u32; Self::N].

+

impl Sub<Simd<[u16; 32]>> for u16x32[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<u16> for u16x32[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[u16; 32]>> for u16x32[src]

impl SubAssign<u16> for u16x32[src]

impl<'a> Sum<&'a Simd<[u16; 32]>> for u16x32[src]

impl Sum<Simd<[u16; 32]>> for u16x32[src]

impl UpperHex for u16x32[src]

\ No newline at end of file diff --git a/packed_simd/type.u16x4.html b/packed_simd/type.u16x4.html new file mode 100644 index 000000000..e13d9704f --- /dev/null +++ b/packed_simd/type.u16x4.html @@ -0,0 +1,240 @@ +packed_simd::u16x4 - Rust

[−][src]Type Definition packed_simd::u16x4

type u16x4 = Simd<[u16; 4]>;

A 64-bit vector with 4 u16 lanes.

+

Implementations

impl u16x4[src]

pub const fn new(x0: u16, x1: u16, x2: u16, x3: u16) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: u16) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> u16[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> u16[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: u16) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: u16) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl u16x4[src]

pub fn rotate_left(self, n: u16x4) -> u16x4[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: u16x4) -> u16x4[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl u16x4[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl u16x4[src]

pub fn wrapping_sum(self) -> u16[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> u16[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl u16x4[src]

pub fn max_element(self) -> u16[src]

Largest vector element value.

+

pub fn min_element(self) -> u16[src]

Smallest vector element value.

+

impl u16x4[src]

pub fn and(self) -> u16[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> u16[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> u16[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl u16x4[src]

pub fn from_slice_aligned(slice: &[u16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[u16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[u16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[u16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl u16x4[src]

pub fn write_to_slice_aligned(self, slice: &mut [u16])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [u16])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [u16])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [u16])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl u16x4[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl u16x4[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl u16x4[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl u16x4[src]

pub fn eq(self, other: Self) -> m16x4[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m16x4[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m16x4[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m16x4[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m16x4[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m16x4[src]

Lane-wise greater-than-or-equals comparison.

+

impl u16x4[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<u16x4>[src]

Returns a wrapper that implements PartialOrd.

+

impl u16x4[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<u16x4>[src]

Returns a wrapper that implements Ord.

+

impl u16x4[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl Add<Simd<[u16; 4]>> for u16x4[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<u16> for u16x4[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[u16; 4]>> for u16x4[src]

impl AddAssign<u16> for u16x4[src]

impl Binary for u16x4[src]

impl BitAnd<Simd<[u16; 4]>> for u16x4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<u16> for u16x4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[u16; 4]>> for u16x4[src]

impl BitAndAssign<u16> for u16x4[src]

impl BitOr<Simd<[u16; 4]>> for u16x4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<u16> for u16x4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[u16; 4]>> for u16x4[src]

impl BitOrAssign<u16> for u16x4[src]

impl BitXor<Simd<[u16; 4]>> for u16x4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<u16> for u16x4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[u16; 4]>> for u16x4[src]

impl BitXorAssign<u16> for u16x4[src]

impl Debug for u16x4[src]

impl Default for u16x4[src]

impl Div<Simd<[u16; 4]>> for u16x4[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<u16> for u16x4[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[u16; 4]>> for u16x4[src]

impl DivAssign<u16> for u16x4[src]

impl Eq for u16x4[src]

impl From<[u16; 4]> for u16x4[src]

impl From<Simd<[u8; 4]>> for u16x4[src]

impl FromBits<Simd<[f32; 2]>> for u16x4[src]

impl FromBits<Simd<[i16; 4]>> for u16x4[src]

impl FromBits<Simd<[i32; 2]>> for u16x4[src]

impl FromBits<Simd<[i8; 8]>> for u16x4[src]

impl FromBits<Simd<[m16; 4]>> for u16x4[src]

impl FromBits<Simd<[m32; 2]>> for u16x4[src]

impl FromBits<Simd<[m8; 8]>> for u16x4[src]

impl FromBits<Simd<[u32; 2]>> for u16x4[src]

impl FromBits<Simd<[u8; 8]>> for u16x4[src]

impl FromBits<__m64> for u16x4[src]

impl FromCast<Simd<[f32; 4]>> for u16x4[src]

impl FromCast<Simd<[f64; 4]>> for u16x4[src]

impl FromCast<Simd<[i128; 4]>> for u16x4[src]

impl FromCast<Simd<[i16; 4]>> for u16x4[src]

impl FromCast<Simd<[i32; 4]>> for u16x4[src]

impl FromCast<Simd<[i64; 4]>> for u16x4[src]

impl FromCast<Simd<[i8; 4]>> for u16x4[src]

impl FromCast<Simd<[isize; 4]>> for u16x4[src]

impl FromCast<Simd<[m128; 4]>> for u16x4[src]

impl FromCast<Simd<[m16; 4]>> for u16x4[src]

impl FromCast<Simd<[m32; 4]>> for u16x4[src]

impl FromCast<Simd<[m64; 4]>> for u16x4[src]

impl FromCast<Simd<[m8; 4]>> for u16x4[src]

impl FromCast<Simd<[msize; 4]>> for u16x4[src]

impl FromCast<Simd<[u128; 4]>> for u16x4[src]

impl FromCast<Simd<[u32; 4]>> for u16x4[src]

impl FromCast<Simd<[u64; 4]>> for u16x4[src]

impl FromCast<Simd<[u8; 4]>> for u16x4[src]

impl FromCast<Simd<[usize; 4]>> for u16x4[src]

impl Hash for u16x4[src]

impl LowerHex for u16x4[src]

impl Mul<Simd<[u16; 4]>> for u16x4[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<u16> for u16x4[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[u16; 4]>> for u16x4[src]

impl MulAssign<u16> for u16x4[src]

impl Not for u16x4[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl Octal for u16x4[src]

impl PartialEq<Simd<[u16; 4]>> for u16x4[src]

impl<'a> Product<&'a Simd<[u16; 4]>> for u16x4[src]

impl Product<Simd<[u16; 4]>> for u16x4[src]

impl Rem<Simd<[u16; 4]>> for u16x4[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<u16> for u16x4[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[u16; 4]>> for u16x4[src]

impl RemAssign<u16> for u16x4[src]

impl Shl<Simd<[u16; 4]>> for u16x4[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<u32> for u16x4[src]

type Output = Self

The resulting type after applying the << operator.

+

impl ShlAssign<Simd<[u16; 4]>> for u16x4[src]

impl ShlAssign<u32> for u16x4[src]

impl Shr<Simd<[u16; 4]>> for u16x4[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<u32> for u16x4[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl ShrAssign<Simd<[u16; 4]>> for u16x4[src]

impl ShrAssign<u32> for u16x4[src]

impl Simd for u16x4[src]

type Element = u16

Element type of the SIMD vector

+

type LanesType = [u32; 4]

The type: [u32; Self::N].

+

impl Sub<Simd<[u16; 4]>> for u16x4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<u16> for u16x4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[u16; 4]>> for u16x4[src]

impl SubAssign<u16> for u16x4[src]

impl<'a> Sum<&'a Simd<[u16; 4]>> for u16x4[src]

impl Sum<Simd<[u16; 4]>> for u16x4[src]

impl UpperHex for u16x4[src]

\ No newline at end of file diff --git a/packed_simd/type.u16x8.html b/packed_simd/type.u16x8.html new file mode 100644 index 000000000..53ad0e3c3 --- /dev/null +++ b/packed_simd/type.u16x8.html @@ -0,0 +1,246 @@ +packed_simd::u16x8 - Rust

[−][src]Type Definition packed_simd::u16x8

type u16x8 = Simd<[u16; 8]>;

A 128-bit vector with 8 u16 lanes.

+

Implementations

impl u16x8[src]

pub const fn new(
    x0: u16,
    x1: u16,
    x2: u16,
    x3: u16,
    x4: u16,
    x5: u16,
    x6: u16,
    x7: u16
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: u16) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> u16[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> u16[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: u16) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: u16) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl u16x8[src]

pub fn rotate_left(self, n: u16x8) -> u16x8[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: u16x8) -> u16x8[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl u16x8[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl u16x8[src]

pub fn wrapping_sum(self) -> u16[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> u16[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl u16x8[src]

pub fn max_element(self) -> u16[src]

Largest vector element value.

+

pub fn min_element(self) -> u16[src]

Smallest vector element value.

+

impl u16x8[src]

pub fn and(self) -> u16[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> u16[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> u16[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl u16x8[src]

pub fn from_slice_aligned(slice: &[u16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[u16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[u16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[u16]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl u16x8[src]

pub fn write_to_slice_aligned(self, slice: &mut [u16])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [u16])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [u16])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [u16])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl u16x8[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl u16x8[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl u16x8[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl u16x8[src]

pub fn eq(self, other: Self) -> m16x8[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m16x8[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m16x8[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m16x8[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m16x8[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m16x8[src]

Lane-wise greater-than-or-equals comparison.

+

impl u16x8[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<u16x8>[src]

Returns a wrapper that implements PartialOrd.

+

impl u16x8[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<u16x8>[src]

Returns a wrapper that implements Ord.

+

impl u16x8[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl Add<Simd<[u16; 8]>> for u16x8[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<u16> for u16x8[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[u16; 8]>> for u16x8[src]

impl AddAssign<u16> for u16x8[src]

impl Binary for u16x8[src]

impl BitAnd<Simd<[u16; 8]>> for u16x8[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<u16> for u16x8[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[u16; 8]>> for u16x8[src]

impl BitAndAssign<u16> for u16x8[src]

impl BitOr<Simd<[u16; 8]>> for u16x8[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<u16> for u16x8[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[u16; 8]>> for u16x8[src]

impl BitOrAssign<u16> for u16x8[src]

impl BitXor<Simd<[u16; 8]>> for u16x8[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<u16> for u16x8[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[u16; 8]>> for u16x8[src]

impl BitXorAssign<u16> for u16x8[src]

impl Debug for u16x8[src]

impl Default for u16x8[src]

impl Div<Simd<[u16; 8]>> for u16x8[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<u16> for u16x8[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[u16; 8]>> for u16x8[src]

impl DivAssign<u16> for u16x8[src]

impl Eq for u16x8[src]

impl From<[u16; 8]> for u16x8[src]

impl From<Simd<[u8; 8]>> for u16x8[src]

impl FromBits<Simd<[f32; 4]>> for u16x8[src]

impl FromBits<Simd<[f64; 2]>> for u16x8[src]

impl FromBits<Simd<[i128; 1]>> for u16x8[src]

impl FromBits<Simd<[i16; 8]>> for u16x8[src]

impl FromBits<Simd<[i32; 4]>> for u16x8[src]

impl FromBits<Simd<[i64; 2]>> for u16x8[src]

impl FromBits<Simd<[i8; 16]>> for u16x8[src]

impl FromBits<Simd<[m128; 1]>> for u16x8[src]

impl FromBits<Simd<[m16; 8]>> for u16x8[src]

impl FromBits<Simd<[m32; 4]>> for u16x8[src]

impl FromBits<Simd<[m64; 2]>> for u16x8[src]

impl FromBits<Simd<[m8; 16]>> for u16x8[src]

impl FromBits<Simd<[u128; 1]>> for u16x8[src]

impl FromBits<Simd<[u32; 4]>> for u16x8[src]

impl FromBits<Simd<[u64; 2]>> for u16x8[src]

impl FromBits<Simd<[u8; 16]>> for u16x8[src]

impl FromBits<__m128> for u16x8[src]

impl FromBits<__m128d> for u16x8[src]

impl FromBits<__m128i> for u16x8[src]

impl FromCast<Simd<[f32; 8]>> for u16x8[src]

impl FromCast<Simd<[f64; 8]>> for u16x8[src]

impl FromCast<Simd<[i16; 8]>> for u16x8[src]

impl FromCast<Simd<[i32; 8]>> for u16x8[src]

impl FromCast<Simd<[i64; 8]>> for u16x8[src]

impl FromCast<Simd<[i8; 8]>> for u16x8[src]

impl FromCast<Simd<[isize; 8]>> for u16x8[src]

impl FromCast<Simd<[m16; 8]>> for u16x8[src]

impl FromCast<Simd<[m32; 8]>> for u16x8[src]

impl FromCast<Simd<[m64; 8]>> for u16x8[src]

impl FromCast<Simd<[m8; 8]>> for u16x8[src]

impl FromCast<Simd<[msize; 8]>> for u16x8[src]

impl FromCast<Simd<[u32; 8]>> for u16x8[src]

impl FromCast<Simd<[u64; 8]>> for u16x8[src]

impl FromCast<Simd<[u8; 8]>> for u16x8[src]

impl FromCast<Simd<[usize; 8]>> for u16x8[src]

impl Hash for u16x8[src]

impl LowerHex for u16x8[src]

impl Mul<Simd<[u16; 8]>> for u16x8[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<u16> for u16x8[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[u16; 8]>> for u16x8[src]

impl MulAssign<u16> for u16x8[src]

impl Not for u16x8[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl Octal for u16x8[src]

impl PartialEq<Simd<[u16; 8]>> for u16x8[src]

impl<'a> Product<&'a Simd<[u16; 8]>> for u16x8[src]

impl Product<Simd<[u16; 8]>> for u16x8[src]

impl Rem<Simd<[u16; 8]>> for u16x8[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<u16> for u16x8[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[u16; 8]>> for u16x8[src]

impl RemAssign<u16> for u16x8[src]

impl Shl<Simd<[u16; 8]>> for u16x8[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<u32> for u16x8[src]

type Output = Self

The resulting type after applying the << operator.

+

impl ShlAssign<Simd<[u16; 8]>> for u16x8[src]

impl ShlAssign<u32> for u16x8[src]

impl Shr<Simd<[u16; 8]>> for u16x8[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<u32> for u16x8[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl ShrAssign<Simd<[u16; 8]>> for u16x8[src]

impl ShrAssign<u32> for u16x8[src]

impl Simd for u16x8[src]

type Element = u16

Element type of the SIMD vector

+

type LanesType = [u32; 8]

The type: [u32; Self::N].

+

impl Sub<Simd<[u16; 8]>> for u16x8[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<u16> for u16x8[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[u16; 8]>> for u16x8[src]

impl SubAssign<u16> for u16x8[src]

impl<'a> Sum<&'a Simd<[u16; 8]>> for u16x8[src]

impl Sum<Simd<[u16; 8]>> for u16x8[src]

impl UpperHex for u16x8[src]

\ No newline at end of file diff --git a/packed_simd/type.u32x16.html b/packed_simd/type.u32x16.html new file mode 100644 index 000000000..3fff4c769 --- /dev/null +++ b/packed_simd/type.u32x16.html @@ -0,0 +1,237 @@ +packed_simd::u32x16 - Rust

[−][src]Type Definition packed_simd::u32x16

type u32x16 = Simd<[u32; 16]>;

A 512-bit vector with 16 u32 lanes.

+

Implementations

impl u32x16[src]

pub const fn new(
    x0: u32,
    x1: u32,
    x2: u32,
    x3: u32,
    x4: u32,
    x5: u32,
    x6: u32,
    x7: u32,
    x8: u32,
    x9: u32,
    x10: u32,
    x11: u32,
    x12: u32,
    x13: u32,
    x14: u32,
    x15: u32
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: u32) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> u32[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> u32[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: u32) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: u32) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl u32x16[src]

pub fn rotate_left(self, n: u32x16) -> u32x16[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: u32x16) -> u32x16[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl u32x16[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl u32x16[src]

pub fn wrapping_sum(self) -> u32[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> u32[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl u32x16[src]

pub fn max_element(self) -> u32[src]

Largest vector element value.

+

pub fn min_element(self) -> u32[src]

Smallest vector element value.

+

impl u32x16[src]

pub fn and(self) -> u32[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> u32[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> u32[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl u32x16[src]

pub fn from_slice_aligned(slice: &[u32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[u32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[u32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[u32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl u32x16[src]

pub fn write_to_slice_aligned(self, slice: &mut [u32])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [u32])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [u32])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [u32])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl u32x16[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl u32x16[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl u32x16[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl u32x16[src]

pub fn eq(self, other: Self) -> m32x16[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m32x16[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m32x16[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m32x16[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m32x16[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m32x16[src]

Lane-wise greater-than-or-equals comparison.

+

impl u32x16[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<u32x16>[src]

Returns a wrapper that implements PartialOrd.

+

impl u32x16[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<u32x16>[src]

Returns a wrapper that implements Ord.

+

impl u32x16[src]

pub fn bitmask(self) -> u16[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl Add<Simd<[u32; 16]>> for u32x16[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<u32> for u32x16[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[u32; 16]>> for u32x16[src]

impl AddAssign<u32> for u32x16[src]

impl Binary for u32x16[src]

impl BitAnd<Simd<[u32; 16]>> for u32x16[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<u32> for u32x16[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[u32; 16]>> for u32x16[src]

impl BitAndAssign<u32> for u32x16[src]

impl BitOr<Simd<[u32; 16]>> for u32x16[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<u32> for u32x16[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[u32; 16]>> for u32x16[src]

impl BitOrAssign<u32> for u32x16[src]

impl BitXor<Simd<[u32; 16]>> for u32x16[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<u32> for u32x16[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[u32; 16]>> for u32x16[src]

impl BitXorAssign<u32> for u32x16[src]

impl Debug for u32x16[src]

impl Default for u32x16[src]

impl Div<Simd<[u32; 16]>> for u32x16[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<u32> for u32x16[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[u32; 16]>> for u32x16[src]

impl DivAssign<u32> for u32x16[src]

impl Eq for u32x16[src]

impl From<[u32; 16]> for u32x16[src]

impl From<Simd<[u16; 16]>> for u32x16[src]

impl From<Simd<[u8; 16]>> for u32x16[src]

impl FromBits<Simd<[f32; 16]>> for u32x16[src]

impl FromBits<Simd<[f64; 8]>> for u32x16[src]

impl FromBits<Simd<[i128; 4]>> for u32x16[src]

impl FromBits<Simd<[i16; 32]>> for u32x16[src]

impl FromBits<Simd<[i32; 16]>> for u32x16[src]

impl FromBits<Simd<[i64; 8]>> for u32x16[src]

impl FromBits<Simd<[i8; 64]>> for u32x16[src]

impl FromBits<Simd<[m128; 4]>> for u32x16[src]

impl FromBits<Simd<[m16; 32]>> for u32x16[src]

impl FromBits<Simd<[m32; 16]>> for u32x16[src]

impl FromBits<Simd<[m64; 8]>> for u32x16[src]

impl FromBits<Simd<[m8; 64]>> for u32x16[src]

impl FromBits<Simd<[u128; 4]>> for u32x16[src]

impl FromBits<Simd<[u16; 32]>> for u32x16[src]

impl FromBits<Simd<[u64; 8]>> for u32x16[src]

impl FromBits<Simd<[u8; 64]>> for u32x16[src]

impl FromCast<Simd<[f32; 16]>> for u32x16[src]

impl FromCast<Simd<[i16; 16]>> for u32x16[src]

impl FromCast<Simd<[i32; 16]>> for u32x16[src]

impl FromCast<Simd<[i8; 16]>> for u32x16[src]

impl FromCast<Simd<[m16; 16]>> for u32x16[src]

impl FromCast<Simd<[m32; 16]>> for u32x16[src]

impl FromCast<Simd<[m8; 16]>> for u32x16[src]

impl FromCast<Simd<[u16; 16]>> for u32x16[src]

impl FromCast<Simd<[u8; 16]>> for u32x16[src]

impl Hash for u32x16[src]

impl LowerHex for u32x16[src]

impl Mul<Simd<[u32; 16]>> for u32x16[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<u32> for u32x16[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[u32; 16]>> for u32x16[src]

impl MulAssign<u32> for u32x16[src]

impl Not for u32x16[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl Octal for u32x16[src]

impl PartialEq<Simd<[u32; 16]>> for u32x16[src]

impl<'a> Product<&'a Simd<[u32; 16]>> for u32x16[src]

impl Product<Simd<[u32; 16]>> for u32x16[src]

impl Rem<Simd<[u32; 16]>> for u32x16[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<u32> for u32x16[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[u32; 16]>> for u32x16[src]

impl RemAssign<u32> for u32x16[src]

impl Shl<Simd<[u32; 16]>> for u32x16[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<u32> for u32x16[src]

type Output = Self

The resulting type after applying the << operator.

+

impl ShlAssign<Simd<[u32; 16]>> for u32x16[src]

impl ShlAssign<u32> for u32x16[src]

impl Shr<Simd<[u32; 16]>> for u32x16[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<u32> for u32x16[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl ShrAssign<Simd<[u32; 16]>> for u32x16[src]

impl ShrAssign<u32> for u32x16[src]

impl Simd for u32x16[src]

type Element = u32

Element type of the SIMD vector

+

type LanesType = [u32; 16]

The type: [u32; Self::N].

+

impl Sub<Simd<[u32; 16]>> for u32x16[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<u32> for u32x16[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[u32; 16]>> for u32x16[src]

impl SubAssign<u32> for u32x16[src]

impl<'a> Sum<&'a Simd<[u32; 16]>> for u32x16[src]

impl Sum<Simd<[u32; 16]>> for u32x16[src]

impl UpperHex for u32x16[src]

\ No newline at end of file diff --git a/packed_simd/type.u32x2.html b/packed_simd/type.u32x2.html new file mode 100644 index 000000000..a9488319a --- /dev/null +++ b/packed_simd/type.u32x2.html @@ -0,0 +1,241 @@ +packed_simd::u32x2 - Rust

[−][src]Type Definition packed_simd::u32x2

type u32x2 = Simd<[u32; 2]>;

A 64-bit vector with 2 u32 lanes.

+

Implementations

impl u32x2[src]

pub const fn new(x0: u32, x1: u32) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: u32) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> u32[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> u32[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: u32) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: u32) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl u32x2[src]

pub fn rotate_left(self, n: u32x2) -> u32x2[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: u32x2) -> u32x2[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl u32x2[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl u32x2[src]

pub fn wrapping_sum(self) -> u32[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> u32[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl u32x2[src]

pub fn max_element(self) -> u32[src]

Largest vector element value.

+

pub fn min_element(self) -> u32[src]

Smallest vector element value.

+

impl u32x2[src]

pub fn and(self) -> u32[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> u32[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> u32[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl u32x2[src]

pub fn from_slice_aligned(slice: &[u32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[u32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[u32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[u32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl u32x2[src]

pub fn write_to_slice_aligned(self, slice: &mut [u32])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [u32])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [u32])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [u32])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl u32x2[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl u32x2[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl u32x2[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl u32x2[src]

pub fn eq(self, other: Self) -> m32x2[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m32x2[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m32x2[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m32x2[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m32x2[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m32x2[src]

Lane-wise greater-than-or-equals comparison.

+

impl u32x2[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<u32x2>[src]

Returns a wrapper that implements PartialOrd.

+

impl u32x2[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<u32x2>[src]

Returns a wrapper that implements Ord.

+

impl u32x2[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl Add<Simd<[u32; 2]>> for u32x2[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<u32> for u32x2[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[u32; 2]>> for u32x2[src]

impl AddAssign<u32> for u32x2[src]

impl Binary for u32x2[src]

impl BitAnd<Simd<[u32; 2]>> for u32x2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<u32> for u32x2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[u32; 2]>> for u32x2[src]

impl BitAndAssign<u32> for u32x2[src]

impl BitOr<Simd<[u32; 2]>> for u32x2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<u32> for u32x2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[u32; 2]>> for u32x2[src]

impl BitOrAssign<u32> for u32x2[src]

impl BitXor<Simd<[u32; 2]>> for u32x2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<u32> for u32x2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[u32; 2]>> for u32x2[src]

impl BitXorAssign<u32> for u32x2[src]

impl Debug for u32x2[src]

impl Default for u32x2[src]

impl Div<Simd<[u32; 2]>> for u32x2[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<u32> for u32x2[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[u32; 2]>> for u32x2[src]

impl DivAssign<u32> for u32x2[src]

impl Eq for u32x2[src]

impl From<[u32; 2]> for u32x2[src]

impl From<Simd<[u16; 2]>> for u32x2[src]

impl From<Simd<[u8; 2]>> for u32x2[src]

impl FromBits<Simd<[f32; 2]>> for u32x2[src]

impl FromBits<Simd<[i16; 4]>> for u32x2[src]

impl FromBits<Simd<[i32; 2]>> for u32x2[src]

impl FromBits<Simd<[i8; 8]>> for u32x2[src]

impl FromBits<Simd<[m16; 4]>> for u32x2[src]

impl FromBits<Simd<[m32; 2]>> for u32x2[src]

impl FromBits<Simd<[m8; 8]>> for u32x2[src]

impl FromBits<Simd<[u16; 4]>> for u32x2[src]

impl FromBits<Simd<[u8; 8]>> for u32x2[src]

impl FromBits<__m64> for u32x2[src]

impl FromCast<Simd<[f32; 2]>> for u32x2[src]

impl FromCast<Simd<[f64; 2]>> for u32x2[src]

impl FromCast<Simd<[i128; 2]>> for u32x2[src]

impl FromCast<Simd<[i16; 2]>> for u32x2[src]

impl FromCast<Simd<[i32; 2]>> for u32x2[src]

impl FromCast<Simd<[i64; 2]>> for u32x2[src]

impl FromCast<Simd<[i8; 2]>> for u32x2[src]

impl FromCast<Simd<[isize; 2]>> for u32x2[src]

impl FromCast<Simd<[m128; 2]>> for u32x2[src]

impl FromCast<Simd<[m16; 2]>> for u32x2[src]

impl FromCast<Simd<[m32; 2]>> for u32x2[src]

impl FromCast<Simd<[m64; 2]>> for u32x2[src]

impl FromCast<Simd<[m8; 2]>> for u32x2[src]

impl FromCast<Simd<[msize; 2]>> for u32x2[src]

impl FromCast<Simd<[u128; 2]>> for u32x2[src]

impl FromCast<Simd<[u16; 2]>> for u32x2[src]

impl FromCast<Simd<[u64; 2]>> for u32x2[src]

impl FromCast<Simd<[u8; 2]>> for u32x2[src]

impl FromCast<Simd<[usize; 2]>> for u32x2[src]

impl Hash for u32x2[src]

impl LowerHex for u32x2[src]

impl Mul<Simd<[u32; 2]>> for u32x2[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<u32> for u32x2[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[u32; 2]>> for u32x2[src]

impl MulAssign<u32> for u32x2[src]

impl Not for u32x2[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl Octal for u32x2[src]

impl PartialEq<Simd<[u32; 2]>> for u32x2[src]

impl<'a> Product<&'a Simd<[u32; 2]>> for u32x2[src]

impl Product<Simd<[u32; 2]>> for u32x2[src]

impl Rem<Simd<[u32; 2]>> for u32x2[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<u32> for u32x2[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[u32; 2]>> for u32x2[src]

impl RemAssign<u32> for u32x2[src]

impl Shl<Simd<[u32; 2]>> for u32x2[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<u32> for u32x2[src]

type Output = Self

The resulting type after applying the << operator.

+

impl ShlAssign<Simd<[u32; 2]>> for u32x2[src]

impl ShlAssign<u32> for u32x2[src]

impl Shr<Simd<[u32; 2]>> for u32x2[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<u32> for u32x2[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl ShrAssign<Simd<[u32; 2]>> for u32x2[src]

impl ShrAssign<u32> for u32x2[src]

impl Simd for u32x2[src]

type Element = u32

Element type of the SIMD vector

+

type LanesType = [u32; 2]

The type: [u32; Self::N].

+

impl Sub<Simd<[u32; 2]>> for u32x2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<u32> for u32x2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[u32; 2]>> for u32x2[src]

impl SubAssign<u32> for u32x2[src]

impl<'a> Sum<&'a Simd<[u32; 2]>> for u32x2[src]

impl Sum<Simd<[u32; 2]>> for u32x2[src]

impl UpperHex for u32x2[src]

\ No newline at end of file diff --git a/packed_simd/type.u32x4.html b/packed_simd/type.u32x4.html new file mode 100644 index 000000000..2aff0b829 --- /dev/null +++ b/packed_simd/type.u32x4.html @@ -0,0 +1,250 @@ +packed_simd::u32x4 - Rust

[−][src]Type Definition packed_simd::u32x4

type u32x4 = Simd<[u32; 4]>;

A 128-bit vector with 4 u32 lanes.

+

Implementations

impl u32x4[src]

pub const fn new(x0: u32, x1: u32, x2: u32, x3: u32) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: u32) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> u32[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> u32[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: u32) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: u32) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl u32x4[src]

pub fn rotate_left(self, n: u32x4) -> u32x4[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: u32x4) -> u32x4[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl u32x4[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl u32x4[src]

pub fn wrapping_sum(self) -> u32[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> u32[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl u32x4[src]

pub fn max_element(self) -> u32[src]

Largest vector element value.

+

pub fn min_element(self) -> u32[src]

Smallest vector element value.

+

impl u32x4[src]

pub fn and(self) -> u32[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> u32[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> u32[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl u32x4[src]

pub fn from_slice_aligned(slice: &[u32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[u32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[u32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[u32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl u32x4[src]

pub fn write_to_slice_aligned(self, slice: &mut [u32])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [u32])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [u32])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [u32])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl u32x4[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl u32x4[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl u32x4[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl u32x4[src]

pub fn eq(self, other: Self) -> m32x4[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m32x4[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m32x4[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m32x4[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m32x4[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m32x4[src]

Lane-wise greater-than-or-equals comparison.

+

impl u32x4[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<u32x4>[src]

Returns a wrapper that implements PartialOrd.

+

impl u32x4[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<u32x4>[src]

Returns a wrapper that implements Ord.

+

impl u32x4[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl Add<Simd<[u32; 4]>> for u32x4[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<u32> for u32x4[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[u32; 4]>> for u32x4[src]

impl AddAssign<u32> for u32x4[src]

impl Binary for u32x4[src]

impl BitAnd<Simd<[u32; 4]>> for u32x4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<u32> for u32x4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[u32; 4]>> for u32x4[src]

impl BitAndAssign<u32> for u32x4[src]

impl BitOr<Simd<[u32; 4]>> for u32x4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<u32> for u32x4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[u32; 4]>> for u32x4[src]

impl BitOrAssign<u32> for u32x4[src]

impl BitXor<Simd<[u32; 4]>> for u32x4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<u32> for u32x4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[u32; 4]>> for u32x4[src]

impl BitXorAssign<u32> for u32x4[src]

impl Debug for u32x4[src]

impl Default for u32x4[src]

impl Div<Simd<[u32; 4]>> for u32x4[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<u32> for u32x4[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[u32; 4]>> for u32x4[src]

impl DivAssign<u32> for u32x4[src]

impl Eq for u32x4[src]

impl From<[u32; 4]> for u32x4[src]

impl From<Simd<[u16; 4]>> for u32x4[src]

impl From<Simd<[u8; 4]>> for u32x4[src]

impl FromBits<Simd<[f32; 4]>> for u32x4[src]

impl FromBits<Simd<[f64; 2]>> for u32x4[src]

impl FromBits<Simd<[i128; 1]>> for u32x4[src]

impl FromBits<Simd<[i16; 8]>> for u32x4[src]

impl FromBits<Simd<[i32; 4]>> for u32x4[src]

impl FromBits<Simd<[i64; 2]>> for u32x4[src]

impl FromBits<Simd<[i8; 16]>> for u32x4[src]

impl FromBits<Simd<[m128; 1]>> for u32x4[src]

impl FromBits<Simd<[m16; 8]>> for u32x4[src]

impl FromBits<Simd<[m32; 4]>> for u32x4[src]

impl FromBits<Simd<[m64; 2]>> for u32x4[src]

impl FromBits<Simd<[m8; 16]>> for u32x4[src]

impl FromBits<Simd<[u128; 1]>> for u32x4[src]

impl FromBits<Simd<[u16; 8]>> for u32x4[src]

impl FromBits<Simd<[u64; 2]>> for u32x4[src]

impl FromBits<Simd<[u8; 16]>> for u32x4[src]

impl FromBits<__m128> for u32x4[src]

impl FromBits<__m128d> for u32x4[src]

impl FromBits<__m128i> for u32x4[src]

impl FromCast<Simd<[f32; 4]>> for u32x4[src]

impl FromCast<Simd<[f64; 4]>> for u32x4[src]

impl FromCast<Simd<[i128; 4]>> for u32x4[src]

impl FromCast<Simd<[i16; 4]>> for u32x4[src]

impl FromCast<Simd<[i32; 4]>> for u32x4[src]

impl FromCast<Simd<[i64; 4]>> for u32x4[src]

impl FromCast<Simd<[i8; 4]>> for u32x4[src]

impl FromCast<Simd<[isize; 4]>> for u32x4[src]

impl FromCast<Simd<[m128; 4]>> for u32x4[src]

impl FromCast<Simd<[m16; 4]>> for u32x4[src]

impl FromCast<Simd<[m32; 4]>> for u32x4[src]

impl FromCast<Simd<[m64; 4]>> for u32x4[src]

impl FromCast<Simd<[m8; 4]>> for u32x4[src]

impl FromCast<Simd<[msize; 4]>> for u32x4[src]

impl FromCast<Simd<[u128; 4]>> for u32x4[src]

impl FromCast<Simd<[u16; 4]>> for u32x4[src]

impl FromCast<Simd<[u64; 4]>> for u32x4[src]

impl FromCast<Simd<[u8; 4]>> for u32x4[src]

impl FromCast<Simd<[usize; 4]>> for u32x4[src]

impl Hash for u32x4[src]

impl LowerHex for u32x4[src]

impl Mul<Simd<[u32; 4]>> for u32x4[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<u32> for u32x4[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[u32; 4]>> for u32x4[src]

impl MulAssign<u32> for u32x4[src]

impl Not for u32x4[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl Octal for u32x4[src]

impl PartialEq<Simd<[u32; 4]>> for u32x4[src]

impl<'a> Product<&'a Simd<[u32; 4]>> for u32x4[src]

impl Product<Simd<[u32; 4]>> for u32x4[src]

impl Rem<Simd<[u32; 4]>> for u32x4[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<u32> for u32x4[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[u32; 4]>> for u32x4[src]

impl RemAssign<u32> for u32x4[src]

impl Shl<Simd<[u32; 4]>> for u32x4[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<u32> for u32x4[src]

type Output = Self

The resulting type after applying the << operator.

+

impl ShlAssign<Simd<[u32; 4]>> for u32x4[src]

impl ShlAssign<u32> for u32x4[src]

impl Shr<Simd<[u32; 4]>> for u32x4[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<u32> for u32x4[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl ShrAssign<Simd<[u32; 4]>> for u32x4[src]

impl ShrAssign<u32> for u32x4[src]

impl Simd for u32x4[src]

type Element = u32

Element type of the SIMD vector

+

type LanesType = [u32; 4]

The type: [u32; Self::N].

+

impl Sub<Simd<[u32; 4]>> for u32x4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<u32> for u32x4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[u32; 4]>> for u32x4[src]

impl SubAssign<u32> for u32x4[src]

impl<'a> Sum<&'a Simd<[u32; 4]>> for u32x4[src]

impl Sum<Simd<[u32; 4]>> for u32x4[src]

impl UpperHex for u32x4[src]

\ No newline at end of file diff --git a/packed_simd/type.u32x8.html b/packed_simd/type.u32x8.html new file mode 100644 index 000000000..de99a3cb5 --- /dev/null +++ b/packed_simd/type.u32x8.html @@ -0,0 +1,247 @@ +packed_simd::u32x8 - Rust

[−][src]Type Definition packed_simd::u32x8

type u32x8 = Simd<[u32; 8]>;

A 256-bit vector with 8 u32 lanes.

+

Implementations

impl u32x8[src]

pub const fn new(
    x0: u32,
    x1: u32,
    x2: u32,
    x3: u32,
    x4: u32,
    x5: u32,
    x6: u32,
    x7: u32
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: u32) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> u32[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> u32[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: u32) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: u32) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl u32x8[src]

pub fn rotate_left(self, n: u32x8) -> u32x8[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: u32x8) -> u32x8[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl u32x8[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl u32x8[src]

pub fn wrapping_sum(self) -> u32[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> u32[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl u32x8[src]

pub fn max_element(self) -> u32[src]

Largest vector element value.

+

pub fn min_element(self) -> u32[src]

Smallest vector element value.

+

impl u32x8[src]

pub fn and(self) -> u32[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> u32[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> u32[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl u32x8[src]

pub fn from_slice_aligned(slice: &[u32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[u32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[u32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[u32]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl u32x8[src]

pub fn write_to_slice_aligned(self, slice: &mut [u32])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [u32])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [u32])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [u32])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl u32x8[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl u32x8[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl u32x8[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl u32x8[src]

pub fn eq(self, other: Self) -> m32x8[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m32x8[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m32x8[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m32x8[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m32x8[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m32x8[src]

Lane-wise greater-than-or-equals comparison.

+

impl u32x8[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<u32x8>[src]

Returns a wrapper that implements PartialOrd.

+

impl u32x8[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<u32x8>[src]

Returns a wrapper that implements Ord.

+

impl u32x8[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl Add<Simd<[u32; 8]>> for u32x8[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<u32> for u32x8[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[u32; 8]>> for u32x8[src]

impl AddAssign<u32> for u32x8[src]

impl Binary for u32x8[src]

impl BitAnd<Simd<[u32; 8]>> for u32x8[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<u32> for u32x8[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[u32; 8]>> for u32x8[src]

impl BitAndAssign<u32> for u32x8[src]

impl BitOr<Simd<[u32; 8]>> for u32x8[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<u32> for u32x8[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[u32; 8]>> for u32x8[src]

impl BitOrAssign<u32> for u32x8[src]

impl BitXor<Simd<[u32; 8]>> for u32x8[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<u32> for u32x8[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[u32; 8]>> for u32x8[src]

impl BitXorAssign<u32> for u32x8[src]

impl Debug for u32x8[src]

impl Default for u32x8[src]

impl Div<Simd<[u32; 8]>> for u32x8[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<u32> for u32x8[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[u32; 8]>> for u32x8[src]

impl DivAssign<u32> for u32x8[src]

impl Eq for u32x8[src]

impl From<[u32; 8]> for u32x8[src]

impl From<Simd<[u16; 8]>> for u32x8[src]

impl From<Simd<[u8; 8]>> for u32x8[src]

impl FromBits<Simd<[f32; 8]>> for u32x8[src]

impl FromBits<Simd<[f64; 4]>> for u32x8[src]

impl FromBits<Simd<[i128; 2]>> for u32x8[src]

impl FromBits<Simd<[i16; 16]>> for u32x8[src]

impl FromBits<Simd<[i32; 8]>> for u32x8[src]

impl FromBits<Simd<[i64; 4]>> for u32x8[src]

impl FromBits<Simd<[i8; 32]>> for u32x8[src]

impl FromBits<Simd<[m128; 2]>> for u32x8[src]

impl FromBits<Simd<[m16; 16]>> for u32x8[src]

impl FromBits<Simd<[m32; 8]>> for u32x8[src]

impl FromBits<Simd<[m64; 4]>> for u32x8[src]

impl FromBits<Simd<[m8; 32]>> for u32x8[src]

impl FromBits<Simd<[u128; 2]>> for u32x8[src]

impl FromBits<Simd<[u16; 16]>> for u32x8[src]

impl FromBits<Simd<[u64; 4]>> for u32x8[src]

impl FromBits<Simd<[u8; 32]>> for u32x8[src]

impl FromBits<__m256> for u32x8[src]

impl FromBits<__m256d> for u32x8[src]

impl FromBits<__m256i> for u32x8[src]

impl FromCast<Simd<[f32; 8]>> for u32x8[src]

impl FromCast<Simd<[f64; 8]>> for u32x8[src]

impl FromCast<Simd<[i16; 8]>> for u32x8[src]

impl FromCast<Simd<[i32; 8]>> for u32x8[src]

impl FromCast<Simd<[i64; 8]>> for u32x8[src]

impl FromCast<Simd<[i8; 8]>> for u32x8[src]

impl FromCast<Simd<[isize; 8]>> for u32x8[src]

impl FromCast<Simd<[m16; 8]>> for u32x8[src]

impl FromCast<Simd<[m32; 8]>> for u32x8[src]

impl FromCast<Simd<[m64; 8]>> for u32x8[src]

impl FromCast<Simd<[m8; 8]>> for u32x8[src]

impl FromCast<Simd<[msize; 8]>> for u32x8[src]

impl FromCast<Simd<[u16; 8]>> for u32x8[src]

impl FromCast<Simd<[u64; 8]>> for u32x8[src]

impl FromCast<Simd<[u8; 8]>> for u32x8[src]

impl FromCast<Simd<[usize; 8]>> for u32x8[src]

impl Hash for u32x8[src]

impl LowerHex for u32x8[src]

impl Mul<Simd<[u32; 8]>> for u32x8[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<u32> for u32x8[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[u32; 8]>> for u32x8[src]

impl MulAssign<u32> for u32x8[src]

impl Not for u32x8[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl Octal for u32x8[src]

impl PartialEq<Simd<[u32; 8]>> for u32x8[src]

impl<'a> Product<&'a Simd<[u32; 8]>> for u32x8[src]

impl Product<Simd<[u32; 8]>> for u32x8[src]

impl Rem<Simd<[u32; 8]>> for u32x8[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<u32> for u32x8[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[u32; 8]>> for u32x8[src]

impl RemAssign<u32> for u32x8[src]

impl Shl<Simd<[u32; 8]>> for u32x8[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<u32> for u32x8[src]

type Output = Self

The resulting type after applying the << operator.

+

impl ShlAssign<Simd<[u32; 8]>> for u32x8[src]

impl ShlAssign<u32> for u32x8[src]

impl Shr<Simd<[u32; 8]>> for u32x8[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<u32> for u32x8[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl ShrAssign<Simd<[u32; 8]>> for u32x8[src]

impl ShrAssign<u32> for u32x8[src]

impl Simd for u32x8[src]

type Element = u32

Element type of the SIMD vector

+

type LanesType = [u32; 8]

The type: [u32; Self::N].

+

impl Sub<Simd<[u32; 8]>> for u32x8[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<u32> for u32x8[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[u32; 8]>> for u32x8[src]

impl SubAssign<u32> for u32x8[src]

impl<'a> Sum<&'a Simd<[u32; 8]>> for u32x8[src]

impl Sum<Simd<[u32; 8]>> for u32x8[src]

impl UpperHex for u32x8[src]

\ No newline at end of file diff --git a/packed_simd/type.u64x2.html b/packed_simd/type.u64x2.html new file mode 100644 index 000000000..f69667423 --- /dev/null +++ b/packed_simd/type.u64x2.html @@ -0,0 +1,251 @@ +packed_simd::u64x2 - Rust

[−][src]Type Definition packed_simd::u64x2

type u64x2 = Simd<[u64; 2]>;

A 128-bit vector with 2 u64 lanes.

+

Implementations

impl u64x2[src]

pub const fn new(x0: u64, x1: u64) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: u64) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> u64[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> u64[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: u64) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: u64) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl u64x2[src]

pub fn rotate_left(self, n: u64x2) -> u64x2[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: u64x2) -> u64x2[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl u64x2[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl u64x2[src]

pub fn wrapping_sum(self) -> u64[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> u64[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl u64x2[src]

pub fn max_element(self) -> u64[src]

Largest vector element value.

+

pub fn min_element(self) -> u64[src]

Smallest vector element value.

+

impl u64x2[src]

pub fn and(self) -> u64[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> u64[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> u64[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl u64x2[src]

pub fn from_slice_aligned(slice: &[u64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[u64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[u64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[u64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl u64x2[src]

pub fn write_to_slice_aligned(self, slice: &mut [u64])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [u64])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [u64])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [u64])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl u64x2[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl u64x2[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl u64x2[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl u64x2[src]

pub fn eq(self, other: Self) -> m64x2[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m64x2[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m64x2[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m64x2[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m64x2[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m64x2[src]

Lane-wise greater-than-or-equals comparison.

+

impl u64x2[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<u64x2>[src]

Returns a wrapper that implements PartialOrd.

+

impl u64x2[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<u64x2>[src]

Returns a wrapper that implements Ord.

+

impl u64x2[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl Add<Simd<[u64; 2]>> for u64x2[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<u64> for u64x2[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[u64; 2]>> for u64x2[src]

impl AddAssign<u64> for u64x2[src]

impl Binary for u64x2[src]

impl BitAnd<Simd<[u64; 2]>> for u64x2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<u64> for u64x2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[u64; 2]>> for u64x2[src]

impl BitAndAssign<u64> for u64x2[src]

impl BitOr<Simd<[u64; 2]>> for u64x2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<u64> for u64x2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[u64; 2]>> for u64x2[src]

impl BitOrAssign<u64> for u64x2[src]

impl BitXor<Simd<[u64; 2]>> for u64x2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<u64> for u64x2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[u64; 2]>> for u64x2[src]

impl BitXorAssign<u64> for u64x2[src]

impl Debug for u64x2[src]

impl Default for u64x2[src]

impl Div<Simd<[u64; 2]>> for u64x2[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<u64> for u64x2[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[u64; 2]>> for u64x2[src]

impl DivAssign<u64> for u64x2[src]

impl Eq for u64x2[src]

impl From<[u64; 2]> for u64x2[src]

impl From<Simd<[u16; 2]>> for u64x2[src]

impl From<Simd<[u32; 2]>> for u64x2[src]

impl From<Simd<[u8; 2]>> for u64x2[src]

impl FromBits<Simd<[f32; 4]>> for u64x2[src]

impl FromBits<Simd<[f64; 2]>> for u64x2[src]

impl FromBits<Simd<[i128; 1]>> for u64x2[src]

impl FromBits<Simd<[i16; 8]>> for u64x2[src]

impl FromBits<Simd<[i32; 4]>> for u64x2[src]

impl FromBits<Simd<[i64; 2]>> for u64x2[src]

impl FromBits<Simd<[i8; 16]>> for u64x2[src]

impl FromBits<Simd<[m128; 1]>> for u64x2[src]

impl FromBits<Simd<[m16; 8]>> for u64x2[src]

impl FromBits<Simd<[m32; 4]>> for u64x2[src]

impl FromBits<Simd<[m64; 2]>> for u64x2[src]

impl FromBits<Simd<[m8; 16]>> for u64x2[src]

impl FromBits<Simd<[u128; 1]>> for u64x2[src]

impl FromBits<Simd<[u16; 8]>> for u64x2[src]

impl FromBits<Simd<[u32; 4]>> for u64x2[src]

impl FromBits<Simd<[u8; 16]>> for u64x2[src]

impl FromBits<__m128> for u64x2[src]

impl FromBits<__m128d> for u64x2[src]

impl FromBits<__m128i> for u64x2[src]

impl FromCast<Simd<[f32; 2]>> for u64x2[src]

impl FromCast<Simd<[f64; 2]>> for u64x2[src]

impl FromCast<Simd<[i128; 2]>> for u64x2[src]

impl FromCast<Simd<[i16; 2]>> for u64x2[src]

impl FromCast<Simd<[i32; 2]>> for u64x2[src]

impl FromCast<Simd<[i64; 2]>> for u64x2[src]

impl FromCast<Simd<[i8; 2]>> for u64x2[src]

impl FromCast<Simd<[isize; 2]>> for u64x2[src]

impl FromCast<Simd<[m128; 2]>> for u64x2[src]

impl FromCast<Simd<[m16; 2]>> for u64x2[src]

impl FromCast<Simd<[m32; 2]>> for u64x2[src]

impl FromCast<Simd<[m64; 2]>> for u64x2[src]

impl FromCast<Simd<[m8; 2]>> for u64x2[src]

impl FromCast<Simd<[msize; 2]>> for u64x2[src]

impl FromCast<Simd<[u128; 2]>> for u64x2[src]

impl FromCast<Simd<[u16; 2]>> for u64x2[src]

impl FromCast<Simd<[u32; 2]>> for u64x2[src]

impl FromCast<Simd<[u8; 2]>> for u64x2[src]

impl FromCast<Simd<[usize; 2]>> for u64x2[src]

impl Hash for u64x2[src]

impl LowerHex for u64x2[src]

impl Mul<Simd<[u64; 2]>> for u64x2[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<u64> for u64x2[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[u64; 2]>> for u64x2[src]

impl MulAssign<u64> for u64x2[src]

impl Not for u64x2[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl Octal for u64x2[src]

impl PartialEq<Simd<[u64; 2]>> for u64x2[src]

impl<'a> Product<&'a Simd<[u64; 2]>> for u64x2[src]

impl Product<Simd<[u64; 2]>> for u64x2[src]

impl Rem<Simd<[u64; 2]>> for u64x2[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<u64> for u64x2[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[u64; 2]>> for u64x2[src]

impl RemAssign<u64> for u64x2[src]

impl Shl<Simd<[u64; 2]>> for u64x2[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<u32> for u64x2[src]

type Output = Self

The resulting type after applying the << operator.

+

impl ShlAssign<Simd<[u64; 2]>> for u64x2[src]

impl ShlAssign<u32> for u64x2[src]

impl Shr<Simd<[u64; 2]>> for u64x2[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<u32> for u64x2[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl ShrAssign<Simd<[u64; 2]>> for u64x2[src]

impl ShrAssign<u32> for u64x2[src]

impl Simd for u64x2[src]

type Element = u64

Element type of the SIMD vector

+

type LanesType = [u32; 2]

The type: [u32; Self::N].

+

impl Sub<Simd<[u64; 2]>> for u64x2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<u64> for u64x2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[u64; 2]>> for u64x2[src]

impl SubAssign<u64> for u64x2[src]

impl<'a> Sum<&'a Simd<[u64; 2]>> for u64x2[src]

impl Sum<Simd<[u64; 2]>> for u64x2[src]

impl UpperHex for u64x2[src]

\ No newline at end of file diff --git a/packed_simd/type.u64x4.html b/packed_simd/type.u64x4.html new file mode 100644 index 000000000..9fedfeb3d --- /dev/null +++ b/packed_simd/type.u64x4.html @@ -0,0 +1,251 @@ +packed_simd::u64x4 - Rust

[−][src]Type Definition packed_simd::u64x4

type u64x4 = Simd<[u64; 4]>;

A 256-bit vector with 4 u64 lanes.

+

Implementations

impl u64x4[src]

pub const fn new(x0: u64, x1: u64, x2: u64, x3: u64) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: u64) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> u64[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> u64[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: u64) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: u64) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl u64x4[src]

pub fn rotate_left(self, n: u64x4) -> u64x4[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: u64x4) -> u64x4[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl u64x4[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl u64x4[src]

pub fn wrapping_sum(self) -> u64[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> u64[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl u64x4[src]

pub fn max_element(self) -> u64[src]

Largest vector element value.

+

pub fn min_element(self) -> u64[src]

Smallest vector element value.

+

impl u64x4[src]

pub fn and(self) -> u64[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> u64[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> u64[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl u64x4[src]

pub fn from_slice_aligned(slice: &[u64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[u64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[u64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[u64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl u64x4[src]

pub fn write_to_slice_aligned(self, slice: &mut [u64])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [u64])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [u64])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [u64])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl u64x4[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl u64x4[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl u64x4[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl u64x4[src]

pub fn eq(self, other: Self) -> m64x4[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m64x4[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m64x4[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m64x4[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m64x4[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m64x4[src]

Lane-wise greater-than-or-equals comparison.

+

impl u64x4[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<u64x4>[src]

Returns a wrapper that implements PartialOrd.

+

impl u64x4[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<u64x4>[src]

Returns a wrapper that implements Ord.

+

impl u64x4[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl Add<Simd<[u64; 4]>> for u64x4[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<u64> for u64x4[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[u64; 4]>> for u64x4[src]

impl AddAssign<u64> for u64x4[src]

impl Binary for u64x4[src]

impl BitAnd<Simd<[u64; 4]>> for u64x4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<u64> for u64x4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[u64; 4]>> for u64x4[src]

impl BitAndAssign<u64> for u64x4[src]

impl BitOr<Simd<[u64; 4]>> for u64x4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<u64> for u64x4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[u64; 4]>> for u64x4[src]

impl BitOrAssign<u64> for u64x4[src]

impl BitXor<Simd<[u64; 4]>> for u64x4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<u64> for u64x4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[u64; 4]>> for u64x4[src]

impl BitXorAssign<u64> for u64x4[src]

impl Debug for u64x4[src]

impl Default for u64x4[src]

impl Div<Simd<[u64; 4]>> for u64x4[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<u64> for u64x4[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[u64; 4]>> for u64x4[src]

impl DivAssign<u64> for u64x4[src]

impl Eq for u64x4[src]

impl From<[u64; 4]> for u64x4[src]

impl From<Simd<[u16; 4]>> for u64x4[src]

impl From<Simd<[u32; 4]>> for u64x4[src]

impl From<Simd<[u8; 4]>> for u64x4[src]

impl FromBits<Simd<[f32; 8]>> for u64x4[src]

impl FromBits<Simd<[f64; 4]>> for u64x4[src]

impl FromBits<Simd<[i128; 2]>> for u64x4[src]

impl FromBits<Simd<[i16; 16]>> for u64x4[src]

impl FromBits<Simd<[i32; 8]>> for u64x4[src]

impl FromBits<Simd<[i64; 4]>> for u64x4[src]

impl FromBits<Simd<[i8; 32]>> for u64x4[src]

impl FromBits<Simd<[m128; 2]>> for u64x4[src]

impl FromBits<Simd<[m16; 16]>> for u64x4[src]

impl FromBits<Simd<[m32; 8]>> for u64x4[src]

impl FromBits<Simd<[m64; 4]>> for u64x4[src]

impl FromBits<Simd<[m8; 32]>> for u64x4[src]

impl FromBits<Simd<[u128; 2]>> for u64x4[src]

impl FromBits<Simd<[u16; 16]>> for u64x4[src]

impl FromBits<Simd<[u32; 8]>> for u64x4[src]

impl FromBits<Simd<[u8; 32]>> for u64x4[src]

impl FromBits<__m256> for u64x4[src]

impl FromBits<__m256d> for u64x4[src]

impl FromBits<__m256i> for u64x4[src]

impl FromCast<Simd<[f32; 4]>> for u64x4[src]

impl FromCast<Simd<[f64; 4]>> for u64x4[src]

impl FromCast<Simd<[i128; 4]>> for u64x4[src]

impl FromCast<Simd<[i16; 4]>> for u64x4[src]

impl FromCast<Simd<[i32; 4]>> for u64x4[src]

impl FromCast<Simd<[i64; 4]>> for u64x4[src]

impl FromCast<Simd<[i8; 4]>> for u64x4[src]

impl FromCast<Simd<[isize; 4]>> for u64x4[src]

impl FromCast<Simd<[m128; 4]>> for u64x4[src]

impl FromCast<Simd<[m16; 4]>> for u64x4[src]

impl FromCast<Simd<[m32; 4]>> for u64x4[src]

impl FromCast<Simd<[m64; 4]>> for u64x4[src]

impl FromCast<Simd<[m8; 4]>> for u64x4[src]

impl FromCast<Simd<[msize; 4]>> for u64x4[src]

impl FromCast<Simd<[u128; 4]>> for u64x4[src]

impl FromCast<Simd<[u16; 4]>> for u64x4[src]

impl FromCast<Simd<[u32; 4]>> for u64x4[src]

impl FromCast<Simd<[u8; 4]>> for u64x4[src]

impl FromCast<Simd<[usize; 4]>> for u64x4[src]

impl Hash for u64x4[src]

impl LowerHex for u64x4[src]

impl Mul<Simd<[u64; 4]>> for u64x4[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<u64> for u64x4[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[u64; 4]>> for u64x4[src]

impl MulAssign<u64> for u64x4[src]

impl Not for u64x4[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl Octal for u64x4[src]

impl PartialEq<Simd<[u64; 4]>> for u64x4[src]

impl<'a> Product<&'a Simd<[u64; 4]>> for u64x4[src]

impl Product<Simd<[u64; 4]>> for u64x4[src]

impl Rem<Simd<[u64; 4]>> for u64x4[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<u64> for u64x4[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[u64; 4]>> for u64x4[src]

impl RemAssign<u64> for u64x4[src]

impl Shl<Simd<[u64; 4]>> for u64x4[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<u32> for u64x4[src]

type Output = Self

The resulting type after applying the << operator.

+

impl ShlAssign<Simd<[u64; 4]>> for u64x4[src]

impl ShlAssign<u32> for u64x4[src]

impl Shr<Simd<[u64; 4]>> for u64x4[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<u32> for u64x4[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl ShrAssign<Simd<[u64; 4]>> for u64x4[src]

impl ShrAssign<u32> for u64x4[src]

impl Simd for u64x4[src]

type Element = u64

Element type of the SIMD vector

+

type LanesType = [u32; 4]

The type: [u32; Self::N].

+

impl Sub<Simd<[u64; 4]>> for u64x4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<u64> for u64x4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[u64; 4]>> for u64x4[src]

impl SubAssign<u64> for u64x4[src]

impl<'a> Sum<&'a Simd<[u64; 4]>> for u64x4[src]

impl Sum<Simd<[u64; 4]>> for u64x4[src]

impl UpperHex for u64x4[src]

\ No newline at end of file diff --git a/packed_simd/type.u64x8.html b/packed_simd/type.u64x8.html new file mode 100644 index 000000000..3444a7fd1 --- /dev/null +++ b/packed_simd/type.u64x8.html @@ -0,0 +1,245 @@ +packed_simd::u64x8 - Rust

[−][src]Type Definition packed_simd::u64x8

type u64x8 = Simd<[u64; 8]>;

A 512-bit vector with 8 u64 lanes.

+

Implementations

impl u64x8[src]

pub const fn new(
    x0: u64,
    x1: u64,
    x2: u64,
    x3: u64,
    x4: u64,
    x5: u64,
    x6: u64,
    x7: u64
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: u64) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> u64[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> u64[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: u64) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: u64) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl u64x8[src]

pub fn rotate_left(self, n: u64x8) -> u64x8[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: u64x8) -> u64x8[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl u64x8[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl u64x8[src]

pub fn wrapping_sum(self) -> u64[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> u64[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl u64x8[src]

pub fn max_element(self) -> u64[src]

Largest vector element value.

+

pub fn min_element(self) -> u64[src]

Smallest vector element value.

+

impl u64x8[src]

pub fn and(self) -> u64[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> u64[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> u64[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl u64x8[src]

pub fn from_slice_aligned(slice: &[u64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[u64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[u64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[u64]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl u64x8[src]

pub fn write_to_slice_aligned(self, slice: &mut [u64])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [u64])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [u64])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [u64])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl u64x8[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl u64x8[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl u64x8[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl u64x8[src]

pub fn eq(self, other: Self) -> m64x8[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m64x8[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m64x8[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m64x8[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m64x8[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m64x8[src]

Lane-wise greater-than-or-equals comparison.

+

impl u64x8[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<u64x8>[src]

Returns a wrapper that implements PartialOrd.

+

impl u64x8[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<u64x8>[src]

Returns a wrapper that implements Ord.

+

impl u64x8[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl Add<Simd<[u64; 8]>> for u64x8[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<u64> for u64x8[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[u64; 8]>> for u64x8[src]

impl AddAssign<u64> for u64x8[src]

impl Binary for u64x8[src]

impl BitAnd<Simd<[u64; 8]>> for u64x8[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<u64> for u64x8[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[u64; 8]>> for u64x8[src]

impl BitAndAssign<u64> for u64x8[src]

impl BitOr<Simd<[u64; 8]>> for u64x8[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<u64> for u64x8[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[u64; 8]>> for u64x8[src]

impl BitOrAssign<u64> for u64x8[src]

impl BitXor<Simd<[u64; 8]>> for u64x8[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<u64> for u64x8[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[u64; 8]>> for u64x8[src]

impl BitXorAssign<u64> for u64x8[src]

impl Debug for u64x8[src]

impl Default for u64x8[src]

impl Div<Simd<[u64; 8]>> for u64x8[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<u64> for u64x8[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[u64; 8]>> for u64x8[src]

impl DivAssign<u64> for u64x8[src]

impl Eq for u64x8[src]

impl From<[u64; 8]> for u64x8[src]

impl From<Simd<[u16; 8]>> for u64x8[src]

impl From<Simd<[u32; 8]>> for u64x8[src]

impl From<Simd<[u8; 8]>> for u64x8[src]

impl FromBits<Simd<[f32; 16]>> for u64x8[src]

impl FromBits<Simd<[f64; 8]>> for u64x8[src]

impl FromBits<Simd<[i128; 4]>> for u64x8[src]

impl FromBits<Simd<[i16; 32]>> for u64x8[src]

impl FromBits<Simd<[i32; 16]>> for u64x8[src]

impl FromBits<Simd<[i64; 8]>> for u64x8[src]

impl FromBits<Simd<[i8; 64]>> for u64x8[src]

impl FromBits<Simd<[m128; 4]>> for u64x8[src]

impl FromBits<Simd<[m16; 32]>> for u64x8[src]

impl FromBits<Simd<[m32; 16]>> for u64x8[src]

impl FromBits<Simd<[m64; 8]>> for u64x8[src]

impl FromBits<Simd<[m8; 64]>> for u64x8[src]

impl FromBits<Simd<[u128; 4]>> for u64x8[src]

impl FromBits<Simd<[u16; 32]>> for u64x8[src]

impl FromBits<Simd<[u32; 16]>> for u64x8[src]

impl FromBits<Simd<[u8; 64]>> for u64x8[src]

impl FromCast<Simd<[f32; 8]>> for u64x8[src]

impl FromCast<Simd<[f64; 8]>> for u64x8[src]

impl FromCast<Simd<[i16; 8]>> for u64x8[src]

impl FromCast<Simd<[i32; 8]>> for u64x8[src]

impl FromCast<Simd<[i64; 8]>> for u64x8[src]

impl FromCast<Simd<[i8; 8]>> for u64x8[src]

impl FromCast<Simd<[isize; 8]>> for u64x8[src]

impl FromCast<Simd<[m16; 8]>> for u64x8[src]

impl FromCast<Simd<[m32; 8]>> for u64x8[src]

impl FromCast<Simd<[m64; 8]>> for u64x8[src]

impl FromCast<Simd<[m8; 8]>> for u64x8[src]

impl FromCast<Simd<[msize; 8]>> for u64x8[src]

impl FromCast<Simd<[u16; 8]>> for u64x8[src]

impl FromCast<Simd<[u32; 8]>> for u64x8[src]

impl FromCast<Simd<[u8; 8]>> for u64x8[src]

impl FromCast<Simd<[usize; 8]>> for u64x8[src]

impl Hash for u64x8[src]

impl LowerHex for u64x8[src]

impl Mul<Simd<[u64; 8]>> for u64x8[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<u64> for u64x8[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[u64; 8]>> for u64x8[src]

impl MulAssign<u64> for u64x8[src]

impl Not for u64x8[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl Octal for u64x8[src]

impl PartialEq<Simd<[u64; 8]>> for u64x8[src]

impl<'a> Product<&'a Simd<[u64; 8]>> for u64x8[src]

impl Product<Simd<[u64; 8]>> for u64x8[src]

impl Rem<Simd<[u64; 8]>> for u64x8[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<u64> for u64x8[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[u64; 8]>> for u64x8[src]

impl RemAssign<u64> for u64x8[src]

impl Shl<Simd<[u64; 8]>> for u64x8[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<u32> for u64x8[src]

type Output = Self

The resulting type after applying the << operator.

+

impl ShlAssign<Simd<[u64; 8]>> for u64x8[src]

impl ShlAssign<u32> for u64x8[src]

impl Shr<Simd<[u64; 8]>> for u64x8[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<u32> for u64x8[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl ShrAssign<Simd<[u64; 8]>> for u64x8[src]

impl ShrAssign<u32> for u64x8[src]

impl Simd for u64x8[src]

type Element = u64

Element type of the SIMD vector

+

type LanesType = [u32; 8]

The type: [u32; Self::N].

+

impl Sub<Simd<[u64; 8]>> for u64x8[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<u64> for u64x8[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[u64; 8]>> for u64x8[src]

impl SubAssign<u64> for u64x8[src]

impl<'a> Sum<&'a Simd<[u64; 8]>> for u64x8[src]

impl Sum<Simd<[u64; 8]>> for u64x8[src]

impl UpperHex for u64x8[src]

\ No newline at end of file diff --git a/packed_simd/type.u8x16.html b/packed_simd/type.u8x16.html new file mode 100644 index 000000000..d2095efa2 --- /dev/null +++ b/packed_simd/type.u8x16.html @@ -0,0 +1,238 @@ +packed_simd::u8x16 - Rust

[−][src]Type Definition packed_simd::u8x16

type u8x16 = Simd<[u8; 16]>;

A 128-bit vector with 16 u8 lanes.

+

Implementations

impl u8x16[src]

pub const fn new(
    x0: u8,
    x1: u8,
    x2: u8,
    x3: u8,
    x4: u8,
    x5: u8,
    x6: u8,
    x7: u8,
    x8: u8,
    x9: u8,
    x10: u8,
    x11: u8,
    x12: u8,
    x13: u8,
    x14: u8,
    x15: u8
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: u8) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> u8[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> u8[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: u8) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: u8) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl u8x16[src]

pub fn rotate_left(self, n: u8x16) -> u8x16[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: u8x16) -> u8x16[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl u8x16[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl u8x16[src]

pub fn wrapping_sum(self) -> u8[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> u8[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl u8x16[src]

pub fn max_element(self) -> u8[src]

Largest vector element value.

+

pub fn min_element(self) -> u8[src]

Smallest vector element value.

+

impl u8x16[src]

pub fn and(self) -> u8[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> u8[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> u8[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl u8x16[src]

pub fn from_slice_aligned(slice: &[u8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[u8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[u8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[u8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl u8x16[src]

pub fn write_to_slice_aligned(self, slice: &mut [u8])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [u8])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [u8])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [u8])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl u8x16[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl u8x16[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl u8x16[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl u8x16[src]

pub fn eq(self, other: Self) -> m8x16[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m8x16[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m8x16[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m8x16[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m8x16[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m8x16[src]

Lane-wise greater-than-or-equals comparison.

+

impl u8x16[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<u8x16>[src]

Returns a wrapper that implements PartialOrd.

+

impl u8x16[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<u8x16>[src]

Returns a wrapper that implements Ord.

+

impl u8x16[src]

pub fn bitmask(self) -> u16[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl Add<Simd<[u8; 16]>> for u8x16[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<u8> for u8x16[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[u8; 16]>> for u8x16[src]

impl AddAssign<u8> for u8x16[src]

impl Binary for u8x16[src]

impl BitAnd<Simd<[u8; 16]>> for u8x16[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<u8> for u8x16[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[u8; 16]>> for u8x16[src]

impl BitAndAssign<u8> for u8x16[src]

impl BitOr<Simd<[u8; 16]>> for u8x16[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<u8> for u8x16[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[u8; 16]>> for u8x16[src]

impl BitOrAssign<u8> for u8x16[src]

impl BitXor<Simd<[u8; 16]>> for u8x16[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<u8> for u8x16[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[u8; 16]>> for u8x16[src]

impl BitXorAssign<u8> for u8x16[src]

impl Debug for u8x16[src]

impl Default for u8x16[src]

impl Div<Simd<[u8; 16]>> for u8x16[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<u8> for u8x16[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[u8; 16]>> for u8x16[src]

impl DivAssign<u8> for u8x16[src]

impl Eq for u8x16[src]

impl From<[u8; 16]> for u8x16[src]

impl FromBits<Simd<[f32; 4]>> for u8x16[src]

impl FromBits<Simd<[f64; 2]>> for u8x16[src]

impl FromBits<Simd<[i128; 1]>> for u8x16[src]

impl FromBits<Simd<[i16; 8]>> for u8x16[src]

impl FromBits<Simd<[i32; 4]>> for u8x16[src]

impl FromBits<Simd<[i64; 2]>> for u8x16[src]

impl FromBits<Simd<[i8; 16]>> for u8x16[src]

impl FromBits<Simd<[m128; 1]>> for u8x16[src]

impl FromBits<Simd<[m16; 8]>> for u8x16[src]

impl FromBits<Simd<[m32; 4]>> for u8x16[src]

impl FromBits<Simd<[m64; 2]>> for u8x16[src]

impl FromBits<Simd<[m8; 16]>> for u8x16[src]

impl FromBits<Simd<[u128; 1]>> for u8x16[src]

impl FromBits<Simd<[u16; 8]>> for u8x16[src]

impl FromBits<Simd<[u32; 4]>> for u8x16[src]

impl FromBits<Simd<[u64; 2]>> for u8x16[src]

impl FromBits<__m128> for u8x16[src]

impl FromBits<__m128d> for u8x16[src]

impl FromBits<__m128i> for u8x16[src]

impl FromCast<Simd<[f32; 16]>> for u8x16[src]

impl FromCast<Simd<[i16; 16]>> for u8x16[src]

impl FromCast<Simd<[i32; 16]>> for u8x16[src]

impl FromCast<Simd<[i8; 16]>> for u8x16[src]

impl FromCast<Simd<[m16; 16]>> for u8x16[src]

impl FromCast<Simd<[m32; 16]>> for u8x16[src]

impl FromCast<Simd<[m8; 16]>> for u8x16[src]

impl FromCast<Simd<[u16; 16]>> for u8x16[src]

impl FromCast<Simd<[u32; 16]>> for u8x16[src]

impl Hash for u8x16[src]

impl LowerHex for u8x16[src]

impl Mul<Simd<[u8; 16]>> for u8x16[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<u8> for u8x16[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[u8; 16]>> for u8x16[src]

impl MulAssign<u8> for u8x16[src]

impl Not for u8x16[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl Octal for u8x16[src]

impl PartialEq<Simd<[u8; 16]>> for u8x16[src]

impl<'a> Product<&'a Simd<[u8; 16]>> for u8x16[src]

impl Product<Simd<[u8; 16]>> for u8x16[src]

impl Rem<Simd<[u8; 16]>> for u8x16[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<u8> for u8x16[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[u8; 16]>> for u8x16[src]

impl RemAssign<u8> for u8x16[src]

impl Shl<Simd<[u8; 16]>> for u8x16[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<u32> for u8x16[src]

type Output = Self

The resulting type after applying the << operator.

+

impl ShlAssign<Simd<[u8; 16]>> for u8x16[src]

impl ShlAssign<u32> for u8x16[src]

impl Shr<Simd<[u8; 16]>> for u8x16[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<u32> for u8x16[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl ShrAssign<Simd<[u8; 16]>> for u8x16[src]

impl ShrAssign<u32> for u8x16[src]

impl Simd for u8x16[src]

type Element = u8

Element type of the SIMD vector

+

type LanesType = [u32; 16]

The type: [u32; Self::N].

+

impl Sub<Simd<[u8; 16]>> for u8x16[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<u8> for u8x16[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[u8; 16]>> for u8x16[src]

impl SubAssign<u8> for u8x16[src]

impl<'a> Sum<&'a Simd<[u8; 16]>> for u8x16[src]

impl Sum<Simd<[u8; 16]>> for u8x16[src]

impl UpperHex for u8x16[src]

\ No newline at end of file diff --git a/packed_simd/type.u8x2.html b/packed_simd/type.u8x2.html new file mode 100644 index 000000000..d17548143 --- /dev/null +++ b/packed_simd/type.u8x2.html @@ -0,0 +1,231 @@ +packed_simd::u8x2 - Rust

[−][src]Type Definition packed_simd::u8x2

type u8x2 = Simd<[u8; 2]>;

A 16-bit vector with 2 u8 lanes.

+

Implementations

impl u8x2[src]

pub const fn new(x0: u8, x1: u8) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: u8) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> u8[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> u8[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: u8) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: u8) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl u8x2[src]

pub fn rotate_left(self, n: u8x2) -> u8x2[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: u8x2) -> u8x2[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl u8x2[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl u8x2[src]

pub fn wrapping_sum(self) -> u8[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> u8[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl u8x2[src]

pub fn max_element(self) -> u8[src]

Largest vector element value.

+

pub fn min_element(self) -> u8[src]

Smallest vector element value.

+

impl u8x2[src]

pub fn and(self) -> u8[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> u8[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> u8[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl u8x2[src]

pub fn from_slice_aligned(slice: &[u8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[u8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[u8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[u8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl u8x2[src]

pub fn write_to_slice_aligned(self, slice: &mut [u8])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [u8])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [u8])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [u8])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl u8x2[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl u8x2[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl u8x2[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl u8x2[src]

pub fn eq(self, other: Self) -> m8x2[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m8x2[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m8x2[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m8x2[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m8x2[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m8x2[src]

Lane-wise greater-than-or-equals comparison.

+

impl u8x2[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<u8x2>[src]

Returns a wrapper that implements PartialOrd.

+

impl u8x2[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<u8x2>[src]

Returns a wrapper that implements Ord.

+

impl u8x2[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl Add<Simd<[u8; 2]>> for u8x2[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<u8> for u8x2[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[u8; 2]>> for u8x2[src]

impl AddAssign<u8> for u8x2[src]

impl Binary for u8x2[src]

impl BitAnd<Simd<[u8; 2]>> for u8x2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<u8> for u8x2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[u8; 2]>> for u8x2[src]

impl BitAndAssign<u8> for u8x2[src]

impl BitOr<Simd<[u8; 2]>> for u8x2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<u8> for u8x2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[u8; 2]>> for u8x2[src]

impl BitOrAssign<u8> for u8x2[src]

impl BitXor<Simd<[u8; 2]>> for u8x2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<u8> for u8x2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[u8; 2]>> for u8x2[src]

impl BitXorAssign<u8> for u8x2[src]

impl Debug for u8x2[src]

impl Default for u8x2[src]

impl Div<Simd<[u8; 2]>> for u8x2[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<u8> for u8x2[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[u8; 2]>> for u8x2[src]

impl DivAssign<u8> for u8x2[src]

impl Eq for u8x2[src]

impl From<[u8; 2]> for u8x2[src]

impl FromBits<Simd<[i8; 2]>> for u8x2[src]

impl FromBits<Simd<[m8; 2]>> for u8x2[src]

impl FromCast<Simd<[f32; 2]>> for u8x2[src]

impl FromCast<Simd<[f64; 2]>> for u8x2[src]

impl FromCast<Simd<[i128; 2]>> for u8x2[src]

impl FromCast<Simd<[i16; 2]>> for u8x2[src]

impl FromCast<Simd<[i32; 2]>> for u8x2[src]

impl FromCast<Simd<[i64; 2]>> for u8x2[src]

impl FromCast<Simd<[i8; 2]>> for u8x2[src]

impl FromCast<Simd<[isize; 2]>> for u8x2[src]

impl FromCast<Simd<[m128; 2]>> for u8x2[src]

impl FromCast<Simd<[m16; 2]>> for u8x2[src]

impl FromCast<Simd<[m32; 2]>> for u8x2[src]

impl FromCast<Simd<[m64; 2]>> for u8x2[src]

impl FromCast<Simd<[m8; 2]>> for u8x2[src]

impl FromCast<Simd<[msize; 2]>> for u8x2[src]

impl FromCast<Simd<[u128; 2]>> for u8x2[src]

impl FromCast<Simd<[u16; 2]>> for u8x2[src]

impl FromCast<Simd<[u32; 2]>> for u8x2[src]

impl FromCast<Simd<[u64; 2]>> for u8x2[src]

impl FromCast<Simd<[usize; 2]>> for u8x2[src]

impl Hash for u8x2[src]

impl LowerHex for u8x2[src]

impl Mul<Simd<[u8; 2]>> for u8x2[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<u8> for u8x2[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[u8; 2]>> for u8x2[src]

impl MulAssign<u8> for u8x2[src]

impl Not for u8x2[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl Octal for u8x2[src]

impl PartialEq<Simd<[u8; 2]>> for u8x2[src]

impl<'a> Product<&'a Simd<[u8; 2]>> for u8x2[src]

impl Product<Simd<[u8; 2]>> for u8x2[src]

impl Rem<Simd<[u8; 2]>> for u8x2[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<u8> for u8x2[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[u8; 2]>> for u8x2[src]

impl RemAssign<u8> for u8x2[src]

impl Shl<Simd<[u8; 2]>> for u8x2[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<u32> for u8x2[src]

type Output = Self

The resulting type after applying the << operator.

+

impl ShlAssign<Simd<[u8; 2]>> for u8x2[src]

impl ShlAssign<u32> for u8x2[src]

impl Shr<Simd<[u8; 2]>> for u8x2[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<u32> for u8x2[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl ShrAssign<Simd<[u8; 2]>> for u8x2[src]

impl ShrAssign<u32> for u8x2[src]

impl Simd for u8x2[src]

type Element = u8

Element type of the SIMD vector

+

type LanesType = [u32; 2]

The type: [u32; Self::N].

+

impl Sub<Simd<[u8; 2]>> for u8x2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<u8> for u8x2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[u8; 2]>> for u8x2[src]

impl SubAssign<u8> for u8x2[src]

impl<'a> Sum<&'a Simd<[u8; 2]>> for u8x2[src]

impl Sum<Simd<[u8; 2]>> for u8x2[src]

impl UpperHex for u8x2[src]

\ No newline at end of file diff --git a/packed_simd/type.u8x32.html b/packed_simd/type.u8x32.html new file mode 100644 index 000000000..e031f40eb --- /dev/null +++ b/packed_simd/type.u8x32.html @@ -0,0 +1,234 @@ +packed_simd::u8x32 - Rust

[−][src]Type Definition packed_simd::u8x32

type u8x32 = Simd<[u8; 32]>;

A 256-bit vector with 32 u8 lanes.

+

Implementations

impl u8x32[src]

pub const fn new(
    x0: u8,
    x1: u8,
    x2: u8,
    x3: u8,
    x4: u8,
    x5: u8,
    x6: u8,
    x7: u8,
    x8: u8,
    x9: u8,
    x10: u8,
    x11: u8,
    x12: u8,
    x13: u8,
    x14: u8,
    x15: u8,
    x16: u8,
    x17: u8,
    x18: u8,
    x19: u8,
    x20: u8,
    x21: u8,
    x22: u8,
    x23: u8,
    x24: u8,
    x25: u8,
    x26: u8,
    x27: u8,
    x28: u8,
    x29: u8,
    x30: u8,
    x31: u8
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: u8) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> u8[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> u8[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: u8) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: u8) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl u8x32[src]

pub fn rotate_left(self, n: u8x32) -> u8x32[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: u8x32) -> u8x32[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl u8x32[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl u8x32[src]

pub fn wrapping_sum(self) -> u8[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> u8[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl u8x32[src]

pub fn max_element(self) -> u8[src]

Largest vector element value.

+

pub fn min_element(self) -> u8[src]

Smallest vector element value.

+

impl u8x32[src]

pub fn and(self) -> u8[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> u8[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> u8[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl u8x32[src]

pub fn from_slice_aligned(slice: &[u8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[u8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[u8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[u8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl u8x32[src]

pub fn write_to_slice_aligned(self, slice: &mut [u8])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [u8])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [u8])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [u8])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl u8x32[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl u8x32[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl u8x32[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl u8x32[src]

pub fn eq(self, other: Self) -> m8x32[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m8x32[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m8x32[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m8x32[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m8x32[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m8x32[src]

Lane-wise greater-than-or-equals comparison.

+

impl u8x32[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<u8x32>[src]

Returns a wrapper that implements PartialOrd.

+

impl u8x32[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<u8x32>[src]

Returns a wrapper that implements Ord.

+

impl u8x32[src]

pub fn bitmask(self) -> u32[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl Add<Simd<[u8; 32]>> for u8x32[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<u8> for u8x32[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[u8; 32]>> for u8x32[src]

impl AddAssign<u8> for u8x32[src]

impl Binary for u8x32[src]

impl BitAnd<Simd<[u8; 32]>> for u8x32[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<u8> for u8x32[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[u8; 32]>> for u8x32[src]

impl BitAndAssign<u8> for u8x32[src]

impl BitOr<Simd<[u8; 32]>> for u8x32[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<u8> for u8x32[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[u8; 32]>> for u8x32[src]

impl BitOrAssign<u8> for u8x32[src]

impl BitXor<Simd<[u8; 32]>> for u8x32[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<u8> for u8x32[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[u8; 32]>> for u8x32[src]

impl BitXorAssign<u8> for u8x32[src]

impl Debug for u8x32[src]

impl Default for u8x32[src]

impl Div<Simd<[u8; 32]>> for u8x32[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<u8> for u8x32[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[u8; 32]>> for u8x32[src]

impl DivAssign<u8> for u8x32[src]

impl Eq for u8x32[src]

impl From<[u8; 32]> for u8x32[src]

impl FromBits<Simd<[f32; 8]>> for u8x32[src]

impl FromBits<Simd<[f64; 4]>> for u8x32[src]

impl FromBits<Simd<[i128; 2]>> for u8x32[src]

impl FromBits<Simd<[i16; 16]>> for u8x32[src]

impl FromBits<Simd<[i32; 8]>> for u8x32[src]

impl FromBits<Simd<[i64; 4]>> for u8x32[src]

impl FromBits<Simd<[i8; 32]>> for u8x32[src]

impl FromBits<Simd<[m128; 2]>> for u8x32[src]

impl FromBits<Simd<[m16; 16]>> for u8x32[src]

impl FromBits<Simd<[m32; 8]>> for u8x32[src]

impl FromBits<Simd<[m64; 4]>> for u8x32[src]

impl FromBits<Simd<[m8; 32]>> for u8x32[src]

impl FromBits<Simd<[u128; 2]>> for u8x32[src]

impl FromBits<Simd<[u16; 16]>> for u8x32[src]

impl FromBits<Simd<[u32; 8]>> for u8x32[src]

impl FromBits<Simd<[u64; 4]>> for u8x32[src]

impl FromBits<__m256> for u8x32[src]

impl FromBits<__m256d> for u8x32[src]

impl FromBits<__m256i> for u8x32[src]

impl FromCast<Simd<[i16; 32]>> for u8x32[src]

impl FromCast<Simd<[i8; 32]>> for u8x32[src]

impl FromCast<Simd<[m16; 32]>> for u8x32[src]

impl FromCast<Simd<[m8; 32]>> for u8x32[src]

impl FromCast<Simd<[u16; 32]>> for u8x32[src]

impl Hash for u8x32[src]

impl LowerHex for u8x32[src]

impl Mul<Simd<[u8; 32]>> for u8x32[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<u8> for u8x32[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[u8; 32]>> for u8x32[src]

impl MulAssign<u8> for u8x32[src]

impl Not for u8x32[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl Octal for u8x32[src]

impl PartialEq<Simd<[u8; 32]>> for u8x32[src]

impl<'a> Product<&'a Simd<[u8; 32]>> for u8x32[src]

impl Product<Simd<[u8; 32]>> for u8x32[src]

impl Rem<Simd<[u8; 32]>> for u8x32[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<u8> for u8x32[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[u8; 32]>> for u8x32[src]

impl RemAssign<u8> for u8x32[src]

impl Shl<Simd<[u8; 32]>> for u8x32[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<u32> for u8x32[src]

type Output = Self

The resulting type after applying the << operator.

+

impl ShlAssign<Simd<[u8; 32]>> for u8x32[src]

impl ShlAssign<u32> for u8x32[src]

impl Shr<Simd<[u8; 32]>> for u8x32[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<u32> for u8x32[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl ShrAssign<Simd<[u8; 32]>> for u8x32[src]

impl ShrAssign<u32> for u8x32[src]

impl Simd for u8x32[src]

type Element = u8

Element type of the SIMD vector

+

type LanesType = [u32; 32]

The type: [u32; Self::N].

+

impl Sub<Simd<[u8; 32]>> for u8x32[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<u8> for u8x32[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[u8; 32]>> for u8x32[src]

impl SubAssign<u8> for u8x32[src]

impl<'a> Sum<&'a Simd<[u8; 32]>> for u8x32[src]

impl Sum<Simd<[u8; 32]>> for u8x32[src]

impl UpperHex for u8x32[src]

\ No newline at end of file diff --git a/packed_simd/type.u8x4.html b/packed_simd/type.u8x4.html new file mode 100644 index 000000000..8ac1df9a1 --- /dev/null +++ b/packed_simd/type.u8x4.html @@ -0,0 +1,234 @@ +packed_simd::u8x4 - Rust

[−][src]Type Definition packed_simd::u8x4

type u8x4 = Simd<[u8; 4]>;

A 32-bit vector with 4 u8 lanes.

+

Implementations

impl u8x4[src]

pub const fn new(x0: u8, x1: u8, x2: u8, x3: u8) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: u8) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> u8[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> u8[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: u8) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: u8) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl u8x4[src]

pub fn rotate_left(self, n: u8x4) -> u8x4[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: u8x4) -> u8x4[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl u8x4[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl u8x4[src]

pub fn wrapping_sum(self) -> u8[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> u8[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl u8x4[src]

pub fn max_element(self) -> u8[src]

Largest vector element value.

+

pub fn min_element(self) -> u8[src]

Smallest vector element value.

+

impl u8x4[src]

pub fn and(self) -> u8[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> u8[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> u8[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl u8x4[src]

pub fn from_slice_aligned(slice: &[u8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[u8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[u8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[u8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl u8x4[src]

pub fn write_to_slice_aligned(self, slice: &mut [u8])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [u8])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [u8])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [u8])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl u8x4[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl u8x4[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl u8x4[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl u8x4[src]

pub fn eq(self, other: Self) -> m8x4[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m8x4[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m8x4[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m8x4[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m8x4[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m8x4[src]

Lane-wise greater-than-or-equals comparison.

+

impl u8x4[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<u8x4>[src]

Returns a wrapper that implements PartialOrd.

+

impl u8x4[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<u8x4>[src]

Returns a wrapper that implements Ord.

+

impl u8x4[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl Add<Simd<[u8; 4]>> for u8x4[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<u8> for u8x4[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[u8; 4]>> for u8x4[src]

impl AddAssign<u8> for u8x4[src]

impl Binary for u8x4[src]

impl BitAnd<Simd<[u8; 4]>> for u8x4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<u8> for u8x4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[u8; 4]>> for u8x4[src]

impl BitAndAssign<u8> for u8x4[src]

impl BitOr<Simd<[u8; 4]>> for u8x4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<u8> for u8x4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[u8; 4]>> for u8x4[src]

impl BitOrAssign<u8> for u8x4[src]

impl BitXor<Simd<[u8; 4]>> for u8x4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<u8> for u8x4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[u8; 4]>> for u8x4[src]

impl BitXorAssign<u8> for u8x4[src]

impl Debug for u8x4[src]

impl Default for u8x4[src]

impl Div<Simd<[u8; 4]>> for u8x4[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<u8> for u8x4[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[u8; 4]>> for u8x4[src]

impl DivAssign<u8> for u8x4[src]

impl Eq for u8x4[src]

impl From<[u8; 4]> for u8x4[src]

impl FromBits<Simd<[i16; 2]>> for u8x4[src]

impl FromBits<Simd<[i8; 4]>> for u8x4[src]

impl FromBits<Simd<[m16; 2]>> for u8x4[src]

impl FromBits<Simd<[m8; 4]>> for u8x4[src]

impl FromBits<Simd<[u16; 2]>> for u8x4[src]

impl FromCast<Simd<[f32; 4]>> for u8x4[src]

impl FromCast<Simd<[f64; 4]>> for u8x4[src]

impl FromCast<Simd<[i128; 4]>> for u8x4[src]

impl FromCast<Simd<[i16; 4]>> for u8x4[src]

impl FromCast<Simd<[i32; 4]>> for u8x4[src]

impl FromCast<Simd<[i64; 4]>> for u8x4[src]

impl FromCast<Simd<[i8; 4]>> for u8x4[src]

impl FromCast<Simd<[isize; 4]>> for u8x4[src]

impl FromCast<Simd<[m128; 4]>> for u8x4[src]

impl FromCast<Simd<[m16; 4]>> for u8x4[src]

impl FromCast<Simd<[m32; 4]>> for u8x4[src]

impl FromCast<Simd<[m64; 4]>> for u8x4[src]

impl FromCast<Simd<[m8; 4]>> for u8x4[src]

impl FromCast<Simd<[msize; 4]>> for u8x4[src]

impl FromCast<Simd<[u128; 4]>> for u8x4[src]

impl FromCast<Simd<[u16; 4]>> for u8x4[src]

impl FromCast<Simd<[u32; 4]>> for u8x4[src]

impl FromCast<Simd<[u64; 4]>> for u8x4[src]

impl FromCast<Simd<[usize; 4]>> for u8x4[src]

impl Hash for u8x4[src]

impl LowerHex for u8x4[src]

impl Mul<Simd<[u8; 4]>> for u8x4[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<u8> for u8x4[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[u8; 4]>> for u8x4[src]

impl MulAssign<u8> for u8x4[src]

impl Not for u8x4[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl Octal for u8x4[src]

impl PartialEq<Simd<[u8; 4]>> for u8x4[src]

impl<'a> Product<&'a Simd<[u8; 4]>> for u8x4[src]

impl Product<Simd<[u8; 4]>> for u8x4[src]

impl Rem<Simd<[u8; 4]>> for u8x4[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<u8> for u8x4[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[u8; 4]>> for u8x4[src]

impl RemAssign<u8> for u8x4[src]

impl Shl<Simd<[u8; 4]>> for u8x4[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<u32> for u8x4[src]

type Output = Self

The resulting type after applying the << operator.

+

impl ShlAssign<Simd<[u8; 4]>> for u8x4[src]

impl ShlAssign<u32> for u8x4[src]

impl Shr<Simd<[u8; 4]>> for u8x4[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<u32> for u8x4[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl ShrAssign<Simd<[u8; 4]>> for u8x4[src]

impl ShrAssign<u32> for u8x4[src]

impl Simd for u8x4[src]

type Element = u8

Element type of the SIMD vector

+

type LanesType = [u32; 4]

The type: [u32; Self::N].

+

impl Sub<Simd<[u8; 4]>> for u8x4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<u8> for u8x4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[u8; 4]>> for u8x4[src]

impl SubAssign<u8> for u8x4[src]

impl<'a> Sum<&'a Simd<[u8; 4]>> for u8x4[src]

impl Sum<Simd<[u8; 4]>> for u8x4[src]

impl UpperHex for u8x4[src]

\ No newline at end of file diff --git a/packed_simd/type.u8x64.html b/packed_simd/type.u8x64.html new file mode 100644 index 000000000..c039706fc --- /dev/null +++ b/packed_simd/type.u8x64.html @@ -0,0 +1,228 @@ +packed_simd::u8x64 - Rust

[−][src]Type Definition packed_simd::u8x64

type u8x64 = Simd<[u8; 64]>;

A 512-bit vector with 64 u8 lanes.

+

Implementations

impl u8x64[src]

pub const fn new(
    x0: u8,
    x1: u8,
    x2: u8,
    x3: u8,
    x4: u8,
    x5: u8,
    x6: u8,
    x7: u8,
    x8: u8,
    x9: u8,
    x10: u8,
    x11: u8,
    x12: u8,
    x13: u8,
    x14: u8,
    x15: u8,
    x16: u8,
    x17: u8,
    x18: u8,
    x19: u8,
    x20: u8,
    x21: u8,
    x22: u8,
    x23: u8,
    x24: u8,
    x25: u8,
    x26: u8,
    x27: u8,
    x28: u8,
    x29: u8,
    x30: u8,
    x31: u8,
    x32: u8,
    x33: u8,
    x34: u8,
    x35: u8,
    x36: u8,
    x37: u8,
    x38: u8,
    x39: u8,
    x40: u8,
    x41: u8,
    x42: u8,
    x43: u8,
    x44: u8,
    x45: u8,
    x46: u8,
    x47: u8,
    x48: u8,
    x49: u8,
    x50: u8,
    x51: u8,
    x52: u8,
    x53: u8,
    x54: u8,
    x55: u8,
    x56: u8,
    x57: u8,
    x58: u8,
    x59: u8,
    x60: u8,
    x61: u8,
    x62: u8,
    x63: u8
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: u8) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> u8[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> u8[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: u8) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: u8) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl u8x64[src]

pub fn rotate_left(self, n: u8x64) -> u8x64[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: u8x64) -> u8x64[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl u8x64[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl u8x64[src]

pub fn wrapping_sum(self) -> u8[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> u8[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl u8x64[src]

pub fn max_element(self) -> u8[src]

Largest vector element value.

+

pub fn min_element(self) -> u8[src]

Smallest vector element value.

+

impl u8x64[src]

pub fn and(self) -> u8[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> u8[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> u8[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl u8x64[src]

pub fn from_slice_aligned(slice: &[u8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[u8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[u8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[u8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl u8x64[src]

pub fn write_to_slice_aligned(self, slice: &mut [u8])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [u8])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [u8])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [u8])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl u8x64[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl u8x64[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl u8x64[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl u8x64[src]

pub fn eq(self, other: Self) -> m8x64[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m8x64[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m8x64[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m8x64[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m8x64[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m8x64[src]

Lane-wise greater-than-or-equals comparison.

+

impl u8x64[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<u8x64>[src]

Returns a wrapper that implements PartialOrd.

+

impl u8x64[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<u8x64>[src]

Returns a wrapper that implements Ord.

+

impl u8x64[src]

pub fn bitmask(self) -> u64[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl Add<Simd<[u8; 64]>> for u8x64[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<u8> for u8x64[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[u8; 64]>> for u8x64[src]

impl AddAssign<u8> for u8x64[src]

impl Binary for u8x64[src]

impl BitAnd<Simd<[u8; 64]>> for u8x64[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<u8> for u8x64[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[u8; 64]>> for u8x64[src]

impl BitAndAssign<u8> for u8x64[src]

impl BitOr<Simd<[u8; 64]>> for u8x64[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<u8> for u8x64[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[u8; 64]>> for u8x64[src]

impl BitOrAssign<u8> for u8x64[src]

impl BitXor<Simd<[u8; 64]>> for u8x64[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<u8> for u8x64[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[u8; 64]>> for u8x64[src]

impl BitXorAssign<u8> for u8x64[src]

impl Debug for u8x64[src]

impl Default for u8x64[src]

impl Div<Simd<[u8; 64]>> for u8x64[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<u8> for u8x64[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[u8; 64]>> for u8x64[src]

impl DivAssign<u8> for u8x64[src]

impl Eq for u8x64[src]

impl From<[u8; 64]> for u8x64[src]

impl FromBits<Simd<[f32; 16]>> for u8x64[src]

impl FromBits<Simd<[f64; 8]>> for u8x64[src]

impl FromBits<Simd<[i128; 4]>> for u8x64[src]

impl FromBits<Simd<[i16; 32]>> for u8x64[src]

impl FromBits<Simd<[i32; 16]>> for u8x64[src]

impl FromBits<Simd<[i64; 8]>> for u8x64[src]

impl FromBits<Simd<[i8; 64]>> for u8x64[src]

impl FromBits<Simd<[m128; 4]>> for u8x64[src]

impl FromBits<Simd<[m16; 32]>> for u8x64[src]

impl FromBits<Simd<[m32; 16]>> for u8x64[src]

impl FromBits<Simd<[m64; 8]>> for u8x64[src]

impl FromBits<Simd<[m8; 64]>> for u8x64[src]

impl FromBits<Simd<[u128; 4]>> for u8x64[src]

impl FromBits<Simd<[u16; 32]>> for u8x64[src]

impl FromBits<Simd<[u32; 16]>> for u8x64[src]

impl FromBits<Simd<[u64; 8]>> for u8x64[src]

impl FromCast<Simd<[i8; 64]>> for u8x64[src]

impl FromCast<Simd<[m8; 64]>> for u8x64[src]

impl Hash for u8x64[src]

impl LowerHex for u8x64[src]

impl Mul<Simd<[u8; 64]>> for u8x64[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<u8> for u8x64[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[u8; 64]>> for u8x64[src]

impl MulAssign<u8> for u8x64[src]

impl Not for u8x64[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl Octal for u8x64[src]

impl PartialEq<Simd<[u8; 64]>> for u8x64[src]

impl<'a> Product<&'a Simd<[u8; 64]>> for u8x64[src]

impl Product<Simd<[u8; 64]>> for u8x64[src]

impl Rem<Simd<[u8; 64]>> for u8x64[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<u8> for u8x64[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[u8; 64]>> for u8x64[src]

impl RemAssign<u8> for u8x64[src]

impl Shl<Simd<[u8; 64]>> for u8x64[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<u32> for u8x64[src]

type Output = Self

The resulting type after applying the << operator.

+

impl ShlAssign<Simd<[u8; 64]>> for u8x64[src]

impl ShlAssign<u32> for u8x64[src]

impl Shr<Simd<[u8; 64]>> for u8x64[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<u32> for u8x64[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl ShrAssign<Simd<[u8; 64]>> for u8x64[src]

impl ShrAssign<u32> for u8x64[src]

impl Simd for u8x64[src]

type Element = u8

Element type of the SIMD vector

+

type LanesType = [u32; 64]

The type: [u32; Self::N].

+

impl Sub<Simd<[u8; 64]>> for u8x64[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<u8> for u8x64[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[u8; 64]>> for u8x64[src]

impl SubAssign<u8> for u8x64[src]

impl<'a> Sum<&'a Simd<[u8; 64]>> for u8x64[src]

impl Sum<Simd<[u8; 64]>> for u8x64[src]

impl UpperHex for u8x64[src]

\ No newline at end of file diff --git a/packed_simd/type.u8x8.html b/packed_simd/type.u8x8.html new file mode 100644 index 000000000..55871a0ec --- /dev/null +++ b/packed_simd/type.u8x8.html @@ -0,0 +1,236 @@ +packed_simd::u8x8 - Rust

[−][src]Type Definition packed_simd::u8x8

type u8x8 = Simd<[u8; 8]>;

A 64-bit vector with 8 u8 lanes.

+

Implementations

impl u8x8[src]

pub const fn new(
    x0: u8,
    x1: u8,
    x2: u8,
    x3: u8,
    x4: u8,
    x5: u8,
    x6: u8,
    x7: u8
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: u8) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> u8[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> u8[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: u8) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: u8) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl u8x8[src]

pub fn rotate_left(self, n: u8x8) -> u8x8[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: u8x8) -> u8x8[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl u8x8[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl u8x8[src]

pub fn wrapping_sum(self) -> u8[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> u8[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl u8x8[src]

pub fn max_element(self) -> u8[src]

Largest vector element value.

+

pub fn min_element(self) -> u8[src]

Smallest vector element value.

+

impl u8x8[src]

pub fn and(self) -> u8[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> u8[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> u8[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl u8x8[src]

pub fn from_slice_aligned(slice: &[u8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[u8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[u8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[u8]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl u8x8[src]

pub fn write_to_slice_aligned(self, slice: &mut [u8])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [u8])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [u8])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [u8])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl u8x8[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl u8x8[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl u8x8[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl u8x8[src]

pub fn eq(self, other: Self) -> m8x8[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> m8x8[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> m8x8[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> m8x8[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> m8x8[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> m8x8[src]

Lane-wise greater-than-or-equals comparison.

+

impl u8x8[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<u8x8>[src]

Returns a wrapper that implements PartialOrd.

+

impl u8x8[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<u8x8>[src]

Returns a wrapper that implements Ord.

+

impl u8x8[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl Add<Simd<[u8; 8]>> for u8x8[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<u8> for u8x8[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[u8; 8]>> for u8x8[src]

impl AddAssign<u8> for u8x8[src]

impl Binary for u8x8[src]

impl BitAnd<Simd<[u8; 8]>> for u8x8[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<u8> for u8x8[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[u8; 8]>> for u8x8[src]

impl BitAndAssign<u8> for u8x8[src]

impl BitOr<Simd<[u8; 8]>> for u8x8[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<u8> for u8x8[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[u8; 8]>> for u8x8[src]

impl BitOrAssign<u8> for u8x8[src]

impl BitXor<Simd<[u8; 8]>> for u8x8[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<u8> for u8x8[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[u8; 8]>> for u8x8[src]

impl BitXorAssign<u8> for u8x8[src]

impl Debug for u8x8[src]

impl Default for u8x8[src]

impl Div<Simd<[u8; 8]>> for u8x8[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<u8> for u8x8[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[u8; 8]>> for u8x8[src]

impl DivAssign<u8> for u8x8[src]

impl Eq for u8x8[src]

impl From<[u8; 8]> for u8x8[src]

impl FromBits<Simd<[f32; 2]>> for u8x8[src]

impl FromBits<Simd<[i16; 4]>> for u8x8[src]

impl FromBits<Simd<[i32; 2]>> for u8x8[src]

impl FromBits<Simd<[i8; 8]>> for u8x8[src]

impl FromBits<Simd<[m16; 4]>> for u8x8[src]

impl FromBits<Simd<[m32; 2]>> for u8x8[src]

impl FromBits<Simd<[m8; 8]>> for u8x8[src]

impl FromBits<Simd<[u16; 4]>> for u8x8[src]

impl FromBits<Simd<[u32; 2]>> for u8x8[src]

impl FromBits<__m64> for u8x8[src]

impl FromCast<Simd<[f32; 8]>> for u8x8[src]

impl FromCast<Simd<[f64; 8]>> for u8x8[src]

impl FromCast<Simd<[i16; 8]>> for u8x8[src]

impl FromCast<Simd<[i32; 8]>> for u8x8[src]

impl FromCast<Simd<[i64; 8]>> for u8x8[src]

impl FromCast<Simd<[i8; 8]>> for u8x8[src]

impl FromCast<Simd<[isize; 8]>> for u8x8[src]

impl FromCast<Simd<[m16; 8]>> for u8x8[src]

impl FromCast<Simd<[m32; 8]>> for u8x8[src]

impl FromCast<Simd<[m64; 8]>> for u8x8[src]

impl FromCast<Simd<[m8; 8]>> for u8x8[src]

impl FromCast<Simd<[msize; 8]>> for u8x8[src]

impl FromCast<Simd<[u16; 8]>> for u8x8[src]

impl FromCast<Simd<[u32; 8]>> for u8x8[src]

impl FromCast<Simd<[u64; 8]>> for u8x8[src]

impl FromCast<Simd<[usize; 8]>> for u8x8[src]

impl Hash for u8x8[src]

impl LowerHex for u8x8[src]

impl Mul<Simd<[u8; 8]>> for u8x8[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<u8> for u8x8[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[u8; 8]>> for u8x8[src]

impl MulAssign<u8> for u8x8[src]

impl Not for u8x8[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl Octal for u8x8[src]

impl PartialEq<Simd<[u8; 8]>> for u8x8[src]

impl<'a> Product<&'a Simd<[u8; 8]>> for u8x8[src]

impl Product<Simd<[u8; 8]>> for u8x8[src]

impl Rem<Simd<[u8; 8]>> for u8x8[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<u8> for u8x8[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[u8; 8]>> for u8x8[src]

impl RemAssign<u8> for u8x8[src]

impl Shl<Simd<[u8; 8]>> for u8x8[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<u32> for u8x8[src]

type Output = Self

The resulting type after applying the << operator.

+

impl ShlAssign<Simd<[u8; 8]>> for u8x8[src]

impl ShlAssign<u32> for u8x8[src]

impl Shr<Simd<[u8; 8]>> for u8x8[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<u32> for u8x8[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl ShrAssign<Simd<[u8; 8]>> for u8x8[src]

impl ShrAssign<u32> for u8x8[src]

impl Simd for u8x8[src]

type Element = u8

Element type of the SIMD vector

+

type LanesType = [u32; 8]

The type: [u32; Self::N].

+

impl Sub<Simd<[u8; 8]>> for u8x8[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<u8> for u8x8[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[u8; 8]>> for u8x8[src]

impl SubAssign<u8> for u8x8[src]

impl<'a> Sum<&'a Simd<[u8; 8]>> for u8x8[src]

impl Sum<Simd<[u8; 8]>> for u8x8[src]

impl UpperHex for u8x8[src]

\ No newline at end of file diff --git a/packed_simd/type.usizex2.html b/packed_simd/type.usizex2.html new file mode 100644 index 000000000..84dc590fb --- /dev/null +++ b/packed_simd/type.usizex2.html @@ -0,0 +1,229 @@ +packed_simd::usizex2 - Rust

[−][src]Type Definition packed_simd::usizex2

type usizex2 = Simd<[usize; 2]>;

A vector with 2 usize lanes.

+

Implementations

impl usizex2[src]

pub const fn new(x0: usize, x1: usize) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: usize) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> usize[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> usize[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: usize) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: usize) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl usizex2[src]

pub fn rotate_left(self, n: usizex2) -> usizex2[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: usizex2) -> usizex2[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl usizex2[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl usizex2[src]

pub fn wrapping_sum(self) -> usize[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> usize[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl usizex2[src]

pub fn max_element(self) -> usize[src]

Largest vector element value.

+

pub fn min_element(self) -> usize[src]

Smallest vector element value.

+

impl usizex2[src]

pub fn and(self) -> usize[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> usize[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> usize[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl usizex2[src]

pub fn from_slice_aligned(slice: &[usize]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[usize]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[usize]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[usize]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl usizex2[src]

pub fn write_to_slice_aligned(self, slice: &mut [usize])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [usize])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [usize])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [usize])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl usizex2[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl usizex2[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl usizex2[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl usizex2[src]

pub fn eq(self, other: Self) -> msizex2[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> msizex2[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> msizex2[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> msizex2[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> msizex2[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> msizex2[src]

Lane-wise greater-than-or-equals comparison.

+

impl usizex2[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<usizex2>[src]

Returns a wrapper that implements PartialOrd.

+

impl usizex2[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<usizex2>[src]

Returns a wrapper that implements Ord.

+

impl usizex2[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl Add<Simd<[usize; 2]>> for usizex2[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<usize> for usizex2[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[usize; 2]>> for usizex2[src]

impl AddAssign<usize> for usizex2[src]

impl Binary for usizex2[src]

impl BitAnd<Simd<[usize; 2]>> for usizex2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<usize> for usizex2[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[usize; 2]>> for usizex2[src]

impl BitAndAssign<usize> for usizex2[src]

impl BitOr<Simd<[usize; 2]>> for usizex2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<usize> for usizex2[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[usize; 2]>> for usizex2[src]

impl BitOrAssign<usize> for usizex2[src]

impl BitXor<Simd<[usize; 2]>> for usizex2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<usize> for usizex2[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[usize; 2]>> for usizex2[src]

impl BitXorAssign<usize> for usizex2[src]

impl Debug for usizex2[src]

impl Default for usizex2[src]

impl Div<Simd<[usize; 2]>> for usizex2[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<usize> for usizex2[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[usize; 2]>> for usizex2[src]

impl DivAssign<usize> for usizex2[src]

impl Eq for usizex2[src]

impl From<[usize; 2]> for usizex2[src]

impl FromCast<Simd<[f32; 2]>> for usizex2[src]

impl FromCast<Simd<[f64; 2]>> for usizex2[src]

impl FromCast<Simd<[i128; 2]>> for usizex2[src]

impl FromCast<Simd<[i16; 2]>> for usizex2[src]

impl FromCast<Simd<[i32; 2]>> for usizex2[src]

impl FromCast<Simd<[i64; 2]>> for usizex2[src]

impl FromCast<Simd<[i8; 2]>> for usizex2[src]

impl FromCast<Simd<[isize; 2]>> for usizex2[src]

impl FromCast<Simd<[m128; 2]>> for usizex2[src]

impl FromCast<Simd<[m16; 2]>> for usizex2[src]

impl FromCast<Simd<[m32; 2]>> for usizex2[src]

impl FromCast<Simd<[m64; 2]>> for usizex2[src]

impl FromCast<Simd<[m8; 2]>> for usizex2[src]

impl FromCast<Simd<[msize; 2]>> for usizex2[src]

impl FromCast<Simd<[u128; 2]>> for usizex2[src]

impl FromCast<Simd<[u16; 2]>> for usizex2[src]

impl FromCast<Simd<[u32; 2]>> for usizex2[src]

impl FromCast<Simd<[u64; 2]>> for usizex2[src]

impl FromCast<Simd<[u8; 2]>> for usizex2[src]

impl Hash for usizex2[src]

impl LowerHex for usizex2[src]

impl Mul<Simd<[usize; 2]>> for usizex2[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<usize> for usizex2[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[usize; 2]>> for usizex2[src]

impl MulAssign<usize> for usizex2[src]

impl Not for usizex2[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl Octal for usizex2[src]

impl PartialEq<Simd<[usize; 2]>> for usizex2[src]

impl<'a> Product<&'a Simd<[usize; 2]>> for usizex2[src]

impl Product<Simd<[usize; 2]>> for usizex2[src]

impl Rem<Simd<[usize; 2]>> for usizex2[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<usize> for usizex2[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[usize; 2]>> for usizex2[src]

impl RemAssign<usize> for usizex2[src]

impl Shl<Simd<[usize; 2]>> for usizex2[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<u32> for usizex2[src]

type Output = Self

The resulting type after applying the << operator.

+

impl ShlAssign<Simd<[usize; 2]>> for usizex2[src]

impl ShlAssign<u32> for usizex2[src]

impl Shr<Simd<[usize; 2]>> for usizex2[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<u32> for usizex2[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl ShrAssign<Simd<[usize; 2]>> for usizex2[src]

impl ShrAssign<u32> for usizex2[src]

impl Simd for usizex2[src]

type Element = usize

Element type of the SIMD vector

+

type LanesType = [u32; 2]

The type: [u32; Self::N].

+

impl Sub<Simd<[usize; 2]>> for usizex2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<usize> for usizex2[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[usize; 2]>> for usizex2[src]

impl SubAssign<usize> for usizex2[src]

impl<'a> Sum<&'a Simd<[usize; 2]>> for usizex2[src]

impl Sum<Simd<[usize; 2]>> for usizex2[src]

impl UpperHex for usizex2[src]

\ No newline at end of file diff --git a/packed_simd/type.usizex4.html b/packed_simd/type.usizex4.html new file mode 100644 index 000000000..cf63b4503 --- /dev/null +++ b/packed_simd/type.usizex4.html @@ -0,0 +1,229 @@ +packed_simd::usizex4 - Rust

[−][src]Type Definition packed_simd::usizex4

type usizex4 = Simd<[usize; 4]>;

A vector with 4 usize lanes.

+

Implementations

impl usizex4[src]

pub const fn new(x0: usize, x1: usize, x2: usize, x3: usize) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: usize) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> usize[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> usize[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: usize) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: usize) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl usizex4[src]

pub fn rotate_left(self, n: usizex4) -> usizex4[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: usizex4) -> usizex4[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl usizex4[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl usizex4[src]

pub fn wrapping_sum(self) -> usize[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> usize[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl usizex4[src]

pub fn max_element(self) -> usize[src]

Largest vector element value.

+

pub fn min_element(self) -> usize[src]

Smallest vector element value.

+

impl usizex4[src]

pub fn and(self) -> usize[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> usize[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> usize[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl usizex4[src]

pub fn from_slice_aligned(slice: &[usize]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[usize]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[usize]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[usize]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl usizex4[src]

pub fn write_to_slice_aligned(self, slice: &mut [usize])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [usize])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [usize])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [usize])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl usizex4[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl usizex4[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl usizex4[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl usizex4[src]

pub fn eq(self, other: Self) -> msizex4[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> msizex4[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> msizex4[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> msizex4[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> msizex4[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> msizex4[src]

Lane-wise greater-than-or-equals comparison.

+

impl usizex4[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<usizex4>[src]

Returns a wrapper that implements PartialOrd.

+

impl usizex4[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<usizex4>[src]

Returns a wrapper that implements Ord.

+

impl usizex4[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl Add<Simd<[usize; 4]>> for usizex4[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<usize> for usizex4[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[usize; 4]>> for usizex4[src]

impl AddAssign<usize> for usizex4[src]

impl Binary for usizex4[src]

impl BitAnd<Simd<[usize; 4]>> for usizex4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<usize> for usizex4[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[usize; 4]>> for usizex4[src]

impl BitAndAssign<usize> for usizex4[src]

impl BitOr<Simd<[usize; 4]>> for usizex4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<usize> for usizex4[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[usize; 4]>> for usizex4[src]

impl BitOrAssign<usize> for usizex4[src]

impl BitXor<Simd<[usize; 4]>> for usizex4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<usize> for usizex4[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[usize; 4]>> for usizex4[src]

impl BitXorAssign<usize> for usizex4[src]

impl Debug for usizex4[src]

impl Default for usizex4[src]

impl Div<Simd<[usize; 4]>> for usizex4[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<usize> for usizex4[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[usize; 4]>> for usizex4[src]

impl DivAssign<usize> for usizex4[src]

impl Eq for usizex4[src]

impl From<[usize; 4]> for usizex4[src]

impl FromCast<Simd<[f32; 4]>> for usizex4[src]

impl FromCast<Simd<[f64; 4]>> for usizex4[src]

impl FromCast<Simd<[i128; 4]>> for usizex4[src]

impl FromCast<Simd<[i16; 4]>> for usizex4[src]

impl FromCast<Simd<[i32; 4]>> for usizex4[src]

impl FromCast<Simd<[i64; 4]>> for usizex4[src]

impl FromCast<Simd<[i8; 4]>> for usizex4[src]

impl FromCast<Simd<[isize; 4]>> for usizex4[src]

impl FromCast<Simd<[m128; 4]>> for usizex4[src]

impl FromCast<Simd<[m16; 4]>> for usizex4[src]

impl FromCast<Simd<[m32; 4]>> for usizex4[src]

impl FromCast<Simd<[m64; 4]>> for usizex4[src]

impl FromCast<Simd<[m8; 4]>> for usizex4[src]

impl FromCast<Simd<[msize; 4]>> for usizex4[src]

impl FromCast<Simd<[u128; 4]>> for usizex4[src]

impl FromCast<Simd<[u16; 4]>> for usizex4[src]

impl FromCast<Simd<[u32; 4]>> for usizex4[src]

impl FromCast<Simd<[u64; 4]>> for usizex4[src]

impl FromCast<Simd<[u8; 4]>> for usizex4[src]

impl Hash for usizex4[src]

impl LowerHex for usizex4[src]

impl Mul<Simd<[usize; 4]>> for usizex4[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<usize> for usizex4[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[usize; 4]>> for usizex4[src]

impl MulAssign<usize> for usizex4[src]

impl Not for usizex4[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl Octal for usizex4[src]

impl PartialEq<Simd<[usize; 4]>> for usizex4[src]

impl<'a> Product<&'a Simd<[usize; 4]>> for usizex4[src]

impl Product<Simd<[usize; 4]>> for usizex4[src]

impl Rem<Simd<[usize; 4]>> for usizex4[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<usize> for usizex4[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[usize; 4]>> for usizex4[src]

impl RemAssign<usize> for usizex4[src]

impl Shl<Simd<[usize; 4]>> for usizex4[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<u32> for usizex4[src]

type Output = Self

The resulting type after applying the << operator.

+

impl ShlAssign<Simd<[usize; 4]>> for usizex4[src]

impl ShlAssign<u32> for usizex4[src]

impl Shr<Simd<[usize; 4]>> for usizex4[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<u32> for usizex4[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl ShrAssign<Simd<[usize; 4]>> for usizex4[src]

impl ShrAssign<u32> for usizex4[src]

impl Simd for usizex4[src]

type Element = usize

Element type of the SIMD vector

+

type LanesType = [u32; 4]

The type: [u32; Self::N].

+

impl Sub<Simd<[usize; 4]>> for usizex4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<usize> for usizex4[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[usize; 4]>> for usizex4[src]

impl SubAssign<usize> for usizex4[src]

impl<'a> Sum<&'a Simd<[usize; 4]>> for usizex4[src]

impl Sum<Simd<[usize; 4]>> for usizex4[src]

impl UpperHex for usizex4[src]

\ No newline at end of file diff --git a/packed_simd/type.usizex8.html b/packed_simd/type.usizex8.html new file mode 100644 index 000000000..880e937ea --- /dev/null +++ b/packed_simd/type.usizex8.html @@ -0,0 +1,226 @@ +packed_simd::usizex8 - Rust

[−][src]Type Definition packed_simd::usizex8

type usizex8 = Simd<[usize; 8]>;

A vector with 8 usize lanes.

+

Implementations

impl usizex8[src]

pub const fn new(
    x0: usize,
    x1: usize,
    x2: usize,
    x3: usize,
    x4: usize,
    x5: usize,
    x6: usize,
    x7: usize
) -> Self[src]

Creates a new instance with each vector elements initialized +with the provided values.

+

pub const fn lanes() -> usize[src]

Returns the number of vector lanes.

+

pub const fn splat(value: usize) -> Self[src]

Constructs a new instance with each element initialized to +value.

+

pub fn extract(self, index: usize) -> usize[src]

Extracts the value at index.

+

Panics

+

If index >= Self::lanes().

+

pub unsafe fn extract_unchecked(self, index: usize) -> usize[src]

Extracts the value at index.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

#[must_use = + "replace does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub fn replace(self, index: usize, new_value: usize) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Panics

+

If index >= Self::lanes().

+

#[must_use = + "replace_unchecked does not modify the original value - \ + it returns a new vector with the value at `index` \ + replaced by `new_value`d"]pub unsafe fn replace_unchecked(self, index: usize, new_value: usize) -> Self[src]

Returns a new vector where the value at index is replaced by new_value.

+

Precondition

+

If index >= Self::lanes() the behavior is undefined.

+

impl usizex8[src]

pub fn rotate_left(self, n: usizex8) -> usizex8[src]

Shifts the bits of each lane to the left by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the end of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

pub fn rotate_right(self, n: usizex8) -> usizex8[src]

Shifts the bits of each lane to the right by the specified +amount in the corresponding lane of n, wrapping the +truncated bits to the beginning of the resulting integer.

+

Note: this is neither the same operation as << nor equivalent +to slice::rotate_left.

+

impl usizex8[src]

pub fn min(self, x: Self) -> Self[src]

Minimum of two vectors.

+

Returns a new vector containing the minimum value of each of +the input vector lanes.

+

pub fn max(self, x: Self) -> Self[src]

Maximum of two vectors.

+

Returns a new vector containing the maximum value of each of +the input vector lanes.

+

impl usizex8[src]

pub fn wrapping_sum(self) -> usize[src]

Horizontal wrapping sum of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

pub fn wrapping_product(self) -> usize[src]

Horizontal wrapping product of the vector elements.

+

The intrinsic performs a tree-reduction of the vector elements. +That is, for an 8 element vector:

+
+

((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))

+
+

If an operation overflows it returns the mathematical result +modulo 2^n where n is the number of times it overflows.

+

impl usizex8[src]

pub fn max_element(self) -> usize[src]

Largest vector element value.

+

pub fn min_element(self) -> usize[src]

Smallest vector element value.

+

impl usizex8[src]

pub fn and(self) -> usize[src]

Lane-wise bitwise and of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn or(self) -> usize[src]

Lane-wise bitwise or of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

pub fn xor(self) -> usize[src]

Lane-wise bitwise xor of the vector elements.

+

Note: if the vector has one lane, the first element of the +vector is returned.

+

impl usizex8[src]

pub fn from_slice_aligned(slice: &[usize]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary.

+

pub fn from_slice_unaligned(slice: &[usize]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn from_slice_aligned_unchecked(slice: &[usize]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not aligned +to an align_of::<Self>() boundary, the behavior is undefined.

+

pub unsafe fn from_slice_unaligned_unchecked(slice: &[usize]) -> Self[src]

Instantiates a new vector with the values of the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl usizex8[src]

pub fn write_to_slice_aligned(self, slice: &mut [usize])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary.

+

pub fn write_to_slice_unaligned(self, slice: &mut [usize])[src]

Writes the values of the vector to the slice.

+

Panics

+

If slice.len() < Self::lanes().

+

pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [usize])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() or &slice[0] is not +aligned to an align_of::<Self>() boundary, the behavior is +undefined.

+

pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [usize])[src]

Writes the values of the vector to the slice.

+

Precondition

+

If slice.len() < Self::lanes() the behavior is undefined.

+

impl usizex8[src]

pub fn swap_bytes(self) -> Self[src]

Reverses the byte order of the vector.

+

pub fn to_le(self) -> Self[src]

Converts self to little endian from the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn to_be(self) -> Self[src]

Converts self to big endian from the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

pub fn from_le(x: Self) -> Self[src]

Converts a vector from little endian to the target's endianness.

+

On little endian this is a no-op. On big endian the bytes are +swapped.

+

pub fn from_be(x: Self) -> Self[src]

Converts a vector from big endian to the target's endianness.

+

On big endian this is a no-op. On little endian the bytes are +swapped.

+

impl usizex8[src]

pub fn count_ones(self) -> Self[src]

Returns the number of ones in the binary representation of +the lanes of self.

+

pub fn count_zeros(self) -> Self[src]

Returns the number of zeros in the binary representation of +the lanes of self.

+

pub fn leading_zeros(self) -> Self[src]

Returns the number of leading zeros in the binary +representation of the lanes of self.

+

pub fn trailing_zeros(self) -> Self[src]

Returns the number of trailing zeros in the binary +representation of the lanes of self.

+

impl usizex8[src]

pub fn shuffle1_dyn<I>(self, indices: I) -> Self where
    Self: Shuffle1Dyn<Indices = I>, [src]

Shuffle vector elements according to indices.

+

impl usizex8[src]

pub fn eq(self, other: Self) -> msizex8[src]

Lane-wise equality comparison.

+

pub fn ne(self, other: Self) -> msizex8[src]

Lane-wise inequality comparison.

+

pub fn lt(self, other: Self) -> msizex8[src]

Lane-wise less-than comparison.

+

pub fn le(self, other: Self) -> msizex8[src]

Lane-wise less-than-or-equals comparison.

+

pub fn gt(self, other: Self) -> msizex8[src]

Lane-wise greater-than comparison.

+

pub fn ge(self, other: Self) -> msizex8[src]

Lane-wise greater-than-or-equals comparison.

+

impl usizex8[src]

pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<usizex8>[src]

Returns a wrapper that implements PartialOrd.

+

impl usizex8[src]

pub fn lex_ord(&self) -> LexicographicallyOrdered<usizex8>[src]

Returns a wrapper that implements Ord.

+

impl usizex8[src]

pub fn bitmask(self) -> u8[src]

Creates a bitmask with the MSB of each vector lane.

+

If the vector has less than 8 lanes, the bits that do not +correspond to any vector lanes are cleared.

+

Trait Implementations

impl Add<Simd<[usize; 8]>> for usizex8[src]

type Output = Self

The resulting type after applying the + operator.

+

impl Add<usize> for usizex8[src]

type Output = Self

The resulting type after applying the + operator.

+

impl AddAssign<Simd<[usize; 8]>> for usizex8[src]

impl AddAssign<usize> for usizex8[src]

impl Binary for usizex8[src]

impl BitAnd<Simd<[usize; 8]>> for usizex8[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAnd<usize> for usizex8[src]

type Output = Self

The resulting type after applying the & operator.

+

impl BitAndAssign<Simd<[usize; 8]>> for usizex8[src]

impl BitAndAssign<usize> for usizex8[src]

impl BitOr<Simd<[usize; 8]>> for usizex8[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOr<usize> for usizex8[src]

type Output = Self

The resulting type after applying the | operator.

+

impl BitOrAssign<Simd<[usize; 8]>> for usizex8[src]

impl BitOrAssign<usize> for usizex8[src]

impl BitXor<Simd<[usize; 8]>> for usizex8[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXor<usize> for usizex8[src]

type Output = Self

The resulting type after applying the ^ operator.

+

impl BitXorAssign<Simd<[usize; 8]>> for usizex8[src]

impl BitXorAssign<usize> for usizex8[src]

impl Debug for usizex8[src]

impl Default for usizex8[src]

impl Div<Simd<[usize; 8]>> for usizex8[src]

type Output = Self

The resulting type after applying the / operator.

+

impl Div<usize> for usizex8[src]

type Output = Self

The resulting type after applying the / operator.

+

impl DivAssign<Simd<[usize; 8]>> for usizex8[src]

impl DivAssign<usize> for usizex8[src]

impl Eq for usizex8[src]

impl From<[usize; 8]> for usizex8[src]

impl FromCast<Simd<[f32; 8]>> for usizex8[src]

impl FromCast<Simd<[f64; 8]>> for usizex8[src]

impl FromCast<Simd<[i16; 8]>> for usizex8[src]

impl FromCast<Simd<[i32; 8]>> for usizex8[src]

impl FromCast<Simd<[i64; 8]>> for usizex8[src]

impl FromCast<Simd<[i8; 8]>> for usizex8[src]

impl FromCast<Simd<[isize; 8]>> for usizex8[src]

impl FromCast<Simd<[m16; 8]>> for usizex8[src]

impl FromCast<Simd<[m32; 8]>> for usizex8[src]

impl FromCast<Simd<[m64; 8]>> for usizex8[src]

impl FromCast<Simd<[m8; 8]>> for usizex8[src]

impl FromCast<Simd<[msize; 8]>> for usizex8[src]

impl FromCast<Simd<[u16; 8]>> for usizex8[src]

impl FromCast<Simd<[u32; 8]>> for usizex8[src]

impl FromCast<Simd<[u64; 8]>> for usizex8[src]

impl FromCast<Simd<[u8; 8]>> for usizex8[src]

impl Hash for usizex8[src]

impl LowerHex for usizex8[src]

impl Mul<Simd<[usize; 8]>> for usizex8[src]

type Output = Self

The resulting type after applying the * operator.

+

impl Mul<usize> for usizex8[src]

type Output = Self

The resulting type after applying the * operator.

+

impl MulAssign<Simd<[usize; 8]>> for usizex8[src]

impl MulAssign<usize> for usizex8[src]

impl Not for usizex8[src]

type Output = Self

The resulting type after applying the ! operator.

+

impl Octal for usizex8[src]

impl PartialEq<Simd<[usize; 8]>> for usizex8[src]

impl<'a> Product<&'a Simd<[usize; 8]>> for usizex8[src]

impl Product<Simd<[usize; 8]>> for usizex8[src]

impl Rem<Simd<[usize; 8]>> for usizex8[src]

type Output = Self

The resulting type after applying the % operator.

+

impl Rem<usize> for usizex8[src]

type Output = Self

The resulting type after applying the % operator.

+

impl RemAssign<Simd<[usize; 8]>> for usizex8[src]

impl RemAssign<usize> for usizex8[src]

impl Shl<Simd<[usize; 8]>> for usizex8[src]

type Output = Self

The resulting type after applying the << operator.

+

impl Shl<u32> for usizex8[src]

type Output = Self

The resulting type after applying the << operator.

+

impl ShlAssign<Simd<[usize; 8]>> for usizex8[src]

impl ShlAssign<u32> for usizex8[src]

impl Shr<Simd<[usize; 8]>> for usizex8[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl Shr<u32> for usizex8[src]

type Output = Self

The resulting type after applying the >> operator.

+

impl ShrAssign<Simd<[usize; 8]>> for usizex8[src]

impl ShrAssign<u32> for usizex8[src]

impl Simd for usizex8[src]

type Element = usize

Element type of the SIMD vector

+

type LanesType = [u32; 8]

The type: [u32; Self::N].

+

impl Sub<Simd<[usize; 8]>> for usizex8[src]

type Output = Self

The resulting type after applying the - operator.

+

impl Sub<usize> for usizex8[src]

type Output = Self

The resulting type after applying the - operator.

+

impl SubAssign<Simd<[usize; 8]>> for usizex8[src]

impl SubAssign<usize> for usizex8[src]

impl<'a> Sum<&'a Simd<[usize; 8]>> for usizex8[src]

impl Sum<Simd<[usize; 8]>> for usizex8[src]

impl UpperHex for usizex8[src]

\ No newline at end of file diff --git a/packed_simd/v128/type.f32x4.html b/packed_simd/v128/type.f32x4.html new file mode 100644 index 000000000..fcff403b8 --- /dev/null +++ b/packed_simd/v128/type.f32x4.html @@ -0,0 +1,10 @@ + + + + + + +

Redirecting to ../../packed_simd/type.f32x4.html...

+ + + \ No newline at end of file diff --git a/packed_simd/v128/type.f64x2.html b/packed_simd/v128/type.f64x2.html new file mode 100644 index 000000000..a3f21f33e --- /dev/null +++ b/packed_simd/v128/type.f64x2.html @@ -0,0 +1,10 @@ + + + + + + +

Redirecting to ../../packed_simd/type.f64x2.html...

+ + + \ No newline at end of file diff --git a/packed_simd/v128/type.i128x1.html b/packed_simd/v128/type.i128x1.html new file mode 100644 index 000000000..2a0b8cb13 --- /dev/null +++ b/packed_simd/v128/type.i128x1.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/packed_simd/v128/type.i16x8.html b/packed_simd/v128/type.i16x8.html new file mode 100644 index 000000000..b853d0ee0 --- /dev/null +++ b/packed_simd/v128/type.i16x8.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/packed_simd/v128/type.i32x4.html b/packed_simd/v128/type.i32x4.html new file mode 100644 index 000000000..448205330 --- /dev/null +++ b/packed_simd/v128/type.i32x4.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/packed_simd/v128/type.i64x2.html b/packed_simd/v128/type.i64x2.html new file mode 100644 index 000000000..8e018f5c2 --- /dev/null +++ b/packed_simd/v128/type.i64x2.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/packed_simd/v128/type.i8x16.html b/packed_simd/v128/type.i8x16.html new file mode 100644 index 000000000..c227729ff --- /dev/null +++ b/packed_simd/v128/type.i8x16.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/packed_simd/v128/type.m128x1.html b/packed_simd/v128/type.m128x1.html new file mode 100644 index 000000000..8e430ef8d --- /dev/null +++ b/packed_simd/v128/type.m128x1.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/packed_simd/v128/type.m16x8.html b/packed_simd/v128/type.m16x8.html new file mode 100644 index 000000000..38609e661 --- /dev/null +++ b/packed_simd/v128/type.m16x8.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/packed_simd/v128/type.m32x4.html b/packed_simd/v128/type.m32x4.html new file mode 100644 index 000000000..5f5ed9ded --- /dev/null +++ b/packed_simd/v128/type.m32x4.html @@ -0,0 +1,10 @@ + + + + + + +

Redirecting to ../../packed_simd/type.m32x4.html...

+ + + \ No newline at end of file diff --git a/packed_simd/v128/type.m64x2.html b/packed_simd/v128/type.m64x2.html new file mode 100644 index 000000000..ae12b8212 --- /dev/null +++ b/packed_simd/v128/type.m64x2.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/packed_simd/v128/type.m8x16.html b/packed_simd/v128/type.m8x16.html new file mode 100644 index 000000000..b9374ec8a --- /dev/null +++ b/packed_simd/v128/type.m8x16.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/packed_simd/v128/type.u128x1.html b/packed_simd/v128/type.u128x1.html new file mode 100644 index 000000000..c31b92a58 --- /dev/null +++ b/packed_simd/v128/type.u128x1.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/packed_simd/v128/type.u16x8.html b/packed_simd/v128/type.u16x8.html new file mode 100644 index 000000000..0aab06016 --- /dev/null +++ b/packed_simd/v128/type.u16x8.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/packed_simd/v128/type.u32x4.html b/packed_simd/v128/type.u32x4.html new file mode 100644 index 000000000..de8f251e2 --- /dev/null +++ b/packed_simd/v128/type.u32x4.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/packed_simd/v128/type.u64x2.html b/packed_simd/v128/type.u64x2.html new file mode 100644 index 000000000..1f3006e4f --- /dev/null +++ b/packed_simd/v128/type.u64x2.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/packed_simd/v128/type.u8x16.html b/packed_simd/v128/type.u8x16.html new file mode 100644 index 000000000..7daeed316 --- /dev/null +++ b/packed_simd/v128/type.u8x16.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/packed_simd/v16/type.i8x2.html b/packed_simd/v16/type.i8x2.html new file mode 100644 index 000000000..93b857f5f --- /dev/null +++ b/packed_simd/v16/type.i8x2.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/packed_simd/v16/type.m8x2.html b/packed_simd/v16/type.m8x2.html new file mode 100644 index 000000000..804a4f9f1 --- /dev/null +++ b/packed_simd/v16/type.m8x2.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/packed_simd/v16/type.u8x2.html b/packed_simd/v16/type.u8x2.html new file mode 100644 index 000000000..ab91689f9 --- /dev/null +++ b/packed_simd/v16/type.u8x2.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/packed_simd/v256/type.f32x8.html b/packed_simd/v256/type.f32x8.html new file mode 100644 index 000000000..b52b27634 --- /dev/null +++ b/packed_simd/v256/type.f32x8.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/packed_simd/v256/type.f64x4.html b/packed_simd/v256/type.f64x4.html new file mode 100644 index 000000000..b1428862a --- /dev/null +++ b/packed_simd/v256/type.f64x4.html @@ -0,0 +1,10 @@ + + + + + + +

Redirecting to ../../packed_simd/type.f64x4.html...

+ + + \ No newline at end of file diff --git a/packed_simd/v256/type.i128x2.html b/packed_simd/v256/type.i128x2.html new file mode 100644 index 000000000..28046f954 --- /dev/null +++ b/packed_simd/v256/type.i128x2.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/packed_simd/v256/type.i16x16.html b/packed_simd/v256/type.i16x16.html new file mode 100644 index 000000000..4c0684f0f --- /dev/null +++ b/packed_simd/v256/type.i16x16.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/packed_simd/v256/type.i32x8.html b/packed_simd/v256/type.i32x8.html new file mode 100644 index 000000000..30bf10d3c --- /dev/null +++ b/packed_simd/v256/type.i32x8.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/packed_simd/v256/type.i64x4.html b/packed_simd/v256/type.i64x4.html new file mode 100644 index 000000000..4af141b72 --- /dev/null +++ b/packed_simd/v256/type.i64x4.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/packed_simd/v256/type.i8x32.html b/packed_simd/v256/type.i8x32.html new file mode 100644 index 000000000..163d6bbaa --- /dev/null +++ b/packed_simd/v256/type.i8x32.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/packed_simd/v256/type.m128x2.html b/packed_simd/v256/type.m128x2.html new file mode 100644 index 000000000..3fb9d4f0f --- /dev/null +++ b/packed_simd/v256/type.m128x2.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/packed_simd/v256/type.m16x16.html b/packed_simd/v256/type.m16x16.html new file mode 100644 index 000000000..7cadc6f95 --- /dev/null +++ b/packed_simd/v256/type.m16x16.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/packed_simd/v256/type.m32x8.html b/packed_simd/v256/type.m32x8.html new file mode 100644 index 000000000..5f387ea36 --- /dev/null +++ b/packed_simd/v256/type.m32x8.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/packed_simd/v256/type.m64x4.html b/packed_simd/v256/type.m64x4.html new file mode 100644 index 000000000..f98afaa3c --- /dev/null +++ b/packed_simd/v256/type.m64x4.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/packed_simd/v256/type.m8x32.html b/packed_simd/v256/type.m8x32.html new file mode 100644 index 000000000..04d2be16d --- /dev/null +++ b/packed_simd/v256/type.m8x32.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/packed_simd/v256/type.u128x2.html b/packed_simd/v256/type.u128x2.html new file mode 100644 index 000000000..e7411f397 --- /dev/null +++ b/packed_simd/v256/type.u128x2.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/packed_simd/v256/type.u16x16.html b/packed_simd/v256/type.u16x16.html new file mode 100644 index 000000000..b62145000 --- /dev/null +++ b/packed_simd/v256/type.u16x16.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/packed_simd/v256/type.u32x8.html b/packed_simd/v256/type.u32x8.html new file mode 100644 index 000000000..02bd446be --- /dev/null +++ b/packed_simd/v256/type.u32x8.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/packed_simd/v256/type.u64x4.html b/packed_simd/v256/type.u64x4.html new file mode 100644 index 000000000..a2d2ab4e3 --- /dev/null +++ b/packed_simd/v256/type.u64x4.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/packed_simd/v256/type.u8x32.html b/packed_simd/v256/type.u8x32.html new file mode 100644 index 000000000..2fd2a47e8 --- /dev/null +++ b/packed_simd/v256/type.u8x32.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/packed_simd/v32/type.i16x2.html b/packed_simd/v32/type.i16x2.html new file mode 100644 index 000000000..7629009fa --- /dev/null +++ b/packed_simd/v32/type.i16x2.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/packed_simd/v32/type.i8x4.html b/packed_simd/v32/type.i8x4.html new file mode 100644 index 000000000..12022bf58 --- /dev/null +++ b/packed_simd/v32/type.i8x4.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/packed_simd/v32/type.m16x2.html b/packed_simd/v32/type.m16x2.html new file mode 100644 index 000000000..053181538 --- /dev/null +++ b/packed_simd/v32/type.m16x2.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/packed_simd/v32/type.m8x4.html b/packed_simd/v32/type.m8x4.html new file mode 100644 index 000000000..96bb51366 --- /dev/null +++ b/packed_simd/v32/type.m8x4.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/packed_simd/v32/type.u16x2.html b/packed_simd/v32/type.u16x2.html new file mode 100644 index 000000000..0584a1d5f --- /dev/null +++ b/packed_simd/v32/type.u16x2.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/packed_simd/v512/type.f32x16.html b/packed_simd/v512/type.f32x16.html new file mode 100644 index 000000000..5026be32b --- /dev/null +++ b/packed_simd/v512/type.f32x16.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/packed_simd/v512/type.f64x8.html b/packed_simd/v512/type.f64x8.html new file mode 100644 index 000000000..738e1f8bc --- /dev/null +++ b/packed_simd/v512/type.f64x8.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/packed_simd/v512/type.i128x4.html b/packed_simd/v512/type.i128x4.html new file mode 100644 index 000000000..20cb37545 --- /dev/null +++ b/packed_simd/v512/type.i128x4.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/packed_simd/v512/type.i16x32.html b/packed_simd/v512/type.i16x32.html new file mode 100644 index 000000000..c40e2cc65 --- /dev/null +++ b/packed_simd/v512/type.i16x32.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/packed_simd/v512/type.i32x16.html b/packed_simd/v512/type.i32x16.html new file mode 100644 index 000000000..d32ba0297 --- /dev/null +++ b/packed_simd/v512/type.i32x16.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/packed_simd/v512/type.i64x8.html b/packed_simd/v512/type.i64x8.html new file mode 100644 index 000000000..1a1e04c3d --- /dev/null +++ b/packed_simd/v512/type.i64x8.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/packed_simd/v512/type.i8x64.html b/packed_simd/v512/type.i8x64.html new file mode 100644 index 000000000..01ca5e3be --- /dev/null +++ b/packed_simd/v512/type.i8x64.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/packed_simd/v512/type.m128x4.html b/packed_simd/v512/type.m128x4.html new file mode 100644 index 000000000..b50990b02 --- /dev/null +++ b/packed_simd/v512/type.m128x4.html @@ -0,0 +1,10 @@ + + + + + + +

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+ + + \ No newline at end of file diff --git a/packed_simd/v512/type.m16x32.html b/packed_simd/v512/type.m16x32.html new file mode 100644 index 000000000..a0df42e7d --- /dev/null +++ b/packed_simd/v512/type.m16x32.html @@ -0,0 +1,10 @@ + + + + + + +

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+} diff --git a/perf-guide/ayu-highlight.css b/perf-guide/ayu-highlight.css new file mode 100644 index 000000000..0c45c6f14 --- /dev/null +++ b/perf-guide/ayu-highlight.css @@ -0,0 +1,79 @@ +/* +Based off of the Ayu theme +Original by Dempfi (https://github.com/dempfi/ayu) +*/ + +.hljs { + display: block; + overflow-x: auto; + background: #191f26; + color: #e6e1cf; + padding: 0.5em; +} + +.hljs-comment, +.hljs-quote { + color: #5c6773; + font-style: italic; +} + +.hljs-variable, +.hljs-template-variable, +.hljs-attribute, +.hljs-attr, +.hljs-regexp, +.hljs-link, +.hljs-selector-id, +.hljs-selector-class { + color: #ff7733; +} + +.hljs-number, +.hljs-meta, +.hljs-builtin-name, +.hljs-literal, +.hljs-type, +.hljs-params { + color: #ffee99; +} + +.hljs-string, +.hljs-bullet { + color: #b8cc52; +} + +.hljs-title, +.hljs-built_in, +.hljs-section { + color: #ffb454; +} + +.hljs-keyword, +.hljs-selector-tag, +.hljs-symbol { + color: #ff7733; +} + +.hljs-name { + color: #36a3d9; +} + +.hljs-tag { + color: #00568d; +} + +.hljs-emphasis { + font-style: italic; +} + +.hljs-strong { + font-weight: bold; +} + +.hljs-addition { + color: #91b362; +} + +.hljs-deletion { + color: #d96c75; +} diff --git a/perf-guide/book.js b/perf-guide/book.js new file mode 100644 index 000000000..049505fc6 --- /dev/null +++ b/perf-guide/book.js @@ -0,0 +1,660 @@ +"use strict"; + +// Fix back button cache problem +window.onunload = function () { }; + +// Global variable, shared between modules +function playground_text(playground) { + let code_block = playground.querySelector("code"); + + if (window.ace && code_block.classList.contains("editable")) { + let editor = window.ace.edit(code_block); + return editor.getValue(); + } else { + return code_block.textContent; + } +} + +(function codeSnippets() { + function fetch_with_timeout(url, options, timeout = 6000) { + return Promise.race([ + fetch(url, options), + new Promise((_, reject) => setTimeout(() => reject(new Error('timeout')), timeout)) + ]); + } + + var playgrounds = Array.from(document.querySelectorAll(".playground")); + if (playgrounds.length > 0) { + fetch_with_timeout("https://play.rust-lang.org/meta/crates", { + headers: { + 'Content-Type': "application/json", + }, + method: 'POST', + mode: 'cors', + }) + .then(response => response.json()) + .then(response => { + // get list of crates available in the rust playground + let playground_crates = response.crates.map(item => item["id"]); + playgrounds.forEach(block => handle_crate_list_update(block, playground_crates)); + }); + } + + function handle_crate_list_update(playground_block, playground_crates) { + // update the play buttons after receiving the response + update_play_button(playground_block, playground_crates); + + // and install on change listener to dynamically update ACE editors + if (window.ace) { + let code_block = playground_block.querySelector("code"); + if (code_block.classList.contains("editable")) { + let editor = window.ace.edit(code_block); + editor.addEventListener("change", function (e) { + update_play_button(playground_block, playground_crates); + }); + // add Ctrl-Enter command to execute rust code + editor.commands.addCommand({ + name: "run", + bindKey: { + win: "Ctrl-Enter", + mac: "Ctrl-Enter" + }, + exec: _editor => run_rust_code(playground_block) + }); + } + } + } + + // updates the visibility of play button based on `no_run` class and + // used crates vs ones available on http://play.rust-lang.org + function update_play_button(pre_block, playground_crates) { + var play_button = pre_block.querySelector(".play-button"); + + // skip if code is `no_run` + if (pre_block.querySelector('code').classList.contains("no_run")) { + play_button.classList.add("hidden"); + return; + } + + // get list of `extern crate`'s from snippet + var txt = playground_text(pre_block); + var re = /extern\s+crate\s+([a-zA-Z_0-9]+)\s*;/g; + var snippet_crates = []; + var item; + while (item = re.exec(txt)) { + snippet_crates.push(item[1]); + } + + // check if all used crates are available on play.rust-lang.org + var all_available = snippet_crates.every(function (elem) { + return playground_crates.indexOf(elem) > -1; + }); + + if (all_available) { + play_button.classList.remove("hidden"); + } else { + play_button.classList.add("hidden"); + } + } + + function run_rust_code(code_block) { + var result_block = code_block.querySelector(".result"); + if (!result_block) { + result_block = document.createElement('code'); + result_block.className = 'result hljs language-bash'; + + code_block.append(result_block); + } + + let text = playground_text(code_block); + let classes = code_block.querySelector('code').classList; + let has_2018 = classes.contains("edition2018"); + let edition = has_2018 ? "2018" : "2015"; + + var params = { + version: "stable", + optimize: "0", + code: text, + edition: edition + }; + + if (text.indexOf("#![feature") !== -1) { + params.version = "nightly"; + } + + result_block.innerText = "Running..."; + + fetch_with_timeout("https://play.rust-lang.org/evaluate.json", { + headers: { + 'Content-Type': "application/json", + }, + method: 'POST', + mode: 'cors', + body: JSON.stringify(params) + }) + .then(response => response.json()) + .then(response => result_block.innerText = response.result) + .catch(error => result_block.innerText = "Playground Communication: " + error.message); + } + + // Syntax highlighting Configuration + hljs.configure({ + tabReplace: ' ', // 4 spaces + languages: [], // Languages used for auto-detection + }); + + let code_nodes = Array + .from(document.querySelectorAll('code')) + // Don't highlight `inline code` blocks in headers. + .filter(function (node) {return !node.parentElement.classList.contains("header"); }); + + if (window.ace) { + // language-rust class needs to be removed for editable + // blocks or highlightjs will capture events + Array + .from(document.querySelectorAll('code.editable')) + .forEach(function (block) { block.classList.remove('language-rust'); }); + + Array + .from(document.querySelectorAll('code:not(.editable)')) + .forEach(function (block) { hljs.highlightBlock(block); }); + } else { + code_nodes.forEach(function (block) { hljs.highlightBlock(block); }); + } + + // Adding the hljs class gives code blocks the color css + // even if highlighting doesn't apply + code_nodes.forEach(function (block) { block.classList.add('hljs'); }); + + Array.from(document.querySelectorAll("code.language-rust")).forEach(function (block) { + + var lines = Array.from(block.querySelectorAll('.boring')); + // If no lines were hidden, return + if (!lines.length) { return; } + block.classList.add("hide-boring"); + + var buttons = document.createElement('div'); + buttons.className = 'buttons'; + buttons.innerHTML = ""; + + // add expand button + var pre_block = block.parentNode; + pre_block.insertBefore(buttons, pre_block.firstChild); + + pre_block.querySelector('.buttons').addEventListener('click', function (e) { + if (e.target.classList.contains('fa-expand')) { + e.target.classList.remove('fa-expand'); + e.target.classList.add('fa-compress'); + e.target.title = 'Hide lines'; + e.target.setAttribute('aria-label', e.target.title); + + block.classList.remove('hide-boring'); + } else if (e.target.classList.contains('fa-compress')) { + e.target.classList.remove('fa-compress'); + e.target.classList.add('fa-expand'); + e.target.title = 'Show hidden lines'; + e.target.setAttribute('aria-label', e.target.title); + + block.classList.add('hide-boring'); + } + }); + }); + + if (window.playground_copyable) { + Array.from(document.querySelectorAll('pre code')).forEach(function (block) { + var pre_block = block.parentNode; + if (!pre_block.classList.contains('playground')) { + var buttons = pre_block.querySelector(".buttons"); + if (!buttons) { + buttons = document.createElement('div'); + buttons.className = 'buttons'; + pre_block.insertBefore(buttons, pre_block.firstChild); + } + + var clipButton = document.createElement('button'); + clipButton.className = 'fa fa-copy clip-button'; + clipButton.title = 'Copy to clipboard'; + clipButton.setAttribute('aria-label', clipButton.title); + clipButton.innerHTML = ''; + + buttons.insertBefore(clipButton, buttons.firstChild); + } + }); + } + + // Process playground code blocks + Array.from(document.querySelectorAll(".playground")).forEach(function (pre_block) { + // Add play button + var buttons = pre_block.querySelector(".buttons"); + if (!buttons) { + buttons = document.createElement('div'); + buttons.className = 'buttons'; + pre_block.insertBefore(buttons, pre_block.firstChild); + } + + var runCodeButton = document.createElement('button'); + runCodeButton.className = 'fa fa-play play-button'; + runCodeButton.hidden = true; + runCodeButton.title = 'Run this code'; + runCodeButton.setAttribute('aria-label', runCodeButton.title); + + buttons.insertBefore(runCodeButton, buttons.firstChild); + runCodeButton.addEventListener('click', function (e) { + run_rust_code(pre_block); + }); + + if (window.playground_copyable) { + var copyCodeClipboardButton = document.createElement('button'); + copyCodeClipboardButton.className = 'fa fa-copy clip-button'; + copyCodeClipboardButton.innerHTML = ''; + copyCodeClipboardButton.title = 'Copy to clipboard'; + copyCodeClipboardButton.setAttribute('aria-label', copyCodeClipboardButton.title); + + buttons.insertBefore(copyCodeClipboardButton, buttons.firstChild); + } + + let code_block = pre_block.querySelector("code"); + if (window.ace && code_block.classList.contains("editable")) { + var undoChangesButton = document.createElement('button'); + undoChangesButton.className = 'fa fa-history reset-button'; + undoChangesButton.title = 'Undo changes'; + undoChangesButton.setAttribute('aria-label', undoChangesButton.title); + + buttons.insertBefore(undoChangesButton, buttons.firstChild); + + undoChangesButton.addEventListener('click', function () { + let editor = window.ace.edit(code_block); + editor.setValue(editor.originalCode); + editor.clearSelection(); + }); + } + }); +})(); + +(function themes() { + var html = document.querySelector('html'); + var themeToggleButton = document.getElementById('theme-toggle'); + var themePopup = document.getElementById('theme-list'); + var themeColorMetaTag = document.querySelector('meta[name="theme-color"]'); + var stylesheets = { + ayuHighlight: document.querySelector("[href$='ayu-highlight.css']"), + tomorrowNight: document.querySelector("[href$='tomorrow-night.css']"), + highlight: document.querySelector("[href$='highlight.css']"), + }; + + function showThemes() { + themePopup.style.display = 'block'; + themeToggleButton.setAttribute('aria-expanded', true); + themePopup.querySelector("button#" + get_theme()).focus(); + } + + function hideThemes() { + themePopup.style.display = 'none'; + themeToggleButton.setAttribute('aria-expanded', false); + themeToggleButton.focus(); + } + + function get_theme() { + var theme; + try { theme = localStorage.getItem('mdbook-theme'); } catch (e) { } + if (theme === null || theme === undefined) { + return default_theme; + } else { + return theme; + } + } + + function set_theme(theme, store = true) { + let ace_theme; + + if (theme == 'coal' || theme == 'navy') { + stylesheets.ayuHighlight.disabled = true; + stylesheets.tomorrowNight.disabled = false; + stylesheets.highlight.disabled = true; + + ace_theme = "ace/theme/tomorrow_night"; + } else if (theme == 'ayu') { + stylesheets.ayuHighlight.disabled = false; + stylesheets.tomorrowNight.disabled = true; + stylesheets.highlight.disabled = true; + ace_theme = "ace/theme/tomorrow_night"; + } else { + stylesheets.ayuHighlight.disabled = true; + stylesheets.tomorrowNight.disabled = true; + stylesheets.highlight.disabled = false; + ace_theme = "ace/theme/dawn"; + } + + setTimeout(function () { + themeColorMetaTag.content = getComputedStyle(document.body).backgroundColor; + }, 1); + + if (window.ace && window.editors) { + window.editors.forEach(function (editor) { + editor.setTheme(ace_theme); + }); + } + + var previousTheme = get_theme(); + + if (store) { + try { localStorage.setItem('mdbook-theme', theme); } catch (e) { } + } + + html.classList.remove(previousTheme); + html.classList.add(theme); + } + + // Set theme + var theme = get_theme(); + + set_theme(theme, false); + + themeToggleButton.addEventListener('click', function () { + if (themePopup.style.display === 'block') { + hideThemes(); + } else { + showThemes(); + } + }); + + themePopup.addEventListener('click', function (e) { + var theme = e.target.id || e.target.parentElement.id; + set_theme(theme); + }); + + themePopup.addEventListener('focusout', function(e) { + // e.relatedTarget is null in Safari and Firefox on macOS (see workaround below) + if (!!e.relatedTarget && !themeToggleButton.contains(e.relatedTarget) && !themePopup.contains(e.relatedTarget)) { + hideThemes(); + } + }); + + // Should not be needed, but it works around an issue on macOS & iOS: https://github.com/rust-lang/mdBook/issues/628 + document.addEventListener('click', function(e) { + if (themePopup.style.display === 'block' && !themeToggleButton.contains(e.target) && !themePopup.contains(e.target)) { + hideThemes(); + } + }); + + document.addEventListener('keydown', function (e) { + if (e.altKey || e.ctrlKey || e.metaKey || e.shiftKey) { return; } + if (!themePopup.contains(e.target)) { return; } + + switch (e.key) { + case 'Escape': + e.preventDefault(); + hideThemes(); + break; + case 'ArrowUp': + e.preventDefault(); + var li = document.activeElement.parentElement; + if (li && li.previousElementSibling) { + li.previousElementSibling.querySelector('button').focus(); + } + break; + case 'ArrowDown': + e.preventDefault(); + var li = document.activeElement.parentElement; + if (li && li.nextElementSibling) { + li.nextElementSibling.querySelector('button').focus(); + } + break; + case 'Home': + e.preventDefault(); + themePopup.querySelector('li:first-child button').focus(); + break; + case 'End': + e.preventDefault(); + themePopup.querySelector('li:last-child button').focus(); + break; + } + }); +})(); + +(function sidebar() { + var html = document.querySelector("html"); + var sidebar = document.getElementById("sidebar"); + var sidebarLinks = document.querySelectorAll('#sidebar a'); + var sidebarToggleButton = document.getElementById("sidebar-toggle"); + var sidebarResizeHandle = document.getElementById("sidebar-resize-handle"); + var firstContact = null; + + function showSidebar() { + html.classList.remove('sidebar-hidden') + html.classList.add('sidebar-visible'); + Array.from(sidebarLinks).forEach(function (link) { + link.setAttribute('tabIndex', 0); + }); + sidebarToggleButton.setAttribute('aria-expanded', true); + sidebar.setAttribute('aria-hidden', false); + try { localStorage.setItem('mdbook-sidebar', 'visible'); } catch (e) { } + } + + + var sidebarAnchorToggles = document.querySelectorAll('#sidebar a.toggle'); + + function toggleSection(ev) { + ev.currentTarget.parentElement.classList.toggle('expanded'); + } + + Array.from(sidebarAnchorToggles).forEach(function (el) { + el.addEventListener('click', toggleSection); + }); + + function hideSidebar() { + html.classList.remove('sidebar-visible') + html.classList.add('sidebar-hidden'); + Array.from(sidebarLinks).forEach(function (link) { + link.setAttribute('tabIndex', -1); + }); + sidebarToggleButton.setAttribute('aria-expanded', false); + sidebar.setAttribute('aria-hidden', true); + try { localStorage.setItem('mdbook-sidebar', 'hidden'); } catch (e) { } + } + + // Toggle sidebar + sidebarToggleButton.addEventListener('click', function sidebarToggle() { + if (html.classList.contains("sidebar-hidden")) { + var current_width = parseInt( + document.documentElement.style.getPropertyValue('--sidebar-width'), 10); + if (current_width < 150) { + document.documentElement.style.setProperty('--sidebar-width', '150px'); + } + showSidebar(); + } else if (html.classList.contains("sidebar-visible")) { + hideSidebar(); + } else { + if (getComputedStyle(sidebar)['transform'] === 'none') { + hideSidebar(); + } else { + showSidebar(); + } + } + }); + + sidebarResizeHandle.addEventListener('mousedown', initResize, false); + + function initResize(e) { + window.addEventListener('mousemove', resize, false); + window.addEventListener('mouseup', stopResize, false); + html.classList.add('sidebar-resizing'); + } + function resize(e) { + var pos = (e.clientX - sidebar.offsetLeft); + if (pos < 20) { + hideSidebar(); + } else { + if (html.classList.contains("sidebar-hidden")) { + showSidebar(); + } + pos = Math.min(pos, window.innerWidth - 100); + document.documentElement.style.setProperty('--sidebar-width', pos + 'px'); + } + } + //on mouseup remove windows functions mousemove & mouseup + function stopResize(e) { + html.classList.remove('sidebar-resizing'); + window.removeEventListener('mousemove', resize, false); + window.removeEventListener('mouseup', stopResize, false); + } + + document.addEventListener('touchstart', function (e) { + firstContact = { + x: e.touches[0].clientX, + time: Date.now() + }; + }, { passive: true }); + + document.addEventListener('touchmove', function (e) { + if (!firstContact) + return; + + var curX = e.touches[0].clientX; + var xDiff = curX - firstContact.x, + tDiff = Date.now() - firstContact.time; + + if (tDiff < 250 && Math.abs(xDiff) >= 150) { + if (xDiff >= 0 && firstContact.x < Math.min(document.body.clientWidth * 0.25, 300)) + showSidebar(); + else if (xDiff < 0 && curX < 300) + hideSidebar(); + + firstContact = null; + } + }, { passive: true }); + + // Scroll sidebar to current active section + var activeSection = document.getElementById("sidebar").querySelector(".active"); + if (activeSection) { + // https://developer.mozilla.org/en-US/docs/Web/API/Element/scrollIntoView + activeSection.scrollIntoView({ block: 'center' }); + } +})(); + +(function chapterNavigation() { + document.addEventListener('keydown', function (e) { + if (e.altKey || e.ctrlKey || e.metaKey || e.shiftKey) { return; } + if (window.search && window.search.hasFocus()) { return; } + + switch (e.key) { + case 'ArrowRight': + e.preventDefault(); + var nextButton = document.querySelector('.nav-chapters.next'); + if (nextButton) { + window.location.href = nextButton.href; + } + break; + case 'ArrowLeft': + e.preventDefault(); + var previousButton = document.querySelector('.nav-chapters.previous'); + if (previousButton) { + window.location.href = previousButton.href; + } + break; + } + }); +})(); + +(function clipboard() { + var clipButtons = document.querySelectorAll('.clip-button'); + + function hideTooltip(elem) { + elem.firstChild.innerText = ""; + elem.className = 'fa fa-copy clip-button'; + } + + function showTooltip(elem, msg) { + elem.firstChild.innerText = msg; + elem.className = 'fa fa-copy tooltipped'; + } + + var clipboardSnippets = new ClipboardJS('.clip-button', { + text: function (trigger) { + hideTooltip(trigger); + let playground = trigger.closest("pre"); + return playground_text(playground); + } + }); + + Array.from(clipButtons).forEach(function (clipButton) { + clipButton.addEventListener('mouseout', function (e) { + hideTooltip(e.currentTarget); + }); + }); + + clipboardSnippets.on('success', function (e) { + e.clearSelection(); + showTooltip(e.trigger, "Copied!"); + }); + + clipboardSnippets.on('error', function (e) { + showTooltip(e.trigger, "Clipboard error!"); + }); +})(); + +(function scrollToTop () { + var menuTitle = document.querySelector('.menu-title'); + + menuTitle.addEventListener('click', function () { + document.scrollingElement.scrollTo({ top: 0, behavior: 'smooth' }); + }); +})(); + +(function controllMenu() { + var menu = document.getElementById('menu-bar'); + + (function controllPosition() { + var scrollTop = document.scrollingElement.scrollTop; + var prevScrollTop = scrollTop; + var minMenuY = -menu.clientHeight - 50; + // When the script loads, the page can be at any scroll (e.g. if you reforesh it). + menu.style.top = scrollTop + 'px'; + // Same as parseInt(menu.style.top.slice(0, -2), but faster + var topCache = menu.style.top.slice(0, -2); + menu.classList.remove('sticky'); + var stickyCache = false; // Same as menu.classList.contains('sticky'), but faster + document.addEventListener('scroll', function () { + scrollTop = Math.max(document.scrollingElement.scrollTop, 0); + // `null` means that it doesn't need to be updated + var nextSticky = null; + var nextTop = null; + var scrollDown = scrollTop > prevScrollTop; + var menuPosAbsoluteY = topCache - scrollTop; + if (scrollDown) { + nextSticky = false; + if (menuPosAbsoluteY > 0) { + nextTop = prevScrollTop; + } + } else { + if (menuPosAbsoluteY > 0) { + nextSticky = true; + } else if (menuPosAbsoluteY < minMenuY) { + nextTop = prevScrollTop + minMenuY; + } + } + if (nextSticky === true && stickyCache === false) { + menu.classList.add('sticky'); + stickyCache = true; + } else if (nextSticky === false && stickyCache === true) { + menu.classList.remove('sticky'); + stickyCache = false; + } + if (nextTop !== null) { + menu.style.top = nextTop + 'px'; + topCache = nextTop; + } + prevScrollTop = scrollTop; + }, { passive: true }); + })(); + (function controllBorder() { + menu.classList.remove('bordered'); + document.addEventListener('scroll', function () { + if (menu.offsetTop === 0) { + menu.classList.remove('bordered'); + } else { + menu.classList.add('bordered'); + } + }, { passive: true }); + })(); +})(); diff --git a/perf-guide/bound_checks.html b/perf-guide/bound_checks.html new file mode 100644 index 000000000..32a350839 --- /dev/null +++ b/perf-guide/bound_checks.html @@ -0,0 +1,246 @@ + + + + + + Bounds checking - Rust SIMD Performance Guide + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ +
+ + + + + + + + + + + +
+
+

Bounds checking

+

Reading and writing packed vectors to/from slices is checked by default. +Independently of the configuration options used, the safe functions:

+
    +
  • Simd<[T; N]>::from_slice_aligned(& s[..])
    • +
  • Simd<[T; N]>::write_to_slice_aligned(&mut s[..])
    • +
+

always check that:

+
    +
  • the slice is big enough to hold the vector
    • +
  • the slice is suitably aligned to perform an aligned load/store for a Simd<[T; N]> (this alignment is often much larger than that of T).
    • +
+

There are _unaligned versions that use unaligned load and stores, as well as +unsafe _unchecked that do not perform any checks iff debug-assertions = false / debug = false. That is, the _unchecked methods do still assert size +and alignment in debug builds and could also do so in release builds depending +on the configuration options.

+

These assertions do often significantly impact performance and you should be +aware of them.

+ +
+ + +
+
+ + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/perf-guide/clipboard.min.js b/perf-guide/clipboard.min.js new file mode 100644 index 000000000..02c549e35 --- /dev/null +++ b/perf-guide/clipboard.min.js @@ -0,0 +1,7 @@ +/*! + * clipboard.js v2.0.4 + * https://zenorocha.github.io/clipboard.js + * + * Licensed MIT © Zeno Rocha + */ +!function(t,e){"object"==typeof exports&&"object"==typeof module?module.exports=e():"function"==typeof define&&define.amd?define([],e):"object"==typeof exports?exports.ClipboardJS=e():t.ClipboardJS=e()}(this,function(){return function(n){var o={};function r(t){if(o[t])return o[t].exports;var e=o[t]={i:t,l:!1,exports:{}};return n[t].call(e.exports,e,e.exports,r),e.l=!0,e.exports}return r.m=n,r.c=o,r.d=function(t,e,n){r.o(t,e)||Object.defineProperty(t,e,{enumerable:!0,get:n})},r.r=function(t){"undefined"!=typeof Symbol&&Symbol.toStringTag&&Object.defineProperty(t,Symbol.toStringTag,{value:"Module"}),Object.defineProperty(t,"__esModule",{value:!0})},r.t=function(e,t){if(1&t&&(e=r(e)),8&t)return e;if(4&t&&"object"==typeof e&&e&&e.__esModule)return e;var n=Object.create(null);if(r.r(n),Object.defineProperty(n,"default",{enumerable:!0,value:e}),2&t&&"string"!=typeof e)for(var o in e)r.d(n,o,function(t){return e[t]}.bind(null,o));return n},r.n=function(t){var e=t&&t.__esModule?function(){return t.default}:function(){return t};return r.d(e,"a",e),e},r.o=function(t,e){return Object.prototype.hasOwnProperty.call(t,e)},r.p="",r(r.s=0)}([function(t,e,n){"use strict";var r="function"==typeof Symbol&&"symbol"==typeof Symbol.iterator?function(t){return typeof t}:function(t){return t&&"function"==typeof Symbol&&t.constructor===Symbol&&t!==Symbol.prototype?"symbol":typeof t},i=function(){function o(t,e){for(var n=0;n .hljs { + color: var(--links); +} + +/* Menu Bar */ + +#menu-bar, +#menu-bar-hover-placeholder { + z-index: 101; + margin: auto calc(0px - var(--page-padding)); +} +#menu-bar { + position: relative; + display: flex; + flex-wrap: wrap; + background-color: var(--bg); + border-bottom-color: var(--bg); + border-bottom-width: 1px; + border-bottom-style: solid; +} +#menu-bar.sticky, +.js #menu-bar-hover-placeholder:hover + #menu-bar, +.js #menu-bar:hover, +.js.sidebar-visible #menu-bar { + position: -webkit-sticky; + position: sticky; + top: 0 !important; +} +#menu-bar-hover-placeholder { + position: sticky; + position: -webkit-sticky; + top: 0; + height: var(--menu-bar-height); +} +#menu-bar.bordered { + border-bottom-color: var(--table-border-color); +} +#menu-bar i, #menu-bar .icon-button { + position: relative; + padding: 0 8px; + z-index: 10; + line-height: var(--menu-bar-height); + cursor: pointer; + transition: color 0.5s; +} +@media only screen and (max-width: 420px) { + #menu-bar i, #menu-bar .icon-button { + padding: 0 5px; + } +} + +.icon-button { + border: none; + background: none; + padding: 0; + color: inherit; +} +.icon-button i { + margin: 0; +} + +.right-buttons { + margin: 0 15px; +} +.right-buttons a { + text-decoration: none; +} + +.left-buttons { + display: flex; + margin: 0 5px; +} +.no-js .left-buttons { + display: none; +} + +.menu-title { + display: inline-block; + font-weight: 200; + font-size: 2rem; + line-height: var(--menu-bar-height); + text-align: center; + margin: 0; + flex: 1; + white-space: nowrap; + overflow: hidden; + text-overflow: ellipsis; +} +.js .menu-title { + cursor: pointer; +} + +.menu-bar, +.menu-bar:visited, +.nav-chapters, +.nav-chapters:visited, +.mobile-nav-chapters, +.mobile-nav-chapters:visited, +.menu-bar .icon-button, +.menu-bar a i { + color: var(--icons); +} + +.menu-bar i:hover, +.menu-bar .icon-button:hover, +.nav-chapters:hover, +.mobile-nav-chapters i:hover { + color: var(--icons-hover); +} + +/* Nav Icons */ + +.nav-chapters { + font-size: 2.5em; + text-align: center; + text-decoration: none; + + position: fixed; + top: 0; + bottom: 0; + margin: 0; + max-width: 150px; + min-width: 90px; + + display: flex; + justify-content: center; + align-content: center; + flex-direction: column; + + transition: color 0.5s, background-color 0.5s; +} + +.nav-chapters:hover { + text-decoration: none; + background-color: var(--theme-hover); + transition: background-color 0.15s, color 0.15s; +} + +.nav-wrapper { + margin-top: 50px; + display: none; +} + +.mobile-nav-chapters { + font-size: 2.5em; + text-align: center; + text-decoration: none; + width: 90px; + border-radius: 5px; + background-color: var(--sidebar-bg); +} + +.previous { + float: left; +} + +.next { + float: right; + right: var(--page-padding); +} + +@media only screen and (max-width: 1080px) { + .nav-wide-wrapper { display: none; } + .nav-wrapper { display: block; } +} + +@media only screen and (max-width: 1380px) { + .sidebar-visible .nav-wide-wrapper { display: none; } + .sidebar-visible .nav-wrapper { display: block; } +} + +/* Inline code */ + +:not(pre) > .hljs { + display: inline; + padding: 0.1em 0.3em; + border-radius: 3px; +} + +:not(pre):not(a) > .hljs { + color: var(--inline-code-color); + overflow-x: initial; +} + +a:hover > .hljs { + text-decoration: underline; +} + +pre { + position: relative; +} +pre > .buttons { + position: absolute; + z-index: 100; + right: 5px; + top: 5px; + + color: var(--sidebar-fg); + cursor: pointer; +} +pre > .buttons :hover { + color: var(--sidebar-active); +} +pre > .buttons i { + margin-left: 8px; +} +pre > .buttons button { + color: inherit; + background: transparent; + border: none; + cursor: inherit; +} +pre > .result { + margin-top: 10px; +} + +/* Search */ + +#searchresults a { + text-decoration: none; +} + +mark { + border-radius: 2px; + padding: 0 3px 1px 3px; + margin: 0 -3px -1px -3px; + background-color: var(--search-mark-bg); + transition: background-color 300ms linear; + cursor: pointer; +} + +mark.fade-out { + background-color: rgba(0,0,0,0) !important; + cursor: auto; +} + +.searchbar-outer { + margin-left: auto; + margin-right: auto; + max-width: var(--content-max-width); +} + +#searchbar { + width: 100%; + margin: 5px auto 0px auto; + padding: 10px 16px; + transition: box-shadow 300ms ease-in-out; + border: 1px solid var(--searchbar-border-color); + border-radius: 3px; + background-color: var(--searchbar-bg); + color: var(--searchbar-fg); +} +#searchbar:focus, +#searchbar.active { + box-shadow: 0 0 3px var(--searchbar-shadow-color); +} + +.searchresults-header { + font-weight: bold; + font-size: 1em; + padding: 18px 0 0 5px; + color: var(--searchresults-header-fg); +} + +.searchresults-outer { + margin-left: auto; + margin-right: auto; + max-width: var(--content-max-width); + border-bottom: 1px dashed var(--searchresults-border-color); +} + +ul#searchresults { + list-style: none; + padding-left: 20px; +} +ul#searchresults li { + margin: 10px 0px; + padding: 2px; + border-radius: 2px; +} +ul#searchresults li.focus { + background-color: var(--searchresults-li-bg); +} +ul#searchresults span.teaser { + display: block; + clear: both; + margin: 5px 0 0 20px; + font-size: 0.8em; +} +ul#searchresults span.teaser em { + font-weight: bold; + font-style: normal; +} + +/* Sidebar */ + +.sidebar { + position: fixed; + left: 0; + top: 0; + bottom: 0; + width: var(--sidebar-width); + font-size: 0.875em; + box-sizing: border-box; + -webkit-overflow-scrolling: touch; + overscroll-behavior-y: contain; + background-color: var(--sidebar-bg); + color: var(--sidebar-fg); +} +.sidebar-resizing { + -moz-user-select: none; + -webkit-user-select: none; + -ms-user-select: none; + user-select: none; +} +.js:not(.sidebar-resizing) .sidebar { + transition: transform 0.3s; /* Animation: slide away */ +} +.sidebar code { + line-height: 2em; +} +.sidebar .sidebar-scrollbox { + overflow-y: auto; + position: absolute; + top: 0; + bottom: 0; + left: 0; + right: 0; + padding: 10px 10px; +} +.sidebar .sidebar-resize-handle { + position: absolute; + cursor: col-resize; + width: 0; + right: 0; + top: 0; + bottom: 0; +} +.js .sidebar .sidebar-resize-handle { + cursor: col-resize; + width: 5px; +} +.sidebar-hidden .sidebar { + transform: translateX(calc(0px - var(--sidebar-width))); +} +.sidebar::-webkit-scrollbar { + background: var(--sidebar-bg); +} +.sidebar::-webkit-scrollbar-thumb { + background: var(--scrollbar); +} + +.sidebar-visible .page-wrapper { + transform: translateX(var(--sidebar-width)); +} +@media only screen and (min-width: 620px) { + .sidebar-visible .page-wrapper { + transform: none; + margin-left: var(--sidebar-width); + } +} + +.chapter { + list-style: none outside none; + padding-left: 0; + line-height: 2.2em; +} + +.chapter ol { + width: 100%; +} + +.chapter li { + display: flex; + color: var(--sidebar-non-existant); +} +.chapter li a { + display: block; + padding: 0; + text-decoration: none; + color: var(--sidebar-fg); +} + +.chapter li a:hover { + color: var(--sidebar-active); +} + +.chapter li a.active { + color: var(--sidebar-active); +} + +.chapter li > a.toggle { + cursor: pointer; + display: block; + margin-left: auto; + padding: 0 10px; + user-select: none; + opacity: 0.68; +} + +.chapter li > a.toggle div { + transition: transform 0.5s; +} + +/* collapse the section */ +.chapter li:not(.expanded) + li > ol { + display: none; +} + +.chapter li.chapter-item { + line-height: 1.5em; + margin-top: 0.6em; +} + +.chapter li.expanded > a.toggle div { + transform: rotate(90deg); +} + +.spacer { + width: 100%; + height: 3px; + margin: 5px 0px; +} +.chapter .spacer { + background-color: var(--sidebar-spacer); +} + +@media (-moz-touch-enabled: 1), (pointer: coarse) { + .chapter li a { padding: 5px 0; } + .spacer { margin: 10px 0; } +} + +.section { + list-style: none outside none; + padding-left: 20px; + line-height: 1.9em; +} + +/* Theme Menu Popup */ + +.theme-popup { + position: absolute; + left: 10px; + top: var(--menu-bar-height); + z-index: 1000; + border-radius: 4px; + font-size: 0.7em; + color: var(--fg); + background: var(--theme-popup-bg); + border: 1px solid var(--theme-popup-border); + margin: 0; + padding: 0; + list-style: none; + display: none; +} +.theme-popup .default { + color: var(--icons); +} +.theme-popup .theme { + width: 100%; + border: 0; + margin: 0; + padding: 2px 10px; + line-height: 25px; + white-space: nowrap; + text-align: left; + cursor: pointer; + color: inherit; + background: inherit; + font-size: inherit; +} +.theme-popup .theme:hover { + background-color: var(--theme-hover); +} +.theme-popup .theme:hover:first-child, +.theme-popup .theme:hover:last-child { + border-top-left-radius: inherit; + border-top-right-radius: inherit; +} diff --git a/perf-guide/css/general.css b/perf-guide/css/general.css new file mode 100644 index 000000000..815dae1ad --- /dev/null +++ b/perf-guide/css/general.css @@ -0,0 +1,174 @@ +/* Base styles and content styles */ + +@import 'variables.css'; + +:root { + /* Browser default font-size is 16px, this way 1 rem = 10px */ + font-size: 62.5%; +} + +html { + font-family: "Open Sans", sans-serif; + color: var(--fg); + background-color: var(--bg); + text-size-adjust: none; +} + +body { + margin: 0; + font-size: 1.6rem; + overflow-x: hidden; +} + +code { + font-family: "Source Code Pro", Consolas, "Ubuntu Mono", Menlo, "DejaVu Sans Mono", monospace, monospace !important; + font-size: 0.875em; /* please adjust the ace font size accordingly in editor.js */ +} + +/* Don't change font size in headers. */ +h1 code, h2 code, h3 code, h4 code, h5 code, h6 code { + font-size: unset; +} + +.left { float: left; } +.right { float: right; } +.boring { opacity: 0.6; } +.hide-boring .boring { display: none; } +.hidden { display: none !important; } + +h2, h3 { margin-top: 2.5em; } +h4, h5 { margin-top: 2em; } + +.header + .header h3, +.header + .header h4, +.header + .header h5 { + margin-top: 1em; +} + +h1 a.header:target::before, +h2 a.header:target::before, +h3 a.header:target::before, +h4 a.header:target::before { + display: inline-block; + content: "»"; + margin-left: -30px; + width: 30px; +} + +h1 a.header:target, +h2 a.header:target, +h3 a.header:target, +h4 a.header:target { + scroll-margin-top: calc(var(--menu-bar-height) + 0.5em); +} + +.page { + outline: 0; + padding: 0 var(--page-padding); + margin-top: calc(0px - var(--menu-bar-height)); /* Compensate for the #menu-bar-hover-placeholder */ +} +.page-wrapper { + box-sizing: border-box; +} +.js:not(.sidebar-resizing) .page-wrapper { + transition: margin-left 0.3s ease, transform 0.3s ease; /* Animation: slide away */ +} + +.content { + overflow-y: auto; + padding: 0 15px; + padding-bottom: 50px; +} +.content main { + margin-left: auto; + margin-right: auto; + max-width: var(--content-max-width); +} +.content p { line-height: 1.45em; } +.content ol { line-height: 1.45em; } +.content ul { line-height: 1.45em; } +.content a { text-decoration: none; } +.content a:hover { text-decoration: underline; } +.content img { max-width: 100%; } +.content .header:link, +.content .header:visited { + color: var(--fg); +} +.content .header:link, +.content .header:visited:hover { + text-decoration: none; +} + +table { + margin: 0 auto; + border-collapse: collapse; +} +table td { + padding: 3px 20px; + border: 1px var(--table-border-color) solid; +} +table thead { + background: var(--table-header-bg); +} +table thead td { + font-weight: 700; + border: none; +} +table thead th { + padding: 3px 20px; +} +table thead tr { + border: 1px var(--table-header-bg) solid; +} +/* Alternate background colors for rows */ +table tbody tr:nth-child(2n) { + background: var(--table-alternate-bg); +} + + +blockquote { + margin: 20px 0; + padding: 0 20px; + color: var(--fg); + background-color: var(--quote-bg); + border-top: .1em solid var(--quote-border); + border-bottom: .1em solid var(--quote-border); +} + + +:not(.footnote-definition) + .footnote-definition, +.footnote-definition + :not(.footnote-definition) { + margin-top: 2em; +} +.footnote-definition { + font-size: 0.9em; + margin: 0.5em 0; +} +.footnote-definition p { + display: inline; +} + +.tooltiptext { + position: absolute; + visibility: hidden; + color: #fff; + background-color: #333; + transform: translateX(-50%); /* Center by moving tooltip 50% of its width left */ + left: -8px; /* Half of the width of the icon */ + top: -35px; + font-size: 0.8em; + text-align: center; + border-radius: 6px; + padding: 5px 8px; + margin: 5px; + z-index: 1000; +} +.tooltipped .tooltiptext { + visibility: visible; +} + +.chapter li.part-title { + color: var(--sidebar-fg); + margin: 5px 0px; + font-weight: bold; +} diff --git a/perf-guide/css/print.css b/perf-guide/css/print.css new file mode 100644 index 000000000..5e690f755 --- /dev/null +++ b/perf-guide/css/print.css @@ -0,0 +1,54 @@ + +#sidebar, +#menu-bar, +.nav-chapters, +.mobile-nav-chapters { + display: none; +} + +#page-wrapper.page-wrapper { + transform: none; + margin-left: 0px; + overflow-y: initial; +} + +#content { + max-width: none; + margin: 0; + padding: 0; +} + +.page { + overflow-y: initial; +} + +code { + background-color: #666666; + border-radius: 5px; + + /* Force background to be printed in Chrome */ + -webkit-print-color-adjust: exact; +} + +pre > .buttons { + z-index: 2; +} + +a, a:visited, a:active, a:hover { + color: #4183c4; + text-decoration: none; +} + +h1, h2, h3, h4, h5, h6 { + page-break-inside: avoid; + page-break-after: avoid; +} + +pre, code { + page-break-inside: avoid; + white-space: pre-wrap; +} + +.fa { + display: none !important; +} diff --git a/perf-guide/css/variables.css b/perf-guide/css/variables.css new file mode 100644 index 000000000..9534ec8d1 --- /dev/null +++ b/perf-guide/css/variables.css @@ -0,0 +1,253 @@ + +/* Globals */ + +:root { + --sidebar-width: 300px; + --page-padding: 15px; + --content-max-width: 750px; + --menu-bar-height: 50px; +} + +/* Themes */ + +.ayu { + --bg: hsl(210, 25%, 8%); + --fg: #c5c5c5; + + --sidebar-bg: #14191f; + --sidebar-fg: #c8c9db; + --sidebar-non-existant: #5c6773; + --sidebar-active: #ffb454; + --sidebar-spacer: #2d334f; + + --scrollbar: var(--sidebar-fg); + + --icons: #737480; + --icons-hover: #b7b9cc; + + --links: #0096cf; + + --inline-code-color: #ffb454; + + --theme-popup-bg: #14191f; + --theme-popup-border: #5c6773; + --theme-hover: #191f26; + + --quote-bg: hsl(226, 15%, 17%); + --quote-border: hsl(226, 15%, 22%); + + --table-border-color: hsl(210, 25%, 13%); + --table-header-bg: hsl(210, 25%, 28%); + --table-alternate-bg: hsl(210, 25%, 11%); + + --searchbar-border-color: #848484; + --searchbar-bg: #424242; + --searchbar-fg: #fff; + --searchbar-shadow-color: #d4c89f; + --searchresults-header-fg: #666; + --searchresults-border-color: #888; + --searchresults-li-bg: #252932; + --search-mark-bg: #e3b171; +} + +.coal { + --bg: hsl(200, 7%, 8%); + --fg: #98a3ad; + + --sidebar-bg: #292c2f; + --sidebar-fg: #a1adb8; + --sidebar-non-existant: #505254; + --sidebar-active: #3473ad; + --sidebar-spacer: #393939; + + --scrollbar: var(--sidebar-fg); + + --icons: #43484d; + --icons-hover: #b3c0cc; + + --links: #2b79a2; + + --inline-code-color: #c5c8c6;; + + --theme-popup-bg: #141617; + --theme-popup-border: #43484d; + --theme-hover: #1f2124; + + --quote-bg: hsl(234, 21%, 18%); + --quote-border: hsl(234, 21%, 23%); + + --table-border-color: hsl(200, 7%, 13%); + --table-header-bg: hsl(200, 7%, 28%); + --table-alternate-bg: hsl(200, 7%, 11%); + + --searchbar-border-color: #aaa; + --searchbar-bg: #b7b7b7; + --searchbar-fg: #000; + --searchbar-shadow-color: #aaa; + --searchresults-header-fg: #666; + --searchresults-border-color: #98a3ad; + --searchresults-li-bg: #2b2b2f; + --search-mark-bg: #355c7d; +} + +.light { + --bg: hsl(0, 0%, 100%); + --fg: #333333; + + --sidebar-bg: #fafafa; + --sidebar-fg: #364149; + --sidebar-non-existant: #aaaaaa; + --sidebar-active: #008cff; + --sidebar-spacer: #f4f4f4; + + --scrollbar: #cccccc; + + --icons: #cccccc; + --icons-hover: #333333; + + --links: #4183c4; + + --inline-code-color: #6e6b5e; + + --theme-popup-bg: #fafafa; + --theme-popup-border: #cccccc; + --theme-hover: #e6e6e6; + + --quote-bg: hsl(197, 37%, 96%); + --quote-border: hsl(197, 37%, 91%); + + --table-border-color: hsl(0, 0%, 95%); + --table-header-bg: hsl(0, 0%, 80%); + --table-alternate-bg: hsl(0, 0%, 97%); + + --searchbar-border-color: #aaa; + --searchbar-bg: #fafafa; + --searchbar-fg: #000; + --searchbar-shadow-color: #aaa; + --searchresults-header-fg: #666; + --searchresults-border-color: #888; + --searchresults-li-bg: #e4f2fe; + --search-mark-bg: #a2cff5; +} + +.navy { + --bg: hsl(226, 23%, 11%); + --fg: #bcbdd0; + + --sidebar-bg: #282d3f; + --sidebar-fg: #c8c9db; + --sidebar-non-existant: #505274; + --sidebar-active: #2b79a2; + --sidebar-spacer: #2d334f; + + --scrollbar: var(--sidebar-fg); + + --icons: #737480; + --icons-hover: #b7b9cc; + + --links: #2b79a2; + + --inline-code-color: #c5c8c6;; + + --theme-popup-bg: #161923; + --theme-popup-border: #737480; + --theme-hover: #282e40; + + --quote-bg: hsl(226, 15%, 17%); + --quote-border: hsl(226, 15%, 22%); + + --table-border-color: hsl(226, 23%, 16%); + --table-header-bg: hsl(226, 23%, 31%); + --table-alternate-bg: hsl(226, 23%, 14%); + + --searchbar-border-color: #aaa; + --searchbar-bg: #aeaec6; + --searchbar-fg: #000; + --searchbar-shadow-color: #aaa; + --searchresults-header-fg: #5f5f71; + --searchresults-border-color: #5c5c68; + --searchresults-li-bg: #242430; + --search-mark-bg: #a2cff5; +} + +.rust { + --bg: hsl(60, 9%, 87%); + --fg: #262625; + + --sidebar-bg: #3b2e2a; + --sidebar-fg: #c8c9db; + --sidebar-non-existant: #505254; + --sidebar-active: #e69f67; + --sidebar-spacer: #45373a; + + --scrollbar: var(--sidebar-fg); + + --icons: #737480; + --icons-hover: #262625; + + --links: #2b79a2; + + --inline-code-color: #6e6b5e; + + --theme-popup-bg: #e1e1db; + --theme-popup-border: #b38f6b; + --theme-hover: #99908a; + + --quote-bg: hsl(60, 5%, 75%); + --quote-border: hsl(60, 5%, 70%); + + --table-border-color: hsl(60, 9%, 82%); + --table-header-bg: #b3a497; + --table-alternate-bg: hsl(60, 9%, 84%); + + --searchbar-border-color: #aaa; + --searchbar-bg: #fafafa; + --searchbar-fg: #000; + --searchbar-shadow-color: #aaa; + --searchresults-header-fg: #666; + --searchresults-border-color: #888; + --searchresults-li-bg: #dec2a2; + --search-mark-bg: #e69f67; +} + +@media (prefers-color-scheme: dark) { + .light.no-js { + --bg: hsl(200, 7%, 8%); + --fg: #98a3ad; + + --sidebar-bg: #292c2f; + --sidebar-fg: #a1adb8; + --sidebar-non-existant: #505254; + --sidebar-active: #3473ad; + --sidebar-spacer: #393939; + + --scrollbar: var(--sidebar-fg); + + --icons: #43484d; + --icons-hover: #b3c0cc; + + --links: #2b79a2; + + --inline-code-color: #c5c8c6;; + + --theme-popup-bg: #141617; + --theme-popup-border: #43484d; + --theme-hover: #1f2124; + + --quote-bg: hsl(234, 21%, 18%); + --quote-border: hsl(234, 21%, 23%); + + --table-border-color: hsl(200, 7%, 13%); + --table-header-bg: hsl(200, 7%, 28%); + --table-alternate-bg: hsl(200, 7%, 11%); + + --searchbar-border-color: #aaa; + --searchbar-bg: #b7b7b7; + --searchbar-fg: #000; + --searchbar-shadow-color: #aaa; + --searchresults-header-fg: #666; + --searchresults-border-color: #98a3ad; + --searchresults-li-bg: #2b2b2f; + --search-mark-bg: #355c7d; + } +} diff --git a/perf-guide/elasticlunr.min.js b/perf-guide/elasticlunr.min.js new file mode 100644 index 000000000..94b20dd2e --- /dev/null +++ b/perf-guide/elasticlunr.min.js @@ -0,0 +1,10 @@ +/** + * elasticlunr - http://weixsong.github.io + * Lightweight full-text search engine in Javascript for browser search and offline search. - 0.9.5 + * + * Copyright (C) 2017 Oliver Nightingale + * Copyright (C) 2017 Wei Song + * MIT Licensed + * @license + */ +!function(){function e(e){if(null===e||"object"!=typeof e)return e;var t=e.constructor();for(var n in e)e.hasOwnProperty(n)&&(t[n]=e[n]);return t}var t=function(e){var n=new t.Index;return n.pipeline.add(t.trimmer,t.stopWordFilter,t.stemmer),e&&e.call(n,n),n};t.version="0.9.5",lunr=t,t.utils={},t.utils.warn=function(e){return function(t){e.console&&console.warn&&console.warn(t)}}(this),t.utils.toString=function(e){return void 0===e||null===e?"":e.toString()},t.EventEmitter=function(){this.events={}},t.EventEmitter.prototype.addListener=function(){var e=Array.prototype.slice.call(arguments),t=e.pop(),n=e;if("function"!=typeof t)throw new TypeError("last argument must be a function");n.forEach(function(e){this.hasHandler(e)||(this.events[e]=[]),this.events[e].push(t)},this)},t.EventEmitter.prototype.removeListener=function(e,t){if(this.hasHandler(e)){var n=this.events[e].indexOf(t);-1!==n&&(this.events[e].splice(n,1),0==this.events[e].length&&delete this.events[e])}},t.EventEmitter.prototype.emit=function(e){if(this.hasHandler(e)){var t=Array.prototype.slice.call(arguments,1);this.events[e].forEach(function(e){e.apply(void 0,t)},this)}},t.EventEmitter.prototype.hasHandler=function(e){return e in this.events},t.tokenizer=function(e){if(!arguments.length||null===e||void 0===e)return[];if(Array.isArray(e)){var n=e.filter(function(e){return null===e||void 0===e?!1:!0});n=n.map(function(e){return t.utils.toString(e).toLowerCase()});var i=[];return n.forEach(function(e){var n=e.split(t.tokenizer.seperator);i=i.concat(n)},this),i}return e.toString().trim().toLowerCase().split(t.tokenizer.seperator)},t.tokenizer.defaultSeperator=/[\s\-]+/,t.tokenizer.seperator=t.tokenizer.defaultSeperator,t.tokenizer.setSeperator=function(e){null!==e&&void 0!==e&&"object"==typeof e&&(t.tokenizer.seperator=e)},t.tokenizer.resetSeperator=function(){t.tokenizer.seperator=t.tokenizer.defaultSeperator},t.tokenizer.getSeperator=function(){return t.tokenizer.seperator},t.Pipeline=function(){this._queue=[]},t.Pipeline.registeredFunctions={},t.Pipeline.registerFunction=function(e,n){n in t.Pipeline.registeredFunctions&&t.utils.warn("Overwriting existing registered function: "+n),e.label=n,t.Pipeline.registeredFunctions[n]=e},t.Pipeline.getRegisteredFunction=function(e){return e in t.Pipeline.registeredFunctions!=!0?null:t.Pipeline.registeredFunctions[e]},t.Pipeline.warnIfFunctionNotRegistered=function(e){var n=e.label&&e.label in this.registeredFunctions;n||t.utils.warn("Function is not registered with pipeline. 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configuration"),this.buildDefaultConfig(n)}},t.Configuration.prototype.buildDefaultConfig=function(e){this.reset(),e.forEach(function(e){this.config[e]={boost:1,bool:"OR",expand:!1}},this)},t.Configuration.prototype.buildUserConfig=function(e,n){var i="OR",o=!1;if(this.reset(),"bool"in e&&(i=e.bool||i),"expand"in e&&(o=e.expand||o),"fields"in e)for(var r in e.fields)if(n.indexOf(r)>-1){var s=e.fields[r],u=o;void 0!=s.expand&&(u=s.expand),this.config[r]={boost:s.boost||0===s.boost?s.boost:1,bool:s.bool||i,expand:u}}else t.utils.warn("field name in user configuration not found in index instance fields");else this.addAllFields2UserConfig(i,o,n)},t.Configuration.prototype.addAllFields2UserConfig=function(e,t,n){n.forEach(function(n){this.config[n]={boost:1,bool:e,expand:t}},this)},t.Configuration.prototype.get=function(){return this.config},t.Configuration.prototype.reset=function(){this.config={}},lunr.SortedSet=function(){this.length=0,this.elements=[]},lunr.SortedSet.load=function(e){var t=new this;return t.elements=e,t.length=e.length,t},lunr.SortedSet.prototype.add=function(){var e,t;for(e=0;e1;){if(r===e)return o;e>r&&(t=o),r>e&&(n=o),i=n-t,o=t+Math.floor(i/2),r=this.elements[o]}return r===e?o:-1},lunr.SortedSet.prototype.locationFor=function(e){for(var t=0,n=this.elements.length,i=n-t,o=t+Math.floor(i/2),r=this.elements[o];i>1;)e>r&&(t=o),r>e&&(n=o),i=n-t,o=t+Math.floor(i/2),r=this.elements[o];return r>e?o:e>r?o+1:void 0},lunr.SortedSet.prototype.intersect=function(e){for(var t=new lunr.SortedSet,n=0,i=0,o=this.length,r=e.length,s=this.elements,u=e.elements;;){if(n>o-1||i>r-1)break;s[n]!==u[i]?s[n]u[i]&&i++:(t.add(s[n]),n++,i++)}return t},lunr.SortedSet.prototype.clone=function(){var e=new lunr.SortedSet;return e.elements=this.toArray(),e.length=e.elements.length,e},lunr.SortedSet.prototype.union=function(e){var t,n,i;this.length>=e.length?(t=this,n=e):(t=e,n=this),i=t.clone();for(var o=0,r=n.toArray();o + + + + diff --git a/perf-guide/float-math/approx.html b/perf-guide/float-math/approx.html new file mode 100644 index 000000000..514354db8 --- /dev/null +++ b/perf-guide/float-math/approx.html @@ -0,0 +1,235 @@ + + + + + + Approximate functions - Rust SIMD Performance Guide + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ +
+ + + + + + + + + + + +
+
+

Approximate functions

+ + +
+ + +
+
+ + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/perf-guide/float-math/fma.html b/perf-guide/float-math/fma.html new file mode 100644 index 000000000..b49231c44 --- /dev/null +++ b/perf-guide/float-math/fma.html @@ -0,0 +1,233 @@ + + + + + + Fused multiply-accumulate - Rust SIMD Performance Guide + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ +
+ + + + + + + + + + + +
+
+

Fused Multiply Add

+ + +
+ + +
+
+ + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/perf-guide/float-math/fp.html b/perf-guide/float-math/fp.html new file mode 100644 index 000000000..5355b55b4 --- /dev/null +++ b/perf-guide/float-math/fp.html @@ -0,0 +1,230 @@ + + + + + + Floating-point Math - Rust SIMD Performance Guide + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ +
+ + + + + + + + + + + +
+
+

Floating-point math

+

This chapter contains information pertaining to working with floating-point numbers.

+ +
+ + +
+
+ + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/perf-guide/float-math/svml.html b/perf-guide/float-math/svml.html new file mode 100644 index 000000000..a6f791f96 --- /dev/null +++ b/perf-guide/float-math/svml.html @@ -0,0 +1,234 @@ + + + + + + Short-vector Math Library - Rust SIMD Performance Guide + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ +
+ + + + + + + + + + + +
+
+

Short Vector Math Library

+ + +
+ + +
+
+ + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/perf-guide/fonts/OPEN-SANS-LICENSE.txt b/perf-guide/fonts/OPEN-SANS-LICENSE.txt new file mode 100644 index 000000000..d64569567 --- /dev/null +++ b/perf-guide/fonts/OPEN-SANS-LICENSE.txt @@ -0,0 +1,202 @@ + + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. Definitions. + + "License" shall mean the terms and conditions for use, reproduction, + and distribution as defined by Sections 1 through 9 of this document. + + "Licensor" shall mean the copyright owner or entity authorized by + the copyright owner that is granting the License. + + "Legal Entity" shall mean the union of the acting entity and all + other entities that control, are controlled by, or are under common + control with that entity. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright [yyyy] [name of copyright owner] + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/perf-guide/fonts/SOURCE-CODE-PRO-LICENSE.txt b/perf-guide/fonts/SOURCE-CODE-PRO-LICENSE.txt new file mode 100644 index 000000000..366206f54 --- /dev/null +++ b/perf-guide/fonts/SOURCE-CODE-PRO-LICENSE.txt @@ -0,0 +1,93 @@ +Copyright 2010, 2012 Adobe Systems Incorporated (http://www.adobe.com/), with Reserved Font Name 'Source'. All Rights Reserved. Source is a trademark of Adobe Systems Incorporated in the United States and/or other countries. + +This Font Software is licensed under the SIL Open Font License, Version 1.1. +This license is copied below, and is also available with a FAQ at: +http://scripts.sil.org/OFL + + +----------------------------------------------------------- +SIL OPEN FONT LICENSE Version 1.1 - 26 February 2007 +----------------------------------------------------------- + +PREAMBLE +The goals of the Open Font License (OFL) are to stimulate worldwide +development of collaborative font projects, to support the font creation +efforts of academic and linguistic communities, and to provide a free and +open framework in which fonts may be shared and improved in partnership +with others. + +The OFL allows the licensed fonts to be used, studied, modified and +redistributed freely as long as they are not sold by themselves. The +fonts, including any derivative works, can be bundled, embedded, +redistributed and/or sold with any software provided that any reserved +names are not used by derivative works. The fonts and derivatives, +however, cannot be released under any other type of license. The +requirement for fonts to remain under this license does not apply +to any document created using the fonts or their derivatives. + +DEFINITIONS +"Font Software" refers to the set of files released by the Copyright +Holder(s) under this license and clearly marked as such. This may +include source files, build scripts and documentation. + +"Reserved Font Name" refers to any names specified as such after the +copyright statement(s). + +"Original Version" refers to the collection of Font Software components as +distributed by the Copyright Holder(s). + +"Modified Version" refers to any derivative made by adding to, deleting, +or substituting -- in part or in whole -- any of the components of the +Original Version, by changing formats or by porting the Font Software to a +new environment. + +"Author" refers to any designer, engineer, programmer, technical +writer or other person who contributed to the Font Software. + +PERMISSION & CONDITIONS +Permission is hereby granted, free of charge, to any person obtaining +a copy of the Font Software, to use, study, copy, merge, embed, modify, +redistribute, and sell modified and unmodified copies of the Font +Software, subject to the following conditions: + +1) Neither the Font Software nor any of its individual components, +in Original or Modified Versions, may be sold by itself. + +2) Original or Modified Versions of the Font Software may be bundled, +redistributed and/or sold with any software, provided that each copy +contains the above copyright notice and this license. These can be +included either as stand-alone text files, human-readable headers or +in the appropriate machine-readable metadata fields within text or +binary files as long as those fields can be easily viewed by the user. + +3) No Modified Version of the Font Software may use the Reserved Font +Name(s) unless explicit written permission is granted by the corresponding +Copyright Holder. This restriction only applies to the primary font name as +presented to the users. + +4) The name(s) of the Copyright Holder(s) or the Author(s) of the Font +Software shall not be used to promote, endorse or advertise any +Modified Version, except to acknowledge the contribution(s) of the +Copyright Holder(s) and the Author(s) or with their explicit written +permission. + +5) The Font Software, modified or unmodified, in part or in whole, +must be distributed entirely under this license, and must not be +distributed under any other license. The requirement for fonts to +remain under this license does not apply to any document created +using the Font Software. + +TERMINATION +This license becomes null and void if any of the above conditions are +not met. + +DISCLAIMER +THE FONT SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT +OF COPYRIGHT, PATENT, TRADEMARK, OR OTHER RIGHT. IN NO EVENT SHALL THE +COPYRIGHT HOLDER BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +INCLUDING ANY GENERAL, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL +DAMAGES, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF THE USE OR INABILITY TO USE THE FONT SOFTWARE OR FROM +OTHER DEALINGS IN THE FONT SOFTWARE. diff --git a/perf-guide/fonts/fonts.css b/perf-guide/fonts/fonts.css new file mode 100644 index 000000000..b2b63d027 --- /dev/null +++ b/perf-guide/fonts/fonts.css @@ -0,0 +1,101 @@ +/* Open Sans is licensed under the Apache License, Version 2.0. See http://www.apache.org/licenses/LICENSE-2.0 */ +/* Source Code Pro is under the Open Font License. See https://scripts.sil.org/cms/scripts/page.php?site_id=nrsi&id=OFL */ + +/* open-sans-300 - latin_vietnamese_latin-ext_greek-ext_greek_cyrillic-ext_cyrillic */ +@font-face { + font-family: 'Open Sans'; + font-style: normal; + font-weight: 300; + src: local('Open Sans Light'), local('OpenSans-Light'), + url('open-sans-v17-all-charsets-300.woff2') format('woff2'); +} + +/* open-sans-300italic - latin_vietnamese_latin-ext_greek-ext_greek_cyrillic-ext_cyrillic */ +@font-face { + font-family: 'Open Sans'; + font-style: italic; + font-weight: 300; + src: local('Open Sans Light Italic'), local('OpenSans-LightItalic'), + url('open-sans-v17-all-charsets-300italic.woff2') format('woff2'); +} + +/* open-sans-regular - latin_vietnamese_latin-ext_greek-ext_greek_cyrillic-ext_cyrillic */ +@font-face { + font-family: 'Open Sans'; + font-style: normal; + font-weight: 400; + src: local('Open Sans Regular'), local('OpenSans-Regular'), + url('open-sans-v17-all-charsets-regular.woff2') format('woff2'); +} + +/* open-sans-italic - latin_vietnamese_latin-ext_greek-ext_greek_cyrillic-ext_cyrillic */ +@font-face { + font-family: 'Open Sans'; + font-style: italic; + font-weight: 400; + src: local('Open Sans Italic'), local('OpenSans-Italic'), + url('open-sans-v17-all-charsets-italic.woff2') format('woff2'); +} + +/* open-sans-600 - latin_vietnamese_latin-ext_greek-ext_greek_cyrillic-ext_cyrillic */ +@font-face { + font-family: 'Open Sans'; + font-style: normal; + font-weight: 600; + src: local('Open Sans SemiBold'), local('OpenSans-SemiBold'), + url('open-sans-v17-all-charsets-600.woff2') format('woff2'); +} + +/* open-sans-600italic - latin_vietnamese_latin-ext_greek-ext_greek_cyrillic-ext_cyrillic */ +@font-face { + font-family: 'Open Sans'; + font-style: italic; + font-weight: 600; + src: local('Open Sans SemiBold Italic'), local('OpenSans-SemiBoldItalic'), + url('open-sans-v17-all-charsets-600italic.woff2') format('woff2'); +} + +/* open-sans-700 - latin_vietnamese_latin-ext_greek-ext_greek_cyrillic-ext_cyrillic */ +@font-face { + font-family: 'Open Sans'; + font-style: normal; + font-weight: 700; + src: local('Open Sans Bold'), local('OpenSans-Bold'), + url('open-sans-v17-all-charsets-700.woff2') format('woff2'); +} + +/* open-sans-700italic - latin_vietnamese_latin-ext_greek-ext_greek_cyrillic-ext_cyrillic */ +@font-face { + font-family: 'Open Sans'; + font-style: italic; + font-weight: 700; + src: local('Open Sans Bold Italic'), local('OpenSans-BoldItalic'), + url('open-sans-v17-all-charsets-700italic.woff2') format('woff2'); +} + +/* open-sans-800 - latin_vietnamese_latin-ext_greek-ext_greek_cyrillic-ext_cyrillic */ +@font-face { + font-family: 'Open Sans'; + font-style: normal; + font-weight: 800; + src: local('Open Sans ExtraBold'), local('OpenSans-ExtraBold'), + url('open-sans-v17-all-charsets-800.woff2') format('woff2'); +} + +/* open-sans-800italic - latin_vietnamese_latin-ext_greek-ext_greek_cyrillic-ext_cyrillic */ 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+ +
+ + + + + + + + + + + +
+
+

Introduction

+

What is SIMD

+ +

History of SIMD in Rust

+ +

Discover packed_simd

+ +

Writing fast and portable SIMD algorithms using packed_simd is, unfortunately, +not trivial. There are many pitfals that one should be aware of, and some idioms +that help avoid those pitfalls.

+

This book attempts to document these best practices and provides practical examples +on how to apply the tips to your code.

+ +
+ + +
+
+ + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/perf-guide/introduction.html b/perf-guide/introduction.html new file mode 100644 index 000000000..0341aa87d --- /dev/null +++ b/perf-guide/introduction.html @@ -0,0 +1,238 @@ + + + + + + Introduction - Rust SIMD Performance Guide + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ +
+ + + + + + + + + + + +
+
+

Introduction

+

What is SIMD

+ +

History of SIMD in Rust

+ +

Discover packed_simd

+ +

Writing fast and portable SIMD algorithms using packed_simd is, unfortunately, +not trivial. There are many pitfals that one should be aware of, and some idioms +that help avoid those pitfalls.

+

This book attempts to document these best practices and provides practical examples +on how to apply the tips to your code.

+ +
+ + +
+
+ + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/perf-guide/mark.min.js b/perf-guide/mark.min.js new file mode 100644 index 000000000..163623188 --- /dev/null +++ b/perf-guide/mark.min.js @@ -0,0 +1,7 @@ +/*!*************************************************** +* mark.js v8.11.1 +* https://markjs.io/ +* Copyright (c) 2014–2018, Julian Kühnel +* Released under the MIT license https://git.io/vwTVl +*****************************************************/ +!function(e,t){"object"==typeof exports&&"undefined"!=typeof module?module.exports=t():"function"==typeof define&&define.amd?define(t):e.Mark=t()}(this,function(){"use strict";var e="function"==typeof Symbol&&"symbol"==typeof Symbol.iterator?function(e){return typeof e}:function(e){return e&&"function"==typeof Symbol&&e.constructor===Symbol&&e!==Symbol.prototype?"symbol":typeof e},t=function(e,t){if(!(e instanceof t))throw new TypeError("Cannot call a class as a function")},n=function(){function e(e,t){for(var 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r((e=this.wrapRangeInTextNode(e,t,t+n)).previousSibling),e}},{key:"separateGroups",value:function(e,t,n,r,i){for(var o=t.length,a=1;a-1&&r(t[a],e)&&(e=this.wrapGroups(e,s,t[a].length,i))}return e}},{key:"wrapMatches",value:function(e,t,n,r,i){var o=this,a=0===t?0:t+1;this.getTextNodes(function(t){t.nodes.forEach(function(t){t=t.node;for(var i=void 0;null!==(i=e.exec(t.textContent))&&""!==i[a];){if(o.opt.separateGroups)t=o.separateGroups(t,i,a,n,r);else{if(!n(i[a],t))continue;var s=i.index;if(0!==a)for(var c=1;c + + + + + Rust SIMD Performance Guide + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ +
+ + + + + + + + + + + +
+
+

Introduction

+

What is SIMD

+ +

History of SIMD in Rust

+ +

Discover packed_simd

+ +

Writing fast and portable SIMD algorithms using packed_simd is, unfortunately, +not trivial. There are many pitfals that one should be aware of, and some idioms +that help avoid those pitfalls.

+

This book attempts to document these best practices and provides practical examples +on how to apply the tips to your code.

+

Floating-point math

+

This chapter contains information pertaining to working with floating-point numbers.

+

Short Vector Math Library

+ +

Approximate functions

+ +

Fused Multiply Add

+ +

Enabling target features

+

Not all processors of a certain architecture will have SIMD processing units, +and using a SIMD instruction which is not supported will trigger undefined behavior.

+

To allow building safe, portable programs, the Rust compiler will not, by default, +generate any sort of vector instructions, unless it can statically determine +they are supported. For example, on AMD64, SSE2 support is architecturally guaranteed. +The x86_64-apple-darwin target enables up to SSSE3. The get a defintive list of +which features are enabled by default on various platforms, refer to the target +specifications in the compiler's source code.

+

Using RUSTFLAGS

+

One of the easiest ways to benefit from SIMD is to allow the compiler +to generate code using certain vector instruction extensions.

+

The environment variable RUSTFLAGS can be used to pass options for code +generation to the Rust compiler. These flags will affect all compiled crates.

+

There are two flags which can be used to enable specific vector extensions:

+

target-feature

+
    +
  • +

    Syntax: -C target-feature=<features>

    +
    • +
  • +

    Provides the compiler with a comma-separated set of instruction extensions +to enable.

    +

    Example: Use -C target-features=+sse3,+avx to enable generating instructions +for Streaming SIMD Extensions 3 and +Advanced Vector Extensions.

    +
    • +
  • +

    To list target triples for all targets supported by Rust, use:

    +
    rustc --print target-list
+
    +
    • +
  • +

    To list all support target features for a certain target triple, use:

    +
    rustc --target=${TRIPLE} --print target-features
+
    +
    • +
  • +

    Note that all CPU features are independent, and will have to be enabled individually.

    +

    Example: Setting -C target-features=+avx2 will not enable fma, even though +all CPUs which support AVX2 also support FMA. To enable both, one has to use +-C target-features=+avx2,+fma

    +
    • +
  • +

    Some features also depend on other features, which need to be enabled for the +target instructions to be generated.

    +

    Example: Unless v7 is specified as the target CPU (see below), to enable +NEON on ARM it is necessary to use -C target-feature=+v7,+neon.

    +
    • +
+

target-cpu

+
    +
  • +

    Syntax: -C target-cpu=<cpu>

    +
    • +
  • +

    Sets the identifier of a CPU family / model for which to build and optimize the code.

    +

    Example: RUSTFLAGS='-C target-cpu=cortex-a75'

    +
    • +
  • +

    To list all supported target CPUs for a certain target triple, use:

    +
    rustc --target=${TRIPLE} --print target-cpus
+
    +

    Example:

    +
    rustc --target=i686-pc-windows-msvc --print target-cpus
+
    +
    • +
  • +

    The compiler will translate this into a list of target features. Therefore, +individual feature checks (#[cfg(target_feature = "...")]) will still +work properly.

    +
    • +
  • +

    It will cause the code generator to optimize the generated code for that +specific CPU model.

    +
    • +
  • +

    Using native as the CPU model will cause Rust to generate and optimize code +for the CPU running the compiler. It is useful when building programs which you +plan to only use locally. This should never be used when the generated programs +are meant to be run on other computers, such as when packaging for distribution +or cross-compiling.

    +
    • +
+

The target_feature attribute

+ +

Inlining

+ +

Detecting host features at runtime

+ +

Bounds checking

+

Reading and writing packed vectors to/from slices is checked by default. +Independently of the configuration options used, the safe functions:

+
    +
  • Simd<[T; N]>::from_slice_aligned(& s[..])
    • +
  • Simd<[T; N]>::write_to_slice_aligned(&mut s[..])
    • +
+

always check that:

+
    +
  • the slice is big enough to hold the vector
    • +
  • the slice is suitably aligned to perform an aligned load/store for a Simd<[T; N]> (this alignment is often much larger than that of T).
    • +
+

There are _unaligned versions that use unaligned load and stores, as well as +unsafe _unchecked that do not perform any checks iff debug-assertions = false / debug = false. That is, the _unchecked methods do still assert size +and alignment in debug builds and could also do so in release builds depending +on the configuration options.

+

These assertions do often significantly impact performance and you should be +aware of them.

+

Vertical and horizontal operations

+

In SIMD terminology, each vector has a certain "width" (number of lanes). +A vector processor is able to perform two kinds of operations on a vector:

+
    +
  • Vertical operations: +operate on two vectors of the same width, result has same width
    • +
+

Example: vertical addition of two f32x4 vectors

+
  %0     == | 2 | -3.5 |  0 | 7 |
+              +     +     +   +
+  %1     == | 4 |  1.5 | -1 | 0 |
+              =     =     =   =
+%0 + %1  == | 6 |  -2  | -1 | 7 |
+
+
    +
  • Horizontal operations: +reduce the elements of two vectors in some way, +the result's elements combine information from the two original ones
    • +
+

Example: horizontal addition of two u64x2 vectors

+
  %0     == | 1 |  3 |
+              └─+───┘
+                └───────┐
+                        │
+  %1     == | 4 | -1 |  │
+              └─+──┘    │
+                └───┐   │
+                    │   │
+              ┌─────│───┘
+              ▼     ▼
+%0 + %1  == | 4 |   3 |
+
+

Performance consideration of horizontal operations

+

The result of vertical operations, like vector negation: -a, for a given lane, +does not depend on the result of the operation for the other lanes. The result +of horizontal operations, like the vector sum reduction: a.sum(), depends on +the value of all vector lanes.

+

In virtually all architectures vertical operations are fast, while horizontal +operations are, by comparison, very slow.

+

Consider the following two functions for computing the sum of all f32 values +in a slice:

+

+#![allow(unused)]
+fn main() {
+fn fast_sum(x: &[f32]) -> f32 {
+    assert!(x.len() % 4 == 0);
+    let mut sum = f32x4::splat(0.); // [0., 0., 0., 0.]
+    for i in (0..x.len()).step_by(4) {
+        sum += f32x4::from_slice_unaligned(&x[i..]);
+    }
+    sum.sum()
+}
+
+fn slow_sum(x: &[f32]) -> f32 {
+    assert!(x.len() % 4 == 0);
+    let mut sum: f32 = 0.;
+    for i in (0..x.len()).step_by(4) {
+        sum += f32x4::from_slice_unaligned(&x[i..]).sum();
+    }
+    sum
+}
+}
+
+

The inner loop over the slice is where the bulk of the work actually happens. +There, the fast_sum function perform vertical operations into a vector, doing +a single horizontal reduction at the end, while the slow_sum function performs +horizontal vector operations inside of the loop.

+

On all widely-used architectures, fast_sum is a large constant factor faster +than slow_sum. You can run the slice_sum example and see for yourself. On +the particular machine tested there the algorithm using the horizontal vector +addition is 2.7x slower than the one using vertical vector operations!

+

Performance profiling

+

While the rest of the book provides practical advice on how to improve the performance +of SIMD code, this chapter is dedicated to performance profiling. +Profiling consists of recording a program's execution in order to identify program +hotspots.

+

Important: most profilers require debug information in order to accurately +link the program hotspots back to the corresponding source code lines. Rust will +disable debug info generation by default for optimized builds, but you can change +that in your Cargo.toml.

+

Performance profiling on Linux

+

Using perf

+

perf is the most powerful performance profiler +for Linux, featuring support for various hardware Performance Monitoring Units, +as well as integration with the kernel's performance events framework.

+

We will only look at how can the perf command can be used to profile SIMD code. +Full system profiling is outside of the scope of this book.

+

Recording

+

The first step is to record a program's execution during an average workload. +It helps if you can isolate the parts of your program which have performance +issues, and set up a benchmark which can be easily (re)run.

+

Build the benchmark binary in release mode, after having enabled debug info:

+
$ cargo build --release
+Finished release [optimized + debuginfo] target(s) in 0.02s
+
+

Then use the perf record subcommand:

+
$ perf record --call-graph=dwarf ./target/release/my-program
+[ perf record: Woken up 10 times to write data ]
+[ perf record: Captured and wrote 2,356 MB perf.data (292 samples) ]
+
+

Instead of using --call-graph=dwarf, which can become pretty slow, you can use +--call-graph=lbr if you have a processor with support for Last Branch Record +(i.e. Intel Haswell and newer).

+

perf will, by default, record the count of CPU cycles it takes to execute +various parts of your program. You can use the -e command line option +to enable other performance events, such as cache-misses. Use perf list +to get a list of all hardware counters supported by your CPU.

+

Viewing the report

+

The next step is getting a bird's eye view of the program's execution. +perf provides a ncurses-based interface which will get you started.

+

Use perf report to open a visualization of your program's performance:

+
perf report --hierarchy -M intel
+
+

--hierarchy will display a tree-like structure of where your program spent +most of its time. -M intel enables disassembly output with Intel syntax, which +is subjectively more readable than the default AT&T syntax.

+

Here is the output from profiling the nbody benchmark:

+
- 100,00% nbody
+  - 94,18% nbody
+    + 93,48% [.] nbody_lib::simd::advance
+    + 0,70% [.] nbody_lib::run
+    + 5,06% libc-2.28.so
+
+

If you move with the arrow keys to any node in the tree, you can the press a +to have perf annotate that node. This means it will:

+
    +
  • +

    disassemble the function

    +
    • +
  • +

    associate every instruction with the percentage of time which was spent executing it

    +
    • +
  • +

    interleaves the disassembly with the source code, +assuming it found the debug symbols +(you can use s to toggle this behaviour)

    +
    • +
+

perf will, by default, open the instruction which it identified as being the +hottest spot in the function:

+
0,76  │ movapd xmm2,xmm0
+0,38  │ movhlps xmm2,xmm0
+      │ addpd  xmm2,xmm0
+      │ unpcklpd xmm1,xmm2
+12,50 │ sqrtpd xmm0,xmm1
+1,52  │ mulpd  xmm0,xmm1
+
+

In this case, sqrtpd will be highlighted in red, since that's the instruction +which the CPU spends most of its time executing.

+

Using Valgrind

+

Valgrind is a set of tools which initially helped C/C++ programmers find unsafe +memory accesses in their code. Nowadays the project also has

+
    +
  • +

    a heap profiler called massif

    +
    • +
  • +

    a cache utilization profiler called cachegrind

    +
    • +
  • +

    a call-graph performance profiler called callgrind

    +
    • +
+ +

Machine code analysis tools

+

The microarchitecture of modern CPUs

+

While you might have heard of Instruction Set Architectures, such as x86 or +arm or mips, the term microarchitecture (also written here as µ-arch), +refers to the internal details of an actual family of CPUs, such as Intel's +Haswell or AMD's Jaguar.

+

Replacing scalar code with SIMD code will improve performance on all CPUs +supporting the required vector extensions. +However, due to microarchitectural differences, the actual speed-up at +runtime might vary.

+

Example: a simple example arises when optimizing for AMD K8 CPUs. +The assembly generated for an empty function should look like this:

+
nop
+ret
+
+

The nop is used to align the ret instruction for better performance. +However, the compiler will actually generated the following code:

+
repz ret
+
+

The repz instruction will repeat the following instruction until a certain +condition. Of course, in this situation, the function will simply immediately +return, and the ret instruction is still aligned. +However, AMD K8's branch predictor performs better with the latter code.

+

For those looking to absolutely maximize performance for a certain target µ-arch, +you will have to read some CPU manuals, or ask the compiler to do it for you +with -C target-cpu.

+

Summary of CPU internals

+

Modern processors are able to execute instructions out-of-order for better performance, +by utilizing tricks such as branch prediction, instruction pipelining, +or superscalar execution.

+

SIMD instructions are also subject to these optimizations, meaning it can get pretty +difficult to determine where the slowdown happens. +For example, if the profiler reports a store operation is slow, one of two things +could be happening:

+
    +
  • +

    the store is limited by the CPU's memory bandwidth, which is actually an ideal +scenario, all things considered;

    +
    • +
  • +

    memory bandwidth is nowhere near its peak, but the value to be stored is at the +end of a long chain of operations, and this store is where the profiler +encountered the pipeline stall;

    +
    • +
+

Since most profilers are simple tools which don't understand the subtleties of +instruction scheduling, you

+

Analyzing the machine code

+

Certain tools have knowledge of internal CPU microarchitecture, i.e. they know

+
    +
  • +

    how many physical register files a CPU actually has

    +
    • +
  • +

    what is the latency / throughtput of an instruction

    +
    • +
  • +

    what µ-ops are generated for a set of instructions

    +
    • +
+

and many other architectural details.

+

These tools are therefore able to provide accurate information as to why some +instructions are inefficient, and where the bottleneck is.

+

The disadvantage is that the output of these tools requires advanced knowledge +of the target architecture to understand, i.e. they cannot point out what +the cause of the issue is explicitly.

+

Intel's Architecture Code Analyzer (IACA)

+

IACA is a free tool offered by Intel for analyzing the performance of various +computational kernels.

+

Being a proprietary, closed source tool, it only supports Intel's µ-arches.

+

llvm-mca

+ + +
+ + +
+
+ + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/perf-guide/prof/linux.html b/perf-guide/prof/linux.html new file mode 100644 index 000000000..9ad68e44e --- /dev/null +++ b/perf-guide/prof/linux.html @@ -0,0 +1,315 @@ + + + + + + Profiling on Linux - Rust SIMD Performance Guide + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ +
+ + + + + + + + + + + +
+
+

Performance profiling on Linux

+

Using perf

+

perf is the most powerful performance profiler +for Linux, featuring support for various hardware Performance Monitoring Units, +as well as integration with the kernel's performance events framework.

+

We will only look at how can the perf command can be used to profile SIMD code. +Full system profiling is outside of the scope of this book.

+

Recording

+

The first step is to record a program's execution during an average workload. +It helps if you can isolate the parts of your program which have performance +issues, and set up a benchmark which can be easily (re)run.

+

Build the benchmark binary in release mode, after having enabled debug info:

+
$ cargo build --release
+Finished release [optimized + debuginfo] target(s) in 0.02s
+
+

Then use the perf record subcommand:

+
$ perf record --call-graph=dwarf ./target/release/my-program
+[ perf record: Woken up 10 times to write data ]
+[ perf record: Captured and wrote 2,356 MB perf.data (292 samples) ]
+
+

Instead of using --call-graph=dwarf, which can become pretty slow, you can use +--call-graph=lbr if you have a processor with support for Last Branch Record +(i.e. Intel Haswell and newer).

+

perf will, by default, record the count of CPU cycles it takes to execute +various parts of your program. You can use the -e command line option +to enable other performance events, such as cache-misses. Use perf list +to get a list of all hardware counters supported by your CPU.

+

Viewing the report

+

The next step is getting a bird's eye view of the program's execution. +perf provides a ncurses-based interface which will get you started.

+

Use perf report to open a visualization of your program's performance:

+
perf report --hierarchy -M intel
+
+

--hierarchy will display a tree-like structure of where your program spent +most of its time. -M intel enables disassembly output with Intel syntax, which +is subjectively more readable than the default AT&T syntax.

+

Here is the output from profiling the nbody benchmark:

+
- 100,00% nbody
+  - 94,18% nbody
+    + 93,48% [.] nbody_lib::simd::advance
+    + 0,70% [.] nbody_lib::run
+    + 5,06% libc-2.28.so
+
+

If you move with the arrow keys to any node in the tree, you can the press a +to have perf annotate that node. This means it will:

+
    +
  • +

    disassemble the function

    +
    • +
  • +

    associate every instruction with the percentage of time which was spent executing it

    +
    • +
  • +

    interleaves the disassembly with the source code, +assuming it found the debug symbols +(you can use s to toggle this behaviour)

    +
    • +
+

perf will, by default, open the instruction which it identified as being the +hottest spot in the function:

+
0,76  │ movapd xmm2,xmm0
+0,38  │ movhlps xmm2,xmm0
+      │ addpd  xmm2,xmm0
+      │ unpcklpd xmm1,xmm2
+12,50 │ sqrtpd xmm0,xmm1
+1,52  │ mulpd  xmm0,xmm1
+
+

In this case, sqrtpd will be highlighted in red, since that's the instruction +which the CPU spends most of its time executing.

+

Using Valgrind

+

Valgrind is a set of tools which initially helped C/C++ programmers find unsafe +memory accesses in their code. Nowadays the project also has

+
    +
  • +

    a heap profiler called massif

    +
    • +
  • +

    a cache utilization profiler called cachegrind

    +
    • +
  • +

    a call-graph performance profiler called callgrind

    +
    • +
+ + +
+ + +
+
+ + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/perf-guide/prof/mca.html b/perf-guide/prof/mca.html new file mode 100644 index 000000000..64cc75c68 --- /dev/null +++ b/perf-guide/prof/mca.html @@ -0,0 +1,295 @@ + + + + + + Using machine code analyzers - Rust SIMD Performance Guide + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ +
+ + + + + + + + + + + +
+
+

Machine code analysis tools

+

The microarchitecture of modern CPUs

+

While you might have heard of Instruction Set Architectures, such as x86 or +arm or mips, the term microarchitecture (also written here as µ-arch), +refers to the internal details of an actual family of CPUs, such as Intel's +Haswell or AMD's Jaguar.

+

Replacing scalar code with SIMD code will improve performance on all CPUs +supporting the required vector extensions. +However, due to microarchitectural differences, the actual speed-up at +runtime might vary.

+

Example: a simple example arises when optimizing for AMD K8 CPUs. +The assembly generated for an empty function should look like this:

+
nop
+ret
+
+

The nop is used to align the ret instruction for better performance. +However, the compiler will actually generated the following code:

+
repz ret
+
+

The repz instruction will repeat the following instruction until a certain +condition. Of course, in this situation, the function will simply immediately +return, and the ret instruction is still aligned. +However, AMD K8's branch predictor performs better with the latter code.

+

For those looking to absolutely maximize performance for a certain target µ-arch, +you will have to read some CPU manuals, or ask the compiler to do it for you +with -C target-cpu.

+

Summary of CPU internals

+

Modern processors are able to execute instructions out-of-order for better performance, +by utilizing tricks such as branch prediction, instruction pipelining, +or superscalar execution.

+

SIMD instructions are also subject to these optimizations, meaning it can get pretty +difficult to determine where the slowdown happens. +For example, if the profiler reports a store operation is slow, one of two things +could be happening:

+
    +
  • +

    the store is limited by the CPU's memory bandwidth, which is actually an ideal +scenario, all things considered;

    +
    • +
  • +

    memory bandwidth is nowhere near its peak, but the value to be stored is at the +end of a long chain of operations, and this store is where the profiler +encountered the pipeline stall;

    +
    • +
+

Since most profilers are simple tools which don't understand the subtleties of +instruction scheduling, you

+

Analyzing the machine code

+

Certain tools have knowledge of internal CPU microarchitecture, i.e. they know

+
    +
  • +

    how many physical register files a CPU actually has

    +
    • +
  • +

    what is the latency / throughtput of an instruction

    +
    • +
  • +

    what µ-ops are generated for a set of instructions

    +
    • +
+

and many other architectural details.

+

These tools are therefore able to provide accurate information as to why some +instructions are inefficient, and where the bottleneck is.

+

The disadvantage is that the output of these tools requires advanced knowledge +of the target architecture to understand, i.e. they cannot point out what +the cause of the issue is explicitly.

+

Intel's Architecture Code Analyzer (IACA)

+

IACA is a free tool offered by Intel for analyzing the performance of various +computational kernels.

+

Being a proprietary, closed source tool, it only supports Intel's µ-arches.

+

llvm-mca

+ + +
+ + +
+
+ + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/perf-guide/prof/profiling.html b/perf-guide/prof/profiling.html new file mode 100644 index 000000000..a7ea66003 --- /dev/null +++ b/perf-guide/prof/profiling.html @@ -0,0 +1,237 @@ + + + + + + Performance profiling - Rust SIMD Performance Guide + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ +
+ + + + + + + + + + + +
+
+

Performance profiling

+

While the rest of the book provides practical advice on how to improve the performance +of SIMD code, this chapter is dedicated to performance profiling. +Profiling consists of recording a program's execution in order to identify program +hotspots.

+

Important: most profilers require debug information in order to accurately +link the program hotspots back to the corresponding source code lines. Rust will +disable debug info generation by default for optimized builds, but you can change +that in your Cargo.toml.

+ +
+ + +
+
+ + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/perf-guide/searcher.js b/perf-guide/searcher.js new file mode 100644 index 000000000..e1cc806b8 --- /dev/null +++ b/perf-guide/searcher.js @@ -0,0 +1,477 @@ +"use strict"; +window.search = window.search || {}; +(function search(search) { + // Search functionality + // + // You can use !hasFocus() to prevent keyhandling in your key + // event handlers while the user is typing their search. + + if (!Mark || !elasticlunr) { + return; + } + + //IE 11 Compatibility from https://developer.mozilla.org/en-US/docs/Web/JavaScript/Reference/Global_Objects/String/startsWith + if (!String.prototype.startsWith) { + String.prototype.startsWith = function(search, pos) { + return this.substr(!pos || pos < 0 ? 0 : +pos, search.length) === search; + }; + } + + var search_wrap = document.getElementById('search-wrapper'), + searchbar = document.getElementById('searchbar'), + searchbar_outer = document.getElementById('searchbar-outer'), + searchresults = document.getElementById('searchresults'), + searchresults_outer = document.getElementById('searchresults-outer'), + searchresults_header = document.getElementById('searchresults-header'), + searchicon = document.getElementById('search-toggle'), + content = document.getElementById('content'), + + searchindex = null, + doc_urls = [], + results_options = { + teaser_word_count: 30, + limit_results: 30, + }, + search_options = { + bool: "AND", + expand: true, + fields: { + title: {boost: 1}, + body: {boost: 1}, + breadcrumbs: {boost: 0} + } + }, + mark_exclude = [], + marker = new Mark(content), + current_searchterm = "", + URL_SEARCH_PARAM = 'search', + URL_MARK_PARAM = 'highlight', + teaser_count = 0, + + SEARCH_HOTKEY_KEYCODE = 83, + ESCAPE_KEYCODE = 27, + DOWN_KEYCODE = 40, + UP_KEYCODE = 38, + SELECT_KEYCODE = 13; + + function hasFocus() { + return searchbar === document.activeElement; + } + + function removeChildren(elem) { + while (elem.firstChild) { + elem.removeChild(elem.firstChild); + } + } + + // Helper to parse a url into its building blocks. + function parseURL(url) { + var a = document.createElement('a'); + a.href = url; + return { + source: url, + protocol: a.protocol.replace(':',''), + host: a.hostname, + port: a.port, + params: (function(){ + var ret = {}; + var seg = a.search.replace(/^\?/,'').split('&'); + var len = seg.length, i = 0, s; + for (;i': '>', + '"': '"', + "'": ''' + }; + var repl = function(c) { return MAP[c]; }; + return function(s) { + return s.replace(/[&<>'"]/g, repl); + }; + })(); + + function formatSearchMetric(count, searchterm) { + if (count == 1) { + return count + " search result for '" + searchterm + "':"; + } else if (count == 0) { + return "No search results for '" + searchterm + "'."; + } else { + return count + " search results for '" + searchterm + "':"; + } + } + + function formatSearchResult(result, searchterms) { + var teaser = makeTeaser(escapeHTML(result.doc.body), searchterms); + teaser_count++; + + // The ?URL_MARK_PARAM= parameter belongs inbetween the page and the #heading-anchor + var url = doc_urls[result.ref].split("#"); + if (url.length == 1) { // no anchor found + url.push(""); + } + + return '' + result.doc.breadcrumbs + '' + + '' + + teaser + ''; + } + + function makeTeaser(body, searchterms) { + // The strategy is as follows: + // First, assign a value to each word in the document: + // Words that correspond to search terms (stemmer aware): 40 + // Normal words: 2 + // First word in a sentence: 8 + // Then use a sliding window with a constant number of words and count the + // sum of the values of the words within the window. Then use the window that got the + // maximum sum. If there are multiple maximas, then get the last one. + // Enclose the terms in . + var stemmed_searchterms = searchterms.map(function(w) { + return elasticlunr.stemmer(w.toLowerCase()); + }); + var searchterm_weight = 40; + var weighted = []; // contains elements of ["word", weight, index_in_document] + // split in sentences, then words + var sentences = body.toLowerCase().split('. '); + var index = 0; + var value = 0; + var searchterm_found = false; + for (var sentenceindex in sentences) { + var words = sentences[sentenceindex].split(' '); + value = 8; + for (var wordindex in words) { + var word = words[wordindex]; + if (word.length > 0) { + for (var searchtermindex in stemmed_searchterms) { + if (elasticlunr.stemmer(word).startsWith(stemmed_searchterms[searchtermindex])) { + value = searchterm_weight; + searchterm_found = true; + } + }; + weighted.push([word, value, index]); + value = 2; + } + index += word.length; + index += 1; // ' ' or '.' if last word in sentence + }; + index += 1; // because we split at a two-char boundary '. ' + }; + + if (weighted.length == 0) { + return body; + } + + var window_weight = []; + var window_size = Math.min(weighted.length, results_options.teaser_word_count); + + var cur_sum = 0; + for (var wordindex = 0; wordindex < window_size; wordindex++) { + cur_sum += weighted[wordindex][1]; + }; + window_weight.push(cur_sum); + for (var wordindex = 0; wordindex < weighted.length - window_size; wordindex++) { + cur_sum -= weighted[wordindex][1]; + cur_sum += weighted[wordindex + window_size][1]; + window_weight.push(cur_sum); + }; + + if (searchterm_found) { + var max_sum = 0; + var max_sum_window_index = 0; + // backwards + for (var i = window_weight.length - 1; i >= 0; i--) { + if (window_weight[i] > max_sum) { + max_sum = window_weight[i]; + max_sum_window_index = i; + } + }; + } else { + max_sum_window_index = 0; + } + + // add around searchterms + var teaser_split = []; + var index = weighted[max_sum_window_index][2]; + for (var i = max_sum_window_index; i < max_sum_window_index+window_size; i++) { + var word = weighted[i]; + if (index < word[2]) { + // missing text from index to start of `word` + teaser_split.push(body.substring(index, word[2])); + index = word[2]; + } + if (word[1] == searchterm_weight) { + teaser_split.push("") + } + index = word[2] + word[0].length; + teaser_split.push(body.substring(word[2], index)); + if (word[1] == searchterm_weight) { + teaser_split.push("") + } + }; + + return teaser_split.join(''); + } + + function init(config) { + results_options = config.results_options; + search_options = config.search_options; + searchbar_outer = config.searchbar_outer; + doc_urls = config.doc_urls; + searchindex = elasticlunr.Index.load(config.index); + + // Set up events + searchicon.addEventListener('click', function(e) { searchIconClickHandler(); }, false); + searchbar.addEventListener('keyup', function(e) { searchbarKeyUpHandler(); }, false); + document.addEventListener('keydown', function(e) { globalKeyHandler(e); }, false); + // If the user uses the browser buttons, do the same as if a reload happened + window.onpopstate = function(e) { doSearchOrMarkFromUrl(); }; + // Suppress "submit" events so the page doesn't reload when the user presses Enter + document.addEventListener('submit', function(e) { e.preventDefault(); }, false); + + // If reloaded, do the search or mark again, depending on the current url parameters + doSearchOrMarkFromUrl(); + } + + function unfocusSearchbar() { + // hacky, but just focusing a div only works once + var tmp = document.createElement('input'); + tmp.setAttribute('style', 'position: absolute; opacity: 0;'); + searchicon.appendChild(tmp); + tmp.focus(); + tmp.remove(); + } + + // On reload or browser history backwards/forwards events, parse the url and do search or mark + function doSearchOrMarkFromUrl() { + // Check current URL for search request + var url = parseURL(window.location.href); + if (url.params.hasOwnProperty(URL_SEARCH_PARAM) + && url.params[URL_SEARCH_PARAM] != "") { + showSearch(true); + searchbar.value = decodeURIComponent( + (url.params[URL_SEARCH_PARAM]+'').replace(/\+/g, '%20')); + searchbarKeyUpHandler(); // -> doSearch() + } else { + showSearch(false); + } + + if (url.params.hasOwnProperty(URL_MARK_PARAM)) { + var words = url.params[URL_MARK_PARAM].split(' '); + marker.mark(words, { + exclude: mark_exclude + }); + + var markers = document.querySelectorAll("mark"); + function hide() { + for (var i = 0; i < markers.length; i++) { + markers[i].classList.add("fade-out"); + window.setTimeout(function(e) { marker.unmark(); }, 300); + } + } + for (var i = 0; i < markers.length; i++) { + markers[i].addEventListener('click', hide); + } + } + } + + // Eventhandler for keyevents on `document` + function globalKeyHandler(e) { + if (e.altKey || e.ctrlKey || e.metaKey || e.shiftKey || e.target.type === 'textarea' || e.target.type === 'text') { return; } + + if (e.keyCode === ESCAPE_KEYCODE) { + e.preventDefault(); + searchbar.classList.remove("active"); + setSearchUrlParameters("", + (searchbar.value.trim() !== "") ? "push" : "replace"); + if (hasFocus()) { + unfocusSearchbar(); + } + showSearch(false); + marker.unmark(); + } else if (!hasFocus() && e.keyCode === SEARCH_HOTKEY_KEYCODE) { + e.preventDefault(); + showSearch(true); + window.scrollTo(0, 0); + searchbar.select(); + } else if (hasFocus() && e.keyCode === DOWN_KEYCODE) { + e.preventDefault(); + unfocusSearchbar(); + searchresults.firstElementChild.classList.add("focus"); + } else if (!hasFocus() && (e.keyCode === DOWN_KEYCODE + || e.keyCode === UP_KEYCODE + || e.keyCode === SELECT_KEYCODE)) { + // not `:focus` because browser does annoying scrolling + var focused = searchresults.querySelector("li.focus"); + if (!focused) return; + e.preventDefault(); + if (e.keyCode === DOWN_KEYCODE) { + var next = focused.nextElementSibling; + if (next) { + focused.classList.remove("focus"); + next.classList.add("focus"); + } + } else if (e.keyCode === UP_KEYCODE) { + focused.classList.remove("focus"); + var prev = focused.previousElementSibling; + if (prev) { + prev.classList.add("focus"); + } else { + searchbar.select(); + } + } else { // SELECT_KEYCODE + window.location.assign(focused.querySelector('a')); + } + } + } + + function showSearch(yes) { + if (yes) { + search_wrap.classList.remove('hidden'); + searchicon.setAttribute('aria-expanded', 'true'); + } else { + search_wrap.classList.add('hidden'); + searchicon.setAttribute('aria-expanded', 'false'); + var results = searchresults.children; + for (var i = 0; i < results.length; i++) { + results[i].classList.remove("focus"); + } + } + } + + function showResults(yes) { + if (yes) { + searchresults_outer.classList.remove('hidden'); + } else { + searchresults_outer.classList.add('hidden'); + } + } + + // Eventhandler for search icon + function searchIconClickHandler() { + if (search_wrap.classList.contains('hidden')) { + showSearch(true); + window.scrollTo(0, 0); + searchbar.select(); + } else { + showSearch(false); + } + } + + // Eventhandler for keyevents while the searchbar is focused + function searchbarKeyUpHandler() { + var searchterm = searchbar.value.trim(); + if (searchterm != "") { + searchbar.classList.add("active"); + doSearch(searchterm); + } else { + searchbar.classList.remove("active"); + showResults(false); + removeChildren(searchresults); + } + + setSearchUrlParameters(searchterm, "push_if_new_search_else_replace"); + + // Remove marks + marker.unmark(); + } + + // Update current url with ?URL_SEARCH_PARAM= parameter, remove ?URL_MARK_PARAM and #heading-anchor . + // `action` can be one of "push", "replace", "push_if_new_search_else_replace" + // and replaces or pushes a new browser history item. + // "push_if_new_search_else_replace" pushes if there is no `?URL_SEARCH_PARAM=abc` yet. + function setSearchUrlParameters(searchterm, action) { + var url = parseURL(window.location.href); + var first_search = ! url.params.hasOwnProperty(URL_SEARCH_PARAM); + if (searchterm != "" || action == "push_if_new_search_else_replace") { + url.params[URL_SEARCH_PARAM] = searchterm; + delete url.params[URL_MARK_PARAM]; + url.hash = ""; + } else { + delete url.params[URL_SEARCH_PARAM]; + } + // A new search will also add a new history item, so the user can go back + // to the page prior to searching. A updated search term will only replace + // the url. + if (action == "push" || (action == "push_if_new_search_else_replace" && first_search) ) { + history.pushState({}, document.title, renderURL(url)); + } else if (action == "replace" || (action == "push_if_new_search_else_replace" && !first_search) ) { + history.replaceState({}, document.title, renderURL(url)); + } + } + + function doSearch(searchterm) { + + // Don't search the same twice + if (current_searchterm == searchterm) { return; } + else { current_searchterm = searchterm; } + + if (searchindex == null) { return; } + + // Do the actual search + var results = searchindex.search(searchterm, search_options); + var resultcount = Math.min(results.length, results_options.limit_results); + + // Display search metrics + searchresults_header.innerText = formatSearchMetric(resultcount, searchterm); + + // Clear and insert results + var searchterms = searchterm.split(' '); + removeChildren(searchresults); + for(var i = 0; i < resultcount ; i++){ + var resultElem = document.createElement('li'); + resultElem.innerHTML = formatSearchResult(results[i], searchterms); + searchresults.appendChild(resultElem); + } + + // Display results + showResults(true); + } + + fetch(path_to_root + 'searchindex.json') + .then(response => response.json()) + .then(json => init(json)) + .catch(error => { // Try to load searchindex.js if fetch failed + var script = document.createElement('script'); + script.src = path_to_root + 'searchindex.js'; + script.onload = () => init(window.search); + document.head.appendChild(script); + }); + + // Exported functions + search.hasFocus = hasFocus; +})(window.search); diff --git a/perf-guide/searchindex.js b/perf-guide/searchindex.js new file mode 100644 index 000000000..a70d0d120 --- /dev/null +++ b/perf-guide/searchindex.js @@ -0,0 +1 @@ +Object.assign(window.search, {"doc_urls":["introduction.html#introduction","introduction.html#what-is-simd","introduction.html#history-of-simd-in-rust","introduction.html#discover-packed_simd","float-math/fp.html#floating-point-math","float-math/svml.html#short-vector-math-library","float-math/approx.html#approximate-functions","float-math/fma.html#fused-multiply-add","target-feature/features.html#enabling-target-features","target-feature/rustflags.html#using-rustflags","target-feature/rustflags.html#target-feature","target-feature/rustflags.html#target-cpu","target-feature/attribute.html#the-target_feature-attribute","target-feature/inlining.html#inlining","target-feature/runtime.html#detecting-host-features-at-runtime","bound_checks.html#bounds-checking","vert-hor-ops.html#vertical-and-horizontal-operations","vert-hor-ops.html#performance-consideration-of-horizontal-operations","prof/profiling.html#performance-profiling","prof/linux.html#performance-profiling-on-linux","prof/linux.html#using-perf","prof/linux.html#recording","prof/linux.html#viewing-the-report","prof/linux.html#using-valgrind","prof/mca.html#machine-code-analysis-tools","prof/mca.html#the-microarchitecture-of-modern-cpus","prof/mca.html#summary-of-cpu-internals","prof/mca.html#analyzing-the-machine-code","prof/mca.html#intels-architecture-code-analyzer-iaca","prof/mca.html#llvm-mca"],"index":{"documentStore":{"docInfo":{"0":{"body":0,"breadcrumbs":1,"title":1},"1":{"body":0,"breadcrumbs":1,"title":1},"10":{"body":102,"breadcrumbs":4,"title":2},"11":{"body":92,"breadcrumbs":4,"title":2},"12":{"body":0,"breadcrumbs":4,"title":2},"13":{"body":0,"breadcrumbs":3,"title":1},"14":{"body":0,"breadcrumbs":6,"title":4},"15":{"body":74,"breadcrumbs":2,"title":2},"16":{"body":77,"breadcrumbs":3,"title":3},"17":{"body":130,"breadcrumbs":4,"title":4},"18":{"body":47,"breadcrumbs":2,"title":2},"19":{"body":0,"breadcrumbs":5,"title":3},"2":{"body":0,"breadcrumbs":3,"title":3},"20":{"body":31,"breadcrumbs":4,"title":2},"21":{"body":113,"breadcrumbs":3,"title":1},"22":{"body":127,"breadcrumbs":4,"title":2},"23":{"body":29,"breadcrumbs":4,"title":2},"24":{"body":0,"breadcrumbs":6,"title":4},"25":{"body":115,"breadcrumbs":5,"title":3},"26":{"body":71,"breadcrumbs":5,"title":3},"27":{"body":47,"breadcrumbs":5,"title":3},"28":{"body":18,"breadcrumbs":7,"title":5},"29":{"body":0,"breadcrumbs":4,"title":2},"3":{"body":29,"breadcrumbs":2,"title":2},"4":{"body":8,"breadcrumbs":3,"title":3},"5":{"body":0,"breadcrumbs":7,"title":4},"6":{"body":0,"breadcrumbs":5,"title":2},"7":{"body":0,"breadcrumbs":6,"title":3},"8":{"body":55,"breadcrumbs":3,"title":3},"9":{"body":35,"breadcrumbs":4,"title":2}},"docs":{"0":{"body":"","breadcrumbs":"Introduction","id":"0","title":"Introduction"},"1":{"body":"","breadcrumbs":"What is SIMD","id":"1","title":"What is SIMD"},"10":{"body":"Syntax: -C target-feature= Provides the compiler with a comma-separated set of instruction extensions to enable. Example : Use -C target-features=+sse3,+avx to enable generating instructions for Streaming SIMD Extensions 3 and Advanced Vector Extensions . To list target triples for all targets supported by Rust, use: rustc --print target-list To list all support target features for a certain target triple, use: rustc --target=${TRIPLE} --print target-features Note that all CPU features are independent, and will have to be enabled individually. Example : Setting -C target-features=+avx2 will not enable fma, even though all CPUs which support AVX2 also support FMA. To enable both, one has to use -C target-features=+avx2,+fma Some features also depend on other features, which need to be enabled for the target instructions to be generated. Example : Unless v7 is specified as the target CPU (see below), to enable NEON on ARM it is necessary to use -C target-feature=+v7,+neon.","breadcrumbs":"Target features » target-feature","id":"10","title":"target-feature"},"11":{"body":"Syntax: -C target-cpu= Sets the identifier of a CPU family / model for which to build and optimize the code. Example : RUSTFLAGS='-C target-cpu=cortex-a75' To list all supported target CPUs for a certain target triple, use: rustc --target=${TRIPLE} --print target-cpus Example : rustc --target=i686-pc-windows-msvc --print target-cpus The compiler will translate this into a list of target features. Therefore, individual feature checks (#[cfg(target_feature = \"...\")]) will still work properly. It will cause the code generator to optimize the generated code for that specific CPU model. Using native as the CPU model will cause Rust to generate and optimize code for the CPU running the compiler. It is useful when building programs which you plan to only use locally. This should never be used when the generated programs are meant to be run on other computers, such as when packaging for distribution or cross-compiling.","breadcrumbs":"Target features » target-cpu","id":"11","title":"target-cpu"},"12":{"body":"","breadcrumbs":"Target features » The target_feature attribute","id":"12","title":"The target_feature attribute"},"13":{"body":"","breadcrumbs":"Target features » Inlining","id":"13","title":"Inlining"},"14":{"body":"","breadcrumbs":"Target features » Detecting host features at runtime","id":"14","title":"Detecting host features at runtime"},"15":{"body":"Reading and writing packed vectors to/from slices is checked by default. Independently of the configuration options used, the safe functions: Simd<[T; N]>::from_slice_aligned(& s[..]) Simd<[T; N]>::write_to_slice_aligned(&mut s[..]) always check that: the slice is big enough to hold the vector the slice is suitably aligned to perform an aligned load/store for a Simd<[T; N]> (this alignment is often much larger than that of T). There are _unaligned versions that use unaligned load and stores, as well as unsafe _unchecked that do not perform any checks iff debug-assertions = false / debug = false. That is, the _unchecked methods do still assert size and alignment in debug builds and could also do so in release builds depending on the configuration options. These assertions do often significantly impact performance and you should be aware of them.","breadcrumbs":"Bounds checking","id":"15","title":"Bounds checking"},"16":{"body":"In SIMD terminology, each vector has a certain \"width\" (number of lanes). A vector processor is able to perform two kinds of operations on a vector: Vertical operations: operate on two vectors of the same width, result has same width Example : vertical addition of two f32x4 vectors %0 == | 2 | -3.5 | 0 | 7 | + + + + %1 == | 4 | 1.5 | -1 | 0 | = = = =\n%0 + %1 == | 6 | -2 | -1 | 7 | Horizontal operations: reduce the elements of two vectors in some way, the result's elements combine information from the two original ones Example : horizontal addition of two u64x2 vectors %0 == | 1 | 3 | └─+───┘ └───────┐ │ %1 == | 4 | -1 | │ └─+──┘ │ └───┐ │ │ │ ┌─────│───┘ ▼ ▼\n%0 + %1 == | 4 | 3 |","breadcrumbs":"Vertical and horizontal operations","id":"16","title":"Vertical and horizontal operations"},"17":{"body":"The result of vertical operations, like vector negation: -a, for a given lane, does not depend on the result of the operation for the other lanes. The result of horizontal operations, like the vector sum reduction: a.sum(), depends on the value of all vector lanes. In virtually all architectures vertical operations are fast, while horizontal operations are, by comparison, very slow. Consider the following two functions for computing the sum of all f32 values in a slice: fn fast_sum(x: &[f32]) -> f32 { assert!(x.len() % 4 == 0); let mut sum = f32x4::splat(0.); // [0., 0., 0., 0.] for i in (0..x.len()).step_by(4) { sum += f32x4::from_slice_unaligned(&x[i..]); } sum.sum()\n} fn slow_sum(x: &[f32]) -> f32 { assert!(x.len() % 4 == 0); let mut sum: f32 = 0.; for i in (0..x.len()).step_by(4) { sum += f32x4::from_slice_unaligned(&x[i..]).sum(); } sum\n} The inner loop over the slice is where the bulk of the work actually happens. There, the fast_sum function perform vertical operations into a vector, doing a single horizontal reduction at the end, while the slow_sum function performs horizontal vector operations inside of the loop. On all widely-used architectures, fast_sum is a large constant factor faster than slow_sum. You can run the slice_sum example and see for yourself. On the particular machine tested there the algorithm using the horizontal vector addition is 2.7x slower than the one using vertical vector operations!","breadcrumbs":"Performance consideration of horizontal operations","id":"17","title":"Performance consideration of horizontal operations"},"18":{"body":"While the rest of the book provides practical advice on how to improve the performance of SIMD code, this chapter is dedicated to performance profiling . Profiling consists of recording a program's execution in order to identify program hotspots. Important : most profilers require debug information in order to accurately link the program hotspots back to the corresponding source code lines. Rust will disable debug info generation by default for optimized builds, but you can change that in your Cargo.toml .","breadcrumbs":"Performance profiling","id":"18","title":"Performance profiling"},"19":{"body":"","breadcrumbs":"Performance profiling » Performance profiling on Linux","id":"19","title":"Performance profiling on Linux"},"2":{"body":"","breadcrumbs":"History of SIMD in Rust","id":"2","title":"History of SIMD in Rust"},"20":{"body":"perf is the most powerful performance profiler for Linux, featuring support for various hardware Performance Monitoring Units, as well as integration with the kernel's performance events framework. We will only look at how can the perf command can be used to profile SIMD code. Full system profiling is outside of the scope of this book.","breadcrumbs":"Performance profiling » Using perf","id":"20","title":"Using perf"},"21":{"body":"The first step is to record a program's execution during an average workload. It helps if you can isolate the parts of your program which have performance issues, and set up a benchmark which can be easily (re)run. Build the benchmark binary in release mode, after having enabled debug info: $ cargo build --release\nFinished release [optimized + debuginfo] target(s) in 0.02s Then use the perf record subcommand: $ perf record --call-graph=dwarf ./target/release/my-program\n[ perf record: Woken up 10 times to write data ]\n[ perf record: Captured and wrote 2,356 MB perf.data (292 samples) ] Instead of using --call-graph=dwarf, which can become pretty slow, you can use --call-graph=lbr if you have a processor with support for Last Branch Record (i.e. Intel Haswell and newer). perf will, by default, record the count of CPU cycles it takes to execute various parts of your program. You can use the -e command line option to enable other performance events, such as cache-misses. Use perf list to get a list of all hardware counters supported by your CPU.","breadcrumbs":"Performance profiling » Recording","id":"21","title":"Recording"},"22":{"body":"The next step is getting a bird's eye view of the program's execution. perf provides a ncurses-based interface which will get you started. Use perf report to open a visualization of your program's performance: perf report --hierarchy -M intel --hierarchy will display a tree-like structure of where your program spent most of its time. -M intel enables disassembly output with Intel syntax, which is subjectively more readable than the default AT&T syntax. Here is the output from profiling the nbody benchmark: - 100,00% nbody - 94,18% nbody + 93,48% [.] nbody_lib::simd::advance + 0,70% [.] nbody_lib::run + 5,06% libc-2.28.so If you move with the arrow keys to any node in the tree, you can the press a to have perf annotate that node. This means it will: disassemble the function associate every instruction with the percentage of time which was spent executing it interleaves the disassembly with the source code, assuming it found the debug symbols (you can use s to toggle this behaviour) perf will, by default, open the instruction which it identified as being the hottest spot in the function: 0,76 │ movapd xmm2,xmm0\n0,38 │ movhlps xmm2,xmm0 │ addpd xmm2,xmm0 │ unpcklpd xmm1,xmm2\n12,50 │ sqrtpd xmm0,xmm1\n1,52 │ mulpd xmm0,xmm1 In this case, sqrtpd will be highlighted in red, since that's the instruction which the CPU spends most of its time executing.","breadcrumbs":"Performance profiling » Viewing the report","id":"22","title":"Viewing the report"},"23":{"body":"Valgrind is a set of tools which initially helped C/C++ programmers find unsafe memory accesses in their code. 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Independently of the configuration options used, the safe functions: Simd<[T; N]>::from_slice_aligned(& s[..]) Simd<[T; N]>::write_to_slice_aligned(&mut s[..]) always check that: the slice is big enough to hold the vector the slice is suitably aligned to perform an aligned load/store for a Simd<[T; N]> (this alignment is often much larger than that of T). There are _unaligned versions that use unaligned load and stores, as well as unsafe _unchecked that do not perform any checks iff debug-assertions = false / debug = false. That is, the _unchecked methods do still assert size and alignment in debug builds and could also do so in release builds depending on the configuration options. These assertions do often significantly impact performance and you should be aware of them.","breadcrumbs":"Bounds checking","id":"15","title":"Bounds checking"},"16":{"body":"In SIMD terminology, each vector has a certain \"width\" (number of lanes). A vector processor is able to perform two kinds of operations on a vector: Vertical operations: operate on two vectors of the same width, result has same width Example : vertical addition of two f32x4 vectors %0 == | 2 | -3.5 | 0 | 7 | + + + + %1 == | 4 | 1.5 | -1 | 0 | = = = =\n%0 + %1 == | 6 | -2 | -1 | 7 | Horizontal operations: reduce the elements of two vectors in some way, the result's elements combine information from the two original ones Example : horizontal addition of two u64x2 vectors %0 == | 1 | 3 | └─+───┘ └───────┐ │ %1 == | 4 | -1 | │ └─+──┘ │ └───┐ │ │ │ ┌─────│───┘ ▼ ▼\n%0 + %1 == | 4 | 3 |","breadcrumbs":"Vertical and horizontal operations","id":"16","title":"Vertical and horizontal operations"},"17":{"body":"The result of vertical operations, like vector negation: -a, for a given lane, does not depend on the result of the operation for the other lanes. The result of horizontal operations, like the vector sum reduction: a.sum(), depends on the value of all vector lanes. In virtually all architectures vertical operations are fast, while horizontal operations are, by comparison, very slow. Consider the following two functions for computing the sum of all f32 values in a slice: fn fast_sum(x: &[f32]) -> f32 { assert!(x.len() % 4 == 0); let mut sum = f32x4::splat(0.); // [0., 0., 0., 0.] for i in (0..x.len()).step_by(4) { sum += f32x4::from_slice_unaligned(&x[i..]); } sum.sum()\n} fn slow_sum(x: &[f32]) -> f32 { assert!(x.len() % 4 == 0); let mut sum: f32 = 0.; for i in (0..x.len()).step_by(4) { sum += f32x4::from_slice_unaligned(&x[i..]).sum(); } sum\n} The inner loop over the slice is where the bulk of the work actually happens. There, the fast_sum function perform vertical operations into a vector, doing a single horizontal reduction at the end, while the slow_sum function performs horizontal vector operations inside of the loop. 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This means it will: disassemble the function associate every instruction with the percentage of time which was spent executing it interleaves the disassembly with the source code, assuming it found the debug symbols (you can use s to toggle this behaviour) perf will, by default, open the instruction which it identified as being the hottest spot in the function: 0,76 │ movapd xmm2,xmm0\n0,38 │ movhlps xmm2,xmm0 │ addpd xmm2,xmm0 │ unpcklpd xmm1,xmm2\n12,50 │ sqrtpd xmm0,xmm1\n1,52 │ mulpd xmm0,xmm1 In this case, sqrtpd will be highlighted in red, since that's the instruction which the CPU spends most of its time executing.","breadcrumbs":"Performance profiling » Viewing the report","id":"22","title":"Viewing the report"},"23":{"body":"Valgrind is a set of tools which initially helped C/C++ programmers find unsafe memory accesses in their code. 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\ No newline at end of file diff --git a/perf-guide/src/ascii.css b/perf-guide/src/ascii.css new file mode 100644 index 000000000..4c0265119 --- /dev/null +++ b/perf-guide/src/ascii.css @@ -0,0 +1,4 @@ +code { + /* "Source Code Pro" breaks ASCII art */ + font-family: Consolas, "Ubuntu Mono", Menlo, "DejaVu Sans Mono", monospace; +} diff --git a/perf-guide/target-feature/attribute.html b/perf-guide/target-feature/attribute.html new file mode 100644 index 000000000..15c1be9c4 --- /dev/null +++ b/perf-guide/target-feature/attribute.html @@ -0,0 +1,232 @@ + + + + + + Using the target_feature attribute - Rust SIMD Performance Guide + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ +
+ + + + + + + + + + + +
+
+

The target_feature attribute

+ + +
+ + +
+
+ + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/perf-guide/target-feature/features.html b/perf-guide/target-feature/features.html new file mode 100644 index 000000000..058bc6bdb --- /dev/null +++ b/perf-guide/target-feature/features.html @@ -0,0 +1,237 @@ + + + + + + Target features - Rust SIMD Performance Guide + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ +
+ + + + + + + + + + + +
+
+

Enabling target features

+

Not all processors of a certain architecture will have SIMD processing units, +and using a SIMD instruction which is not supported will trigger undefined behavior.

+

To allow building safe, portable programs, the Rust compiler will not, by default, +generate any sort of vector instructions, unless it can statically determine +they are supported. For example, on AMD64, SSE2 support is architecturally guaranteed. +The x86_64-apple-darwin target enables up to SSSE3. The get a defintive list of +which features are enabled by default on various platforms, refer to the target +specifications in the compiler's source code.

+ +
+ + +
+
+ + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/perf-guide/target-feature/inlining.html b/perf-guide/target-feature/inlining.html new file mode 100644 index 000000000..cb1de3b72 --- /dev/null +++ b/perf-guide/target-feature/inlining.html @@ -0,0 +1,232 @@ + + + + + + Interaction with inlining - Rust SIMD Performance Guide + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ +
+ + + + + + + + + + + +
+
+

Inlining

+ + +
+ + +
+
+ + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/perf-guide/target-feature/runtime.html b/perf-guide/target-feature/runtime.html new file mode 100644 index 000000000..a44258903 --- /dev/null +++ b/perf-guide/target-feature/runtime.html @@ -0,0 +1,232 @@ + + + + + + Detecting features at runtime - Rust SIMD Performance Guide + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ +
+ + + + + + + + + + + +
+
+

Detecting host features at runtime

+ + +
+ + +
+
+ + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/perf-guide/target-feature/rustflags.html b/perf-guide/target-feature/rustflags.html new file mode 100644 index 000000000..26906316e --- /dev/null +++ b/perf-guide/target-feature/rustflags.html @@ -0,0 +1,303 @@ + + + + + + Using RUSTFLAGS - Rust SIMD Performance Guide + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ +
+ + + + + + + + + + + +
+
+

Using RUSTFLAGS

+

One of the easiest ways to benefit from SIMD is to allow the compiler +to generate code using certain vector instruction extensions.

+

The environment variable RUSTFLAGS can be used to pass options for code +generation to the Rust compiler. These flags will affect all compiled crates.

+

There are two flags which can be used to enable specific vector extensions:

+

target-feature

+
    +
  • +

    Syntax: -C target-feature=<features>

    +
    • +
  • +

    Provides the compiler with a comma-separated set of instruction extensions +to enable.

    +

    Example: Use -C target-features=+sse3,+avx to enable generating instructions +for Streaming SIMD Extensions 3 and +Advanced Vector Extensions.

    +
    • +
  • +

    To list target triples for all targets supported by Rust, use:

    +
    rustc --print target-list
+
    +
    • +
  • +

    To list all support target features for a certain target triple, use:

    +
    rustc --target=${TRIPLE} --print target-features
+
    +
    • +
  • +

    Note that all CPU features are independent, and will have to be enabled individually.

    +

    Example: Setting -C target-features=+avx2 will not enable fma, even though +all CPUs which support AVX2 also support FMA. To enable both, one has to use +-C target-features=+avx2,+fma

    +
    • +
  • +

    Some features also depend on other features, which need to be enabled for the +target instructions to be generated.

    +

    Example: Unless v7 is specified as the target CPU (see below), to enable +NEON on ARM it is necessary to use -C target-feature=+v7,+neon.

    +
    • +
+

target-cpu

+
    +
  • +

    Syntax: -C target-cpu=<cpu>

    +
    • +
  • +

    Sets the identifier of a CPU family / model for which to build and optimize the code.

    +

    Example: RUSTFLAGS='-C target-cpu=cortex-a75'

    +
    • +
  • +

    To list all supported target CPUs for a certain target triple, use:

    +
    rustc --target=${TRIPLE} --print target-cpus
+
    +

    Example:

    +
    rustc --target=i686-pc-windows-msvc --print target-cpus
+
    +
    • +
  • +

    The compiler will translate this into a list of target features. Therefore, +individual feature checks (#[cfg(target_feature = "...")]) will still +work properly.

    +
    • +
  • +

    It will cause the code generator to optimize the generated code for that +specific CPU model.

    +
    • +
  • +

    Using native as the CPU model will cause Rust to generate and optimize code +for the CPU running the compiler. It is useful when building programs which you +plan to only use locally. This should never be used when the generated programs +are meant to be run on other computers, such as when packaging for distribution +or cross-compiling.

    +
    • +
+ +
+ + +
+
+ + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/perf-guide/tomorrow-night.css b/perf-guide/tomorrow-night.css new file mode 100644 index 000000000..f71979258 --- /dev/null +++ b/perf-guide/tomorrow-night.css @@ -0,0 +1,104 @@ +/* Tomorrow Night Theme */ +/* http://jmblog.github.com/color-themes-for-google-code-highlightjs */ +/* Original theme - https://github.com/chriskempson/tomorrow-theme */ +/* http://jmblog.github.com/color-themes-for-google-code-highlightjs */ + +/* Tomorrow Comment */ +.hljs-comment { + color: #969896; +} + +/* Tomorrow Red */ +.hljs-variable, +.hljs-attribute, +.hljs-tag, +.hljs-regexp, +.ruby .hljs-constant, +.xml .hljs-tag .hljs-title, +.xml .hljs-pi, +.xml .hljs-doctype, +.html .hljs-doctype, +.css .hljs-id, +.css .hljs-class, +.css .hljs-pseudo { + color: #cc6666; +} + +/* Tomorrow Orange */ +.hljs-number, +.hljs-preprocessor, +.hljs-pragma, +.hljs-built_in, +.hljs-literal, +.hljs-params, +.hljs-constant { + color: #de935f; +} + +/* Tomorrow Yellow */ +.ruby .hljs-class .hljs-title, +.css .hljs-rule .hljs-attribute { + color: #f0c674; +} + +/* Tomorrow Green */ +.hljs-string, +.hljs-value, +.hljs-inheritance, +.hljs-header, +.hljs-name, +.ruby .hljs-symbol, +.xml .hljs-cdata { + color: #b5bd68; +} + +/* Tomorrow Aqua */ +.hljs-title, +.css .hljs-hexcolor { + color: #8abeb7; +} + +/* Tomorrow Blue */ +.hljs-function, +.python .hljs-decorator, +.python .hljs-title, +.ruby .hljs-function .hljs-title, +.ruby .hljs-title .hljs-keyword, +.perl .hljs-sub, +.javascript .hljs-title, +.coffeescript .hljs-title { + color: #81a2be; +} + +/* Tomorrow Purple */ +.hljs-keyword, +.javascript .hljs-function { + color: #b294bb; +} + +.hljs { + display: block; + overflow-x: auto; + background: #1d1f21; + color: #c5c8c6; + padding: 0.5em; + -webkit-text-size-adjust: none; +} + +.coffeescript .javascript, +.javascript .xml, +.tex .hljs-formula, +.xml .javascript, +.xml .vbscript, +.xml .css, +.xml .hljs-cdata { + opacity: 0.5; +} + +.hljs-addition { + color: #718c00; +} + +.hljs-deletion { + color: #c82829; +} diff --git a/perf-guide/vert-hor-ops.html b/perf-guide/vert-hor-ops.html new file mode 100644 index 000000000..4028f6f5c --- /dev/null +++ b/perf-guide/vert-hor-ops.html @@ -0,0 +1,299 @@ + + + + + + Vertical and horizontal operations - Rust SIMD Performance Guide + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ +
+ + + + + + + + + + + +
+
+

Vertical and horizontal operations

+

In SIMD terminology, each vector has a certain "width" (number of lanes). +A vector processor is able to perform two kinds of operations on a vector:

+
    +
  • Vertical operations: +operate on two vectors of the same width, result has same width
    • +
+

Example: vertical addition of two f32x4 vectors

+
  %0     == | 2 | -3.5 |  0 | 7 |
+              +     +     +   +
+  %1     == | 4 |  1.5 | -1 | 0 |
+              =     =     =   =
+%0 + %1  == | 6 |  -2  | -1 | 7 |
+
+
    +
  • Horizontal operations: +reduce the elements of two vectors in some way, +the result's elements combine information from the two original ones
    • +
+

Example: horizontal addition of two u64x2 vectors

+
  %0     == | 1 |  3 |
+              └─+───┘
+                └───────┐
+                        │
+  %1     == | 4 | -1 |  │
+              └─+──┘    │
+                └───┐   │
+                    │   │
+              ┌─────│───┘
+              ▼     ▼
+%0 + %1  == | 4 |   3 |
+
+

Performance consideration of horizontal operations

+

The result of vertical operations, like vector negation: -a, for a given lane, +does not depend on the result of the operation for the other lanes. The result +of horizontal operations, like the vector sum reduction: a.sum(), depends on +the value of all vector lanes.

+

In virtually all architectures vertical operations are fast, while horizontal +operations are, by comparison, very slow.

+

Consider the following two functions for computing the sum of all f32 values +in a slice:

+

+#![allow(unused)]
+fn main() {
+fn fast_sum(x: &[f32]) -> f32 {
+    assert!(x.len() % 4 == 0);
+    let mut sum = f32x4::splat(0.); // [0., 0., 0., 0.]
+    for i in (0..x.len()).step_by(4) {
+        sum += f32x4::from_slice_unaligned(&x[i..]);
+    }
+    sum.sum()
+}
+
+fn slow_sum(x: &[f32]) -> f32 {
+    assert!(x.len() % 4 == 0);
+    let mut sum: f32 = 0.;
+    for i in (0..x.len()).step_by(4) {
+        sum += f32x4::from_slice_unaligned(&x[i..]).sum();
+    }
+    sum
+}
+}
+
+

The inner loop over the slice is where the bulk of the work actually happens. +There, the fast_sum function perform vertical operations into a vector, doing +a single horizontal reduction at the end, while the slow_sum function performs +horizontal vector operations inside of the loop.

+

On all widely-used architectures, fast_sum is a large constant factor faster +than slow_sum. You can run the slice_sum example and see for yourself. On +the particular machine tested there the algorithm using the horizontal vector +addition is 2.7x slower than the one using vertical vector operations!

+ +
+ + +
+
+ + + +
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is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"all","","Are `all` vector lanes `true`?",6,[[]]],[11,"any","","Is `any` vector lane `true`?",6,[[]]],[11,"none","","Are `all` vector lanes `false`?",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m8x2",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m8x2",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m8x2",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m8x2",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m8x2",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m8x2",6]]],[11,"select","","Selects elements of `a` and `b` using mask.",6,[[["simd",3]],["simd",3]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["m8x2",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["m8x2",6],["lexicographicallyordered",3]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",6,[[["i8x4",6]],["i8x4",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",6,[[["i8x4",6]],["i8x4",6]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",6,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the 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target\'s…",6,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",6,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",6,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",6,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m8x4",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m8x4",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m8x4",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m8x4",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m8x4",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m8x4",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["lexicographicallyordered",3],["i8x4",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["lexicographicallyordered",3],["i8x4",6]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",6,[[["u8x4",6]],["u8x4",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",6,[[["u8x4",6]],["u8x4",6]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",6,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",6,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",6,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",6,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",6,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",6,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",6,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",6,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",6,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m8x4",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m8x4",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m8x4",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m8x4",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m8x4",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m8x4",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["u8x4",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["u8x4",6],["lexicographicallyordered",3]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"all","","Are `all` vector lanes `true`?",6,[[]]],[11,"any","","Is `any` vector lane `true`?",6,[[]]],[11,"none","","Are `all` vector lanes `false`?",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m8x4",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m8x4",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m8x4",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m8x4",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m8x4",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m8x4",6]]],[11,"select","","Selects elements of `a` and `b` using mask.",6,[[["simd",3]],["simd",3]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["lexicographicallyordered",3],["m8x4",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["lexicographicallyordered",3],["m8x4",6]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",6,[[["i16x2",6]],["i16x2",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",6,[[["i16x2",6]],["i16x2",6]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",6,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",6,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",6,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",6,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",6,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",6,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",6,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",6,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",6,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m16x2",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m16x2",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m16x2",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m16x2",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m16x2",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m16x2",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["lexicographicallyordered",3],["i16x2",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["lexicographicallyordered",3],["i16x2",6]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",6,[[["u16x2",6]],["u16x2",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",6,[[["u16x2",6]],["u16x2",6]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",6,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",6,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",6,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",6,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",6,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",6,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",6,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",6,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",6,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m16x2",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m16x2",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m16x2",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m16x2",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m16x2",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m16x2",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["u16x2",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["u16x2",6],["lexicographicallyordered",3]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"all","","Are `all` vector lanes `true`?",6,[[]]],[11,"any","","Is `any` vector lane `true`?",6,[[]]],[11,"none","","Are `all` vector lanes `false`?",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m16x2",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m16x2",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m16x2",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m16x2",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m16x2",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m16x2",6]]],[11,"select","","Selects elements of `a` and `b` using mask.",6,[[["simd",3]],["simd",3]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["lexicographicallyordered",3],["m16x2",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["lexicographicallyordered",3],["m16x2",6]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",6,[[["i8x8",6]],["i8x8",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",6,[[["i8x8",6]],["i8x8",6]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",6,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",6,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",6,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",6,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",6,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",6,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",6,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",6,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",6,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m8x8",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m8x8",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m8x8",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m8x8",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m8x8",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m8x8",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["lexicographicallyordered",3],["i8x8",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["lexicographicallyordered",3],["i8x8",6]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",6,[[["u8x8",6]],["u8x8",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",6,[[["u8x8",6]],["u8x8",6]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",6,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector 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values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",6,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",6,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",6,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",6,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",6,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",6,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",6,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",6,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m8x8",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m8x8",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m8x8",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m8x8",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m8x8",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m8x8",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["lexicographicallyordered",3],["u8x8",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["lexicographicallyordered",3],["u8x8",6]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"all","","Are `all` vector lanes `true`?",6,[[]]],[11,"any","","Is `any` vector lane `true`?",6,[[]]],[11,"none","","Are `all` vector lanes `false`?",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m8x8",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m8x8",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m8x8",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m8x8",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m8x8",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m8x8",6]]],[11,"select","","Selects elements of `a` and `b` using mask.",6,[[["simd",3]],["simd",3]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["lexicographicallyordered",3],["m8x8",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["lexicographicallyordered",3],["m8x8",6]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",6,[[["i16x4",6]],["i16x4",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",6,[[["i16x4",6]],["i16x4",6]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",6,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",6,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",6,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",6,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",6,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",6,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",6,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",6,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",6,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m16x4",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m16x4",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m16x4",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m16x4",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m16x4",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m16x4",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["i16x4",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["i16x4",6],["lexicographicallyordered",3]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",6,[[["u16x4",6]],["u16x4",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",6,[[["u16x4",6]],["u16x4",6]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",6,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",6,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",6,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",6,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",6,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",6,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",6,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",6,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",6,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m16x4",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m16x4",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m16x4",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m16x4",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m16x4",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m16x4",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["lexicographicallyordered",3],["u16x4",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["lexicographicallyordered",3],["u16x4",6]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"all","","Are `all` vector lanes `true`?",6,[[]]],[11,"any","","Is `any` vector lane `true`?",6,[[]]],[11,"none","","Are `all` vector lanes `false`?",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m16x4",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m16x4",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m16x4",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m16x4",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m16x4",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m16x4",6]]],[11,"select","","Selects elements of `a` and `b` using mask.",6,[[["simd",3]],["simd",3]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["lexicographicallyordered",3],["m16x4",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["lexicographicallyordered",3],["m16x4",6]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",6,[[["i32x2",6]],["i32x2",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",6,[[["i32x2",6]],["i32x2",6]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",6,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",6,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",6,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",6,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",6,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",6,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",6,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",6,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",6,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m32x2",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m32x2",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m32x2",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m32x2",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m32x2",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m32x2",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["i32x2",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["i32x2",6],["lexicographicallyordered",3]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",6,[[["u32x2",6]],["u32x2",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",6,[[["u32x2",6]],["u32x2",6]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",6,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",6,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",6,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",6,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",6,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",6,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",6,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",6,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",6,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m32x2",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m32x2",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m32x2",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m32x2",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m32x2",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m32x2",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["lexicographicallyordered",3],["u32x2",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["lexicographicallyordered",3],["u32x2",6]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"all","","Are `all` vector lanes `true`?",6,[[]]],[11,"any","","Is `any` vector lane `true`?",6,[[]]],[11,"none","","Are `all` vector lanes `false`?",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m32x2",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m32x2",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m32x2",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m32x2",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m32x2",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m32x2",6]]],[11,"select","","Selects elements of `a` and `b` using mask.",6,[[["simd",3]],["simd",3]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["lexicographicallyordered",3],["m32x2",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["lexicographicallyordered",3],["m32x2",6]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"sum","","Horizontal sum of the vector elements.",6,[[]]],[11,"product","","Horizontal product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[18,"EPSILON","","Machine epsilon value.",6,null],[18,"MIN","","Smallest finite value.",6,null],[18,"MIN_POSITIVE","","Smallest positive normal value.",6,null],[18,"MAX","","Largest finite value.",6,null],[18,"NAN","","Not a Number (NaN).",6,null],[18,"INFINITY","","Infinity (∞).",6,null],[18,"NEG_INFINITY","","Negative infinity (-∞).",6,null],[18,"PI","","Archimedes\' constant (π)",6,null],[18,"FRAC_PI_2","","π/2",6,null],[18,"FRAC_PI_3","","π/3",6,null],[18,"FRAC_PI_4","","π/4",6,null],[18,"FRAC_PI_6","","π/6",6,null],[18,"FRAC_PI_8","","π/8",6,null],[18,"FRAC_1_PI","","1/π",6,null],[18,"FRAC_2_PI","","2/π",6,null],[18,"FRAC_2_SQRT_PI","","2/sqrt(π)",6,null],[18,"SQRT_2","","sqrt(2)",6,null],[18,"FRAC_1_SQRT_2","","1/sqrt(2)",6,null],[18,"E","","Euler\'s number (e)",6,null],[18,"LOG2_E","","log2(e)",6,null],[18,"LOG10_E","","log10(e)",6,null],[18,"LN_2","","ln(2)",6,null],[18,"LN_10","","ln(10)",6,null],[11,"is_nan","","",6,[[],["m32x2",6]]],[11,"is_infinite","","",6,[[],["m32x2",6]]],[11,"is_finite","","",6,[[],["m32x2",6]]],[11,"abs","","Absolute value.",6,[[]]],[11,"cos","","Cosine.",6,[[]]],[11,"cos_pi","","Cosine of `self * PI`.",6,[[]]],[11,"exp","","Returns the exponential function of `self`: `e^(self)`.",6,[[]]],[11,"ln","","Returns the natural logarithm of `self`.",6,[[]]],[11,"mul_add","","Fused multiply add: `self * y + z`",6,[[]]],[11,"mul_adde","","Fused multiply add estimate: ~= `self * y + z`",6,[[]]],[11,"powf","","Raises `self` number to the floating point power of `x`.",6,[[]]],[11,"recpre","","Reciprocal estimate: `~= 1. / self`.",6,[[]]],[11,"rsqrte","","Reciprocal square-root estimate: `~= 1. / self.sqrt()`.",6,[[]]],[11,"sin","","Sine.",6,[[]]],[11,"sin_pi","","Sine of `self * PI`.",6,[[]]],[11,"sin_cos_pi","","Sine and cosine of `self * PI`.",6,[[]]],[11,"sqrt","","",6,[[]]],[11,"sqrte","","Square-root estimate.",6,[[]]],[11,"tanh","","Tanh.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m32x2",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m32x2",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m32x2",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m32x2",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m32x2",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m32x2",6]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",6,[[["i8x16",6]],["i8x16",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",6,[[["i8x16",6]],["i8x16",6]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",6,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",6,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",6,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",6,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",6,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",6,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",6,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",6,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",6,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m8x16",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m8x16",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m8x16",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m8x16",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m8x16",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m8x16",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["i8x16",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["i8x16",6],["lexicographicallyordered",3]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",6,[[["u8x16",6]],["u8x16",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",6,[[["u8x16",6]],["u8x16",6]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",6,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",6,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",6,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",6,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",6,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",6,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",6,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",6,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",6,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m8x16",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m8x16",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m8x16",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m8x16",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m8x16",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m8x16",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["lexicographicallyordered",3],["u8x16",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["lexicographicallyordered",3],["u8x16",6]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"all","","Are `all` vector lanes `true`?",6,[[]]],[11,"any","","Is `any` vector lane `true`?",6,[[]]],[11,"none","","Are `all` vector lanes `false`?",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m8x16",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m8x16",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m8x16",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m8x16",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m8x16",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m8x16",6]]],[11,"select","","Selects elements of `a` and `b` using mask.",6,[[["simd",3]],["simd",3]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["lexicographicallyordered",3],["m8x16",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["lexicographicallyordered",3],["m8x16",6]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",6,[[["i16x8",6]],["i16x8",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",6,[[["i16x8",6]],["i16x8",6]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",6,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",6,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",6,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",6,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",6,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",6,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",6,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",6,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",6,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m16x8",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m16x8",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m16x8",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m16x8",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m16x8",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m16x8",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["lexicographicallyordered",3],["i16x8",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["lexicographicallyordered",3],["i16x8",6]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",6,[[["u16x8",6]],["u16x8",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",6,[[["u16x8",6]],["u16x8",6]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",6,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",6,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",6,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",6,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",6,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",6,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",6,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",6,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",6,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m16x8",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m16x8",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m16x8",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m16x8",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m16x8",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m16x8",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["lexicographicallyordered",3],["u16x8",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["lexicographicallyordered",3],["u16x8",6]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"all","","Are `all` vector lanes `true`?",6,[[]]],[11,"any","","Is `any` vector lane `true`?",6,[[]]],[11,"none","","Are `all` vector lanes `false`?",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m16x8",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m16x8",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m16x8",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m16x8",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m16x8",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m16x8",6]]],[11,"select","","Selects elements of `a` and `b` using mask.",6,[[["simd",3]],["simd",3]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["m16x8",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["m16x8",6],["lexicographicallyordered",3]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",6,[[["i32x4",6]],["i32x4",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",6,[[["i32x4",6]],["i32x4",6]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",6,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",6,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",6,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",6,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",6,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",6,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",6,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",6,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",6,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m32x4",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m32x4",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m32x4",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m32x4",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m32x4",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m32x4",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["lexicographicallyordered",3],["i32x4",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["lexicographicallyordered",3],["i32x4",6]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",6,[[["u32x4",6]],["u32x4",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",6,[[["u32x4",6]],["u32x4",6]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",6,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",6,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",6,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",6,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",6,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",6,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",6,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",6,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",6,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m32x4",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m32x4",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m32x4",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m32x4",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m32x4",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m32x4",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["u32x4",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["u32x4",6],["lexicographicallyordered",3]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"sum","","Horizontal sum of the vector elements.",6,[[]]],[11,"product","","Horizontal product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[18,"EPSILON","","Machine epsilon value.",6,null],[18,"MIN","","Smallest finite value.",6,null],[18,"MIN_POSITIVE","","Smallest positive normal value.",6,null],[18,"MAX","","Largest finite value.",6,null],[18,"NAN","","Not a Number (NaN).",6,null],[18,"INFINITY","","Infinity (∞).",6,null],[18,"NEG_INFINITY","","Negative infinity (-∞).",6,null],[18,"PI","","Archimedes\' constant (π)",6,null],[18,"FRAC_PI_2","","π/2",6,null],[18,"FRAC_PI_3","","π/3",6,null],[18,"FRAC_PI_4","","π/4",6,null],[18,"FRAC_PI_6","","π/6",6,null],[18,"FRAC_PI_8","","π/8",6,null],[18,"FRAC_1_PI","","1/π",6,null],[18,"FRAC_2_PI","","2/π",6,null],[18,"FRAC_2_SQRT_PI","","2/sqrt(π)",6,null],[18,"SQRT_2","","sqrt(2)",6,null],[18,"FRAC_1_SQRT_2","","1/sqrt(2)",6,null],[18,"E","","Euler\'s number (e)",6,null],[18,"LOG2_E","","log2(e)",6,null],[18,"LOG10_E","","log10(e)",6,null],[18,"LN_2","","ln(2)",6,null],[18,"LN_10","","ln(10)",6,null],[11,"is_nan","","",6,[[],["m32x4",6]]],[11,"is_infinite","","",6,[[],["m32x4",6]]],[11,"is_finite","","",6,[[],["m32x4",6]]],[11,"abs","","Absolute value.",6,[[]]],[11,"cos","","Cosine.",6,[[]]],[11,"cos_pi","","Cosine of `self * PI`.",6,[[]]],[11,"exp","","Returns the exponential function of `self`: `e^(self)`.",6,[[]]],[11,"ln","","Returns the natural logarithm of `self`.",6,[[]]],[11,"mul_add","","Fused multiply add: `self * y + z`",6,[[]]],[11,"mul_adde","","Fused multiply add estimate: ~= `self * y + z`",6,[[]]],[11,"powf","","Raises `self` number to the floating point power of `x`.",6,[[]]],[11,"recpre","","Reciprocal estimate: `~= 1. / self`.",6,[[]]],[11,"rsqrte","","Reciprocal square-root estimate: `~= 1. / self.sqrt()`.",6,[[]]],[11,"sin","","Sine.",6,[[]]],[11,"sin_pi","","Sine of `self * PI`.",6,[[]]],[11,"sin_cos_pi","","Sine and cosine of `self * PI`.",6,[[]]],[11,"sqrt","","",6,[[]]],[11,"sqrte","","Square-root estimate.",6,[[]]],[11,"tanh","","Tanh.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m32x4",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m32x4",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m32x4",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m32x4",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m32x4",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m32x4",6]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"all","","Are `all` vector lanes `true`?",6,[[]]],[11,"any","","Is `any` vector lane `true`?",6,[[]]],[11,"none","","Are `all` vector lanes `false`?",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m32x4",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m32x4",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m32x4",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m32x4",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m32x4",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m32x4",6]]],[11,"select","","Selects elements of `a` and `b` using mask.",6,[[["simd",3]],["simd",3]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["lexicographicallyordered",3],["m32x4",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["lexicographicallyordered",3],["m32x4",6]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",6,[[["i64x2",6]],["i64x2",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",6,[[["i64x2",6]],["i64x2",6]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",6,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",6,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",6,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",6,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",6,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",6,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",6,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",6,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",6,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m64x2",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m64x2",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m64x2",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m64x2",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m64x2",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m64x2",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["lexicographicallyordered",3],["i64x2",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["lexicographicallyordered",3],["i64x2",6]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",6,[[["u64x2",6]],["u64x2",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",6,[[["u64x2",6]],["u64x2",6]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",6,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",6,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",6,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",6,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",6,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",6,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",6,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",6,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",6,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m64x2",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m64x2",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m64x2",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m64x2",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m64x2",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m64x2",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["lexicographicallyordered",3],["u64x2",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["lexicographicallyordered",3],["u64x2",6]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"sum","","Horizontal sum of the vector elements.",6,[[]]],[11,"product","","Horizontal product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[18,"EPSILON","","Machine epsilon value.",6,null],[18,"MIN","","Smallest finite value.",6,null],[18,"MIN_POSITIVE","","Smallest positive normal value.",6,null],[18,"MAX","","Largest finite value.",6,null],[18,"NAN","","Not a Number (NaN).",6,null],[18,"INFINITY","","Infinity (∞).",6,null],[18,"NEG_INFINITY","","Negative infinity (-∞).",6,null],[18,"PI","","Archimedes\' constant (π)",6,null],[18,"FRAC_PI_2","","π/2",6,null],[18,"FRAC_PI_3","","π/3",6,null],[18,"FRAC_PI_4","","π/4",6,null],[18,"FRAC_PI_6","","π/6",6,null],[18,"FRAC_PI_8","","π/8",6,null],[18,"FRAC_1_PI","","1/π",6,null],[18,"FRAC_2_PI","","2/π",6,null],[18,"FRAC_2_SQRT_PI","","2/sqrt(π)",6,null],[18,"SQRT_2","","sqrt(2)",6,null],[18,"FRAC_1_SQRT_2","","1/sqrt(2)",6,null],[18,"E","","Euler\'s number (e)",6,null],[18,"LOG2_E","","log2(e)",6,null],[18,"LOG10_E","","log10(e)",6,null],[18,"LN_2","","ln(2)",6,null],[18,"LN_10","","ln(10)",6,null],[11,"is_nan","","",6,[[],["m64x2",6]]],[11,"is_infinite","","",6,[[],["m64x2",6]]],[11,"is_finite","","",6,[[],["m64x2",6]]],[11,"abs","","Absolute value.",6,[[]]],[11,"cos","","Cosine.",6,[[]]],[11,"cos_pi","","Cosine of `self * PI`.",6,[[]]],[11,"exp","","Returns the exponential function of `self`: `e^(self)`.",6,[[]]],[11,"ln","","Returns the natural logarithm of `self`.",6,[[]]],[11,"mul_add","","Fused multiply add: `self * y + z`",6,[[]]],[11,"mul_adde","","Fused multiply add estimate: ~= `self * y + z`",6,[[]]],[11,"powf","","Raises `self` number to the floating point power of `x`.",6,[[]]],[11,"recpre","","Reciprocal estimate: `~= 1. / self`.",6,[[]]],[11,"rsqrte","","Reciprocal square-root estimate: `~= 1. / self.sqrt()`.",6,[[]]],[11,"sin","","Sine.",6,[[]]],[11,"sin_pi","","Sine of `self * PI`.",6,[[]]],[11,"sin_cos_pi","","Sine and cosine of `self * PI`.",6,[[]]],[11,"sqrt","","",6,[[]]],[11,"sqrte","","Square-root estimate.",6,[[]]],[11,"tanh","","Tanh.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m64x2",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m64x2",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m64x2",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m64x2",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m64x2",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m64x2",6]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"all","","Are `all` vector lanes `true`?",6,[[]]],[11,"any","","Is `any` vector lane `true`?",6,[[]]],[11,"none","","Are `all` vector lanes `false`?",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m64x2",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m64x2",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m64x2",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m64x2",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m64x2",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m64x2",6]]],[11,"select","","Selects elements of `a` and `b` using mask.",6,[[["simd",3]],["simd",3]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["lexicographicallyordered",3],["m64x2",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["lexicographicallyordered",3],["m64x2",6]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",6,[[["i128x1",6]],["i128x1",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",6,[[["i128x1",6]],["i128x1",6]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",6,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",6,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",6,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",6,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",6,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",6,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",6,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",6,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",6,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m128x1",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m128x1",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m128x1",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m128x1",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m128x1",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m128x1",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["i128x1",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["i128x1",6],["lexicographicallyordered",3]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",6,[[["u128x1",6]],["u128x1",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",6,[[["u128x1",6]],["u128x1",6]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",6,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",6,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",6,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",6,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",6,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",6,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",6,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",6,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",6,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m128x1",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m128x1",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m128x1",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m128x1",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m128x1",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m128x1",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["lexicographicallyordered",3],["u128x1",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["lexicographicallyordered",3],["u128x1",6]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"all","","Are `all` vector lanes `true`?",6,[[]]],[11,"any","","Is `any` vector lane `true`?",6,[[]]],[11,"none","","Are `all` vector lanes `false`?",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m128x1",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m128x1",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m128x1",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m128x1",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m128x1",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m128x1",6]]],[11,"select","","Selects elements of `a` and `b` using mask.",6,[[["simd",3]],["simd",3]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["lexicographicallyordered",3],["m128x1",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["lexicographicallyordered",3],["m128x1",6]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",6,[[["i8x32",6]],["i8x32",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",6,[[["i8x32",6]],["i8x32",6]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",6,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",6,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",6,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",6,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",6,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",6,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",6,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",6,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",6,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m8x32",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m8x32",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m8x32",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m8x32",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m8x32",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m8x32",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["lexicographicallyordered",3],["i8x32",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["lexicographicallyordered",3],["i8x32",6]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",6,[[["u8x32",6]],["u8x32",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",6,[[["u8x32",6]],["u8x32",6]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",6,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",6,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",6,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",6,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",6,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",6,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",6,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",6,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",6,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m8x32",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m8x32",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m8x32",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m8x32",6]]],[11,"gt","","Lane-wise greater-than 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elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"all","","Are `all` vector lanes `true`?",6,[[]]],[11,"any","","Is `any` vector lane `true`?",6,[[]]],[11,"none","","Are `all` vector lanes `false`?",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m8x32",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m8x32",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m8x32",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m8x32",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m8x32",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m8x32",6]]],[11,"select","","Selects elements of `a` and `b` using mask.",6,[[["simd",3]],["simd",3]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["lexicographicallyordered",3],["m8x32",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["lexicographicallyordered",3],["m8x32",6]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",6,[[["i16x16",6]],["i16x16",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",6,[[["i16x16",6]],["i16x16",6]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",6,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new 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representation…",6,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",6,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m16x16",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m16x16",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m16x16",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m16x16",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m16x16",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m16x16",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["lexicographicallyordered",3],["i16x16",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["lexicographicallyordered",3],["i16x16",6]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",6,[[["u16x16",6]],["u16x16",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",6,[[["u16x16",6]],["u16x16",6]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",6,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",6,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",6,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",6,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",6,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",6,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",6,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",6,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",6,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m16x16",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m16x16",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m16x16",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m16x16",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m16x16",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m16x16",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["lexicographicallyordered",3],["u16x16",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["lexicographicallyordered",3],["u16x16",6]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"all","","Are `all` vector lanes `true`?",6,[[]]],[11,"any","","Is `any` vector lane `true`?",6,[[]]],[11,"none","","Are `all` vector lanes `false`?",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m16x16",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m16x16",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m16x16",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m16x16",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m16x16",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m16x16",6]]],[11,"select","","Selects elements of `a` and `b` using mask.",6,[[["simd",3]],["simd",3]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["lexicographicallyordered",3],["m16x16",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["lexicographicallyordered",3],["m16x16",6]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",6,[[["i32x8",6]],["i32x8",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",6,[[["i32x8",6]],["i32x8",6]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",6,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector 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big endian from the target\'s endianness.",6,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",6,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",6,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",6,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",6,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",6,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m32x8",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m32x8",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m32x8",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m32x8",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m32x8",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m32x8",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["lexicographicallyordered",3],["i32x8",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["lexicographicallyordered",3],["i32x8",6]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",6,[[["u32x8",6]],["u32x8",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",6,[[["u32x8",6]],["u32x8",6]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",6,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",6,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",6,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",6,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",6,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",6,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",6,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",6,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",6,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m32x8",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m32x8",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m32x8",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m32x8",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m32x8",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m32x8",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["u32x8",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["u32x8",6],["lexicographicallyordered",3]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"sum","","Horizontal sum of the vector elements.",6,[[]]],[11,"product","","Horizontal product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[18,"EPSILON","","Machine epsilon value.",6,null],[18,"MIN","","Smallest finite value.",6,null],[18,"MIN_POSITIVE","","Smallest positive normal value.",6,null],[18,"MAX","","Largest finite value.",6,null],[18,"NAN","","Not a Number (NaN).",6,null],[18,"INFINITY","","Infinity (∞).",6,null],[18,"NEG_INFINITY","","Negative infinity (-∞).",6,null],[18,"PI","","Archimedes\' constant (π)",6,null],[18,"FRAC_PI_2","","π/2",6,null],[18,"FRAC_PI_3","","π/3",6,null],[18,"FRAC_PI_4","","π/4",6,null],[18,"FRAC_PI_6","","π/6",6,null],[18,"FRAC_PI_8","","π/8",6,null],[18,"FRAC_1_PI","","1/π",6,null],[18,"FRAC_2_PI","","2/π",6,null],[18,"FRAC_2_SQRT_PI","","2/sqrt(π)",6,null],[18,"SQRT_2","","sqrt(2)",6,null],[18,"FRAC_1_SQRT_2","","1/sqrt(2)",6,null],[18,"E","","Euler\'s number (e)",6,null],[18,"LOG2_E","","log2(e)",6,null],[18,"LOG10_E","","log10(e)",6,null],[18,"LN_2","","ln(2)",6,null],[18,"LN_10","","ln(10)",6,null],[11,"is_nan","","",6,[[],["m32x8",6]]],[11,"is_infinite","","",6,[[],["m32x8",6]]],[11,"is_finite","","",6,[[],["m32x8",6]]],[11,"abs","","Absolute value.",6,[[]]],[11,"cos","","Cosine.",6,[[]]],[11,"cos_pi","","Cosine of `self * PI`.",6,[[]]],[11,"exp","","Returns the exponential function of `self`: `e^(self)`.",6,[[]]],[11,"ln","","Returns the natural logarithm of `self`.",6,[[]]],[11,"mul_add","","Fused multiply add: `self * y + z`",6,[[]]],[11,"mul_adde","","Fused multiply add estimate: ~= `self * y + z`",6,[[]]],[11,"powf","","Raises `self` number to the floating point power of `x`.",6,[[]]],[11,"recpre","","Reciprocal estimate: `~= 1. / self`.",6,[[]]],[11,"rsqrte","","Reciprocal square-root estimate: `~= 1. / self.sqrt()`.",6,[[]]],[11,"sin","","Sine.",6,[[]]],[11,"sin_pi","","Sine of `self * PI`.",6,[[]]],[11,"sin_cos_pi","","Sine and cosine of `self * PI`.",6,[[]]],[11,"sqrt","","",6,[[]]],[11,"sqrte","","Square-root estimate.",6,[[]]],[11,"tanh","","Tanh.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m32x8",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m32x8",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m32x8",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m32x8",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m32x8",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m32x8",6]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"all","","Are `all` vector lanes `true`?",6,[[]]],[11,"any","","Is `any` vector lane `true`?",6,[[]]],[11,"none","","Are `all` vector lanes `false`?",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m32x8",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m32x8",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m32x8",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m32x8",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m32x8",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m32x8",6]]],[11,"select","","Selects elements of `a` and `b` using mask.",6,[[["simd",3]],["simd",3]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["lexicographicallyordered",3],["m32x8",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["lexicographicallyordered",3],["m32x8",6]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",6,[[["i64x4",6]],["i64x4",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",6,[[["i64x4",6]],["i64x4",6]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",6,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",6,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",6,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",6,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",6,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",6,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",6,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",6,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",6,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m64x4",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m64x4",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m64x4",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m64x4",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m64x4",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m64x4",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["lexicographicallyordered",3],["i64x4",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["lexicographicallyordered",3],["i64x4",6]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",6,[[["u64x4",6]],["u64x4",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",6,[[["u64x4",6]],["u64x4",6]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",6,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",6,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",6,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",6,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",6,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",6,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",6,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",6,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",6,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m64x4",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m64x4",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m64x4",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m64x4",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m64x4",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m64x4",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["lexicographicallyordered",3],["u64x4",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["lexicographicallyordered",3],["u64x4",6]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"sum","","Horizontal sum of the vector elements.",6,[[]]],[11,"product","","Horizontal product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[18,"EPSILON","","Machine epsilon value.",6,null],[18,"MIN","","Smallest finite value.",6,null],[18,"MIN_POSITIVE","","Smallest positive normal value.",6,null],[18,"MAX","","Largest finite value.",6,null],[18,"NAN","","Not a Number (NaN).",6,null],[18,"INFINITY","","Infinity (∞).",6,null],[18,"NEG_INFINITY","","Negative infinity (-∞).",6,null],[18,"PI","","Archimedes\' constant (π)",6,null],[18,"FRAC_PI_2","","π/2",6,null],[18,"FRAC_PI_3","","π/3",6,null],[18,"FRAC_PI_4","","π/4",6,null],[18,"FRAC_PI_6","","π/6",6,null],[18,"FRAC_PI_8","","π/8",6,null],[18,"FRAC_1_PI","","1/π",6,null],[18,"FRAC_2_PI","","2/π",6,null],[18,"FRAC_2_SQRT_PI","","2/sqrt(π)",6,null],[18,"SQRT_2","","sqrt(2)",6,null],[18,"FRAC_1_SQRT_2","","1/sqrt(2)",6,null],[18,"E","","Euler\'s number (e)",6,null],[18,"LOG2_E","","log2(e)",6,null],[18,"LOG10_E","","log10(e)",6,null],[18,"LN_2","","ln(2)",6,null],[18,"LN_10","","ln(10)",6,null],[11,"is_nan","","",6,[[],["m64x4",6]]],[11,"is_infinite","","",6,[[],["m64x4",6]]],[11,"is_finite","","",6,[[],["m64x4",6]]],[11,"abs","","Absolute value.",6,[[]]],[11,"cos","","Cosine.",6,[[]]],[11,"cos_pi","","Cosine of `self * PI`.",6,[[]]],[11,"exp","","Returns the exponential function of `self`: `e^(self)`.",6,[[]]],[11,"ln","","Returns the natural logarithm of `self`.",6,[[]]],[11,"mul_add","","Fused multiply add: `self * y + z`",6,[[]]],[11,"mul_adde","","Fused multiply add estimate: ~= `self * y + z`",6,[[]]],[11,"powf","","Raises `self` number to the floating point power of `x`.",6,[[]]],[11,"recpre","","Reciprocal estimate: `~= 1. / self`.",6,[[]]],[11,"rsqrte","","Reciprocal square-root estimate: `~= 1. / self.sqrt()`.",6,[[]]],[11,"sin","","Sine.",6,[[]]],[11,"sin_pi","","Sine of `self * PI`.",6,[[]]],[11,"sin_cos_pi","","Sine and cosine of `self * PI`.",6,[[]]],[11,"sqrt","","",6,[[]]],[11,"sqrte","","Square-root estimate.",6,[[]]],[11,"tanh","","Tanh.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m64x4",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m64x4",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m64x4",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m64x4",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m64x4",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m64x4",6]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"all","","Are `all` vector lanes `true`?",6,[[]]],[11,"any","","Is `any` vector lane `true`?",6,[[]]],[11,"none","","Are `all` vector lanes `false`?",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m64x4",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m64x4",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m64x4",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m64x4",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m64x4",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m64x4",6]]],[11,"select","","Selects elements of `a` and `b` using mask.",6,[[["simd",3]],["simd",3]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["m64x4",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["m64x4",6],["lexicographicallyordered",3]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",6,[[["i128x2",6]],["i128x2",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",6,[[["i128x2",6]],["i128x2",6]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",6,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",6,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",6,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",6,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",6,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",6,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",6,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",6,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",6,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m128x2",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m128x2",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m128x2",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m128x2",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m128x2",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m128x2",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["lexicographicallyordered",3],["i128x2",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["lexicographicallyordered",3],["i128x2",6]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",6,[[["u128x2",6]],["u128x2",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",6,[[["u128x2",6]],["u128x2",6]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",6,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",6,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",6,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",6,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",6,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",6,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",6,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",6,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",6,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m128x2",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m128x2",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m128x2",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m128x2",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m128x2",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m128x2",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["lexicographicallyordered",3],["u128x2",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["lexicographicallyordered",3],["u128x2",6]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"all","","Are `all` vector lanes `true`?",6,[[]]],[11,"any","","Is `any` vector lane `true`?",6,[[]]],[11,"none","","Are `all` vector lanes `false`?",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m128x2",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m128x2",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m128x2",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m128x2",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m128x2",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m128x2",6]]],[11,"select","","Selects elements of `a` and `b` using mask.",6,[[["simd",3]],["simd",3]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["m128x2",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["m128x2",6],["lexicographicallyordered",3]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",6,[[["i8x64",6]],["i8x64",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",6,[[["i8x64",6]],["i8x64",6]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",6,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",6,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",6,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",6,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",6,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",6,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",6,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",6,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",6,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m8x64",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m8x64",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m8x64",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m8x64",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m8x64",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m8x64",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["i8x64",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["i8x64",6],["lexicographicallyordered",3]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",6,[[["u8x64",6]],["u8x64",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",6,[[["u8x64",6]],["u8x64",6]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",6,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",6,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",6,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",6,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",6,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",6,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",6,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",6,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",6,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m8x64",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m8x64",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m8x64",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m8x64",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m8x64",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m8x64",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["u8x64",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["u8x64",6],["lexicographicallyordered",3]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"all","","Are `all` vector lanes `true`?",6,[[]]],[11,"any","","Is `any` vector lane `true`?",6,[[]]],[11,"none","","Are `all` vector lanes `false`?",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m8x64",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m8x64",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m8x64",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m8x64",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m8x64",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m8x64",6]]],[11,"select","","Selects elements of `a` and `b` using mask.",6,[[["simd",3]],["simd",3]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["m8x64",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["m8x64",6],["lexicographicallyordered",3]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",6,[[["i16x32",6]],["i16x32",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",6,[[["i16x32",6]],["i16x32",6]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",6,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"swap_bytes","","Reverses the byte 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comparison.",6,[[],["m16x32",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m16x32",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m16x32",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m16x32",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["i16x32",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["i16x32",6],["lexicographicallyordered",3]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",6,[[["u16x32",6]],["u16x32",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",6,[[["u16x32",6]],["u16x32",6]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",6,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",6,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",6,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",6,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",6,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",6,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",6,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",6,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",6,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m16x32",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m16x32",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m16x32",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m16x32",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m16x32",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m16x32",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["u16x32",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["u16x32",6],["lexicographicallyordered",3]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"all","","Are `all` vector lanes `true`?",6,[[]]],[11,"any","","Is `any` vector lane `true`?",6,[[]]],[11,"none","","Are `all` vector lanes `false`?",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m16x32",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m16x32",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m16x32",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m16x32",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m16x32",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m16x32",6]]],[11,"select","","Selects elements of `a` and `b` using mask.",6,[[["simd",3]],["simd",3]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["m16x32",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["m16x32",6],["lexicographicallyordered",3]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",6,[[["i32x16",6]],["i32x16",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",6,[[["i32x16",6]],["i32x16",6]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",6,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",6,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",6,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",6,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",6,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",6,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",6,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",6,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",6,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m32x16",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m32x16",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m32x16",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m32x16",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m32x16",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m32x16",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["i32x16",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["i32x16",6],["lexicographicallyordered",3]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",6,[[["u32x16",6]],["u32x16",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",6,[[["u32x16",6]],["u32x16",6]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",6,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",6,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",6,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",6,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",6,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",6,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",6,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",6,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",6,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m32x16",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m32x16",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m32x16",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m32x16",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m32x16",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m32x16",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["lexicographicallyordered",3],["u32x16",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["lexicographicallyordered",3],["u32x16",6]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"sum","","Horizontal sum of the vector elements.",6,[[]]],[11,"product","","Horizontal product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[18,"EPSILON","","Machine epsilon value.",6,null],[18,"MIN","","Smallest finite value.",6,null],[18,"MIN_POSITIVE","","Smallest positive normal value.",6,null],[18,"MAX","","Largest finite value.",6,null],[18,"NAN","","Not a Number (NaN).",6,null],[18,"INFINITY","","Infinity (∞).",6,null],[18,"NEG_INFINITY","","Negative infinity (-∞).",6,null],[18,"PI","","Archimedes\' constant (π)",6,null],[18,"FRAC_PI_2","","π/2",6,null],[18,"FRAC_PI_3","","π/3",6,null],[18,"FRAC_PI_4","","π/4",6,null],[18,"FRAC_PI_6","","π/6",6,null],[18,"FRAC_PI_8","","π/8",6,null],[18,"FRAC_1_PI","","1/π",6,null],[18,"FRAC_2_PI","","2/π",6,null],[18,"FRAC_2_SQRT_PI","","2/sqrt(π)",6,null],[18,"SQRT_2","","sqrt(2)",6,null],[18,"FRAC_1_SQRT_2","","1/sqrt(2)",6,null],[18,"E","","Euler\'s number (e)",6,null],[18,"LOG2_E","","log2(e)",6,null],[18,"LOG10_E","","log10(e)",6,null],[18,"LN_2","","ln(2)",6,null],[18,"LN_10","","ln(10)",6,null],[11,"is_nan","","",6,[[],["m32x16",6]]],[11,"is_infinite","","",6,[[],["m32x16",6]]],[11,"is_finite","","",6,[[],["m32x16",6]]],[11,"abs","","Absolute value.",6,[[]]],[11,"cos","","Cosine.",6,[[]]],[11,"cos_pi","","Cosine of `self * PI`.",6,[[]]],[11,"exp","","Returns the exponential function of `self`: `e^(self)`.",6,[[]]],[11,"ln","","Returns the natural logarithm of `self`.",6,[[]]],[11,"mul_add","","Fused multiply add: `self * y + z`",6,[[]]],[11,"mul_adde","","Fused multiply add estimate: ~= `self * y + z`",6,[[]]],[11,"powf","","Raises `self` number to the floating point power of `x`.",6,[[]]],[11,"recpre","","Reciprocal estimate: `~= 1. / self`.",6,[[]]],[11,"rsqrte","","Reciprocal square-root estimate: `~= 1. / self.sqrt()`.",6,[[]]],[11,"sin","","Sine.",6,[[]]],[11,"sin_pi","","Sine of `self * PI`.",6,[[]]],[11,"sin_cos_pi","","Sine and cosine of `self * PI`.",6,[[]]],[11,"sqrt","","",6,[[]]],[11,"sqrte","","Square-root estimate.",6,[[]]],[11,"tanh","","Tanh.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m32x16",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m32x16",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m32x16",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m32x16",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m32x16",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m32x16",6]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"all","","Are `all` vector lanes `true`?",6,[[]]],[11,"any","","Is `any` vector lane `true`?",6,[[]]],[11,"none","","Are `all` vector lanes `false`?",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m32x16",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m32x16",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m32x16",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m32x16",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m32x16",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m32x16",6]]],[11,"select","","Selects elements of `a` and `b` using mask.",6,[[["simd",3]],["simd",3]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["lexicographicallyordered",3],["m32x16",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["lexicographicallyordered",3],["m32x16",6]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",6,[[["i64x8",6]],["i64x8",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",6,[[["i64x8",6]],["i64x8",6]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",6,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",6,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",6,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",6,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",6,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",6,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",6,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",6,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",6,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m64x8",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m64x8",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m64x8",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m64x8",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m64x8",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m64x8",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["i64x8",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["i64x8",6],["lexicographicallyordered",3]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",6,[[["u64x8",6]],["u64x8",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",6,[[["u64x8",6]],["u64x8",6]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",6,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",6,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",6,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",6,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",6,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",6,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",6,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",6,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",6,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m64x8",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m64x8",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m64x8",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m64x8",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m64x8",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m64x8",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["lexicographicallyordered",3],["u64x8",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["lexicographicallyordered",3],["u64x8",6]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"sum","","Horizontal sum of the vector elements.",6,[[]]],[11,"product","","Horizontal product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[18,"EPSILON","","Machine epsilon value.",6,null],[18,"MIN","","Smallest finite value.",6,null],[18,"MIN_POSITIVE","","Smallest positive normal value.",6,null],[18,"MAX","","Largest finite value.",6,null],[18,"NAN","","Not a Number (NaN).",6,null],[18,"INFINITY","","Infinity (∞).",6,null],[18,"NEG_INFINITY","","Negative infinity (-∞).",6,null],[18,"PI","","Archimedes\' constant (π)",6,null],[18,"FRAC_PI_2","","π/2",6,null],[18,"FRAC_PI_3","","π/3",6,null],[18,"FRAC_PI_4","","π/4",6,null],[18,"FRAC_PI_6","","π/6",6,null],[18,"FRAC_PI_8","","π/8",6,null],[18,"FRAC_1_PI","","1/π",6,null],[18,"FRAC_2_PI","","2/π",6,null],[18,"FRAC_2_SQRT_PI","","2/sqrt(π)",6,null],[18,"SQRT_2","","sqrt(2)",6,null],[18,"FRAC_1_SQRT_2","","1/sqrt(2)",6,null],[18,"E","","Euler\'s number (e)",6,null],[18,"LOG2_E","","log2(e)",6,null],[18,"LOG10_E","","log10(e)",6,null],[18,"LN_2","","ln(2)",6,null],[18,"LN_10","","ln(10)",6,null],[11,"is_nan","","",6,[[],["m64x8",6]]],[11,"is_infinite","","",6,[[],["m64x8",6]]],[11,"is_finite","","",6,[[],["m64x8",6]]],[11,"abs","","Absolute value.",6,[[]]],[11,"cos","","Cosine.",6,[[]]],[11,"cos_pi","","Cosine of `self * PI`.",6,[[]]],[11,"exp","","Returns the exponential function of `self`: `e^(self)`.",6,[[]]],[11,"ln","","Returns the natural logarithm of `self`.",6,[[]]],[11,"mul_add","","Fused multiply add: `self * y + z`",6,[[]]],[11,"mul_adde","","Fused multiply add estimate: ~= `self * y + z`",6,[[]]],[11,"powf","","Raises `self` number to the floating point power of `x`.",6,[[]]],[11,"recpre","","Reciprocal estimate: `~= 1. / self`.",6,[[]]],[11,"rsqrte","","Reciprocal square-root estimate: `~= 1. / self.sqrt()`.",6,[[]]],[11,"sin","","Sine.",6,[[]]],[11,"sin_pi","","Sine of `self * PI`.",6,[[]]],[11,"sin_cos_pi","","Sine and cosine of `self * PI`.",6,[[]]],[11,"sqrt","","",6,[[]]],[11,"sqrte","","Square-root estimate.",6,[[]]],[11,"tanh","","Tanh.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m64x8",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m64x8",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m64x8",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m64x8",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m64x8",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m64x8",6]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"all","","Are `all` vector lanes `true`?",6,[[]]],[11,"any","","Is `any` vector lane `true`?",6,[[]]],[11,"none","","Are `all` vector lanes `false`?",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m64x8",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m64x8",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m64x8",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m64x8",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m64x8",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m64x8",6]]],[11,"select","","Selects elements of `a` and `b` using mask.",6,[[["simd",3]],["simd",3]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["m64x8",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["m64x8",6],["lexicographicallyordered",3]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",6,[[["i128x4",6]],["i128x4",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",6,[[["i128x4",6]],["i128x4",6]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",6,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",6,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",6,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",6,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",6,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",6,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",6,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",6,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",6,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m128x4",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m128x4",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m128x4",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m128x4",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m128x4",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m128x4",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["i128x4",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["i128x4",6],["lexicographicallyordered",3]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",6,[[["u128x4",6]],["u128x4",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",6,[[["u128x4",6]],["u128x4",6]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",6,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",6,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",6,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",6,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",6,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",6,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",6,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",6,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",6,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m128x4",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m128x4",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m128x4",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m128x4",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m128x4",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m128x4",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["u128x4",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["u128x4",6],["lexicographicallyordered",3]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"all","","Are `all` vector lanes `true`?",6,[[]]],[11,"any","","Is `any` vector lane `true`?",6,[[]]],[11,"none","","Are `all` vector lanes `false`?",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["m128x4",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["m128x4",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["m128x4",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["m128x4",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["m128x4",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["m128x4",6]]],[11,"select","","Selects elements of `a` and `b` using mask.",6,[[["simd",3]],["simd",3]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["m128x4",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["m128x4",6],["lexicographicallyordered",3]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",6,[[["isizex2",6]],["isizex2",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",6,[[["isizex2",6]],["isizex2",6]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",6,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",6,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",6,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",6,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",6,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",6,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",6,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",6,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",6,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["msizex2",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["msizex2",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["msizex2",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["msizex2",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["msizex2",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["msizex2",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["isizex2",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["isizex2",6],["lexicographicallyordered",3]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",6,[[["usizex2",6]],["usizex2",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",6,[[["usizex2",6]],["usizex2",6]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",6,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",6,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",6,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",6,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",6,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",6,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",6,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",6,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",6,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["msizex2",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["msizex2",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["msizex2",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["msizex2",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["msizex2",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["msizex2",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["usizex2",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["usizex2",6],["lexicographicallyordered",3]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"all","","Are `all` vector lanes `true`?",6,[[]]],[11,"any","","Is `any` vector lane `true`?",6,[[]]],[11,"none","","Are `all` vector lanes `false`?",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["msizex2",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["msizex2",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["msizex2",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["msizex2",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["msizex2",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["msizex2",6]]],[11,"select","","Selects elements of `a` and `b` using mask.",6,[[["simd",3]],["simd",3]]],[11,"partial_lex_ord","","Returns a wrapper that implements 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specified…",6,[[["isizex4",6]],["isizex4",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",6,[[["isizex4",6]],["isizex4",6]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",6,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the 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representation…",6,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",6,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["msizex4",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["msizex4",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["msizex4",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["msizex4",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["msizex4",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["msizex4",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["lexicographicallyordered",3],["usizex4",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["lexicographicallyordered",3],["usizex4",6]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"all","","Are `all` vector lanes `true`?",6,[[]]],[11,"any","","Is `any` vector lane `true`?",6,[[]]],[11,"none","","Are `all` vector lanes `false`?",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["msizex4",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["msizex4",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["msizex4",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["msizex4",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["msizex4",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["msizex4",6]]],[11,"select","","Selects elements of `a` and `b` using mask.",6,[[["simd",3]],["simd",3]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["lexicographicallyordered",3],["msizex4",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["lexicographicallyordered",3],["msizex4",6]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",6,[[["isizex8",6]],["isizex8",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",6,[[["isizex8",6]],["isizex8",6]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",6,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",6,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",6,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",6,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",6,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",6,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",6,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",6,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",6,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["msizex8",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["msizex8",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["msizex8",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["msizex8",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["msizex8",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["msizex8",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["isizex8",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["isizex8",6],["lexicographicallyordered",3]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",6,[[["usizex8",6]],["usizex8",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",6,[[["usizex8",6]],["usizex8",6]]],[11,"min","","Minimum of two vectors.",6,[[]]],[11,"max","","Maximum of two vectors.",6,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",6,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",6,[[]]],[11,"max_element","","Largest vector element value.",6,[[]]],[11,"min_element","","Smallest vector element value.",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector 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from the target\'s endianness.",6,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",6,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",6,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",6,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",6,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",6,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",6,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",6,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["msizex8",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["msizex8",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["msizex8",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["msizex8",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["msizex8",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["msizex8",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["usizex8",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["usizex8",6],["lexicographicallyordered",3]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",6,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",6,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",6,[[]]],[11,"all","","Are `all` vector lanes `true`?",6,[[]]],[11,"any","","Is `any` vector lane `true`?",6,[[]]],[11,"none","","Are `all` vector lanes `false`?",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["msizex8",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["msizex8",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["msizex8",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["msizex8",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["msizex8",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["msizex8",6]]],[11,"select","","Selects elements of `a` and `b` using mask.",6,[[["simd",3]],["simd",3]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",6,[[],[["lexicographicallyordered",3],["msizex8",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",6,[[],[["lexicographicallyordered",3],["msizex8",6]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",6,[[]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"null","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"is_null","","Returns a mask that selects those lanes that contain…",6,[[],["msizex2",6]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["msizex2",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["msizex2",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["msizex2",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["msizex2",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["msizex2",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["msizex2",6]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"offset","","Calculates the offset from a pointer.",6,[[["isizex2",6]]]],[11,"wrapping_offset","","Calculates the offset from a pointer using wrapping…",6,[[["isizex2",6]]]],[11,"offset_from","","Calculates the distance between two pointers.",6,[[],["isizex2",6]]],[11,"wrapping_offset_from","","Calculates the distance between two pointers.",6,[[],["isizex2",6]]],[11,"add","","Calculates the offset from a pointer (convenience for…",6,[[["usizex2",6]]]],[11,"sub","","Calculates the offset from a pointer (convenience for…",6,[[["usizex2",6]]]],[11,"wrapping_add","","Calculates the offset from a pointer using wrapping…",6,[[["usizex2",6]]]],[11,"wrapping_sub","","Calculates the offset from a pointer using wrapping…",6,[[["usizex2",6]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"read","","Reads selected vector elements from memory.",6,[[["simd",3],["simd",3]],["simd",3]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"null","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"is_null","","Returns a mask that selects those lanes that contain…",6,[[],["msizex2",6]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["msizex2",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["msizex2",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["msizex2",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["msizex2",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["msizex2",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["msizex2",6]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"offset","","Calculates the offset from a pointer.",6,[[["isizex2",6]]]],[11,"wrapping_offset","","Calculates the offset from a pointer using wrapping…",6,[[["isizex2",6]]]],[11,"offset_from","","Calculates the distance between two pointers.",6,[[],["isizex2",6]]],[11,"wrapping_offset_from","","Calculates the distance between two pointers.",6,[[],["isizex2",6]]],[11,"add","","Calculates the offset from a pointer (convenience for…",6,[[["usizex2",6]]]],[11,"sub","","Calculates the offset from a pointer (convenience for…",6,[[["usizex2",6]]]],[11,"wrapping_add","","Calculates the offset from a pointer using wrapping…",6,[[["usizex2",6]]]],[11,"wrapping_sub","","Calculates the offset from a pointer using wrapping…",6,[[["usizex2",6]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"read","","Reads selected vector elements from memory.",6,[[["simd",3],["simd",3]],["simd",3]]],[11,"write","","Writes selected vector elements to memory.",6,[[["simd",3],["simd",3]]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"null","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"is_null","","Returns a mask that selects those lanes that contain…",6,[[],["msizex4",6]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["msizex4",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["msizex4",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["msizex4",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["msizex4",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["msizex4",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["msizex4",6]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"offset","","Calculates the offset from a pointer.",6,[[["isizex4",6]]]],[11,"wrapping_offset","","Calculates the offset from a pointer using wrapping…",6,[[["isizex4",6]]]],[11,"offset_from","","Calculates the distance between two pointers.",6,[[],["isizex4",6]]],[11,"wrapping_offset_from","","Calculates the distance between two pointers.",6,[[],["isizex4",6]]],[11,"add","","Calculates the offset from a pointer (convenience for…",6,[[["usizex4",6]]]],[11,"sub","","Calculates the offset from a pointer (convenience for…",6,[[["usizex4",6]]]],[11,"wrapping_add","","Calculates the offset from a pointer using wrapping…",6,[[["usizex4",6]]]],[11,"wrapping_sub","","Calculates the offset from a pointer using wrapping…",6,[[["usizex4",6]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"read","","Reads selected vector elements from memory.",6,[[["simd",3],["simd",3]],["simd",3]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"null","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"is_null","","Returns a mask that selects those lanes that contain…",6,[[],["msizex4",6]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["msizex4",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["msizex4",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["msizex4",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["msizex4",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["msizex4",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["msizex4",6]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"offset","","Calculates the offset from a pointer.",6,[[["isizex4",6]]]],[11,"wrapping_offset","","Calculates the offset from a pointer using wrapping…",6,[[["isizex4",6]]]],[11,"offset_from","","Calculates the distance between two pointers.",6,[[],["isizex4",6]]],[11,"wrapping_offset_from","","Calculates the distance between two pointers.",6,[[],["isizex4",6]]],[11,"add","","Calculates the offset from a pointer (convenience for…",6,[[["usizex4",6]]]],[11,"sub","","Calculates the offset from a pointer (convenience for…",6,[[["usizex4",6]]]],[11,"wrapping_add","","Calculates the offset from a pointer using wrapping…",6,[[["usizex4",6]]]],[11,"wrapping_sub","","Calculates the offset from a pointer using wrapping…",6,[[["usizex4",6]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"read","","Reads selected vector elements from memory.",6,[[["simd",3],["simd",3]],["simd",3]]],[11,"write","","Writes selected vector elements to memory.",6,[[["simd",3],["simd",3]]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"null","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"is_null","","Returns a mask that selects those lanes that contain…",6,[[],["msizex8",6]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["msizex8",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["msizex8",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["msizex8",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["msizex8",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["msizex8",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["msizex8",6]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"offset","","Calculates the offset from a pointer.",6,[[["isizex8",6]]]],[11,"wrapping_offset","","Calculates the offset from a pointer using wrapping…",6,[[["isizex8",6]]]],[11,"offset_from","","Calculates the distance between two pointers.",6,[[],["isizex8",6]]],[11,"wrapping_offset_from","","Calculates the distance between two pointers.",6,[[],["isizex8",6]]],[11,"add","","Calculates the offset from a pointer (convenience for…",6,[[["usizex8",6]]]],[11,"sub","","Calculates the offset from a pointer (convenience for…",6,[[["usizex8",6]]]],[11,"wrapping_add","","Calculates the offset from a pointer using wrapping…",6,[[["usizex8",6]]]],[11,"wrapping_sub","","Calculates the offset from a pointer using wrapping…",6,[[["usizex8",6]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"read","","Reads selected vector elements from memory.",6,[[["simd",3],["simd",3]],["simd",3]]],[11,"new","","Creates a new instance with each vector elements…",6,[[]]],[11,"lanes","","Returns the number of vector lanes.",6,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"null","","Constructs a new instance with each element initialized to…",6,[[]]],[11,"is_null","","Returns a mask that selects those lanes that contain…",6,[[],["msizex8",6]]],[11,"extract","","Extracts the value at `index`.",6,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",6,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",6,[[]]],[11,"eq","","Lane-wise equality comparison.",6,[[],["msizex8",6]]],[11,"ne","","Lane-wise inequality comparison.",6,[[],["msizex8",6]]],[11,"lt","","Lane-wise less-than comparison.",6,[[],["msizex8",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",6,[[],["msizex8",6]]],[11,"gt","","Lane-wise greater-than comparison.",6,[[],["msizex8",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",6,[[],["msizex8",6]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",6,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",6,[[]]],[11,"offset","","Calculates the offset from a pointer.",6,[[["isizex8",6]]]],[11,"wrapping_offset","","Calculates the offset from a pointer using wrapping…",6,[[["isizex8",6]]]],[11,"offset_from","","Calculates the distance between two pointers.",6,[[],["isizex8",6]]],[11,"wrapping_offset_from","","Calculates the distance between two pointers.",6,[[],["isizex8",6]]],[11,"add","","Calculates the offset from a pointer (convenience for…",6,[[["usizex8",6]]]],[11,"sub","","Calculates the offset from a pointer (convenience for…",6,[[["usizex8",6]]]],[11,"wrapping_add","","Calculates the offset from a pointer using wrapping…",6,[[["usizex8",6]]]],[11,"wrapping_sub","","Calculates the offset from a pointer using wrapping…",6,[[["usizex8",6]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",6,[[]]],[11,"read","","Reads selected vector elements from memory.",6,[[["simd",3],["simd",3]],["simd",3]]],[11,"write","","Writes selected vector elements to memory.",6,[[["simd",3],["simd",3]]]],[6,"i8x2","","A 16-bit vector with 2 `i8` lanes.",null,null],[6,"u8x2","","A 16-bit vector with 2 `u8` lanes.",null,null],[6,"m8x2","","A 16-bit vector mask with 2 `m8` lanes.",null,null],[6,"i8x4","","A 32-bit vector with 4 `i8` lanes.",null,null],[6,"u8x4","","A 32-bit vector with 4 `u8` lanes.",null,null],[6,"m8x4","","A 32-bit vector mask with 4 `m8` lanes.",null,null],[6,"i16x2","","A 32-bit vector with 2 `i16` lanes.",null,null],[6,"u16x2","","A 32-bit vector with 2 `u16` lanes.",null,null],[6,"m16x2","","A 32-bit vector mask with 2 `m16` lanes.",null,null],[6,"i8x8","","A 64-bit vector with 8 `i8` lanes.",null,null],[6,"u8x8","","A 64-bit vector with 8 `u8` lanes.",null,null],[6,"m8x8","","A 64-bit vector mask with 8 `m8` lanes.",null,null],[6,"i16x4","","A 64-bit vector with 4 `i16` lanes.",null,null],[6,"u16x4","","A 64-bit vector with 4 `u16` lanes.",null,null],[6,"m16x4","","A 64-bit vector mask with 4 `m16` lanes.",null,null],[6,"i32x2","","A 64-bit vector with 2 `i32` lanes.",null,null],[6,"u32x2","","A 64-bit vector with 2 `u32` lanes.",null,null],[6,"m32x2","","A 64-bit vector mask with 2 `m32` lanes.",null,null],[6,"f32x2","","A 64-bit vector with 2 `f32` lanes.",null,null],[6,"i8x16","","A 128-bit vector with 16 `i8` lanes.",null,null],[6,"u8x16","","A 128-bit vector with 16 `u8` lanes.",null,null],[6,"m8x16","","A 128-bit vector mask with 16 `m8` lanes.",null,null],[6,"i16x8","","A 128-bit vector with 8 `i16` lanes.",null,null],[6,"u16x8","","A 128-bit vector with 8 `u16` lanes.",null,null],[6,"m16x8","","A 128-bit vector mask with 8 `m16` lanes.",null,null],[6,"i32x4","","A 128-bit vector with 4 `i32` lanes.",null,null],[6,"u32x4","","A 128-bit vector with 4 `u32` lanes.",null,null],[6,"f32x4","","A 128-bit vector with 4 `f32` lanes.",null,null],[6,"m32x4","","A 128-bit vector mask with 4 `m32` lanes.",null,null],[6,"i64x2","","A 128-bit vector with 2 `i64` lanes.",null,null],[6,"u64x2","","A 128-bit vector with 2 `u64` lanes.",null,null],[6,"f64x2","","A 128-bit vector with 2 `f64` lanes.",null,null],[6,"m64x2","","A 128-bit vector mask with 2 `m64` lanes.",null,null],[6,"i128x1","","A 128-bit vector with 1 `i128` lane.",null,null],[6,"u128x1","","A 128-bit vector with 1 `u128` lane.",null,null],[6,"m128x1","","A 128-bit vector mask with 1 `m128` lane.",null,null],[6,"i8x32","","A 256-bit vector with 32 `i8` lanes.",null,null],[6,"u8x32","","A 256-bit vector with 32 `u8` lanes.",null,null],[6,"m8x32","","A 256-bit vector mask with 32 `m8` lanes.",null,null],[6,"i16x16","","A 256-bit vector with 16 `i16` lanes.",null,null],[6,"u16x16","","A 256-bit vector with 16 `u16` lanes.",null,null],[6,"m16x16","","A 256-bit vector mask with 16 `m16` lanes.",null,null],[6,"i32x8","","A 256-bit vector with 8 `i32` lanes.",null,null],[6,"u32x8","","A 256-bit vector with 8 `u32` lanes.",null,null],[6,"f32x8","","A 256-bit vector with 8 `f32` lanes.",null,null],[6,"m32x8","","A 256-bit vector mask with 8 `m32` lanes.",null,null],[6,"i64x4","","A 256-bit vector with 4 `i64` lanes.",null,null],[6,"u64x4","","A 256-bit vector with 4 `u64` lanes.",null,null],[6,"f64x4","","A 256-bit vector with 4 `f64` lanes.",null,null],[6,"m64x4","","A 256-bit vector mask with 4 `m64` lanes.",null,null],[6,"i128x2","","A 256-bit vector with 2 `i128` lanes.",null,null],[6,"u128x2","","A 256-bit vector with 2 `u128` lanes.",null,null],[6,"m128x2","","A 256-bit vector mask with 2 `m128` lanes.",null,null],[6,"i8x64","","A 512-bit vector with 64 `i8` lanes.",null,null],[6,"u8x64","","A 512-bit vector with 64 `u8` lanes.",null,null],[6,"m8x64","","A 512-bit vector mask with 64 `m8` lanes.",null,null],[6,"i16x32","","A 512-bit vector with 32 `i16` lanes.",null,null],[6,"u16x32","","A 512-bit vector with 32 `u16` lanes.",null,null],[6,"m16x32","","A 512-bit vector mask with 32 `m16` lanes.",null,null],[6,"i32x16","","A 512-bit vector with 16 `i32` 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`PartialOrd`.",19,[[],[["u8x4",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",19,[[],[["u8x4",6],["lexicographicallyordered",3]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",19,[[]]],[11,"new","","Creates a new instance with each vector elements…",20,[[]]],[11,"lanes","","Returns the number of vector lanes.",20,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",20,[[]]],[11,"extract","","Extracts the value at `index`.",20,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",20,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",20,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",20,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",20,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",20,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector 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`indices`.",20,[[]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",20,[[]]],[11,"new","","Creates a new instance with each vector elements…",21,[[]]],[11,"lanes","","Returns the number of vector lanes.",21,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",21,[[]]],[11,"extract","","Extracts the value at `index`.",21,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",21,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",21,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",21,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",21,[[["i16x2",6]],["i16x2",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",21,[[["i16x2",6]],["i16x2",6]]],[11,"min","","Minimum of two vectors.",21,[[]]],[11,"max","","Maximum of two vectors.",21,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",21,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",21,[[]]],[11,"max_element","","Largest vector element value.",21,[[]]],[11,"min_element","","Smallest vector element value.",21,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",21,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",21,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",21,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",21,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",21,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",21,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",21,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",21,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",21,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",21,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",21,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",21,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",21,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",21,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",21,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",21,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",21,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",21,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",21,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",21,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",21,[[]]],[11,"eq","","Lane-wise equality comparison.",21,[[],["m16x2",6]]],[11,"ne","","Lane-wise inequality comparison.",21,[[],["m16x2",6]]],[11,"lt","","Lane-wise less-than comparison.",21,[[],["m16x2",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",21,[[],["m16x2",6]]],[11,"gt","","Lane-wise greater-than comparison.",21,[[],["m16x2",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",21,[[],["m16x2",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",21,[[],[["lexicographicallyordered",3],["i16x2",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",21,[[],[["lexicographicallyordered",3],["i16x2",6]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",21,[[]]],[11,"new","","Creates a new instance with each vector elements…",22,[[]]],[11,"lanes","","Returns the number of vector lanes.",22,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",22,[[]]],[11,"extract","","Extracts the value at `index`.",22,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",22,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",22,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",22,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",22,[[["u16x2",6]],["u16x2",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",22,[[["u16x2",6]],["u16x2",6]]],[11,"min","","Minimum of two vectors.",22,[[]]],[11,"max","","Maximum of two vectors.",22,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",22,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",22,[[]]],[11,"max_element","","Largest vector element value.",22,[[]]],[11,"min_element","","Smallest vector element value.",22,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",22,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",22,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",22,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",22,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",22,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",22,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",22,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",22,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",22,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",22,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",22,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",22,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",22,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",22,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",22,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",22,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",22,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",22,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",22,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",22,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",22,[[]]],[11,"eq","","Lane-wise equality comparison.",22,[[],["m16x2",6]]],[11,"ne","","Lane-wise inequality comparison.",22,[[],["m16x2",6]]],[11,"lt","","Lane-wise less-than comparison.",22,[[],["m16x2",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",22,[[],["m16x2",6]]],[11,"gt","","Lane-wise greater-than comparison.",22,[[],["m16x2",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",22,[[],["m16x2",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",22,[[],[["u16x2",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",22,[[],[["u16x2",6],["lexicographicallyordered",3]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",22,[[]]],[11,"new","","Creates a new instance with each vector elements…",23,[[]]],[11,"lanes","","Returns the number of vector lanes.",23,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",23,[[]]],[11,"extract","","Extracts the value at `index`.",23,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",23,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",23,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",23,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",23,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",23,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",23,[[]]],[11,"all","","Are `all` vector lanes `true`?",23,[[]]],[11,"any","","Is `any` vector lane `true`?",23,[[]]],[11,"none","","Are `all` vector lanes `false`?",23,[[]]],[11,"eq","","Lane-wise equality comparison.",23,[[],["m16x2",6]]],[11,"ne","","Lane-wise inequality comparison.",23,[[],["m16x2",6]]],[11,"lt","","Lane-wise less-than comparison.",23,[[],["m16x2",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",23,[[],["m16x2",6]]],[11,"gt","","Lane-wise greater-than comparison.",23,[[],["m16x2",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",23,[[],["m16x2",6]]],[11,"select","","Selects elements of `a` and `b` using mask.",23,[[["simd",3]],["simd",3]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",23,[[],[["lexicographicallyordered",3],["m16x2",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",23,[[],[["lexicographicallyordered",3],["m16x2",6]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",23,[[]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",23,[[]]],[11,"new","","Creates a new instance with each vector elements…",24,[[]]],[11,"lanes","","Returns the number of vector lanes.",24,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",24,[[]]],[11,"extract","","Extracts the value at `index`.",24,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",24,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",24,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",24,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",24,[[["i8x8",6]],["i8x8",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",24,[[["i8x8",6]],["i8x8",6]]],[11,"min","","Minimum of two vectors.",24,[[]]],[11,"max","","Maximum of two vectors.",24,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",24,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",24,[[]]],[11,"max_element","","Largest vector element value.",24,[[]]],[11,"min_element","","Smallest vector element value.",24,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",24,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",24,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",24,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",24,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",24,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",24,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",24,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",24,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",24,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",24,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",24,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",24,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",24,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",24,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",24,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",24,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",24,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",24,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",24,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",24,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",24,[[]]],[11,"eq","","Lane-wise equality comparison.",24,[[],["m8x8",6]]],[11,"ne","","Lane-wise inequality comparison.",24,[[],["m8x8",6]]],[11,"lt","","Lane-wise less-than comparison.",24,[[],["m8x8",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",24,[[],["m8x8",6]]],[11,"gt","","Lane-wise greater-than comparison.",24,[[],["m8x8",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",24,[[],["m8x8",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",24,[[],[["lexicographicallyordered",3],["i8x8",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",24,[[],[["lexicographicallyordered",3],["i8x8",6]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",24,[[]]],[11,"new","","Creates a new instance with each vector elements…",25,[[]]],[11,"lanes","","Returns the number of vector lanes.",25,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",25,[[]]],[11,"extract","","Extracts the value at `index`.",25,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",25,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",25,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",25,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",25,[[["u8x8",6]],["u8x8",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",25,[[["u8x8",6]],["u8x8",6]]],[11,"min","","Minimum of two vectors.",25,[[]]],[11,"max","","Maximum of two vectors.",25,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",25,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",25,[[]]],[11,"max_element","","Largest vector element value.",25,[[]]],[11,"min_element","","Smallest vector element value.",25,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",25,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",25,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",25,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",25,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",25,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",25,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",25,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",25,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",25,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",25,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",25,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",25,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",25,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",25,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",25,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",25,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",25,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",25,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",25,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",25,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",25,[[]]],[11,"eq","","Lane-wise equality comparison.",25,[[],["m8x8",6]]],[11,"ne","","Lane-wise inequality comparison.",25,[[],["m8x8",6]]],[11,"lt","","Lane-wise less-than comparison.",25,[[],["m8x8",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",25,[[],["m8x8",6]]],[11,"gt","","Lane-wise greater-than comparison.",25,[[],["m8x8",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",25,[[],["m8x8",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",25,[[],[["lexicographicallyordered",3],["u8x8",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",25,[[],[["lexicographicallyordered",3],["u8x8",6]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",25,[[]]],[11,"new","","Creates a new instance with each vector elements…",26,[[]]],[11,"lanes","","Returns the number of vector lanes.",26,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",26,[[]]],[11,"extract","","Extracts the value at `index`.",26,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",26,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",26,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",26,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",26,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",26,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",26,[[]]],[11,"all","","Are `all` vector lanes `true`?",26,[[]]],[11,"any","","Is `any` vector lane `true`?",26,[[]]],[11,"none","","Are `all` vector lanes `false`?",26,[[]]],[11,"eq","","Lane-wise equality comparison.",26,[[],["m8x8",6]]],[11,"ne","","Lane-wise inequality comparison.",26,[[],["m8x8",6]]],[11,"lt","","Lane-wise less-than comparison.",26,[[],["m8x8",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",26,[[],["m8x8",6]]],[11,"gt","","Lane-wise greater-than comparison.",26,[[],["m8x8",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",26,[[],["m8x8",6]]],[11,"select","","Selects elements of `a` and `b` using mask.",26,[[["simd",3]],["simd",3]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",26,[[],[["lexicographicallyordered",3],["m8x8",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",26,[[],[["lexicographicallyordered",3],["m8x8",6]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",26,[[]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",26,[[]]],[11,"new","","Creates a new instance with each vector elements…",27,[[]]],[11,"lanes","","Returns the number of vector lanes.",27,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",27,[[]]],[11,"extract","","Extracts the value at `index`.",27,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",27,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",27,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",27,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",27,[[["i16x4",6]],["i16x4",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",27,[[["i16x4",6]],["i16x4",6]]],[11,"min","","Minimum of two vectors.",27,[[]]],[11,"max","","Maximum of two vectors.",27,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",27,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",27,[[]]],[11,"max_element","","Largest vector element value.",27,[[]]],[11,"min_element","","Smallest vector element value.",27,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",27,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",27,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",27,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",27,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",27,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",27,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",27,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",27,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",27,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",27,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",27,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",27,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",27,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",27,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",27,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",27,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",27,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",27,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",27,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",27,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",27,[[]]],[11,"eq","","Lane-wise equality comparison.",27,[[],["m16x4",6]]],[11,"ne","","Lane-wise inequality comparison.",27,[[],["m16x4",6]]],[11,"lt","","Lane-wise less-than comparison.",27,[[],["m16x4",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",27,[[],["m16x4",6]]],[11,"gt","","Lane-wise greater-than comparison.",27,[[],["m16x4",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",27,[[],["m16x4",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",27,[[],[["i16x4",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",27,[[],[["i16x4",6],["lexicographicallyordered",3]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",27,[[]]],[11,"new","","Creates a new instance with each vector elements…",28,[[]]],[11,"lanes","","Returns the number of vector lanes.",28,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",28,[[]]],[11,"extract","","Extracts the value at `index`.",28,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",28,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",28,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",28,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",28,[[["u16x4",6]],["u16x4",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",28,[[["u16x4",6]],["u16x4",6]]],[11,"min","","Minimum of two vectors.",28,[[]]],[11,"max","","Maximum of two vectors.",28,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",28,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",28,[[]]],[11,"max_element","","Largest vector element value.",28,[[]]],[11,"min_element","","Smallest vector element value.",28,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",28,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",28,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",28,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",28,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",28,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",28,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",28,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",28,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",28,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",28,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",28,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",28,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",28,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",28,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",28,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",28,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",28,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",28,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",28,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",28,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",28,[[]]],[11,"eq","","Lane-wise equality comparison.",28,[[],["m16x4",6]]],[11,"ne","","Lane-wise inequality comparison.",28,[[],["m16x4",6]]],[11,"lt","","Lane-wise less-than comparison.",28,[[],["m16x4",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",28,[[],["m16x4",6]]],[11,"gt","","Lane-wise greater-than comparison.",28,[[],["m16x4",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",28,[[],["m16x4",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",28,[[],[["lexicographicallyordered",3],["u16x4",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",28,[[],[["lexicographicallyordered",3],["u16x4",6]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",28,[[]]],[11,"new","","Creates a new instance with each vector elements…",29,[[]]],[11,"lanes","","Returns the number of vector lanes.",29,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",29,[[]]],[11,"extract","","Extracts the value at `index`.",29,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",29,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",29,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",29,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",29,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",29,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",29,[[]]],[11,"all","","Are `all` vector lanes `true`?",29,[[]]],[11,"any","","Is `any` vector lane `true`?",29,[[]]],[11,"none","","Are `all` vector lanes `false`?",29,[[]]],[11,"eq","","Lane-wise equality comparison.",29,[[],["m16x4",6]]],[11,"ne","","Lane-wise inequality comparison.",29,[[],["m16x4",6]]],[11,"lt","","Lane-wise less-than comparison.",29,[[],["m16x4",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",29,[[],["m16x4",6]]],[11,"gt","","Lane-wise greater-than comparison.",29,[[],["m16x4",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",29,[[],["m16x4",6]]],[11,"select","","Selects elements of `a` and `b` using mask.",29,[[["simd",3]],["simd",3]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",29,[[],[["lexicographicallyordered",3],["m16x4",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",29,[[],[["lexicographicallyordered",3],["m16x4",6]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",29,[[]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",29,[[]]],[11,"new","","Creates a new instance with each vector elements…",30,[[]]],[11,"lanes","","Returns the number of vector lanes.",30,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",30,[[]]],[11,"extract","","Extracts the value at `index`.",30,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",30,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",30,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",30,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",30,[[["i32x2",6]],["i32x2",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",30,[[["i32x2",6]],["i32x2",6]]],[11,"min","","Minimum of two vectors.",30,[[]]],[11,"max","","Maximum of two vectors.",30,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",30,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",30,[[]]],[11,"max_element","","Largest vector element value.",30,[[]]],[11,"min_element","","Smallest vector element value.",30,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",30,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",30,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",30,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",30,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",30,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",30,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",30,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",30,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",30,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",30,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",30,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",30,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",30,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",30,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",30,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",30,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",30,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",30,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",30,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",30,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",30,[[]]],[11,"eq","","Lane-wise equality comparison.",30,[[],["m32x2",6]]],[11,"ne","","Lane-wise inequality comparison.",30,[[],["m32x2",6]]],[11,"lt","","Lane-wise less-than comparison.",30,[[],["m32x2",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",30,[[],["m32x2",6]]],[11,"gt","","Lane-wise greater-than comparison.",30,[[],["m32x2",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",30,[[],["m32x2",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",30,[[],[["i32x2",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",30,[[],[["i32x2",6],["lexicographicallyordered",3]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",30,[[]]],[11,"new","","Creates a new instance with each vector elements…",31,[[]]],[11,"lanes","","Returns the number of vector lanes.",31,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",31,[[]]],[11,"extract","","Extracts the value at `index`.",31,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",31,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",31,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",31,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",31,[[["u32x2",6]],["u32x2",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",31,[[["u32x2",6]],["u32x2",6]]],[11,"min","","Minimum of two vectors.",31,[[]]],[11,"max","","Maximum of two vectors.",31,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",31,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",31,[[]]],[11,"max_element","","Largest vector element value.",31,[[]]],[11,"min_element","","Smallest vector element value.",31,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",31,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",31,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",31,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",31,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",31,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",31,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",31,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",31,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",31,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",31,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",31,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",31,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",31,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",31,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",31,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",31,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",31,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",31,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",31,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",31,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",31,[[]]],[11,"eq","","Lane-wise equality comparison.",31,[[],["m32x2",6]]],[11,"ne","","Lane-wise inequality comparison.",31,[[],["m32x2",6]]],[11,"lt","","Lane-wise less-than comparison.",31,[[],["m32x2",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",31,[[],["m32x2",6]]],[11,"gt","","Lane-wise greater-than comparison.",31,[[],["m32x2",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",31,[[],["m32x2",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",31,[[],[["lexicographicallyordered",3],["u32x2",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",31,[[],[["lexicographicallyordered",3],["u32x2",6]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",31,[[]]],[11,"new","","Creates a new instance with each vector elements…",33,[[]]],[11,"lanes","","Returns the number of vector lanes.",33,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",33,[[]]],[11,"extract","","Extracts the value at `index`.",33,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",33,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",33,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",33,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",33,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",33,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",33,[[]]],[11,"all","","Are `all` vector lanes `true`?",33,[[]]],[11,"any","","Is `any` vector lane `true`?",33,[[]]],[11,"none","","Are `all` vector lanes `false`?",33,[[]]],[11,"eq","","Lane-wise equality comparison.",33,[[],["m32x2",6]]],[11,"ne","","Lane-wise inequality comparison.",33,[[],["m32x2",6]]],[11,"lt","","Lane-wise less-than comparison.",33,[[],["m32x2",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",33,[[],["m32x2",6]]],[11,"gt","","Lane-wise greater-than comparison.",33,[[],["m32x2",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",33,[[],["m32x2",6]]],[11,"select","","Selects elements of `a` and `b` using mask.",33,[[["simd",3]],["simd",3]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",33,[[],[["lexicographicallyordered",3],["m32x2",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",33,[[],[["lexicographicallyordered",3],["m32x2",6]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",33,[[]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",33,[[]]],[11,"new","","Creates a new instance with each vector elements…",32,[[]]],[11,"lanes","","Returns the number of vector lanes.",32,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",32,[[]]],[11,"extract","","Extracts the value at `index`.",32,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",32,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",32,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",32,[[]]],[11,"min","","Minimum of two vectors.",32,[[]]],[11,"max","","Maximum of two vectors.",32,[[]]],[11,"sum","","Horizontal sum of the vector elements.",32,[[]]],[11,"product","","Horizontal product of the vector elements.",32,[[]]],[11,"max_element","","Largest vector element value.",32,[[]]],[11,"min_element","","Smallest vector element value.",32,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",32,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",32,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",32,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",32,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",32,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",32,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",32,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",32,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",32,[[]]],[18,"EPSILON","","Machine epsilon value.",32,null],[18,"MIN","","Smallest finite value.",32,null],[18,"MIN_POSITIVE","","Smallest positive normal value.",32,null],[18,"MAX","","Largest finite value.",32,null],[18,"NAN","","Not a Number (NaN).",32,null],[18,"INFINITY","","Infinity (∞).",32,null],[18,"NEG_INFINITY","","Negative infinity (-∞).",32,null],[18,"PI","","Archimedes\' constant (π)",32,null],[18,"FRAC_PI_2","","π/2",32,null],[18,"FRAC_PI_3","","π/3",32,null],[18,"FRAC_PI_4","","π/4",32,null],[18,"FRAC_PI_6","","π/6",32,null],[18,"FRAC_PI_8","","π/8",32,null],[18,"FRAC_1_PI","","1/π",32,null],[18,"FRAC_2_PI","","2/π",32,null],[18,"FRAC_2_SQRT_PI","","2/sqrt(π)",32,null],[18,"SQRT_2","","sqrt(2)",32,null],[18,"FRAC_1_SQRT_2","","1/sqrt(2)",32,null],[18,"E","","Euler\'s number (e)",32,null],[18,"LOG2_E","","log2(e)",32,null],[18,"LOG10_E","","log10(e)",32,null],[18,"LN_2","","ln(2)",32,null],[18,"LN_10","","ln(10)",32,null],[11,"is_nan","","",32,[[],["m32x2",6]]],[11,"is_infinite","","",32,[[],["m32x2",6]]],[11,"is_finite","","",32,[[],["m32x2",6]]],[11,"abs","","Absolute value.",32,[[]]],[11,"cos","","Cosine.",32,[[]]],[11,"cos_pi","","Cosine of `self * PI`.",32,[[]]],[11,"exp","","Returns the exponential function of `self`: `e^(self)`.",32,[[]]],[11,"ln","","Returns the natural logarithm of `self`.",32,[[]]],[11,"mul_add","","Fused multiply add: `self * y + z`",32,[[]]],[11,"mul_adde","","Fused multiply add estimate: ~= `self * y + z`",32,[[]]],[11,"powf","","Raises `self` number to the floating point power of `x`.",32,[[]]],[11,"recpre","","Reciprocal estimate: `~= 1. / self`.",32,[[]]],[11,"rsqrte","","Reciprocal square-root estimate: `~= 1. / self.sqrt()`.",32,[[]]],[11,"sin","","Sine.",32,[[]]],[11,"sin_pi","","Sine of `self * PI`.",32,[[]]],[11,"sin_cos_pi","","Sine and cosine of `self * PI`.",32,[[]]],[11,"sqrt","","",32,[[]]],[11,"sqrte","","Square-root estimate.",32,[[]]],[11,"tanh","","Tanh.",32,[[]]],[11,"eq","","Lane-wise equality comparison.",32,[[],["m32x2",6]]],[11,"ne","","Lane-wise inequality comparison.",32,[[],["m32x2",6]]],[11,"lt","","Lane-wise less-than comparison.",32,[[],["m32x2",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",32,[[],["m32x2",6]]],[11,"gt","","Lane-wise greater-than comparison.",32,[[],["m32x2",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",32,[[],["m32x2",6]]],[11,"new","","Creates a new instance with each vector elements…",34,[[]]],[11,"lanes","","Returns the number of vector lanes.",34,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",34,[[]]],[11,"extract","","Extracts the value at `index`.",34,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",34,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",34,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",34,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",34,[[["i8x16",6]],["i8x16",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",34,[[["i8x16",6]],["i8x16",6]]],[11,"min","","Minimum of two vectors.",34,[[]]],[11,"max","","Maximum of two vectors.",34,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",34,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",34,[[]]],[11,"max_element","","Largest vector element value.",34,[[]]],[11,"min_element","","Smallest vector element value.",34,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",34,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",34,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",34,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",34,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",34,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",34,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",34,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",34,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",34,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",34,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",34,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",34,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",34,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",34,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",34,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",34,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",34,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",34,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",34,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",34,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",34,[[]]],[11,"eq","","Lane-wise equality comparison.",34,[[],["m8x16",6]]],[11,"ne","","Lane-wise inequality comparison.",34,[[],["m8x16",6]]],[11,"lt","","Lane-wise less-than comparison.",34,[[],["m8x16",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",34,[[],["m8x16",6]]],[11,"gt","","Lane-wise greater-than comparison.",34,[[],["m8x16",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",34,[[],["m8x16",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",34,[[],[["i8x16",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",34,[[],[["i8x16",6],["lexicographicallyordered",3]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",34,[[]]],[11,"new","","Creates a new instance with each vector elements…",35,[[]]],[11,"lanes","","Returns the number of vector lanes.",35,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",35,[[]]],[11,"extract","","Extracts the value at `index`.",35,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",35,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",35,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",35,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",35,[[["u8x16",6]],["u8x16",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",35,[[["u8x16",6]],["u8x16",6]]],[11,"min","","Minimum of two vectors.",35,[[]]],[11,"max","","Maximum of two vectors.",35,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",35,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",35,[[]]],[11,"max_element","","Largest vector element value.",35,[[]]],[11,"min_element","","Smallest vector element value.",35,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",35,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",35,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",35,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",35,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",35,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",35,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",35,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",35,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",35,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",35,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",35,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",35,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",35,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",35,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",35,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",35,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",35,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",35,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",35,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",35,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",35,[[]]],[11,"eq","","Lane-wise equality comparison.",35,[[],["m8x16",6]]],[11,"ne","","Lane-wise inequality comparison.",35,[[],["m8x16",6]]],[11,"lt","","Lane-wise less-than comparison.",35,[[],["m8x16",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",35,[[],["m8x16",6]]],[11,"gt","","Lane-wise greater-than comparison.",35,[[],["m8x16",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",35,[[],["m8x16",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",35,[[],[["lexicographicallyordered",3],["u8x16",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",35,[[],[["lexicographicallyordered",3],["u8x16",6]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",35,[[]]],[11,"new","","Creates a new instance with each vector elements…",36,[[]]],[11,"lanes","","Returns the number of vector lanes.",36,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",36,[[]]],[11,"extract","","Extracts the value at `index`.",36,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",36,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",36,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",36,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",36,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",36,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",36,[[]]],[11,"all","","Are `all` vector lanes `true`?",36,[[]]],[11,"any","","Is `any` vector lane `true`?",36,[[]]],[11,"none","","Are `all` vector lanes `false`?",36,[[]]],[11,"eq","","Lane-wise equality comparison.",36,[[],["m8x16",6]]],[11,"ne","","Lane-wise inequality comparison.",36,[[],["m8x16",6]]],[11,"lt","","Lane-wise less-than comparison.",36,[[],["m8x16",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",36,[[],["m8x16",6]]],[11,"gt","","Lane-wise greater-than comparison.",36,[[],["m8x16",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",36,[[],["m8x16",6]]],[11,"select","","Selects elements of `a` and `b` using mask.",36,[[["simd",3]],["simd",3]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",36,[[],[["lexicographicallyordered",3],["m8x16",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",36,[[],[["lexicographicallyordered",3],["m8x16",6]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",36,[[]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",36,[[]]],[11,"new","","Creates a new instance with each vector elements…",37,[[]]],[11,"lanes","","Returns the number of vector lanes.",37,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",37,[[]]],[11,"extract","","Extracts the value at `index`.",37,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",37,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",37,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",37,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",37,[[["i16x8",6]],["i16x8",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",37,[[["i16x8",6]],["i16x8",6]]],[11,"min","","Minimum of two vectors.",37,[[]]],[11,"max","","Maximum of two vectors.",37,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",37,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",37,[[]]],[11,"max_element","","Largest vector element value.",37,[[]]],[11,"min_element","","Smallest vector element value.",37,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",37,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",37,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",37,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",37,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",37,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",37,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",37,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",37,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",37,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",37,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",37,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",37,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",37,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",37,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",37,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",37,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",37,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",37,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",37,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",37,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",37,[[]]],[11,"eq","","Lane-wise equality comparison.",37,[[],["m16x8",6]]],[11,"ne","","Lane-wise inequality comparison.",37,[[],["m16x8",6]]],[11,"lt","","Lane-wise less-than comparison.",37,[[],["m16x8",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",37,[[],["m16x8",6]]],[11,"gt","","Lane-wise greater-than comparison.",37,[[],["m16x8",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",37,[[],["m16x8",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",37,[[],[["lexicographicallyordered",3],["i16x8",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",37,[[],[["lexicographicallyordered",3],["i16x8",6]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",37,[[]]],[11,"new","","Creates a new instance with each vector elements…",38,[[]]],[11,"lanes","","Returns the number of vector lanes.",38,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",38,[[]]],[11,"extract","","Extracts the value at `index`.",38,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",38,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",38,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",38,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",38,[[["u16x8",6]],["u16x8",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",38,[[["u16x8",6]],["u16x8",6]]],[11,"min","","Minimum of two vectors.",38,[[]]],[11,"max","","Maximum of two vectors.",38,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",38,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",38,[[]]],[11,"max_element","","Largest vector element value.",38,[[]]],[11,"min_element","","Smallest vector element value.",38,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",38,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",38,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",38,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",38,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",38,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",38,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",38,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",38,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",38,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",38,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",38,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",38,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",38,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",38,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",38,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",38,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",38,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",38,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",38,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",38,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",38,[[]]],[11,"eq","","Lane-wise equality comparison.",38,[[],["m16x8",6]]],[11,"ne","","Lane-wise inequality comparison.",38,[[],["m16x8",6]]],[11,"lt","","Lane-wise less-than comparison.",38,[[],["m16x8",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",38,[[],["m16x8",6]]],[11,"gt","","Lane-wise greater-than comparison.",38,[[],["m16x8",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",38,[[],["m16x8",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",38,[[],[["lexicographicallyordered",3],["u16x8",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",38,[[],[["lexicographicallyordered",3],["u16x8",6]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",38,[[]]],[11,"new","","Creates a new instance with each vector elements…",39,[[]]],[11,"lanes","","Returns the number of vector lanes.",39,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",39,[[]]],[11,"extract","","Extracts the value at `index`.",39,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",39,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",39,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",39,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",39,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",39,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",39,[[]]],[11,"all","","Are `all` vector lanes `true`?",39,[[]]],[11,"any","","Is `any` vector lane `true`?",39,[[]]],[11,"none","","Are `all` vector lanes `false`?",39,[[]]],[11,"eq","","Lane-wise equality comparison.",39,[[],["m16x8",6]]],[11,"ne","","Lane-wise inequality comparison.",39,[[],["m16x8",6]]],[11,"lt","","Lane-wise less-than comparison.",39,[[],["m16x8",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",39,[[],["m16x8",6]]],[11,"gt","","Lane-wise greater-than comparison.",39,[[],["m16x8",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",39,[[],["m16x8",6]]],[11,"select","","Selects elements of `a` and `b` using mask.",39,[[["simd",3]],["simd",3]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",39,[[],[["m16x8",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",39,[[],[["m16x8",6],["lexicographicallyordered",3]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",39,[[]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",39,[[]]],[11,"new","","Creates a new instance with each vector elements…",40,[[]]],[11,"lanes","","Returns the number of vector lanes.",40,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",40,[[]]],[11,"extract","","Extracts the value at `index`.",40,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",40,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",40,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",40,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",40,[[["i32x4",6]],["i32x4",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",40,[[["i32x4",6]],["i32x4",6]]],[11,"min","","Minimum of two vectors.",40,[[]]],[11,"max","","Maximum of two vectors.",40,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",40,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",40,[[]]],[11,"max_element","","Largest vector element value.",40,[[]]],[11,"min_element","","Smallest vector element value.",40,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",40,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",40,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",40,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",40,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",40,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",40,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",40,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",40,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",40,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",40,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",40,[[]]],[11,"swap_bytes","","Reverses the byte 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comparison.",40,[[],["m32x4",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",40,[[],["m32x4",6]]],[11,"gt","","Lane-wise greater-than comparison.",40,[[],["m32x4",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",40,[[],["m32x4",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",40,[[],[["lexicographicallyordered",3],["i32x4",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",40,[[],[["lexicographicallyordered",3],["i32x4",6]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",40,[[]]],[11,"new","","Creates a new instance with each vector elements…",41,[[]]],[11,"lanes","","Returns the number of vector lanes.",41,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",41,[[]]],[11,"extract","","Extracts the value at `index`.",41,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",41,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",41,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",41,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",41,[[["u32x4",6]],["u32x4",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",41,[[["u32x4",6]],["u32x4",6]]],[11,"min","","Minimum of two vectors.",41,[[]]],[11,"max","","Maximum of two vectors.",41,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",41,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",41,[[]]],[11,"max_element","","Largest vector element value.",41,[[]]],[11,"min_element","","Smallest vector element value.",41,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",41,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",41,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",41,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",41,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",41,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",41,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",41,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",41,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",41,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",41,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",41,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",41,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",41,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",41,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",41,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",41,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",41,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",41,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",41,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",41,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",41,[[]]],[11,"eq","","Lane-wise equality comparison.",41,[[],["m32x4",6]]],[11,"ne","","Lane-wise inequality comparison.",41,[[],["m32x4",6]]],[11,"lt","","Lane-wise less-than comparison.",41,[[],["m32x4",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",41,[[],["m32x4",6]]],[11,"gt","","Lane-wise greater-than comparison.",41,[[],["m32x4",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",41,[[],["m32x4",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",41,[[],[["u32x4",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",41,[[],[["u32x4",6],["lexicographicallyordered",3]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",41,[[]]],[11,"new","","Creates a new instance with each vector elements…",42,[[]]],[11,"lanes","","Returns the number of vector lanes.",42,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",42,[[]]],[11,"extract","","Extracts the value at `index`.",42,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",42,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",42,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",42,[[]]],[11,"min","","Minimum of two vectors.",42,[[]]],[11,"max","","Maximum of two vectors.",42,[[]]],[11,"sum","","Horizontal sum of the vector elements.",42,[[]]],[11,"product","","Horizontal product of the vector elements.",42,[[]]],[11,"max_element","","Largest vector element value.",42,[[]]],[11,"min_element","","Smallest vector element value.",42,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",42,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",42,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",42,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",42,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",42,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",42,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",42,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",42,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",42,[[]]],[18,"EPSILON","","Machine epsilon value.",42,null],[18,"MIN","","Smallest finite value.",42,null],[18,"MIN_POSITIVE","","Smallest positive normal value.",42,null],[18,"MAX","","Largest finite value.",42,null],[18,"NAN","","Not a Number (NaN).",42,null],[18,"INFINITY","","Infinity (∞).",42,null],[18,"NEG_INFINITY","","Negative infinity (-∞).",42,null],[18,"PI","","Archimedes\' constant (π)",42,null],[18,"FRAC_PI_2","","π/2",42,null],[18,"FRAC_PI_3","","π/3",42,null],[18,"FRAC_PI_4","","π/4",42,null],[18,"FRAC_PI_6","","π/6",42,null],[18,"FRAC_PI_8","","π/8",42,null],[18,"FRAC_1_PI","","1/π",42,null],[18,"FRAC_2_PI","","2/π",42,null],[18,"FRAC_2_SQRT_PI","","2/sqrt(π)",42,null],[18,"SQRT_2","","sqrt(2)",42,null],[18,"FRAC_1_SQRT_2","","1/sqrt(2)",42,null],[18,"E","","Euler\'s number (e)",42,null],[18,"LOG2_E","","log2(e)",42,null],[18,"LOG10_E","","log10(e)",42,null],[18,"LN_2","","ln(2)",42,null],[18,"LN_10","","ln(10)",42,null],[11,"is_nan","","",42,[[],["m32x4",6]]],[11,"is_infinite","","",42,[[],["m32x4",6]]],[11,"is_finite","","",42,[[],["m32x4",6]]],[11,"abs","","Absolute value.",42,[[]]],[11,"cos","","Cosine.",42,[[]]],[11,"cos_pi","","Cosine of `self * PI`.",42,[[]]],[11,"exp","","Returns the exponential function of `self`: `e^(self)`.",42,[[]]],[11,"ln","","Returns the natural logarithm of `self`.",42,[[]]],[11,"mul_add","","Fused multiply add: `self * y + z`",42,[[]]],[11,"mul_adde","","Fused multiply add estimate: ~= `self * y + z`",42,[[]]],[11,"powf","","Raises `self` number to the floating point power of `x`.",42,[[]]],[11,"recpre","","Reciprocal estimate: `~= 1. / self`.",42,[[]]],[11,"rsqrte","","Reciprocal square-root estimate: `~= 1. / self.sqrt()`.",42,[[]]],[11,"sin","","Sine.",42,[[]]],[11,"sin_pi","","Sine of `self * PI`.",42,[[]]],[11,"sin_cos_pi","","Sine and cosine of `self * PI`.",42,[[]]],[11,"sqrt","","",42,[[]]],[11,"sqrte","","Square-root estimate.",42,[[]]],[11,"tanh","","Tanh.",42,[[]]],[11,"eq","","Lane-wise equality comparison.",42,[[],["m32x4",6]]],[11,"ne","","Lane-wise inequality comparison.",42,[[],["m32x4",6]]],[11,"lt","","Lane-wise less-than comparison.",42,[[],["m32x4",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",42,[[],["m32x4",6]]],[11,"gt","","Lane-wise greater-than comparison.",42,[[],["m32x4",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",42,[[],["m32x4",6]]],[11,"new","","Creates a new instance with each vector elements…",43,[[]]],[11,"lanes","","Returns the number of vector lanes.",43,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",43,[[]]],[11,"extract","","Extracts the value at `index`.",43,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",43,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",43,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",43,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",43,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",43,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",43,[[]]],[11,"all","","Are `all` vector lanes `true`?",43,[[]]],[11,"any","","Is `any` vector lane `true`?",43,[[]]],[11,"none","","Are `all` vector lanes `false`?",43,[[]]],[11,"eq","","Lane-wise equality comparison.",43,[[],["m32x4",6]]],[11,"ne","","Lane-wise inequality comparison.",43,[[],["m32x4",6]]],[11,"lt","","Lane-wise less-than comparison.",43,[[],["m32x4",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",43,[[],["m32x4",6]]],[11,"gt","","Lane-wise greater-than comparison.",43,[[],["m32x4",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",43,[[],["m32x4",6]]],[11,"select","","Selects elements of `a` and `b` using mask.",43,[[["simd",3]],["simd",3]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",43,[[],[["lexicographicallyordered",3],["m32x4",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",43,[[],[["lexicographicallyordered",3],["m32x4",6]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",43,[[]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",43,[[]]],[11,"new","","Creates a new instance with each vector elements…",44,[[]]],[11,"lanes","","Returns the number of vector lanes.",44,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",44,[[]]],[11,"extract","","Extracts the value at `index`.",44,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",44,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",44,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",44,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",44,[[["i64x2",6]],["i64x2",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",44,[[["i64x2",6]],["i64x2",6]]],[11,"min","","Minimum of two vectors.",44,[[]]],[11,"max","","Maximum of two vectors.",44,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",44,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",44,[[]]],[11,"max_element","","Largest vector element value.",44,[[]]],[11,"min_element","","Smallest vector element value.",44,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",44,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",44,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",44,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",44,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",44,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",44,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",44,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",44,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",44,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",44,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",44,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",44,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",44,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",44,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",44,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",44,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",44,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",44,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",44,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",44,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",44,[[]]],[11,"eq","","Lane-wise equality comparison.",44,[[],["m64x2",6]]],[11,"ne","","Lane-wise inequality comparison.",44,[[],["m64x2",6]]],[11,"lt","","Lane-wise less-than comparison.",44,[[],["m64x2",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",44,[[],["m64x2",6]]],[11,"gt","","Lane-wise greater-than comparison.",44,[[],["m64x2",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",44,[[],["m64x2",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",44,[[],[["lexicographicallyordered",3],["i64x2",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",44,[[],[["lexicographicallyordered",3],["i64x2",6]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",44,[[]]],[11,"new","","Creates a new instance with each vector elements…",45,[[]]],[11,"lanes","","Returns the number of vector lanes.",45,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",45,[[]]],[11,"extract","","Extracts the value at `index`.",45,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",45,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",45,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",45,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",45,[[["u64x2",6]],["u64x2",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",45,[[["u64x2",6]],["u64x2",6]]],[11,"min","","Minimum of two vectors.",45,[[]]],[11,"max","","Maximum of two vectors.",45,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",45,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",45,[[]]],[11,"max_element","","Largest vector element value.",45,[[]]],[11,"min_element","","Smallest vector element value.",45,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",45,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",45,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",45,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",45,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",45,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",45,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",45,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",45,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",45,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",45,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",45,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",45,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",45,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",45,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",45,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",45,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",45,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",45,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",45,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",45,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",45,[[]]],[11,"eq","","Lane-wise equality comparison.",45,[[],["m64x2",6]]],[11,"ne","","Lane-wise inequality comparison.",45,[[],["m64x2",6]]],[11,"lt","","Lane-wise less-than comparison.",45,[[],["m64x2",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",45,[[],["m64x2",6]]],[11,"gt","","Lane-wise greater-than comparison.",45,[[],["m64x2",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",45,[[],["m64x2",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",45,[[],[["lexicographicallyordered",3],["u64x2",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",45,[[],[["lexicographicallyordered",3],["u64x2",6]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",45,[[]]],[11,"new","","Creates a new instance with each vector elements…",46,[[]]],[11,"lanes","","Returns the number of vector lanes.",46,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",46,[[]]],[11,"extract","","Extracts the value at `index`.",46,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",46,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",46,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",46,[[]]],[11,"min","","Minimum of two vectors.",46,[[]]],[11,"max","","Maximum of two vectors.",46,[[]]],[11,"sum","","Horizontal sum of the vector elements.",46,[[]]],[11,"product","","Horizontal product of the vector elements.",46,[[]]],[11,"max_element","","Largest vector element value.",46,[[]]],[11,"min_element","","Smallest vector element value.",46,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",46,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",46,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",46,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",46,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",46,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",46,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",46,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",46,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",46,[[]]],[18,"EPSILON","","Machine epsilon value.",46,null],[18,"MIN","","Smallest finite value.",46,null],[18,"MIN_POSITIVE","","Smallest positive normal value.",46,null],[18,"MAX","","Largest finite value.",46,null],[18,"NAN","","Not a Number (NaN).",46,null],[18,"INFINITY","","Infinity (∞).",46,null],[18,"NEG_INFINITY","","Negative infinity (-∞).",46,null],[18,"PI","","Archimedes\' constant (π)",46,null],[18,"FRAC_PI_2","","π/2",46,null],[18,"FRAC_PI_3","","π/3",46,null],[18,"FRAC_PI_4","","π/4",46,null],[18,"FRAC_PI_6","","π/6",46,null],[18,"FRAC_PI_8","","π/8",46,null],[18,"FRAC_1_PI","","1/π",46,null],[18,"FRAC_2_PI","","2/π",46,null],[18,"FRAC_2_SQRT_PI","","2/sqrt(π)",46,null],[18,"SQRT_2","","sqrt(2)",46,null],[18,"FRAC_1_SQRT_2","","1/sqrt(2)",46,null],[18,"E","","Euler\'s number (e)",46,null],[18,"LOG2_E","","log2(e)",46,null],[18,"LOG10_E","","log10(e)",46,null],[18,"LN_2","","ln(2)",46,null],[18,"LN_10","","ln(10)",46,null],[11,"is_nan","","",46,[[],["m64x2",6]]],[11,"is_infinite","","",46,[[],["m64x2",6]]],[11,"is_finite","","",46,[[],["m64x2",6]]],[11,"abs","","Absolute value.",46,[[]]],[11,"cos","","Cosine.",46,[[]]],[11,"cos_pi","","Cosine of `self * PI`.",46,[[]]],[11,"exp","","Returns the exponential function of `self`: `e^(self)`.",46,[[]]],[11,"ln","","Returns the natural logarithm of `self`.",46,[[]]],[11,"mul_add","","Fused multiply add: `self * y + z`",46,[[]]],[11,"mul_adde","","Fused multiply add estimate: ~= `self * y + z`",46,[[]]],[11,"powf","","Raises `self` number to the floating point power of `x`.",46,[[]]],[11,"recpre","","Reciprocal estimate: `~= 1. / self`.",46,[[]]],[11,"rsqrte","","Reciprocal square-root estimate: `~= 1. / self.sqrt()`.",46,[[]]],[11,"sin","","Sine.",46,[[]]],[11,"sin_pi","","Sine of `self * PI`.",46,[[]]],[11,"sin_cos_pi","","Sine and cosine of `self * PI`.",46,[[]]],[11,"sqrt","","",46,[[]]],[11,"sqrte","","Square-root estimate.",46,[[]]],[11,"tanh","","Tanh.",46,[[]]],[11,"eq","","Lane-wise equality comparison.",46,[[],["m64x2",6]]],[11,"ne","","Lane-wise inequality comparison.",46,[[],["m64x2",6]]],[11,"lt","","Lane-wise less-than comparison.",46,[[],["m64x2",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",46,[[],["m64x2",6]]],[11,"gt","","Lane-wise greater-than comparison.",46,[[],["m64x2",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",46,[[],["m64x2",6]]],[11,"new","","Creates a new instance with each vector elements…",47,[[]]],[11,"lanes","","Returns the number of vector lanes.",47,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",47,[[]]],[11,"extract","","Extracts the value at `index`.",47,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",47,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",47,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",47,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",47,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",47,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",47,[[]]],[11,"all","","Are `all` vector lanes `true`?",47,[[]]],[11,"any","","Is `any` vector lane `true`?",47,[[]]],[11,"none","","Are `all` vector lanes `false`?",47,[[]]],[11,"eq","","Lane-wise equality comparison.",47,[[],["m64x2",6]]],[11,"ne","","Lane-wise inequality comparison.",47,[[],["m64x2",6]]],[11,"lt","","Lane-wise less-than comparison.",47,[[],["m64x2",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",47,[[],["m64x2",6]]],[11,"gt","","Lane-wise greater-than comparison.",47,[[],["m64x2",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",47,[[],["m64x2",6]]],[11,"select","","Selects elements of `a` and `b` using mask.",47,[[["simd",3]],["simd",3]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",47,[[],[["lexicographicallyordered",3],["m64x2",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",47,[[],[["lexicographicallyordered",3],["m64x2",6]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",47,[[]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",47,[[]]],[11,"new","","Creates a new instance with each vector elements…",51,[[]]],[11,"lanes","","Returns the number of vector lanes.",51,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",51,[[]]],[11,"extract","","Extracts the value at `index`.",51,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",51,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",51,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",51,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",51,[[["i128x1",6]],["i128x1",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",51,[[["i128x1",6]],["i128x1",6]]],[11,"min","","Minimum of two vectors.",51,[[]]],[11,"max","","Maximum of two vectors.",51,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",51,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",51,[[]]],[11,"max_element","","Largest vector element value.",51,[[]]],[11,"min_element","","Smallest vector element value.",51,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",51,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",51,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",51,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",51,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",51,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",51,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",51,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",51,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",51,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",51,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",51,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",51,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",51,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",51,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",51,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",51,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",51,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",51,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",51,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",51,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",51,[[]]],[11,"eq","","Lane-wise equality comparison.",51,[[],["m128x1",6]]],[11,"ne","","Lane-wise inequality comparison.",51,[[],["m128x1",6]]],[11,"lt","","Lane-wise less-than comparison.",51,[[],["m128x1",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",51,[[],["m128x1",6]]],[11,"gt","","Lane-wise greater-than comparison.",51,[[],["m128x1",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",51,[[],["m128x1",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",51,[[],[["i128x1",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",51,[[],[["i128x1",6],["lexicographicallyordered",3]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",51,[[]]],[11,"new","","Creates a new instance with each vector elements…",52,[[]]],[11,"lanes","","Returns the number of vector lanes.",52,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",52,[[]]],[11,"extract","","Extracts the value at `index`.",52,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",52,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",52,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",52,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",52,[[["u128x1",6]],["u128x1",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",52,[[["u128x1",6]],["u128x1",6]]],[11,"min","","Minimum of two vectors.",52,[[]]],[11,"max","","Maximum of two vectors.",52,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",52,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",52,[[]]],[11,"max_element","","Largest vector element value.",52,[[]]],[11,"min_element","","Smallest vector element value.",52,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",52,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",52,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",52,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",52,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",52,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",52,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",52,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",52,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",52,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",52,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",52,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",52,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",52,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",52,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",52,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",52,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",52,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",52,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",52,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",52,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",52,[[]]],[11,"eq","","Lane-wise equality comparison.",52,[[],["m128x1",6]]],[11,"ne","","Lane-wise inequality comparison.",52,[[],["m128x1",6]]],[11,"lt","","Lane-wise less-than comparison.",52,[[],["m128x1",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",52,[[],["m128x1",6]]],[11,"gt","","Lane-wise greater-than comparison.",52,[[],["m128x1",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",52,[[],["m128x1",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",52,[[],[["lexicographicallyordered",3],["u128x1",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",52,[[],[["lexicographicallyordered",3],["u128x1",6]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",52,[[]]],[11,"new","","Creates a new instance with each vector elements…",53,[[]]],[11,"lanes","","Returns the number of vector lanes.",53,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",53,[[]]],[11,"extract","","Extracts the value at `index`.",53,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",53,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",53,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",53,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",53,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",53,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",53,[[]]],[11,"all","","Are `all` vector lanes `true`?",53,[[]]],[11,"any","","Is `any` vector lane `true`?",53,[[]]],[11,"none","","Are `all` vector lanes `false`?",53,[[]]],[11,"eq","","Lane-wise equality comparison.",53,[[],["m128x1",6]]],[11,"ne","","Lane-wise inequality comparison.",53,[[],["m128x1",6]]],[11,"lt","","Lane-wise less-than comparison.",53,[[],["m128x1",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",53,[[],["m128x1",6]]],[11,"gt","","Lane-wise greater-than comparison.",53,[[],["m128x1",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",53,[[],["m128x1",6]]],[11,"select","","Selects elements of `a` and `b` using mask.",53,[[["simd",3]],["simd",3]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",53,[[],[["lexicographicallyordered",3],["m128x1",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",53,[[],[["lexicographicallyordered",3],["m128x1",6]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",53,[[]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",53,[[]]],[11,"new","","Creates a new instance with each vector elements…",54,[[]]],[11,"lanes","","Returns the number of vector lanes.",54,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",54,[[]]],[11,"extract","","Extracts the value at `index`.",54,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",54,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",54,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",54,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",54,[[["i8x32",6]],["i8x32",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",54,[[["i8x32",6]],["i8x32",6]]],[11,"min","","Minimum of two vectors.",54,[[]]],[11,"max","","Maximum of two vectors.",54,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",54,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",54,[[]]],[11,"max_element","","Largest vector element value.",54,[[]]],[11,"min_element","","Smallest vector element value.",54,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",54,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",54,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",54,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",54,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",54,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",54,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",54,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",54,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",54,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",54,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",54,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",54,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",54,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",54,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",54,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",54,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",54,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",54,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",54,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",54,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",54,[[]]],[11,"eq","","Lane-wise equality comparison.",54,[[],["m8x32",6]]],[11,"ne","","Lane-wise inequality comparison.",54,[[],["m8x32",6]]],[11,"lt","","Lane-wise less-than comparison.",54,[[],["m8x32",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",54,[[],["m8x32",6]]],[11,"gt","","Lane-wise greater-than comparison.",54,[[],["m8x32",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",54,[[],["m8x32",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",54,[[],[["lexicographicallyordered",3],["i8x32",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",54,[[],[["lexicographicallyordered",3],["i8x32",6]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",54,[[]]],[11,"new","","Creates a new instance with each vector elements…",55,[[]]],[11,"lanes","","Returns the number of vector lanes.",55,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",55,[[]]],[11,"extract","","Extracts the value at `index`.",55,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",55,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",55,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",55,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",55,[[["u8x32",6]],["u8x32",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",55,[[["u8x32",6]],["u8x32",6]]],[11,"min","","Minimum of two vectors.",55,[[]]],[11,"max","","Maximum of two vectors.",55,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",55,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",55,[[]]],[11,"max_element","","Largest vector element value.",55,[[]]],[11,"min_element","","Smallest vector element value.",55,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",55,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",55,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",55,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",55,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",55,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",55,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",55,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",55,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",55,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",55,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",55,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",55,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",55,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",55,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",55,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",55,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",55,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",55,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",55,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",55,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",55,[[]]],[11,"eq","","Lane-wise equality comparison.",55,[[],["m8x32",6]]],[11,"ne","","Lane-wise inequality comparison.",55,[[],["m8x32",6]]],[11,"lt","","Lane-wise less-than comparison.",55,[[],["m8x32",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",55,[[],["m8x32",6]]],[11,"gt","","Lane-wise greater-than comparison.",55,[[],["m8x32",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",55,[[],["m8x32",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",55,[[],[["lexicographicallyordered",3],["u8x32",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",55,[[],[["lexicographicallyordered",3],["u8x32",6]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",55,[[]]],[11,"new","","Creates a new instance with each vector elements…",56,[[]]],[11,"lanes","","Returns the number of vector lanes.",56,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",56,[[]]],[11,"extract","","Extracts the value at `index`.",56,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",56,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",56,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",56,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",56,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",56,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",56,[[]]],[11,"all","","Are `all` vector lanes `true`?",56,[[]]],[11,"any","","Is `any` vector lane `true`?",56,[[]]],[11,"none","","Are `all` vector lanes `false`?",56,[[]]],[11,"eq","","Lane-wise equality comparison.",56,[[],["m8x32",6]]],[11,"ne","","Lane-wise inequality comparison.",56,[[],["m8x32",6]]],[11,"lt","","Lane-wise less-than comparison.",56,[[],["m8x32",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",56,[[],["m8x32",6]]],[11,"gt","","Lane-wise greater-than comparison.",56,[[],["m8x32",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",56,[[],["m8x32",6]]],[11,"select","","Selects elements of `a` and `b` using mask.",56,[[["simd",3]],["simd",3]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",56,[[],[["lexicographicallyordered",3],["m8x32",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",56,[[],[["lexicographicallyordered",3],["m8x32",6]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",56,[[]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",56,[[]]],[11,"new","","Creates a new instance with each vector elements…",57,[[]]],[11,"lanes","","Returns the number of vector lanes.",57,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",57,[[]]],[11,"extract","","Extracts the value at `index`.",57,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",57,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",57,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",57,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",57,[[["i16x16",6]],["i16x16",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",57,[[["i16x16",6]],["i16x16",6]]],[11,"min","","Minimum of two vectors.",57,[[]]],[11,"max","","Maximum of two vectors.",57,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",57,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",57,[[]]],[11,"max_element","","Largest vector element value.",57,[[]]],[11,"min_element","","Smallest vector element value.",57,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",57,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",57,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",57,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",57,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",57,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",57,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",57,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",57,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",57,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",57,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",57,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",57,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",57,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",57,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",57,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",57,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",57,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",57,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",57,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",57,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",57,[[]]],[11,"eq","","Lane-wise equality comparison.",57,[[],["m16x16",6]]],[11,"ne","","Lane-wise inequality comparison.",57,[[],["m16x16",6]]],[11,"lt","","Lane-wise less-than comparison.",57,[[],["m16x16",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",57,[[],["m16x16",6]]],[11,"gt","","Lane-wise greater-than comparison.",57,[[],["m16x16",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",57,[[],["m16x16",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",57,[[],[["lexicographicallyordered",3],["i16x16",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",57,[[],[["lexicographicallyordered",3],["i16x16",6]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",57,[[]]],[11,"new","","Creates a new instance with each vector elements…",58,[[]]],[11,"lanes","","Returns the number of vector lanes.",58,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",58,[[]]],[11,"extract","","Extracts the value at `index`.",58,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",58,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",58,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",58,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",58,[[["u16x16",6]],["u16x16",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",58,[[["u16x16",6]],["u16x16",6]]],[11,"min","","Minimum of two vectors.",58,[[]]],[11,"max","","Maximum of two vectors.",58,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",58,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",58,[[]]],[11,"max_element","","Largest vector element value.",58,[[]]],[11,"min_element","","Smallest vector element value.",58,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",58,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",58,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",58,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",58,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",58,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",58,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",58,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",58,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",58,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",58,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",58,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",58,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",58,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",58,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",58,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",58,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",58,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",58,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",58,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",58,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",58,[[]]],[11,"eq","","Lane-wise equality comparison.",58,[[],["m16x16",6]]],[11,"ne","","Lane-wise inequality comparison.",58,[[],["m16x16",6]]],[11,"lt","","Lane-wise less-than comparison.",58,[[],["m16x16",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",58,[[],["m16x16",6]]],[11,"gt","","Lane-wise greater-than comparison.",58,[[],["m16x16",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",58,[[],["m16x16",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",58,[[],[["lexicographicallyordered",3],["u16x16",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",58,[[],[["lexicographicallyordered",3],["u16x16",6]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",58,[[]]],[11,"new","","Creates a new instance with each vector elements…",59,[[]]],[11,"lanes","","Returns the number of vector lanes.",59,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",59,[[]]],[11,"extract","","Extracts the value at `index`.",59,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",59,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",59,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",59,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",59,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",59,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",59,[[]]],[11,"all","","Are `all` vector lanes `true`?",59,[[]]],[11,"any","","Is `any` vector lane `true`?",59,[[]]],[11,"none","","Are `all` vector lanes `false`?",59,[[]]],[11,"eq","","Lane-wise equality comparison.",59,[[],["m16x16",6]]],[11,"ne","","Lane-wise inequality comparison.",59,[[],["m16x16",6]]],[11,"lt","","Lane-wise less-than comparison.",59,[[],["m16x16",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",59,[[],["m16x16",6]]],[11,"gt","","Lane-wise greater-than comparison.",59,[[],["m16x16",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",59,[[],["m16x16",6]]],[11,"select","","Selects elements of `a` and `b` using mask.",59,[[["simd",3]],["simd",3]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",59,[[],[["lexicographicallyordered",3],["m16x16",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",59,[[],[["lexicographicallyordered",3],["m16x16",6]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",59,[[]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",59,[[]]],[11,"new","","Creates a new instance with each vector elements…",60,[[]]],[11,"lanes","","Returns the number of vector lanes.",60,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",60,[[]]],[11,"extract","","Extracts the value at `index`.",60,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",60,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",60,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",60,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",60,[[["i32x8",6]],["i32x8",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",60,[[["i32x8",6]],["i32x8",6]]],[11,"min","","Minimum of two vectors.",60,[[]]],[11,"max","","Maximum of two vectors.",60,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",60,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",60,[[]]],[11,"max_element","","Largest vector element value.",60,[[]]],[11,"min_element","","Smallest vector element value.",60,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",60,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",60,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",60,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",60,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",60,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",60,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",60,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",60,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",60,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",60,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",60,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",60,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",60,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",60,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",60,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",60,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",60,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",60,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",60,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",60,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",60,[[]]],[11,"eq","","Lane-wise equality comparison.",60,[[],["m32x8",6]]],[11,"ne","","Lane-wise inequality comparison.",60,[[],["m32x8",6]]],[11,"lt","","Lane-wise less-than comparison.",60,[[],["m32x8",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",60,[[],["m32x8",6]]],[11,"gt","","Lane-wise greater-than comparison.",60,[[],["m32x8",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",60,[[],["m32x8",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",60,[[],[["lexicographicallyordered",3],["i32x8",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",60,[[],[["lexicographicallyordered",3],["i32x8",6]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",60,[[]]],[11,"new","","Creates a new instance with each vector elements…",61,[[]]],[11,"lanes","","Returns the number of vector lanes.",61,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",61,[[]]],[11,"extract","","Extracts the value at `index`.",61,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",61,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",61,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",61,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",61,[[["u32x8",6]],["u32x8",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",61,[[["u32x8",6]],["u32x8",6]]],[11,"min","","Minimum of two vectors.",61,[[]]],[11,"max","","Maximum of two vectors.",61,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",61,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",61,[[]]],[11,"max_element","","Largest vector element value.",61,[[]]],[11,"min_element","","Smallest vector element value.",61,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",61,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",61,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",61,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",61,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",61,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",61,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",61,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",61,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",61,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",61,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",61,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",61,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",61,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",61,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",61,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",61,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",61,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",61,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",61,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",61,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",61,[[]]],[11,"eq","","Lane-wise equality comparison.",61,[[],["m32x8",6]]],[11,"ne","","Lane-wise inequality comparison.",61,[[],["m32x8",6]]],[11,"lt","","Lane-wise less-than comparison.",61,[[],["m32x8",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",61,[[],["m32x8",6]]],[11,"gt","","Lane-wise greater-than comparison.",61,[[],["m32x8",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",61,[[],["m32x8",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",61,[[],[["u32x8",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",61,[[],[["u32x8",6],["lexicographicallyordered",3]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",61,[[]]],[11,"new","","Creates a new instance with each vector elements…",62,[[]]],[11,"lanes","","Returns the number of vector lanes.",62,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",62,[[]]],[11,"extract","","Extracts the value at `index`.",62,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",62,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",62,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",62,[[]]],[11,"min","","Minimum of two vectors.",62,[[]]],[11,"max","","Maximum of two vectors.",62,[[]]],[11,"sum","","Horizontal sum of the vector elements.",62,[[]]],[11,"product","","Horizontal product of the vector elements.",62,[[]]],[11,"max_element","","Largest vector element value.",62,[[]]],[11,"min_element","","Smallest vector element value.",62,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",62,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",62,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",62,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",62,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",62,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",62,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",62,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",62,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",62,[[]]],[18,"EPSILON","","Machine epsilon value.",62,null],[18,"MIN","","Smallest finite value.",62,null],[18,"MIN_POSITIVE","","Smallest positive normal value.",62,null],[18,"MAX","","Largest finite value.",62,null],[18,"NAN","","Not a Number (NaN).",62,null],[18,"INFINITY","","Infinity (∞).",62,null],[18,"NEG_INFINITY","","Negative infinity (-∞).",62,null],[18,"PI","","Archimedes\' constant (π)",62,null],[18,"FRAC_PI_2","","π/2",62,null],[18,"FRAC_PI_3","","π/3",62,null],[18,"FRAC_PI_4","","π/4",62,null],[18,"FRAC_PI_6","","π/6",62,null],[18,"FRAC_PI_8","","π/8",62,null],[18,"FRAC_1_PI","","1/π",62,null],[18,"FRAC_2_PI","","2/π",62,null],[18,"FRAC_2_SQRT_PI","","2/sqrt(π)",62,null],[18,"SQRT_2","","sqrt(2)",62,null],[18,"FRAC_1_SQRT_2","","1/sqrt(2)",62,null],[18,"E","","Euler\'s number (e)",62,null],[18,"LOG2_E","","log2(e)",62,null],[18,"LOG10_E","","log10(e)",62,null],[18,"LN_2","","ln(2)",62,null],[18,"LN_10","","ln(10)",62,null],[11,"is_nan","","",62,[[],["m32x8",6]]],[11,"is_infinite","","",62,[[],["m32x8",6]]],[11,"is_finite","","",62,[[],["m32x8",6]]],[11,"abs","","Absolute value.",62,[[]]],[11,"cos","","Cosine.",62,[[]]],[11,"cos_pi","","Cosine of `self * PI`.",62,[[]]],[11,"exp","","Returns the exponential function of `self`: `e^(self)`.",62,[[]]],[11,"ln","","Returns the natural logarithm of `self`.",62,[[]]],[11,"mul_add","","Fused multiply add: `self * y + z`",62,[[]]],[11,"mul_adde","","Fused multiply add estimate: ~= `self * y + z`",62,[[]]],[11,"powf","","Raises `self` number to the floating point power of `x`.",62,[[]]],[11,"recpre","","Reciprocal estimate: `~= 1. / self`.",62,[[]]],[11,"rsqrte","","Reciprocal square-root estimate: `~= 1. / self.sqrt()`.",62,[[]]],[11,"sin","","Sine.",62,[[]]],[11,"sin_pi","","Sine of `self * PI`.",62,[[]]],[11,"sin_cos_pi","","Sine and cosine of `self * PI`.",62,[[]]],[11,"sqrt","","",62,[[]]],[11,"sqrte","","Square-root estimate.",62,[[]]],[11,"tanh","","Tanh.",62,[[]]],[11,"eq","","Lane-wise equality comparison.",62,[[],["m32x8",6]]],[11,"ne","","Lane-wise inequality comparison.",62,[[],["m32x8",6]]],[11,"lt","","Lane-wise less-than comparison.",62,[[],["m32x8",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",62,[[],["m32x8",6]]],[11,"gt","","Lane-wise greater-than comparison.",62,[[],["m32x8",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",62,[[],["m32x8",6]]],[11,"new","","Creates a new instance with each vector elements…",63,[[]]],[11,"lanes","","Returns the number of vector lanes.",63,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",63,[[]]],[11,"extract","","Extracts the value at `index`.",63,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",63,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",63,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",63,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",63,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",63,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",63,[[]]],[11,"all","","Are `all` vector lanes `true`?",63,[[]]],[11,"any","","Is `any` vector lane `true`?",63,[[]]],[11,"none","","Are `all` vector lanes `false`?",63,[[]]],[11,"eq","","Lane-wise equality comparison.",63,[[],["m32x8",6]]],[11,"ne","","Lane-wise inequality comparison.",63,[[],["m32x8",6]]],[11,"lt","","Lane-wise less-than comparison.",63,[[],["m32x8",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",63,[[],["m32x8",6]]],[11,"gt","","Lane-wise greater-than comparison.",63,[[],["m32x8",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",63,[[],["m32x8",6]]],[11,"select","","Selects elements of `a` and `b` using mask.",63,[[["simd",3]],["simd",3]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",63,[[],[["lexicographicallyordered",3],["m32x8",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",63,[[],[["lexicographicallyordered",3],["m32x8",6]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",63,[[]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",63,[[]]],[11,"new","","Creates a new instance with each vector elements…",64,[[]]],[11,"lanes","","Returns the number of vector lanes.",64,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",64,[[]]],[11,"extract","","Extracts the value at `index`.",64,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",64,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",64,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",64,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",64,[[["i64x4",6]],["i64x4",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",64,[[["i64x4",6]],["i64x4",6]]],[11,"min","","Minimum of two vectors.",64,[[]]],[11,"max","","Maximum of two vectors.",64,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",64,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",64,[[]]],[11,"max_element","","Largest vector element value.",64,[[]]],[11,"min_element","","Smallest vector element value.",64,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",64,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",64,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",64,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",64,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",64,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",64,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",64,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",64,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",64,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",64,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",64,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",64,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",64,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",64,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",64,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",64,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",64,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",64,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",64,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",64,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",64,[[]]],[11,"eq","","Lane-wise equality comparison.",64,[[],["m64x4",6]]],[11,"ne","","Lane-wise inequality comparison.",64,[[],["m64x4",6]]],[11,"lt","","Lane-wise less-than comparison.",64,[[],["m64x4",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",64,[[],["m64x4",6]]],[11,"gt","","Lane-wise greater-than comparison.",64,[[],["m64x4",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",64,[[],["m64x4",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",64,[[],[["lexicographicallyordered",3],["i64x4",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",64,[[],[["lexicographicallyordered",3],["i64x4",6]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",64,[[]]],[11,"new","","Creates a new instance with each vector elements…",65,[[]]],[11,"lanes","","Returns the number of vector lanes.",65,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",65,[[]]],[11,"extract","","Extracts the value at `index`.",65,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",65,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",65,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",65,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",65,[[["u64x4",6]],["u64x4",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",65,[[["u64x4",6]],["u64x4",6]]],[11,"min","","Minimum of two vectors.",65,[[]]],[11,"max","","Maximum of two vectors.",65,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",65,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",65,[[]]],[11,"max_element","","Largest vector element value.",65,[[]]],[11,"min_element","","Smallest vector element value.",65,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",65,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",65,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",65,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",65,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",65,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",65,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",65,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",65,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",65,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",65,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",65,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",65,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",65,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",65,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",65,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",65,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",65,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",65,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",65,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",65,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",65,[[]]],[11,"eq","","Lane-wise equality comparison.",65,[[],["m64x4",6]]],[11,"ne","","Lane-wise inequality comparison.",65,[[],["m64x4",6]]],[11,"lt","","Lane-wise less-than comparison.",65,[[],["m64x4",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",65,[[],["m64x4",6]]],[11,"gt","","Lane-wise greater-than comparison.",65,[[],["m64x4",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",65,[[],["m64x4",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",65,[[],[["lexicographicallyordered",3],["u64x4",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",65,[[],[["lexicographicallyordered",3],["u64x4",6]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",65,[[]]],[11,"new","","Creates a new instance with each vector elements…",66,[[]]],[11,"lanes","","Returns the number of vector lanes.",66,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",66,[[]]],[11,"extract","","Extracts the value at `index`.",66,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",66,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",66,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",66,[[]]],[11,"min","","Minimum of two vectors.",66,[[]]],[11,"max","","Maximum of two vectors.",66,[[]]],[11,"sum","","Horizontal sum of the vector elements.",66,[[]]],[11,"product","","Horizontal product of the vector elements.",66,[[]]],[11,"max_element","","Largest vector element value.",66,[[]]],[11,"min_element","","Smallest vector element value.",66,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",66,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",66,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",66,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",66,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",66,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",66,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",66,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",66,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",66,[[]]],[18,"EPSILON","","Machine epsilon value.",66,null],[18,"MIN","","Smallest finite value.",66,null],[18,"MIN_POSITIVE","","Smallest positive normal value.",66,null],[18,"MAX","","Largest finite value.",66,null],[18,"NAN","","Not a Number (NaN).",66,null],[18,"INFINITY","","Infinity (∞).",66,null],[18,"NEG_INFINITY","","Negative infinity (-∞).",66,null],[18,"PI","","Archimedes\' constant (π)",66,null],[18,"FRAC_PI_2","","π/2",66,null],[18,"FRAC_PI_3","","π/3",66,null],[18,"FRAC_PI_4","","π/4",66,null],[18,"FRAC_PI_6","","π/6",66,null],[18,"FRAC_PI_8","","π/8",66,null],[18,"FRAC_1_PI","","1/π",66,null],[18,"FRAC_2_PI","","2/π",66,null],[18,"FRAC_2_SQRT_PI","","2/sqrt(π)",66,null],[18,"SQRT_2","","sqrt(2)",66,null],[18,"FRAC_1_SQRT_2","","1/sqrt(2)",66,null],[18,"E","","Euler\'s number (e)",66,null],[18,"LOG2_E","","log2(e)",66,null],[18,"LOG10_E","","log10(e)",66,null],[18,"LN_2","","ln(2)",66,null],[18,"LN_10","","ln(10)",66,null],[11,"is_nan","","",66,[[],["m64x4",6]]],[11,"is_infinite","","",66,[[],["m64x4",6]]],[11,"is_finite","","",66,[[],["m64x4",6]]],[11,"abs","","Absolute value.",66,[[]]],[11,"cos","","Cosine.",66,[[]]],[11,"cos_pi","","Cosine of `self * PI`.",66,[[]]],[11,"exp","","Returns the exponential function of `self`: `e^(self)`.",66,[[]]],[11,"ln","","Returns the natural logarithm of `self`.",66,[[]]],[11,"mul_add","","Fused multiply add: `self * y + z`",66,[[]]],[11,"mul_adde","","Fused multiply add estimate: ~= `self * y + z`",66,[[]]],[11,"powf","","Raises `self` number to the floating point power of `x`.",66,[[]]],[11,"recpre","","Reciprocal estimate: `~= 1. / self`.",66,[[]]],[11,"rsqrte","","Reciprocal square-root estimate: `~= 1. / self.sqrt()`.",66,[[]]],[11,"sin","","Sine.",66,[[]]],[11,"sin_pi","","Sine of `self * PI`.",66,[[]]],[11,"sin_cos_pi","","Sine and cosine of `self * PI`.",66,[[]]],[11,"sqrt","","",66,[[]]],[11,"sqrte","","Square-root estimate.",66,[[]]],[11,"tanh","","Tanh.",66,[[]]],[11,"eq","","Lane-wise equality comparison.",66,[[],["m64x4",6]]],[11,"ne","","Lane-wise inequality comparison.",66,[[],["m64x4",6]]],[11,"lt","","Lane-wise less-than comparison.",66,[[],["m64x4",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",66,[[],["m64x4",6]]],[11,"gt","","Lane-wise greater-than comparison.",66,[[],["m64x4",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",66,[[],["m64x4",6]]],[11,"new","","Creates a new instance with each vector elements…",67,[[]]],[11,"lanes","","Returns the number of vector lanes.",67,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",67,[[]]],[11,"extract","","Extracts the value at `index`.",67,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",67,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",67,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",67,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",67,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",67,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",67,[[]]],[11,"all","","Are `all` vector lanes `true`?",67,[[]]],[11,"any","","Is `any` vector lane `true`?",67,[[]]],[11,"none","","Are `all` vector lanes `false`?",67,[[]]],[11,"eq","","Lane-wise equality comparison.",67,[[],["m64x4",6]]],[11,"ne","","Lane-wise inequality comparison.",67,[[],["m64x4",6]]],[11,"lt","","Lane-wise less-than comparison.",67,[[],["m64x4",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",67,[[],["m64x4",6]]],[11,"gt","","Lane-wise greater-than comparison.",67,[[],["m64x4",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",67,[[],["m64x4",6]]],[11,"select","","Selects elements of `a` and `b` using mask.",67,[[["simd",3]],["simd",3]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",67,[[],[["m64x4",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",67,[[],[["m64x4",6],["lexicographicallyordered",3]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",67,[[]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",67,[[]]],[11,"new","","Creates a new instance with each vector elements…",68,[[]]],[11,"lanes","","Returns the number of vector lanes.",68,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",68,[[]]],[11,"extract","","Extracts the value at `index`.",68,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",68,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",68,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",68,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",68,[[["i128x2",6]],["i128x2",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",68,[[["i128x2",6]],["i128x2",6]]],[11,"min","","Minimum of two vectors.",68,[[]]],[11,"max","","Maximum of two vectors.",68,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",68,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",68,[[]]],[11,"max_element","","Largest vector element value.",68,[[]]],[11,"min_element","","Smallest vector element value.",68,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",68,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",68,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",68,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",68,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",68,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",68,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",68,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",68,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",68,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",68,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",68,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",68,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",68,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",68,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",68,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",68,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",68,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",68,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",68,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",68,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",68,[[]]],[11,"eq","","Lane-wise equality comparison.",68,[[],["m128x2",6]]],[11,"ne","","Lane-wise inequality comparison.",68,[[],["m128x2",6]]],[11,"lt","","Lane-wise less-than comparison.",68,[[],["m128x2",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",68,[[],["m128x2",6]]],[11,"gt","","Lane-wise greater-than comparison.",68,[[],["m128x2",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",68,[[],["m128x2",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",68,[[],[["lexicographicallyordered",3],["i128x2",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",68,[[],[["lexicographicallyordered",3],["i128x2",6]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",68,[[]]],[11,"new","","Creates a new instance with each vector elements…",69,[[]]],[11,"lanes","","Returns the number of vector lanes.",69,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",69,[[]]],[11,"extract","","Extracts the value at `index`.",69,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",69,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",69,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",69,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",69,[[["u128x2",6]],["u128x2",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",69,[[["u128x2",6]],["u128x2",6]]],[11,"min","","Minimum of two vectors.",69,[[]]],[11,"max","","Maximum of two vectors.",69,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",69,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",69,[[]]],[11,"max_element","","Largest vector element value.",69,[[]]],[11,"min_element","","Smallest vector element value.",69,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",69,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",69,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",69,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",69,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",69,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",69,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",69,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",69,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",69,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",69,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",69,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",69,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",69,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",69,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",69,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",69,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",69,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",69,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",69,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",69,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",69,[[]]],[11,"eq","","Lane-wise equality comparison.",69,[[],["m128x2",6]]],[11,"ne","","Lane-wise inequality comparison.",69,[[],["m128x2",6]]],[11,"lt","","Lane-wise less-than comparison.",69,[[],["m128x2",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",69,[[],["m128x2",6]]],[11,"gt","","Lane-wise greater-than comparison.",69,[[],["m128x2",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",69,[[],["m128x2",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",69,[[],[["lexicographicallyordered",3],["u128x2",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",69,[[],[["lexicographicallyordered",3],["u128x2",6]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",69,[[]]],[11,"new","","Creates a new instance with each vector elements…",70,[[]]],[11,"lanes","","Returns the number of vector lanes.",70,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",70,[[]]],[11,"extract","","Extracts the value at `index`.",70,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",70,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",70,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",70,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",70,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",70,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",70,[[]]],[11,"all","","Are `all` vector lanes `true`?",70,[[]]],[11,"any","","Is `any` vector lane `true`?",70,[[]]],[11,"none","","Are `all` vector lanes `false`?",70,[[]]],[11,"eq","","Lane-wise equality comparison.",70,[[],["m128x2",6]]],[11,"ne","","Lane-wise inequality comparison.",70,[[],["m128x2",6]]],[11,"lt","","Lane-wise less-than comparison.",70,[[],["m128x2",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",70,[[],["m128x2",6]]],[11,"gt","","Lane-wise greater-than comparison.",70,[[],["m128x2",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",70,[[],["m128x2",6]]],[11,"select","","Selects elements of `a` and `b` using mask.",70,[[["simd",3]],["simd",3]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",70,[[],[["m128x2",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",70,[[],[["m128x2",6],["lexicographicallyordered",3]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",70,[[]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",70,[[]]],[11,"new","","Creates a new instance with each vector elements…",74,[[]]],[11,"lanes","","Returns the number of vector lanes.",74,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",74,[[]]],[11,"extract","","Extracts the value at `index`.",74,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",74,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",74,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",74,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",74,[[["i8x64",6]],["i8x64",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",74,[[["i8x64",6]],["i8x64",6]]],[11,"min","","Minimum of two vectors.",74,[[]]],[11,"max","","Maximum of two vectors.",74,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",74,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",74,[[]]],[11,"max_element","","Largest vector element value.",74,[[]]],[11,"min_element","","Smallest vector element value.",74,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",74,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",74,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",74,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",74,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",74,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",74,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",74,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",74,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",74,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",74,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",74,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",74,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",74,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",74,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",74,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",74,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",74,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",74,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",74,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",74,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",74,[[]]],[11,"eq","","Lane-wise equality comparison.",74,[[],["m8x64",6]]],[11,"ne","","Lane-wise inequality comparison.",74,[[],["m8x64",6]]],[11,"lt","","Lane-wise less-than comparison.",74,[[],["m8x64",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",74,[[],["m8x64",6]]],[11,"gt","","Lane-wise greater-than comparison.",74,[[],["m8x64",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",74,[[],["m8x64",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",74,[[],[["i8x64",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",74,[[],[["i8x64",6],["lexicographicallyordered",3]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",74,[[]]],[11,"new","","Creates a new instance with each vector elements…",75,[[]]],[11,"lanes","","Returns the number of vector lanes.",75,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",75,[[]]],[11,"extract","","Extracts the value at `index`.",75,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",75,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",75,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",75,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",75,[[["u8x64",6]],["u8x64",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",75,[[["u8x64",6]],["u8x64",6]]],[11,"min","","Minimum of two vectors.",75,[[]]],[11,"max","","Maximum of two vectors.",75,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",75,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",75,[[]]],[11,"max_element","","Largest vector element value.",75,[[]]],[11,"min_element","","Smallest vector element value.",75,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",75,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",75,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",75,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",75,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",75,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",75,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",75,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",75,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",75,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",75,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",75,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",75,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",75,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",75,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",75,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",75,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",75,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",75,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",75,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",75,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",75,[[]]],[11,"eq","","Lane-wise equality comparison.",75,[[],["m8x64",6]]],[11,"ne","","Lane-wise inequality comparison.",75,[[],["m8x64",6]]],[11,"lt","","Lane-wise less-than comparison.",75,[[],["m8x64",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",75,[[],["m8x64",6]]],[11,"gt","","Lane-wise greater-than comparison.",75,[[],["m8x64",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",75,[[],["m8x64",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",75,[[],[["u8x64",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",75,[[],[["u8x64",6],["lexicographicallyordered",3]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",75,[[]]],[11,"new","","Creates a new instance with each vector elements…",76,[[]]],[11,"lanes","","Returns the number of vector lanes.",76,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",76,[[]]],[11,"extract","","Extracts the value at `index`.",76,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",76,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",76,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",76,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",76,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",76,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",76,[[]]],[11,"all","","Are `all` vector lanes `true`?",76,[[]]],[11,"any","","Is `any` vector lane `true`?",76,[[]]],[11,"none","","Are `all` vector lanes `false`?",76,[[]]],[11,"eq","","Lane-wise equality comparison.",76,[[],["m8x64",6]]],[11,"ne","","Lane-wise inequality comparison.",76,[[],["m8x64",6]]],[11,"lt","","Lane-wise less-than comparison.",76,[[],["m8x64",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",76,[[],["m8x64",6]]],[11,"gt","","Lane-wise greater-than comparison.",76,[[],["m8x64",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",76,[[],["m8x64",6]]],[11,"select","","Selects elements of `a` and `b` using mask.",76,[[["simd",3]],["simd",3]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",76,[[],[["m8x64",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",76,[[],[["m8x64",6],["lexicographicallyordered",3]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",76,[[]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",76,[[]]],[11,"new","","Creates a new instance with each vector elements…",77,[[]]],[11,"lanes","","Returns the number of vector lanes.",77,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",77,[[]]],[11,"extract","","Extracts the value at `index`.",77,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",77,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",77,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",77,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",77,[[["i16x32",6]],["i16x32",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",77,[[["i16x32",6]],["i16x32",6]]],[11,"min","","Minimum of two vectors.",77,[[]]],[11,"max","","Maximum of two vectors.",77,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",77,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",77,[[]]],[11,"max_element","","Largest vector element value.",77,[[]]],[11,"min_element","","Smallest vector element value.",77,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",77,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",77,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",77,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",77,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",77,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",77,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",77,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",77,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",77,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",77,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",77,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",77,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",77,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",77,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",77,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",77,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",77,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",77,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",77,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",77,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",77,[[]]],[11,"eq","","Lane-wise equality comparison.",77,[[],["m16x32",6]]],[11,"ne","","Lane-wise inequality comparison.",77,[[],["m16x32",6]]],[11,"lt","","Lane-wise less-than comparison.",77,[[],["m16x32",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",77,[[],["m16x32",6]]],[11,"gt","","Lane-wise greater-than comparison.",77,[[],["m16x32",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",77,[[],["m16x32",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",77,[[],[["i16x32",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",77,[[],[["i16x32",6],["lexicographicallyordered",3]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",77,[[]]],[11,"new","","Creates a new instance with each vector elements…",78,[[]]],[11,"lanes","","Returns the number of vector lanes.",78,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",78,[[]]],[11,"extract","","Extracts the value at `index`.",78,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",78,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",78,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",78,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",78,[[["u16x32",6]],["u16x32",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",78,[[["u16x32",6]],["u16x32",6]]],[11,"min","","Minimum of two vectors.",78,[[]]],[11,"max","","Maximum of two vectors.",78,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",78,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",78,[[]]],[11,"max_element","","Largest vector element value.",78,[[]]],[11,"min_element","","Smallest vector element value.",78,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",78,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",78,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",78,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",78,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",78,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",78,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",78,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",78,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",78,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",78,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",78,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",78,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",78,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",78,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",78,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",78,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",78,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",78,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",78,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",78,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",78,[[]]],[11,"eq","","Lane-wise equality comparison.",78,[[],["m16x32",6]]],[11,"ne","","Lane-wise inequality comparison.",78,[[],["m16x32",6]]],[11,"lt","","Lane-wise less-than comparison.",78,[[],["m16x32",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",78,[[],["m16x32",6]]],[11,"gt","","Lane-wise greater-than comparison.",78,[[],["m16x32",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",78,[[],["m16x32",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",78,[[],[["u16x32",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",78,[[],[["u16x32",6],["lexicographicallyordered",3]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",78,[[]]],[11,"new","","Creates a new instance with each vector elements…",79,[[]]],[11,"lanes","","Returns the number of vector lanes.",79,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",79,[[]]],[11,"extract","","Extracts the value at `index`.",79,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",79,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",79,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",79,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",79,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",79,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",79,[[]]],[11,"all","","Are `all` vector lanes `true`?",79,[[]]],[11,"any","","Is `any` vector lane `true`?",79,[[]]],[11,"none","","Are `all` vector lanes `false`?",79,[[]]],[11,"eq","","Lane-wise equality comparison.",79,[[],["m16x32",6]]],[11,"ne","","Lane-wise inequality comparison.",79,[[],["m16x32",6]]],[11,"lt","","Lane-wise less-than comparison.",79,[[],["m16x32",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",79,[[],["m16x32",6]]],[11,"gt","","Lane-wise greater-than comparison.",79,[[],["m16x32",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",79,[[],["m16x32",6]]],[11,"select","","Selects elements of `a` and `b` using mask.",79,[[["simd",3]],["simd",3]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",79,[[],[["m16x32",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",79,[[],[["m16x32",6],["lexicographicallyordered",3]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",79,[[]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",79,[[]]],[11,"new","","Creates a new instance with each vector elements…",80,[[]]],[11,"lanes","","Returns the number of vector lanes.",80,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",80,[[]]],[11,"extract","","Extracts the value at `index`.",80,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",80,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",80,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",80,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",80,[[["i32x16",6]],["i32x16",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",80,[[["i32x16",6]],["i32x16",6]]],[11,"min","","Minimum of two vectors.",80,[[]]],[11,"max","","Maximum of two vectors.",80,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",80,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",80,[[]]],[11,"max_element","","Largest vector element value.",80,[[]]],[11,"min_element","","Smallest vector element value.",80,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",80,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",80,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",80,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",80,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",80,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",80,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",80,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",80,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",80,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",80,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",80,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",80,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",80,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",80,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",80,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",80,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",80,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",80,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",80,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",80,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",80,[[]]],[11,"eq","","Lane-wise equality comparison.",80,[[],["m32x16",6]]],[11,"ne","","Lane-wise inequality comparison.",80,[[],["m32x16",6]]],[11,"lt","","Lane-wise less-than comparison.",80,[[],["m32x16",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",80,[[],["m32x16",6]]],[11,"gt","","Lane-wise greater-than comparison.",80,[[],["m32x16",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",80,[[],["m32x16",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",80,[[],[["i32x16",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",80,[[],[["i32x16",6],["lexicographicallyordered",3]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",80,[[]]],[11,"new","","Creates a new instance with each vector elements…",81,[[]]],[11,"lanes","","Returns the number of vector lanes.",81,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",81,[[]]],[11,"extract","","Extracts the value at `index`.",81,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",81,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",81,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",81,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",81,[[["u32x16",6]],["u32x16",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",81,[[["u32x16",6]],["u32x16",6]]],[11,"min","","Minimum of two vectors.",81,[[]]],[11,"max","","Maximum of two vectors.",81,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",81,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",81,[[]]],[11,"max_element","","Largest vector element value.",81,[[]]],[11,"min_element","","Smallest vector element value.",81,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",81,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",81,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",81,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",81,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",81,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",81,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",81,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",81,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",81,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",81,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",81,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",81,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",81,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",81,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",81,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",81,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",81,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",81,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",81,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",81,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",81,[[]]],[11,"eq","","Lane-wise equality comparison.",81,[[],["m32x16",6]]],[11,"ne","","Lane-wise inequality comparison.",81,[[],["m32x16",6]]],[11,"lt","","Lane-wise less-than comparison.",81,[[],["m32x16",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",81,[[],["m32x16",6]]],[11,"gt","","Lane-wise greater-than comparison.",81,[[],["m32x16",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",81,[[],["m32x16",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",81,[[],[["lexicographicallyordered",3],["u32x16",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",81,[[],[["lexicographicallyordered",3],["u32x16",6]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",81,[[]]],[11,"new","","Creates a new instance with each vector elements…",82,[[]]],[11,"lanes","","Returns the number of vector lanes.",82,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",82,[[]]],[11,"extract","","Extracts the value at `index`.",82,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",82,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",82,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",82,[[]]],[11,"min","","Minimum of two vectors.",82,[[]]],[11,"max","","Maximum of two vectors.",82,[[]]],[11,"sum","","Horizontal sum of the vector elements.",82,[[]]],[11,"product","","Horizontal product of the vector elements.",82,[[]]],[11,"max_element","","Largest vector element value.",82,[[]]],[11,"min_element","","Smallest vector element value.",82,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",82,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",82,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",82,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",82,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",82,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",82,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",82,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",82,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",82,[[]]],[18,"EPSILON","","Machine epsilon value.",82,null],[18,"MIN","","Smallest finite value.",82,null],[18,"MIN_POSITIVE","","Smallest positive normal value.",82,null],[18,"MAX","","Largest finite value.",82,null],[18,"NAN","","Not a Number (NaN).",82,null],[18,"INFINITY","","Infinity (∞).",82,null],[18,"NEG_INFINITY","","Negative infinity (-∞).",82,null],[18,"PI","","Archimedes\' constant (π)",82,null],[18,"FRAC_PI_2","","π/2",82,null],[18,"FRAC_PI_3","","π/3",82,null],[18,"FRAC_PI_4","","π/4",82,null],[18,"FRAC_PI_6","","π/6",82,null],[18,"FRAC_PI_8","","π/8",82,null],[18,"FRAC_1_PI","","1/π",82,null],[18,"FRAC_2_PI","","2/π",82,null],[18,"FRAC_2_SQRT_PI","","2/sqrt(π)",82,null],[18,"SQRT_2","","sqrt(2)",82,null],[18,"FRAC_1_SQRT_2","","1/sqrt(2)",82,null],[18,"E","","Euler\'s number (e)",82,null],[18,"LOG2_E","","log2(e)",82,null],[18,"LOG10_E","","log10(e)",82,null],[18,"LN_2","","ln(2)",82,null],[18,"LN_10","","ln(10)",82,null],[11,"is_nan","","",82,[[],["m32x16",6]]],[11,"is_infinite","","",82,[[],["m32x16",6]]],[11,"is_finite","","",82,[[],["m32x16",6]]],[11,"abs","","Absolute value.",82,[[]]],[11,"cos","","Cosine.",82,[[]]],[11,"cos_pi","","Cosine of `self * PI`.",82,[[]]],[11,"exp","","Returns the exponential function of `self`: `e^(self)`.",82,[[]]],[11,"ln","","Returns the natural logarithm of `self`.",82,[[]]],[11,"mul_add","","Fused multiply add: `self * y + z`",82,[[]]],[11,"mul_adde","","Fused multiply add estimate: ~= `self * y + z`",82,[[]]],[11,"powf","","Raises `self` number to the floating point power of `x`.",82,[[]]],[11,"recpre","","Reciprocal estimate: `~= 1. / self`.",82,[[]]],[11,"rsqrte","","Reciprocal square-root estimate: `~= 1. / self.sqrt()`.",82,[[]]],[11,"sin","","Sine.",82,[[]]],[11,"sin_pi","","Sine of `self * PI`.",82,[[]]],[11,"sin_cos_pi","","Sine and cosine of `self * PI`.",82,[[]]],[11,"sqrt","","",82,[[]]],[11,"sqrte","","Square-root estimate.",82,[[]]],[11,"tanh","","Tanh.",82,[[]]],[11,"eq","","Lane-wise equality comparison.",82,[[],["m32x16",6]]],[11,"ne","","Lane-wise inequality comparison.",82,[[],["m32x16",6]]],[11,"lt","","Lane-wise less-than comparison.",82,[[],["m32x16",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",82,[[],["m32x16",6]]],[11,"gt","","Lane-wise greater-than comparison.",82,[[],["m32x16",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",82,[[],["m32x16",6]]],[11,"new","","Creates a new instance with each vector elements…",83,[[]]],[11,"lanes","","Returns the number of vector lanes.",83,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",83,[[]]],[11,"extract","","Extracts the value at `index`.",83,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",83,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",83,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",83,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",83,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",83,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",83,[[]]],[11,"all","","Are `all` vector lanes `true`?",83,[[]]],[11,"any","","Is `any` vector lane `true`?",83,[[]]],[11,"none","","Are `all` vector lanes `false`?",83,[[]]],[11,"eq","","Lane-wise equality comparison.",83,[[],["m32x16",6]]],[11,"ne","","Lane-wise inequality comparison.",83,[[],["m32x16",6]]],[11,"lt","","Lane-wise less-than comparison.",83,[[],["m32x16",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",83,[[],["m32x16",6]]],[11,"gt","","Lane-wise greater-than comparison.",83,[[],["m32x16",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",83,[[],["m32x16",6]]],[11,"select","","Selects elements of `a` and `b` using mask.",83,[[["simd",3]],["simd",3]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",83,[[],[["lexicographicallyordered",3],["m32x16",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",83,[[],[["lexicographicallyordered",3],["m32x16",6]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",83,[[]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",83,[[]]],[11,"new","","Creates a new instance with each vector elements…",84,[[]]],[11,"lanes","","Returns the number of vector lanes.",84,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",84,[[]]],[11,"extract","","Extracts the value at `index`.",84,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",84,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",84,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",84,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",84,[[["i64x8",6]],["i64x8",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",84,[[["i64x8",6]],["i64x8",6]]],[11,"min","","Minimum of two vectors.",84,[[]]],[11,"max","","Maximum of two vectors.",84,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",84,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",84,[[]]],[11,"max_element","","Largest vector element value.",84,[[]]],[11,"min_element","","Smallest vector element value.",84,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",84,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",84,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",84,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",84,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",84,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",84,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",84,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",84,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",84,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",84,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",84,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",84,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",84,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",84,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",84,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",84,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",84,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",84,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",84,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",84,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",84,[[]]],[11,"eq","","Lane-wise equality comparison.",84,[[],["m64x8",6]]],[11,"ne","","Lane-wise inequality comparison.",84,[[],["m64x8",6]]],[11,"lt","","Lane-wise less-than comparison.",84,[[],["m64x8",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",84,[[],["m64x8",6]]],[11,"gt","","Lane-wise greater-than comparison.",84,[[],["m64x8",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",84,[[],["m64x8",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",84,[[],[["i64x8",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",84,[[],[["i64x8",6],["lexicographicallyordered",3]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",84,[[]]],[11,"new","","Creates a new instance with each vector elements…",85,[[]]],[11,"lanes","","Returns the number of vector lanes.",85,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",85,[[]]],[11,"extract","","Extracts the value at `index`.",85,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",85,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",85,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",85,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",85,[[["u64x8",6]],["u64x8",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",85,[[["u64x8",6]],["u64x8",6]]],[11,"min","","Minimum of two vectors.",85,[[]]],[11,"max","","Maximum of two vectors.",85,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",85,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",85,[[]]],[11,"max_element","","Largest vector element value.",85,[[]]],[11,"min_element","","Smallest vector element value.",85,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",85,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",85,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",85,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",85,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",85,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",85,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",85,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",85,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",85,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",85,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",85,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",85,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",85,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",85,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",85,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",85,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",85,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",85,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",85,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",85,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",85,[[]]],[11,"eq","","Lane-wise equality comparison.",85,[[],["m64x8",6]]],[11,"ne","","Lane-wise inequality comparison.",85,[[],["m64x8",6]]],[11,"lt","","Lane-wise less-than comparison.",85,[[],["m64x8",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",85,[[],["m64x8",6]]],[11,"gt","","Lane-wise greater-than comparison.",85,[[],["m64x8",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",85,[[],["m64x8",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",85,[[],[["lexicographicallyordered",3],["u64x8",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",85,[[],[["lexicographicallyordered",3],["u64x8",6]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",85,[[]]],[11,"new","","Creates a new instance with each vector elements…",86,[[]]],[11,"lanes","","Returns the number of vector lanes.",86,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",86,[[]]],[11,"extract","","Extracts the value at `index`.",86,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",86,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",86,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",86,[[]]],[11,"min","","Minimum of two vectors.",86,[[]]],[11,"max","","Maximum of two vectors.",86,[[]]],[11,"sum","","Horizontal sum of the vector elements.",86,[[]]],[11,"product","","Horizontal product of the vector elements.",86,[[]]],[11,"max_element","","Largest vector element value.",86,[[]]],[11,"min_element","","Smallest vector element value.",86,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",86,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",86,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",86,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",86,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",86,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",86,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",86,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",86,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",86,[[]]],[18,"EPSILON","","Machine epsilon value.",86,null],[18,"MIN","","Smallest finite value.",86,null],[18,"MIN_POSITIVE","","Smallest positive normal value.",86,null],[18,"MAX","","Largest finite value.",86,null],[18,"NAN","","Not a Number (NaN).",86,null],[18,"INFINITY","","Infinity (∞).",86,null],[18,"NEG_INFINITY","","Negative infinity (-∞).",86,null],[18,"PI","","Archimedes\' constant (π)",86,null],[18,"FRAC_PI_2","","π/2",86,null],[18,"FRAC_PI_3","","π/3",86,null],[18,"FRAC_PI_4","","π/4",86,null],[18,"FRAC_PI_6","","π/6",86,null],[18,"FRAC_PI_8","","π/8",86,null],[18,"FRAC_1_PI","","1/π",86,null],[18,"FRAC_2_PI","","2/π",86,null],[18,"FRAC_2_SQRT_PI","","2/sqrt(π)",86,null],[18,"SQRT_2","","sqrt(2)",86,null],[18,"FRAC_1_SQRT_2","","1/sqrt(2)",86,null],[18,"E","","Euler\'s number (e)",86,null],[18,"LOG2_E","","log2(e)",86,null],[18,"LOG10_E","","log10(e)",86,null],[18,"LN_2","","ln(2)",86,null],[18,"LN_10","","ln(10)",86,null],[11,"is_nan","","",86,[[],["m64x8",6]]],[11,"is_infinite","","",86,[[],["m64x8",6]]],[11,"is_finite","","",86,[[],["m64x8",6]]],[11,"abs","","Absolute value.",86,[[]]],[11,"cos","","Cosine.",86,[[]]],[11,"cos_pi","","Cosine of `self * PI`.",86,[[]]],[11,"exp","","Returns the exponential function of `self`: `e^(self)`.",86,[[]]],[11,"ln","","Returns the natural logarithm of `self`.",86,[[]]],[11,"mul_add","","Fused multiply add: `self * y + z`",86,[[]]],[11,"mul_adde","","Fused multiply add estimate: ~= `self * y + z`",86,[[]]],[11,"powf","","Raises `self` number to the floating point power of `x`.",86,[[]]],[11,"recpre","","Reciprocal estimate: `~= 1. / self`.",86,[[]]],[11,"rsqrte","","Reciprocal square-root estimate: `~= 1. / self.sqrt()`.",86,[[]]],[11,"sin","","Sine.",86,[[]]],[11,"sin_pi","","Sine of `self * PI`.",86,[[]]],[11,"sin_cos_pi","","Sine and cosine of `self * PI`.",86,[[]]],[11,"sqrt","","",86,[[]]],[11,"sqrte","","Square-root estimate.",86,[[]]],[11,"tanh","","Tanh.",86,[[]]],[11,"eq","","Lane-wise equality comparison.",86,[[],["m64x8",6]]],[11,"ne","","Lane-wise inequality comparison.",86,[[],["m64x8",6]]],[11,"lt","","Lane-wise less-than comparison.",86,[[],["m64x8",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",86,[[],["m64x8",6]]],[11,"gt","","Lane-wise greater-than comparison.",86,[[],["m64x8",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",86,[[],["m64x8",6]]],[11,"new","","Creates a new instance with each vector elements…",87,[[]]],[11,"lanes","","Returns the number of vector lanes.",87,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",87,[[]]],[11,"extract","","Extracts the value at `index`.",87,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",87,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",87,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",87,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",87,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",87,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",87,[[]]],[11,"all","","Are `all` vector lanes `true`?",87,[[]]],[11,"any","","Is `any` vector lane `true`?",87,[[]]],[11,"none","","Are `all` vector lanes `false`?",87,[[]]],[11,"eq","","Lane-wise equality comparison.",87,[[],["m64x8",6]]],[11,"ne","","Lane-wise inequality comparison.",87,[[],["m64x8",6]]],[11,"lt","","Lane-wise less-than comparison.",87,[[],["m64x8",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",87,[[],["m64x8",6]]],[11,"gt","","Lane-wise greater-than comparison.",87,[[],["m64x8",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",87,[[],["m64x8",6]]],[11,"select","","Selects elements of `a` and `b` using mask.",87,[[["simd",3]],["simd",3]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",87,[[],[["m64x8",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",87,[[],[["m64x8",6],["lexicographicallyordered",3]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",87,[[]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",87,[[]]],[11,"new","","Creates a new instance with each vector elements…",88,[[]]],[11,"lanes","","Returns the number of vector lanes.",88,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",88,[[]]],[11,"extract","","Extracts the value at `index`.",88,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",88,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",88,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",88,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",88,[[["i128x4",6]],["i128x4",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",88,[[["i128x4",6]],["i128x4",6]]],[11,"min","","Minimum of two vectors.",88,[[]]],[11,"max","","Maximum of two vectors.",88,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",88,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",88,[[]]],[11,"max_element","","Largest vector element value.",88,[[]]],[11,"min_element","","Smallest vector element value.",88,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",88,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",88,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",88,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",88,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",88,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",88,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",88,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",88,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",88,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",88,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",88,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",88,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",88,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",88,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",88,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",88,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",88,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",88,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",88,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",88,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",88,[[]]],[11,"eq","","Lane-wise equality comparison.",88,[[],["m128x4",6]]],[11,"ne","","Lane-wise inequality comparison.",88,[[],["m128x4",6]]],[11,"lt","","Lane-wise less-than comparison.",88,[[],["m128x4",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",88,[[],["m128x4",6]]],[11,"gt","","Lane-wise greater-than comparison.",88,[[],["m128x4",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",88,[[],["m128x4",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",88,[[],[["i128x4",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",88,[[],[["i128x4",6],["lexicographicallyordered",3]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",88,[[]]],[11,"new","","Creates a new instance with each vector elements…",89,[[]]],[11,"lanes","","Returns the number of vector lanes.",89,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",89,[[]]],[11,"extract","","Extracts the value at `index`.",89,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",89,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",89,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",89,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",89,[[["u128x4",6]],["u128x4",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",89,[[["u128x4",6]],["u128x4",6]]],[11,"min","","Minimum of two vectors.",89,[[]]],[11,"max","","Maximum of two vectors.",89,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",89,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",89,[[]]],[11,"max_element","","Largest vector element value.",89,[[]]],[11,"min_element","","Smallest vector element value.",89,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",89,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",89,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",89,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",89,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",89,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",89,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",89,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",89,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",89,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",89,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",89,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",89,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",89,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",89,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",89,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",89,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",89,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",89,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",89,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",89,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",89,[[]]],[11,"eq","","Lane-wise equality comparison.",89,[[],["m128x4",6]]],[11,"ne","","Lane-wise inequality comparison.",89,[[],["m128x4",6]]],[11,"lt","","Lane-wise less-than comparison.",89,[[],["m128x4",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",89,[[],["m128x4",6]]],[11,"gt","","Lane-wise greater-than comparison.",89,[[],["m128x4",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",89,[[],["m128x4",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",89,[[],[["u128x4",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",89,[[],[["u128x4",6],["lexicographicallyordered",3]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",89,[[]]],[11,"new","","Creates a new instance with each vector elements…",90,[[]]],[11,"lanes","","Returns the number of vector lanes.",90,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",90,[[]]],[11,"extract","","Extracts the value at `index`.",90,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",90,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",90,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",90,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",90,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",90,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",90,[[]]],[11,"all","","Are `all` vector lanes `true`?",90,[[]]],[11,"any","","Is `any` vector lane `true`?",90,[[]]],[11,"none","","Are `all` vector lanes `false`?",90,[[]]],[11,"eq","","Lane-wise equality comparison.",90,[[],["m128x4",6]]],[11,"ne","","Lane-wise inequality comparison.",90,[[],["m128x4",6]]],[11,"lt","","Lane-wise less-than comparison.",90,[[],["m128x4",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",90,[[],["m128x4",6]]],[11,"gt","","Lane-wise greater-than comparison.",90,[[],["m128x4",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",90,[[],["m128x4",6]]],[11,"select","","Selects elements of `a` and `b` using mask.",90,[[["simd",3]],["simd",3]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",90,[[],[["m128x4",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",90,[[],[["m128x4",6],["lexicographicallyordered",3]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",90,[[]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",90,[[]]],[11,"new","","Creates a new instance with each vector elements…",48,[[]]],[11,"lanes","","Returns the number of vector lanes.",48,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",48,[[]]],[11,"extract","","Extracts the value at `index`.",48,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",48,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",48,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",48,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",48,[[["isizex2",6]],["isizex2",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",48,[[["isizex2",6]],["isizex2",6]]],[11,"min","","Minimum of two vectors.",48,[[]]],[11,"max","","Maximum of two vectors.",48,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",48,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",48,[[]]],[11,"max_element","","Largest vector element value.",48,[[]]],[11,"min_element","","Smallest vector element value.",48,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",48,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",48,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",48,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",48,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",48,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",48,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",48,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",48,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",48,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",48,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",48,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",48,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",48,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",48,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",48,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",48,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",48,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",48,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",48,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",48,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",48,[[]]],[11,"eq","","Lane-wise equality comparison.",48,[[],["msizex2",6]]],[11,"ne","","Lane-wise inequality comparison.",48,[[],["msizex2",6]]],[11,"lt","","Lane-wise less-than comparison.",48,[[],["msizex2",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",48,[[],["msizex2",6]]],[11,"gt","","Lane-wise greater-than comparison.",48,[[],["msizex2",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",48,[[],["msizex2",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",48,[[],[["isizex2",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",48,[[],[["isizex2",6],["lexicographicallyordered",3]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",48,[[]]],[11,"new","","Creates a new instance with each vector elements…",49,[[]]],[11,"lanes","","Returns the number of vector lanes.",49,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",49,[[]]],[11,"extract","","Extracts the value at `index`.",49,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",49,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",49,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",49,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",49,[[["usizex2",6]],["usizex2",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",49,[[["usizex2",6]],["usizex2",6]]],[11,"min","","Minimum of two vectors.",49,[[]]],[11,"max","","Maximum of two vectors.",49,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",49,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",49,[[]]],[11,"max_element","","Largest vector element value.",49,[[]]],[11,"min_element","","Smallest vector element value.",49,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",49,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",49,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",49,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",49,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",49,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",49,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",49,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",49,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",49,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",49,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",49,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",49,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",49,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",49,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",49,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",49,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",49,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",49,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",49,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",49,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",49,[[]]],[11,"eq","","Lane-wise equality comparison.",49,[[],["msizex2",6]]],[11,"ne","","Lane-wise inequality comparison.",49,[[],["msizex2",6]]],[11,"lt","","Lane-wise less-than comparison.",49,[[],["msizex2",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",49,[[],["msizex2",6]]],[11,"gt","","Lane-wise greater-than comparison.",49,[[],["msizex2",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",49,[[],["msizex2",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",49,[[],[["usizex2",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",49,[[],[["usizex2",6],["lexicographicallyordered",3]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",49,[[]]],[11,"new","","Creates a new instance with each vector elements…",50,[[]]],[11,"lanes","","Returns the number of vector lanes.",50,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",50,[[]]],[11,"extract","","Extracts the value at `index`.",50,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",50,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",50,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",50,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",50,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",50,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",50,[[]]],[11,"all","","Are `all` vector lanes `true`?",50,[[]]],[11,"any","","Is `any` vector lane `true`?",50,[[]]],[11,"none","","Are `all` vector lanes `false`?",50,[[]]],[11,"eq","","Lane-wise equality comparison.",50,[[],["msizex2",6]]],[11,"ne","","Lane-wise inequality comparison.",50,[[],["msizex2",6]]],[11,"lt","","Lane-wise less-than comparison.",50,[[],["msizex2",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",50,[[],["msizex2",6]]],[11,"gt","","Lane-wise greater-than comparison.",50,[[],["msizex2",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",50,[[],["msizex2",6]]],[11,"select","","Selects elements of `a` and `b` using mask.",50,[[["simd",3]],["simd",3]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",50,[[],[["msizex2",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",50,[[],[["msizex2",6],["lexicographicallyordered",3]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",50,[[]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",50,[[]]],[11,"new","","Creates a new instance with each vector elements…",71,[[]]],[11,"lanes","","Returns the number of vector lanes.",71,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",71,[[]]],[11,"extract","","Extracts the value at `index`.",71,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",71,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",71,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",71,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",71,[[["isizex4",6]],["isizex4",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",71,[[["isizex4",6]],["isizex4",6]]],[11,"min","","Minimum of two vectors.",71,[[]]],[11,"max","","Maximum of two vectors.",71,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",71,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",71,[[]]],[11,"max_element","","Largest vector element value.",71,[[]]],[11,"min_element","","Smallest vector element value.",71,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",71,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",71,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",71,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",71,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",71,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",71,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",71,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",71,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",71,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",71,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",71,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",71,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",71,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",71,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",71,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",71,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",71,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",71,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",71,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",71,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",71,[[]]],[11,"eq","","Lane-wise equality comparison.",71,[[],["msizex4",6]]],[11,"ne","","Lane-wise inequality comparison.",71,[[],["msizex4",6]]],[11,"lt","","Lane-wise less-than comparison.",71,[[],["msizex4",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",71,[[],["msizex4",6]]],[11,"gt","","Lane-wise greater-than comparison.",71,[[],["msizex4",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",71,[[],["msizex4",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",71,[[],[["isizex4",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",71,[[],[["isizex4",6],["lexicographicallyordered",3]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",71,[[]]],[11,"new","","Creates a new instance with each vector elements…",72,[[]]],[11,"lanes","","Returns the number of vector lanes.",72,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",72,[[]]],[11,"extract","","Extracts the value at `index`.",72,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",72,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",72,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",72,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",72,[[["usizex4",6]],["usizex4",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",72,[[["usizex4",6]],["usizex4",6]]],[11,"min","","Minimum of two vectors.",72,[[]]],[11,"max","","Maximum of two vectors.",72,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",72,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",72,[[]]],[11,"max_element","","Largest vector element value.",72,[[]]],[11,"min_element","","Smallest vector element value.",72,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",72,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",72,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",72,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",72,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",72,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",72,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",72,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",72,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",72,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",72,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",72,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",72,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",72,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",72,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",72,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",72,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",72,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",72,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",72,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",72,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",72,[[]]],[11,"eq","","Lane-wise equality comparison.",72,[[],["msizex4",6]]],[11,"ne","","Lane-wise inequality comparison.",72,[[],["msizex4",6]]],[11,"lt","","Lane-wise less-than comparison.",72,[[],["msizex4",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",72,[[],["msizex4",6]]],[11,"gt","","Lane-wise greater-than comparison.",72,[[],["msizex4",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",72,[[],["msizex4",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",72,[[],[["lexicographicallyordered",3],["usizex4",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",72,[[],[["lexicographicallyordered",3],["usizex4",6]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",72,[[]]],[11,"new","","Creates a new instance with each vector elements…",73,[[]]],[11,"lanes","","Returns the number of vector lanes.",73,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",73,[[]]],[11,"extract","","Extracts the value at `index`.",73,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",73,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",73,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",73,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",73,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",73,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",73,[[]]],[11,"all","","Are `all` vector lanes `true`?",73,[[]]],[11,"any","","Is `any` vector lane `true`?",73,[[]]],[11,"none","","Are `all` vector lanes `false`?",73,[[]]],[11,"eq","","Lane-wise equality comparison.",73,[[],["msizex4",6]]],[11,"ne","","Lane-wise inequality comparison.",73,[[],["msizex4",6]]],[11,"lt","","Lane-wise less-than comparison.",73,[[],["msizex4",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",73,[[],["msizex4",6]]],[11,"gt","","Lane-wise greater-than comparison.",73,[[],["msizex4",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",73,[[],["msizex4",6]]],[11,"select","","Selects elements of `a` and `b` using mask.",73,[[["simd",3]],["simd",3]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",73,[[],[["lexicographicallyordered",3],["msizex4",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",73,[[],[["lexicographicallyordered",3],["msizex4",6]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",73,[[]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",73,[[]]],[11,"new","","Creates a new instance with each vector elements…",91,[[]]],[11,"lanes","","Returns the number of vector lanes.",91,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",91,[[]]],[11,"extract","","Extracts the value at `index`.",91,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",91,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",91,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",91,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",91,[[["isizex8",6]],["isizex8",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",91,[[["isizex8",6]],["isizex8",6]]],[11,"min","","Minimum of two vectors.",91,[[]]],[11,"max","","Maximum of two vectors.",91,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",91,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",91,[[]]],[11,"max_element","","Largest vector element value.",91,[[]]],[11,"min_element","","Smallest vector element value.",91,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",91,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",91,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",91,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",91,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",91,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",91,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",91,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",91,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",91,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",91,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",91,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",91,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",91,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",91,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",91,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",91,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",91,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",91,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",91,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",91,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",91,[[]]],[11,"eq","","Lane-wise equality comparison.",91,[[],["msizex8",6]]],[11,"ne","","Lane-wise inequality comparison.",91,[[],["msizex8",6]]],[11,"lt","","Lane-wise less-than comparison.",91,[[],["msizex8",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",91,[[],["msizex8",6]]],[11,"gt","","Lane-wise greater-than comparison.",91,[[],["msizex8",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",91,[[],["msizex8",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",91,[[],[["isizex8",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",91,[[],[["isizex8",6],["lexicographicallyordered",3]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",91,[[]]],[11,"new","","Creates a new instance with each vector elements…",92,[[]]],[11,"lanes","","Returns the number of vector lanes.",92,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",92,[[]]],[11,"extract","","Extracts the value at `index`.",92,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",92,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",92,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",92,[[]]],[11,"rotate_left","","Shifts the bits of each lane to the left by the specified…",92,[[["usizex8",6]],["usizex8",6]]],[11,"rotate_right","","Shifts the bits of each lane to the right by the specified…",92,[[["usizex8",6]],["usizex8",6]]],[11,"min","","Minimum of two vectors.",92,[[]]],[11,"max","","Maximum of two vectors.",92,[[]]],[11,"wrapping_sum","","Horizontal wrapping sum of the vector elements.",92,[[]]],[11,"wrapping_product","","Horizontal wrapping product of the vector elements.",92,[[]]],[11,"max_element","","Largest vector element value.",92,[[]]],[11,"min_element","","Smallest vector element value.",92,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",92,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",92,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",92,[[]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",92,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",92,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",92,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",92,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",92,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",92,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",92,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",92,[[]]],[11,"swap_bytes","","Reverses the byte order of the vector.",92,[[]]],[11,"to_le","","Converts self to little endian from the target\'s endianness.",92,[[]]],[11,"to_be","","Converts self to big endian from the target\'s endianness.",92,[[]]],[11,"from_le","","Converts a vector from little endian to the target\'s…",92,[[]]],[11,"from_be","","Converts a vector from big endian to the target\'s…",92,[[]]],[11,"count_ones","","Returns the number of ones in the binary representation of…",92,[[]]],[11,"count_zeros","","Returns the number of zeros in the binary representation…",92,[[]]],[11,"leading_zeros","","Returns the number of leading zeros in the binary…",92,[[]]],[11,"trailing_zeros","","Returns the number of trailing zeros in the binary…",92,[[]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",92,[[]]],[11,"eq","","Lane-wise equality comparison.",92,[[],["msizex8",6]]],[11,"ne","","Lane-wise inequality comparison.",92,[[],["msizex8",6]]],[11,"lt","","Lane-wise less-than comparison.",92,[[],["msizex8",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",92,[[],["msizex8",6]]],[11,"gt","","Lane-wise greater-than comparison.",92,[[],["msizex8",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",92,[[],["msizex8",6]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",92,[[],[["usizex8",6],["lexicographicallyordered",3]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",92,[[],[["usizex8",6],["lexicographicallyordered",3]]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",92,[[]]],[11,"new","","Creates a new instance with each vector elements…",93,[[]]],[11,"lanes","","Returns the number of vector lanes.",93,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",93,[[]]],[11,"extract","","Extracts the value at `index`.",93,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",93,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",93,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",93,[[]]],[11,"and","","Lane-wise bitwise `and` of the vector elements.",93,[[]]],[11,"or","","Lane-wise bitwise `or` of the vector elements.",93,[[]]],[11,"xor","","Lane-wise bitwise `xor` of the vector elements.",93,[[]]],[11,"all","","Are `all` vector lanes `true`?",93,[[]]],[11,"any","","Is `any` vector lane `true`?",93,[[]]],[11,"none","","Are `all` vector lanes `false`?",93,[[]]],[11,"eq","","Lane-wise equality comparison.",93,[[],["msizex8",6]]],[11,"ne","","Lane-wise inequality comparison.",93,[[],["msizex8",6]]],[11,"lt","","Lane-wise less-than comparison.",93,[[],["msizex8",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",93,[[],["msizex8",6]]],[11,"gt","","Lane-wise greater-than comparison.",93,[[],["msizex8",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",93,[[],["msizex8",6]]],[11,"select","","Selects elements of `a` and `b` using mask.",93,[[["simd",3]],["simd",3]]],[11,"partial_lex_ord","","Returns a wrapper that implements `PartialOrd`.",93,[[],[["lexicographicallyordered",3],["msizex8",6]]]],[11,"lex_ord","","Returns a wrapper that implements `Ord`.",93,[[],[["lexicographicallyordered",3],["msizex8",6]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",93,[[]]],[11,"bitmask","","Creates a bitmask with the MSB of each vector lane.",93,[[]]],[11,"new","","Creates a new instance with each vector elements…",94,[[]]],[11,"lanes","","Returns the number of vector lanes.",94,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",94,[[]]],[11,"null","","Constructs a new instance with each element initialized to…",94,[[]]],[11,"is_null","","Returns a mask that selects those lanes that contain…",94,[[],["msizex2",6]]],[11,"extract","","Extracts the value at `index`.",94,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",94,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",94,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",94,[[]]],[11,"eq","","Lane-wise equality comparison.",94,[[],["msizex2",6]]],[11,"ne","","Lane-wise inequality comparison.",94,[[],["msizex2",6]]],[11,"lt","","Lane-wise less-than comparison.",94,[[],["msizex2",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",94,[[],["msizex2",6]]],[11,"gt","","Lane-wise greater-than comparison.",94,[[],["msizex2",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",94,[[],["msizex2",6]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",94,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",94,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",94,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",94,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",94,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",94,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",94,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",94,[[]]],[11,"offset","","Calculates the offset from a pointer.",94,[[["isizex2",6]]]],[11,"wrapping_offset","","Calculates the offset from a pointer using wrapping…",94,[[["isizex2",6]]]],[11,"offset_from","","Calculates the distance between two pointers.",94,[[],["isizex2",6]]],[11,"wrapping_offset_from","","Calculates the distance between two pointers.",94,[[],["isizex2",6]]],[11,"add","","Calculates the offset from a pointer (convenience for…",94,[[["usizex2",6]]]],[11,"sub","","Calculates the offset from a pointer (convenience for…",94,[[["usizex2",6]]]],[11,"wrapping_add","","Calculates the offset from a pointer using wrapping…",94,[[["usizex2",6]]]],[11,"wrapping_sub","","Calculates the offset from a pointer using wrapping…",94,[[["usizex2",6]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",94,[[]]],[11,"read","","Reads selected vector elements from memory.",94,[[["simd",3],["simd",3]],["simd",3]]],[11,"new","","Creates a new instance with each vector elements…",95,[[]]],[11,"lanes","","Returns the number of vector lanes.",95,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",95,[[]]],[11,"null","","Constructs a new instance with each element initialized to…",95,[[]]],[11,"is_null","","Returns a mask that selects those lanes that contain…",95,[[],["msizex2",6]]],[11,"extract","","Extracts the value at `index`.",95,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",95,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",95,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",95,[[]]],[11,"eq","","Lane-wise equality comparison.",95,[[],["msizex2",6]]],[11,"ne","","Lane-wise inequality comparison.",95,[[],["msizex2",6]]],[11,"lt","","Lane-wise less-than comparison.",95,[[],["msizex2",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",95,[[],["msizex2",6]]],[11,"gt","","Lane-wise greater-than comparison.",95,[[],["msizex2",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",95,[[],["msizex2",6]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",95,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",95,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",95,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",95,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",95,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",95,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",95,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",95,[[]]],[11,"offset","","Calculates the offset from a pointer.",95,[[["isizex2",6]]]],[11,"wrapping_offset","","Calculates the offset from a pointer using wrapping…",95,[[["isizex2",6]]]],[11,"offset_from","","Calculates the distance between two pointers.",95,[[],["isizex2",6]]],[11,"wrapping_offset_from","","Calculates the distance between two pointers.",95,[[],["isizex2",6]]],[11,"add","","Calculates the offset from a pointer (convenience for…",95,[[["usizex2",6]]]],[11,"sub","","Calculates the offset from a pointer (convenience for…",95,[[["usizex2",6]]]],[11,"wrapping_add","","Calculates the offset from a pointer using wrapping…",95,[[["usizex2",6]]]],[11,"wrapping_sub","","Calculates the offset from a pointer using wrapping…",95,[[["usizex2",6]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",95,[[]]],[11,"read","","Reads selected vector elements from memory.",95,[[["simd",3],["simd",3]],["simd",3]]],[11,"write","","Writes selected vector elements to memory.",95,[[["simd",3],["simd",3]]]],[11,"new","","Creates a new instance with each vector elements…",96,[[]]],[11,"lanes","","Returns the number of vector lanes.",96,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",96,[[]]],[11,"null","","Constructs a new instance with each element initialized to…",96,[[]]],[11,"is_null","","Returns a mask that selects those lanes that contain…",96,[[],["msizex4",6]]],[11,"extract","","Extracts the value at `index`.",96,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",96,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",96,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",96,[[]]],[11,"eq","","Lane-wise equality comparison.",96,[[],["msizex4",6]]],[11,"ne","","Lane-wise inequality comparison.",96,[[],["msizex4",6]]],[11,"lt","","Lane-wise less-than comparison.",96,[[],["msizex4",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",96,[[],["msizex4",6]]],[11,"gt","","Lane-wise greater-than comparison.",96,[[],["msizex4",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",96,[[],["msizex4",6]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",96,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the `slice`.",96,[[]]],[11,"from_slice_aligned_unchecked","","Instantiates a new vector with the values of the `slice`.",96,[[]]],[11,"from_slice_unaligned_unchecked","","Instantiates a new vector with the values of the `slice`.",96,[[]]],[11,"write_to_slice_aligned","","Writes the values of the vector to the `slice`.",96,[[]]],[11,"write_to_slice_unaligned","","Writes the values of the vector to the `slice`.",96,[[]]],[11,"write_to_slice_aligned_unchecked","","Writes the values of the vector to the `slice`.",96,[[]]],[11,"write_to_slice_unaligned_unchecked","","Writes the values of the vector to the `slice`.",96,[[]]],[11,"offset","","Calculates the offset from a pointer.",96,[[["isizex4",6]]]],[11,"wrapping_offset","","Calculates the offset from a pointer using wrapping…",96,[[["isizex4",6]]]],[11,"offset_from","","Calculates the distance between two pointers.",96,[[],["isizex4",6]]],[11,"wrapping_offset_from","","Calculates the distance between two pointers.",96,[[],["isizex4",6]]],[11,"add","","Calculates the offset from a pointer (convenience for…",96,[[["usizex4",6]]]],[11,"sub","","Calculates the offset from a pointer (convenience for…",96,[[["usizex4",6]]]],[11,"wrapping_add","","Calculates the offset from a pointer using wrapping…",96,[[["usizex4",6]]]],[11,"wrapping_sub","","Calculates the offset from a pointer using wrapping…",96,[[["usizex4",6]]]],[11,"shuffle1_dyn","","Shuffle vector elements according to `indices`.",96,[[]]],[11,"read","","Reads selected vector elements from memory.",96,[[["simd",3],["simd",3]],["simd",3]]],[11,"new","","Creates a new instance with each vector elements…",97,[[]]],[11,"lanes","","Returns the number of vector lanes.",97,[[]]],[11,"splat","","Constructs a new instance with each element initialized to…",97,[[]]],[11,"null","","Constructs a new instance with each element initialized to…",97,[[]]],[11,"is_null","","Returns a mask that selects those lanes that contain…",97,[[],["msizex4",6]]],[11,"extract","","Extracts the value at `index`.",97,[[]]],[11,"extract_unchecked","","Extracts the value at `index`.",97,[[]]],[11,"replace","","Returns a new vector where the value at `index` is…",97,[[]]],[11,"replace_unchecked","","Returns a new vector where the value at `index` is…",97,[[]]],[11,"eq","","Lane-wise equality comparison.",97,[[],["msizex4",6]]],[11,"ne","","Lane-wise inequality comparison.",97,[[],["msizex4",6]]],[11,"lt","","Lane-wise less-than comparison.",97,[[],["msizex4",6]]],[11,"le","","Lane-wise less-than-or-equals comparison.",97,[[],["msizex4",6]]],[11,"gt","","Lane-wise greater-than comparison.",97,[[],["msizex4",6]]],[11,"ge","","Lane-wise greater-than-or-equals comparison.",97,[[],["msizex4",6]]],[11,"from_slice_aligned","","Instantiates a new vector with the values of the `slice`.",97,[[]]],[11,"from_slice_unaligned","","Instantiates a new vector with the values of the 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\ No newline at end of file diff --git a/settings.js b/settings.js new file mode 100644 index 000000000..993030905 --- /dev/null +++ b/settings.js @@ -0,0 +1 @@ +(function(){function changeSetting(settingName,isEnabled){updateLocalStorage('rustdoc-'+settingName,isEnabled)}function getSettingValue(settingName){return getCurrentValue('rustdoc-'+settingName)}function setEvents(){var elems=document.getElementsByClassName("slider");if(!elems||elems.length===0){return}for(var i=0;i"){sidebar.style.left="";this.style.left="";child.innerText="<";updateLocalStorage("rustdoc-source-sidebar-show","true")}else{sidebar.style.left="-300px";this.style.left="0";child.innerText=">";updateLocalStorage("rustdoc-source-sidebar-show","false")}}function createSidebarToggle(){var sidebarToggle=document.createElement("div");sidebarToggle.id="sidebar-toggle";sidebarToggle.onclick=toggleSidebar;var inner1=document.createElement("div");inner1.style.position="relative";var inner2=document.createElement("div");inner2.style.paddingTop="3px";if(getCurrentValue("rustdoc-source-sidebar-show")==="true"){inner2.innerText="<"}else{inner2.innerText=">";sidebarToggle.style.left="0"}inner1.appendChild(inner2);sidebarToggle.appendChild(inner1);return sidebarToggle}function createSourceSidebar(){if(window.rootPath.endsWith("/")===false){window.rootPath+="/"}var main=document.getElementById("main");var sidebarToggle=createSidebarToggle();main.insertBefore(sidebarToggle,main.firstChild);var sidebar=document.createElement("div");sidebar.id="source-sidebar";if(getCurrentValue("rustdoc-source-sidebar-show")!=="true"){sidebar.style.left="-300px"}var currentFile=getCurrentFilePath();var hasFoundFile=false;var title=document.createElement("div");title.className="title";title.innerText="Files";sidebar.appendChild(title);Object.keys(sourcesIndex).forEach(function(key){sourcesIndex[key].name=key;hasFoundFile=createDirEntry(sourcesIndex[key],sidebar,"",currentFile,hasFoundFile)});main.insertBefore(sidebar,main.firstChild)} \ No newline at end of file diff --git a/src/cfg_if/lib.rs.html b/src/cfg_if/lib.rs.html new file mode 100644 index 000000000..6a712eb27 --- /dev/null +++ b/src/cfg_if/lib.rs.html @@ -0,0 +1,355 @@ +lib.rs.html -- source
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+
+//! A macro for defining `#[cfg]` if-else statements.
+//!
+//! The macro provided by this crate, `cfg_if`, is similar to the `if/elif` C
+//! preprocessor macro by allowing definition of a cascade of `#[cfg]` cases,
+//! emitting the implementation which matches first.
+//!
+//! This allows you to conveniently provide a long list `#[cfg]`'d blocks of code
+//! without having to rewrite each clause multiple times.
+//!
+//! # Example
+//!
+//! ```
+//! cfg_if::cfg_if! {
+//!     if #[cfg(unix)] {
+//!         fn foo() { /* unix specific functionality */ }
+//!     } else if #[cfg(target_pointer_width = "32")] {
+//!         fn foo() { /* non-unix, 32-bit functionality */ }
+//!     } else {
+//!         fn foo() { /* fallback implementation */ }
+//!     }
+//! }
+//!
+//! # fn main() {}
+//! ```
+
+#![no_std]
+#![doc(html_root_url = "https://docs.rs/cfg-if")]
+#![deny(missing_docs)]
+#![cfg_attr(test, deny(warnings))]
+
+/// The main macro provided by this crate. See crate documentation for more
+/// information.
+#[macro_export]
+macro_rules! cfg_if {
+    // match if/else chains with a final `else`
+    ($(
+        if #[cfg($($meta:meta),*)] { $($tokens:tt)* }
+    ) else * else {
+        $($tokens2:tt)*
+    }) => {
+        $crate::cfg_if! {
+            @__items
+            () ;
+            $( ( ($($meta),*) ($($tokens)*) ), )*
+            ( () ($($tokens2)*) ),
+        }
+    };
+
+    // match if/else chains lacking a final `else`
+    (
+        if #[cfg($($i_met:meta),*)] { $($i_tokens:tt)* }
+        $(
+            else if #[cfg($($e_met:meta),*)] { $($e_tokens:tt)* }
+        )*
+    ) => {
+        $crate::cfg_if! {
+            @__items
+            () ;
+            ( ($($i_met),*) ($($i_tokens)*) ),
+            $( ( ($($e_met),*) ($($e_tokens)*) ), )*
+            ( () () ),
+        }
+    };
+
+    // Internal and recursive macro to emit all the items
+    //
+    // Collects all the negated cfgs in a list at the beginning and after the
+    // semicolon is all the remaining items
+    (@__items ($($not:meta,)*) ; ) => {};
+    (@__items ($($not:meta,)*) ; ( ($($m:meta),*) ($($tokens:tt)*) ), $($rest:tt)*) => {
+        // Emit all items within one block, applying an appropriate #[cfg]. The
+        // #[cfg] will require all `$m` matchers specified and must also negate
+        // all previous matchers.
+        #[cfg(all($($m,)* not(any($($not),*))))] $crate::cfg_if! { @__identity $($tokens)* }
+
+        // Recurse to emit all other items in `$rest`, and when we do so add all
+        // our `$m` matchers to the list of `$not` matchers as future emissions
+        // will have to negate everything we just matched as well.
+        $crate::cfg_if! { @__items ($($not,)* $($m,)*) ; $($rest)* }
+    };
+
+    // Internal macro to make __apply work out right for different match types,
+    // because of how macros matching/expand stuff.
+    (@__identity $($tokens:tt)*) => {
+        $($tokens)*
+    };
+}
+
+#[cfg(test)]
+mod tests {
+    cfg_if! {
+        if #[cfg(test)] {
+            use core::option::Option as Option2;
+            fn works1() -> Option2<u32> { Some(1) }
+        } else {
+            fn works1() -> Option<u32> { None }
+        }
+    }
+
+    cfg_if! {
+        if #[cfg(foo)] {
+            fn works2() -> bool { false }
+        } else if #[cfg(test)] {
+            fn works2() -> bool { true }
+        } else {
+            fn works2() -> bool { false }
+        }
+    }
+
+    cfg_if! {
+        if #[cfg(foo)] {
+            fn works3() -> bool { false }
+        } else {
+            fn works3() -> bool { true }
+        }
+    }
+
+    cfg_if! {
+        if #[cfg(test)] {
+            use core::option::Option as Option3;
+            fn works4() -> Option3<u32> { Some(1) }
+        }
+    }
+
+    cfg_if! {
+        if #[cfg(foo)] {
+            fn works5() -> bool { false }
+        } else if #[cfg(test)] {
+            fn works5() -> bool { true }
+        }
+    }
+
+    #[test]
+    fn it_works() {
+        assert!(works1().is_some());
+        assert!(works2());
+        assert!(works3());
+        assert!(works4().is_some());
+        assert!(works5());
+    }
+
+    #[test]
+    #[allow(clippy::assertions_on_constants)]
+    fn test_usage_within_a_function() {
+        cfg_if! {if #[cfg(debug_assertions)] {
+            // we want to put more than one thing here to make sure that they
+            // all get configured properly.
+            assert!(cfg!(debug_assertions));
+            assert_eq!(4, 2+2);
+        } else {
+            assert!(works1().is_some());
+            assert_eq!(10, 5+5);
+        }}
+    }
+
+    trait Trait {
+        fn blah(&self);
+    }
+
+    #[allow(dead_code)]
+    struct Struct;
+
+    impl Trait for Struct {
+        cfg_if! {
+            if #[cfg(feature = "blah")] {
+                fn blah(&self) {
+                    unimplemented!();
+                }
+            } else {
+                fn blah(&self) {
+                    unimplemented!();
+                }
+            }
+        }
+    }
+}
+
+
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+
+//! libm in pure Rust
+//!
+//! # Usage
+//!
+//! You can use this crate in two ways:
+//!
+//! - By directly using its free functions, e.g. `libm::powf`.
+//!
+//! - By importing the `F32Ext` and / or `F64Ext` extension traits to add methods like `powf` to the
+//! `f32` and `f64` types. Then you'll be able to invoke math functions as methods, e.g. `x.sqrt()`.
+
+#![deny(warnings)]
+#![no_std]
+#![cfg_attr(
+    all(target_arch = "wasm32", not(feature = "stable")),
+    feature(core_intrinsics)
+)]
+
+mod math;
+
+use core::{f32, f64};
+
+pub use self::math::*;
+
+/// Approximate equality with 1 ULP of tolerance
+#[doc(hidden)]
+#[inline]
+pub fn _eqf(a: f32, b: f32) -> Result<(), u32> {
+    if a.is_nan() && b.is_nan() {
+        Ok(())
+    } else {
+        let err = (a.to_bits() as i32).wrapping_sub(b.to_bits() as i32).abs();
+
+        if err <= 1 {
+            Ok(())
+        } else {
+            Err(err as u32)
+        }
+    }
+}
+
+#[doc(hidden)]
+#[inline]
+pub fn _eq(a: f64, b: f64) -> Result<(), u64> {
+    if a.is_nan() && b.is_nan() {
+        Ok(())
+    } else {
+        let err = (a.to_bits() as i64).wrapping_sub(b.to_bits() as i64).abs();
+
+        if err <= 1 {
+            Ok(())
+        } else {
+            Err(err as u64)
+        }
+    }
+}
+
+/// Math support for `f32`
+///
+/// This trait is sealed and cannot be implemented outside of `libm`.
+pub trait F32Ext: private::Sealed + Sized {
+    fn floor(self) -> Self;
+
+    fn ceil(self) -> Self;
+
+    fn round(self) -> Self;
+
+    fn trunc(self) -> Self;
+
+    fn fdim(self, rhs: Self) -> Self;
+
+    fn fract(self) -> Self;
+
+    fn abs(self) -> Self;
+
+    // NOTE depends on unstable intrinsics::copysignf32
+    // fn signum(self) -> Self;
+
+    fn mul_add(self, a: Self, b: Self) -> Self;
+
+    fn div_euc(self, rhs: Self) -> Self;
+
+    fn mod_euc(self, rhs: Self) -> Self;
+
+    // NOTE depends on unstable intrinsics::powif32
+    // fn powi(self, n: i32) -> Self;
+
+    fn powf(self, n: Self) -> Self;
+
+    fn sqrt(self) -> Self;
+
+    fn exp(self) -> Self;
+
+    fn exp2(self) -> Self;
+
+    fn ln(self) -> Self;
+
+    fn log(self, base: Self) -> Self;
+
+    fn log2(self) -> Self;
+
+    fn log10(self) -> Self;
+
+    fn cbrt(self) -> Self;
+
+    fn hypot(self, other: Self) -> Self;
+
+    fn sin(self) -> Self;
+
+    fn cos(self) -> Self;
+
+    fn tan(self) -> Self;
+
+    fn asin(self) -> Self;
+
+    fn acos(self) -> Self;
+
+    fn atan(self) -> Self;
+
+    fn atan2(self, other: Self) -> Self;
+
+    fn sin_cos(self) -> (Self, Self);
+
+    fn exp_m1(self) -> Self;
+
+    fn ln_1p(self) -> Self;
+
+    fn sinh(self) -> Self;
+
+    fn cosh(self) -> Self;
+
+    fn tanh(self) -> Self;
+
+    fn asinh(self) -> Self;
+
+    fn acosh(self) -> Self;
+
+    fn atanh(self) -> Self;
+
+    fn min(self, other: Self) -> Self;
+
+    fn max(self, other: Self) -> Self;
+}
+
+impl F32Ext for f32 {
+    #[inline]
+    fn floor(self) -> Self {
+        floorf(self)
+    }
+
+    #[inline]
+    fn ceil(self) -> Self {
+        ceilf(self)
+    }
+
+    #[inline]
+    fn round(self) -> Self {
+        roundf(self)
+    }
+
+    #[inline]
+    fn trunc(self) -> Self {
+        truncf(self)
+    }
+
+    #[inline]
+    fn fdim(self, rhs: Self) -> Self {
+        fdimf(self, rhs)
+    }
+
+    #[inline]
+    fn fract(self) -> Self {
+        self - self.trunc()
+    }
+
+    #[inline]
+    fn abs(self) -> Self {
+        fabsf(self)
+    }
+
+    #[inline]
+    fn mul_add(self, a: Self, b: Self) -> Self {
+        fmaf(self, a, b)
+    }
+
+    #[inline]
+    fn div_euc(self, rhs: Self) -> Self {
+        let q = (self / rhs).trunc();
+        if self % rhs < 0.0 {
+            return if rhs > 0.0 { q - 1.0 } else { q + 1.0 };
+        }
+        q
+    }
+
+    #[inline]
+    fn mod_euc(self, rhs: f32) -> f32 {
+        let r = self % rhs;
+        if r < 0.0 {
+            r + rhs.abs()
+        } else {
+            r
+        }
+    }
+
+    #[inline]
+    fn powf(self, n: Self) -> Self {
+        powf(self, n)
+    }
+
+    #[inline]
+    fn sqrt(self) -> Self {
+        sqrtf(self)
+    }
+
+    #[inline]
+    fn exp(self) -> Self {
+        expf(self)
+    }
+
+    #[inline]
+    fn exp2(self) -> Self {
+        exp2f(self)
+    }
+
+    #[inline]
+    fn ln(self) -> Self {
+        logf(self)
+    }
+
+    #[inline]
+    fn log(self, base: Self) -> Self {
+        self.ln() / base.ln()
+    }
+
+    #[inline]
+    fn log2(self) -> Self {
+        log2f(self)
+    }
+
+    #[inline]
+    fn log10(self) -> Self {
+        log10f(self)
+    }
+
+    #[inline]
+    fn cbrt(self) -> Self {
+        cbrtf(self)
+    }
+
+    #[inline]
+    fn hypot(self, other: Self) -> Self {
+        hypotf(self, other)
+    }
+
+    #[inline]
+    fn sin(self) -> Self {
+        sinf(self)
+    }
+
+    #[inline]
+    fn cos(self) -> Self {
+        cosf(self)
+    }
+
+    #[inline]
+    fn tan(self) -> Self {
+        tanf(self)
+    }
+
+    #[inline]
+    fn asin(self) -> Self {
+        asinf(self)
+    }
+
+    #[inline]
+    fn acos(self) -> Self {
+        acosf(self)
+    }
+
+    #[inline]
+    fn atan(self) -> Self {
+        atanf(self)
+    }
+
+    #[inline]
+    fn atan2(self, other: Self) -> Self {
+        atan2f(self, other)
+    }
+
+    #[inline]
+    fn sin_cos(self) -> (Self, Self) {
+        sincosf(self)
+    }
+
+    #[inline]
+    fn exp_m1(self) -> Self {
+        expm1f(self)
+    }
+
+    #[inline]
+    fn ln_1p(self) -> Self {
+        log1pf(self)
+    }
+
+    #[inline]
+    fn sinh(self) -> Self {
+        sinhf(self)
+    }
+
+    #[inline]
+    fn cosh(self) -> Self {
+        coshf(self)
+    }
+
+    #[inline]
+    fn tanh(self) -> Self {
+        tanhf(self)
+    }
+
+    #[inline]
+    fn asinh(self) -> Self {
+        asinhf(self)
+    }
+
+    #[inline]
+    fn acosh(self) -> Self {
+        acoshf(self)
+    }
+
+    #[inline]
+    fn atanh(self) -> Self {
+        atanhf(self)
+    }
+
+    #[inline]
+    fn min(self, other: Self) -> Self {
+        fminf(self, other)
+    }
+
+    #[inline]
+    fn max(self, other: Self) -> Self {
+        fmaxf(self, other)
+    }
+}
+
+/// Math support for `f64`
+///
+/// This trait is sealed and cannot be implemented outside of `libm`.
+pub trait F64Ext: private::Sealed + Sized {
+    fn floor(self) -> Self;
+
+    fn ceil(self) -> Self;
+
+    fn round(self) -> Self;
+
+    fn trunc(self) -> Self;
+
+    fn fdim(self, rhs: Self) -> Self;
+
+    fn fract(self) -> Self;
+
+    fn abs(self) -> Self;
+
+    // NOTE depends on unstable intrinsics::copysignf64
+    // fn signum(self) -> Self;
+
+    fn mul_add(self, a: Self, b: Self) -> Self;
+
+    fn div_euc(self, rhs: Self) -> Self;
+
+    fn mod_euc(self, rhs: Self) -> Self;
+
+    // NOTE depends on unstable intrinsics::powif64
+    // fn powi(self, n: i32) -> Self;
+
+    fn powf(self, n: Self) -> Self;
+
+    fn sqrt(self) -> Self;
+
+    fn exp(self) -> Self;
+
+    fn exp2(self) -> Self;
+
+    fn ln(self) -> Self;
+
+    fn log(self, base: Self) -> Self;
+
+    fn log2(self) -> Self;
+
+    fn log10(self) -> Self;
+
+    fn cbrt(self) -> Self;
+
+    fn hypot(self, other: Self) -> Self;
+
+    fn sin(self) -> Self;
+
+    fn cos(self) -> Self;
+
+    fn tan(self) -> Self;
+
+    fn asin(self) -> Self;
+
+    fn acos(self) -> Self;
+
+    fn atan(self) -> Self;
+
+    fn atan2(self, other: Self) -> Self;
+
+    fn sin_cos(self) -> (Self, Self);
+
+    fn exp_m1(self) -> Self;
+
+    fn ln_1p(self) -> Self;
+
+    fn sinh(self) -> Self;
+
+    fn cosh(self) -> Self;
+
+    fn tanh(self) -> Self;
+
+    fn asinh(self) -> Self;
+
+    fn acosh(self) -> Self;
+
+    fn atanh(self) -> Self;
+
+    fn min(self, other: Self) -> Self;
+
+    fn max(self, other: Self) -> Self;
+}
+
+impl F64Ext for f64 {
+    #[inline]
+    fn floor(self) -> Self {
+        floor(self)
+    }
+
+    #[inline]
+    fn ceil(self) -> Self {
+        ceil(self)
+    }
+
+    #[inline]
+    fn round(self) -> Self {
+        round(self)
+    }
+
+    #[inline]
+    fn trunc(self) -> Self {
+        trunc(self)
+    }
+
+    #[inline]
+    fn fdim(self, rhs: Self) -> Self {
+        fdim(self, rhs)
+    }
+
+    #[inline]
+    fn fract(self) -> Self {
+        self - self.trunc()
+    }
+
+    #[inline]
+    fn abs(self) -> Self {
+        fabs(self)
+    }
+
+    #[inline]
+    fn mul_add(self, a: Self, b: Self) -> Self {
+        fma(self, a, b)
+    }
+
+    #[inline]
+    fn div_euc(self, rhs: Self) -> Self {
+        let q = (self / rhs).trunc();
+        if self % rhs < 0.0 {
+            return if rhs > 0.0 { q - 1.0 } else { q + 1.0 };
+        }
+        q
+    }
+
+    #[inline]
+    fn mod_euc(self, rhs: f64) -> f64 {
+        let r = self % rhs;
+        if r < 0.0 {
+            r + rhs.abs()
+        } else {
+            r
+        }
+    }
+
+    #[inline]
+    fn powf(self, n: Self) -> Self {
+        pow(self, n)
+    }
+
+    #[inline]
+    fn sqrt(self) -> Self {
+        sqrt(self)
+    }
+
+    #[inline]
+    fn exp(self) -> Self {
+        exp(self)
+    }
+
+    #[inline]
+    fn exp2(self) -> Self {
+        exp2(self)
+    }
+
+    #[inline]
+    fn ln(self) -> Self {
+        log(self)
+    }
+
+    #[inline]
+    fn log(self, base: Self) -> Self {
+        self.ln() / base.ln()
+    }
+
+    #[inline]
+    fn log2(self) -> Self {
+        log2(self)
+    }
+
+    #[inline]
+    fn log10(self) -> Self {
+        log10(self)
+    }
+
+    #[inline]
+    fn cbrt(self) -> Self {
+        cbrt(self)
+    }
+
+    #[inline]
+    fn hypot(self, other: Self) -> Self {
+        hypot(self, other)
+    }
+
+    #[inline]
+    fn sin(self) -> Self {
+        sin(self)
+    }
+
+    #[inline]
+    fn cos(self) -> Self {
+        cos(self)
+    }
+
+    #[inline]
+    fn tan(self) -> Self {
+        tan(self)
+    }
+
+    #[inline]
+    fn asin(self) -> Self {
+        asin(self)
+    }
+
+    #[inline]
+    fn acos(self) -> Self {
+        acos(self)
+    }
+
+    #[inline]
+    fn atan(self) -> Self {
+        atan(self)
+    }
+
+    #[inline]
+    fn atan2(self, other: Self) -> Self {
+        atan2(self, other)
+    }
+
+    #[inline]
+    fn sin_cos(self) -> (Self, Self) {
+        sincos(self)
+    }
+
+    #[inline]
+    fn exp_m1(self) -> Self {
+        expm1(self)
+    }
+
+    #[inline]
+    fn ln_1p(self) -> Self {
+        log1p(self)
+    }
+
+    #[inline]
+    fn sinh(self) -> Self {
+        sinh(self)
+    }
+
+    #[inline]
+    fn cosh(self) -> Self {
+        cosh(self)
+    }
+
+    #[inline]
+    fn tanh(self) -> Self {
+        tanh(self)
+    }
+
+    #[inline]
+    fn asinh(self) -> Self {
+        asinh(self)
+    }
+
+    #[inline]
+    fn acosh(self) -> Self {
+        acosh(self)
+    }
+
+    #[inline]
+    fn atanh(self) -> Self {
+        atanh(self)
+    }
+
+    #[inline]
+    fn min(self, other: Self) -> Self {
+        fmin(self, other)
+    }
+
+    #[inline]
+    fn max(self, other: Self) -> Self {
+        fmax(self, other)
+    }
+}
+
+mod private {
+    pub trait Sealed {}
+
+    impl Sealed for f32 {}
+    impl Sealed for f64 {}
+}
+
+#[cfg(all(test, feature = "musl-reference-tests"))]
+include!(concat!(env!("OUT_DIR"), "/musl-tests.rs"));
+
+
\ No newline at end of file diff --git a/src/libm/math/acos.rs.html b/src/libm/math/acos.rs.html new file mode 100644 index 000000000..9f9379d1d --- /dev/null +++ b/src/libm/math/acos.rs.html @@ -0,0 +1,231 @@ +acos.rs.html -- source
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+
+/* origin: FreeBSD /usr/src/lib/msun/src/e_acos.c */
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunSoft, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+/* acos(x)
+ * Method :
+ *      acos(x)  = pi/2 - asin(x)
+ *      acos(-x) = pi/2 + asin(x)
+ * For |x|<=0.5
+ *      acos(x) = pi/2 - (x + x*x^2*R(x^2))     (see asin.c)
+ * For x>0.5
+ *      acos(x) = pi/2 - (pi/2 - 2asin(sqrt((1-x)/2)))
+ *              = 2asin(sqrt((1-x)/2))
+ *              = 2s + 2s*z*R(z)        ...z=(1-x)/2, s=sqrt(z)
+ *              = 2f + (2c + 2s*z*R(z))
+ *     where f=hi part of s, and c = (z-f*f)/(s+f) is the correction term
+ *     for f so that f+c ~ sqrt(z).
+ * For x<-0.5
+ *      acos(x) = pi - 2asin(sqrt((1-|x|)/2))
+ *              = pi - 0.5*(s+s*z*R(z)), where z=(1-|x|)/2,s=sqrt(z)
+ *
+ * Special cases:
+ *      if x is NaN, return x itself;
+ *      if |x|>1, return NaN with invalid signal.
+ *
+ * Function needed: sqrt
+ */
+
+use super::sqrt;
+
+const PIO2_HI: f64 = 1.57079632679489655800e+00; /* 0x3FF921FB, 0x54442D18 */
+const PIO2_LO: f64 = 6.12323399573676603587e-17; /* 0x3C91A626, 0x33145C07 */
+const PS0: f64 = 1.66666666666666657415e-01; /* 0x3FC55555, 0x55555555 */
+const PS1: f64 = -3.25565818622400915405e-01; /* 0xBFD4D612, 0x03EB6F7D */
+const PS2: f64 = 2.01212532134862925881e-01; /* 0x3FC9C155, 0x0E884455 */
+const PS3: f64 = -4.00555345006794114027e-02; /* 0xBFA48228, 0xB5688F3B */
+const PS4: f64 = 7.91534994289814532176e-04; /* 0x3F49EFE0, 0x7501B288 */
+const PS5: f64 = 3.47933107596021167570e-05; /* 0x3F023DE1, 0x0DFDF709 */
+const QS1: f64 = -2.40339491173441421878e+00; /* 0xC0033A27, 0x1C8A2D4B */
+const QS2: f64 = 2.02094576023350569471e+00; /* 0x40002AE5, 0x9C598AC8 */
+const QS3: f64 = -6.88283971605453293030e-01; /* 0xBFE6066C, 0x1B8D0159 */
+const QS4: f64 = 7.70381505559019352791e-02; /* 0x3FB3B8C5, 0xB12E9282 */
+
+#[inline]
+fn r(z: f64) -> f64 {
+    let p: f64 = z * (PS0 + z * (PS1 + z * (PS2 + z * (PS3 + z * (PS4 + z * PS5)))));
+    let q: f64 = 1.0 + z * (QS1 + z * (QS2 + z * (QS3 + z * QS4)));
+    p / q
+}
+
+/// Arccosine (f64)
+///
+/// Computes the inverse cosine (arc cosine) of the input value.
+/// Arguments must be in the range -1 to 1.
+/// Returns values in radians, in the range of 0 to pi.
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn acos(x: f64) -> f64 {
+    let x1p_120f = f64::from_bits(0x3870000000000000); // 0x1p-120 === 2 ^ -120
+    let z: f64;
+    let w: f64;
+    let s: f64;
+    let c: f64;
+    let df: f64;
+    let hx: u32;
+    let ix: u32;
+
+    hx = (x.to_bits() >> 32) as u32;
+    ix = hx & 0x7fffffff;
+    /* |x| >= 1 or nan */
+    if ix >= 0x3ff00000 {
+        let lx: u32 = x.to_bits() as u32;
+
+        if ((ix - 0x3ff00000) | lx) == 0 {
+            /* acos(1)=0, acos(-1)=pi */
+            if (hx >> 31) != 0 {
+                return 2. * PIO2_HI + x1p_120f;
+            }
+            return 0.;
+        }
+        return 0. / (x - x);
+    }
+    /* |x| < 0.5 */
+    if ix < 0x3fe00000 {
+        if ix <= 0x3c600000 {
+            /* |x| < 2**-57 */
+            return PIO2_HI + x1p_120f;
+        }
+        return PIO2_HI - (x - (PIO2_LO - x * r(x * x)));
+    }
+    /* x < -0.5 */
+    if (hx >> 31) != 0 {
+        z = (1.0 + x) * 0.5;
+        s = sqrt(z);
+        w = r(z) * s - PIO2_LO;
+        return 2. * (PIO2_HI - (s + w));
+    }
+    /* x > 0.5 */
+    z = (1.0 - x) * 0.5;
+    s = sqrt(z);
+    // Set the low 4 bytes to zero
+    df = f64::from_bits(s.to_bits() & 0xff_ff_ff_ff_00_00_00_00);
+
+    c = (z - df * df) / (s + df);
+    w = r(z) * s + c;
+    2. * (df + w)
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/acosf.rs.html b/src/libm/math/acosf.rs.html new file mode 100644 index 000000000..75a3e632f --- /dev/null +++ b/src/libm/math/acosf.rs.html @@ -0,0 +1,165 @@ +acosf.rs.html -- source
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+/* origin: FreeBSD /usr/src/lib/msun/src/e_acosf.c */
+/*
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+use super::sqrtf::sqrtf;
+
+const PIO2_HI: f32 = 1.5707962513e+00; /* 0x3fc90fda */
+const PIO2_LO: f32 = 7.5497894159e-08; /* 0x33a22168 */
+const P_S0: f32 = 1.6666586697e-01;
+const P_S1: f32 = -4.2743422091e-02;
+const P_S2: f32 = -8.6563630030e-03;
+const Q_S1: f32 = -7.0662963390e-01;
+
+#[inline]
+fn r(z: f32) -> f32 {
+    let p = z * (P_S0 + z * (P_S1 + z * P_S2));
+    let q = 1. + z * Q_S1;
+    p / q
+}
+
+/// Arccosine (f32)
+///
+/// Computes the inverse cosine (arc cosine) of the input value.
+/// Arguments must be in the range -1 to 1.
+/// Returns values in radians, in the range of 0 to pi.
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn acosf(x: f32) -> f32 {
+    let x1p_120 = f32::from_bits(0x03800000); // 0x1p-120 === 2 ^ (-120)
+
+    let z: f32;
+    let w: f32;
+    let s: f32;
+
+    let mut hx = x.to_bits();
+    let ix = hx & 0x7fffffff;
+    /* |x| >= 1 or nan */
+    if ix >= 0x3f800000 {
+        if ix == 0x3f800000 {
+            if (hx >> 31) != 0 {
+                return 2. * PIO2_HI + x1p_120;
+            }
+            return 0.;
+        }
+        return 0. / (x - x);
+    }
+    /* |x| < 0.5 */
+    if ix < 0x3f000000 {
+        if ix <= 0x32800000 {
+            /* |x| < 2**-26 */
+            return PIO2_HI + x1p_120;
+        }
+        return PIO2_HI - (x - (PIO2_LO - x * r(x * x)));
+    }
+    /* x < -0.5 */
+    if (hx >> 31) != 0 {
+        z = (1. + x) * 0.5;
+        s = sqrtf(z);
+        w = r(z) * s - PIO2_LO;
+        return 2. * (PIO2_HI - (s + w));
+    }
+    /* x > 0.5 */
+    z = (1. - x) * 0.5;
+    s = sqrtf(z);
+    hx = s.to_bits();
+    let df = f32::from_bits(hx & 0xfffff000);
+    let c = (z - df * df) / (s + df);
+    w = r(z) * s + c;
+    2. * (df + w)
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/acosh.rs.html b/src/libm/math/acosh.rs.html new file mode 100644 index 000000000..d0b27f065 --- /dev/null +++ b/src/libm/math/acosh.rs.html @@ -0,0 +1,55 @@ +acosh.rs.html -- source
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+use super::{log, log1p, sqrt};
+
+const LN2: f64 = 0.693147180559945309417232121458176568; /* 0x3fe62e42,  0xfefa39ef*/
+
+/// Inverse hyperbolic cosine (f64)
+///
+/// Calculates the inverse hyperbolic cosine of `x`.
+/// Is defined as `log(x + sqrt(x*x-1))`.
+/// `x` must be a number greater than or equal to 1.
+pub fn acosh(x: f64) -> f64 {
+    let u = x.to_bits();
+    let e = ((u >> 52) as usize) & 0x7ff;
+
+    /* x < 1 domain error is handled in the called functions */
+
+    if e < 0x3ff + 1 {
+        /* |x| < 2, up to 2ulp error in [1,1.125] */
+        return log1p(x - 1.0 + sqrt((x - 1.0) * (x - 1.0) + 2.0 * (x - 1.0)));
+    }
+    if e < 0x3ff + 26 {
+        /* |x| < 0x1p26 */
+        return log(2.0 * x - 1.0 / (x + sqrt(x * x - 1.0)));
+    }
+    /* |x| >= 0x1p26 or nan */
+    return log(x) + LN2;
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/acoshf.rs.html b/src/libm/math/acoshf.rs.html new file mode 100644 index 000000000..d30e3fd3a --- /dev/null +++ b/src/libm/math/acoshf.rs.html @@ -0,0 +1,53 @@ +acoshf.rs.html -- source
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+use super::{log1pf, logf, sqrtf};
+
+const LN2: f32 = 0.693147180559945309417232121458176568;
+
+/// Inverse hyperbolic cosine (f32)
+///
+/// Calculates the inverse hyperbolic cosine of `x`.
+/// Is defined as `log(x + sqrt(x*x-1))`.
+/// `x` must be a number greater than or equal to 1.
+pub fn acoshf(x: f32) -> f32 {
+    let u = x.to_bits();
+    let a = u & 0x7fffffff;
+
+    if a < 0x3f800000 + (1 << 23) {
+        /* |x| < 2, invalid if x < 1 or nan */
+        /* up to 2ulp error in [1,1.125] */
+        return log1pf(x - 1.0 + sqrtf((x - 1.0) * (x - 1.0) + 2.0 * (x - 1.0)));
+    }
+    if a < 0x3f800000 + (12 << 23) {
+        /* |x| < 0x1p12 */
+        return logf(2.0 * x - 1.0 / (x + sqrtf(x * x - 1.0)));
+    }
+    /* x >= 0x1p12 */
+    return logf(x) + LN2;
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/asin.rs.html b/src/libm/math/asin.rs.html new file mode 100644 index 000000000..38ecbf351 --- /dev/null +++ b/src/libm/math/asin.rs.html @@ -0,0 +1,245 @@ +asin.rs.html -- source
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+
+/* origin: FreeBSD /usr/src/lib/msun/src/e_asin.c */
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunSoft, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+/* asin(x)
+ * Method :
+ *      Since  asin(x) = x + x^3/6 + x^5*3/40 + x^7*15/336 + ...
+ *      we approximate asin(x) on [0,0.5] by
+ *              asin(x) = x + x*x^2*R(x^2)
+ *      where
+ *              R(x^2) is a rational approximation of (asin(x)-x)/x^3
+ *      and its remez error is bounded by
+ *              |(asin(x)-x)/x^3 - R(x^2)| < 2^(-58.75)
+ *
+ *      For x in [0.5,1]
+ *              asin(x) = pi/2-2*asin(sqrt((1-x)/2))
+ *      Let y = (1-x), z = y/2, s := sqrt(z), and pio2_hi+pio2_lo=pi/2;
+ *      then for x>0.98
+ *              asin(x) = pi/2 - 2*(s+s*z*R(z))
+ *                      = pio2_hi - (2*(s+s*z*R(z)) - pio2_lo)
+ *      For x<=0.98, let pio4_hi = pio2_hi/2, then
+ *              f = hi part of s;
+ *              c = sqrt(z) - f = (z-f*f)/(s+f)         ...f+c=sqrt(z)
+ *      and
+ *              asin(x) = pi/2 - 2*(s+s*z*R(z))
+ *                      = pio4_hi+(pio4-2s)-(2s*z*R(z)-pio2_lo)
+ *                      = pio4_hi+(pio4-2f)-(2s*z*R(z)-(pio2_lo+2c))
+ *
+ * Special cases:
+ *      if x is NaN, return x itself;
+ *      if |x|>1, return NaN with invalid signal.
+ *
+ */
+
+use super::{fabs, get_high_word, get_low_word, sqrt, with_set_low_word};
+
+const PIO2_HI: f64 = 1.57079632679489655800e+00; /* 0x3FF921FB, 0x54442D18 */
+const PIO2_LO: f64 = 6.12323399573676603587e-17; /* 0x3C91A626, 0x33145C07 */
+/* coefficients for R(x^2) */
+const P_S0: f64 = 1.66666666666666657415e-01; /* 0x3FC55555, 0x55555555 */
+const P_S1: f64 = -3.25565818622400915405e-01; /* 0xBFD4D612, 0x03EB6F7D */
+const P_S2: f64 = 2.01212532134862925881e-01; /* 0x3FC9C155, 0x0E884455 */
+const P_S3: f64 = -4.00555345006794114027e-02; /* 0xBFA48228, 0xB5688F3B */
+const P_S4: f64 = 7.91534994289814532176e-04; /* 0x3F49EFE0, 0x7501B288 */
+const P_S5: f64 = 3.47933107596021167570e-05; /* 0x3F023DE1, 0x0DFDF709 */
+const Q_S1: f64 = -2.40339491173441421878e+00; /* 0xC0033A27, 0x1C8A2D4B */
+const Q_S2: f64 = 2.02094576023350569471e+00; /* 0x40002AE5, 0x9C598AC8 */
+const Q_S3: f64 = -6.88283971605453293030e-01; /* 0xBFE6066C, 0x1B8D0159 */
+const Q_S4: f64 = 7.70381505559019352791e-02; /* 0x3FB3B8C5, 0xB12E9282 */
+
+#[inline]
+fn comp_r(z: f64) -> f64 {
+    let p = z * (P_S0 + z * (P_S1 + z * (P_S2 + z * (P_S3 + z * (P_S4 + z * P_S5)))));
+    let q = 1.0 + z * (Q_S1 + z * (Q_S2 + z * (Q_S3 + z * Q_S4)));
+    p / q
+}
+
+/// Arcsine (f64)
+///
+/// Computes the inverse sine (arc sine) of the argument `x`.
+/// Arguments to asin must be in the range -1 to 1.
+/// Returns values in radians, in the range of -pi/2 to pi/2.
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn asin(mut x: f64) -> f64 {
+    let z: f64;
+    let r: f64;
+    let s: f64;
+    let hx: u32;
+    let ix: u32;
+
+    hx = get_high_word(x);
+    ix = hx & 0x7fffffff;
+    /* |x| >= 1 or nan */
+    if ix >= 0x3ff00000 {
+        let lx: u32;
+        lx = get_low_word(x);
+        if ((ix - 0x3ff00000) | lx) == 0 {
+            /* asin(1) = +-pi/2 with inexact */
+            return x * PIO2_HI + f64::from_bits(0x3870000000000000);
+        } else {
+            return 0.0 / (x - x);
+        }
+    }
+    /* |x| < 0.5 */
+    if ix < 0x3fe00000 {
+        /* if 0x1p-1022 <= |x| < 0x1p-26, avoid raising underflow */
+        if ix < 0x3e500000 && ix >= 0x00100000 {
+            return x;
+        } else {
+            return x + x * comp_r(x * x);
+        }
+    }
+    /* 1 > |x| >= 0.5 */
+    z = (1.0 - fabs(x)) * 0.5;
+    s = sqrt(z);
+    r = comp_r(z);
+    if ix >= 0x3fef3333 {
+        /* if |x| > 0.975 */
+        x = PIO2_HI - (2. * (s + s * r) - PIO2_LO);
+    } else {
+        let f: f64;
+        let c: f64;
+        /* f+c = sqrt(z) */
+        f = with_set_low_word(s, 0);
+        c = (z - f * f) / (s + f);
+        x = 0.5 * PIO2_HI - (2.0 * s * r - (PIO2_LO - 2.0 * c) - (0.5 * PIO2_HI - 2.0 * f));
+    }
+    if hx >> 31 != 0 {
+        -x
+    } else {
+        x
+    }
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/asinf.rs.html b/src/libm/math/asinf.rs.html new file mode 100644 index 000000000..20c16337f --- /dev/null +++ b/src/libm/math/asinf.rs.html @@ -0,0 +1,151 @@ +asinf.rs.html -- source
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+/* origin: FreeBSD /usr/src/lib/msun/src/e_asinf.c */
+/*
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+use super::fabsf::fabsf;
+use super::sqrt::sqrt;
+
+const PIO2: f64 = 1.570796326794896558e+00;
+
+/* coefficients for R(x^2) */
+const P_S0: f32 = 1.6666586697e-01;
+const P_S1: f32 = -4.2743422091e-02;
+const P_S2: f32 = -8.6563630030e-03;
+const Q_S1: f32 = -7.0662963390e-01;
+
+#[inline]
+fn r(z: f32) -> f32 {
+    let p = z * (P_S0 + z * (P_S1 + z * P_S2));
+    let q = 1. + z * Q_S1;
+    p / q
+}
+
+/// Arcsine (f32)
+///
+/// Computes the inverse sine (arc sine) of the argument `x`.
+/// Arguments to asin must be in the range -1 to 1.
+/// Returns values in radians, in the range of -pi/2 to pi/2.
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn asinf(mut x: f32) -> f32 {
+    let x1p_120 = f64::from_bits(0x3870000000000000); // 0x1p-120 === 2 ^ (-120)
+
+    let hx = x.to_bits();
+    let ix = hx & 0x7fffffff;
+
+    if ix >= 0x3f800000 {
+        /* |x| >= 1 */
+        if ix == 0x3f800000 {
+            /* |x| == 1 */
+            return ((x as f64) * PIO2 + x1p_120) as f32; /* asin(+-1) = +-pi/2 with inexact */
+        }
+        return 0. / (x - x); /* asin(|x|>1) is NaN */
+    }
+
+    if ix < 0x3f000000 {
+        /* |x| < 0.5 */
+        /* if 0x1p-126 <= |x| < 0x1p-12, avoid raising underflow */
+        if (ix < 0x39800000) && (ix >= 0x00800000) {
+            return x;
+        }
+        return x + x * r(x * x);
+    }
+
+    /* 1 > |x| >= 0.5 */
+    let z = (1. - fabsf(x)) * 0.5;
+    let s = sqrt(z as f64);
+    x = (PIO2 - 2. * (s + s * (r(z) as f64))) as f32;
+    if (hx >> 31) != 0 {
+        -x
+    } else {
+        x
+    }
+}
+
+
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+use super::{log, log1p, sqrt};
+
+const LN2: f64 = 0.693147180559945309417232121458176568; /* 0x3fe62e42,  0xfefa39ef*/
+
+/* asinh(x) = sign(x)*log(|x|+sqrt(x*x+1)) ~= x - x^3/6 + o(x^5) */
+/// Inverse hyperbolic sine (f64)
+///
+/// Calculates the inverse hyperbolic sine of `x`.
+/// Is defined as `sgn(x)*log(|x|+sqrt(x*x+1))`.
+pub fn asinh(mut x: f64) -> f64 {
+    let mut u = x.to_bits();
+    let e = ((u >> 52) as usize) & 0x7ff;
+    let sign = (u >> 63) != 0;
+
+    /* |x| */
+    u &= (!0) >> 1;
+    x = f64::from_bits(u);
+
+    if e >= 0x3ff + 26 {
+        /* |x| >= 0x1p26 or inf or nan */
+        x = log(x) + LN2;
+    } else if e >= 0x3ff + 1 {
+        /* |x| >= 2 */
+        x = log(2.0 * x + 1.0 / (sqrt(x * x + 1.0) + x));
+    } else if e >= 0x3ff - 26 {
+        /* |x| >= 0x1p-26, up to 1.6ulp error in [0.125,0.5] */
+        x = log1p(x + x * x / (sqrt(x * x + 1.0) + 1.0));
+    } else {
+        /* |x| < 0x1p-26, raise inexact if x != 0 */
+        let x1p120 = f64::from_bits(0x4770000000000000);
+        force_eval!(x + x1p120);
+    }
+
+    if sign {
+        -x
+    } else {
+        x
+    }
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/asinhf.rs.html b/src/libm/math/asinhf.rs.html new file mode 100644 index 000000000..46d0dc729 --- /dev/null +++ b/src/libm/math/asinhf.rs.html @@ -0,0 +1,79 @@ +asinhf.rs.html -- source
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+use super::{log1pf, logf, sqrtf};
+
+const LN2: f32 = 0.693147180559945309417232121458176568;
+
+/* asinh(x) = sign(x)*log(|x|+sqrt(x*x+1)) ~= x - x^3/6 + o(x^5) */
+/// Inverse hyperbolic sine (f32)
+///
+/// Calculates the inverse hyperbolic sine of `x`.
+/// Is defined as `sgn(x)*log(|x|+sqrt(x*x+1))`.
+pub fn asinhf(mut x: f32) -> f32 {
+    let u = x.to_bits();
+    let i = u & 0x7fffffff;
+    let sign = (u >> 31) != 0;
+
+    /* |x| */
+    x = f32::from_bits(i);
+
+    if i >= 0x3f800000 + (12 << 23) {
+        /* |x| >= 0x1p12 or inf or nan */
+        x = logf(x) + LN2;
+    } else if i >= 0x3f800000 + (1 << 23) {
+        /* |x| >= 2 */
+        x = logf(2.0 * x + 1.0 / (sqrtf(x * x + 1.0) + x));
+    } else if i >= 0x3f800000 - (12 << 23) {
+        /* |x| >= 0x1p-12, up to 1.6ulp error in [0.125,0.5] */
+        x = log1pf(x + x * x / (sqrtf(x * x + 1.0) + 1.0));
+    } else {
+        /* |x| < 0x1p-12, raise inexact if x!=0 */
+        let x1p120 = f32::from_bits(0x7b800000);
+        force_eval!(x + x1p120);
+    }
+
+    if sign {
+        -x
+    } else {
+        x
+    }
+}
+
+
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+
+/* origin: FreeBSD /usr/src/lib/msun/src/s_atan.c */
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+/* atan(x)
+ * Method
+ *   1. Reduce x to positive by atan(x) = -atan(-x).
+ *   2. According to the integer k=4t+0.25 chopped, t=x, the argument
+ *      is further reduced to one of the following intervals and the
+ *      arctangent of t is evaluated by the corresponding formula:
+ *
+ *      [0,7/16]      atan(x) = t-t^3*(a1+t^2*(a2+...(a10+t^2*a11)...)
+ *      [7/16,11/16]  atan(x) = atan(1/2) + atan( (t-0.5)/(1+t/2) )
+ *      [11/16.19/16] atan(x) = atan( 1 ) + atan( (t-1)/(1+t) )
+ *      [19/16,39/16] atan(x) = atan(3/2) + atan( (t-1.5)/(1+1.5t) )
+ *      [39/16,INF]   atan(x) = atan(INF) + atan( -1/t )
+ *
+ * Constants:
+ * The hexadecimal values are the intended ones for the following
+ * constants. The decimal values may be used, provided that the
+ * compiler will convert from decimal to binary accurately enough
+ * to produce the hexadecimal values shown.
+ */
+
+use super::fabs;
+use core::f64;
+
+const ATANHI: [f64; 4] = [
+    4.63647609000806093515e-01, /* atan(0.5)hi 0x3FDDAC67, 0x0561BB4F */
+    7.85398163397448278999e-01, /* atan(1.0)hi 0x3FE921FB, 0x54442D18 */
+    9.82793723247329054082e-01, /* atan(1.5)hi 0x3FEF730B, 0xD281F69B */
+    1.57079632679489655800e+00, /* atan(inf)hi 0x3FF921FB, 0x54442D18 */
+];
+
+const ATANLO: [f64; 4] = [
+    2.26987774529616870924e-17, /* atan(0.5)lo 0x3C7A2B7F, 0x222F65E2 */
+    3.06161699786838301793e-17, /* atan(1.0)lo 0x3C81A626, 0x33145C07 */
+    1.39033110312309984516e-17, /* atan(1.5)lo 0x3C700788, 0x7AF0CBBD */
+    6.12323399573676603587e-17, /* atan(inf)lo 0x3C91A626, 0x33145C07 */
+];
+
+const AT: [f64; 11] = [
+    3.33333333333329318027e-01,  /* 0x3FD55555, 0x5555550D */
+    -1.99999999998764832476e-01, /* 0xBFC99999, 0x9998EBC4 */
+    1.42857142725034663711e-01,  /* 0x3FC24924, 0x920083FF */
+    -1.11111104054623557880e-01, /* 0xBFBC71C6, 0xFE231671 */
+    9.09088713343650656196e-02,  /* 0x3FB745CD, 0xC54C206E */
+    -7.69187620504482999495e-02, /* 0xBFB3B0F2, 0xAF749A6D */
+    6.66107313738753120669e-02,  /* 0x3FB10D66, 0xA0D03D51 */
+    -5.83357013379057348645e-02, /* 0xBFADDE2D, 0x52DEFD9A */
+    4.97687799461593236017e-02,  /* 0x3FA97B4B, 0x24760DEB */
+    -3.65315727442169155270e-02, /* 0xBFA2B444, 0x2C6A6C2F */
+    1.62858201153657823623e-02,  /* 0x3F90AD3A, 0xE322DA11 */
+];
+
+/// Arctangent (f64)
+///
+/// Computes the inverse tangent (arc tangent) of the input value.
+/// Returns a value in radians, in the range of -pi/2 to pi/2.
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn atan(x: f64) -> f64 {
+    let mut x = x;
+    let mut ix = (x.to_bits() >> 32) as u32;
+    let sign = ix >> 31;
+    ix &= 0x7fff_ffff;
+    if ix >= 0x4410_0000 {
+        if x.is_nan() {
+            return x;
+        }
+
+        let z = ATANHI[3] + f64::from_bits(0x0380_0000); // 0x1p-120f
+        return if sign != 0 { -z } else { z };
+    }
+
+    let id = if ix < 0x3fdc_0000 {
+        /* |x| < 0.4375 */
+        if ix < 0x3e40_0000 {
+            /* |x| < 2^-27 */
+            if ix < 0x0010_0000 {
+                /* raise underflow for subnormal x */
+                force_eval!(x as f32);
+            }
+
+            return x;
+        }
+
+        -1
+    } else {
+        x = fabs(x);
+        if ix < 0x3ff30000 {
+            /* |x| < 1.1875 */
+            if ix < 0x3fe60000 {
+                /* 7/16 <= |x| < 11/16 */
+                x = (2. * x - 1.) / (2. + x);
+                0
+            } else {
+                /* 11/16 <= |x| < 19/16 */
+                x = (x - 1.) / (x + 1.);
+                1
+            }
+        } else if ix < 0x40038000 {
+            /* |x| < 2.4375 */
+            x = (x - 1.5) / (1. + 1.5 * x);
+            2
+        } else {
+            /* 2.4375 <= |x| < 2^66 */
+            x = -1. / x;
+            3
+        }
+    };
+
+    let z = x * x;
+    let w = z * z;
+    /* break sum from i=0 to 10 AT[i]z**(i+1) into odd and even poly */
+    let s1 = z * (AT[0] + w * (AT[2] + w * (AT[4] + w * (AT[6] + w * (AT[8] + w * AT[10])))));
+    let s2 = w * (AT[1] + w * (AT[3] + w * (AT[5] + w * (AT[7] + w * AT[9]))));
+
+    if id < 0 {
+        return x - x * (s1 + s2);
+    }
+
+    let z = i!(ATANHI, id as usize) - (x * (s1 + s2) - i!(ATANLO, id as usize) - x);
+
+    if sign != 0 {
+        -z
+    } else {
+        z
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use super::atan;
+    use core::f64;
+
+    #[test]
+    fn sanity_check() {
+        for (input, answer) in [
+            (3.0_f64.sqrt() / 3.0, f64::consts::FRAC_PI_6),
+            (1.0, f64::consts::FRAC_PI_4),
+            (3.0_f64.sqrt(), f64::consts::FRAC_PI_3),
+            (-3.0_f64.sqrt() / 3.0, -f64::consts::FRAC_PI_6),
+            (-1.0, -f64::consts::FRAC_PI_4),
+            (-3.0_f64.sqrt(), -f64::consts::FRAC_PI_3),
+        ]
+        .iter()
+        {
+            assert!(
+                (atan(*input) - answer) / answer < 1e-5,
+                "\natan({:.4}/16) = {:.4}, actual: {}",
+                input * 16.0,
+                answer,
+                atan(*input)
+            );
+        }
+    }
+
+    #[test]
+    fn zero() {
+        assert_eq!(atan(0.0), 0.0);
+    }
+
+    #[test]
+    fn infinity() {
+        assert_eq!(atan(f64::INFINITY), f64::consts::FRAC_PI_2);
+    }
+
+    #[test]
+    fn minus_infinity() {
+        assert_eq!(atan(f64::NEG_INFINITY), -f64::consts::FRAC_PI_2);
+    }
+
+    #[test]
+    fn nan() {
+        assert!(atan(f64::NAN).is_nan());
+    }
+}
+
+
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+
+/* origin: FreeBSD /usr/src/lib/msun/src/e_atan2.c */
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunSoft, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ *
+ */
+/* atan2(y,x)
+ * Method :
+ *      1. Reduce y to positive by atan2(y,x)=-atan2(-y,x).
+ *      2. Reduce x to positive by (if x and y are unexceptional):
+ *              ARG (x+iy) = arctan(y/x)           ... if x > 0,
+ *              ARG (x+iy) = pi - arctan[y/(-x)]   ... if x < 0,
+ *
+ * Special cases:
+ *
+ *      ATAN2((anything), NaN ) is NaN;
+ *      ATAN2(NAN , (anything) ) is NaN;
+ *      ATAN2(+-0, +(anything but NaN)) is +-0  ;
+ *      ATAN2(+-0, -(anything but NaN)) is +-pi ;
+ *      ATAN2(+-(anything but 0 and NaN), 0) is +-pi/2;
+ *      ATAN2(+-(anything but INF and NaN), +INF) is +-0 ;
+ *      ATAN2(+-(anything but INF and NaN), -INF) is +-pi;
+ *      ATAN2(+-INF,+INF ) is +-pi/4 ;
+ *      ATAN2(+-INF,-INF ) is +-3pi/4;
+ *      ATAN2(+-INF, (anything but,0,NaN, and INF)) is +-pi/2;
+ *
+ * Constants:
+ * The hexadecimal values are the intended ones for the following
+ * constants. The decimal values may be used, provided that the
+ * compiler will convert from decimal to binary accurately enough
+ * to produce the hexadecimal values shown.
+ */
+
+use super::atan;
+use super::fabs;
+
+const PI: f64 = 3.1415926535897931160E+00; /* 0x400921FB, 0x54442D18 */
+const PI_LO: f64 = 1.2246467991473531772E-16; /* 0x3CA1A626, 0x33145C07 */
+
+/// Arctangent of y/x (f64)
+///
+/// Computes the inverse tangent (arc tangent) of `y/x`.
+/// Produces the correct result even for angles near pi/2 or -pi/2 (that is, when `x` is near 0).
+/// Returns a value in radians, in the range of -pi to pi.
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn atan2(y: f64, x: f64) -> f64 {
+    if x.is_nan() || y.is_nan() {
+        return x + y;
+    }
+    let mut ix = (x.to_bits() >> 32) as u32;
+    let lx = x.to_bits() as u32;
+    let mut iy = (y.to_bits() >> 32) as u32;
+    let ly = y.to_bits() as u32;
+    if ((ix.wrapping_sub(0x3ff00000)) | lx) == 0 {
+        /* x = 1.0 */
+        return atan(y);
+    }
+    let m = ((iy >> 31) & 1) | ((ix >> 30) & 2); /* 2*sign(x)+sign(y) */
+    ix &= 0x7fffffff;
+    iy &= 0x7fffffff;
+
+    /* when y = 0 */
+    if (iy | ly) == 0 {
+        return match m {
+            0 | 1 => y, /* atan(+-0,+anything)=+-0 */
+            2 => PI,    /* atan(+0,-anything) = PI */
+            _ => -PI,   /* atan(-0,-anything) =-PI */
+        };
+    }
+    /* when x = 0 */
+    if (ix | lx) == 0 {
+        return if m & 1 != 0 { -PI / 2.0 } else { PI / 2.0 };
+    }
+    /* when x is INF */
+    if ix == 0x7ff00000 {
+        if iy == 0x7ff00000 {
+            return match m {
+                0 => PI / 4.0,        /* atan(+INF,+INF) */
+                1 => -PI / 4.0,       /* atan(-INF,+INF) */
+                2 => 3.0 * PI / 4.0,  /* atan(+INF,-INF) */
+                _ => -3.0 * PI / 4.0, /* atan(-INF,-INF) */
+            };
+        } else {
+            return match m {
+                0 => 0.0,  /* atan(+...,+INF) */
+                1 => -0.0, /* atan(-...,+INF) */
+                2 => PI,   /* atan(+...,-INF) */
+                _ => -PI,  /* atan(-...,-INF) */
+            };
+        }
+    }
+    /* |y/x| > 0x1p64 */
+    if ix.wrapping_add(64 << 20) < iy || iy == 0x7ff00000 {
+        return if m & 1 != 0 { -PI / 2.0 } else { PI / 2.0 };
+    }
+
+    /* z = atan(|y/x|) without spurious underflow */
+    let z = if (m & 2 != 0) && iy.wrapping_add(64 << 20) < ix {
+        /* |y/x| < 0x1p-64, x<0 */
+        0.0
+    } else {
+        atan(fabs(y / x))
+    };
+    match m {
+        0 => z,                /* atan(+,+) */
+        1 => -z,               /* atan(-,+) */
+        2 => PI - (z - PI_LO), /* atan(+,-) */
+        _ => (z - PI_LO) - PI, /* atan(-,-) */
+    }
+}
+
+#[test]
+fn sanity_check() {
+    assert_eq!(atan2(0.0, 1.0), 0.0);
+    assert_eq!(atan2(0.0, -1.0), PI);
+    assert_eq!(atan2(-0.0, -1.0), -PI);
+    assert_eq!(atan2(3.0, 2.0), atan(3.0 / 2.0));
+    assert_eq!(atan2(2.0, -1.0), atan(2.0 / -1.0) + PI);
+    assert_eq!(atan2(-2.0, -1.0), atan(-2.0 / -1.0) - PI);
+}
+
+
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+/* origin: FreeBSD /usr/src/lib/msun/src/e_atan2f.c */
+/*
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+use super::atanf;
+use super::fabsf;
+
+const PI: f32 = 3.1415927410e+00; /* 0x40490fdb */
+const PI_LO: f32 = -8.7422776573e-08; /* 0xb3bbbd2e */
+
+/// Arctangent of y/x (f32)
+///
+/// Computes the inverse tangent (arc tangent) of `y/x`.
+/// Produces the correct result even for angles near pi/2 or -pi/2 (that is, when `x` is near 0).
+/// Returns a value in radians, in the range of -pi to pi.
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn atan2f(y: f32, x: f32) -> f32 {
+    if x.is_nan() || y.is_nan() {
+        return x + y;
+    }
+    let mut ix = x.to_bits();
+    let mut iy = y.to_bits();
+
+    if ix == 0x3f800000 {
+        /* x=1.0 */
+        return atanf(y);
+    }
+    let m = ((iy >> 31) & 1) | ((ix >> 30) & 2); /* 2*sign(x)+sign(y) */
+    ix &= 0x7fffffff;
+    iy &= 0x7fffffff;
+
+    /* when y = 0 */
+    if iy == 0 {
+        return match m {
+            0 | 1 => y,   /* atan(+-0,+anything)=+-0 */
+            2 => PI,      /* atan(+0,-anything) = pi */
+            3 | _ => -PI, /* atan(-0,-anything) =-pi */
+        };
+    }
+    /* when x = 0 */
+    if ix == 0 {
+        return if m & 1 != 0 { -PI / 2. } else { PI / 2. };
+    }
+    /* when x is INF */
+    if ix == 0x7f800000 {
+        return if iy == 0x7f800000 {
+            match m {
+                0 => PI / 4.,           /* atan(+INF,+INF) */
+                1 => -PI / 4.,          /* atan(-INF,+INF) */
+                2 => 3. * PI / 4.,      /* atan(+INF,-INF)*/
+                3 | _ => -3. * PI / 4., /* atan(-INF,-INF)*/
+            }
+        } else {
+            match m {
+                0 => 0.,      /* atan(+...,+INF) */
+                1 => -0.,     /* atan(-...,+INF) */
+                2 => PI,      /* atan(+...,-INF) */
+                3 | _ => -PI, /* atan(-...,-INF) */
+            }
+        };
+    }
+    /* |y/x| > 0x1p26 */
+    if (ix + (26 << 23) < iy) || (iy == 0x7f800000) {
+        return if m & 1 != 0 { -PI / 2. } else { PI / 2. };
+    }
+
+    /* z = atan(|y/x|) with correct underflow */
+    let z = if (m & 2 != 0) && (iy + (26 << 23) < ix) {
+        /*|y/x| < 0x1p-26, x < 0 */
+        0.
+    } else {
+        atanf(fabsf(y / x))
+    };
+    match m {
+        0 => z,                /* atan(+,+) */
+        1 => -z,               /* atan(-,+) */
+        2 => PI - (z - PI_LO), /* atan(+,-) */
+        _ => (z - PI_LO) - PI, /* case 3 */ /* atan(-,-) */
+    }
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/atanf.rs.html b/src/libm/math/atanf.rs.html new file mode 100644 index 000000000..f8c6b6f26 --- /dev/null +++ b/src/libm/math/atanf.rs.html @@ -0,0 +1,229 @@ +atanf.rs.html -- source
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+/* origin: FreeBSD /usr/src/lib/msun/src/s_atanf.c */
+/*
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+use super::fabsf;
+
+const ATAN_HI: [f32; 4] = [
+    4.6364760399e-01, /* atan(0.5)hi 0x3eed6338 */
+    7.8539812565e-01, /* atan(1.0)hi 0x3f490fda */
+    9.8279368877e-01, /* atan(1.5)hi 0x3f7b985e */
+    1.5707962513e+00, /* atan(inf)hi 0x3fc90fda */
+];
+
+const ATAN_LO: [f32; 4] = [
+    5.0121582440e-09, /* atan(0.5)lo 0x31ac3769 */
+    3.7748947079e-08, /* atan(1.0)lo 0x33222168 */
+    3.4473217170e-08, /* atan(1.5)lo 0x33140fb4 */
+    7.5497894159e-08, /* atan(inf)lo 0x33a22168 */
+];
+
+const A_T: [f32; 5] = [
+    3.3333328366e-01,
+    -1.9999158382e-01,
+    1.4253635705e-01,
+    -1.0648017377e-01,
+    6.1687607318e-02,
+];
+
+/// Arctangent (f32)
+///
+/// Computes the inverse tangent (arc tangent) of the input value.
+/// Returns a value in radians, in the range of -pi/2 to pi/2.
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn atanf(mut x: f32) -> f32 {
+    let x1p_120 = f32::from_bits(0x03800000); // 0x1p-120 === 2 ^ (-120)
+
+    let z: f32;
+
+    let mut ix = x.to_bits();
+    let sign = (ix >> 31) != 0;
+    ix &= 0x7fffffff;
+
+    if ix >= 0x4c800000 {
+        /* if |x| >= 2**26 */
+        if x.is_nan() {
+            return x;
+        }
+        z = ATAN_HI[3] + x1p_120;
+        return if sign { -z } else { z };
+    }
+    let id = if ix < 0x3ee00000 {
+        /* |x| < 0.4375 */
+        if ix < 0x39800000 {
+            /* |x| < 2**-12 */
+            if ix < 0x00800000 {
+                /* raise underflow for subnormal x */
+                force_eval!(x * x);
+            }
+            return x;
+        }
+        -1
+    } else {
+        x = fabsf(x);
+        if ix < 0x3f980000 {
+            /* |x| < 1.1875 */
+            if ix < 0x3f300000 {
+                /*  7/16 <= |x| < 11/16 */
+                x = (2. * x - 1.) / (2. + x);
+                0
+            } else {
+                /* 11/16 <= |x| < 19/16 */
+                x = (x - 1.) / (x + 1.);
+                1
+            }
+        } else if ix < 0x401c0000 {
+            /* |x| < 2.4375 */
+            x = (x - 1.5) / (1. + 1.5 * x);
+            2
+        } else {
+            /* 2.4375 <= |x| < 2**26 */
+            x = -1. / x;
+            3
+        }
+    };
+    /* end of argument reduction */
+    z = x * x;
+    let w = z * z;
+    /* break sum from i=0 to 10 aT[i]z**(i+1) into odd and even poly */
+    let s1 = z * (A_T[0] + w * (A_T[2] + w * A_T[4]));
+    let s2 = w * (A_T[1] + w * A_T[3]);
+    if id < 0 {
+        return x - x * (s1 + s2);
+    }
+    let id = id as usize;
+    let z = ATAN_HI[id] - ((x * (s1 + s2) - ATAN_LO[id]) - x);
+    if sign {
+        -z
+    } else {
+        z
+    }
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/atanh.rs.html b/src/libm/math/atanh.rs.html new file mode 100644 index 000000000..6839bf01b --- /dev/null +++ b/src/libm/math/atanh.rs.html @@ -0,0 +1,75 @@ +atanh.rs.html -- source
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+use super::log1p;
+
+/* atanh(x) = log((1+x)/(1-x))/2 = log1p(2x/(1-x))/2 ~= x + x^3/3 + o(x^5) */
+/// Inverse hyperbolic tangent (f64)
+///
+/// Calculates the inverse hyperbolic tangent of `x`.
+/// Is defined as `log((1+x)/(1-x))/2 = log1p(2x/(1-x))/2`.
+pub fn atanh(x: f64) -> f64 {
+    let u = x.to_bits();
+    let e = ((u >> 52) as usize) & 0x7ff;
+    let sign = (u >> 63) != 0;
+
+    /* |x| */
+    let mut y = f64::from_bits(u & 0x7fff_ffff_ffff_ffff);
+
+    if e < 0x3ff - 1 {
+        if e < 0x3ff - 32 {
+            /* handle underflow */
+            if e == 0 {
+                force_eval!(y as f32);
+            }
+        } else {
+            /* |x| < 0.5, up to 1.7ulp error */
+            y = 0.5 * log1p(2.0 * y + 2.0 * y * y / (1.0 - y));
+        }
+    } else {
+        /* avoid overflow */
+        y = 0.5 * log1p(2.0 * (y / (1.0 - y)));
+    }
+
+    if sign {
+        -y
+    } else {
+        y
+    }
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/atanhf.rs.html b/src/libm/math/atanhf.rs.html new file mode 100644 index 000000000..b7516ae46 --- /dev/null +++ b/src/libm/math/atanhf.rs.html @@ -0,0 +1,75 @@ +atanhf.rs.html -- source
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+use super::log1pf;
+
+/* atanh(x) = log((1+x)/(1-x))/2 = log1p(2x/(1-x))/2 ~= x + x^3/3 + o(x^5) */
+/// Inverse hyperbolic tangent (f32)
+///
+/// Calculates the inverse hyperbolic tangent of `x`.
+/// Is defined as `log((1+x)/(1-x))/2 = log1p(2x/(1-x))/2`.
+pub fn atanhf(mut x: f32) -> f32 {
+    let mut u = x.to_bits();
+    let sign = (u >> 31) != 0;
+
+    /* |x| */
+    u &= 0x7fffffff;
+    x = f32::from_bits(u);
+
+    if u < 0x3f800000 - (1 << 23) {
+        if u < 0x3f800000 - (32 << 23) {
+            /* handle underflow */
+            if u < (1 << 23) {
+                force_eval!((x * x) as f32);
+            }
+        } else {
+            /* |x| < 0.5, up to 1.7ulp error */
+            x = 0.5 * log1pf(2.0 * x + 2.0 * x * x / (1.0 - x));
+        }
+    } else {
+        /* avoid overflow */
+        x = 0.5 * log1pf(2.0 * (x / (1.0 - x)));
+    }
+
+    if sign {
+        -x
+    } else {
+        x
+    }
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/cbrt.rs.html b/src/libm/math/cbrt.rs.html new file mode 100644 index 000000000..a40bcfc47 --- /dev/null +++ b/src/libm/math/cbrt.rs.html @@ -0,0 +1,231 @@ +cbrt.rs.html -- source
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+
+/* origin: FreeBSD /usr/src/lib/msun/src/s_cbrt.c */
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ *
+ * Optimized by Bruce D. Evans.
+ */
+/* cbrt(x)
+ * Return cube root of x
+ */
+
+use core::f64;
+
+const B1: u32 = 715094163; /* B1 = (1023-1023/3-0.03306235651)*2**20 */
+const B2: u32 = 696219795; /* B2 = (1023-1023/3-54/3-0.03306235651)*2**20 */
+
+/* |1/cbrt(x) - p(x)| < 2**-23.5 (~[-7.93e-8, 7.929e-8]). */
+const P0: f64 = 1.87595182427177009643; /* 0x3ffe03e6, 0x0f61e692 */
+const P1: f64 = -1.88497979543377169875; /* 0xbffe28e0, 0x92f02420 */
+const P2: f64 = 1.621429720105354466140; /* 0x3ff9f160, 0x4a49d6c2 */
+const P3: f64 = -0.758397934778766047437; /* 0xbfe844cb, 0xbee751d9 */
+const P4: f64 = 0.145996192886612446982; /* 0x3fc2b000, 0xd4e4edd7 */
+
+// Cube root (f64)
+///
+/// Computes the cube root of the argument.
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn cbrt(x: f64) -> f64 {
+    let x1p54 = f64::from_bits(0x4350000000000000); // 0x1p54 === 2 ^ 54
+
+    let mut ui: u64 = x.to_bits();
+    let mut r: f64;
+    let s: f64;
+    let mut t: f64;
+    let w: f64;
+    let mut hx: u32 = (ui >> 32) as u32 & 0x7fffffff;
+
+    if hx >= 0x7ff00000 {
+        /* cbrt(NaN,INF) is itself */
+        return x + x;
+    }
+
+    /*
+     * Rough cbrt to 5 bits:
+     *    cbrt(2**e*(1+m) ~= 2**(e/3)*(1+(e%3+m)/3)
+     * where e is integral and >= 0, m is real and in [0, 1), and "/" and
+     * "%" are integer division and modulus with rounding towards minus
+     * infinity.  The RHS is always >= the LHS and has a maximum relative
+     * error of about 1 in 16.  Adding a bias of -0.03306235651 to the
+     * (e%3+m)/3 term reduces the error to about 1 in 32. With the IEEE
+     * floating point representation, for finite positive normal values,
+     * ordinary integer divison of the value in bits magically gives
+     * almost exactly the RHS of the above provided we first subtract the
+     * exponent bias (1023 for doubles) and later add it back.  We do the
+     * subtraction virtually to keep e >= 0 so that ordinary integer
+     * division rounds towards minus infinity; this is also efficient.
+     */
+    if hx < 0x00100000 {
+        /* zero or subnormal? */
+        ui = (x * x1p54).to_bits();
+        hx = (ui >> 32) as u32 & 0x7fffffff;
+        if hx == 0 {
+            return x; /* cbrt(0) is itself */
+        }
+        hx = hx / 3 + B2;
+    } else {
+        hx = hx / 3 + B1;
+    }
+    ui &= 1 << 63;
+    ui |= (hx as u64) << 32;
+    t = f64::from_bits(ui);
+
+    /*
+     * New cbrt to 23 bits:
+     *    cbrt(x) = t*cbrt(x/t**3) ~= t*P(t**3/x)
+     * where P(r) is a polynomial of degree 4 that approximates 1/cbrt(r)
+     * to within 2**-23.5 when |r - 1| < 1/10.  The rough approximation
+     * has produced t such than |t/cbrt(x) - 1| ~< 1/32, and cubing this
+     * gives us bounds for r = t**3/x.
+     *
+     * Try to optimize for parallel evaluation as in __tanf.c.
+     */
+    r = (t * t) * (t / x);
+    t = t * ((P0 + r * (P1 + r * P2)) + ((r * r) * r) * (P3 + r * P4));
+
+    /*
+     * Round t away from zero to 23 bits (sloppily except for ensuring that
+     * the result is larger in magnitude than cbrt(x) but not much more than
+     * 2 23-bit ulps larger).  With rounding towards zero, the error bound
+     * would be ~5/6 instead of ~4/6.  With a maximum error of 2 23-bit ulps
+     * in the rounded t, the infinite-precision error in the Newton
+     * approximation barely affects third digit in the final error
+     * 0.667; the error in the rounded t can be up to about 3 23-bit ulps
+     * before the final error is larger than 0.667 ulps.
+     */
+    ui = t.to_bits();
+    ui = (ui + 0x80000000) & 0xffffffffc0000000;
+    t = f64::from_bits(ui);
+
+    /* one step Newton iteration to 53 bits with error < 0.667 ulps */
+    s = t * t; /* t*t is exact */
+    r = x / s; /* error <= 0.5 ulps; |r| < |t| */
+    w = t + t; /* t+t is exact */
+    r = (r - t) / (w + r); /* r-t is exact; w+r ~= 3*t */
+    t = t + t * r; /* error <= 0.5 + 0.5/3 + epsilon */
+    t
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/cbrtf.rs.html b/src/libm/math/cbrtf.rs.html new file mode 100644 index 000000000..9e828af05 --- /dev/null +++ b/src/libm/math/cbrtf.rs.html @@ -0,0 +1,155 @@ +cbrtf.rs.html -- source
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+/* origin: FreeBSD /usr/src/lib/msun/src/s_cbrtf.c */
+/*
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ * Debugged and optimized by Bruce D. Evans.
+ */
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+/* cbrtf(x)
+ * Return cube root of x
+ */
+
+use core::f32;
+
+const B1: u32 = 709958130; /* B1 = (127-127.0/3-0.03306235651)*2**23 */
+const B2: u32 = 642849266; /* B2 = (127-127.0/3-24/3-0.03306235651)*2**23 */
+
+/// Cube root (f32)
+///
+/// Computes the cube root of the argument.
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn cbrtf(x: f32) -> f32 {
+    let x1p24 = f32::from_bits(0x4b800000); // 0x1p24f === 2 ^ 24
+
+    let mut r: f64;
+    let mut t: f64;
+    let mut ui: u32 = x.to_bits();
+    let mut hx: u32 = ui & 0x7fffffff;
+
+    if hx >= 0x7f800000 {
+        /* cbrt(NaN,INF) is itself */
+        return x + x;
+    }
+
+    /* rough cbrt to 5 bits */
+    if hx < 0x00800000 {
+        /* zero or subnormal? */
+        if hx == 0 {
+            return x; /* cbrt(+-0) is itself */
+        }
+        ui = (x * x1p24).to_bits();
+        hx = ui & 0x7fffffff;
+        hx = hx / 3 + B2;
+    } else {
+        hx = hx / 3 + B1;
+    }
+    ui &= 0x80000000;
+    ui |= hx;
+
+    /*
+     * First step Newton iteration (solving t*t-x/t == 0) to 16 bits.  In
+     * double precision so that its terms can be arranged for efficiency
+     * without causing overflow or underflow.
+     */
+    t = f32::from_bits(ui) as f64;
+    r = t * t * t;
+    t = t * (x as f64 + x as f64 + r) / (x as f64 + r + r);
+
+    /*
+     * Second step Newton iteration to 47 bits.  In double precision for
+     * efficiency and accuracy.
+     */
+    r = t * t * t;
+    t = t * (x as f64 + x as f64 + r) / (x as f64 + r + r);
+
+    /* rounding to 24 bits is perfect in round-to-nearest mode */
+    t as f32
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/ceil.rs.html b/src/libm/math/ceil.rs.html new file mode 100644 index 000000000..1402f7638 --- /dev/null +++ b/src/libm/math/ceil.rs.html @@ -0,0 +1,105 @@ +ceil.rs.html -- source
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+use core::f64;
+
+const TOINT: f64 = 1. / f64::EPSILON;
+
+/// Ceil (f64)
+///
+/// Finds the nearest integer greater than or equal to `x`.
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn ceil(x: f64) -> f64 {
+    // On wasm32 we know that LLVM's intrinsic will compile to an optimized
+    // `f64.ceil` native instruction, so we can leverage this for both code size
+    // and speed.
+    llvm_intrinsically_optimized! {
+        #[cfg(target_arch = "wasm32")] {
+            return unsafe { ::core::intrinsics::ceilf64(x) }
+        }
+    }
+    let u: u64 = x.to_bits();
+    let e: i64 = (u >> 52 & 0x7ff) as i64;
+    let y: f64;
+
+    if e >= 0x3ff + 52 || x == 0. {
+        return x;
+    }
+    // y = int(x) - x, where int(x) is an integer neighbor of x
+    y = if (u >> 63) != 0 {
+        x - TOINT + TOINT - x
+    } else {
+        x + TOINT - TOINT - x
+    };
+    // special case because of non-nearest rounding modes
+    if e < 0x3ff {
+        force_eval!(y);
+        return if (u >> 63) != 0 { -0. } else { 1. };
+    }
+    if y < 0. {
+        x + y + 1.
+    } else {
+        x + y
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    #[test]
+    fn sanity_check() {
+        assert_eq!(super::ceil(1.1), 2.0);
+        assert_eq!(super::ceil(2.9), 3.0);
+    }
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/ceilf.rs.html b/src/libm/math/ceilf.rs.html new file mode 100644 index 000000000..b0ffe9308 --- /dev/null +++ b/src/libm/math/ceilf.rs.html @@ -0,0 +1,87 @@ +ceilf.rs.html -- source
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+use core::f32;
+
+/// Ceil (f32)
+///
+/// Finds the nearest integer greater than or equal to `x`.
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn ceilf(x: f32) -> f32 {
+    // On wasm32 we know that LLVM's intrinsic will compile to an optimized
+    // `f32.ceil` native instruction, so we can leverage this for both code size
+    // and speed.
+    llvm_intrinsically_optimized! {
+        #[cfg(target_arch = "wasm32")] {
+            return unsafe { ::core::intrinsics::ceilf32(x) }
+        }
+    }
+    let mut ui = x.to_bits();
+    let e = (((ui >> 23) & 0xff).wrapping_sub(0x7f)) as i32;
+
+    if e >= 23 {
+        return x;
+    }
+    if e >= 0 {
+        let m = 0x007fffff >> e;
+        if (ui & m) == 0 {
+            return x;
+        }
+        force_eval!(x + f32::from_bits(0x7b800000));
+        if ui >> 31 == 0 {
+            ui += m;
+        }
+        ui &= !m;
+    } else {
+        force_eval!(x + f32::from_bits(0x7b800000));
+        if ui >> 31 != 0 {
+            return -0.0;
+        } else if ui << 1 != 0 {
+            return 1.0;
+        }
+    }
+    f32::from_bits(ui)
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/copysign.rs.html b/src/libm/math/copysign.rs.html new file mode 100644 index 000000000..09e082e70 --- /dev/null +++ b/src/libm/math/copysign.rs.html @@ -0,0 +1,25 @@ +copysign.rs.html -- source
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+/// Sign of Y, magnitude of X (f64)
+///
+/// Constructs a number with the magnitude (absolute value) of its
+/// first argument, `x`, and the sign of its second argument, `y`.
+pub fn copysign(x: f64, y: f64) -> f64 {
+    let mut ux = x.to_bits();
+    let uy = y.to_bits();
+    ux &= (!0) >> 1;
+    ux |= uy & (1 << 63);
+    f64::from_bits(ux)
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/copysignf.rs.html b/src/libm/math/copysignf.rs.html new file mode 100644 index 000000000..107ea2bd8 --- /dev/null +++ b/src/libm/math/copysignf.rs.html @@ -0,0 +1,25 @@ +copysignf.rs.html -- source
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+/// Sign of Y, magnitude of X (f32)
+///
+/// Constructs a number with the magnitude (absolute value) of its
+/// first argument, `x`, and the sign of its second argument, `y`.
+pub fn copysignf(x: f32, y: f32) -> f32 {
+    let mut ux = x.to_bits();
+    let uy = y.to_bits();
+    ux &= 0x7fffffff;
+    ux |= uy & 0x80000000;
+    f32::from_bits(ux)
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/cos.rs.html b/src/libm/math/cos.rs.html new file mode 100644 index 000000000..3a72e3c2e --- /dev/null +++ b/src/libm/math/cos.rs.html @@ -0,0 +1,151 @@ +cos.rs.html -- source
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+// origin: FreeBSD /usr/src/lib/msun/src/s_cos.c */
+//
+// ====================================================
+// Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+//
+// Developed at SunPro, a Sun Microsystems, Inc. business.
+// Permission to use, copy, modify, and distribute this
+// software is freely granted, provided that this notice
+// is preserved.
+// ====================================================
+
+use super::{k_cos, k_sin, rem_pio2};
+
+// cos(x)
+// Return cosine function of x.
+//
+// kernel function:
+//      k_sin           ... sine function on [-pi/4,pi/4]
+//      k_cos           ... cosine function on [-pi/4,pi/4]
+//      rem_pio2        ... argument reduction routine
+//
+// Method.
+//      Let S,C and T denote the sin, cos and tan respectively on
+//      [-PI/4, +PI/4]. Reduce the argument x to y1+y2 = x-k*pi/2
+//      in [-pi/4 , +pi/4], and let n = k mod 4.
+//      We have
+//
+//          n        sin(x)      cos(x)        tan(x)
+//     ----------------------------------------------------------
+//          0          S           C             T
+//          1          C          -S            -1/T
+//          2         -S          -C             T
+//          3         -C           S            -1/T
+//     ----------------------------------------------------------
+//
+// Special cases:
+//      Let trig be any of sin, cos, or tan.
+//      trig(+-INF)  is NaN, with signals;
+//      trig(NaN)    is that NaN;
+//
+// Accuracy:
+//      TRIG(x) returns trig(x) nearly rounded
+//
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn cos(x: f64) -> f64 {
+    let ix = (f64::to_bits(x) >> 32) as u32 & 0x7fffffff;
+
+    /* |x| ~< pi/4 */
+    if ix <= 0x3fe921fb {
+        if ix < 0x3e46a09e {
+            /* if x < 2**-27 * sqrt(2) */
+            /* raise inexact if x != 0 */
+            if x as i32 == 0 {
+                return 1.0;
+            }
+        }
+        return k_cos(x, 0.0);
+    }
+
+    /* cos(Inf or NaN) is NaN */
+    if ix >= 0x7ff00000 {
+        return x - x;
+    }
+
+    /* argument reduction needed */
+    let (n, y0, y1) = rem_pio2(x);
+    match n & 3 {
+        0 => k_cos(y0, y1),
+        1 => -k_sin(y0, y1, 1),
+        2 => -k_cos(y0, y1),
+        _ => k_sin(y0, y1, 1),
+    }
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/cosf.rs.html b/src/libm/math/cosf.rs.html new file mode 100644 index 000000000..133d7bae9 --- /dev/null +++ b/src/libm/math/cosf.rs.html @@ -0,0 +1,171 @@ +cosf.rs.html -- source
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+
+/* origin: FreeBSD /usr/src/lib/msun/src/s_cosf.c */
+/*
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ * Optimized by Bruce D. Evans.
+ */
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+use super::{k_cosf, k_sinf, rem_pio2f};
+
+use core::f64::consts::FRAC_PI_2;
+
+/* Small multiples of pi/2 rounded to double precision. */
+const C1_PIO2: f64 = 1. * FRAC_PI_2; /* 0x3FF921FB, 0x54442D18 */
+const C2_PIO2: f64 = 2. * FRAC_PI_2; /* 0x400921FB, 0x54442D18 */
+const C3_PIO2: f64 = 3. * FRAC_PI_2; /* 0x4012D97C, 0x7F3321D2 */
+const C4_PIO2: f64 = 4. * FRAC_PI_2; /* 0x401921FB, 0x54442D18 */
+
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn cosf(x: f32) -> f32 {
+    let x64 = x as f64;
+
+    let x1p120 = f32::from_bits(0x7b800000); // 0x1p120f === 2 ^ 120
+
+    let mut ix = x.to_bits();
+    let sign = (ix >> 31) != 0;
+    ix &= 0x7fffffff;
+
+    if ix <= 0x3f490fda {
+        /* |x| ~<= pi/4 */
+        if ix < 0x39800000 {
+            /* |x| < 2**-12 */
+            /* raise inexact if x != 0 */
+            force_eval!(x + x1p120);
+            return 1.;
+        }
+        return k_cosf(x64);
+    }
+    if ix <= 0x407b53d1 {
+        /* |x| ~<= 5*pi/4 */
+        if ix > 0x4016cbe3 {
+            /* |x|  ~> 3*pi/4 */
+            return -k_cosf(if sign { x64 + C2_PIO2 } else { x64 - C2_PIO2 });
+        } else if sign {
+            return k_sinf(x64 + C1_PIO2);
+        } else {
+            return k_sinf(C1_PIO2 - x64);
+        }
+    }
+    if ix <= 0x40e231d5 {
+        /* |x| ~<= 9*pi/4 */
+        if ix > 0x40afeddf {
+            /* |x| ~> 7*pi/4 */
+            return k_cosf(if sign { x64 + C4_PIO2 } else { x64 - C4_PIO2 });
+        } else if sign {
+            return k_sinf(-x64 - C3_PIO2);
+        } else {
+            return k_sinf(x64 - C3_PIO2);
+        }
+    }
+
+    /* cos(Inf or NaN) is NaN */
+    if ix >= 0x7f800000 {
+        return x - x;
+    }
+
+    /* general argument reduction needed */
+    let (n, y) = rem_pio2f(x);
+    match n & 3 {
+        0 => k_cosf(y),
+        1 => k_sinf(-y),
+        2 => -k_cosf(y),
+        _ => k_sinf(y),
+    }
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/cosh.rs.html b/src/libm/math/cosh.rs.html new file mode 100644 index 000000000..a78092b96 --- /dev/null +++ b/src/libm/math/cosh.rs.html @@ -0,0 +1,81 @@ +cosh.rs.html -- source
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+
+use super::exp;
+use super::expm1;
+use super::k_expo2;
+
+/// Hyperbolic cosine (f64)
+///
+/// Computes the hyperbolic cosine of the argument x.
+/// Is defined as `(exp(x) + exp(-x))/2`
+/// Angles are specified in radians.
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn cosh(mut x: f64) -> f64 {
+    /* |x| */
+    let mut ix = x.to_bits();
+    ix &= 0x7fffffffffffffff;
+    x = f64::from_bits(ix);
+    let w = ix >> 32;
+
+    /* |x| < log(2) */
+    if w < 0x3fe62e42 {
+        if w < 0x3ff00000 - (26 << 20) {
+            let x1p120 = f64::from_bits(0x4770000000000000);
+            force_eval!(x + x1p120);
+            return 1.;
+        }
+        let t = expm1(x); // exponential minus 1
+        return 1. + t * t / (2. * (1. + t));
+    }
+
+    /* |x| < log(DBL_MAX) */
+    if w < 0x40862e42 {
+        let t = exp(x);
+        /* note: if x>log(0x1p26) then the 1/t is not needed */
+        return 0.5 * (t + 1. / t);
+    }
+
+    /* |x| > log(DBL_MAX) or nan */
+    k_expo2(x)
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/coshf.rs.html b/src/libm/math/coshf.rs.html new file mode 100644 index 000000000..d0c53e9c9 --- /dev/null +++ b/src/libm/math/coshf.rs.html @@ -0,0 +1,81 @@ +coshf.rs.html -- source
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+
+use super::expf;
+use super::expm1f;
+use super::k_expo2f;
+
+/// Hyperbolic cosine (f64)
+///
+/// Computes the hyperbolic cosine of the argument x.
+/// Is defined as `(exp(x) + exp(-x))/2`
+/// Angles are specified in radians.
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn coshf(mut x: f32) -> f32 {
+    let x1p120 = f32::from_bits(0x7b800000); // 0x1p120f === 2 ^ 120
+
+    /* |x| */
+    let mut ix = x.to_bits();
+    ix &= 0x7fffffff;
+    x = f32::from_bits(ix);
+    let w = ix;
+
+    /* |x| < log(2) */
+    if w < 0x3f317217 {
+        if w < (0x3f800000 - (12 << 23)) {
+            force_eval!(x + x1p120);
+            return 1.;
+        }
+        let t = expm1f(x);
+        return 1. + t * t / (2. * (1. + t));
+    }
+
+    /* |x| < log(FLT_MAX) */
+    if w < 0x42b17217 {
+        let t = expf(x);
+        return 0.5 * (t + 1. / t);
+    }
+
+    /* |x| > log(FLT_MAX) or nan */
+    k_expo2f(x)
+}
+
+
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+use super::{exp, fabs, get_high_word, with_set_low_word};
+/* origin: FreeBSD /usr/src/lib/msun/src/s_erf.c */
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+/* double erf(double x)
+ * double erfc(double x)
+ *                           x
+ *                    2      |\
+ *     erf(x)  =  ---------  | exp(-t*t)dt
+ *                 sqrt(pi) \|
+ *                           0
+ *
+ *     erfc(x) =  1-erf(x)
+ *  Note that
+ *              erf(-x) = -erf(x)
+ *              erfc(-x) = 2 - erfc(x)
+ *
+ * Method:
+ *      1. For |x| in [0, 0.84375]
+ *          erf(x)  = x + x*R(x^2)
+ *          erfc(x) = 1 - erf(x)           if x in [-.84375,0.25]
+ *                  = 0.5 + ((0.5-x)-x*R)  if x in [0.25,0.84375]
+ *         where R = P/Q where P is an odd poly of degree 8 and
+ *         Q is an odd poly of degree 10.
+ *                                               -57.90
+ *                      | R - (erf(x)-x)/x | <= 2
+ *
+ *
+ *         Remark. The formula is derived by noting
+ *          erf(x) = (2/sqrt(pi))*(x - x^3/3 + x^5/10 - x^7/42 + ....)
+ *         and that
+ *          2/sqrt(pi) = 1.128379167095512573896158903121545171688
+ *         is close to one. The interval is chosen because the fix
+ *         point of erf(x) is near 0.6174 (i.e., erf(x)=x when x is
+ *         near 0.6174), and by some experiment, 0.84375 is chosen to
+ *         guarantee the error is less than one ulp for erf.
+ *
+ *      2. For |x| in [0.84375,1.25], let s = |x| - 1, and
+ *         c = 0.84506291151 rounded to single (24 bits)
+ *              erf(x)  = sign(x) * (c  + P1(s)/Q1(s))
+ *              erfc(x) = (1-c)  - P1(s)/Q1(s) if x > 0
+ *                        1+(c+P1(s)/Q1(s))    if x < 0
+ *              |P1/Q1 - (erf(|x|)-c)| <= 2**-59.06
+ *         Remark: here we use the taylor series expansion at x=1.
+ *              erf(1+s) = erf(1) + s*Poly(s)
+ *                       = 0.845.. + P1(s)/Q1(s)
+ *         That is, we use rational approximation to approximate
+ *                      erf(1+s) - (c = (single)0.84506291151)
+ *         Note that |P1/Q1|< 0.078 for x in [0.84375,1.25]
+ *         where
+ *              P1(s) = degree 6 poly in s
+ *              Q1(s) = degree 6 poly in s
+ *
+ *      3. For x in [1.25,1/0.35(~2.857143)],
+ *              erfc(x) = (1/x)*exp(-x*x-0.5625+R1/S1)
+ *              erf(x)  = 1 - erfc(x)
+ *         where
+ *              R1(z) = degree 7 poly in z, (z=1/x^2)
+ *              S1(z) = degree 8 poly in z
+ *
+ *      4. For x in [1/0.35,28]
+ *              erfc(x) = (1/x)*exp(-x*x-0.5625+R2/S2) if x > 0
+ *                      = 2.0 - (1/x)*exp(-x*x-0.5625+R2/S2) if -6<x<0
+ *                      = 2.0 - tiny            (if x <= -6)
+ *              erf(x)  = sign(x)*(1.0 - erfc(x)) if x < 6, else
+ *              erf(x)  = sign(x)*(1.0 - tiny)
+ *         where
+ *              R2(z) = degree 6 poly in z, (z=1/x^2)
+ *              S2(z) = degree 7 poly in z
+ *
+ *      Note1:
+ *         To compute exp(-x*x-0.5625+R/S), let s be a single
+ *         precision number and s := x; then
+ *              -x*x = -s*s + (s-x)*(s+x)
+ *              exp(-x*x-0.5626+R/S) =
+ *                      exp(-s*s-0.5625)*exp((s-x)*(s+x)+R/S);
+ *      Note2:
+ *         Here 4 and 5 make use of the asymptotic series
+ *                        exp(-x*x)
+ *              erfc(x) ~ ---------- * ( 1 + Poly(1/x^2) )
+ *                        x*sqrt(pi)
+ *         We use rational approximation to approximate
+ *              g(s)=f(1/x^2) = log(erfc(x)*x) - x*x + 0.5625
+ *         Here is the error bound for R1/S1 and R2/S2
+ *              |R1/S1 - f(x)|  < 2**(-62.57)
+ *              |R2/S2 - f(x)|  < 2**(-61.52)
+ *
+ *      5. For inf > x >= 28
+ *              erf(x)  = sign(x) *(1 - tiny)  (raise inexact)
+ *              erfc(x) = tiny*tiny (raise underflow) if x > 0
+ *                      = 2 - tiny if x<0
+ *
+ *      7. Special case:
+ *              erf(0)  = 0, erf(inf)  = 1, erf(-inf) = -1,
+ *              erfc(0) = 1, erfc(inf) = 0, erfc(-inf) = 2,
+ *              erfc/erf(NaN) is NaN
+ */
+
+const ERX: f64 = 8.45062911510467529297e-01; /* 0x3FEB0AC1, 0x60000000 */
+/*
+ * Coefficients for approximation to  erf on [0,0.84375]
+ */
+const EFX8: f64 = 1.02703333676410069053e+00; /* 0x3FF06EBA, 0x8214DB69 */
+const PP0: f64 = 1.28379167095512558561e-01; /* 0x3FC06EBA, 0x8214DB68 */
+const PP1: f64 = -3.25042107247001499370e-01; /* 0xBFD4CD7D, 0x691CB913 */
+const PP2: f64 = -2.84817495755985104766e-02; /* 0xBF9D2A51, 0xDBD7194F */
+const PP3: f64 = -5.77027029648944159157e-03; /* 0xBF77A291, 0x236668E4 */
+const PP4: f64 = -2.37630166566501626084e-05; /* 0xBEF8EAD6, 0x120016AC */
+const QQ1: f64 = 3.97917223959155352819e-01; /* 0x3FD97779, 0xCDDADC09 */
+const QQ2: f64 = 6.50222499887672944485e-02; /* 0x3FB0A54C, 0x5536CEBA */
+const QQ3: f64 = 5.08130628187576562776e-03; /* 0x3F74D022, 0xC4D36B0F */
+const QQ4: f64 = 1.32494738004321644526e-04; /* 0x3F215DC9, 0x221C1A10 */
+const QQ5: f64 = -3.96022827877536812320e-06; /* 0xBED09C43, 0x42A26120 */
+/*
+ * Coefficients for approximation to  erf  in [0.84375,1.25]
+ */
+const PA0: f64 = -2.36211856075265944077e-03; /* 0xBF6359B8, 0xBEF77538 */
+const PA1: f64 = 4.14856118683748331666e-01; /* 0x3FDA8D00, 0xAD92B34D */
+const PA2: f64 = -3.72207876035701323847e-01; /* 0xBFD7D240, 0xFBB8C3F1 */
+const PA3: f64 = 3.18346619901161753674e-01; /* 0x3FD45FCA, 0x805120E4 */
+const PA4: f64 = -1.10894694282396677476e-01; /* 0xBFBC6398, 0x3D3E28EC */
+const PA5: f64 = 3.54783043256182359371e-02; /* 0x3FA22A36, 0x599795EB */
+const PA6: f64 = -2.16637559486879084300e-03; /* 0xBF61BF38, 0x0A96073F */
+const QA1: f64 = 1.06420880400844228286e-01; /* 0x3FBB3E66, 0x18EEE323 */
+const QA2: f64 = 5.40397917702171048937e-01; /* 0x3FE14AF0, 0x92EB6F33 */
+const QA3: f64 = 7.18286544141962662868e-02; /* 0x3FB2635C, 0xD99FE9A7 */
+const QA4: f64 = 1.26171219808761642112e-01; /* 0x3FC02660, 0xE763351F */
+const QA5: f64 = 1.36370839120290507362e-02; /* 0x3F8BEDC2, 0x6B51DD1C */
+const QA6: f64 = 1.19844998467991074170e-02; /* 0x3F888B54, 0x5735151D */
+/*
+ * Coefficients for approximation to  erfc in [1.25,1/0.35]
+ */
+const RA0: f64 = -9.86494403484714822705e-03; /* 0xBF843412, 0x600D6435 */
+const RA1: f64 = -6.93858572707181764372e-01; /* 0xBFE63416, 0xE4BA7360 */
+const RA2: f64 = -1.05586262253232909814e+01; /* 0xC0251E04, 0x41B0E726 */
+const RA3: f64 = -6.23753324503260060396e+01; /* 0xC04F300A, 0xE4CBA38D */
+const RA4: f64 = -1.62396669462573470355e+02; /* 0xC0644CB1, 0x84282266 */
+const RA5: f64 = -1.84605092906711035994e+02; /* 0xC067135C, 0xEBCCABB2 */
+const RA6: f64 = -8.12874355063065934246e+01; /* 0xC0545265, 0x57E4D2F2 */
+const RA7: f64 = -9.81432934416914548592e+00; /* 0xC023A0EF, 0xC69AC25C */
+const SA1: f64 = 1.96512716674392571292e+01; /* 0x4033A6B9, 0xBD707687 */
+const SA2: f64 = 1.37657754143519042600e+02; /* 0x4061350C, 0x526AE721 */
+const SA3: f64 = 4.34565877475229228821e+02; /* 0x407B290D, 0xD58A1A71 */
+const SA4: f64 = 6.45387271733267880336e+02; /* 0x40842B19, 0x21EC2868 */
+const SA5: f64 = 4.29008140027567833386e+02; /* 0x407AD021, 0x57700314 */
+const SA6: f64 = 1.08635005541779435134e+02; /* 0x405B28A3, 0xEE48AE2C */
+const SA7: f64 = 6.57024977031928170135e+00; /* 0x401A47EF, 0x8E484A93 */
+const SA8: f64 = -6.04244152148580987438e-02; /* 0xBFAEEFF2, 0xEE749A62 */
+/*
+ * Coefficients for approximation to  erfc in [1/.35,28]
+ */
+const RB0: f64 = -9.86494292470009928597e-03; /* 0xBF843412, 0x39E86F4A */
+const RB1: f64 = -7.99283237680523006574e-01; /* 0xBFE993BA, 0x70C285DE */
+const RB2: f64 = -1.77579549177547519889e+01; /* 0xC031C209, 0x555F995A */
+const RB3: f64 = -1.60636384855821916062e+02; /* 0xC064145D, 0x43C5ED98 */
+const RB4: f64 = -6.37566443368389627722e+02; /* 0xC083EC88, 0x1375F228 */
+const RB5: f64 = -1.02509513161107724954e+03; /* 0xC0900461, 0x6A2E5992 */
+const RB6: f64 = -4.83519191608651397019e+02; /* 0xC07E384E, 0x9BDC383F */
+const SB1: f64 = 3.03380607434824582924e+01; /* 0x403E568B, 0x261D5190 */
+const SB2: f64 = 3.25792512996573918826e+02; /* 0x40745CAE, 0x221B9F0A */
+const SB3: f64 = 1.53672958608443695994e+03; /* 0x409802EB, 0x189D5118 */
+const SB4: f64 = 3.19985821950859553908e+03; /* 0x40A8FFB7, 0x688C246A */
+const SB5: f64 = 2.55305040643316442583e+03; /* 0x40A3F219, 0xCEDF3BE6 */
+const SB6: f64 = 4.74528541206955367215e+02; /* 0x407DA874, 0xE79FE763 */
+const SB7: f64 = -2.24409524465858183362e+01; /* 0xC03670E2, 0x42712D62 */
+
+fn erfc1(x: f64) -> f64 {
+    let s: f64;
+    let p: f64;
+    let q: f64;
+
+    s = fabs(x) - 1.0;
+    p = PA0 + s * (PA1 + s * (PA2 + s * (PA3 + s * (PA4 + s * (PA5 + s * PA6)))));
+    q = 1.0 + s * (QA1 + s * (QA2 + s * (QA3 + s * (QA4 + s * (QA5 + s * QA6)))));
+
+    1.0 - ERX - p / q
+}
+
+fn erfc2(ix: u32, mut x: f64) -> f64 {
+    let s: f64;
+    let r: f64;
+    let big_s: f64;
+    let z: f64;
+
+    if ix < 0x3ff40000 {
+        /* |x| < 1.25 */
+        return erfc1(x);
+    }
+
+    x = fabs(x);
+    s = 1.0 / (x * x);
+    if ix < 0x4006db6d {
+        /* |x| < 1/.35 ~ 2.85714 */
+        r = RA0 + s * (RA1 + s * (RA2 + s * (RA3 + s * (RA4 + s * (RA5 + s * (RA6 + s * RA7))))));
+        big_s = 1.0
+            + s * (SA1
+                + s * (SA2 + s * (SA3 + s * (SA4 + s * (SA5 + s * (SA6 + s * (SA7 + s * SA8)))))));
+    } else {
+        /* |x| > 1/.35 */
+        r = RB0 + s * (RB1 + s * (RB2 + s * (RB3 + s * (RB4 + s * (RB5 + s * RB6)))));
+        big_s =
+            1.0 + s * (SB1 + s * (SB2 + s * (SB3 + s * (SB4 + s * (SB5 + s * (SB6 + s * SB7))))));
+    }
+    z = with_set_low_word(x, 0);
+
+    exp(-z * z - 0.5625) * exp((z - x) * (z + x) + r / big_s) / x
+}
+
+/// Error function (f64)
+///
+/// Calculates an approximation to the “error function”, which estimates
+/// the probability that an observation will fall within x standard
+/// deviations of the mean (assuming a normal distribution).
+pub fn erf(x: f64) -> f64 {
+    let r: f64;
+    let s: f64;
+    let z: f64;
+    let y: f64;
+    let mut ix: u32;
+    let sign: usize;
+
+    ix = get_high_word(x);
+    sign = (ix >> 31) as usize;
+    ix &= 0x7fffffff;
+    if ix >= 0x7ff00000 {
+        /* erf(nan)=nan, erf(+-inf)=+-1 */
+        return 1.0 - 2.0 * (sign as f64) + 1.0 / x;
+    }
+    if ix < 0x3feb0000 {
+        /* |x| < 0.84375 */
+        if ix < 0x3e300000 {
+            /* |x| < 2**-28 */
+            /* avoid underflow */
+            return 0.125 * (8.0 * x + EFX8 * x);
+        }
+        z = x * x;
+        r = PP0 + z * (PP1 + z * (PP2 + z * (PP3 + z * PP4)));
+        s = 1.0 + z * (QQ1 + z * (QQ2 + z * (QQ3 + z * (QQ4 + z * QQ5))));
+        y = r / s;
+        return x + x * y;
+    }
+    if ix < 0x40180000 {
+        /* 0.84375 <= |x| < 6 */
+        y = 1.0 - erfc2(ix, x);
+    } else {
+        let x1p_1022 = f64::from_bits(0x0010000000000000);
+        y = 1.0 - x1p_1022;
+    }
+
+    if sign != 0 {
+        -y
+    } else {
+        y
+    }
+}
+
+/// Error function (f64)
+///
+/// Calculates the complementary probability.
+/// Is `1 - erf(x)`. Is computed directly, so that you can use it to avoid
+/// the loss of precision that would result from subtracting
+/// large probabilities (on large `x`) from 1.
+pub fn erfc(x: f64) -> f64 {
+    let r: f64;
+    let s: f64;
+    let z: f64;
+    let y: f64;
+    let mut ix: u32;
+    let sign: usize;
+
+    ix = get_high_word(x);
+    sign = (ix >> 31) as usize;
+    ix &= 0x7fffffff;
+    if ix >= 0x7ff00000 {
+        /* erfc(nan)=nan, erfc(+-inf)=0,2 */
+        return 2.0 * (sign as f64) + 1.0 / x;
+    }
+    if ix < 0x3feb0000 {
+        /* |x| < 0.84375 */
+        if ix < 0x3c700000 {
+            /* |x| < 2**-56 */
+            return 1.0 - x;
+        }
+        z = x * x;
+        r = PP0 + z * (PP1 + z * (PP2 + z * (PP3 + z * PP4)));
+        s = 1.0 + z * (QQ1 + z * (QQ2 + z * (QQ3 + z * (QQ4 + z * QQ5))));
+        y = r / s;
+        if sign != 0 || ix < 0x3fd00000 {
+            /* x < 1/4 */
+            return 1.0 - (x + x * y);
+        }
+        return 0.5 - (x - 0.5 + x * y);
+    }
+    if ix < 0x403c0000 {
+        /* 0.84375 <= |x| < 28 */
+        if sign != 0 {
+            return 2.0 - erfc2(ix, x);
+        } else {
+            return erfc2(ix, x);
+        }
+    }
+
+    let x1p_1022 = f64::from_bits(0x0010000000000000);
+    if sign != 0 {
+        2.0 - x1p_1022
+    } else {
+        x1p_1022 * x1p_1022
+    }
+}
+
+
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+
+/* origin: FreeBSD /usr/src/lib/msun/src/s_erff.c */
+/*
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+use super::{expf, fabsf};
+
+const ERX: f32 = 8.4506291151e-01; /* 0x3f58560b */
+/*
+ * Coefficients for approximation to  erf on [0,0.84375]
+ */
+const EFX8: f32 = 1.0270333290e+00; /* 0x3f8375d4 */
+const PP0: f32 = 1.2837916613e-01; /* 0x3e0375d4 */
+const PP1: f32 = -3.2504209876e-01; /* 0xbea66beb */
+const PP2: f32 = -2.8481749818e-02; /* 0xbce9528f */
+const PP3: f32 = -5.7702702470e-03; /* 0xbbbd1489 */
+const PP4: f32 = -2.3763017452e-05; /* 0xb7c756b1 */
+const QQ1: f32 = 3.9791721106e-01; /* 0x3ecbbbce */
+const QQ2: f32 = 6.5022252500e-02; /* 0x3d852a63 */
+const QQ3: f32 = 5.0813062117e-03; /* 0x3ba68116 */
+const QQ4: f32 = 1.3249473704e-04; /* 0x390aee49 */
+const QQ5: f32 = -3.9602282413e-06; /* 0xb684e21a */
+/*
+ * Coefficients for approximation to  erf  in [0.84375,1.25]
+ */
+const PA0: f32 = -2.3621185683e-03; /* 0xbb1acdc6 */
+const PA1: f32 = 4.1485610604e-01; /* 0x3ed46805 */
+const PA2: f32 = -3.7220788002e-01; /* 0xbebe9208 */
+const PA3: f32 = 3.1834661961e-01; /* 0x3ea2fe54 */
+const PA4: f32 = -1.1089469492e-01; /* 0xbde31cc2 */
+const PA5: f32 = 3.5478305072e-02; /* 0x3d1151b3 */
+const PA6: f32 = -2.1663755178e-03; /* 0xbb0df9c0 */
+const QA1: f32 = 1.0642088205e-01; /* 0x3dd9f331 */
+const QA2: f32 = 5.4039794207e-01; /* 0x3f0a5785 */
+const QA3: f32 = 7.1828655899e-02; /* 0x3d931ae7 */
+const QA4: f32 = 1.2617121637e-01; /* 0x3e013307 */
+const QA5: f32 = 1.3637083583e-02; /* 0x3c5f6e13 */
+const QA6: f32 = 1.1984500103e-02; /* 0x3c445aa3 */
+/*
+ * Coefficients for approximation to  erfc in [1.25,1/0.35]
+ */
+const RA0: f32 = -9.8649440333e-03; /* 0xbc21a093 */
+const RA1: f32 = -6.9385856390e-01; /* 0xbf31a0b7 */
+const RA2: f32 = -1.0558626175e+01; /* 0xc128f022 */
+const RA3: f32 = -6.2375331879e+01; /* 0xc2798057 */
+const RA4: f32 = -1.6239666748e+02; /* 0xc322658c */
+const RA5: f32 = -1.8460508728e+02; /* 0xc3389ae7 */
+const RA6: f32 = -8.1287437439e+01; /* 0xc2a2932b */
+const RA7: f32 = -9.8143291473e+00; /* 0xc11d077e */
+const SA1: f32 = 1.9651271820e+01; /* 0x419d35ce */
+const SA2: f32 = 1.3765776062e+02; /* 0x4309a863 */
+const SA3: f32 = 4.3456588745e+02; /* 0x43d9486f */
+const SA4: f32 = 6.4538726807e+02; /* 0x442158c9 */
+const SA5: f32 = 4.2900814819e+02; /* 0x43d6810b */
+const SA6: f32 = 1.0863500214e+02; /* 0x42d9451f */
+const SA7: f32 = 6.5702495575e+00; /* 0x40d23f7c */
+const SA8: f32 = -6.0424413532e-02; /* 0xbd777f97 */
+/*
+ * Coefficients for approximation to  erfc in [1/.35,28]
+ */
+const RB0: f32 = -9.8649431020e-03; /* 0xbc21a092 */
+const RB1: f32 = -7.9928326607e-01; /* 0xbf4c9dd4 */
+const RB2: f32 = -1.7757955551e+01; /* 0xc18e104b */
+const RB3: f32 = -1.6063638306e+02; /* 0xc320a2ea */
+const RB4: f32 = -6.3756646729e+02; /* 0xc41f6441 */
+const RB5: f32 = -1.0250950928e+03; /* 0xc480230b */
+const RB6: f32 = -4.8351919556e+02; /* 0xc3f1c275 */
+const SB1: f32 = 3.0338060379e+01; /* 0x41f2b459 */
+const SB2: f32 = 3.2579251099e+02; /* 0x43a2e571 */
+const SB3: f32 = 1.5367296143e+03; /* 0x44c01759 */
+const SB4: f32 = 3.1998581543e+03; /* 0x4547fdbb */
+const SB5: f32 = 2.5530502930e+03; /* 0x451f90ce */
+const SB6: f32 = 4.7452853394e+02; /* 0x43ed43a7 */
+const SB7: f32 = -2.2440952301e+01; /* 0xc1b38712 */
+
+fn erfc1(x: f32) -> f32 {
+    let s: f32;
+    let p: f32;
+    let q: f32;
+
+    s = fabsf(x) - 1.0;
+    p = PA0 + s * (PA1 + s * (PA2 + s * (PA3 + s * (PA4 + s * (PA5 + s * PA6)))));
+    q = 1.0 + s * (QA1 + s * (QA2 + s * (QA3 + s * (QA4 + s * (QA5 + s * QA6)))));
+    return 1.0 - ERX - p / q;
+}
+
+fn erfc2(mut ix: u32, mut x: f32) -> f32 {
+    let s: f32;
+    let r: f32;
+    let big_s: f32;
+    let z: f32;
+
+    if ix < 0x3fa00000 {
+        /* |x| < 1.25 */
+        return erfc1(x);
+    }
+
+    x = fabsf(x);
+    s = 1.0 / (x * x);
+    if ix < 0x4036db6d {
+        /* |x| < 1/0.35 */
+        r = RA0 + s * (RA1 + s * (RA2 + s * (RA3 + s * (RA4 + s * (RA5 + s * (RA6 + s * RA7))))));
+        big_s = 1.0
+            + s * (SA1
+                + s * (SA2 + s * (SA3 + s * (SA4 + s * (SA5 + s * (SA6 + s * (SA7 + s * SA8)))))));
+    } else {
+        /* |x| >= 1/0.35 */
+        r = RB0 + s * (RB1 + s * (RB2 + s * (RB3 + s * (RB4 + s * (RB5 + s * RB6)))));
+        big_s =
+            1.0 + s * (SB1 + s * (SB2 + s * (SB3 + s * (SB4 + s * (SB5 + s * (SB6 + s * SB7))))));
+    }
+    ix = x.to_bits();
+    z = f32::from_bits(ix & 0xffffe000);
+
+    expf(-z * z - 0.5625) * expf((z - x) * (z + x) + r / big_s) / x
+}
+
+/// Error function (f32)
+///
+/// Calculates an approximation to the “error function”, which estimates
+/// the probability that an observation will fall within x standard
+/// deviations of the mean (assuming a normal distribution).
+pub fn erff(x: f32) -> f32 {
+    let r: f32;
+    let s: f32;
+    let z: f32;
+    let y: f32;
+    let mut ix: u32;
+    let sign: usize;
+
+    ix = x.to_bits();
+    sign = (ix >> 31) as usize;
+    ix &= 0x7fffffff;
+    if ix >= 0x7f800000 {
+        /* erf(nan)=nan, erf(+-inf)=+-1 */
+        return 1.0 - 2.0 * (sign as f32) + 1.0 / x;
+    }
+    if ix < 0x3f580000 {
+        /* |x| < 0.84375 */
+        if ix < 0x31800000 {
+            /* |x| < 2**-28 */
+            /*avoid underflow */
+            return 0.125 * (8.0 * x + EFX8 * x);
+        }
+        z = x * x;
+        r = PP0 + z * (PP1 + z * (PP2 + z * (PP3 + z * PP4)));
+        s = 1.0 + z * (QQ1 + z * (QQ2 + z * (QQ3 + z * (QQ4 + z * QQ5))));
+        y = r / s;
+        return x + x * y;
+    }
+    if ix < 0x40c00000 {
+        /* |x| < 6 */
+        y = 1.0 - erfc2(ix, x);
+    } else {
+        let x1p_120 = f32::from_bits(0x03800000);
+        y = 1.0 - x1p_120;
+    }
+
+    if sign != 0 {
+        -y
+    } else {
+        y
+    }
+}
+
+/// Error function (f32)
+///
+/// Calculates the complementary probability.
+/// Is `1 - erf(x)`. Is computed directly, so that you can use it to avoid
+/// the loss of precision that would result from subtracting
+/// large probabilities (on large `x`) from 1.
+pub fn erfcf(x: f32) -> f32 {
+    let r: f32;
+    let s: f32;
+    let z: f32;
+    let y: f32;
+    let mut ix: u32;
+    let sign: usize;
+
+    ix = x.to_bits();
+    sign = (ix >> 31) as usize;
+    ix &= 0x7fffffff;
+    if ix >= 0x7f800000 {
+        /* erfc(nan)=nan, erfc(+-inf)=0,2 */
+        return 2.0 * (sign as f32) + 1.0 / x;
+    }
+
+    if ix < 0x3f580000 {
+        /* |x| < 0.84375 */
+        if ix < 0x23800000 {
+            /* |x| < 2**-56 */
+            return 1.0 - x;
+        }
+        z = x * x;
+        r = PP0 + z * (PP1 + z * (PP2 + z * (PP3 + z * PP4)));
+        s = 1.0 + z * (QQ1 + z * (QQ2 + z * (QQ3 + z * (QQ4 + z * QQ5))));
+        y = r / s;
+        if sign != 0 || ix < 0x3e800000 {
+            /* x < 1/4 */
+            return 1.0 - (x + x * y);
+        }
+        return 0.5 - (x - 0.5 + x * y);
+    }
+    if ix < 0x41e00000 {
+        /* |x| < 28 */
+        if sign != 0 {
+            return 2.0 - erfc2(ix, x);
+        } else {
+            return erfc2(ix, x);
+        }
+    }
+
+    let x1p_120 = f32::from_bits(0x03800000);
+    if sign != 0 {
+        2.0 - x1p_120
+    } else {
+        x1p_120 * x1p_120
+    }
+}
+
+
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+
+/* origin: FreeBSD /usr/src/lib/msun/src/e_exp.c */
+/*
+ * ====================================================
+ * Copyright (C) 2004 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+/* exp(x)
+ * Returns the exponential of x.
+ *
+ * Method
+ *   1. Argument reduction:
+ *      Reduce x to an r so that |r| <= 0.5*ln2 ~ 0.34658.
+ *      Given x, find r and integer k such that
+ *
+ *               x = k*ln2 + r,  |r| <= 0.5*ln2.
+ *
+ *      Here r will be represented as r = hi-lo for better
+ *      accuracy.
+ *
+ *   2. Approximation of exp(r) by a special rational function on
+ *      the interval [0,0.34658]:
+ *      Write
+ *          R(r**2) = r*(exp(r)+1)/(exp(r)-1) = 2 + r*r/6 - r**4/360 + ...
+ *      We use a special Remez algorithm on [0,0.34658] to generate
+ *      a polynomial of degree 5 to approximate R. The maximum error
+ *      of this polynomial approximation is bounded by 2**-59. In
+ *      other words,
+ *          R(z) ~ 2.0 + P1*z + P2*z**2 + P3*z**3 + P4*z**4 + P5*z**5
+ *      (where z=r*r, and the values of P1 to P5 are listed below)
+ *      and
+ *          |                  5          |     -59
+ *          | 2.0+P1*z+...+P5*z   -  R(z) | <= 2
+ *          |                             |
+ *      The computation of exp(r) thus becomes
+ *                              2*r
+ *              exp(r) = 1 + ----------
+ *                            R(r) - r
+ *                                 r*c(r)
+ *                     = 1 + r + ----------- (for better accuracy)
+ *                                2 - c(r)
+ *      where
+ *                              2       4             10
+ *              c(r) = r - (P1*r  + P2*r  + ... + P5*r   ).
+ *
+ *   3. Scale back to obtain exp(x):
+ *      From step 1, we have
+ *         exp(x) = 2^k * exp(r)
+ *
+ * Special cases:
+ *      exp(INF) is INF, exp(NaN) is NaN;
+ *      exp(-INF) is 0, and
+ *      for finite argument, only exp(0)=1 is exact.
+ *
+ * Accuracy:
+ *      according to an error analysis, the error is always less than
+ *      1 ulp (unit in the last place).
+ *
+ * Misc. info.
+ *      For IEEE double
+ *          if x >  709.782712893383973096 then exp(x) overflows
+ *          if x < -745.133219101941108420 then exp(x) underflows
+ */
+
+use super::scalbn;
+
+const HALF: [f64; 2] = [0.5, -0.5];
+const LN2HI: f64 = 6.93147180369123816490e-01; /* 0x3fe62e42, 0xfee00000 */
+const LN2LO: f64 = 1.90821492927058770002e-10; /* 0x3dea39ef, 0x35793c76 */
+const INVLN2: f64 = 1.44269504088896338700e+00; /* 0x3ff71547, 0x652b82fe */
+const P1: f64 = 1.66666666666666019037e-01; /* 0x3FC55555, 0x5555553E */
+const P2: f64 = -2.77777777770155933842e-03; /* 0xBF66C16C, 0x16BEBD93 */
+const P3: f64 = 6.61375632143793436117e-05; /* 0x3F11566A, 0xAF25DE2C */
+const P4: f64 = -1.65339022054652515390e-06; /* 0xBEBBBD41, 0xC5D26BF1 */
+const P5: f64 = 4.13813679705723846039e-08; /* 0x3E663769, 0x72BEA4D0 */
+
+/// Exponential, base *e* (f64)
+///
+/// Calculate the exponential of `x`, that is, *e* raised to the power `x`
+/// (where *e* is the base of the natural system of logarithms, approximately 2.71828).
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn exp(mut x: f64) -> f64 {
+    let x1p1023 = f64::from_bits(0x7fe0000000000000); // 0x1p1023 === 2 ^ 1023
+    let x1p_149 = f64::from_bits(0x36a0000000000000); // 0x1p-149 === 2 ^ -149
+
+    let hi: f64;
+    let lo: f64;
+    let c: f64;
+    let xx: f64;
+    let y: f64;
+    let k: i32;
+    let sign: i32;
+    let mut hx: u32;
+
+    hx = (x.to_bits() >> 32) as u32;
+    sign = (hx >> 31) as i32;
+    hx &= 0x7fffffff; /* high word of |x| */
+
+    /* special cases */
+    if hx >= 0x4086232b {
+        /* if |x| >= 708.39... */
+        if x.is_nan() {
+            return x;
+        }
+        if x > 709.782712893383973096 {
+            /* overflow if x!=inf */
+            x *= x1p1023;
+            return x;
+        }
+        if x < -708.39641853226410622 {
+            /* underflow if x!=-inf */
+            force_eval!((-x1p_149 / x) as f32);
+            if x < -745.13321910194110842 {
+                return 0.;
+            }
+        }
+    }
+
+    /* argument reduction */
+    if hx > 0x3fd62e42 {
+        /* if |x| > 0.5 ln2 */
+        if hx >= 0x3ff0a2b2 {
+            /* if |x| >= 1.5 ln2 */
+            k = (INVLN2 * x + HALF[sign as usize]) as i32;
+        } else {
+            k = 1 - sign - sign;
+        }
+        hi = x - k as f64 * LN2HI; /* k*ln2hi is exact here */
+        lo = k as f64 * LN2LO;
+        x = hi - lo;
+    } else if hx > 0x3e300000 {
+        /* if |x| > 2**-28 */
+        k = 0;
+        hi = x;
+        lo = 0.;
+    } else {
+        /* inexact if x!=0 */
+        force_eval!(x1p1023 + x);
+        return 1. + x;
+    }
+
+    /* x is now in primary range */
+    xx = x * x;
+    c = x - xx * (P1 + xx * (P2 + xx * (P3 + xx * (P4 + xx * P5))));
+    y = 1. + (x * c / (2. - c) - lo + hi);
+    if k == 0 {
+        y
+    } else {
+        scalbn(y, k)
+    }
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/exp10.rs.html b/src/libm/math/exp10.rs.html new file mode 100644 index 000000000..05a2aee61 --- /dev/null +++ b/src/libm/math/exp10.rs.html @@ -0,0 +1,45 @@ +exp10.rs.html -- source
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+
+use super::{exp2, modf, pow};
+
+const LN10: f64 = 3.32192809488736234787031942948939;
+const P10: &[f64] = &[
+    1e-15, 1e-14, 1e-13, 1e-12, 1e-11, 1e-10, 1e-9, 1e-8, 1e-7, 1e-6, 1e-5, 1e-4, 1e-3, 1e-2, 1e-1,
+    1e0, 1e1, 1e2, 1e3, 1e4, 1e5, 1e6, 1e7, 1e8, 1e9, 1e10, 1e11, 1e12, 1e13, 1e14, 1e15,
+];
+
+pub fn exp10(x: f64) -> f64 {
+    let (mut y, n) = modf(x);
+    let u: u64 = n.to_bits();
+    /* fabs(n) < 16 without raising invalid on nan */
+    if (u >> 52 & 0x7ff) < 0x3ff + 4 {
+        if y == 0.0 {
+            return P10[((n as isize) + 15) as usize];
+        }
+        y = exp2(LN10 * y);
+        return y * P10[((n as isize) + 15) as usize];
+    }
+    return pow(10.0, x);
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/exp10f.rs.html b/src/libm/math/exp10f.rs.html new file mode 100644 index 000000000..96b374553 --- /dev/null +++ b/src/libm/math/exp10f.rs.html @@ -0,0 +1,45 @@ +exp10f.rs.html -- source
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+use super::{exp2, exp2f, modff};
+
+const LN10_F32: f32 = 3.32192809488736234787031942948939;
+const LN10_F64: f64 = 3.32192809488736234787031942948939;
+const P10: &[f32] = &[
+    1e-7, 1e-6, 1e-5, 1e-4, 1e-3, 1e-2, 1e-1, 1e0, 1e1, 1e2, 1e3, 1e4, 1e5, 1e6, 1e7,
+];
+
+pub fn exp10f(x: f32) -> f32 {
+    let (mut y, n) = modff(x);
+    let u = n.to_bits();
+    /* fabsf(n) < 8 without raising invalid on nan */
+    if (u >> 23 & 0xff) < 0x7f + 3 {
+        if y == 0.0 {
+            return P10[((n as isize) + 7) as usize];
+        }
+        y = exp2f(LN10_F32 * y);
+        return y * P10[((n as isize) + 7) as usize];
+    }
+    return exp2(LN10_F64 * (x as f64)) as f32;
+}
+
+
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+
+// origin: FreeBSD /usr/src/lib/msun/src/s_exp2.c */
+//-
+// Copyright (c) 2005 David Schultz <das@FreeBSD.ORG>
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+// 1. Redistributions of source code must retain the above copyright
+//    notice, this list of conditions and the following disclaimer.
+// 2. Redistributions in binary form must reproduce the above copyright
+//    notice, this list of conditions and the following disclaimer in the
+//    documentation and/or other materials provided with the distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+// OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+// LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+// OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+// SUCH DAMAGE.
+
+use super::scalbn;
+
+const TBLSIZE: usize = 256;
+
+#[cfg_attr(rustfmt, rustfmt_skip)]
+static TBL: [u64; TBLSIZE * 2] = [
+    //  exp2(z + eps)          eps
+    0x3fe6a09e667f3d5d, 0x3d39880000000000,
+    0x3fe6b052fa751744, 0x3cd8000000000000,
+    0x3fe6c012750bd9fe, 0xbd28780000000000,
+    0x3fe6cfdcddd476bf, 0x3d1ec00000000000,
+    0x3fe6dfb23c651a29, 0xbcd8000000000000,
+    0x3fe6ef9298593ae3, 0xbcbc000000000000,
+    0x3fe6ff7df9519386, 0xbd2fd80000000000,
+    0x3fe70f7466f42da3, 0xbd2c880000000000,
+    0x3fe71f75e8ec5fc3, 0x3d13c00000000000,
+    0x3fe72f8286eacf05, 0xbd38300000000000,
+    0x3fe73f9a48a58152, 0xbd00c00000000000,
+    0x3fe74fbd35d7ccfc, 0x3d2f880000000000,
+    0x3fe75feb564267f1, 0x3d03e00000000000,
+    0x3fe77024b1ab6d48, 0xbd27d00000000000,
+    0x3fe780694fde5d38, 0xbcdd000000000000,
+    0x3fe790b938ac1d00, 0x3ce3000000000000,
+    0x3fe7a11473eb0178, 0xbced000000000000,
+    0x3fe7b17b0976d060, 0x3d20400000000000,
+    0x3fe7c1ed0130c133, 0x3ca0000000000000,
+    0x3fe7d26a62ff8636, 0xbd26900000000000,
+    0x3fe7e2f336cf4e3b, 0xbd02e00000000000,
+    0x3fe7f3878491c3e8, 0xbd24580000000000,
+    0x3fe80427543e1b4e, 0x3d33000000000000,
+    0x3fe814d2add1071a, 0x3d0f000000000000,
+    0x3fe82589994ccd7e, 0xbd21c00000000000,
+    0x3fe8364c1eb942d0, 0x3d29d00000000000,
+    0x3fe8471a4623cab5, 0x3d47100000000000,
+    0x3fe857f4179f5bbc, 0x3d22600000000000,
+    0x3fe868d99b4491af, 0xbd32c40000000000,
+    0x3fe879cad931a395, 0xbd23000000000000,
+    0x3fe88ac7d98a65b8, 0xbd2a800000000000,
+    0x3fe89bd0a4785800, 0xbced000000000000,
+    0x3fe8ace5422aa223, 0x3d33280000000000,
+    0x3fe8be05bad619fa, 0x3d42b40000000000,
+    0x3fe8cf3216b54383, 0xbd2ed00000000000,
+    0x3fe8e06a5e08664c, 0xbd20500000000000,
+    0x3fe8f1ae99157807, 0x3d28280000000000,
+    0x3fe902fed0282c0e, 0xbd1cb00000000000,
+    0x3fe9145b0b91ff96, 0xbd05e00000000000,
+    0x3fe925c353aa2ff9, 0x3cf5400000000000,
+    0x3fe93737b0cdc64a, 0x3d17200000000000,
+    0x3fe948b82b5f98ae, 0xbd09000000000000,
+    0x3fe95a44cbc852cb, 0x3d25680000000000,
+    0x3fe96bdd9a766f21, 0xbd36d00000000000,
+    0x3fe97d829fde4e2a, 0xbd01000000000000,
+    0x3fe98f33e47a23a3, 0x3d2d000000000000,
+    0x3fe9a0f170ca0604, 0xbd38a40000000000,
+    0x3fe9b2bb4d53ff89, 0x3d355c0000000000,
+    0x3fe9c49182a3f15b, 0x3d26b80000000000,
+    0x3fe9d674194bb8c5, 0xbcec000000000000,
+    0x3fe9e86319e3238e, 0x3d17d00000000000,
+    0x3fe9fa5e8d07f302, 0x3d16400000000000,
+    0x3fea0c667b5de54d, 0xbcf5000000000000,
+    0x3fea1e7aed8eb8f6, 0x3d09e00000000000,
+    0x3fea309bec4a2e27, 0x3d2ad80000000000,
+    0x3fea42c980460a5d, 0xbd1af00000000000,
+    0x3fea5503b23e259b, 0x3d0b600000000000,
+    0x3fea674a8af46213, 0x3d38880000000000,
+    0x3fea799e1330b3a7, 0x3d11200000000000,
+    0x3fea8bfe53c12e8d, 0x3d06c00000000000,
+    0x3fea9e6b5579fcd2, 0xbd29b80000000000,
+    0x3feab0e521356fb8, 0x3d2b700000000000,
+    0x3feac36bbfd3f381, 0x3cd9000000000000,
+    0x3fead5ff3a3c2780, 0x3ce4000000000000,
+    0x3feae89f995ad2a3, 0xbd2c900000000000,
+    0x3feafb4ce622f367, 0x3d16500000000000,
+    0x3feb0e07298db790, 0x3d2fd40000000000,
+    0x3feb20ce6c9a89a9, 0x3d12700000000000,
+    0x3feb33a2b84f1a4b, 0x3d4d470000000000,
+    0x3feb468415b747e7, 0xbd38380000000000,
+    0x3feb59728de5593a, 0x3c98000000000000,
+    0x3feb6c6e29f1c56a, 0x3d0ad00000000000,
+    0x3feb7f76f2fb5e50, 0x3cde800000000000,
+    0x3feb928cf22749b2, 0xbd04c00000000000,
+    0x3feba5b030a10603, 0xbd0d700000000000,
+    0x3febb8e0b79a6f66, 0x3d0d900000000000,
+    0x3febcc1e904bc1ff, 0x3d02a00000000000,
+    0x3febdf69c3f3a16f, 0xbd1f780000000000,
+    0x3febf2c25bd71db8, 0xbd10a00000000000,
+    0x3fec06286141b2e9, 0xbd11400000000000,
+    0x3fec199bdd8552e0, 0x3d0be00000000000,
+    0x3fec2d1cd9fa64ee, 0xbd09400000000000,
+    0x3fec40ab5fffd02f, 0xbd0ed00000000000,
+    0x3fec544778fafd15, 0x3d39660000000000,
+    0x3fec67f12e57d0cb, 0xbd1a100000000000,
+    0x3fec7ba88988c1b6, 0xbd58458000000000,
+    0x3fec8f6d9406e733, 0xbd1a480000000000,
+    0x3feca3405751c4df, 0x3ccb000000000000,
+    0x3fecb720dcef9094, 0x3d01400000000000,
+    0x3feccb0f2e6d1689, 0x3cf0200000000000,
+    0x3fecdf0b555dc412, 0x3cf3600000000000,
+    0x3fecf3155b5bab3b, 0xbd06900000000000,
+    0x3fed072d4a0789bc, 0x3d09a00000000000,
+    0x3fed1b532b08c8fa, 0xbd15e00000000000,
+    0x3fed2f87080d8a85, 0x3d1d280000000000,
+    0x3fed43c8eacaa203, 0x3d01a00000000000,
+    0x3fed5818dcfba491, 0x3cdf000000000000,
+    0x3fed6c76e862e6a1, 0xbd03a00000000000,
+    0x3fed80e316c9834e, 0xbd0cd80000000000,
+    0x3fed955d71ff6090, 0x3cf4c00000000000,
+    0x3feda9e603db32ae, 0x3cff900000000000,
+    0x3fedbe7cd63a8325, 0x3ce9800000000000,
+    0x3fedd321f301b445, 0xbcf5200000000000,
+    0x3fede7d5641c05bf, 0xbd1d700000000000,
+    0x3fedfc97337b9aec, 0xbd16140000000000,
+    0x3fee11676b197d5e, 0x3d0b480000000000,
+    0x3fee264614f5a3e7, 0x3d40ce0000000000,
+    0x3fee3b333b16ee5c, 0x3d0c680000000000,
+    0x3fee502ee78b3fb4, 0xbd09300000000000,
+    0x3fee653924676d68, 0xbce5000000000000,
+    0x3fee7a51fbc74c44, 0xbd07f80000000000,
+    0x3fee8f7977cdb726, 0xbcf3700000000000,
+    0x3feea4afa2a490e8, 0x3ce5d00000000000,
+    0x3feeb9f4867ccae4, 0x3d161a0000000000,
+    0x3feecf482d8e680d, 0x3cf5500000000000,
+    0x3feee4aaa2188514, 0x3cc6400000000000,
+    0x3feefa1bee615a13, 0xbcee800000000000,
+    0x3fef0f9c1cb64106, 0xbcfa880000000000,
+    0x3fef252b376bb963, 0xbd2c900000000000,
+    0x3fef3ac948dd7275, 0x3caa000000000000,
+    0x3fef50765b6e4524, 0xbcf4f00000000000,
+    0x3fef6632798844fd, 0x3cca800000000000,
+    0x3fef7bfdad9cbe38, 0x3cfabc0000000000,
+    0x3fef91d802243c82, 0xbcd4600000000000,
+    0x3fefa7c1819e908e, 0xbd0b0c0000000000,
+    0x3fefbdba3692d511, 0xbcc0e00000000000,
+    0x3fefd3c22b8f7194, 0xbd10de8000000000,
+    0x3fefe9d96b2a23ee, 0x3cee430000000000,
+    0x3ff0000000000000, 0x0,
+    0x3ff00b1afa5abcbe, 0xbcb3400000000000,
+    0x3ff0163da9fb3303, 0xbd12170000000000,
+    0x3ff02168143b0282, 0x3cba400000000000,
+    0x3ff02c9a3e77806c, 0x3cef980000000000,
+    0x3ff037d42e11bbca, 0xbcc7400000000000,
+    0x3ff04315e86e7f89, 0x3cd8300000000000,
+    0x3ff04e5f72f65467, 0xbd1a3f0000000000,
+    0x3ff059b0d315855a, 0xbd02840000000000,
+    0x3ff0650a0e3c1f95, 0x3cf1600000000000,
+    0x3ff0706b29ddf71a, 0x3d15240000000000,
+    0x3ff07bd42b72a82d, 0xbce9a00000000000,
+    0x3ff0874518759bd0, 0x3ce6400000000000,
+    0x3ff092bdf66607c8, 0xbd00780000000000,
+    0x3ff09e3ecac6f383, 0xbc98000000000000,
+    0x3ff0a9c79b1f3930, 0x3cffa00000000000,
+    0x3ff0b5586cf988fc, 0xbcfac80000000000,
+    0x3ff0c0f145e46c8a, 0x3cd9c00000000000,
+    0x3ff0cc922b724816, 0x3d05200000000000,
+    0x3ff0d83b23395dd8, 0xbcfad00000000000,
+    0x3ff0e3ec32d3d1f3, 0x3d1bac0000000000,
+    0x3ff0efa55fdfa9a6, 0xbd04e80000000000,
+    0x3ff0fb66affed2f0, 0xbd0d300000000000,
+    0x3ff1073028d7234b, 0x3cf1500000000000,
+    0x3ff11301d0125b5b, 0x3cec000000000000,
+    0x3ff11edbab5e2af9, 0x3d16bc0000000000,
+    0x3ff12abdc06c31d5, 0x3ce8400000000000,
+    0x3ff136a814f2047d, 0xbd0ed00000000000,
+    0x3ff1429aaea92de9, 0x3ce8e00000000000,
+    0x3ff14e95934f3138, 0x3ceb400000000000,
+    0x3ff15a98c8a58e71, 0x3d05300000000000,
+    0x3ff166a45471c3df, 0x3d03380000000000,
+    0x3ff172b83c7d5211, 0x3d28d40000000000,
+    0x3ff17ed48695bb9f, 0xbd05d00000000000,
+    0x3ff18af9388c8d93, 0xbd1c880000000000,
+    0x3ff1972658375d66, 0x3d11f00000000000,
+    0x3ff1a35beb6fcba7, 0x3d10480000000000,
+    0x3ff1af99f81387e3, 0xbd47390000000000,
+    0x3ff1bbe084045d54, 0x3d24e40000000000,
+    0x3ff1c82f95281c43, 0xbd0a200000000000,
+    0x3ff1d4873168b9b2, 0x3ce3800000000000,
+    0x3ff1e0e75eb44031, 0x3ceac00000000000,
+    0x3ff1ed5022fcd938, 0x3d01900000000000,
+    0x3ff1f9c18438cdf7, 0xbd1b780000000000,
+    0x3ff2063b88628d8f, 0x3d2d940000000000,
+    0x3ff212be3578a81e, 0x3cd8000000000000,
+    0x3ff21f49917ddd41, 0x3d2b340000000000,
+    0x3ff22bdda2791323, 0x3d19f80000000000,
+    0x3ff2387a6e7561e7, 0xbd19c80000000000,
+    0x3ff2451ffb821427, 0x3d02300000000000,
+    0x3ff251ce4fb2a602, 0xbd13480000000000,
+    0x3ff25e85711eceb0, 0x3d12700000000000,
+    0x3ff26b4565e27d16, 0x3d11d00000000000,
+    0x3ff2780e341de00f, 0x3d31ee0000000000,
+    0x3ff284dfe1f5633e, 0xbd14c00000000000,
+    0x3ff291ba7591bb30, 0xbd13d80000000000,
+    0x3ff29e9df51fdf09, 0x3d08b00000000000,
+    0x3ff2ab8a66d10e9b, 0xbd227c0000000000,
+    0x3ff2b87fd0dada3a, 0x3d2a340000000000,
+    0x3ff2c57e39771af9, 0xbd10800000000000,
+    0x3ff2d285a6e402d9, 0xbd0ed00000000000,
+    0x3ff2df961f641579, 0xbcf4200000000000,
+    0x3ff2ecafa93e2ecf, 0xbd24980000000000,
+    0x3ff2f9d24abd8822, 0xbd16300000000000,
+    0x3ff306fe0a31b625, 0xbd32360000000000,
+    0x3ff31432edeea50b, 0xbd70df8000000000,
+    0x3ff32170fc4cd7b8, 0xbd22480000000000,
+    0x3ff32eb83ba8e9a2, 0xbd25980000000000,
+    0x3ff33c08b2641766, 0x3d1ed00000000000,
+    0x3ff3496266e3fa27, 0xbcdc000000000000,
+    0x3ff356c55f929f0f, 0xbd30d80000000000,
+    0x3ff36431a2de88b9, 0x3d22c80000000000,
+    0x3ff371a7373aaa39, 0x3d20600000000000,
+    0x3ff37f26231e74fe, 0xbd16600000000000,
+    0x3ff38cae6d05d838, 0xbd0ae00000000000,
+    0x3ff39a401b713ec3, 0xbd44720000000000,
+    0x3ff3a7db34e5a020, 0x3d08200000000000,
+    0x3ff3b57fbfec6e95, 0x3d3e800000000000,
+    0x3ff3c32dc313a8f2, 0x3cef800000000000,
+    0x3ff3d0e544ede122, 0xbd17a00000000000,
+    0x3ff3dea64c1234bb, 0x3d26300000000000,
+    0x3ff3ec70df1c4ecc, 0xbd48a60000000000,
+    0x3ff3fa4504ac7e8c, 0xbd3cdc0000000000,
+    0x3ff40822c367a0bb, 0x3d25b80000000000,
+    0x3ff4160a21f72e95, 0x3d1ec00000000000,
+    0x3ff423fb27094646, 0xbd13600000000000,
+    0x3ff431f5d950a920, 0x3d23980000000000,
+    0x3ff43ffa3f84b9eb, 0x3cfa000000000000,
+    0x3ff44e0860618919, 0xbcf6c00000000000,
+    0x3ff45c2042a7d201, 0xbd0bc00000000000,
+    0x3ff46a41ed1d0016, 0xbd12800000000000,
+    0x3ff4786d668b3326, 0x3d30e00000000000,
+    0x3ff486a2b5c13c00, 0xbd2d400000000000,
+    0x3ff494e1e192af04, 0x3d0c200000000000,
+    0x3ff4a32af0d7d372, 0xbd1e500000000000,
+    0x3ff4b17dea6db801, 0x3d07800000000000,
+    0x3ff4bfdad53629e1, 0xbd13800000000000,
+    0x3ff4ce41b817c132, 0x3d00800000000000,
+    0x3ff4dcb299fddddb, 0x3d2c700000000000,
+    0x3ff4eb2d81d8ab96, 0xbd1ce00000000000,
+    0x3ff4f9b2769d2d02, 0x3d19200000000000,
+    0x3ff508417f4531c1, 0xbd08c00000000000,
+    0x3ff516daa2cf662a, 0xbcfa000000000000,
+    0x3ff5257de83f51ea, 0x3d4a080000000000,
+    0x3ff5342b569d4eda, 0xbd26d80000000000,
+    0x3ff542e2f4f6ac1a, 0xbd32440000000000,
+    0x3ff551a4ca5d94db, 0x3d483c0000000000,
+    0x3ff56070dde9116b, 0x3d24b00000000000,
+    0x3ff56f4736b529de, 0x3d415a0000000000,
+    0x3ff57e27dbe2c40e, 0xbd29e00000000000,
+    0x3ff58d12d497c76f, 0xbd23080000000000,
+    0x3ff59c0827ff0b4c, 0x3d4dec0000000000,
+    0x3ff5ab07dd485427, 0xbcc4000000000000,
+    0x3ff5ba11fba87af4, 0x3d30080000000000,
+    0x3ff5c9268a59460b, 0xbd26c80000000000,
+    0x3ff5d84590998e3f, 0x3d469a0000000000,
+    0x3ff5e76f15ad20e1, 0xbd1b400000000000,
+    0x3ff5f6a320dcebca, 0x3d17700000000000,
+    0x3ff605e1b976dcb8, 0x3d26f80000000000,
+    0x3ff6152ae6cdf715, 0x3d01000000000000,
+    0x3ff6247eb03a5531, 0xbd15d00000000000,
+    0x3ff633dd1d1929b5, 0xbd12d00000000000,
+    0x3ff6434634ccc313, 0xbcea800000000000,
+    0x3ff652b9febc8efa, 0xbd28600000000000,
+    0x3ff6623882553397, 0x3d71fe0000000000,
+    0x3ff671c1c708328e, 0xbd37200000000000,
+    0x3ff68155d44ca97e, 0x3ce6800000000000,
+    0x3ff690f4b19e9471, 0xbd29780000000000,
+];
+
+// exp2(x): compute the base 2 exponential of x
+//
+// Accuracy: Peak error < 0.503 ulp for normalized results.
+//
+// Method: (accurate tables)
+//
+//   Reduce x:
+//     x = k + y, for integer k and |y| <= 1/2.
+//     Thus we have exp2(x) = 2**k * exp2(y).
+//
+//   Reduce y:
+//     y = i/TBLSIZE + z - eps[i] for integer i near y * TBLSIZE.
+//     Thus we have exp2(y) = exp2(i/TBLSIZE) * exp2(z - eps[i]),
+//     with |z - eps[i]| <= 2**-9 + 2**-39 for the table used.
+//
+//   We compute exp2(i/TBLSIZE) via table lookup and exp2(z - eps[i]) via
+//   a degree-5 minimax polynomial with maximum error under 1.3 * 2**-61.
+//   The values in exp2t[] and eps[] are chosen such that
+//   exp2t[i] = exp2(i/TBLSIZE + eps[i]), and eps[i] is a small offset such
+//   that exp2t[i] is accurate to 2**-64.
+//
+//   Note that the range of i is +-TBLSIZE/2, so we actually index the tables
+//   by i0 = i + TBLSIZE/2.  For cache efficiency, exp2t[] and eps[] are
+//   virtual tables, interleaved in the real table tbl[].
+//
+//   This method is due to Gal, with many details due to Gal and Bachelis:
+//
+//      Gal, S. and Bachelis, B.  An Accurate Elementary Mathematical Library
+//      for the IEEE Floating Point Standard.  TOMS 17(1), 26-46 (1991).
+
+/// Exponential, base 2 (f64)
+///
+/// Calculate `2^x`, that is, 2 raised to the power `x`.
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn exp2(mut x: f64) -> f64 {
+    let redux = f64::from_bits(0x4338000000000000) / TBLSIZE as f64;
+    let p1 = f64::from_bits(0x3fe62e42fefa39ef);
+    let p2 = f64::from_bits(0x3fcebfbdff82c575);
+    let p3 = f64::from_bits(0x3fac6b08d704a0a6);
+    let p4 = f64::from_bits(0x3f83b2ab88f70400);
+    let p5 = f64::from_bits(0x3f55d88003875c74);
+
+    // double_t r, t, z;
+    // uint32_t ix, i0;
+    // union {double f; uint64_t i;} u = {x};
+    // union {uint32_t u; int32_t i;} k;
+    let x1p1023 = f64::from_bits(0x7fe0000000000000);
+    let x1p52 = f64::from_bits(0x4330000000000000);
+    let _0x1p_149 = f64::from_bits(0xb6a0000000000000);
+
+    /* Filter out exceptional cases. */
+    let ui = f64::to_bits(x);
+    let ix = ui >> 32 & 0x7fffffff;
+    if ix >= 0x408ff000 {
+        /* |x| >= 1022 or nan */
+        if ix >= 0x40900000 && ui >> 63 == 0 {
+            /* x >= 1024 or nan */
+            /* overflow */
+            x *= x1p1023;
+            return x;
+        }
+        if ix >= 0x7ff00000 {
+            /* -inf or -nan */
+            return -1.0 / x;
+        }
+        if ui >> 63 != 0 {
+            /* x <= -1022 */
+            /* underflow */
+            if x <= -1075.0 || x - x1p52 + x1p52 != x {
+                force_eval!((_0x1p_149 / x) as f32);
+            }
+            if x <= -1075.0 {
+                return 0.0;
+            }
+        }
+    } else if ix < 0x3c900000 {
+        /* |x| < 0x1p-54 */
+        return 1.0 + x;
+    }
+
+    /* Reduce x, computing z, i0, and k. */
+    let ui = f64::to_bits(x + redux);
+    let mut i0 = ui as u32;
+    i0 = i0.wrapping_add(TBLSIZE as u32 / 2);
+    let ku = i0 / TBLSIZE as u32 * TBLSIZE as u32;
+    let ki = ku as i32 / TBLSIZE as i32;
+    i0 %= TBLSIZE as u32;
+    let uf = f64::from_bits(ui) - redux;
+    let mut z = x - uf;
+
+    /* Compute r = exp2(y) = exp2t[i0] * p(z - eps[i]). */
+    let t = f64::from_bits(TBL[2 * i0 as usize]); /* exp2t[i0] */
+    z -= f64::from_bits(TBL[2 * i0 as usize + 1]); /* eps[i0]   */
+    let r = t + t * z * (p1 + z * (p2 + z * (p3 + z * (p4 + z * p5))));
+
+    scalbn(r, ki)
+}
+
+#[test]
+fn i0_wrap_test() {
+    let x = -3.0 / 256.0;
+    assert_eq!(exp2(x), f64::from_bits(0x3fefbdba3692d514));
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/exp2f.rs.html b/src/libm/math/exp2f.rs.html new file mode 100644 index 000000000..aeecb67bd --- /dev/null +++ b/src/libm/math/exp2f.rs.html @@ -0,0 +1,275 @@ +exp2f.rs.html -- source
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+// origin: FreeBSD /usr/src/lib/msun/src/s_exp2f.c
+//-
+// Copyright (c) 2005 David Schultz <das@FreeBSD.ORG>
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+// 1. Redistributions of source code must retain the above copyright
+//    notice, this list of conditions and the following disclaimer.
+// 2. Redistributions in binary form must reproduce the above copyright
+//    notice, this list of conditions and the following disclaimer in the
+//    documentation and/or other materials provided with the distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+// OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+// LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+// OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+// SUCH DAMAGE.
+
+const TBLSIZE: usize = 16;
+
+static EXP2FT: [u64; TBLSIZE] = [
+    0x3fe6a09e667f3bcd,
+    0x3fe7a11473eb0187,
+    0x3fe8ace5422aa0db,
+    0x3fe9c49182a3f090,
+    0x3feae89f995ad3ad,
+    0x3fec199bdd85529c,
+    0x3fed5818dcfba487,
+    0x3feea4afa2a490da,
+    0x3ff0000000000000,
+    0x3ff0b5586cf9890f,
+    0x3ff172b83c7d517b,
+    0x3ff2387a6e756238,
+    0x3ff306fe0a31b715,
+    0x3ff3dea64c123422,
+    0x3ff4bfdad5362a27,
+    0x3ff5ab07dd485429,
+];
+
+// exp2f(x): compute the base 2 exponential of x
+//
+// Accuracy: Peak error < 0.501 ulp; location of peak: -0.030110927.
+//
+// Method: (equally-spaced tables)
+//
+//   Reduce x:
+//     x = k + y, for integer k and |y| <= 1/2.
+//     Thus we have exp2f(x) = 2**k * exp2(y).
+//
+//   Reduce y:
+//     y = i/TBLSIZE + z for integer i near y * TBLSIZE.
+//     Thus we have exp2(y) = exp2(i/TBLSIZE) * exp2(z),
+//     with |z| <= 2**-(TBLSIZE+1).
+//
+//   We compute exp2(i/TBLSIZE) via table lookup and exp2(z) via a
+//   degree-4 minimax polynomial with maximum error under 1.4 * 2**-33.
+//   Using double precision for everything except the reduction makes
+//   roundoff error insignificant and simplifies the scaling step.
+//
+//   This method is due to Tang, but I do not use his suggested parameters:
+//
+//      Tang, P.  Table-driven Implementation of the Exponential Function
+//      in IEEE Floating-Point Arithmetic.  TOMS 15(2), 144-157 (1989).
+
+/// Exponential, base 2 (f32)
+///
+/// Calculate `2^x`, that is, 2 raised to the power `x`.
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn exp2f(mut x: f32) -> f32 {
+    let redux = f32::from_bits(0x4b400000) / TBLSIZE as f32;
+    let p1 = f32::from_bits(0x3f317218);
+    let p2 = f32::from_bits(0x3e75fdf0);
+    let p3 = f32::from_bits(0x3d6359a4);
+    let p4 = f32::from_bits(0x3c1d964e);
+
+    // double_t t, r, z;
+    // uint32_t ix, i0, k;
+
+    let x1p127 = f32::from_bits(0x7f000000);
+
+    /* Filter out exceptional cases. */
+    let ui = f32::to_bits(x);
+    let ix = ui & 0x7fffffff;
+    if ix > 0x42fc0000 {
+        /* |x| > 126 */
+        if ix > 0x7f800000 {
+            /* NaN */
+            return x;
+        }
+        if ui >= 0x43000000 && ui < 0x80000000 {
+            /* x >= 128 */
+            x *= x1p127;
+            return x;
+        }
+        if ui >= 0x80000000 {
+            /* x < -126 */
+            if ui >= 0xc3160000 || (ui & 0x0000ffff != 0) {
+                force_eval!(f32::from_bits(0x80000001) / x);
+            }
+            if ui >= 0xc3160000 {
+                /* x <= -150 */
+                return 0.0;
+            }
+        }
+    } else if ix <= 0x33000000 {
+        /* |x| <= 0x1p-25 */
+        return 1.0 + x;
+    }
+
+    /* Reduce x, computing z, i0, and k. */
+    let ui = f32::to_bits(x + redux);
+    let mut i0 = ui;
+    i0 += TBLSIZE as u32 / 2;
+    let k = i0 / TBLSIZE as u32;
+    let ukf = f64::from_bits(((0x3ff + k) as u64) << 52);
+    i0 &= TBLSIZE as u32 - 1;
+    let mut uf = f32::from_bits(ui);
+    uf -= redux;
+    let z: f64 = (x - uf) as f64;
+    /* Compute r = exp2(y) = exp2ft[i0] * p(z). */
+    let r: f64 = f64::from_bits(EXP2FT[i0 as usize]);
+    let t: f64 = r as f64 * z;
+    let r: f64 = r + t * (p1 as f64 + z * p2 as f64) + t * (z * z) * (p3 as f64 + z * p4 as f64);
+
+    /* Scale by 2**k */
+    (r * ukf) as f32
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/expf.rs.html b/src/libm/math/expf.rs.html new file mode 100644 index 000000000..7b86caed8 --- /dev/null +++ b/src/libm/math/expf.rs.html @@ -0,0 +1,207 @@ +expf.rs.html -- source
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+/* origin: FreeBSD /usr/src/lib/msun/src/e_expf.c */
+/*
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+use super::scalbnf;
+
+const HALF: [f32; 2] = [0.5, -0.5];
+const LN2_HI: f32 = 6.9314575195e-01; /* 0x3f317200 */
+const LN2_LO: f32 = 1.4286067653e-06; /* 0x35bfbe8e */
+const INV_LN2: f32 = 1.4426950216e+00; /* 0x3fb8aa3b */
+/*
+ * Domain [-0.34568, 0.34568], range ~[-4.278e-9, 4.447e-9]:
+ * |x*(exp(x)+1)/(exp(x)-1) - p(x)| < 2**-27.74
+ */
+const P1: f32 = 1.6666625440e-1; /*  0xaaaa8f.0p-26 */
+const P2: f32 = -2.7667332906e-3; /* -0xb55215.0p-32 */
+
+/// Exponential, base *e* (f32)
+///
+/// Calculate the exponential of `x`, that is, *e* raised to the power `x`
+/// (where *e* is the base of the natural system of logarithms, approximately 2.71828).
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn expf(mut x: f32) -> f32 {
+    let x1p127 = f32::from_bits(0x7f000000); // 0x1p127f === 2 ^ 127
+    let x1p_126 = f32::from_bits(0x800000); // 0x1p-126f === 2 ^ -126  /*original 0x1p-149f    ??????????? */
+    let mut hx = x.to_bits();
+    let sign = (hx >> 31) as i32; /* sign bit of x */
+    let signb: bool = sign != 0;
+    hx &= 0x7fffffff; /* high word of |x| */
+
+    /* special cases */
+    if hx >= 0x42aeac50 {
+        /* if |x| >= -87.33655f or NaN */
+        if hx > 0x7f800000 {
+            /* NaN */
+            return x;
+        }
+        if (hx >= 0x42b17218) && (!signb) {
+            /* x >= 88.722839f */
+            /* overflow */
+            x *= x1p127;
+            return x;
+        }
+        if signb {
+            /* underflow */
+            force_eval!(-x1p_126 / x);
+            if hx >= 0x42cff1b5 {
+                /* x <= -103.972084f */
+                return 0.;
+            }
+        }
+    }
+
+    /* argument reduction */
+    let k: i32;
+    let hi: f32;
+    let lo: f32;
+    if hx > 0x3eb17218 {
+        /* if |x| > 0.5 ln2 */
+        if hx > 0x3f851592 {
+            /* if |x| > 1.5 ln2 */
+            k = (INV_LN2 * x + HALF[sign as usize]) as i32;
+        } else {
+            k = 1 - sign - sign;
+        }
+        let kf = k as f32;
+        hi = x - kf * LN2_HI; /* k*ln2hi is exact here */
+        lo = kf * LN2_LO;
+        x = hi - lo;
+    } else if hx > 0x39000000 {
+        /* |x| > 2**-14 */
+        k = 0;
+        hi = x;
+        lo = 0.;
+    } else {
+        /* raise inexact */
+        force_eval!(x1p127 + x);
+        return 1. + x;
+    }
+
+    /* x is now in primary range */
+    let xx = x * x;
+    let c = x - xx * (P1 + xx * P2);
+    let y = 1. + (x * c / (2. - c) - lo + hi);
+    if k == 0 {
+        y
+    } else {
+        scalbnf(y, k)
+    }
+}
+
+
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+
+/* origin: FreeBSD /usr/src/lib/msun/src/s_expm1.c */
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+use core::f64;
+
+const O_THRESHOLD: f64 = 7.09782712893383973096e+02; /* 0x40862E42, 0xFEFA39EF */
+const LN2_HI: f64 = 6.93147180369123816490e-01; /* 0x3fe62e42, 0xfee00000 */
+const LN2_LO: f64 = 1.90821492927058770002e-10; /* 0x3dea39ef, 0x35793c76 */
+const INVLN2: f64 = 1.44269504088896338700e+00; /* 0x3ff71547, 0x652b82fe */
+/* Scaled Q's: Qn_here = 2**n * Qn_above, for R(2*z) where z = hxs = x*x/2: */
+const Q1: f64 = -3.33333333333331316428e-02; /* BFA11111 111110F4 */
+const Q2: f64 = 1.58730158725481460165e-03; /* 3F5A01A0 19FE5585 */
+const Q3: f64 = -7.93650757867487942473e-05; /* BF14CE19 9EAADBB7 */
+const Q4: f64 = 4.00821782732936239552e-06; /* 3ED0CFCA 86E65239 */
+const Q5: f64 = -2.01099218183624371326e-07; /* BE8AFDB7 6E09C32D */
+
+/// Exponential, base *e*, of x-1 (f64)
+///
+/// Calculates the exponential of `x` and subtract 1, that is, *e* raised
+/// to the power `x` minus 1 (where *e* is the base of the natural
+/// system of logarithms, approximately 2.71828).
+/// The result is accurate even for small values of `x`,
+/// where using `exp(x)-1` would lose many significant digits.
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn expm1(mut x: f64) -> f64 {
+    let hi: f64;
+    let lo: f64;
+    let k: i32;
+    let c: f64;
+    let mut t: f64;
+    let mut y: f64;
+
+    let mut ui = x.to_bits();
+    let hx = ((ui >> 32) & 0x7fffffff) as u32;
+    let sign = (ui >> 63) as i32;
+
+    /* filter out huge and non-finite argument */
+    if hx >= 0x4043687A {
+        /* if |x|>=56*ln2 */
+        if x.is_nan() {
+            return x;
+        }
+        if sign != 0 {
+            return -1.0;
+        }
+        if x > O_THRESHOLD {
+            x *= f64::from_bits(0x7fe0000000000000);
+            return x;
+        }
+    }
+
+    /* argument reduction */
+    if hx > 0x3fd62e42 {
+        /* if  |x| > 0.5 ln2 */
+        if hx < 0x3FF0A2B2 {
+            /* and |x| < 1.5 ln2 */
+            if sign == 0 {
+                hi = x - LN2_HI;
+                lo = LN2_LO;
+                k = 1;
+            } else {
+                hi = x + LN2_HI;
+                lo = -LN2_LO;
+                k = -1;
+            }
+        } else {
+            k = (INVLN2 * x + if sign != 0 { -0.5 } else { 0.5 }) as i32;
+            t = k as f64;
+            hi = x - t * LN2_HI; /* t*ln2_hi is exact here */
+            lo = t * LN2_LO;
+        }
+        x = hi - lo;
+        c = (hi - x) - lo;
+    } else if hx < 0x3c900000 {
+        /* |x| < 2**-54, return x */
+        if hx < 0x00100000 {
+            force_eval!(x);
+        }
+        return x;
+    } else {
+        c = 0.0;
+        k = 0;
+    }
+
+    /* x is now in primary range */
+    let hfx = 0.5 * x;
+    let hxs = x * hfx;
+    let r1 = 1.0 + hxs * (Q1 + hxs * (Q2 + hxs * (Q3 + hxs * (Q4 + hxs * Q5))));
+    t = 3.0 - r1 * hfx;
+    let mut e = hxs * ((r1 - t) / (6.0 - x * t));
+    if k == 0 {
+        /* c is 0 */
+        return x - (x * e - hxs);
+    }
+    e = x * (e - c) - c;
+    e -= hxs;
+    /* exp(x) ~ 2^k (x_reduced - e + 1) */
+    if k == -1 {
+        return 0.5 * (x - e) - 0.5;
+    }
+    if k == 1 {
+        if x < -0.25 {
+            return -2.0 * (e - (x + 0.5));
+        }
+        return 1.0 + 2.0 * (x - e);
+    }
+    ui = ((0x3ff + k) as u64) << 52; /* 2^k */
+    let twopk = f64::from_bits(ui);
+    if k < 0 || k > 56 {
+        /* suffice to return exp(x)-1 */
+        y = x - e + 1.0;
+        if k == 1024 {
+            y = y * 2.0 * f64::from_bits(0x7fe0000000000000);
+        } else {
+            y = y * twopk;
+        }
+        return y - 1.0;
+    }
+    ui = ((0x3ff - k) as u64) << 52; /* 2^-k */
+    let uf = f64::from_bits(ui);
+    if k < 20 {
+        y = (x - e + (1.0 - uf)) * twopk;
+    } else {
+        y = (x - (e + uf) + 1.0) * twopk;
+    }
+    y
+}
+
+#[cfg(test)]
+mod tests {
+    #[test]
+    fn sanity_check() {
+        assert_eq!(super::expm1(1.1), 2.0041660239464334);
+    }
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/expm1f.rs.html b/src/libm/math/expm1f.rs.html new file mode 100644 index 000000000..74703b4e7 --- /dev/null +++ b/src/libm/math/expm1f.rs.html @@ -0,0 +1,273 @@ +expm1f.rs.html -- source
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+
+/* origin: FreeBSD /usr/src/lib/msun/src/s_expm1f.c */
+/*
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+const O_THRESHOLD: f32 = 8.8721679688e+01; /* 0x42b17180 */
+const LN2_HI: f32 = 6.9313812256e-01; /* 0x3f317180 */
+const LN2_LO: f32 = 9.0580006145e-06; /* 0x3717f7d1 */
+const INV_LN2: f32 = 1.4426950216e+00; /* 0x3fb8aa3b */
+/*
+ * Domain [-0.34568, 0.34568], range ~[-6.694e-10, 6.696e-10]:
+ * |6 / x * (1 + 2 * (1 / (exp(x) - 1) - 1 / x)) - q(x)| < 2**-30.04
+ * Scaled coefficients: Qn_here = 2**n * Qn_for_q (see s_expm1.c):
+ */
+const Q1: f32 = -3.3333212137e-2; /* -0x888868.0p-28 */
+const Q2: f32 = 1.5807170421e-3; /*  0xcf3010.0p-33 */
+
+/// Exponential, base *e*, of x-1 (f32)
+///
+/// Calculates the exponential of `x` and subtract 1, that is, *e* raised
+/// to the power `x` minus 1 (where *e* is the base of the natural
+/// system of logarithms, approximately 2.71828).
+/// The result is accurate even for small values of `x`,
+/// where using `exp(x)-1` would lose many significant digits.
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn expm1f(mut x: f32) -> f32 {
+    let x1p127 = f32::from_bits(0x7f000000); // 0x1p127f === 2 ^ 127
+
+    let mut hx = x.to_bits();
+    let sign = (hx >> 31) != 0;
+    hx &= 0x7fffffff;
+
+    /* filter out huge and non-finite argument */
+    if hx >= 0x4195b844 {
+        /* if |x|>=27*ln2 */
+        if hx > 0x7f800000 {
+            /* NaN */
+            return x;
+        }
+        if sign {
+            return -1.;
+        }
+        if x > O_THRESHOLD {
+            x *= x1p127;
+            return x;
+        }
+    }
+
+    let k: i32;
+    let hi: f32;
+    let lo: f32;
+    let mut c = 0f32;
+    /* argument reduction */
+    if hx > 0x3eb17218 {
+        /* if  |x| > 0.5 ln2 */
+        if hx < 0x3F851592 {
+            /* and |x| < 1.5 ln2 */
+            if !sign {
+                hi = x - LN2_HI;
+                lo = LN2_LO;
+                k = 1;
+            } else {
+                hi = x + LN2_HI;
+                lo = -LN2_LO;
+                k = -1;
+            }
+        } else {
+            k = (INV_LN2 * x + (if sign { -0.5 } else { 0.5 })) as i32;
+            let t = k as f32;
+            hi = x - t * LN2_HI; /* t*ln2_hi is exact here */
+            lo = t * LN2_LO;
+        }
+        x = hi - lo;
+        c = (hi - x) - lo;
+    } else if hx < 0x33000000 {
+        /* when |x|<2**-25, return x */
+        if hx < 0x00800000 {
+            force_eval!(x * x);
+        }
+        return x;
+    } else {
+        k = 0;
+    }
+
+    /* x is now in primary range */
+    let hfx = 0.5 * x;
+    let hxs = x * hfx;
+    let r1 = 1. + hxs * (Q1 + hxs * Q2);
+    let t = 3. - r1 * hfx;
+    let mut e = hxs * ((r1 - t) / (6. - x * t));
+    if k == 0 {
+        /* c is 0 */
+        return x - (x * e - hxs);
+    }
+    e = x * (e - c) - c;
+    e -= hxs;
+    /* exp(x) ~ 2^k (x_reduced - e + 1) */
+    if k == -1 {
+        return 0.5 * (x - e) - 0.5;
+    }
+    if k == 1 {
+        if x < -0.25 {
+            return -2. * (e - (x + 0.5));
+        }
+        return 1. + 2. * (x - e);
+    }
+    let twopk = f32::from_bits(((0x7f + k) << 23) as u32); /* 2^k */
+    if (k < 0) || (k > 56) {
+        /* suffice to return exp(x)-1 */
+        let mut y = x - e + 1.;
+        if k == 128 {
+            y = y * 2. * x1p127;
+        } else {
+            y = y * twopk;
+        }
+        return y - 1.;
+    }
+    let uf = f32::from_bits(((0x7f - k) << 23) as u32); /* 2^-k */
+    if k < 23 {
+        (x - e + (1. - uf)) * twopk
+    } else {
+        (x - (e + uf) + 1.) * twopk
+    }
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/expo2.rs.html b/src/libm/math/expo2.rs.html new file mode 100644 index 000000000..5fde6a244 --- /dev/null +++ b/src/libm/math/expo2.rs.html @@ -0,0 +1,33 @@ +expo2.rs.html -- source
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+use super::{combine_words, exp};
+
+/* exp(x)/2 for x >= log(DBL_MAX), slightly better than 0.5*exp(x/2)*exp(x/2) */
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub(crate) fn expo2(x: f64) -> f64 {
+    /* k is such that k*ln2 has minimal relative error and x - kln2 > log(DBL_MIN) */
+    const K: i32 = 2043;
+    let kln2 = f64::from_bits(0x40962066151add8b);
+
+    /* note that k is odd and scale*scale overflows */
+    let scale = combine_words(((0x3ff + K / 2) as u32) << 20, 0);
+    /* exp(x - k ln2) * 2**(k-1) */
+    exp(x - kln2) * scale * scale
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/fabs.rs.html b/src/libm/math/fabs.rs.html new file mode 100644 index 000000000..b53ee9ad9 --- /dev/null +++ b/src/libm/math/fabs.rs.html @@ -0,0 +1,39 @@ +fabs.rs.html -- source
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+use core::u64;
+
+/// Absolute value (magnitude) (f64)
+/// Calculates the absolute value (magnitude) of the argument `x`,
+/// by direct manipulation of the bit representation of `x`.
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn fabs(x: f64) -> f64 {
+    // On wasm32 we know that LLVM's intrinsic will compile to an optimized
+    // `f64.abs` native instruction, so we can leverage this for both code size
+    // and speed.
+    llvm_intrinsically_optimized! {
+        #[cfg(target_arch = "wasm32")] {
+            return unsafe { ::core::intrinsics::fabsf64(x) }
+        }
+    }
+    f64::from_bits(x.to_bits() & (u64::MAX / 2))
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/fabsf.rs.html b/src/libm/math/fabsf.rs.html new file mode 100644 index 000000000..b64b63a33 --- /dev/null +++ b/src/libm/math/fabsf.rs.html @@ -0,0 +1,35 @@ +fabsf.rs.html -- source
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+
+/// Absolute value (magnitude) (f32)
+/// Calculates the absolute value (magnitude) of the argument `x`,
+/// by direct manipulation of the bit representation of `x`.
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn fabsf(x: f32) -> f32 {
+    // On wasm32 we know that LLVM's intrinsic will compile to an optimized
+    // `f32.abs` native instruction, so we can leverage this for both code size
+    // and speed.
+    llvm_intrinsically_optimized! {
+        #[cfg(target_arch = "wasm32")] {
+            return unsafe { ::core::intrinsics::fabsf32(x) }
+        }
+    }
+    f32::from_bits(x.to_bits() & 0x7fffffff)
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/fdim.rs.html b/src/libm/math/fdim.rs.html new file mode 100644 index 000000000..f8495786f --- /dev/null +++ b/src/libm/math/fdim.rs.html @@ -0,0 +1,49 @@ +fdim.rs.html -- source
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+
+use core::f64;
+
+/// Positive difference (f64)
+///
+/// Determines the positive difference between arguments, returning:
+/// * x - y	if x > y, or
+/// * +0	if x <= y, or
+/// * NAN	if either argument is NAN.
+///
+/// A range error may occur.
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn fdim(x: f64, y: f64) -> f64 {
+    if x.is_nan() {
+        x
+    } else if y.is_nan() {
+        y
+    } else if x > y {
+        x - y
+    } else {
+        0.0
+    }
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/fdimf.rs.html b/src/libm/math/fdimf.rs.html new file mode 100644 index 000000000..0a09c3cab --- /dev/null +++ b/src/libm/math/fdimf.rs.html @@ -0,0 +1,49 @@ +fdimf.rs.html -- source
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+use core::f32;
+
+/// Positive difference (f32)
+///
+/// Determines the positive difference between arguments, returning:
+/// * x - y	if x > y, or
+/// * +0	if x <= y, or
+/// * NAN	if either argument is NAN.
+///
+/// A range error may occur.
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn fdimf(x: f32, y: f32) -> f32 {
+    if x.is_nan() {
+        x
+    } else if y.is_nan() {
+        y
+    } else if x > y {
+        x - y
+    } else {
+        0.0
+    }
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/fenv.rs.html b/src/libm/math/fenv.rs.html new file mode 100644 index 000000000..1ff786e03 --- /dev/null +++ b/src/libm/math/fenv.rs.html @@ -0,0 +1,69 @@ +fenv.rs.html -- source
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+// src: musl/src/fenv/fenv.c
+/* Dummy functions for archs lacking fenv implementation */
+
+pub const FE_UNDERFLOW: i32 = 0;
+pub const FE_INEXACT: i32 = 0;
+
+pub const FE_TONEAREST: i32 = 0;
+pub const FE_TOWARDZERO: i32 = 0;
+
+#[inline]
+pub fn feclearexcept(_mask: i32) -> i32 {
+    0
+}
+
+#[inline]
+pub fn feraiseexcept(_mask: i32) -> i32 {
+    0
+}
+
+#[inline]
+pub fn fetestexcept(_mask: i32) -> i32 {
+    0
+}
+
+#[inline]
+pub fn fegetround() -> i32 {
+    FE_TONEAREST
+}
+
+#[inline]
+pub fn fesetround(_r: i32) -> i32 {
+    0
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/floor.rs.html b/src/libm/math/floor.rs.html new file mode 100644 index 000000000..e8fae4e23 --- /dev/null +++ b/src/libm/math/floor.rs.html @@ -0,0 +1,85 @@ +floor.rs.html -- source
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+use core::f64;
+
+const TOINT: f64 = 1. / f64::EPSILON;
+
+/// Floor (f64)
+///
+/// Finds the nearest integer less than or equal to `x`.
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn floor(x: f64) -> f64 {
+    // On wasm32 we know that LLVM's intrinsic will compile to an optimized
+    // `f64.floor` native instruction, so we can leverage this for both code size
+    // and speed.
+    llvm_intrinsically_optimized! {
+        #[cfg(target_arch = "wasm32")] {
+            return unsafe { ::core::intrinsics::floorf64(x) }
+        }
+    }
+    let ui = x.to_bits();
+    let e = ((ui >> 52) & 0x7ff) as i32;
+
+    if (e >= 0x3ff + 52) || (x == 0.) {
+        return x;
+    }
+    /* y = int(x) - x, where int(x) is an integer neighbor of x */
+    let y = if (ui >> 63) != 0 {
+        x - TOINT + TOINT - x
+    } else {
+        x + TOINT - TOINT - x
+    };
+    /* special case because of non-nearest rounding modes */
+    if e < 0x3ff {
+        force_eval!(y);
+        return if (ui >> 63) != 0 { -1. } else { 0. };
+    }
+    if y > 0. {
+        x + y - 1.
+    } else {
+        x + y
+    }
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/floorf.rs.html b/src/libm/math/floorf.rs.html new file mode 100644 index 000000000..8ccd692cb --- /dev/null +++ b/src/libm/math/floorf.rs.html @@ -0,0 +1,103 @@ +floorf.rs.html -- source
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+use core::f32;
+
+/// Floor (f64)
+///
+/// Finds the nearest integer less than or equal to `x`.
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn floorf(x: f32) -> f32 {
+    // On wasm32 we know that LLVM's intrinsic will compile to an optimized
+    // `f32.floor` native instruction, so we can leverage this for both code size
+    // and speed.
+    llvm_intrinsically_optimized! {
+        #[cfg(target_arch = "wasm32")] {
+            return unsafe { ::core::intrinsics::floorf32(x) }
+        }
+    }
+    let mut ui = x.to_bits();
+    let e = (((ui >> 23) as i32) & 0xff) - 0x7f;
+
+    if e >= 23 {
+        return x;
+    }
+    if e >= 0 {
+        let m: u32 = 0x007fffff >> e;
+        if (ui & m) == 0 {
+            return x;
+        }
+        force_eval!(x + f32::from_bits(0x7b800000));
+        if ui >> 31 != 0 {
+            ui += m;
+        }
+        ui &= !m;
+    } else {
+        force_eval!(x + f32::from_bits(0x7b800000));
+        if ui >> 31 == 0 {
+            ui = 0;
+        } else if ui << 1 != 0 {
+            return -1.0;
+        }
+    }
+    f32::from_bits(ui)
+}
+
+#[cfg(test)]
+mod tests {
+    #[test]
+    fn no_overflow() {
+        assert_eq!(super::floorf(0.5), 0.0);
+    }
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/fma.rs.html b/src/libm/math/fma.rs.html new file mode 100644 index 000000000..e121900e4 --- /dev/null +++ b/src/libm/math/fma.rs.html @@ -0,0 +1,417 @@ +fma.rs.html -- source
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+
+use core::{f32, f64};
+
+use super::scalbn;
+
+const ZEROINFNAN: i32 = 0x7ff - 0x3ff - 52 - 1;
+
+struct Num {
+    m: u64,
+    e: i32,
+    sign: i32,
+}
+
+#[inline]
+fn normalize(x: f64) -> Num {
+    let x1p63: f64 = f64::from_bits(0x43e0000000000000); // 0x1p63 === 2 ^ 63
+
+    let mut ix: u64 = x.to_bits();
+    let mut e: i32 = (ix >> 52) as i32;
+    let sign: i32 = e & 0x800;
+    e &= 0x7ff;
+    if e == 0 {
+        ix = (x * x1p63).to_bits();
+        e = (ix >> 52) as i32 & 0x7ff;
+        e = if e != 0 { e - 63 } else { 0x800 };
+    }
+    ix &= (1 << 52) - 1;
+    ix |= 1 << 52;
+    ix <<= 1;
+    e -= 0x3ff + 52 + 1;
+    Num { m: ix, e, sign }
+}
+
+#[inline]
+fn mul(x: u64, y: u64) -> (u64, u64) {
+    let t1: u64;
+    let t2: u64;
+    let t3: u64;
+    let xlo: u64 = x as u32 as u64;
+    let xhi: u64 = x >> 32;
+    let ylo: u64 = y as u32 as u64;
+    let yhi: u64 = y >> 32;
+
+    t1 = xlo * ylo;
+    t2 = xlo * yhi + xhi * ylo;
+    t3 = xhi * yhi;
+    let lo = t1.wrapping_add(t2 << 32);
+    let hi = t3 + (t2 >> 32) + (t1 > lo) as u64;
+    (hi, lo)
+}
+
+/// Floating multiply add (f64)
+///
+/// Computes `(x*y)+z`, rounded as one ternary operation:
+/// Computes the value (as if) to infinite precision and rounds once to the result format,
+/// according to the rounding mode characterized by the value of FLT_ROUNDS.
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn fma(x: f64, y: f64, z: f64) -> f64 {
+    let x1p63: f64 = f64::from_bits(0x43e0000000000000); // 0x1p63 === 2 ^ 63
+    let x0_ffffff8p_63 = f64::from_bits(0x3bfffffff0000000); // 0x0.ffffff8p-63
+
+    /* normalize so top 10bits and last bit are 0 */
+    let nx = normalize(x);
+    let ny = normalize(y);
+    let nz = normalize(z);
+
+    if nx.e >= ZEROINFNAN || ny.e >= ZEROINFNAN {
+        return x * y + z;
+    }
+    if nz.e >= ZEROINFNAN {
+        if nz.e > ZEROINFNAN {
+            /* z==0 */
+            return x * y + z;
+        }
+        return z;
+    }
+
+    /* mul: r = x*y */
+    let zhi: u64;
+    let zlo: u64;
+    let (mut rhi, mut rlo) = mul(nx.m, ny.m);
+    /* either top 20 or 21 bits of rhi and last 2 bits of rlo are 0 */
+
+    /* align exponents */
+    let mut e: i32 = nx.e + ny.e;
+    let mut d: i32 = nz.e - e;
+    /* shift bits z<<=kz, r>>=kr, so kz+kr == d, set e = e+kr (== ez-kz) */
+    if d > 0 {
+        if d < 64 {
+            zlo = nz.m << d;
+            zhi = nz.m >> (64 - d);
+        } else {
+            zlo = 0;
+            zhi = nz.m;
+            e = nz.e - 64;
+            d -= 64;
+            if d == 0 {
+            } else if d < 64 {
+                rlo = rhi << (64 - d) | rlo >> d | ((rlo << (64 - d)) != 0) as u64;
+                rhi = rhi >> d;
+            } else {
+                rlo = 1;
+                rhi = 0;
+            }
+        }
+    } else {
+        zhi = 0;
+        d = -d;
+        if d == 0 {
+            zlo = nz.m;
+        } else if d < 64 {
+            zlo = nz.m >> d | ((nz.m << (64 - d)) != 0) as u64;
+        } else {
+            zlo = 1;
+        }
+    }
+
+    /* add */
+    let mut sign: i32 = nx.sign ^ ny.sign;
+    let samesign: bool = (sign ^ nz.sign) == 0;
+    let mut nonzero: i32 = 1;
+    if samesign {
+        /* r += z */
+        rlo = rlo.wrapping_add(zlo);
+        rhi += zhi + (rlo < zlo) as u64;
+    } else {
+        /* r -= z */
+        let t = rlo;
+        rlo -= zlo;
+        rhi = rhi - zhi - (t < rlo) as u64;
+        if (rhi >> 63) != 0 {
+            rlo = (-(rlo as i64)) as u64;
+            rhi = (-(rhi as i64)) as u64 - (rlo != 0) as u64;
+            sign = (sign == 0) as i32;
+        }
+        nonzero = (rhi != 0) as i32;
+    }
+
+    /* set rhi to top 63bit of the result (last bit is sticky) */
+    if nonzero != 0 {
+        e += 64;
+        d = rhi.leading_zeros() as i32 - 1;
+        /* note: d > 0 */
+        rhi = rhi << d | rlo >> (64 - d) | ((rlo << d) != 0) as u64;
+    } else if rlo != 0 {
+        d = rlo.leading_zeros() as i32 - 1;
+        if d < 0 {
+            rhi = rlo >> 1 | (rlo & 1);
+        } else {
+            rhi = rlo << d;
+        }
+    } else {
+        /* exact +-0 */
+        return x * y + z;
+    }
+    e -= d;
+
+    /* convert to double */
+    let mut i: i64 = rhi as i64; /* i is in [1<<62,(1<<63)-1] */
+    if sign != 0 {
+        i = -i;
+    }
+    let mut r: f64 = i as f64; /* |r| is in [0x1p62,0x1p63] */
+
+    if e < -1022 - 62 {
+        /* result is subnormal before rounding */
+        if e == -1022 - 63 {
+            let mut c: f64 = x1p63;
+            if sign != 0 {
+                c = -c;
+            }
+            if r == c {
+                /* min normal after rounding, underflow depends
+                on arch behaviour which can be imitated by
+                a double to float conversion */
+                let fltmin: f32 = (x0_ffffff8p_63 * f32::MIN_POSITIVE as f64 * r) as f32;
+                return f64::MIN_POSITIVE / f32::MIN_POSITIVE as f64 * fltmin as f64;
+            }
+            /* one bit is lost when scaled, add another top bit to
+            only round once at conversion if it is inexact */
+            if (rhi << 53) != 0 {
+                i = (rhi >> 1 | (rhi & 1) | 1 << 62) as i64;
+                if sign != 0 {
+                    i = -i;
+                }
+                r = i as f64;
+                r = 2. * r - c; /* remove top bit */
+
+                /* raise underflow portably, such that it
+                cannot be optimized away */
+                {
+                    let tiny: f64 = f64::MIN_POSITIVE / f32::MIN_POSITIVE as f64 * r;
+                    r += (tiny * tiny) * (r - r);
+                }
+            }
+        } else {
+            /* only round once when scaled */
+            d = 10;
+            i = ((rhi >> d | ((rhi << (64 - d)) != 0) as u64) << d) as i64;
+            if sign != 0 {
+                i = -i;
+            }
+            r = i as f64;
+        }
+    }
+    scalbn(r, e)
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/fmaf.rs.html b/src/libm/math/fmaf.rs.html new file mode 100644 index 000000000..bf3f3682a --- /dev/null +++ b/src/libm/math/fmaf.rs.html @@ -0,0 +1,217 @@ +fmaf.rs.html -- source
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+
+/* origin: FreeBSD /usr/src/lib/msun/src/s_fmaf.c */
+/*-
+ * Copyright (c) 2005-2011 David Schultz <das@FreeBSD.ORG>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+use core::f32;
+use core::ptr::read_volatile;
+
+use super::fenv::{
+    feclearexcept, fegetround, feraiseexcept, fesetround, fetestexcept, FE_INEXACT, FE_TONEAREST,
+    FE_TOWARDZERO, FE_UNDERFLOW,
+};
+
+/*
+ * Fused multiply-add: Compute x * y + z with a single rounding error.
+ *
+ * A double has more than twice as much precision than a float, so
+ * direct double-precision arithmetic suffices, except where double
+ * rounding occurs.
+ */
+
+/// Floating multiply add (f32)
+///
+/// Computes `(x*y)+z`, rounded as one ternary operation:
+/// Computes the value (as if) to infinite precision and rounds once to the result format,
+/// according to the rounding mode characterized by the value of FLT_ROUNDS.
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn fmaf(x: f32, y: f32, mut z: f32) -> f32 {
+    let xy: f64;
+    let mut result: f64;
+    let mut ui: u64;
+    let e: i32;
+
+    xy = x as f64 * y as f64;
+    result = xy + z as f64;
+    ui = result.to_bits();
+    e = (ui >> 52) as i32 & 0x7ff;
+    /* Common case: The double precision result is fine. */
+    if (
+        /* not a halfway case */
+        ui & 0x1fffffff) != 0x10000000 ||
+        /* NaN */
+        e == 0x7ff ||
+        /* exact */
+        (result - xy == z as f64 && result - z as f64 == xy) ||
+        /* not round-to-nearest */
+        fegetround() != FE_TONEAREST
+    {
+        /*
+            underflow may not be raised correctly, example:
+            fmaf(0x1p-120f, 0x1p-120f, 0x1p-149f)
+        */
+        if e < 0x3ff - 126 && e >= 0x3ff - 149 && fetestexcept(FE_INEXACT) != 0 {
+            feclearexcept(FE_INEXACT);
+            // prevent `xy + vz` from being CSE'd with `xy + z` above
+            let vz: f32 = unsafe { read_volatile(&z) };
+            result = xy + vz as f64;
+            if fetestexcept(FE_INEXACT) != 0 {
+                feraiseexcept(FE_UNDERFLOW);
+            } else {
+                feraiseexcept(FE_INEXACT);
+            }
+        }
+        z = result as f32;
+        return z;
+    }
+
+    /*
+     * If result is inexact, and exactly halfway between two float values,
+     * we need to adjust the low-order bit in the direction of the error.
+     */
+    fesetround(FE_TOWARDZERO);
+    // prevent `vxy + z` from being CSE'd with `xy + z` above
+    let vxy: f64 = unsafe { read_volatile(&xy) };
+    let mut adjusted_result: f64 = vxy + z as f64;
+    fesetround(FE_TONEAREST);
+    if result == adjusted_result {
+        ui = adjusted_result.to_bits();
+        ui += 1;
+        adjusted_result = f64::from_bits(ui);
+    }
+    z = adjusted_result as f32;
+    z
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/fmax.rs.html b/src/libm/math/fmax.rs.html new file mode 100644 index 000000000..b72b6942a --- /dev/null +++ b/src/libm/math/fmax.rs.html @@ -0,0 +1,29 @@ +fmax.rs.html -- source
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+
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn fmax(x: f64, y: f64) -> f64 {
+    // IEEE754 says: maxNum(x, y) is the canonicalized number y if x < y, x if y < x, the
+    // canonicalized number if one operand is a number and the other a quiet NaN. Otherwise it
+    // is either x or y, canonicalized (this means results might differ among implementations).
+    // When either x or y is a signalingNaN, then the result is according to 6.2.
+    //
+    // Since we do not support sNaN in Rust yet, we do not need to handle them.
+    // FIXME(nagisa): due to https://bugs.llvm.org/show_bug.cgi?id=33303 we canonicalize by
+    // multiplying by 1.0. Should switch to the `canonicalize` when it works.
+    (if x.is_nan() || x < y { y } else { x }) * 1.0
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/fmaxf.rs.html b/src/libm/math/fmaxf.rs.html new file mode 100644 index 000000000..2e4b5f3c3 --- /dev/null +++ b/src/libm/math/fmaxf.rs.html @@ -0,0 +1,29 @@ +fmaxf.rs.html -- source
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+
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn fmaxf(x: f32, y: f32) -> f32 {
+    // IEEE754 says: maxNum(x, y) is the canonicalized number y if x < y, x if y < x, the
+    // canonicalized number if one operand is a number and the other a quiet NaN. Otherwise it
+    // is either x or y, canonicalized (this means results might differ among implementations).
+    // When either x or y is a signalingNaN, then the result is according to 6.2.
+    //
+    // Since we do not support sNaN in Rust yet, we do not need to handle them.
+    // FIXME(nagisa): due to https://bugs.llvm.org/show_bug.cgi?id=33303 we canonicalize by
+    // multiplying by 1.0. Should switch to the `canonicalize` when it works.
+    (if x.is_nan() || x < y { y } else { x }) * 1.0
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/fmin.rs.html b/src/libm/math/fmin.rs.html new file mode 100644 index 000000000..1f489e6de --- /dev/null +++ b/src/libm/math/fmin.rs.html @@ -0,0 +1,29 @@ +fmin.rs.html -- source
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+
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn fmin(x: f64, y: f64) -> f64 {
+    // IEEE754 says: minNum(x, y) is the canonicalized number x if x < y, y if y < x, the
+    // canonicalized number if one operand is a number and the other a quiet NaN. Otherwise it
+    // is either x or y, canonicalized (this means results might differ among implementations).
+    // When either x or y is a signalingNaN, then the result is according to 6.2.
+    //
+    // Since we do not support sNaN in Rust yet, we do not need to handle them.
+    // FIXME(nagisa): due to https://bugs.llvm.org/show_bug.cgi?id=33303 we canonicalize by
+    // multiplying by 1.0. Should switch to the `canonicalize` when it works.
+    (if y.is_nan() || x < y { x } else { y }) * 1.0
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/fminf.rs.html b/src/libm/math/fminf.rs.html new file mode 100644 index 000000000..4f2097b60 --- /dev/null +++ b/src/libm/math/fminf.rs.html @@ -0,0 +1,29 @@ +fminf.rs.html -- source
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+
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn fminf(x: f32, y: f32) -> f32 {
+    // IEEE754 says: minNum(x, y) is the canonicalized number x if x < y, y if y < x, the
+    // canonicalized number if one operand is a number and the other a quiet NaN. Otherwise it
+    // is either x or y, canonicalized (this means results might differ among implementations).
+    // When either x or y is a signalingNaN, then the result is according to 6.2.
+    //
+    // Since we do not support sNaN in Rust yet, we do not need to handle them.
+    // FIXME(nagisa): due to https://bugs.llvm.org/show_bug.cgi?id=33303 we canonicalize by
+    // multiplying by 1.0. Should switch to the `canonicalize` when it works.
+    (if y.is_nan() || x < y { x } else { y }) * 1.0
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/fmod.rs.html b/src/libm/math/fmod.rs.html new file mode 100644 index 000000000..1616c8173 --- /dev/null +++ b/src/libm/math/fmod.rs.html @@ -0,0 +1,165 @@ +fmod.rs.html -- source
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+
+use core::u64;
+
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn fmod(x: f64, y: f64) -> f64 {
+    let mut uxi = x.to_bits();
+    let mut uyi = y.to_bits();
+    let mut ex = (uxi >> 52 & 0x7ff) as i64;
+    let mut ey = (uyi >> 52 & 0x7ff) as i64;
+    let sx = uxi >> 63;
+    let mut i;
+
+    if uyi << 1 == 0 || y.is_nan() || ex == 0x7ff {
+        return (x * y) / (x * y);
+    }
+    if uxi << 1 <= uyi << 1 {
+        if uxi << 1 == uyi << 1 {
+            return 0.0 * x;
+        }
+        return x;
+    }
+
+    /* normalize x and y */
+    if ex == 0 {
+        i = uxi << 12;
+        while i >> 63 == 0 {
+            ex -= 1;
+            i <<= 1;
+        }
+        uxi <<= -ex + 1;
+    } else {
+        uxi &= u64::MAX >> 12;
+        uxi |= 1 << 52;
+    }
+    if ey == 0 {
+        i = uyi << 12;
+        while i >> 63 == 0 {
+            ey -= 1;
+            i <<= 1;
+        }
+        uyi <<= -ey + 1;
+    } else {
+        uyi &= u64::MAX >> 12;
+        uyi |= 1 << 52;
+    }
+
+    /* x mod y */
+    while ex > ey {
+        i = uxi.wrapping_sub(uyi);
+        if i >> 63 == 0 {
+            if i == 0 {
+                return 0.0 * x;
+            }
+            uxi = i;
+        }
+        uxi <<= 1;
+        ex -= 1;
+    }
+    i = uxi.wrapping_sub(uyi);
+    if i >> 63 == 0 {
+        if i == 0 {
+            return 0.0 * x;
+        }
+        uxi = i;
+    }
+    while uxi >> 52 == 0 {
+        uxi <<= 1;
+        ex -= 1;
+    }
+
+    /* scale result */
+    if ex > 0 {
+        uxi -= 1 << 52;
+        uxi |= (ex as u64) << 52;
+    } else {
+        uxi >>= -ex + 1;
+    }
+    uxi |= (sx as u64) << 63;
+
+    f64::from_bits(uxi)
+}
+
+
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+use core::f32;
+use core::u32;
+
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn fmodf(x: f32, y: f32) -> f32 {
+    let mut uxi = x.to_bits();
+    let mut uyi = y.to_bits();
+    let mut ex = (uxi >> 23 & 0xff) as i32;
+    let mut ey = (uyi >> 23 & 0xff) as i32;
+    let sx = uxi & 0x80000000;
+    let mut i;
+
+    if uyi << 1 == 0 || y.is_nan() || ex == 0xff {
+        return (x * y) / (x * y);
+    }
+
+    if uxi << 1 <= uyi << 1 {
+        if uxi << 1 == uyi << 1 {
+            return 0.0 * x;
+        }
+
+        return x;
+    }
+
+    /* normalize x and y */
+    if ex == 0 {
+        i = uxi << 9;
+        while i >> 31 == 0 {
+            ex -= 1;
+            i <<= 1;
+        }
+
+        uxi <<= -ex + 1;
+    } else {
+        uxi &= u32::MAX >> 9;
+        uxi |= 1 << 23;
+    }
+
+    if ey == 0 {
+        i = uyi << 9;
+        while i >> 31 == 0 {
+            ey -= 1;
+            i <<= 1;
+        }
+
+        uyi <<= -ey + 1;
+    } else {
+        uyi &= u32::MAX >> 9;
+        uyi |= 1 << 23;
+    }
+
+    /* x mod y */
+    while ex > ey {
+        i = uxi.wrapping_sub(uyi);
+        if i >> 31 == 0 {
+            if i == 0 {
+                return 0.0 * x;
+            }
+            uxi = i;
+        }
+        uxi <<= 1;
+
+        ex -= 1;
+    }
+
+    i = uxi.wrapping_sub(uyi);
+    if i >> 31 == 0 {
+        if i == 0 {
+            return 0.0 * x;
+        }
+        uxi = i;
+    }
+
+    while uxi >> 23 == 0 {
+        uxi <<= 1;
+        ex -= 1;
+    }
+
+    /* scale result up */
+    if ex > 0 {
+        uxi -= 1 << 23;
+        uxi |= (ex as u32) << 23;
+    } else {
+        uxi >>= -ex + 1;
+    }
+    uxi |= sx;
+
+    f32::from_bits(uxi)
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/frexp.rs.html b/src/libm/math/frexp.rs.html new file mode 100644 index 000000000..3cb838d77 --- /dev/null +++ b/src/libm/math/frexp.rs.html @@ -0,0 +1,43 @@ +frexp.rs.html -- source
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+pub fn frexp(x: f64) -> (f64, i32) {
+    let mut y = x.to_bits();
+    let ee = ((y >> 52) & 0x7ff) as i32;
+
+    if ee == 0 {
+        if x != 0.0 {
+            let x1p64 = f64::from_bits(0x43f0000000000000);
+            let (x, e) = frexp(x * x1p64);
+            return (x, e - 64);
+        }
+        return (x, 0);
+    } else if ee == 0x7ff {
+        return (x, 0);
+    }
+
+    let e = ee - 0x3fe;
+    y &= 0x800fffffffffffff;
+    y |= 0x3fe0000000000000;
+    return (f64::from_bits(y), e);
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/frexpf.rs.html b/src/libm/math/frexpf.rs.html new file mode 100644 index 000000000..47fff31b7 --- /dev/null +++ b/src/libm/math/frexpf.rs.html @@ -0,0 +1,45 @@ +frexpf.rs.html -- source
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+
+pub fn frexpf(x: f32) -> (f32, i32) {
+    let mut y = x.to_bits();
+    let ee: i32 = ((y >> 23) & 0xff) as i32;
+
+    if ee == 0 {
+        if x != 0.0 {
+            let x1p64 = f32::from_bits(0x5f800000);
+            let (x, e) = frexpf(x * x1p64);
+            return (x, e - 64);
+        } else {
+            return (x, 0);
+        }
+    } else if ee == 0xff {
+        return (x, 0);
+    }
+
+    let e = ee - 0x7e;
+    y &= 0x807fffff;
+    y |= 0x3f000000;
+    (f32::from_bits(y), e)
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/hypot.rs.html b/src/libm/math/hypot.rs.html new file mode 100644 index 000000000..8770ab488 --- /dev/null +++ b/src/libm/math/hypot.rs.html @@ -0,0 +1,155 @@ +hypot.rs.html -- source
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+use core::f64;
+
+use super::sqrt;
+
+const SPLIT: f64 = 134217728. + 1.; // 0x1p27 + 1 === (2 ^ 27) + 1
+
+#[inline]
+fn sq(x: f64) -> (f64, f64) {
+    let xh: f64;
+    let xl: f64;
+    let xc: f64;
+
+    xc = x * SPLIT;
+    xh = x - xc + xc;
+    xl = x - xh;
+    let hi = x * x;
+    let lo = xh * xh - hi + 2. * xh * xl + xl * xl;
+    (hi, lo)
+}
+
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn hypot(mut x: f64, mut y: f64) -> f64 {
+    let x1p700 = f64::from_bits(0x6bb0000000000000); // 0x1p700 === 2 ^ 700
+    let x1p_700 = f64::from_bits(0x1430000000000000); // 0x1p-700 === 2 ^ -700
+
+    let mut uxi = x.to_bits();
+    let mut uyi = y.to_bits();
+    let uti;
+    let ex: i64;
+    let ey: i64;
+    let mut z: f64;
+
+    /* arrange |x| >= |y| */
+    uxi &= -1i64 as u64 >> 1;
+    uyi &= -1i64 as u64 >> 1;
+    if uxi < uyi {
+        uti = uxi;
+        uxi = uyi;
+        uyi = uti;
+    }
+
+    /* special cases */
+    ex = (uxi >> 52) as i64;
+    ey = (uyi >> 52) as i64;
+    x = f64::from_bits(uxi);
+    y = f64::from_bits(uyi);
+    /* note: hypot(inf,nan) == inf */
+    if ey == 0x7ff {
+        return y;
+    }
+    if ex == 0x7ff || uyi == 0 {
+        return x;
+    }
+    /* note: hypot(x,y) ~= x + y*y/x/2 with inexact for small y/x */
+    /* 64 difference is enough for ld80 double_t */
+    if ex - ey > 64 {
+        return x + y;
+    }
+
+    /* precise sqrt argument in nearest rounding mode without overflow */
+    /* xh*xh must not overflow and xl*xl must not underflow in sq */
+    z = 1.;
+    if ex > 0x3ff + 510 {
+        z = x1p700;
+        x *= x1p_700;
+        y *= x1p_700;
+    } else if ey < 0x3ff - 450 {
+        z = x1p_700;
+        x *= x1p700;
+        y *= x1p700;
+    }
+    let (hx, lx) = sq(x);
+    let (hy, ly) = sq(y);
+    z * sqrt(ly + lx + hy + hx)
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/hypotf.rs.html b/src/libm/math/hypotf.rs.html new file mode 100644 index 000000000..0ae67a5e1 --- /dev/null +++ b/src/libm/math/hypotf.rs.html @@ -0,0 +1,91 @@ +hypotf.rs.html -- source
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+
+use core::f32;
+
+use super::sqrtf;
+
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn hypotf(mut x: f32, mut y: f32) -> f32 {
+    let x1p90 = f32::from_bits(0x6c800000); // 0x1p90f === 2 ^ 90
+    let x1p_90 = f32::from_bits(0x12800000); // 0x1p-90f === 2 ^ -90
+
+    let mut uxi = x.to_bits();
+    let mut uyi = y.to_bits();
+    let uti;
+    let mut z: f32;
+
+    uxi &= -1i32 as u32 >> 1;
+    uyi &= -1i32 as u32 >> 1;
+    if uxi < uyi {
+        uti = uxi;
+        uxi = uyi;
+        uyi = uti;
+    }
+
+    x = f32::from_bits(uxi);
+    y = f32::from_bits(uyi);
+    if uyi == 0xff << 23 {
+        return y;
+    }
+    if uxi >= 0xff << 23 || uyi == 0 || uxi - uyi >= 25 << 23 {
+        return x + y;
+    }
+
+    z = 1.;
+    if uxi >= (0x7f + 60) << 23 {
+        z = x1p90;
+        x *= x1p_90;
+        y *= x1p_90;
+    } else if uyi < (0x7f - 60) << 23 {
+        z = x1p_90;
+        x *= x1p90;
+        y *= x1p90;
+    }
+    z * sqrtf((x as f64 * x as f64 + y as f64 * y as f64) as f32)
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/ilogb.rs.html b/src/libm/math/ilogb.rs.html new file mode 100644 index 000000000..9e63f300b --- /dev/null +++ b/src/libm/math/ilogb.rs.html @@ -0,0 +1,65 @@ +ilogb.rs.html -- source
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+
+const FP_ILOGBNAN: i32 = -1 - 0x7fffffff;
+const FP_ILOGB0: i32 = FP_ILOGBNAN;
+
+pub fn ilogb(x: f64) -> i32 {
+    let mut i: u64 = x.to_bits();
+    let e = ((i >> 52) & 0x7ff) as i32;
+
+    if e == 0 {
+        i <<= 12;
+        if i == 0 {
+            force_eval!(0.0 / 0.0);
+            return FP_ILOGB0;
+        }
+        /* subnormal x */
+        let mut e = -0x3ff;
+        while (i >> 63) == 0 {
+            e -= 1;
+            i <<= 1;
+        }
+        e
+    } else if e == 0x7ff {
+        force_eval!(0.0 / 0.0);
+        if (i << 12) != 0 {
+            FP_ILOGBNAN
+        } else {
+            i32::max_value()
+        }
+    } else {
+        e - 0x3ff
+    }
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/ilogbf.rs.html b/src/libm/math/ilogbf.rs.html new file mode 100644 index 000000000..a229ec62a --- /dev/null +++ b/src/libm/math/ilogbf.rs.html @@ -0,0 +1,65 @@ +ilogbf.rs.html -- source
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+
+const FP_ILOGBNAN: i32 = -1 - 0x7fffffff;
+const FP_ILOGB0: i32 = FP_ILOGBNAN;
+
+pub fn ilogbf(x: f32) -> i32 {
+    let mut i = x.to_bits();
+    let e = ((i >> 23) & 0xff) as i32;
+
+    if e == 0 {
+        i <<= 9;
+        if i == 0 {
+            force_eval!(0.0 / 0.0);
+            return FP_ILOGB0;
+        }
+        /* subnormal x */
+        let mut e = -0x7f;
+        while (i >> 31) == 0 {
+            e -= 1;
+            i <<= 1;
+        }
+        e
+    } else if e == 0xff {
+        force_eval!(0.0 / 0.0);
+        if (i << 9) != 0 {
+            FP_ILOGBNAN
+        } else {
+            i32::max_value()
+        }
+    } else {
+        e - 0x7f
+    }
+}
+
+
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+
+/* origin: FreeBSD /usr/src/lib/msun/src/e_j0.c */
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunSoft, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+/* j0(x), y0(x)
+ * Bessel function of the first and second kinds of order zero.
+ * Method -- j0(x):
+ *      1. For tiny x, we use j0(x) = 1 - x^2/4 + x^4/64 - ...
+ *      2. Reduce x to |x| since j0(x)=j0(-x),  and
+ *         for x in (0,2)
+ *              j0(x) = 1-z/4+ z^2*R0/S0,  where z = x*x;
+ *         (precision:  |j0-1+z/4-z^2R0/S0 |<2**-63.67 )
+ *         for x in (2,inf)
+ *              j0(x) = sqrt(2/(pi*x))*(p0(x)*cos(x0)-q0(x)*sin(x0))
+ *         where x0 = x-pi/4. It is better to compute sin(x0),cos(x0)
+ *         as follow:
+ *              cos(x0) = cos(x)cos(pi/4)+sin(x)sin(pi/4)
+ *                      = 1/sqrt(2) * (cos(x) + sin(x))
+ *              sin(x0) = sin(x)cos(pi/4)-cos(x)sin(pi/4)
+ *                      = 1/sqrt(2) * (sin(x) - cos(x))
+ *         (To avoid cancellation, use
+ *              sin(x) +- cos(x) = -cos(2x)/(sin(x) -+ cos(x))
+ *          to compute the worse one.)
+ *
+ *      3 Special cases
+ *              j0(nan)= nan
+ *              j0(0) = 1
+ *              j0(inf) = 0
+ *
+ * Method -- y0(x):
+ *      1. For x<2.
+ *         Since
+ *              y0(x) = 2/pi*(j0(x)*(ln(x/2)+Euler) + x^2/4 - ...)
+ *         therefore y0(x)-2/pi*j0(x)*ln(x) is an even function.
+ *         We use the following function to approximate y0,
+ *              y0(x) = U(z)/V(z) + (2/pi)*(j0(x)*ln(x)), z= x^2
+ *         where
+ *              U(z) = u00 + u01*z + ... + u06*z^6
+ *              V(z) = 1  + v01*z + ... + v04*z^4
+ *         with absolute approximation error bounded by 2**-72.
+ *         Note: For tiny x, U/V = u0 and j0(x)~1, hence
+ *              y0(tiny) = u0 + (2/pi)*ln(tiny), (choose tiny<2**-27)
+ *      2. For x>=2.
+ *              y0(x) = sqrt(2/(pi*x))*(p0(x)*cos(x0)+q0(x)*sin(x0))
+ *         where x0 = x-pi/4. It is better to compute sin(x0),cos(x0)
+ *         by the method mentioned above.
+ *      3. Special cases: y0(0)=-inf, y0(x<0)=NaN, y0(inf)=0.
+ */
+
+use super::{cos, fabs, get_high_word, get_low_word, log, sin, sqrt};
+const INVSQRTPI: f64 = 5.64189583547756279280e-01; /* 0x3FE20DD7, 0x50429B6D */
+const TPI: f64 = 6.36619772367581382433e-01; /* 0x3FE45F30, 0x6DC9C883 */
+
+/* common method when |x|>=2 */
+fn common(ix: u32, x: f64, y0: bool) -> f64 {
+    let s: f64;
+    let mut c: f64;
+    let mut ss: f64;
+    let mut cc: f64;
+    let z: f64;
+
+    /*
+     * j0(x) = sqrt(2/(pi*x))*(p0(x)*cos(x-pi/4)-q0(x)*sin(x-pi/4))
+     * y0(x) = sqrt(2/(pi*x))*(p0(x)*sin(x-pi/4)+q0(x)*cos(x-pi/4))
+     *
+     * sin(x-pi/4) = (sin(x) - cos(x))/sqrt(2)
+     * cos(x-pi/4) = (sin(x) + cos(x))/sqrt(2)
+     * sin(x) +- cos(x) = -cos(2x)/(sin(x) -+ cos(x))
+     */
+    s = sin(x);
+    c = cos(x);
+    if y0 {
+        c = -c;
+    }
+    cc = s + c;
+    /* avoid overflow in 2*x, big ulp error when x>=0x1p1023 */
+    if ix < 0x7fe00000 {
+        ss = s - c;
+        z = -cos(2.0 * x);
+        if s * c < 0.0 {
+            cc = z / ss;
+        } else {
+            ss = z / cc;
+        }
+        if ix < 0x48000000 {
+            if y0 {
+                ss = -ss;
+            }
+            cc = pzero(x) * cc - qzero(x) * ss;
+        }
+    }
+    return INVSQRTPI * cc / sqrt(x);
+}
+
+/* R0/S0 on [0, 2.00] */
+const R02: f64 = 1.56249999999999947958e-02; /* 0x3F8FFFFF, 0xFFFFFFFD */
+const R03: f64 = -1.89979294238854721751e-04; /* 0xBF28E6A5, 0xB61AC6E9 */
+const R04: f64 = 1.82954049532700665670e-06; /* 0x3EBEB1D1, 0x0C503919 */
+const R05: f64 = -4.61832688532103189199e-09; /* 0xBE33D5E7, 0x73D63FCE */
+const S01: f64 = 1.56191029464890010492e-02; /* 0x3F8FFCE8, 0x82C8C2A4 */
+const S02: f64 = 1.16926784663337450260e-04; /* 0x3F1EA6D2, 0xDD57DBF4 */
+const S03: f64 = 5.13546550207318111446e-07; /* 0x3EA13B54, 0xCE84D5A9 */
+const S04: f64 = 1.16614003333790000205e-09; /* 0x3E1408BC, 0xF4745D8F */
+
+pub fn j0(mut x: f64) -> f64 {
+    let z: f64;
+    let r: f64;
+    let s: f64;
+    let mut ix: u32;
+
+    ix = get_high_word(x);
+    ix &= 0x7fffffff;
+
+    /* j0(+-inf)=0, j0(nan)=nan */
+    if ix >= 0x7ff00000 {
+        return 1.0 / (x * x);
+    }
+    x = fabs(x);
+
+    if ix >= 0x40000000 {
+        /* |x| >= 2 */
+        /* large ulp error near zeros: 2.4, 5.52, 8.6537,.. */
+        return common(ix, x, false);
+    }
+
+    /* 1 - x*x/4 + x*x*R(x^2)/S(x^2) */
+    if ix >= 0x3f200000 {
+        /* |x| >= 2**-13 */
+        /* up to 4ulp error close to 2 */
+        z = x * x;
+        r = z * (R02 + z * (R03 + z * (R04 + z * R05)));
+        s = 1.0 + z * (S01 + z * (S02 + z * (S03 + z * S04)));
+        return (1.0 + x / 2.0) * (1.0 - x / 2.0) + z * (r / s);
+    }
+
+    /* 1 - x*x/4 */
+    /* prevent underflow */
+    /* inexact should be raised when x!=0, this is not done correctly */
+    if ix >= 0x38000000 {
+        /* |x| >= 2**-127 */
+        x = 0.25 * x * x;
+    }
+    return 1.0 - x;
+}
+
+const U00: f64 = -7.38042951086872317523e-02; /* 0xBFB2E4D6, 0x99CBD01F */
+const U01: f64 = 1.76666452509181115538e-01; /* 0x3FC69D01, 0x9DE9E3FC */
+const U02: f64 = -1.38185671945596898896e-02; /* 0xBF8C4CE8, 0xB16CFA97 */
+const U03: f64 = 3.47453432093683650238e-04; /* 0x3F36C54D, 0x20B29B6B */
+const U04: f64 = -3.81407053724364161125e-06; /* 0xBECFFEA7, 0x73D25CAD */
+const U05: f64 = 1.95590137035022920206e-08; /* 0x3E550057, 0x3B4EABD4 */
+const U06: f64 = -3.98205194132103398453e-11; /* 0xBDC5E43D, 0x693FB3C8 */
+const V01: f64 = 1.27304834834123699328e-02; /* 0x3F8A1270, 0x91C9C71A */
+const V02: f64 = 7.60068627350353253702e-05; /* 0x3F13ECBB, 0xF578C6C1 */
+const V03: f64 = 2.59150851840457805467e-07; /* 0x3E91642D, 0x7FF202FD */
+const V04: f64 = 4.41110311332675467403e-10; /* 0x3DFE5018, 0x3BD6D9EF */
+
+pub fn y0(x: f64) -> f64 {
+    let z: f64;
+    let u: f64;
+    let v: f64;
+    let ix: u32;
+    let lx: u32;
+
+    ix = get_high_word(x);
+    lx = get_low_word(x);
+
+    /* y0(nan)=nan, y0(<0)=nan, y0(0)=-inf, y0(inf)=0 */
+    if ((ix << 1) | lx) == 0 {
+        return -1.0 / 0.0;
+    }
+    if (ix >> 31) != 0 {
+        return 0.0 / 0.0;
+    }
+    if ix >= 0x7ff00000 {
+        return 1.0 / x;
+    }
+
+    if ix >= 0x40000000 {
+        /* x >= 2 */
+        /* large ulp errors near zeros: 3.958, 7.086,.. */
+        return common(ix, x, true);
+    }
+
+    /* U(x^2)/V(x^2) + (2/pi)*j0(x)*log(x) */
+    if ix >= 0x3e400000 {
+        /* x >= 2**-27 */
+        /* large ulp error near the first zero, x ~= 0.89 */
+        z = x * x;
+        u = U00 + z * (U01 + z * (U02 + z * (U03 + z * (U04 + z * (U05 + z * U06)))));
+        v = 1.0 + z * (V01 + z * (V02 + z * (V03 + z * V04)));
+        return u / v + TPI * (j0(x) * log(x));
+    }
+    return U00 + TPI * log(x);
+}
+
+/* The asymptotic expansions of pzero is
+ *      1 - 9/128 s^2 + 11025/98304 s^4 - ...,  where s = 1/x.
+ * For x >= 2, We approximate pzero by
+ *      pzero(x) = 1 + (R/S)
+ * where  R = pR0 + pR1*s^2 + pR2*s^4 + ... + pR5*s^10
+ *        S = 1 + pS0*s^2 + ... + pS4*s^10
+ * and
+ *      | pzero(x)-1-R/S | <= 2  ** ( -60.26)
+ */
+const PR8: [f64; 6] = [
+    /* for x in [inf, 8]=1/[0,0.125] */
+    0.00000000000000000000e+00,  /* 0x00000000, 0x00000000 */
+    -7.03124999999900357484e-02, /* 0xBFB1FFFF, 0xFFFFFD32 */
+    -8.08167041275349795626e+00, /* 0xC02029D0, 0xB44FA779 */
+    -2.57063105679704847262e+02, /* 0xC0701102, 0x7B19E863 */
+    -2.48521641009428822144e+03, /* 0xC0A36A6E, 0xCD4DCAFC */
+    -5.25304380490729545272e+03, /* 0xC0B4850B, 0x36CC643D */
+];
+const PS8: [f64; 5] = [
+    1.16534364619668181717e+02, /* 0x405D2233, 0x07A96751 */
+    3.83374475364121826715e+03, /* 0x40ADF37D, 0x50596938 */
+    4.05978572648472545552e+04, /* 0x40E3D2BB, 0x6EB6B05F */
+    1.16752972564375915681e+05, /* 0x40FC810F, 0x8F9FA9BD */
+    4.76277284146730962675e+04, /* 0x40E74177, 0x4F2C49DC */
+];
+
+const PR5: [f64; 6] = [
+    /* for x in [8,4.5454]=1/[0.125,0.22001] */
+    -1.14125464691894502584e-11, /* 0xBDA918B1, 0x47E495CC */
+    -7.03124940873599280078e-02, /* 0xBFB1FFFF, 0xE69AFBC6 */
+    -4.15961064470587782438e+00, /* 0xC010A370, 0xF90C6BBF */
+    -6.76747652265167261021e+01, /* 0xC050EB2F, 0x5A7D1783 */
+    -3.31231299649172967747e+02, /* 0xC074B3B3, 0x6742CC63 */
+    -3.46433388365604912451e+02, /* 0xC075A6EF, 0x28A38BD7 */
+];
+const PS5: [f64; 5] = [
+    6.07539382692300335975e+01, /* 0x404E6081, 0x0C98C5DE */
+    1.05125230595704579173e+03, /* 0x40906D02, 0x5C7E2864 */
+    5.97897094333855784498e+03, /* 0x40B75AF8, 0x8FBE1D60 */
+    9.62544514357774460223e+03, /* 0x40C2CCB8, 0xFA76FA38 */
+    2.40605815922939109441e+03, /* 0x40A2CC1D, 0xC70BE864 */
+];
+
+const PR3: [f64; 6] = [
+    /* for x in [4.547,2.8571]=1/[0.2199,0.35001] */
+    -2.54704601771951915620e-09, /* 0xBE25E103, 0x6FE1AA86 */
+    -7.03119616381481654654e-02, /* 0xBFB1FFF6, 0xF7C0E24B */
+    -2.40903221549529611423e+00, /* 0xC00345B2, 0xAEA48074 */
+    -2.19659774734883086467e+01, /* 0xC035F74A, 0x4CB94E14 */
+    -5.80791704701737572236e+01, /* 0xC04D0A22, 0x420A1A45 */
+    -3.14479470594888503854e+01, /* 0xC03F72AC, 0xA892D80F */
+];
+const PS3: [f64; 5] = [
+    3.58560338055209726349e+01, /* 0x4041ED92, 0x84077DD3 */
+    3.61513983050303863820e+02, /* 0x40769839, 0x464A7C0E */
+    1.19360783792111533330e+03, /* 0x4092A66E, 0x6D1061D6 */
+    1.12799679856907414432e+03, /* 0x40919FFC, 0xB8C39B7E */
+    1.73580930813335754692e+02, /* 0x4065B296, 0xFC379081 */
+];
+
+const PR2: [f64; 6] = [
+    /* for x in [2.8570,2]=1/[0.3499,0.5] */
+    -8.87534333032526411254e-08, /* 0xBE77D316, 0xE927026D */
+    -7.03030995483624743247e-02, /* 0xBFB1FF62, 0x495E1E42 */
+    -1.45073846780952986357e+00, /* 0xBFF73639, 0x8A24A843 */
+    -7.63569613823527770791e+00, /* 0xC01E8AF3, 0xEDAFA7F3 */
+    -1.11931668860356747786e+01, /* 0xC02662E6, 0xC5246303 */
+    -3.23364579351335335033e+00, /* 0xC009DE81, 0xAF8FE70F */
+];
+const PS2: [f64; 5] = [
+    2.22202997532088808441e+01, /* 0x40363865, 0x908B5959 */
+    1.36206794218215208048e+02, /* 0x4061069E, 0x0EE8878F */
+    2.70470278658083486789e+02, /* 0x4070E786, 0x42EA079B */
+    1.53875394208320329881e+02, /* 0x40633C03, 0x3AB6FAFF */
+    1.46576176948256193810e+01, /* 0x402D50B3, 0x44391809 */
+];
+
+fn pzero(x: f64) -> f64 {
+    let p: &[f64; 6];
+    let q: &[f64; 5];
+    let z: f64;
+    let r: f64;
+    let s: f64;
+    let mut ix: u32;
+
+    ix = get_high_word(x);
+    ix &= 0x7fffffff;
+    if ix >= 0x40200000 {
+        p = &PR8;
+        q = &PS8;
+    } else if ix >= 0x40122E8B {
+        p = &PR5;
+        q = &PS5;
+    } else if ix >= 0x4006DB6D {
+        p = &PR3;
+        q = &PS3;
+    } else
+    /*ix >= 0x40000000*/
+    {
+        p = &PR2;
+        q = &PS2;
+    }
+    z = 1.0 / (x * x);
+    r = p[0] + z * (p[1] + z * (p[2] + z * (p[3] + z * (p[4] + z * p[5]))));
+    s = 1.0 + z * (q[0] + z * (q[1] + z * (q[2] + z * (q[3] + z * q[4]))));
+    return 1.0 + r / s;
+}
+
+/* For x >= 8, the asymptotic expansions of qzero is
+ *      -1/8 s + 75/1024 s^3 - ..., where s = 1/x.
+ * We approximate pzero by
+ *      qzero(x) = s*(-1.25 + (R/S))
+ * where  R = qR0 + qR1*s^2 + qR2*s^4 + ... + qR5*s^10
+ *        S = 1 + qS0*s^2 + ... + qS5*s^12
+ * and
+ *      | qzero(x)/s +1.25-R/S | <= 2  ** ( -61.22)
+ */
+const QR8: [f64; 6] = [
+    /* for x in [inf, 8]=1/[0,0.125] */
+    0.00000000000000000000e+00, /* 0x00000000, 0x00000000 */
+    7.32421874999935051953e-02, /* 0x3FB2BFFF, 0xFFFFFE2C */
+    1.17682064682252693899e+01, /* 0x40278952, 0x5BB334D6 */
+    5.57673380256401856059e+02, /* 0x40816D63, 0x15301825 */
+    8.85919720756468632317e+03, /* 0x40C14D99, 0x3E18F46D */
+    3.70146267776887834771e+04, /* 0x40E212D4, 0x0E901566 */
+];
+const QS8: [f64; 6] = [
+    1.63776026895689824414e+02,  /* 0x406478D5, 0x365B39BC */
+    8.09834494656449805916e+03,  /* 0x40BFA258, 0x4E6B0563 */
+    1.42538291419120476348e+05,  /* 0x41016652, 0x54D38C3F */
+    8.03309257119514397345e+05,  /* 0x412883DA, 0x83A52B43 */
+    8.40501579819060512818e+05,  /* 0x4129A66B, 0x28DE0B3D */
+    -3.43899293537866615225e+05, /* 0xC114FD6D, 0x2C9530C5 */
+];
+
+const QR5: [f64; 6] = [
+    /* for x in [8,4.5454]=1/[0.125,0.22001] */
+    1.84085963594515531381e-11, /* 0x3DB43D8F, 0x29CC8CD9 */
+    7.32421766612684765896e-02, /* 0x3FB2BFFF, 0xD172B04C */
+    5.83563508962056953777e+00, /* 0x401757B0, 0xB9953DD3 */
+    1.35111577286449829671e+02, /* 0x4060E392, 0x0A8788E9 */
+    1.02724376596164097464e+03, /* 0x40900CF9, 0x9DC8C481 */
+    1.98997785864605384631e+03, /* 0x409F17E9, 0x53C6E3A6 */
+];
+const QS5: [f64; 6] = [
+    8.27766102236537761883e+01,  /* 0x4054B1B3, 0xFB5E1543 */
+    2.07781416421392987104e+03,  /* 0x40A03BA0, 0xDA21C0CE */
+    1.88472887785718085070e+04,  /* 0x40D267D2, 0x7B591E6D */
+    5.67511122894947329769e+04,  /* 0x40EBB5E3, 0x97E02372 */
+    3.59767538425114471465e+04,  /* 0x40E19118, 0x1F7A54A0 */
+    -5.35434275601944773371e+03, /* 0xC0B4EA57, 0xBEDBC609 */
+];
+
+const QR3: [f64; 6] = [
+    /* for x in [4.547,2.8571]=1/[0.2199,0.35001] */
+    4.37741014089738620906e-09, /* 0x3E32CD03, 0x6ADECB82 */
+    7.32411180042911447163e-02, /* 0x3FB2BFEE, 0x0E8D0842 */
+    3.34423137516170720929e+00, /* 0x400AC0FC, 0x61149CF5 */
+    4.26218440745412650017e+01, /* 0x40454F98, 0x962DAEDD */
+    1.70808091340565596283e+02, /* 0x406559DB, 0xE25EFD1F */
+    1.66733948696651168575e+02, /* 0x4064D77C, 0x81FA21E0 */
+];
+const QS3: [f64; 6] = [
+    4.87588729724587182091e+01,  /* 0x40486122, 0xBFE343A6 */
+    7.09689221056606015736e+02,  /* 0x40862D83, 0x86544EB3 */
+    3.70414822620111362994e+03,  /* 0x40ACF04B, 0xE44DFC63 */
+    6.46042516752568917582e+03,  /* 0x40B93C6C, 0xD7C76A28 */
+    2.51633368920368957333e+03,  /* 0x40A3A8AA, 0xD94FB1C0 */
+    -1.49247451836156386662e+02, /* 0xC062A7EB, 0x201CF40F */
+];
+
+const QR2: [f64; 6] = [
+    /* for x in [2.8570,2]=1/[0.3499,0.5] */
+    1.50444444886983272379e-07, /* 0x3E84313B, 0x54F76BDB */
+    7.32234265963079278272e-02, /* 0x3FB2BEC5, 0x3E883E34 */
+    1.99819174093815998816e+00, /* 0x3FFFF897, 0xE727779C */
+    1.44956029347885735348e+01, /* 0x402CFDBF, 0xAAF96FE5 */
+    3.16662317504781540833e+01, /* 0x403FAA8E, 0x29FBDC4A */
+    1.62527075710929267416e+01, /* 0x403040B1, 0x71814BB4 */
+];
+const QS2: [f64; 6] = [
+    3.03655848355219184498e+01,  /* 0x403E5D96, 0xF7C07AED */
+    2.69348118608049844624e+02,  /* 0x4070D591, 0xE4D14B40 */
+    8.44783757595320139444e+02,  /* 0x408A6645, 0x22B3BF22 */
+    8.82935845112488550512e+02,  /* 0x408B977C, 0x9C5CC214 */
+    2.12666388511798828631e+02,  /* 0x406A9553, 0x0E001365 */
+    -5.31095493882666946917e+00, /* 0xC0153E6A, 0xF8B32931 */
+];
+
+fn qzero(x: f64) -> f64 {
+    let p: &[f64; 6];
+    let q: &[f64; 6];
+    let s: f64;
+    let r: f64;
+    let z: f64;
+    let mut ix: u32;
+
+    ix = get_high_word(x);
+    ix &= 0x7fffffff;
+    if ix >= 0x40200000 {
+        p = &QR8;
+        q = &QS8;
+    } else if ix >= 0x40122E8B {
+        p = &QR5;
+        q = &QS5;
+    } else if ix >= 0x4006DB6D {
+        p = &QR3;
+        q = &QS3;
+    } else
+    /*ix >= 0x40000000*/
+    {
+        p = &QR2;
+        q = &QS2;
+    }
+    z = 1.0 / (x * x);
+    r = p[0] + z * (p[1] + z * (p[2] + z * (p[3] + z * (p[4] + z * p[5]))));
+    s = 1.0 + z * (q[0] + z * (q[1] + z * (q[2] + z * (q[3] + z * (q[4] + z * q[5])))));
+    return (-0.125 + r / s) / x;
+}
+
+
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+
+/* origin: FreeBSD /usr/src/lib/msun/src/e_j0f.c */
+/*
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+use super::{cosf, fabsf, logf, sinf, sqrtf};
+
+const INVSQRTPI: f32 = 5.6418961287e-01; /* 0x3f106ebb */
+const TPI: f32 = 6.3661974669e-01; /* 0x3f22f983 */
+
+fn common(ix: u32, x: f32, y0: bool) -> f32 {
+    let z: f32;
+    let s: f32;
+    let mut c: f32;
+    let mut ss: f32;
+    let mut cc: f32;
+    /*
+     * j0(x) = 1/sqrt(pi) * (P(0,x)*cc - Q(0,x)*ss) / sqrt(x)
+     * y0(x) = 1/sqrt(pi) * (P(0,x)*ss + Q(0,x)*cc) / sqrt(x)
+     */
+    s = sinf(x);
+    c = cosf(x);
+    if y0 {
+        c = -c;
+    }
+    cc = s + c;
+    if ix < 0x7f000000 {
+        ss = s - c;
+        z = -cosf(2.0 * x);
+        if s * c < 0.0 {
+            cc = z / ss;
+        } else {
+            ss = z / cc;
+        }
+        if ix < 0x58800000 {
+            if y0 {
+                ss = -ss;
+            }
+            cc = pzerof(x) * cc - qzerof(x) * ss;
+        }
+    }
+    return INVSQRTPI * cc / sqrtf(x);
+}
+
+/* R0/S0 on [0, 2.00] */
+const R02: f32 = 1.5625000000e-02; /* 0x3c800000 */
+const R03: f32 = -1.8997929874e-04; /* 0xb947352e */
+const R04: f32 = 1.8295404516e-06; /* 0x35f58e88 */
+const R05: f32 = -4.6183270541e-09; /* 0xb19eaf3c */
+const S01: f32 = 1.5619102865e-02; /* 0x3c7fe744 */
+const S02: f32 = 1.1692678527e-04; /* 0x38f53697 */
+const S03: f32 = 5.1354652442e-07; /* 0x3509daa6 */
+const S04: f32 = 1.1661400734e-09; /* 0x30a045e8 */
+
+pub fn j0f(mut x: f32) -> f32 {
+    let z: f32;
+    let r: f32;
+    let s: f32;
+    let mut ix: u32;
+
+    ix = x.to_bits();
+    ix &= 0x7fffffff;
+    if ix >= 0x7f800000 {
+        return 1.0 / (x * x);
+    }
+    x = fabsf(x);
+
+    if ix >= 0x40000000 {
+        /* |x| >= 2 */
+        /* large ulp error near zeros */
+        return common(ix, x, false);
+    }
+    if ix >= 0x3a000000 {
+        /* |x| >= 2**-11 */
+        /* up to 4ulp error near 2 */
+        z = x * x;
+        r = z * (R02 + z * (R03 + z * (R04 + z * R05)));
+        s = 1.0 + z * (S01 + z * (S02 + z * (S03 + z * S04)));
+        return (1.0 + x / 2.0) * (1.0 - x / 2.0) + z * (r / s);
+    }
+    if ix >= 0x21800000 {
+        /* |x| >= 2**-60 */
+        x = 0.25 * x * x;
+    }
+    return 1.0 - x;
+}
+
+const U00: f32 = -7.3804296553e-02; /* 0xbd9726b5 */
+const U01: f32 = 1.7666645348e-01; /* 0x3e34e80d */
+const U02: f32 = -1.3818567619e-02; /* 0xbc626746 */
+const U03: f32 = 3.4745343146e-04; /* 0x39b62a69 */
+const U04: f32 = -3.8140706238e-06; /* 0xb67ff53c */
+const U05: f32 = 1.9559013964e-08; /* 0x32a802ba */
+const U06: f32 = -3.9820518410e-11; /* 0xae2f21eb */
+const V01: f32 = 1.2730483897e-02; /* 0x3c509385 */
+const V02: f32 = 7.6006865129e-05; /* 0x389f65e0 */
+const V03: f32 = 2.5915085189e-07; /* 0x348b216c */
+const V04: f32 = 4.4111031494e-10; /* 0x2ff280c2 */
+
+pub fn y0f(x: f32) -> f32 {
+    let z: f32;
+    let u: f32;
+    let v: f32;
+    let ix: u32;
+
+    ix = x.to_bits();
+    if (ix & 0x7fffffff) == 0 {
+        return -1.0 / 0.0;
+    }
+    if (ix >> 31) != 0 {
+        return 0.0 / 0.0;
+    }
+    if ix >= 0x7f800000 {
+        return 1.0 / x;
+    }
+    if ix >= 0x40000000 {
+        /* |x| >= 2.0 */
+        /* large ulp error near zeros */
+        return common(ix, x, true);
+    }
+    if ix >= 0x39000000 {
+        /* x >= 2**-13 */
+        /* large ulp error at x ~= 0.89 */
+        z = x * x;
+        u = U00 + z * (U01 + z * (U02 + z * (U03 + z * (U04 + z * (U05 + z * U06)))));
+        v = 1.0 + z * (V01 + z * (V02 + z * (V03 + z * V04)));
+        return u / v + TPI * (j0f(x) * logf(x));
+    }
+    return U00 + TPI * logf(x);
+}
+
+/* The asymptotic expansions of pzero is
+ *      1 - 9/128 s^2 + 11025/98304 s^4 - ...,  where s = 1/x.
+ * For x >= 2, We approximate pzero by
+ *      pzero(x) = 1 + (R/S)
+ * where  R = pR0 + pR1*s^2 + pR2*s^4 + ... + pR5*s^10
+ *        S = 1 + pS0*s^2 + ... + pS4*s^10
+ * and
+ *      | pzero(x)-1-R/S | <= 2  ** ( -60.26)
+ */
+const PR8: [f32; 6] = [
+    /* for x in [inf, 8]=1/[0,0.125] */
+    0.0000000000e+00,  /* 0x00000000 */
+    -7.0312500000e-02, /* 0xbd900000 */
+    -8.0816707611e+00, /* 0xc1014e86 */
+    -2.5706311035e+02, /* 0xc3808814 */
+    -2.4852163086e+03, /* 0xc51b5376 */
+    -5.2530439453e+03, /* 0xc5a4285a */
+];
+const PS8: [f32; 5] = [
+    1.1653436279e+02, /* 0x42e91198 */
+    3.8337448730e+03, /* 0x456f9beb */
+    4.0597855469e+04, /* 0x471e95db */
+    1.1675296875e+05, /* 0x47e4087c */
+    4.7627726562e+04, /* 0x473a0bba */
+];
+const PR5: [f32; 6] = [
+    /* for x in [8,4.5454]=1/[0.125,0.22001] */
+    -1.1412546255e-11, /* 0xad48c58a */
+    -7.0312492549e-02, /* 0xbd8fffff */
+    -4.1596107483e+00, /* 0xc0851b88 */
+    -6.7674766541e+01, /* 0xc287597b */
+    -3.3123129272e+02, /* 0xc3a59d9b */
+    -3.4643338013e+02, /* 0xc3ad3779 */
+];
+const PS5: [f32; 5] = [
+    6.0753936768e+01, /* 0x42730408 */
+    1.0512523193e+03, /* 0x44836813 */
+    5.9789707031e+03, /* 0x45bad7c4 */
+    9.6254453125e+03, /* 0x461665c8 */
+    2.4060581055e+03, /* 0x451660ee */
+];
+
+const PR3: [f32; 6] = [
+    /* for x in [4.547,2.8571]=1/[0.2199,0.35001] */
+    -2.5470459075e-09, /* 0xb12f081b */
+    -7.0311963558e-02, /* 0xbd8fffb8 */
+    -2.4090321064e+00, /* 0xc01a2d95 */
+    -2.1965976715e+01, /* 0xc1afba52 */
+    -5.8079170227e+01, /* 0xc2685112 */
+    -3.1447946548e+01, /* 0xc1fb9565 */
+];
+const PS3: [f32; 5] = [
+    3.5856033325e+01, /* 0x420f6c94 */
+    3.6151397705e+02, /* 0x43b4c1ca */
+    1.1936077881e+03, /* 0x44953373 */
+    1.1279968262e+03, /* 0x448cffe6 */
+    1.7358093262e+02, /* 0x432d94b8 */
+];
+
+const PR2: [f32; 6] = [
+    /* for x in [2.8570,2]=1/[0.3499,0.5] */
+    -8.8753431271e-08, /* 0xb3be98b7 */
+    -7.0303097367e-02, /* 0xbd8ffb12 */
+    -1.4507384300e+00, /* 0xbfb9b1cc */
+    -7.6356959343e+00, /* 0xc0f4579f */
+    -1.1193166733e+01, /* 0xc1331736 */
+    -3.2336456776e+00, /* 0xc04ef40d */
+];
+const PS2: [f32; 5] = [
+    2.2220300674e+01, /* 0x41b1c32d */
+    1.3620678711e+02, /* 0x430834f0 */
+    2.7047027588e+02, /* 0x43873c32 */
+    1.5387539673e+02, /* 0x4319e01a */
+    1.4657617569e+01, /* 0x416a859a */
+];
+
+fn pzerof(x: f32) -> f32 {
+    let p: &[f32; 6];
+    let q: &[f32; 5];
+    let z: f32;
+    let r: f32;
+    let s: f32;
+    let mut ix: u32;
+
+    ix = x.to_bits();
+    ix &= 0x7fffffff;
+    if ix >= 0x41000000 {
+        p = &PR8;
+        q = &PS8;
+    } else if ix >= 0x409173eb {
+        p = &PR5;
+        q = &PS5;
+    } else if ix >= 0x4036d917 {
+        p = &PR3;
+        q = &PS3;
+    } else
+    /*ix >= 0x40000000*/
+    {
+        p = &PR2;
+        q = &PS2;
+    }
+    z = 1.0 / (x * x);
+    r = p[0] + z * (p[1] + z * (p[2] + z * (p[3] + z * (p[4] + z * p[5]))));
+    s = 1.0 + z * (q[0] + z * (q[1] + z * (q[2] + z * (q[3] + z * q[4]))));
+    return 1.0 + r / s;
+}
+
+/* For x >= 8, the asymptotic expansions of qzero is
+ *      -1/8 s + 75/1024 s^3 - ..., where s = 1/x.
+ * We approximate pzero by
+ *      qzero(x) = s*(-1.25 + (R/S))
+ * where  R = qR0 + qR1*s^2 + qR2*s^4 + ... + qR5*s^10
+ *        S = 1 + qS0*s^2 + ... + qS5*s^12
+ * and
+ *      | qzero(x)/s +1.25-R/S | <= 2  ** ( -61.22)
+ */
+const QR8: [f32; 6] = [
+    /* for x in [inf, 8]=1/[0,0.125] */
+    0.0000000000e+00, /* 0x00000000 */
+    7.3242187500e-02, /* 0x3d960000 */
+    1.1768206596e+01, /* 0x413c4a93 */
+    5.5767340088e+02, /* 0x440b6b19 */
+    8.8591972656e+03, /* 0x460a6cca */
+    3.7014625000e+04, /* 0x471096a0 */
+];
+const QS8: [f32; 6] = [
+    1.6377603149e+02,  /* 0x4323c6aa */
+    8.0983447266e+03,  /* 0x45fd12c2 */
+    1.4253829688e+05,  /* 0x480b3293 */
+    8.0330925000e+05,  /* 0x49441ed4 */
+    8.4050156250e+05,  /* 0x494d3359 */
+    -3.4389928125e+05, /* 0xc8a7eb69 */
+];
+
+const QR5: [f32; 6] = [
+    /* for x in [8,4.5454]=1/[0.125,0.22001] */
+    1.8408595828e-11, /* 0x2da1ec79 */
+    7.3242180049e-02, /* 0x3d95ffff */
+    5.8356351852e+00, /* 0x40babd86 */
+    1.3511157227e+02, /* 0x43071c90 */
+    1.0272437744e+03, /* 0x448067cd */
+    1.9899779053e+03, /* 0x44f8bf4b */
+];
+const QS5: [f32; 6] = [
+    8.2776611328e+01,  /* 0x42a58da0 */
+    2.0778142090e+03,  /* 0x4501dd07 */
+    1.8847289062e+04,  /* 0x46933e94 */
+    5.6751113281e+04,  /* 0x475daf1d */
+    3.5976753906e+04,  /* 0x470c88c1 */
+    -5.3543427734e+03, /* 0xc5a752be */
+];
+
+const QR3: [f32; 6] = [
+    /* for x in [4.547,2.8571]=1/[0.2199,0.35001] */
+    4.3774099900e-09, /* 0x3196681b */
+    7.3241114616e-02, /* 0x3d95ff70 */
+    3.3442313671e+00, /* 0x405607e3 */
+    4.2621845245e+01, /* 0x422a7cc5 */
+    1.7080809021e+02, /* 0x432acedf */
+    1.6673394775e+02, /* 0x4326bbe4 */
+];
+const QS3: [f32; 6] = [
+    4.8758872986e+01,  /* 0x42430916 */
+    7.0968920898e+02,  /* 0x44316c1c */
+    3.7041481934e+03,  /* 0x4567825f */
+    6.4604252930e+03,  /* 0x45c9e367 */
+    2.5163337402e+03,  /* 0x451d4557 */
+    -1.4924745178e+02, /* 0xc3153f59 */
+];
+
+const QR2: [f32; 6] = [
+    /* for x in [2.8570,2]=1/[0.3499,0.5] */
+    1.5044444979e-07, /* 0x342189db */
+    7.3223426938e-02, /* 0x3d95f62a */
+    1.9981917143e+00, /* 0x3fffc4bf */
+    1.4495602608e+01, /* 0x4167edfd */
+    3.1666231155e+01, /* 0x41fd5471 */
+    1.6252708435e+01, /* 0x4182058c */
+];
+const QS2: [f32; 6] = [
+    3.0365585327e+01,  /* 0x41f2ecb8 */
+    2.6934811401e+02,  /* 0x4386ac8f */
+    8.4478375244e+02,  /* 0x44533229 */
+    8.8293585205e+02,  /* 0x445cbbe5 */
+    2.1266638184e+02,  /* 0x4354aa98 */
+    -5.3109550476e+00, /* 0xc0a9f358 */
+];
+
+fn qzerof(x: f32) -> f32 {
+    let p: &[f32; 6];
+    let q: &[f32; 6];
+    let s: f32;
+    let r: f32;
+    let z: f32;
+    let mut ix: u32;
+
+    ix = x.to_bits();
+    ix &= 0x7fffffff;
+    if ix >= 0x41000000 {
+        p = &QR8;
+        q = &QS8;
+    } else if ix >= 0x409173eb {
+        p = &QR5;
+        q = &QS5;
+    } else if ix >= 0x4036d917 {
+        p = &QR3;
+        q = &QS3;
+    } else
+    /*ix >= 0x40000000*/
+    {
+        p = &QR2;
+        q = &QS2;
+    }
+    z = 1.0 / (x * x);
+    r = p[0] + z * (p[1] + z * (p[2] + z * (p[3] + z * (p[4] + z * p[5]))));
+    s = 1.0 + z * (q[0] + z * (q[1] + z * (q[2] + z * (q[3] + z * (q[4] + z * q[5])))));
+    return (-0.125 + r / s) / x;
+}
+
+
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+
+/* origin: FreeBSD /usr/src/lib/msun/src/e_j1.c */
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunSoft, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+/* j1(x), y1(x)
+ * Bessel function of the first and second kinds of order zero.
+ * Method -- j1(x):
+ *      1. For tiny x, we use j1(x) = x/2 - x^3/16 + x^5/384 - ...
+ *      2. Reduce x to |x| since j1(x)=-j1(-x),  and
+ *         for x in (0,2)
+ *              j1(x) = x/2 + x*z*R0/S0,  where z = x*x;
+ *         (precision:  |j1/x - 1/2 - R0/S0 |<2**-61.51 )
+ *         for x in (2,inf)
+ *              j1(x) = sqrt(2/(pi*x))*(p1(x)*cos(x1)-q1(x)*sin(x1))
+ *              y1(x) = sqrt(2/(pi*x))*(p1(x)*sin(x1)+q1(x)*cos(x1))
+ *         where x1 = x-3*pi/4. It is better to compute sin(x1),cos(x1)
+ *         as follow:
+ *              cos(x1) =  cos(x)cos(3pi/4)+sin(x)sin(3pi/4)
+ *                      =  1/sqrt(2) * (sin(x) - cos(x))
+ *              sin(x1) =  sin(x)cos(3pi/4)-cos(x)sin(3pi/4)
+ *                      = -1/sqrt(2) * (sin(x) + cos(x))
+ *         (To avoid cancellation, use
+ *              sin(x) +- cos(x) = -cos(2x)/(sin(x) -+ cos(x))
+ *          to compute the worse one.)
+ *
+ *      3 Special cases
+ *              j1(nan)= nan
+ *              j1(0) = 0
+ *              j1(inf) = 0
+ *
+ * Method -- y1(x):
+ *      1. screen out x<=0 cases: y1(0)=-inf, y1(x<0)=NaN
+ *      2. For x<2.
+ *         Since
+ *              y1(x) = 2/pi*(j1(x)*(ln(x/2)+Euler)-1/x-x/2+5/64*x^3-...)
+ *         therefore y1(x)-2/pi*j1(x)*ln(x)-1/x is an odd function.
+ *         We use the following function to approximate y1,
+ *              y1(x) = x*U(z)/V(z) + (2/pi)*(j1(x)*ln(x)-1/x), z= x^2
+ *         where for x in [0,2] (abs err less than 2**-65.89)
+ *              U(z) = U0[0] + U0[1]*z + ... + U0[4]*z^4
+ *              V(z) = 1  + v0[0]*z + ... + v0[4]*z^5
+ *         Note: For tiny x, 1/x dominate y1 and hence
+ *              y1(tiny) = -2/pi/tiny, (choose tiny<2**-54)
+ *      3. For x>=2.
+ *              y1(x) = sqrt(2/(pi*x))*(p1(x)*sin(x1)+q1(x)*cos(x1))
+ *         where x1 = x-3*pi/4. It is better to compute sin(x1),cos(x1)
+ *         by method mentioned above.
+ */
+
+use super::{cos, fabs, get_high_word, get_low_word, log, sin, sqrt};
+
+const INVSQRTPI: f64 = 5.64189583547756279280e-01; /* 0x3FE20DD7, 0x50429B6D */
+const TPI: f64 = 6.36619772367581382433e-01; /* 0x3FE45F30, 0x6DC9C883 */
+
+fn common(ix: u32, x: f64, y1: bool, sign: bool) -> f64 {
+    let z: f64;
+    let mut s: f64;
+    let c: f64;
+    let mut ss: f64;
+    let mut cc: f64;
+
+    /*
+     * j1(x) = sqrt(2/(pi*x))*(p1(x)*cos(x-3pi/4)-q1(x)*sin(x-3pi/4))
+     * y1(x) = sqrt(2/(pi*x))*(p1(x)*sin(x-3pi/4)+q1(x)*cos(x-3pi/4))
+     *
+     * sin(x-3pi/4) = -(sin(x) + cos(x))/sqrt(2)
+     * cos(x-3pi/4) = (sin(x) - cos(x))/sqrt(2)
+     * sin(x) +- cos(x) = -cos(2x)/(sin(x) -+ cos(x))
+     */
+    s = sin(x);
+    if y1 {
+        s = -s;
+    }
+    c = cos(x);
+    cc = s - c;
+    if ix < 0x7fe00000 {
+        /* avoid overflow in 2*x */
+        ss = -s - c;
+        z = cos(2.0 * x);
+        if s * c > 0.0 {
+            cc = z / ss;
+        } else {
+            ss = z / cc;
+        }
+        if ix < 0x48000000 {
+            if y1 {
+                ss = -ss;
+            }
+            cc = pone(x) * cc - qone(x) * ss;
+        }
+    }
+    if sign {
+        cc = -cc;
+    }
+    return INVSQRTPI * cc / sqrt(x);
+}
+
+/* R0/S0 on [0,2] */
+const R00: f64 = -6.25000000000000000000e-02; /* 0xBFB00000, 0x00000000 */
+const R01: f64 = 1.40705666955189706048e-03; /* 0x3F570D9F, 0x98472C61 */
+const R02: f64 = -1.59955631084035597520e-05; /* 0xBEF0C5C6, 0xBA169668 */
+const R03: f64 = 4.96727999609584448412e-08; /* 0x3E6AAAFA, 0x46CA0BD9 */
+const S01: f64 = 1.91537599538363460805e-02; /* 0x3F939D0B, 0x12637E53 */
+const S02: f64 = 1.85946785588630915560e-04; /* 0x3F285F56, 0xB9CDF664 */
+const S03: f64 = 1.17718464042623683263e-06; /* 0x3EB3BFF8, 0x333F8498 */
+const S04: f64 = 5.04636257076217042715e-09; /* 0x3E35AC88, 0xC97DFF2C */
+const S05: f64 = 1.23542274426137913908e-11; /* 0x3DAB2ACF, 0xCFB97ED8 */
+
+pub fn j1(x: f64) -> f64 {
+    let mut z: f64;
+    let r: f64;
+    let s: f64;
+    let mut ix: u32;
+    let sign: bool;
+
+    ix = get_high_word(x);
+    sign = (ix >> 31) != 0;
+    ix &= 0x7fffffff;
+    if ix >= 0x7ff00000 {
+        return 1.0 / (x * x);
+    }
+    if ix >= 0x40000000 {
+        /* |x| >= 2 */
+        return common(ix, fabs(x), false, sign);
+    }
+    if ix >= 0x38000000 {
+        /* |x| >= 2**-127 */
+        z = x * x;
+        r = z * (R00 + z * (R01 + z * (R02 + z * R03)));
+        s = 1.0 + z * (S01 + z * (S02 + z * (S03 + z * (S04 + z * S05))));
+        z = r / s;
+    } else {
+        /* avoid underflow, raise inexact if x!=0 */
+        z = x;
+    }
+    return (0.5 + z) * x;
+}
+
+const U0: [f64; 5] = [
+    -1.96057090646238940668e-01, /* 0xBFC91866, 0x143CBC8A */
+    5.04438716639811282616e-02,  /* 0x3FA9D3C7, 0x76292CD1 */
+    -1.91256895875763547298e-03, /* 0xBF5F55E5, 0x4844F50F */
+    2.35252600561610495928e-05,  /* 0x3EF8AB03, 0x8FA6B88E */
+    -9.19099158039878874504e-08, /* 0xBE78AC00, 0x569105B8 */
+];
+const V0: [f64; 5] = [
+    1.99167318236649903973e-02, /* 0x3F94650D, 0x3F4DA9F0 */
+    2.02552581025135171496e-04, /* 0x3F2A8C89, 0x6C257764 */
+    1.35608801097516229404e-06, /* 0x3EB6C05A, 0x894E8CA6 */
+    6.22741452364621501295e-09, /* 0x3E3ABF1D, 0x5BA69A86 */
+    1.66559246207992079114e-11, /* 0x3DB25039, 0xDACA772A */
+];
+
+pub fn y1(x: f64) -> f64 {
+    let z: f64;
+    let u: f64;
+    let v: f64;
+    let ix: u32;
+    let lx: u32;
+
+    ix = get_high_word(x);
+    lx = get_low_word(x);
+
+    /* y1(nan)=nan, y1(<0)=nan, y1(0)=-inf, y1(inf)=0 */
+    if (ix << 1 | lx) == 0 {
+        return -1.0 / 0.0;
+    }
+    if (ix >> 31) != 0 {
+        return 0.0 / 0.0;
+    }
+    if ix >= 0x7ff00000 {
+        return 1.0 / x;
+    }
+
+    if ix >= 0x40000000 {
+        /* x >= 2 */
+        return common(ix, x, true, false);
+    }
+    if ix < 0x3c900000 {
+        /* x < 2**-54 */
+        return -TPI / x;
+    }
+    z = x * x;
+    u = U0[0] + z * (U0[1] + z * (U0[2] + z * (U0[3] + z * U0[4])));
+    v = 1.0 + z * (V0[0] + z * (V0[1] + z * (V0[2] + z * (V0[3] + z * V0[4]))));
+    return x * (u / v) + TPI * (j1(x) * log(x) - 1.0 / x);
+}
+
+/* For x >= 8, the asymptotic expansions of pone is
+ *      1 + 15/128 s^2 - 4725/2^15 s^4 - ...,   where s = 1/x.
+ * We approximate pone by
+ *      pone(x) = 1 + (R/S)
+ * where  R = pr0 + pr1*s^2 + pr2*s^4 + ... + pr5*s^10
+ *        S = 1 + ps0*s^2 + ... + ps4*s^10
+ * and
+ *      | pone(x)-1-R/S | <= 2  ** ( -60.06)
+ */
+
+const PR8: [f64; 6] = [
+    /* for x in [inf, 8]=1/[0,0.125] */
+    0.00000000000000000000e+00, /* 0x00000000, 0x00000000 */
+    1.17187499999988647970e-01, /* 0x3FBDFFFF, 0xFFFFFCCE */
+    1.32394806593073575129e+01, /* 0x402A7A9D, 0x357F7FCE */
+    4.12051854307378562225e+02, /* 0x4079C0D4, 0x652EA590 */
+    3.87474538913960532227e+03, /* 0x40AE457D, 0xA3A532CC */
+    7.91447954031891731574e+03, /* 0x40BEEA7A, 0xC32782DD */
+];
+const PS8: [f64; 5] = [
+    1.14207370375678408436e+02, /* 0x405C8D45, 0x8E656CAC */
+    3.65093083420853463394e+03, /* 0x40AC85DC, 0x964D274F */
+    3.69562060269033463555e+04, /* 0x40E20B86, 0x97C5BB7F */
+    9.76027935934950801311e+04, /* 0x40F7D42C, 0xB28F17BB */
+    3.08042720627888811578e+04, /* 0x40DE1511, 0x697A0B2D */
+];
+
+const PR5: [f64; 6] = [
+    /* for x in [8,4.5454]=1/[0.125,0.22001] */
+    1.31990519556243522749e-11, /* 0x3DAD0667, 0xDAE1CA7D */
+    1.17187493190614097638e-01, /* 0x3FBDFFFF, 0xE2C10043 */
+    6.80275127868432871736e+00, /* 0x401B3604, 0x6E6315E3 */
+    1.08308182990189109773e+02, /* 0x405B13B9, 0x452602ED */
+    5.17636139533199752805e+02, /* 0x40802D16, 0xD052D649 */
+    5.28715201363337541807e+02, /* 0x408085B8, 0xBB7E0CB7 */
+];
+const PS5: [f64; 5] = [
+    5.92805987221131331921e+01, /* 0x404DA3EA, 0xA8AF633D */
+    9.91401418733614377743e+02, /* 0x408EFB36, 0x1B066701 */
+    5.35326695291487976647e+03, /* 0x40B4E944, 0x5706B6FB */
+    7.84469031749551231769e+03, /* 0x40BEA4B0, 0xB8A5BB15 */
+    1.50404688810361062679e+03, /* 0x40978030, 0x036F5E51 */
+];
+
+const PR3: [f64; 6] = [
+    3.02503916137373618024e-09, /* 0x3E29FC21, 0xA7AD9EDD */
+    1.17186865567253592491e-01, /* 0x3FBDFFF5, 0x5B21D17B */
+    3.93297750033315640650e+00, /* 0x400F76BC, 0xE85EAD8A */
+    3.51194035591636932736e+01, /* 0x40418F48, 0x9DA6D129 */
+    9.10550110750781271918e+01, /* 0x4056C385, 0x4D2C1837 */
+    4.85590685197364919645e+01, /* 0x4048478F, 0x8EA83EE5 */
+];
+const PS3: [f64; 5] = [
+    3.47913095001251519989e+01, /* 0x40416549, 0xA134069C */
+    3.36762458747825746741e+02, /* 0x40750C33, 0x07F1A75F */
+    1.04687139975775130551e+03, /* 0x40905B7C, 0x5037D523 */
+    8.90811346398256432622e+02, /* 0x408BD67D, 0xA32E31E9 */
+    1.03787932439639277504e+02, /* 0x4059F26D, 0x7C2EED53 */
+];
+
+const PR2: [f64; 6] = [
+    /* for x in [2.8570,2]=1/[0.3499,0.5] */
+    1.07710830106873743082e-07, /* 0x3E7CE9D4, 0xF65544F4 */
+    1.17176219462683348094e-01, /* 0x3FBDFF42, 0xBE760D83 */
+    2.36851496667608785174e+00, /* 0x4002F2B7, 0xF98FAEC0 */
+    1.22426109148261232917e+01, /* 0x40287C37, 0x7F71A964 */
+    1.76939711271687727390e+01, /* 0x4031B1A8, 0x177F8EE2 */
+    5.07352312588818499250e+00, /* 0x40144B49, 0xA574C1FE */
+];
+const PS2: [f64; 5] = [
+    2.14364859363821409488e+01, /* 0x40356FBD, 0x8AD5ECDC */
+    1.25290227168402751090e+02, /* 0x405F5293, 0x14F92CD5 */
+    2.32276469057162813669e+02, /* 0x406D08D8, 0xD5A2DBD9 */
+    1.17679373287147100768e+02, /* 0x405D6B7A, 0xDA1884A9 */
+    8.36463893371618283368e+00, /* 0x4020BAB1, 0xF44E5192 */
+];
+
+fn pone(x: f64) -> f64 {
+    let p: &[f64; 6];
+    let q: &[f64; 5];
+    let z: f64;
+    let r: f64;
+    let s: f64;
+    let mut ix: u32;
+
+    ix = get_high_word(x);
+    ix &= 0x7fffffff;
+    if ix >= 0x40200000 {
+        p = &PR8;
+        q = &PS8;
+    } else if ix >= 0x40122E8B {
+        p = &PR5;
+        q = &PS5;
+    } else if ix >= 0x4006DB6D {
+        p = &PR3;
+        q = &PS3;
+    } else
+    /*ix >= 0x40000000*/
+    {
+        p = &PR2;
+        q = &PS2;
+    }
+    z = 1.0 / (x * x);
+    r = p[0] + z * (p[1] + z * (p[2] + z * (p[3] + z * (p[4] + z * p[5]))));
+    s = 1.0 + z * (q[0] + z * (q[1] + z * (q[2] + z * (q[3] + z * q[4]))));
+    return 1.0 + r / s;
+}
+
+/* For x >= 8, the asymptotic expansions of qone is
+ *      3/8 s - 105/1024 s^3 - ..., where s = 1/x.
+ * We approximate pone by
+ *      qone(x) = s*(0.375 + (R/S))
+ * where  R = qr1*s^2 + qr2*s^4 + ... + qr5*s^10
+ *        S = 1 + qs1*s^2 + ... + qs6*s^12
+ * and
+ *      | qone(x)/s -0.375-R/S | <= 2  ** ( -61.13)
+ */
+
+const QR8: [f64; 6] = [
+    /* for x in [inf, 8]=1/[0,0.125] */
+    0.00000000000000000000e+00,  /* 0x00000000, 0x00000000 */
+    -1.02539062499992714161e-01, /* 0xBFBA3FFF, 0xFFFFFDF3 */
+    -1.62717534544589987888e+01, /* 0xC0304591, 0xA26779F7 */
+    -7.59601722513950107896e+02, /* 0xC087BCD0, 0x53E4B576 */
+    -1.18498066702429587167e+04, /* 0xC0C724E7, 0x40F87415 */
+    -4.84385124285750353010e+04, /* 0xC0E7A6D0, 0x65D09C6A */
+];
+const QS8: [f64; 6] = [
+    1.61395369700722909556e+02,  /* 0x40642CA6, 0xDE5BCDE5 */
+    7.82538599923348465381e+03,  /* 0x40BE9162, 0xD0D88419 */
+    1.33875336287249578163e+05,  /* 0x4100579A, 0xB0B75E98 */
+    7.19657723683240939863e+05,  /* 0x4125F653, 0x72869C19 */
+    6.66601232617776375264e+05,  /* 0x412457D2, 0x7719AD5C */
+    -2.94490264303834643215e+05, /* 0xC111F969, 0x0EA5AA18 */
+];
+
+const QR5: [f64; 6] = [
+    /* for x in [8,4.5454]=1/[0.125,0.22001] */
+    -2.08979931141764104297e-11, /* 0xBDB6FA43, 0x1AA1A098 */
+    -1.02539050241375426231e-01, /* 0xBFBA3FFF, 0xCB597FEF */
+    -8.05644828123936029840e+00, /* 0xC0201CE6, 0xCA03AD4B */
+    -1.83669607474888380239e+02, /* 0xC066F56D, 0x6CA7B9B0 */
+    -1.37319376065508163265e+03, /* 0xC09574C6, 0x6931734F */
+    -2.61244440453215656817e+03, /* 0xC0A468E3, 0x88FDA79D */
+];
+const QS5: [f64; 6] = [
+    8.12765501384335777857e+01,  /* 0x405451B2, 0xFF5A11B2 */
+    1.99179873460485964642e+03,  /* 0x409F1F31, 0xE77BF839 */
+    1.74684851924908907677e+04,  /* 0x40D10F1F, 0x0D64CE29 */
+    4.98514270910352279316e+04,  /* 0x40E8576D, 0xAABAD197 */
+    2.79480751638918118260e+04,  /* 0x40DB4B04, 0xCF7C364B */
+    -4.71918354795128470869e+03, /* 0xC0B26F2E, 0xFCFFA004 */
+];
+
+const QR3: [f64; 6] = [
+    -5.07831226461766561369e-09, /* 0xBE35CFA9, 0xD38FC84F */
+    -1.02537829820837089745e-01, /* 0xBFBA3FEB, 0x51AEED54 */
+    -4.61011581139473403113e+00, /* 0xC01270C2, 0x3302D9FF */
+    -5.78472216562783643212e+01, /* 0xC04CEC71, 0xC25D16DA */
+    -2.28244540737631695038e+02, /* 0xC06C87D3, 0x4718D55F */
+    -2.19210128478909325622e+02, /* 0xC06B66B9, 0x5F5C1BF6 */
+];
+const QS3: [f64; 6] = [
+    4.76651550323729509273e+01,  /* 0x4047D523, 0xCCD367E4 */
+    6.73865112676699709482e+02,  /* 0x40850EEB, 0xC031EE3E */
+    3.38015286679526343505e+03,  /* 0x40AA684E, 0x448E7C9A */
+    5.54772909720722782367e+03,  /* 0x40B5ABBA, 0xA61D54A6 */
+    1.90311919338810798763e+03,  /* 0x409DBC7A, 0x0DD4DF4B */
+    -1.35201191444307340817e+02, /* 0xC060E670, 0x290A311F */
+];
+
+const QR2: [f64; 6] = [
+    /* for x in [2.8570,2]=1/[0.3499,0.5] */
+    -1.78381727510958865572e-07, /* 0xBE87F126, 0x44C626D2 */
+    -1.02517042607985553460e-01, /* 0xBFBA3E8E, 0x9148B010 */
+    -2.75220568278187460720e+00, /* 0xC0060484, 0x69BB4EDA */
+    -1.96636162643703720221e+01, /* 0xC033A9E2, 0xC168907F */
+    -4.23253133372830490089e+01, /* 0xC04529A3, 0xDE104AAA */
+    -2.13719211703704061733e+01, /* 0xC0355F36, 0x39CF6E52 */
+];
+const QS2: [f64; 6] = [
+    2.95333629060523854548e+01,  /* 0x403D888A, 0x78AE64FF */
+    2.52981549982190529136e+02,  /* 0x406F9F68, 0xDB821CBA */
+    7.57502834868645436472e+02,  /* 0x4087AC05, 0xCE49A0F7 */
+    7.39393205320467245656e+02,  /* 0x40871B25, 0x48D4C029 */
+    1.55949003336666123687e+02,  /* 0x40637E5E, 0x3C3ED8D4 */
+    -4.95949898822628210127e+00, /* 0xC013D686, 0xE71BE86B */
+];
+
+fn qone(x: f64) -> f64 {
+    let p: &[f64; 6];
+    let q: &[f64; 6];
+    let s: f64;
+    let r: f64;
+    let z: f64;
+    let mut ix: u32;
+
+    ix = get_high_word(x);
+    ix &= 0x7fffffff;
+    if ix >= 0x40200000 {
+        p = &QR8;
+        q = &QS8;
+    } else if ix >= 0x40122E8B {
+        p = &QR5;
+        q = &QS5;
+    } else if ix >= 0x4006DB6D {
+        p = &QR3;
+        q = &QS3;
+    } else
+    /*ix >= 0x40000000*/
+    {
+        p = &QR2;
+        q = &QS2;
+    }
+    z = 1.0 / (x * x);
+    r = p[0] + z * (p[1] + z * (p[2] + z * (p[3] + z * (p[4] + z * p[5]))));
+    s = 1.0 + z * (q[0] + z * (q[1] + z * (q[2] + z * (q[3] + z * (q[4] + z * q[5])))));
+    return (0.375 + r / s) / x;
+}
+
+
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+
+/* origin: FreeBSD /usr/src/lib/msun/src/e_j1f.c */
+/*
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+use super::{cosf, fabsf, logf, sinf, sqrtf};
+
+const INVSQRTPI: f32 = 5.6418961287e-01; /* 0x3f106ebb */
+const TPI: f32 = 6.3661974669e-01; /* 0x3f22f983 */
+
+fn common(ix: u32, x: f32, y1: bool, sign: bool) -> f32 {
+    let z: f64;
+    let mut s: f64;
+    let c: f64;
+    let mut ss: f64;
+    let mut cc: f64;
+
+    s = sinf(x) as f64;
+    if y1 {
+        s = -s;
+    }
+    c = cosf(x) as f64;
+    cc = s - c;
+    if ix < 0x7f000000 {
+        ss = -s - c;
+        z = cosf(2.0 * x) as f64;
+        if s * c > 0.0 {
+            cc = z / ss;
+        } else {
+            ss = z / cc;
+        }
+        if ix < 0x58800000 {
+            if y1 {
+                ss = -ss;
+            }
+            cc = (ponef(x) as f64) * cc - (qonef(x) as f64) * ss;
+        }
+    }
+    if sign {
+        cc = -cc;
+    }
+    return INVSQRTPI * (cc as f32) / sqrtf(x);
+}
+
+/* R0/S0 on [0,2] */
+const R00: f32 = -6.2500000000e-02; /* 0xbd800000 */
+const R01: f32 = 1.4070566976e-03; /* 0x3ab86cfd */
+const R02: f32 = -1.5995563444e-05; /* 0xb7862e36 */
+const R03: f32 = 4.9672799207e-08; /* 0x335557d2 */
+const S01: f32 = 1.9153760746e-02; /* 0x3c9ce859 */
+const S02: f32 = 1.8594678841e-04; /* 0x3942fab6 */
+const S03: f32 = 1.1771846857e-06; /* 0x359dffc2 */
+const S04: f32 = 5.0463624390e-09; /* 0x31ad6446 */
+const S05: f32 = 1.2354227016e-11; /* 0x2d59567e */
+
+pub fn j1f(x: f32) -> f32 {
+    let mut z: f32;
+    let r: f32;
+    let s: f32;
+    let mut ix: u32;
+    let sign: bool;
+
+    ix = x.to_bits();
+    sign = (ix >> 31) != 0;
+    ix &= 0x7fffffff;
+    if ix >= 0x7f800000 {
+        return 1.0 / (x * x);
+    }
+    if ix >= 0x40000000 {
+        /* |x| >= 2 */
+        return common(ix, fabsf(x), false, sign);
+    }
+    if ix >= 0x39000000 {
+        /* |x| >= 2**-13 */
+        z = x * x;
+        r = z * (R00 + z * (R01 + z * (R02 + z * R03)));
+        s = 1.0 + z * (S01 + z * (S02 + z * (S03 + z * (S04 + z * S05))));
+        z = 0.5 + r / s;
+    } else {
+        z = 0.5;
+    }
+    return z * x;
+}
+
+const U0: [f32; 5] = [
+    -1.9605709612e-01, /* 0xbe48c331 */
+    5.0443872809e-02,  /* 0x3d4e9e3c */
+    -1.9125689287e-03, /* 0xbafaaf2a */
+    2.3525259166e-05,  /* 0x37c5581c */
+    -9.1909917899e-08, /* 0xb3c56003 */
+];
+const V0: [f32; 5] = [
+    1.9916731864e-02, /* 0x3ca3286a */
+    2.0255257550e-04, /* 0x3954644b */
+    1.3560879779e-06, /* 0x35b602d4 */
+    6.2274145840e-09, /* 0x31d5f8eb */
+    1.6655924903e-11, /* 0x2d9281cf */
+];
+
+pub fn y1f(x: f32) -> f32 {
+    let z: f32;
+    let u: f32;
+    let v: f32;
+    let ix: u32;
+
+    ix = x.to_bits();
+    if (ix & 0x7fffffff) == 0 {
+        return -1.0 / 0.0;
+    }
+    if (ix >> 31) != 0 {
+        return 0.0 / 0.0;
+    }
+    if ix >= 0x7f800000 {
+        return 1.0 / x;
+    }
+    if ix >= 0x40000000 {
+        /* |x| >= 2.0 */
+        return common(ix, x, true, false);
+    }
+    if ix < 0x33000000 {
+        /* x < 2**-25 */
+        return -TPI / x;
+    }
+    z = x * x;
+    u = U0[0] + z * (U0[1] + z * (U0[2] + z * (U0[3] + z * U0[4])));
+    v = 1.0 + z * (V0[0] + z * (V0[1] + z * (V0[2] + z * (V0[3] + z * V0[4]))));
+    return x * (u / v) + TPI * (j1f(x) * logf(x) - 1.0 / x);
+}
+
+/* For x >= 8, the asymptotic expansions of pone is
+ *      1 + 15/128 s^2 - 4725/2^15 s^4 - ...,   where s = 1/x.
+ * We approximate pone by
+ *      pone(x) = 1 + (R/S)
+ * where  R = pr0 + pr1*s^2 + pr2*s^4 + ... + pr5*s^10
+ *        S = 1 + ps0*s^2 + ... + ps4*s^10
+ * and
+ *      | pone(x)-1-R/S | <= 2  ** ( -60.06)
+ */
+
+const PR8: [f32; 6] = [
+    /* for x in [inf, 8]=1/[0,0.125] */
+    0.0000000000e+00, /* 0x00000000 */
+    1.1718750000e-01, /* 0x3df00000 */
+    1.3239480972e+01, /* 0x4153d4ea */
+    4.1205184937e+02, /* 0x43ce06a3 */
+    3.8747453613e+03, /* 0x45722bed */
+    7.9144794922e+03, /* 0x45f753d6 */
+];
+const PS8: [f32; 5] = [
+    1.1420736694e+02, /* 0x42e46a2c */
+    3.6509309082e+03, /* 0x45642ee5 */
+    3.6956207031e+04, /* 0x47105c35 */
+    9.7602796875e+04, /* 0x47bea166 */
+    3.0804271484e+04, /* 0x46f0a88b */
+];
+
+const PR5: [f32; 6] = [
+    /* for x in [8,4.5454]=1/[0.125,0.22001] */
+    1.3199052094e-11, /* 0x2d68333f */
+    1.1718749255e-01, /* 0x3defffff */
+    6.8027510643e+00, /* 0x40d9b023 */
+    1.0830818176e+02, /* 0x42d89dca */
+    5.1763616943e+02, /* 0x440168b7 */
+    5.2871520996e+02, /* 0x44042dc6 */
+];
+const PS5: [f32; 5] = [
+    5.9280597687e+01, /* 0x426d1f55 */
+    9.9140142822e+02, /* 0x4477d9b1 */
+    5.3532670898e+03, /* 0x45a74a23 */
+    7.8446904297e+03, /* 0x45f52586 */
+    1.5040468750e+03, /* 0x44bc0180 */
+];
+
+const PR3: [f32; 6] = [
+    3.0250391081e-09, /* 0x314fe10d */
+    1.1718686670e-01, /* 0x3defffab */
+    3.9329774380e+00, /* 0x407bb5e7 */
+    3.5119403839e+01, /* 0x420c7a45 */
+    9.1055007935e+01, /* 0x42b61c2a */
+    4.8559066772e+01, /* 0x42423c7c */
+];
+const PS3: [f32; 5] = [
+    3.4791309357e+01, /* 0x420b2a4d */
+    3.3676245117e+02, /* 0x43a86198 */
+    1.0468714600e+03, /* 0x4482dbe3 */
+    8.9081134033e+02, /* 0x445eb3ed */
+    1.0378793335e+02, /* 0x42cf936c */
+];
+
+const PR2: [f32; 6] = [
+    /* for x in [2.8570,2]=1/[0.3499,0.5] */
+    1.0771083225e-07, /* 0x33e74ea8 */
+    1.1717621982e-01, /* 0x3deffa16 */
+    2.3685150146e+00, /* 0x401795c0 */
+    1.2242610931e+01, /* 0x4143e1bc */
+    1.7693971634e+01, /* 0x418d8d41 */
+    5.0735230446e+00, /* 0x40a25a4d */
+];
+const PS2: [f32; 5] = [
+    2.1436485291e+01, /* 0x41ab7dec */
+    1.2529022980e+02, /* 0x42fa9499 */
+    2.3227647400e+02, /* 0x436846c7 */
+    1.1767937469e+02, /* 0x42eb5bd7 */
+    8.3646392822e+00, /* 0x4105d590 */
+];
+
+fn ponef(x: f32) -> f32 {
+    let p: &[f32; 6];
+    let q: &[f32; 5];
+    let z: f32;
+    let r: f32;
+    let s: f32;
+    let mut ix: u32;
+
+    ix = x.to_bits();
+    ix &= 0x7fffffff;
+    if ix >= 0x41000000 {
+        p = &PR8;
+        q = &PS8;
+    } else if ix >= 0x409173eb {
+        p = &PR5;
+        q = &PS5;
+    } else if ix >= 0x4036d917 {
+        p = &PR3;
+        q = &PS3;
+    } else
+    /*ix >= 0x40000000*/
+    {
+        p = &PR2;
+        q = &PS2;
+    }
+    z = 1.0 / (x * x);
+    r = p[0] + z * (p[1] + z * (p[2] + z * (p[3] + z * (p[4] + z * p[5]))));
+    s = 1.0 + z * (q[0] + z * (q[1] + z * (q[2] + z * (q[3] + z * q[4]))));
+    return 1.0 + r / s;
+}
+
+/* For x >= 8, the asymptotic expansions of qone is
+ *      3/8 s - 105/1024 s^3 - ..., where s = 1/x.
+ * We approximate pone by
+ *      qone(x) = s*(0.375 + (R/S))
+ * where  R = qr1*s^2 + qr2*s^4 + ... + qr5*s^10
+ *        S = 1 + qs1*s^2 + ... + qs6*s^12
+ * and
+ *      | qone(x)/s -0.375-R/S | <= 2  ** ( -61.13)
+ */
+
+const QR8: [f32; 6] = [
+    /* for x in [inf, 8]=1/[0,0.125] */
+    0.0000000000e+00,  /* 0x00000000 */
+    -1.0253906250e-01, /* 0xbdd20000 */
+    -1.6271753311e+01, /* 0xc1822c8d */
+    -7.5960174561e+02, /* 0xc43de683 */
+    -1.1849806641e+04, /* 0xc639273a */
+    -4.8438511719e+04, /* 0xc73d3683 */
+];
+const QS8: [f32; 6] = [
+    1.6139537048e+02,  /* 0x43216537 */
+    7.8253862305e+03,  /* 0x45f48b17 */
+    1.3387534375e+05,  /* 0x4802bcd6 */
+    7.1965775000e+05,  /* 0x492fb29c */
+    6.6660125000e+05,  /* 0x4922be94 */
+    -2.9449025000e+05, /* 0xc88fcb48 */
+];
+
+const QR5: [f32; 6] = [
+    /* for x in [8,4.5454]=1/[0.125,0.22001] */
+    -2.0897993405e-11, /* 0xadb7d219 */
+    -1.0253904760e-01, /* 0xbdd1fffe */
+    -8.0564479828e+00, /* 0xc100e736 */
+    -1.8366960144e+02, /* 0xc337ab6b */
+    -1.3731937256e+03, /* 0xc4aba633 */
+    -2.6124443359e+03, /* 0xc523471c */
+];
+const QS5: [f32; 6] = [
+    8.1276550293e+01,  /* 0x42a28d98 */
+    1.9917987061e+03,  /* 0x44f8f98f */
+    1.7468484375e+04,  /* 0x468878f8 */
+    4.9851425781e+04,  /* 0x4742bb6d */
+    2.7948074219e+04,  /* 0x46da5826 */
+    -4.7191835938e+03, /* 0xc5937978 */
+];
+
+const QR3: [f32; 6] = [
+    -5.0783124372e-09, /* 0xb1ae7d4f */
+    -1.0253783315e-01, /* 0xbdd1ff5b */
+    -4.6101160049e+00, /* 0xc0938612 */
+    -5.7847221375e+01, /* 0xc267638e */
+    -2.2824453735e+02, /* 0xc3643e9a */
+    -2.1921012878e+02, /* 0xc35b35cb */
+];
+const QS3: [f32; 6] = [
+    4.7665153503e+01,  /* 0x423ea91e */
+    6.7386511230e+02,  /* 0x4428775e */
+    3.3801528320e+03,  /* 0x45534272 */
+    5.5477290039e+03,  /* 0x45ad5dd5 */
+    1.9031191406e+03,  /* 0x44ede3d0 */
+    -1.3520118713e+02, /* 0xc3073381 */
+];
+
+const QR2: [f32; 6] = [
+    /* for x in [2.8570,2]=1/[0.3499,0.5] */
+    -1.7838172539e-07, /* 0xb43f8932 */
+    -1.0251704603e-01, /* 0xbdd1f475 */
+    -2.7522056103e+00, /* 0xc0302423 */
+    -1.9663616180e+01, /* 0xc19d4f16 */
+    -4.2325313568e+01, /* 0xc2294d1f */
+    -2.1371921539e+01, /* 0xc1aaf9b2 */
+];
+const QS2: [f32; 6] = [
+    2.9533363342e+01,  /* 0x41ec4454 */
+    2.5298155212e+02,  /* 0x437cfb47 */
+    7.5750280762e+02,  /* 0x443d602e */
+    7.3939318848e+02,  /* 0x4438d92a */
+    1.5594900513e+02,  /* 0x431bf2f2 */
+    -4.9594988823e+00, /* 0xc09eb437 */
+];
+
+fn qonef(x: f32) -> f32 {
+    let p: &[f32; 6];
+    let q: &[f32; 6];
+    let s: f32;
+    let r: f32;
+    let z: f32;
+    let mut ix: u32;
+
+    ix = x.to_bits();
+    ix &= 0x7fffffff;
+    if ix >= 0x41000000 {
+        p = &QR8;
+        q = &QS8;
+    } else if ix >= 0x409173eb {
+        p = &QR5;
+        q = &QS5;
+    } else if ix >= 0x4036d917 {
+        p = &QR3;
+        q = &QS3;
+    } else
+    /*ix >= 0x40000000*/
+    {
+        p = &QR2;
+        q = &QS2;
+    }
+    z = 1.0 / (x * x);
+    r = p[0] + z * (p[1] + z * (p[2] + z * (p[3] + z * (p[4] + z * p[5]))));
+    s = 1.0 + z * (q[0] + z * (q[1] + z * (q[2] + z * (q[3] + z * (q[4] + z * q[5])))));
+    return (0.375 + r / s) / x;
+}
+
+
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+
+/* origin: FreeBSD /usr/src/lib/msun/src/e_jn.c */
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunSoft, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+/*
+ * jn(n, x), yn(n, x)
+ * floating point Bessel's function of the 1st and 2nd kind
+ * of order n
+ *
+ * Special cases:
+ *      y0(0)=y1(0)=yn(n,0) = -inf with division by zero signal;
+ *      y0(-ve)=y1(-ve)=yn(n,-ve) are NaN with invalid signal.
+ * Note 2. About jn(n,x), yn(n,x)
+ *      For n=0, j0(x) is called,
+ *      for n=1, j1(x) is called,
+ *      for n<=x, forward recursion is used starting
+ *      from values of j0(x) and j1(x).
+ *      for n>x, a continued fraction approximation to
+ *      j(n,x)/j(n-1,x) is evaluated and then backward
+ *      recursion is used starting from a supposed value
+ *      for j(n,x). The resulting value of j(0,x) is
+ *      compared with the actual value to correct the
+ *      supposed value of j(n,x).
+ *
+ *      yn(n,x) is similar in all respects, except
+ *      that forward recursion is used for all
+ *      values of n>1.
+ */
+
+use super::{cos, fabs, get_high_word, get_low_word, j0, j1, log, sin, sqrt, y0, y1};
+
+const INVSQRTPI: f64 = 5.64189583547756279280e-01; /* 0x3FE20DD7, 0x50429B6D */
+
+pub fn jn(n: i32, mut x: f64) -> f64 {
+    let mut ix: u32;
+    let lx: u32;
+    let nm1: i32;
+    let mut i: i32;
+    let mut sign: bool;
+    let mut a: f64;
+    let mut b: f64;
+    let mut temp: f64;
+
+    ix = get_high_word(x);
+    lx = get_low_word(x);
+    sign = (ix >> 31) != 0;
+    ix &= 0x7fffffff;
+
+    // -lx == !lx + 1
+    if (ix | (lx | ((!lx).wrapping_add(1))) >> 31) > 0x7ff00000 {
+        /* nan */
+        return x;
+    }
+
+    /* J(-n,x) = (-1)^n * J(n, x), J(n, -x) = (-1)^n * J(n, x)
+     * Thus, J(-n,x) = J(n,-x)
+     */
+    /* nm1 = |n|-1 is used instead of |n| to handle n==INT_MIN */
+    if n == 0 {
+        return j0(x);
+    }
+    if n < 0 {
+        nm1 = -(n + 1);
+        x = -x;
+        sign = !sign;
+    } else {
+        nm1 = n - 1;
+    }
+    if nm1 == 0 {
+        return j1(x);
+    }
+
+    sign &= (n & 1) != 0; /* even n: 0, odd n: signbit(x) */
+    x = fabs(x);
+    if (ix | lx) == 0 || ix == 0x7ff00000 {
+        /* if x is 0 or inf */
+        b = 0.0;
+    } else if (nm1 as f64) < x {
+        /* Safe to use J(n+1,x)=2n/x *J(n,x)-J(n-1,x) */
+        if ix >= 0x52d00000 {
+            /* x > 2**302 */
+            /* (x >> n**2)
+             *      Jn(x) = cos(x-(2n+1)*pi/4)*sqrt(2/x*pi)
+             *      Yn(x) = sin(x-(2n+1)*pi/4)*sqrt(2/x*pi)
+             *      Let s=sin(x), c=cos(x),
+             *          xn=x-(2n+1)*pi/4, sqt2 = sqrt(2),then
+             *
+             *             n    sin(xn)*sqt2    cos(xn)*sqt2
+             *          ----------------------------------
+             *             0     s-c             c+s
+             *             1    -s-c            -c+s
+             *             2    -s+c            -c-s
+             *             3     s+c             c-s
+             */
+            temp = match nm1 & 3 {
+                0 => -cos(x) + sin(x),
+                1 => -cos(x) - sin(x),
+                2 => cos(x) - sin(x),
+                3 | _ => cos(x) + sin(x),
+            };
+            b = INVSQRTPI * temp / sqrt(x);
+        } else {
+            a = j0(x);
+            b = j1(x);
+            i = 0;
+            while i < nm1 {
+                i += 1;
+                temp = b;
+                b = b * (2.0 * (i as f64) / x) - a; /* avoid underflow */
+                a = temp;
+            }
+        }
+    } else {
+        if ix < 0x3e100000 {
+            /* x < 2**-29 */
+            /* x is tiny, return the first Taylor expansion of J(n,x)
+             * J(n,x) = 1/n!*(x/2)^n  - ...
+             */
+            if nm1 > 32 {
+                /* underflow */
+                b = 0.0;
+            } else {
+                temp = x * 0.5;
+                b = temp;
+                a = 1.0;
+                i = 2;
+                while i <= nm1 + 1 {
+                    a *= i as f64; /* a = n! */
+                    b *= temp; /* b = (x/2)^n */
+                    i += 1;
+                }
+                b = b / a;
+            }
+        } else {
+            /* use backward recurrence */
+            /*                      x      x^2      x^2
+             *  J(n,x)/J(n-1,x) =  ----   ------   ------   .....
+             *                      2n  - 2(n+1) - 2(n+2)
+             *
+             *                      1      1        1
+             *  (for large x)   =  ----  ------   ------   .....
+             *                      2n   2(n+1)   2(n+2)
+             *                      -- - ------ - ------ -
+             *                       x     x         x
+             *
+             * Let w = 2n/x and h=2/x, then the above quotient
+             * is equal to the continued fraction:
+             *                  1
+             *      = -----------------------
+             *                     1
+             *         w - -----------------
+             *                        1
+             *              w+h - ---------
+             *                     w+2h - ...
+             *
+             * To determine how many terms needed, let
+             * Q(0) = w, Q(1) = w(w+h) - 1,
+             * Q(k) = (w+k*h)*Q(k-1) - Q(k-2),
+             * When Q(k) > 1e4      good for single
+             * When Q(k) > 1e9      good for double
+             * When Q(k) > 1e17     good for quadruple
+             */
+            /* determine k */
+            let mut t: f64;
+            let mut q0: f64;
+            let mut q1: f64;
+            let mut w: f64;
+            let h: f64;
+            let mut z: f64;
+            let mut tmp: f64;
+            let nf: f64;
+
+            let mut k: i32;
+
+            nf = (nm1 as f64) + 1.0;
+            w = 2.0 * nf / x;
+            h = 2.0 / x;
+            z = w + h;
+            q0 = w;
+            q1 = w * z - 1.0;
+            k = 1;
+            while q1 < 1.0e9 {
+                k += 1;
+                z += h;
+                tmp = z * q1 - q0;
+                q0 = q1;
+                q1 = tmp;
+            }
+            t = 0.0;
+            i = k;
+            while i >= 0 {
+                t = 1.0 / (2.0 * ((i as f64) + nf) / x - t);
+                i -= 1;
+            }
+            a = t;
+            b = 1.0;
+            /*  estimate log((2/x)^n*n!) = n*log(2/x)+n*ln(n)
+             *  Hence, if n*(log(2n/x)) > ...
+             *  single 8.8722839355e+01
+             *  double 7.09782712893383973096e+02
+             *  long double 1.1356523406294143949491931077970765006170e+04
+             *  then recurrent value may overflow and the result is
+             *  likely underflow to zero
+             */
+            tmp = nf * log(fabs(w));
+            if tmp < 7.09782712893383973096e+02 {
+                i = nm1;
+                while i > 0 {
+                    temp = b;
+                    b = b * (2.0 * (i as f64)) / x - a;
+                    a = temp;
+                    i -= 1;
+                }
+            } else {
+                i = nm1;
+                while i > 0 {
+                    temp = b;
+                    b = b * (2.0 * (i as f64)) / x - a;
+                    a = temp;
+                    /* scale b to avoid spurious overflow */
+                    let x1p500 = f64::from_bits(0x5f30000000000000); // 0x1p500 == 2^500
+                    if b > x1p500 {
+                        a /= b;
+                        t /= b;
+                        b = 1.0;
+                    }
+                    i -= 1;
+                }
+            }
+            z = j0(x);
+            w = j1(x);
+            if fabs(z) >= fabs(w) {
+                b = t * z / b;
+            } else {
+                b = t * w / a;
+            }
+        }
+    }
+
+    if sign {
+        -b
+    } else {
+        b
+    }
+}
+
+pub fn yn(n: i32, x: f64) -> f64 {
+    let mut ix: u32;
+    let lx: u32;
+    let mut ib: u32;
+    let nm1: i32;
+    let mut sign: bool;
+    let mut i: i32;
+    let mut a: f64;
+    let mut b: f64;
+    let mut temp: f64;
+
+    ix = get_high_word(x);
+    lx = get_low_word(x);
+    sign = (ix >> 31) != 0;
+    ix &= 0x7fffffff;
+
+    // -lx == !lx + 1
+    if (ix | (lx | ((!lx).wrapping_add(1))) >> 31) > 0x7ff00000 {
+        /* nan */
+        return x;
+    }
+    if sign && (ix | lx) != 0 {
+        /* x < 0 */
+        return 0.0 / 0.0;
+    }
+    if ix == 0x7ff00000 {
+        return 0.0;
+    }
+
+    if n == 0 {
+        return y0(x);
+    }
+    if n < 0 {
+        nm1 = -(n + 1);
+        sign = (n & 1) != 0;
+    } else {
+        nm1 = n - 1;
+        sign = false;
+    }
+    if nm1 == 0 {
+        if sign {
+            return -y1(x);
+        } else {
+            return y1(x);
+        }
+    }
+
+    if ix >= 0x52d00000 {
+        /* x > 2**302 */
+        /* (x >> n**2)
+         *      Jn(x) = cos(x-(2n+1)*pi/4)*sqrt(2/x*pi)
+         *      Yn(x) = sin(x-(2n+1)*pi/4)*sqrt(2/x*pi)
+         *      Let s=sin(x), c=cos(x),
+         *          xn=x-(2n+1)*pi/4, sqt2 = sqrt(2),then
+         *
+         *             n    sin(xn)*sqt2    cos(xn)*sqt2
+         *          ----------------------------------
+         *             0     s-c             c+s
+         *             1    -s-c            -c+s
+         *             2    -s+c            -c-s
+         *             3     s+c             c-s
+         */
+        temp = match nm1 & 3 {
+            0 => -sin(x) - cos(x),
+            1 => -sin(x) + cos(x),
+            2 => sin(x) + cos(x),
+            3 | _ => sin(x) - cos(x),
+        };
+        b = INVSQRTPI * temp / sqrt(x);
+    } else {
+        a = y0(x);
+        b = y1(x);
+        /* quit if b is -inf */
+        ib = get_high_word(b);
+        i = 0;
+        while i < nm1 && ib != 0xfff00000 {
+            i += 1;
+            temp = b;
+            b = (2.0 * (i as f64) / x) * b - a;
+            ib = get_high_word(b);
+            a = temp;
+        }
+    }
+
+    if sign {
+        -b
+    } else {
+        b
+    }
+}
+
+
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+
+/* origin: FreeBSD /usr/src/lib/msun/src/e_jnf.c */
+/*
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+use super::{fabsf, j0f, j1f, logf, y0f, y1f};
+
+pub fn jnf(n: i32, mut x: f32) -> f32 {
+    let mut ix: u32;
+    let mut nm1: i32;
+    let mut sign: bool;
+    let mut i: i32;
+    let mut a: f32;
+    let mut b: f32;
+    let mut temp: f32;
+
+    ix = x.to_bits();
+    sign = (ix >> 31) != 0;
+    ix &= 0x7fffffff;
+    if ix > 0x7f800000 {
+        /* nan */
+        return x;
+    }
+
+    /* J(-n,x) = J(n,-x), use |n|-1 to avoid overflow in -n */
+    if n == 0 {
+        return j0f(x);
+    }
+    if n < 0 {
+        nm1 = -(n + 1);
+        x = -x;
+        sign = !sign;
+    } else {
+        nm1 = n - 1;
+    }
+    if nm1 == 0 {
+        return j1f(x);
+    }
+
+    sign &= (n & 1) != 0; /* even n: 0, odd n: signbit(x) */
+    x = fabsf(x);
+    if ix == 0 || ix == 0x7f800000 {
+        /* if x is 0 or inf */
+        b = 0.0;
+    } else if (nm1 as f32) < x {
+        /* Safe to use J(n+1,x)=2n/x *J(n,x)-J(n-1,x) */
+        a = j0f(x);
+        b = j1f(x);
+        i = 0;
+        while i < nm1 {
+            i += 1;
+            temp = b;
+            b = b * (2.0 * (i as f32) / x) - a;
+            a = temp;
+        }
+    } else {
+        if ix < 0x35800000 {
+            /* x < 2**-20 */
+            /* x is tiny, return the first Taylor expansion of J(n,x)
+             * J(n,x) = 1/n!*(x/2)^n  - ...
+             */
+            if nm1 > 8 {
+                /* underflow */
+                nm1 = 8;
+            }
+            temp = 0.5 * x;
+            b = temp;
+            a = 1.0;
+            i = 2;
+            while i <= nm1 + 1 {
+                a *= i as f32; /* a = n! */
+                b *= temp; /* b = (x/2)^n */
+                i += 1;
+            }
+            b = b / a;
+        } else {
+            /* use backward recurrence */
+            /*                      x      x^2      x^2
+             *  J(n,x)/J(n-1,x) =  ----   ------   ------   .....
+             *                      2n  - 2(n+1) - 2(n+2)
+             *
+             *                      1      1        1
+             *  (for large x)   =  ----  ------   ------   .....
+             *                      2n   2(n+1)   2(n+2)
+             *                      -- - ------ - ------ -
+             *                       x     x         x
+             *
+             * Let w = 2n/x and h=2/x, then the above quotient
+             * is equal to the continued fraction:
+             *                  1
+             *      = -----------------------
+             *                     1
+             *         w - -----------------
+             *                        1
+             *              w+h - ---------
+             *                     w+2h - ...
+             *
+             * To determine how many terms needed, let
+             * Q(0) = w, Q(1) = w(w+h) - 1,
+             * Q(k) = (w+k*h)*Q(k-1) - Q(k-2),
+             * When Q(k) > 1e4      good for single
+             * When Q(k) > 1e9      good for double
+             * When Q(k) > 1e17     good for quadruple
+             */
+            /* determine k */
+            let mut t: f32;
+            let mut q0: f32;
+            let mut q1: f32;
+            let mut w: f32;
+            let h: f32;
+            let mut z: f32;
+            let mut tmp: f32;
+            let nf: f32;
+            let mut k: i32;
+
+            nf = (nm1 as f32) + 1.0;
+            w = 2.0 * (nf as f32) / x;
+            h = 2.0 / x;
+            z = w + h;
+            q0 = w;
+            q1 = w * z - 1.0;
+            k = 1;
+            while q1 < 1.0e4 {
+                k += 1;
+                z += h;
+                tmp = z * q1 - q0;
+                q0 = q1;
+                q1 = tmp;
+            }
+            t = 0.0;
+            i = k;
+            while i >= 0 {
+                t = 1.0 / (2.0 * ((i as f32) + nf) / x - t);
+                i -= 1;
+            }
+            a = t;
+            b = 1.0;
+            /*  estimate log((2/x)^n*n!) = n*log(2/x)+n*ln(n)
+             *  Hence, if n*(log(2n/x)) > ...
+             *  single 8.8722839355e+01
+             *  double 7.09782712893383973096e+02
+             *  long double 1.1356523406294143949491931077970765006170e+04
+             *  then recurrent value may overflow and the result is
+             *  likely underflow to zero
+             */
+            tmp = nf * logf(fabsf(w));
+            if tmp < 88.721679688 {
+                i = nm1;
+                while i > 0 {
+                    temp = b;
+                    b = 2.0 * (i as f32) * b / x - a;
+                    a = temp;
+                    i -= 1;
+                }
+            } else {
+                i = nm1;
+                while i > 0 {
+                    temp = b;
+                    b = 2.0 * (i as f32) * b / x - a;
+                    a = temp;
+                    /* scale b to avoid spurious overflow */
+                    let x1p60 = f32::from_bits(0x5d800000); // 0x1p60 == 2^60
+                    if b > x1p60 {
+                        a /= b;
+                        t /= b;
+                        b = 1.0;
+                    }
+                    i -= 1;
+                }
+            }
+            z = j0f(x);
+            w = j1f(x);
+            if fabsf(z) >= fabsf(w) {
+                b = t * z / b;
+            } else {
+                b = t * w / a;
+            }
+        }
+    }
+
+    if sign {
+        -b
+    } else {
+        b
+    }
+}
+
+pub fn ynf(n: i32, x: f32) -> f32 {
+    let mut ix: u32;
+    let mut ib: u32;
+    let nm1: i32;
+    let mut sign: bool;
+    let mut i: i32;
+    let mut a: f32;
+    let mut b: f32;
+    let mut temp: f32;
+
+    ix = x.to_bits();
+    sign = (ix >> 31) != 0;
+    ix &= 0x7fffffff;
+    if ix > 0x7f800000 {
+        /* nan */
+        return x;
+    }
+    if sign && ix != 0 {
+        /* x < 0 */
+        return 0.0 / 0.0;
+    }
+    if ix == 0x7f800000 {
+        return 0.0;
+    }
+
+    if n == 0 {
+        return y0f(x);
+    }
+    if n < 0 {
+        nm1 = -(n + 1);
+        sign = (n & 1) != 0;
+    } else {
+        nm1 = n - 1;
+        sign = false;
+    }
+    if nm1 == 0 {
+        if sign {
+            return -y1f(x);
+        } else {
+            return y1f(x);
+        }
+    }
+
+    a = y0f(x);
+    b = y1f(x);
+    /* quit if b is -inf */
+    ib = b.to_bits();
+    i = 0;
+    while i < nm1 && ib != 0xff800000 {
+        i += 1;
+        temp = b;
+        b = (2.0 * (i as f32) / x) * b - a;
+        ib = b.to_bits();
+        a = temp;
+    }
+
+    if sign {
+        -b
+    } else {
+        b
+    }
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/k_cos.rs.html b/src/libm/math/k_cos.rs.html new file mode 100644 index 000000000..adac7eed1 --- /dev/null +++ b/src/libm/math/k_cos.rs.html @@ -0,0 +1,129 @@ +k_cos.rs.html -- source
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+// origin: FreeBSD /usr/src/lib/msun/src/k_cos.c
+//
+// ====================================================
+// Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+//
+// Developed at SunSoft, a Sun Microsystems, Inc. business.
+// Permission to use, copy, modify, and distribute this
+// software is freely granted, provided that this notice
+// is preserved.
+// ====================================================
+
+const C1: f64 = 4.16666666666666019037e-02; /* 0x3FA55555, 0x5555554C */
+const C2: f64 = -1.38888888888741095749e-03; /* 0xBF56C16C, 0x16C15177 */
+const C3: f64 = 2.48015872894767294178e-05; /* 0x3EFA01A0, 0x19CB1590 */
+const C4: f64 = -2.75573143513906633035e-07; /* 0xBE927E4F, 0x809C52AD */
+const C5: f64 = 2.08757232129817482790e-09; /* 0x3E21EE9E, 0xBDB4B1C4 */
+const C6: f64 = -1.13596475577881948265e-11; /* 0xBDA8FAE9, 0xBE8838D4 */
+
+// kernel cos function on [-pi/4, pi/4], pi/4 ~ 0.785398164
+// Input x is assumed to be bounded by ~pi/4 in magnitude.
+// Input y is the tail of x.
+//
+// Algorithm
+//      1. Since cos(-x) = cos(x), we need only to consider positive x.
+//      2. if x < 2^-27 (hx<0x3e400000 0), return 1 with inexact if x!=0.
+//      3. cos(x) is approximated by a polynomial of degree 14 on
+//         [0,pi/4]
+//                                       4            14
+//              cos(x) ~ 1 - x*x/2 + C1*x + ... + C6*x
+//         where the remez error is
+//
+//      |              2     4     6     8     10    12     14 |     -58
+//      |cos(x)-(1-.5*x +C1*x +C2*x +C3*x +C4*x +C5*x  +C6*x  )| <= 2
+//      |                                                      |
+//
+//                     4     6     8     10    12     14
+//      4. let r = C1*x +C2*x +C3*x +C4*x +C5*x  +C6*x  , then
+//             cos(x) ~ 1 - x*x/2 + r
+//         since cos(x+y) ~ cos(x) - sin(x)*y
+//                        ~ cos(x) - x*y,
+//         a correction term is necessary in cos(x) and hence
+//              cos(x+y) = 1 - (x*x/2 - (r - x*y))
+//         For better accuracy, rearrange to
+//              cos(x+y) ~ w + (tmp + (r-x*y))
+//         where w = 1 - x*x/2 and tmp is a tiny correction term
+//         (1 - x*x/2 == w + tmp exactly in infinite precision).
+//         The exactness of w + tmp in infinite precision depends on w
+//         and tmp having the same precision as x.  If they have extra
+//         precision due to compiler bugs, then the extra precision is
+//         only good provided it is retained in all terms of the final
+//         expression for cos().  Retention happens in all cases tested
+//         under FreeBSD, so don't pessimize things by forcibly clipping
+//         any extra precision in w.
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub(crate) fn k_cos(x: f64, y: f64) -> f64 {
+    let z = x * x;
+    let w = z * z;
+    let r = z * (C1 + z * (C2 + z * C3)) + w * w * (C4 + z * (C5 + z * C6));
+    let hz = 0.5 * z;
+    let w = 1.0 - hz;
+    w + (((1.0 - w) - hz) + (z * r - x * y))
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/k_cosf.rs.html b/src/libm/math/k_cosf.rs.html new file mode 100644 index 000000000..252aceca3 --- /dev/null +++ b/src/libm/math/k_cosf.rs.html @@ -0,0 +1,63 @@ +k_cosf.rs.html -- source
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+
+/* origin: FreeBSD /usr/src/lib/msun/src/k_cosf.c */
+/*
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ * Debugged and optimized by Bruce D. Evans.
+ */
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+/* |cos(x) - c(x)| < 2**-34.1 (~[-5.37e-11, 5.295e-11]). */
+const C0: f64 = -0.499999997251031003120; /* -0x1ffffffd0c5e81.0p-54 */
+const C1: f64 = 0.0416666233237390631894; /*  0x155553e1053a42.0p-57 */
+const C2: f64 = -0.00138867637746099294692; /* -0x16c087e80f1e27.0p-62 */
+const C3: f64 = 0.0000243904487962774090654; /*  0x199342e0ee5069.0p-68 */
+
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub(crate) fn k_cosf(x: f64) -> f32 {
+    let z = x * x;
+    let w = z * z;
+    let r = C2 + z * C3;
+    (((1.0 + z * C0) + w * C1) + (w * z) * r) as f32
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/k_expo2.rs.html b/src/libm/math/k_expo2.rs.html new file mode 100644 index 000000000..f69182657 --- /dev/null +++ b/src/libm/math/k_expo2.rs.html @@ -0,0 +1,33 @@ +k_expo2.rs.html -- source
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+use super::exp;
+
+/* k is such that k*ln2 has minimal relative error and x - kln2 > log(FLT_MIN) */
+const K: i32 = 2043;
+
+/* expf(x)/2 for x >= log(FLT_MAX), slightly better than 0.5f*expf(x/2)*expf(x/2) */
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub(crate) fn k_expo2(x: f64) -> f64 {
+    let k_ln2 = f64::from_bits(0x40962066151add8b);
+    /* note that k is odd and scale*scale overflows */
+    let scale = f64::from_bits(((((0x3ff + K / 2) as u32) << 20) as u64) << 32);
+    /* exp(x - k ln2) * 2**(k-1) */
+    exp(x - k_ln2) * scale * scale
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/k_expo2f.rs.html b/src/libm/math/k_expo2f.rs.html new file mode 100644 index 000000000..e222fd26e --- /dev/null +++ b/src/libm/math/k_expo2f.rs.html @@ -0,0 +1,33 @@ +k_expo2f.rs.html -- source
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+use super::expf;
+
+/* k is such that k*ln2 has minimal relative error and x - kln2 > log(FLT_MIN) */
+const K: i32 = 235;
+
+/* expf(x)/2 for x >= log(FLT_MAX), slightly better than 0.5f*expf(x/2)*expf(x/2) */
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub(crate) fn k_expo2f(x: f32) -> f32 {
+    let k_ln2 = f32::from_bits(0x4322e3bc);
+    /* note that k is odd and scale*scale overflows */
+    let scale = f32::from_bits(((0x7f + K / 2) as u32) << 23);
+    /* exp(x - k ln2) * 2**(k-1) */
+    expf(x - k_ln2) * scale * scale
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/k_sin.rs.html b/src/libm/math/k_sin.rs.html new file mode 100644 index 000000000..d9b3b5337 --- /dev/null +++ b/src/libm/math/k_sin.rs.html @@ -0,0 +1,119 @@ +k_sin.rs.html -- source
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+
+// origin: FreeBSD /usr/src/lib/msun/src/k_sin.c
+//
+// ====================================================
+// Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+//
+// Developed at SunSoft, a Sun Microsystems, Inc. business.
+// Permission to use, copy, modify, and distribute this
+// software is freely granted, provided that this notice
+// is preserved.
+// ====================================================
+
+const S1: f64 = -1.66666666666666324348e-01; /* 0xBFC55555, 0x55555549 */
+const S2: f64 = 8.33333333332248946124e-03; /* 0x3F811111, 0x1110F8A6 */
+const S3: f64 = -1.98412698298579493134e-04; /* 0xBF2A01A0, 0x19C161D5 */
+const S4: f64 = 2.75573137070700676789e-06; /* 0x3EC71DE3, 0x57B1FE7D */
+const S5: f64 = -2.50507602534068634195e-08; /* 0xBE5AE5E6, 0x8A2B9CEB */
+const S6: f64 = 1.58969099521155010221e-10; /* 0x3DE5D93A, 0x5ACFD57C */
+
+// kernel sin function on ~[-pi/4, pi/4] (except on -0), pi/4 ~ 0.7854
+// Input x is assumed to be bounded by ~pi/4 in magnitude.
+// Input y is the tail of x.
+// Input iy indicates whether y is 0. (if iy=0, y assume to be 0).
+//
+// Algorithm
+//      1. Since sin(-x) = -sin(x), we need only to consider positive x.
+//      2. Callers must return sin(-0) = -0 without calling here since our
+//         odd polynomial is not evaluated in a way that preserves -0.
+//         Callers may do the optimization sin(x) ~ x for tiny x.
+//      3. sin(x) is approximated by a polynomial of degree 13 on
+//         [0,pi/4]
+//                               3            13
+//              sin(x) ~ x + S1*x + ... + S6*x
+//         where
+//
+//      |sin(x)         2     4     6     8     10     12  |     -58
+//      |----- - (1+S1*x +S2*x +S3*x +S4*x +S5*x  +S6*x   )| <= 2
+//      |  x                                               |
+//
+//      4. sin(x+y) = sin(x) + sin'(x')*y
+//                  ~ sin(x) + (1-x*x/2)*y
+//         For better accuracy, let
+//                   3      2      2      2      2
+//              r = x *(S2+x *(S3+x *(S4+x *(S5+x *S6))))
+//         then                   3    2
+//              sin(x) = x + (S1*x + (x *(r-y/2)+y))
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub(crate) fn k_sin(x: f64, y: f64, iy: i32) -> f64 {
+    let z = x * x;
+    let w = z * z;
+    let r = S2 + z * (S3 + z * S4) + z * w * (S5 + z * S6);
+    let v = z * x;
+    if iy == 0 {
+        x + v * (S1 + z * r)
+    } else {
+        x - ((z * (0.5 * y - v * r) - y) - v * S1)
+    }
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/k_sinf.rs.html b/src/libm/math/k_sinf.rs.html new file mode 100644 index 000000000..5968e3c8b --- /dev/null +++ b/src/libm/math/k_sinf.rs.html @@ -0,0 +1,65 @@ +k_sinf.rs.html -- source
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+
+/* origin: FreeBSD /usr/src/lib/msun/src/k_sinf.c */
+/*
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ * Optimized by Bruce D. Evans.
+ */
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+/* |sin(x)/x - s(x)| < 2**-37.5 (~[-4.89e-12, 4.824e-12]). */
+const S1: f64 = -0.166666666416265235595; /* -0x15555554cbac77.0p-55 */
+const S2: f64 = 0.0083333293858894631756; /*  0x111110896efbb2.0p-59 */
+const S3: f64 = -0.000198393348360966317347; /* -0x1a00f9e2cae774.0p-65 */
+const S4: f64 = 0.0000027183114939898219064; /*  0x16cd878c3b46a7.0p-71 */
+
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub(crate) fn k_sinf(x: f64) -> f32 {
+    let z = x * x;
+    let w = z * z;
+    let r = S3 + z * S4;
+    let s = z * x;
+    ((x + s * (S1 + z * S2)) + s * w * r) as f32
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/k_tan.rs.html b/src/libm/math/k_tan.rs.html new file mode 100644 index 000000000..e5f639bd1 --- /dev/null +++ b/src/libm/math/k_tan.rs.html @@ -0,0 +1,217 @@ +k_tan.rs.html -- source
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+
+// origin: FreeBSD /usr/src/lib/msun/src/k_tan.c */
+//
+// ====================================================
+// Copyright 2004 Sun Microsystems, Inc.  All Rights Reserved.
+//
+// Permission to use, copy, modify, and distribute this
+// software is freely granted, provided that this notice
+// is preserved.
+// ====================================================
+
+// kernel tan function on ~[-pi/4, pi/4] (except on -0), pi/4 ~ 0.7854
+// Input x is assumed to be bounded by ~pi/4 in magnitude.
+// Input y is the tail of x.
+// Input odd indicates whether tan (if odd = 0) or -1/tan (if odd = 1) is returned.
+//
+// Algorithm
+//      1. Since tan(-x) = -tan(x), we need only to consider positive x.
+//      2. Callers must return tan(-0) = -0 without calling here since our
+//         odd polynomial is not evaluated in a way that preserves -0.
+//         Callers may do the optimization tan(x) ~ x for tiny x.
+//      3. tan(x) is approximated by a odd polynomial of degree 27 on
+//         [0,0.67434]
+//                               3             27
+//              tan(x) ~ x + T1*x + ... + T13*x
+//         where
+//
+//              |tan(x)         2     4            26   |     -59.2
+//              |----- - (1+T1*x +T2*x +.... +T13*x    )| <= 2
+//              |  x                                    |
+//
+//         Note: tan(x+y) = tan(x) + tan'(x)*y
+//                        ~ tan(x) + (1+x*x)*y
+//         Therefore, for better accuracy in computing tan(x+y), let
+//                   3      2      2       2       2
+//              r = x *(T2+x *(T3+x *(...+x *(T12+x *T13))))
+//         then
+//                                  3    2
+//              tan(x+y) = x + (T1*x + (x *(r+y)+y))
+//
+//      4. For x in [0.67434,pi/4],  let y = pi/4 - x, then
+//              tan(x) = tan(pi/4-y) = (1-tan(y))/(1+tan(y))
+//                     = 1 - 2*(tan(y) - (tan(y)^2)/(1+tan(y)))
+static T: [f64; 13] = [
+    3.33333333333334091986e-01,  /* 3FD55555, 55555563 */
+    1.33333333333201242699e-01,  /* 3FC11111, 1110FE7A */
+    5.39682539762260521377e-02,  /* 3FABA1BA, 1BB341FE */
+    2.18694882948595424599e-02,  /* 3F9664F4, 8406D637 */
+    8.86323982359930005737e-03,  /* 3F8226E3, E96E8493 */
+    3.59207910759131235356e-03,  /* 3F6D6D22, C9560328 */
+    1.45620945432529025516e-03,  /* 3F57DBC8, FEE08315 */
+    5.88041240820264096874e-04,  /* 3F4344D8, F2F26501 */
+    2.46463134818469906812e-04,  /* 3F3026F7, 1A8D1068 */
+    7.81794442939557092300e-05,  /* 3F147E88, A03792A6 */
+    7.14072491382608190305e-05,  /* 3F12B80F, 32F0A7E9 */
+    -1.85586374855275456654e-05, /* BEF375CB, DB605373 */
+    2.59073051863633712884e-05,  /* 3EFB2A70, 74BF7AD4 */
+];
+const PIO4: f64 = 7.85398163397448278999e-01; /* 3FE921FB, 54442D18 */
+const PIO4_LO: f64 = 3.06161699786838301793e-17; /* 3C81A626, 33145C07 */
+
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub(crate) fn k_tan(mut x: f64, mut y: f64, odd: i32) -> f64 {
+    let hx = (f64::to_bits(x) >> 32) as u32;
+    let big = (hx & 0x7fffffff) >= 0x3FE59428; /* |x| >= 0.6744 */
+    if big {
+        let sign = hx >> 31;
+        if sign != 0 {
+            x = -x;
+            y = -y;
+        }
+        x = (PIO4 - x) + (PIO4_LO - y);
+        y = 0.0;
+    }
+    let z = x * x;
+    let w = z * z;
+    /*
+     * Break x^5*(T[1]+x^2*T[2]+...) into
+     * x^5(T[1]+x^4*T[3]+...+x^20*T[11]) +
+     * x^5(x^2*(T[2]+x^4*T[4]+...+x^22*[T12]))
+     */
+    let r = T[1] + w * (T[3] + w * (T[5] + w * (T[7] + w * (T[9] + w * T[11]))));
+    let v = z * (T[2] + w * (T[4] + w * (T[6] + w * (T[8] + w * (T[10] + w * T[12])))));
+    let s = z * x;
+    let r = y + z * (s * (r + v) + y) + s * T[0];
+    let w = x + r;
+    if big {
+        let sign = hx >> 31;
+        let s = 1.0 - 2.0 * odd as f64;
+        let v = s - 2.0 * (x + (r - w * w / (w + s)));
+        return if sign != 0 { -v } else { v };
+    }
+    if odd == 0 {
+        return w;
+    }
+    /* -1.0/(x+r) has up to 2ulp error, so compute it accurately */
+    let w0 = zero_low_word(w);
+    let v = r - (w0 - x); /* w0+v = r+x */
+    let a = -1.0 / w;
+    let a0 = zero_low_word(a);
+    a0 + a * (1.0 + a0 * w0 + a0 * v)
+}
+
+#[inline]
+fn zero_low_word(x: f64) -> f64 {
+    f64::from_bits(f64::to_bits(x) & 0xFFFF_FFFF_0000_0000)
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/k_tanf.rs.html b/src/libm/math/k_tanf.rs.html new file mode 100644 index 000000000..cda78bc7d --- /dev/null +++ b/src/libm/math/k_tanf.rs.html @@ -0,0 +1,97 @@ +k_tanf.rs.html -- source
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+/* origin: FreeBSD /usr/src/lib/msun/src/k_tan.c */
+/*
+ * ====================================================
+ * Copyright 2004 Sun Microsystems, Inc.  All Rights Reserved.
+ *
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+/* |tan(x)/x - t(x)| < 2**-25.5 (~[-2e-08, 2e-08]). */
+const T: [f64; 6] = [
+    0.333331395030791399758,   /* 0x15554d3418c99f.0p-54 */
+    0.133392002712976742718,   /* 0x1112fd38999f72.0p-55 */
+    0.0533812378445670393523,  /* 0x1b54c91d865afe.0p-57 */
+    0.0245283181166547278873,  /* 0x191df3908c33ce.0p-58 */
+    0.00297435743359967304927, /* 0x185dadfcecf44e.0p-61 */
+    0.00946564784943673166728, /* 0x1362b9bf971bcd.0p-59 */
+];
+
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub(crate) fn k_tanf(x: f64, odd: bool) -> f32 {
+    let z = x * x;
+    /*
+     * Split up the polynomial into small independent terms to give
+     * opportunities for parallel evaluation.  The chosen splitting is
+     * micro-optimized for Athlons (XP, X64).  It costs 2 multiplications
+     * relative to Horner's method on sequential machines.
+     *
+     * We add the small terms from lowest degree up for efficiency on
+     * non-sequential machines (the lowest degree terms tend to be ready
+     * earlier).  Apart from this, we don't care about order of
+     * operations, and don't need to to care since we have precision to
+     * spare.  However, the chosen splitting is good for accuracy too,
+     * and would give results as accurate as Horner's method if the
+     * small terms were added from highest degree down.
+     */
+    let mut r = T[4] + z * T[5];
+    let t = T[2] + z * T[3];
+    let w = z * z;
+    let s = z * x;
+    let u = T[0] + z * T[1];
+    r = (x + s * u) + (s * w) * (t + w * r);
+    (if odd { -1. / r } else { r }) as f32
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/ldexp.rs.html b/src/libm/math/ldexp.rs.html new file mode 100644 index 000000000..2cf34024a --- /dev/null +++ b/src/libm/math/ldexp.rs.html @@ -0,0 +1,13 @@ +ldexp.rs.html -- source
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+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn ldexp(x: f64, n: i32) -> f64 {
+    super::scalbn(x, n)
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/ldexpf.rs.html b/src/libm/math/ldexpf.rs.html new file mode 100644 index 000000000..084ae1c95 --- /dev/null +++ b/src/libm/math/ldexpf.rs.html @@ -0,0 +1,13 @@ +ldexpf.rs.html -- source
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+
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn ldexpf(x: f32, n: i32) -> f32 {
+    super::scalbnf(x, n)
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/lgamma.rs.html b/src/libm/math/lgamma.rs.html new file mode 100644 index 000000000..5e399274b --- /dev/null +++ b/src/libm/math/lgamma.rs.html @@ -0,0 +1,13 @@ +lgamma.rs.html -- source
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+use super::lgamma_r;
+
+pub fn lgamma(x: f64) -> f64 {
+    lgamma_r(x).0
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/lgamma_r.rs.html b/src/libm/math/lgamma_r.rs.html new file mode 100644 index 000000000..7b251bd07 --- /dev/null +++ b/src/libm/math/lgamma_r.rs.html @@ -0,0 +1,641 @@ +lgamma_r.rs.html -- source
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+
+/* origin: FreeBSD /usr/src/lib/msun/src/e_lgamma_r.c */
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunSoft, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ *
+ */
+/* lgamma_r(x, signgamp)
+ * Reentrant version of the logarithm of the Gamma function
+ * with user provide pointer for the sign of Gamma(x).
+ *
+ * Method:
+ *   1. Argument Reduction for 0 < x <= 8
+ *      Since gamma(1+s)=s*gamma(s), for x in [0,8], we may
+ *      reduce x to a number in [1.5,2.5] by
+ *              lgamma(1+s) = log(s) + lgamma(s)
+ *      for example,
+ *              lgamma(7.3) = log(6.3) + lgamma(6.3)
+ *                          = log(6.3*5.3) + lgamma(5.3)
+ *                          = log(6.3*5.3*4.3*3.3*2.3) + lgamma(2.3)
+ *   2. Polynomial approximation of lgamma around its
+ *      minimun ymin=1.461632144968362245 to maintain monotonicity.
+ *      On [ymin-0.23, ymin+0.27] (i.e., [1.23164,1.73163]), use
+ *              Let z = x-ymin;
+ *              lgamma(x) = -1.214862905358496078218 + z^2*poly(z)
+ *      where
+ *              poly(z) is a 14 degree polynomial.
+ *   2. Rational approximation in the primary interval [2,3]
+ *      We use the following approximation:
+ *              s = x-2.0;
+ *              lgamma(x) = 0.5*s + s*P(s)/Q(s)
+ *      with accuracy
+ *              |P/Q - (lgamma(x)-0.5s)| < 2**-61.71
+ *      Our algorithms are based on the following observation
+ *
+ *                             zeta(2)-1    2    zeta(3)-1    3
+ * lgamma(2+s) = s*(1-Euler) + --------- * s  -  --------- * s  + ...
+ *                                 2                 3
+ *
+ *      where Euler = 0.5771... is the Euler constant, which is very
+ *      close to 0.5.
+ *
+ *   3. For x>=8, we have
+ *      lgamma(x)~(x-0.5)log(x)-x+0.5*log(2pi)+1/(12x)-1/(360x**3)+....
+ *      (better formula:
+ *         lgamma(x)~(x-0.5)*(log(x)-1)-.5*(log(2pi)-1) + ...)
+ *      Let z = 1/x, then we approximation
+ *              f(z) = lgamma(x) - (x-0.5)(log(x)-1)
+ *      by
+ *                                  3       5             11
+ *              w = w0 + w1*z + w2*z  + w3*z  + ... + w6*z
+ *      where
+ *              |w - f(z)| < 2**-58.74
+ *
+ *   4. For negative x, since (G is gamma function)
+ *              -x*G(-x)*G(x) = PI/sin(PI*x),
+ *      we have
+ *              G(x) = PI/(sin(PI*x)*(-x)*G(-x))
+ *      since G(-x) is positive, sign(G(x)) = sign(sin(PI*x)) for x<0
+ *      Hence, for x<0, signgam = sign(sin(PI*x)) and
+ *              lgamma(x) = log(|Gamma(x)|)
+ *                        = log(PI/(|x*sin(PI*x)|)) - lgamma(-x);
+ *      Note: one should avoid compute PI*(-x) directly in the
+ *            computation of sin(PI*(-x)).
+ *
+ *   5. Special Cases
+ *              lgamma(2+s) ~ s*(1-Euler) for tiny s
+ *              lgamma(1) = lgamma(2) = 0
+ *              lgamma(x) ~ -log(|x|) for tiny x
+ *              lgamma(0) = lgamma(neg.integer) = inf and raise divide-by-zero
+ *              lgamma(inf) = inf
+ *              lgamma(-inf) = inf (bug for bug compatible with C99!?)
+ *
+ */
+
+use super::{floor, k_cos, k_sin, log};
+
+const PI: f64 = 3.14159265358979311600e+00; /* 0x400921FB, 0x54442D18 */
+const A0: f64 = 7.72156649015328655494e-02; /* 0x3FB3C467, 0xE37DB0C8 */
+const A1: f64 = 3.22467033424113591611e-01; /* 0x3FD4A34C, 0xC4A60FAD */
+const A2: f64 = 6.73523010531292681824e-02; /* 0x3FB13E00, 0x1A5562A7 */
+const A3: f64 = 2.05808084325167332806e-02; /* 0x3F951322, 0xAC92547B */
+const A4: f64 = 7.38555086081402883957e-03; /* 0x3F7E404F, 0xB68FEFE8 */
+const A5: f64 = 2.89051383673415629091e-03; /* 0x3F67ADD8, 0xCCB7926B */
+const A6: f64 = 1.19270763183362067845e-03; /* 0x3F538A94, 0x116F3F5D */
+const A7: f64 = 5.10069792153511336608e-04; /* 0x3F40B6C6, 0x89B99C00 */
+const A8: f64 = 2.20862790713908385557e-04; /* 0x3F2CF2EC, 0xED10E54D */
+const A9: f64 = 1.08011567247583939954e-04; /* 0x3F1C5088, 0x987DFB07 */
+const A10: f64 = 2.52144565451257326939e-05; /* 0x3EFA7074, 0x428CFA52 */
+const A11: f64 = 4.48640949618915160150e-05; /* 0x3F07858E, 0x90A45837 */
+const TC: f64 = 1.46163214496836224576e+00; /* 0x3FF762D8, 0x6356BE3F */
+const TF: f64 = -1.21486290535849611461e-01; /* 0xBFBF19B9, 0xBCC38A42 */
+/* tt = -(tail of TF) */
+const TT: f64 = -3.63867699703950536541e-18; /* 0xBC50C7CA, 0xA48A971F */
+const T0: f64 = 4.83836122723810047042e-01; /* 0x3FDEF72B, 0xC8EE38A2 */
+const T1: f64 = -1.47587722994593911752e-01; /* 0xBFC2E427, 0x8DC6C509 */
+const T2: f64 = 6.46249402391333854778e-02; /* 0x3FB08B42, 0x94D5419B */
+const T3: f64 = -3.27885410759859649565e-02; /* 0xBFA0C9A8, 0xDF35B713 */
+const T4: f64 = 1.79706750811820387126e-02; /* 0x3F9266E7, 0x970AF9EC */
+const T5: f64 = -1.03142241298341437450e-02; /* 0xBF851F9F, 0xBA91EC6A */
+const T6: f64 = 6.10053870246291332635e-03; /* 0x3F78FCE0, 0xE370E344 */
+const T7: f64 = -3.68452016781138256760e-03; /* 0xBF6E2EFF, 0xB3E914D7 */
+const T8: f64 = 2.25964780900612472250e-03; /* 0x3F6282D3, 0x2E15C915 */
+const T9: f64 = -1.40346469989232843813e-03; /* 0xBF56FE8E, 0xBF2D1AF1 */
+const T10: f64 = 8.81081882437654011382e-04; /* 0x3F4CDF0C, 0xEF61A8E9 */
+const T11: f64 = -5.38595305356740546715e-04; /* 0xBF41A610, 0x9C73E0EC */
+const T12: f64 = 3.15632070903625950361e-04; /* 0x3F34AF6D, 0x6C0EBBF7 */
+const T13: f64 = -3.12754168375120860518e-04; /* 0xBF347F24, 0xECC38C38 */
+const T14: f64 = 3.35529192635519073543e-04; /* 0x3F35FD3E, 0xE8C2D3F4 */
+const U0: f64 = -7.72156649015328655494e-02; /* 0xBFB3C467, 0xE37DB0C8 */
+const U1: f64 = 6.32827064025093366517e-01; /* 0x3FE4401E, 0x8B005DFF */
+const U2: f64 = 1.45492250137234768737e+00; /* 0x3FF7475C, 0xD119BD6F */
+const U3: f64 = 9.77717527963372745603e-01; /* 0x3FEF4976, 0x44EA8450 */
+const U4: f64 = 2.28963728064692451092e-01; /* 0x3FCD4EAE, 0xF6010924 */
+const U5: f64 = 1.33810918536787660377e-02; /* 0x3F8B678B, 0xBF2BAB09 */
+const V1: f64 = 2.45597793713041134822e+00; /* 0x4003A5D7, 0xC2BD619C */
+const V2: f64 = 2.12848976379893395361e+00; /* 0x40010725, 0xA42B18F5 */
+const V3: f64 = 7.69285150456672783825e-01; /* 0x3FE89DFB, 0xE45050AF */
+const V4: f64 = 1.04222645593369134254e-01; /* 0x3FBAAE55, 0xD6537C88 */
+const V5: f64 = 3.21709242282423911810e-03; /* 0x3F6A5ABB, 0x57D0CF61 */
+const S0: f64 = -7.72156649015328655494e-02; /* 0xBFB3C467, 0xE37DB0C8 */
+const S1: f64 = 2.14982415960608852501e-01; /* 0x3FCB848B, 0x36E20878 */
+const S2: f64 = 3.25778796408930981787e-01; /* 0x3FD4D98F, 0x4F139F59 */
+const S3: f64 = 1.46350472652464452805e-01; /* 0x3FC2BB9C, 0xBEE5F2F7 */
+const S4: f64 = 2.66422703033638609560e-02; /* 0x3F9B481C, 0x7E939961 */
+const S5: f64 = 1.84028451407337715652e-03; /* 0x3F5E26B6, 0x7368F239 */
+const S6: f64 = 3.19475326584100867617e-05; /* 0x3F00BFEC, 0xDD17E945 */
+const R1: f64 = 1.39200533467621045958e+00; /* 0x3FF645A7, 0x62C4AB74 */
+const R2: f64 = 7.21935547567138069525e-01; /* 0x3FE71A18, 0x93D3DCDC */
+const R3: f64 = 1.71933865632803078993e-01; /* 0x3FC601ED, 0xCCFBDF27 */
+const R4: f64 = 1.86459191715652901344e-02; /* 0x3F9317EA, 0x742ED475 */
+const R5: f64 = 7.77942496381893596434e-04; /* 0x3F497DDA, 0xCA41A95B */
+const R6: f64 = 7.32668430744625636189e-06; /* 0x3EDEBAF7, 0xA5B38140 */
+const W0: f64 = 4.18938533204672725052e-01; /* 0x3FDACFE3, 0x90C97D69 */
+const W1: f64 = 8.33333333333329678849e-02; /* 0x3FB55555, 0x5555553B */
+const W2: f64 = -2.77777777728775536470e-03; /* 0xBF66C16C, 0x16B02E5C */
+const W3: f64 = 7.93650558643019558500e-04; /* 0x3F4A019F, 0x98CF38B6 */
+const W4: f64 = -5.95187557450339963135e-04; /* 0xBF4380CB, 0x8C0FE741 */
+const W5: f64 = 8.36339918996282139126e-04; /* 0x3F4B67BA, 0x4CDAD5D1 */
+const W6: f64 = -1.63092934096575273989e-03; /* 0xBF5AB89D, 0x0B9E43E4 */
+
+/* sin(PI*x) assuming x > 2^-100, if sin(PI*x)==0 the sign is arbitrary */
+fn sin_pi(mut x: f64) -> f64 {
+    let mut n: i32;
+
+    /* spurious inexact if odd int */
+    x = 2.0 * (x * 0.5 - floor(x * 0.5)); /* x mod 2.0 */
+
+    n = (x * 4.0) as i32;
+    n = (n + 1) / 2;
+    x -= (n as f64) * 0.5;
+    x *= PI;
+
+    match n {
+        1 => k_cos(x, 0.0),
+        2 => k_sin(-x, 0.0, 0),
+        3 => -k_cos(x, 0.0),
+        0 | _ => k_sin(x, 0.0, 0),
+    }
+}
+
+pub fn lgamma_r(mut x: f64) -> (f64, i32) {
+    let u: u64 = x.to_bits();
+    let mut t: f64;
+    let y: f64;
+    let mut z: f64;
+    let nadj: f64;
+    let p: f64;
+    let p1: f64;
+    let p2: f64;
+    let p3: f64;
+    let q: f64;
+    let mut r: f64;
+    let w: f64;
+    let ix: u32;
+    let sign: bool;
+    let i: i32;
+    let mut signgam: i32;
+
+    /* purge off +-inf, NaN, +-0, tiny and negative arguments */
+    signgam = 1;
+    sign = (u >> 63) != 0;
+    ix = ((u >> 32) as u32) & 0x7fffffff;
+    if ix >= 0x7ff00000 {
+        return (x * x, signgam);
+    }
+    if ix < (0x3ff - 70) << 20 {
+        /* |x|<2**-70, return -log(|x|) */
+        if sign {
+            x = -x;
+            signgam = -1;
+        }
+        return (-log(x), signgam);
+    }
+    if sign {
+        x = -x;
+        t = sin_pi(x);
+        if t == 0.0 {
+            /* -integer */
+            return (1.0 / (x - x), signgam);
+        }
+        if t > 0.0 {
+            signgam = -1;
+        } else {
+            t = -t;
+        }
+        nadj = log(PI / (t * x));
+    } else {
+        nadj = 0.0;
+    }
+
+    /* purge off 1 and 2 */
+    if (ix == 0x3ff00000 || ix == 0x40000000) && (u & 0xffffffff) == 0 {
+        r = 0.0;
+    }
+    /* for x < 2.0 */
+    else if ix < 0x40000000 {
+        if ix <= 0x3feccccc {
+            /* lgamma(x) = lgamma(x+1)-log(x) */
+            r = -log(x);
+            if ix >= 0x3FE76944 {
+                y = 1.0 - x;
+                i = 0;
+            } else if ix >= 0x3FCDA661 {
+                y = x - (TC - 1.0);
+                i = 1;
+            } else {
+                y = x;
+                i = 2;
+            }
+        } else {
+            r = 0.0;
+            if ix >= 0x3FFBB4C3 {
+                /* [1.7316,2] */
+                y = 2.0 - x;
+                i = 0;
+            } else if ix >= 0x3FF3B4C4 {
+                /* [1.23,1.73] */
+                y = x - TC;
+                i = 1;
+            } else {
+                y = x - 1.0;
+                i = 2;
+            }
+        }
+        match i {
+            0 => {
+                z = y * y;
+                p1 = A0 + z * (A2 + z * (A4 + z * (A6 + z * (A8 + z * A10))));
+                p2 = z * (A1 + z * (A3 + z * (A5 + z * (A7 + z * (A9 + z * A11)))));
+                p = y * p1 + p2;
+                r += p - 0.5 * y;
+            }
+            1 => {
+                z = y * y;
+                w = z * y;
+                p1 = T0 + w * (T3 + w * (T6 + w * (T9 + w * T12))); /* parallel comp */
+                p2 = T1 + w * (T4 + w * (T7 + w * (T10 + w * T13)));
+                p3 = T2 + w * (T5 + w * (T8 + w * (T11 + w * T14)));
+                p = z * p1 - (TT - w * (p2 + y * p3));
+                r += TF + p;
+            }
+            2 => {
+                p1 = y * (U0 + y * (U1 + y * (U2 + y * (U3 + y * (U4 + y * U5)))));
+                p2 = 1.0 + y * (V1 + y * (V2 + y * (V3 + y * (V4 + y * V5))));
+                r += -0.5 * y + p1 / p2;
+            }
+            #[cfg(feature = "checked")]
+            _ => unreachable!(),
+            #[cfg(not(feature = "checked"))]
+            _ => {}
+        }
+    } else if ix < 0x40200000 {
+        /* x < 8.0 */
+        i = x as i32;
+        y = x - (i as f64);
+        p = y * (S0 + y * (S1 + y * (S2 + y * (S3 + y * (S4 + y * (S5 + y * S6))))));
+        q = 1.0 + y * (R1 + y * (R2 + y * (R3 + y * (R4 + y * (R5 + y * R6)))));
+        r = 0.5 * y + p / q;
+        z = 1.0; /* lgamma(1+s) = log(s) + lgamma(s) */
+        // TODO: In C, this was implemented using switch jumps with fallthrough.
+        // Does this implementation have performance problems?
+        if i >= 7 {
+            z *= y + 6.0;
+        }
+        if i >= 6 {
+            z *= y + 5.0;
+        }
+        if i >= 5 {
+            z *= y + 4.0;
+        }
+        if i >= 4 {
+            z *= y + 3.0;
+        }
+        if i >= 3 {
+            z *= y + 2.0;
+            r += log(z);
+        }
+    } else if ix < 0x43900000 {
+        /* 8.0 <= x < 2**58 */
+        t = log(x);
+        z = 1.0 / x;
+        y = z * z;
+        w = W0 + z * (W1 + y * (W2 + y * (W3 + y * (W4 + y * (W5 + y * W6)))));
+        r = (x - 0.5) * (t - 1.0) + w;
+    } else {
+        /* 2**58 <= x <= inf */
+        r = x * (log(x) - 1.0);
+    }
+    if sign {
+        r = nadj - r;
+    }
+    return (r, signgam);
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/lgammaf.rs.html b/src/libm/math/lgammaf.rs.html new file mode 100644 index 000000000..26e4d785d --- /dev/null +++ b/src/libm/math/lgammaf.rs.html @@ -0,0 +1,13 @@ +lgammaf.rs.html -- source
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+
+use super::lgammaf_r;
+
+pub fn lgammaf(x: f32) -> f32 {
+    lgammaf_r(x).0
+}
+
+
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+
+/* origin: FreeBSD /usr/src/lib/msun/src/e_lgammaf_r.c */
+/*
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+use super::{floorf, k_cosf, k_sinf, logf};
+
+const PI: f32 = 3.1415927410e+00; /* 0x40490fdb */
+const A0: f32 = 7.7215664089e-02; /* 0x3d9e233f */
+const A1: f32 = 3.2246702909e-01; /* 0x3ea51a66 */
+const A2: f32 = 6.7352302372e-02; /* 0x3d89f001 */
+const A3: f32 = 2.0580807701e-02; /* 0x3ca89915 */
+const A4: f32 = 7.3855509982e-03; /* 0x3bf2027e */
+const A5: f32 = 2.8905137442e-03; /* 0x3b3d6ec6 */
+const A6: f32 = 1.1927076848e-03; /* 0x3a9c54a1 */
+const A7: f32 = 5.1006977446e-04; /* 0x3a05b634 */
+const A8: f32 = 2.2086278477e-04; /* 0x39679767 */
+const A9: f32 = 1.0801156895e-04; /* 0x38e28445 */
+const A10: f32 = 2.5214456400e-05; /* 0x37d383a2 */
+const A11: f32 = 4.4864096708e-05; /* 0x383c2c75 */
+const TC: f32 = 1.4616321325e+00; /* 0x3fbb16c3 */
+const TF: f32 = -1.2148628384e-01; /* 0xbdf8cdcd */
+/* TT = -(tail of TF) */
+const TT: f32 = 6.6971006518e-09; /* 0x31e61c52 */
+const T0: f32 = 4.8383611441e-01; /* 0x3ef7b95e */
+const T1: f32 = -1.4758771658e-01; /* 0xbe17213c */
+const T2: f32 = 6.4624942839e-02; /* 0x3d845a15 */
+const T3: f32 = -3.2788541168e-02; /* 0xbd064d47 */
+const T4: f32 = 1.7970675603e-02; /* 0x3c93373d */
+const T5: f32 = -1.0314224288e-02; /* 0xbc28fcfe */
+const T6: f32 = 6.1005386524e-03; /* 0x3bc7e707 */
+const T7: f32 = -3.6845202558e-03; /* 0xbb7177fe */
+const T8: f32 = 2.2596477065e-03; /* 0x3b141699 */
+const T9: f32 = -1.4034647029e-03; /* 0xbab7f476 */
+const T10: f32 = 8.8108185446e-04; /* 0x3a66f867 */
+const T11: f32 = -5.3859531181e-04; /* 0xba0d3085 */
+const T12: f32 = 3.1563205994e-04; /* 0x39a57b6b */
+const T13: f32 = -3.1275415677e-04; /* 0xb9a3f927 */
+const T14: f32 = 3.3552918467e-04; /* 0x39afe9f7 */
+const U0: f32 = -7.7215664089e-02; /* 0xbd9e233f */
+const U1: f32 = 6.3282704353e-01; /* 0x3f2200f4 */
+const U2: f32 = 1.4549225569e+00; /* 0x3fba3ae7 */
+const U3: f32 = 9.7771751881e-01; /* 0x3f7a4bb2 */
+const U4: f32 = 2.2896373272e-01; /* 0x3e6a7578 */
+const U5: f32 = 1.3381091878e-02; /* 0x3c5b3c5e */
+const V1: f32 = 2.4559779167e+00; /* 0x401d2ebe */
+const V2: f32 = 2.1284897327e+00; /* 0x4008392d */
+const V3: f32 = 7.6928514242e-01; /* 0x3f44efdf */
+const V4: f32 = 1.0422264785e-01; /* 0x3dd572af */
+const V5: f32 = 3.2170924824e-03; /* 0x3b52d5db */
+const S0: f32 = -7.7215664089e-02; /* 0xbd9e233f */
+const S1: f32 = 2.1498242021e-01; /* 0x3e5c245a */
+const S2: f32 = 3.2577878237e-01; /* 0x3ea6cc7a */
+const S3: f32 = 1.4635047317e-01; /* 0x3e15dce6 */
+const S4: f32 = 2.6642270386e-02; /* 0x3cda40e4 */
+const S5: f32 = 1.8402845599e-03; /* 0x3af135b4 */
+const S6: f32 = 3.1947532989e-05; /* 0x3805ff67 */
+const R1: f32 = 1.3920053244e+00; /* 0x3fb22d3b */
+const R2: f32 = 7.2193557024e-01; /* 0x3f38d0c5 */
+const R3: f32 = 1.7193385959e-01; /* 0x3e300f6e */
+const R4: f32 = 1.8645919859e-02; /* 0x3c98bf54 */
+const R5: f32 = 7.7794247773e-04; /* 0x3a4beed6 */
+const R6: f32 = 7.3266842264e-06; /* 0x36f5d7bd */
+const W0: f32 = 4.1893854737e-01; /* 0x3ed67f1d */
+const W1: f32 = 8.3333335817e-02; /* 0x3daaaaab */
+const W2: f32 = -2.7777778450e-03; /* 0xbb360b61 */
+const W3: f32 = 7.9365057172e-04; /* 0x3a500cfd */
+const W4: f32 = -5.9518753551e-04; /* 0xba1c065c */
+const W5: f32 = 8.3633989561e-04; /* 0x3a5b3dd2 */
+const W6: f32 = -1.6309292987e-03; /* 0xbad5c4e8 */
+
+/* sin(PI*x) assuming x > 2^-100, if sin(PI*x)==0 the sign is arbitrary */
+fn sin_pi(mut x: f32) -> f32 {
+    let mut y: f64;
+    let mut n: isize;
+
+    /* spurious inexact if odd int */
+    x = 2.0 * (x * 0.5 - floorf(x * 0.5)); /* x mod 2.0 */
+
+    n = (x * 4.0) as isize;
+    n = (n + 1) / 2;
+    y = (x as f64) - (n as f64) * 0.5;
+    y *= 3.14159265358979323846;
+    match n {
+        1 => k_cosf(y),
+        2 => k_sinf(-y),
+        3 => -k_cosf(y),
+        0 | _ => k_sinf(y),
+    }
+}
+
+pub fn lgammaf_r(mut x: f32) -> (f32, i32) {
+    let u = x.to_bits();
+    let mut t: f32;
+    let y: f32;
+    let mut z: f32;
+    let nadj: f32;
+    let p: f32;
+    let p1: f32;
+    let p2: f32;
+    let p3: f32;
+    let q: f32;
+    let mut r: f32;
+    let w: f32;
+    let ix: u32;
+    let i: i32;
+    let sign: bool;
+    let mut signgam: i32;
+
+    /* purge off +-inf, NaN, +-0, tiny and negative arguments */
+    signgam = 1;
+    sign = (u >> 31) != 0;
+    ix = u & 0x7fffffff;
+    if ix >= 0x7f800000 {
+        return (x * x, signgam);
+    }
+    if ix < 0x35000000 {
+        /* |x| < 2**-21, return -log(|x|) */
+        if sign {
+            signgam = -1;
+            x = -x;
+        }
+        return (-logf(x), signgam);
+    }
+    if sign {
+        x = -x;
+        t = sin_pi(x);
+        if t == 0.0 {
+            /* -integer */
+            return (1.0 / (x - x), signgam);
+        }
+        if t > 0.0 {
+            signgam = -1;
+        } else {
+            t = -t;
+        }
+        nadj = logf(PI / (t * x));
+    } else {
+        nadj = 0.0;
+    }
+
+    /* purge off 1 and 2 */
+    if ix == 0x3f800000 || ix == 0x40000000 {
+        r = 0.0;
+    }
+    /* for x < 2.0 */
+    else if ix < 0x40000000 {
+        if ix <= 0x3f666666 {
+            /* lgamma(x) = lgamma(x+1)-log(x) */
+            r = -logf(x);
+            if ix >= 0x3f3b4a20 {
+                y = 1.0 - x;
+                i = 0;
+            } else if ix >= 0x3e6d3308 {
+                y = x - (TC - 1.0);
+                i = 1;
+            } else {
+                y = x;
+                i = 2;
+            }
+        } else {
+            r = 0.0;
+            if ix >= 0x3fdda618 {
+                /* [1.7316,2] */
+                y = 2.0 - x;
+                i = 0;
+            } else if ix >= 0x3F9da620 {
+                /* [1.23,1.73] */
+                y = x - TC;
+                i = 1;
+            } else {
+                y = x - 1.0;
+                i = 2;
+            }
+        }
+        match i {
+            0 => {
+                z = y * y;
+                p1 = A0 + z * (A2 + z * (A4 + z * (A6 + z * (A8 + z * A10))));
+                p2 = z * (A1 + z * (A3 + z * (A5 + z * (A7 + z * (A9 + z * A11)))));
+                p = y * p1 + p2;
+                r += p - 0.5 * y;
+            }
+            1 => {
+                z = y * y;
+                w = z * y;
+                p1 = T0 + w * (T3 + w * (T6 + w * (T9 + w * T12))); /* parallel comp */
+                p2 = T1 + w * (T4 + w * (T7 + w * (T10 + w * T13)));
+                p3 = T2 + w * (T5 + w * (T8 + w * (T11 + w * T14)));
+                p = z * p1 - (TT - w * (p2 + y * p3));
+                r += TF + p;
+            }
+            2 => {
+                p1 = y * (U0 + y * (U1 + y * (U2 + y * (U3 + y * (U4 + y * U5)))));
+                p2 = 1.0 + y * (V1 + y * (V2 + y * (V3 + y * (V4 + y * V5))));
+                r += -0.5 * y + p1 / p2;
+            }
+            #[cfg(feature = "checked")]
+            _ => unreachable!(),
+            #[cfg(not(feature = "checked"))]
+            _ => {}
+        }
+    } else if ix < 0x41000000 {
+        /* x < 8.0 */
+        i = x as i32;
+        y = x - (i as f32);
+        p = y * (S0 + y * (S1 + y * (S2 + y * (S3 + y * (S4 + y * (S5 + y * S6))))));
+        q = 1.0 + y * (R1 + y * (R2 + y * (R3 + y * (R4 + y * (R5 + y * R6)))));
+        r = 0.5 * y + p / q;
+        z = 1.0; /* lgamma(1+s) = log(s) + lgamma(s) */
+        // TODO: In C, this was implemented using switch jumps with fallthrough.
+        // Does this implementation have performance problems?
+        if i >= 7 {
+            z *= y + 6.0;
+        }
+        if i >= 6 {
+            z *= y + 5.0;
+        }
+        if i >= 5 {
+            z *= y + 4.0;
+        }
+        if i >= 4 {
+            z *= y + 3.0;
+        }
+        if i >= 3 {
+            z *= y + 2.0;
+            r += logf(z);
+        }
+    } else if ix < 0x5c800000 {
+        /* 8.0 <= x < 2**58 */
+        t = logf(x);
+        z = 1.0 / x;
+        y = z * z;
+        w = W0 + z * (W1 + y * (W2 + y * (W3 + y * (W4 + y * (W5 + y * W6)))));
+        r = (x - 0.5) * (t - 1.0) + w;
+    } else {
+        /* 2**58 <= x <= inf */
+        r = x * (logf(x) - 1.0);
+    }
+    if sign {
+        r = nadj - r;
+    }
+    return (r, signgam);
+}
+
+
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+/* origin: FreeBSD /usr/src/lib/msun/src/e_log.c */
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunSoft, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+/* log(x)
+ * Return the logarithm of x
+ *
+ * Method :
+ *   1. Argument Reduction: find k and f such that
+ *                      x = 2^k * (1+f),
+ *         where  sqrt(2)/2 < 1+f < sqrt(2) .
+ *
+ *   2. Approximation of log(1+f).
+ *      Let s = f/(2+f) ; based on log(1+f) = log(1+s) - log(1-s)
+ *               = 2s + 2/3 s**3 + 2/5 s**5 + .....,
+ *               = 2s + s*R
+ *      We use a special Remez algorithm on [0,0.1716] to generate
+ *      a polynomial of degree 14 to approximate R The maximum error
+ *      of this polynomial approximation is bounded by 2**-58.45. In
+ *      other words,
+ *                      2      4      6      8      10      12      14
+ *          R(z) ~ Lg1*s +Lg2*s +Lg3*s +Lg4*s +Lg5*s  +Lg6*s  +Lg7*s
+ *      (the values of Lg1 to Lg7 are listed in the program)
+ *      and
+ *          |      2          14          |     -58.45
+ *          | Lg1*s +...+Lg7*s    -  R(z) | <= 2
+ *          |                             |
+ *      Note that 2s = f - s*f = f - hfsq + s*hfsq, where hfsq = f*f/2.
+ *      In order to guarantee error in log below 1ulp, we compute log
+ *      by
+ *              log(1+f) = f - s*(f - R)        (if f is not too large)
+ *              log(1+f) = f - (hfsq - s*(hfsq+R)).     (better accuracy)
+ *
+ *      3. Finally,  log(x) = k*ln2 + log(1+f).
+ *                          = k*ln2_hi+(f-(hfsq-(s*(hfsq+R)+k*ln2_lo)))
+ *         Here ln2 is split into two floating point number:
+ *                      ln2_hi + ln2_lo,
+ *         where n*ln2_hi is always exact for |n| < 2000.
+ *
+ * Special cases:
+ *      log(x) is NaN with signal if x < 0 (including -INF) ;
+ *      log(+INF) is +INF; log(0) is -INF with signal;
+ *      log(NaN) is that NaN with no signal.
+ *
+ * Accuracy:
+ *      according to an error analysis, the error is always less than
+ *      1 ulp (unit in the last place).
+ *
+ * Constants:
+ * The hexadecimal values are the intended ones for the following
+ * constants. The decimal values may be used, provided that the
+ * compiler will convert from decimal to binary accurately enough
+ * to produce the hexadecimal values shown.
+ */
+
+const LN2_HI: f64 = 6.93147180369123816490e-01; /* 3fe62e42 fee00000 */
+const LN2_LO: f64 = 1.90821492927058770002e-10; /* 3dea39ef 35793c76 */
+const LG1: f64 = 6.666666666666735130e-01; /* 3FE55555 55555593 */
+const LG2: f64 = 3.999999999940941908e-01; /* 3FD99999 9997FA04 */
+const LG3: f64 = 2.857142874366239149e-01; /* 3FD24924 94229359 */
+const LG4: f64 = 2.222219843214978396e-01; /* 3FCC71C5 1D8E78AF */
+const LG5: f64 = 1.818357216161805012e-01; /* 3FC74664 96CB03DE */
+const LG6: f64 = 1.531383769920937332e-01; /* 3FC39A09 D078C69F */
+const LG7: f64 = 1.479819860511658591e-01; /* 3FC2F112 DF3E5244 */
+
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn log(mut x: f64) -> f64 {
+    let x1p54 = f64::from_bits(0x4350000000000000); // 0x1p54 === 2 ^ 54
+
+    let mut ui = x.to_bits();
+    let mut hx: u32 = (ui >> 32) as u32;
+    let mut k: i32 = 0;
+
+    if (hx < 0x00100000) || ((hx >> 31) != 0) {
+        /* x < 2**-126  */
+        if ui << 1 == 0 {
+            return -1. / (x * x); /* log(+-0)=-inf */
+        }
+        if hx >> 31 != 0 {
+            return (x - x) / 0.0; /* log(-#) = NaN */
+        }
+        /* subnormal number, scale x up */
+        k -= 54;
+        x *= x1p54;
+        ui = x.to_bits();
+        hx = (ui >> 32) as u32;
+    } else if hx >= 0x7ff00000 {
+        return x;
+    } else if hx == 0x3ff00000 && ui << 32 == 0 {
+        return 0.;
+    }
+
+    /* reduce x into [sqrt(2)/2, sqrt(2)] */
+    hx += 0x3ff00000 - 0x3fe6a09e;
+    k += ((hx >> 20) as i32) - 0x3ff;
+    hx = (hx & 0x000fffff) + 0x3fe6a09e;
+    ui = ((hx as u64) << 32) | (ui & 0xffffffff);
+    x = f64::from_bits(ui);
+
+    let f: f64 = x - 1.0;
+    let hfsq: f64 = 0.5 * f * f;
+    let s: f64 = f / (2.0 + f);
+    let z: f64 = s * s;
+    let w: f64 = z * z;
+    let t1: f64 = w * (LG2 + w * (LG4 + w * LG6));
+    let t2: f64 = z * (LG1 + w * (LG3 + w * (LG5 + w * LG7)));
+    let r: f64 = t2 + t1;
+    let dk: f64 = k as f64;
+    s * (hfsq + r) + dk * LN2_LO - hfsq + f + dk * LN2_HI
+}
+
+
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+/* origin: FreeBSD /usr/src/lib/msun/src/e_log10.c */
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunSoft, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+/*
+ * Return the base 10 logarithm of x.  See log.c for most comments.
+ *
+ * Reduce x to 2^k (1+f) and calculate r = log(1+f) - f + f*f/2
+ * as in log.c, then combine and scale in extra precision:
+ *    log10(x) = (f - f*f/2 + r)/log(10) + k*log10(2)
+ */
+
+use core::f64;
+
+const IVLN10HI: f64 = 4.34294481878168880939e-01; /* 0x3fdbcb7b, 0x15200000 */
+const IVLN10LO: f64 = 2.50829467116452752298e-11; /* 0x3dbb9438, 0xca9aadd5 */
+const LOG10_2HI: f64 = 3.01029995663611771306e-01; /* 0x3FD34413, 0x509F6000 */
+const LOG10_2LO: f64 = 3.69423907715893078616e-13; /* 0x3D59FEF3, 0x11F12B36 */
+const LG1: f64 = 6.666666666666735130e-01; /* 3FE55555 55555593 */
+const LG2: f64 = 3.999999999940941908e-01; /* 3FD99999 9997FA04 */
+const LG3: f64 = 2.857142874366239149e-01; /* 3FD24924 94229359 */
+const LG4: f64 = 2.222219843214978396e-01; /* 3FCC71C5 1D8E78AF */
+const LG5: f64 = 1.818357216161805012e-01; /* 3FC74664 96CB03DE */
+const LG6: f64 = 1.531383769920937332e-01; /* 3FC39A09 D078C69F */
+const LG7: f64 = 1.479819860511658591e-01; /* 3FC2F112 DF3E5244 */
+
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn log10(mut x: f64) -> f64 {
+    let x1p54 = f64::from_bits(0x4350000000000000); // 0x1p54 === 2 ^ 54
+
+    let mut ui: u64 = x.to_bits();
+    let hfsq: f64;
+    let f: f64;
+    let s: f64;
+    let z: f64;
+    let r: f64;
+    let mut w: f64;
+    let t1: f64;
+    let t2: f64;
+    let dk: f64;
+    let y: f64;
+    let mut hi: f64;
+    let lo: f64;
+    let mut val_hi: f64;
+    let mut val_lo: f64;
+    let mut hx: u32;
+    let mut k: i32;
+
+    hx = (ui >> 32) as u32;
+    k = 0;
+    if hx < 0x00100000 || (hx >> 31) > 0 {
+        if ui << 1 == 0 {
+            return -1. / (x * x); /* log(+-0)=-inf */
+        }
+        if (hx >> 31) > 0 {
+            return (x - x) / 0.0; /* log(-#) = NaN */
+        }
+        /* subnormal number, scale x up */
+        k -= 54;
+        x *= x1p54;
+        ui = x.to_bits();
+        hx = (ui >> 32) as u32;
+    } else if hx >= 0x7ff00000 {
+        return x;
+    } else if hx == 0x3ff00000 && ui << 32 == 0 {
+        return 0.;
+    }
+
+    /* reduce x into [sqrt(2)/2, sqrt(2)] */
+    hx += 0x3ff00000 - 0x3fe6a09e;
+    k += (hx >> 20) as i32 - 0x3ff;
+    hx = (hx & 0x000fffff) + 0x3fe6a09e;
+    ui = (hx as u64) << 32 | (ui & 0xffffffff);
+    x = f64::from_bits(ui);
+
+    f = x - 1.0;
+    hfsq = 0.5 * f * f;
+    s = f / (2.0 + f);
+    z = s * s;
+    w = z * z;
+    t1 = w * (LG2 + w * (LG4 + w * LG6));
+    t2 = z * (LG1 + w * (LG3 + w * (LG5 + w * LG7)));
+    r = t2 + t1;
+
+    /* See log2.c for details. */
+    /* hi+lo = f - hfsq + s*(hfsq+R) ~ log(1+f) */
+    hi = f - hfsq;
+    ui = hi.to_bits();
+    ui &= (-1i64 as u64) << 32;
+    hi = f64::from_bits(ui);
+    lo = f - hi - hfsq + s * (hfsq + r);
+
+    /* val_hi+val_lo ~ log10(1+f) + k*log10(2) */
+    val_hi = hi * IVLN10HI;
+    dk = k as f64;
+    y = dk * LOG10_2HI;
+    val_lo = dk * LOG10_2LO + (lo + hi) * IVLN10LO + lo * IVLN10HI;
+
+    /*
+     * Extra precision in for adding y is not strictly needed
+     * since there is no very large cancellation near x = sqrt(2) or
+     * x = 1/sqrt(2), but we do it anyway since it costs little on CPUs
+     * with some parallelism and it reduces the error for many args.
+     */
+    w = y + val_hi;
+    val_lo += (y - w) + val_hi;
+    val_hi = w;
+
+    val_lo + val_hi
+}
+
+
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+/* origin: FreeBSD /usr/src/lib/msun/src/e_log10f.c */
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+/*
+ * See comments in log10.c.
+ */
+
+use core::f32;
+
+const IVLN10HI: f32 = 4.3432617188e-01; /* 0x3ede6000 */
+const IVLN10LO: f32 = -3.1689971365e-05; /* 0xb804ead9 */
+const LOG10_2HI: f32 = 3.0102920532e-01; /* 0x3e9a2080 */
+const LOG10_2LO: f32 = 7.9034151668e-07; /* 0x355427db */
+/* |(log(1+s)-log(1-s))/s - Lg(s)| < 2**-34.24 (~[-4.95e-11, 4.97e-11]). */
+const LG1: f32 = 0.66666662693; /* 0xaaaaaa.0p-24 */
+const LG2: f32 = 0.40000972152; /* 0xccce13.0p-25 */
+const LG3: f32 = 0.28498786688; /* 0x91e9ee.0p-25 */
+const LG4: f32 = 0.24279078841; /* 0xf89e26.0p-26 */
+
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn log10f(mut x: f32) -> f32 {
+    let x1p25f = f32::from_bits(0x4c000000); // 0x1p25f === 2 ^ 25
+
+    let mut ui: u32 = x.to_bits();
+    let hfsq: f32;
+    let f: f32;
+    let s: f32;
+    let z: f32;
+    let r: f32;
+    let w: f32;
+    let t1: f32;
+    let t2: f32;
+    let dk: f32;
+    let mut hi: f32;
+    let lo: f32;
+    let mut ix: u32;
+    let mut k: i32;
+
+    ix = ui;
+    k = 0;
+    if ix < 0x00800000 || (ix >> 31) > 0 {
+        /* x < 2**-126  */
+        if ix << 1 == 0 {
+            return -1. / (x * x); /* log(+-0)=-inf */
+        }
+        if (ix >> 31) > 0 {
+            return (x - x) / 0.0; /* log(-#) = NaN */
+        }
+        /* subnormal number, scale up x */
+        k -= 25;
+        x *= x1p25f;
+        ui = x.to_bits();
+        ix = ui;
+    } else if ix >= 0x7f800000 {
+        return x;
+    } else if ix == 0x3f800000 {
+        return 0.;
+    }
+
+    /* reduce x into [sqrt(2)/2, sqrt(2)] */
+    ix += 0x3f800000 - 0x3f3504f3;
+    k += (ix >> 23) as i32 - 0x7f;
+    ix = (ix & 0x007fffff) + 0x3f3504f3;
+    ui = ix;
+    x = f32::from_bits(ui);
+
+    f = x - 1.0;
+    s = f / (2.0 + f);
+    z = s * s;
+    w = z * z;
+    t1 = w * (LG2 + w * LG4);
+    t2 = z * (LG1 + w * LG3);
+    r = t2 + t1;
+    hfsq = 0.5 * f * f;
+
+    hi = f - hfsq;
+    ui = hi.to_bits();
+    ui &= 0xfffff000;
+    hi = f32::from_bits(ui);
+    lo = f - hi - hfsq + s * (hfsq + r);
+    dk = k as f32;
+    dk * LOG10_2LO + (lo + hi) * IVLN10LO + lo * IVLN10HI + hi * IVLN10HI + dk * LOG10_2HI
+}
+
+
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+
+/* origin: FreeBSD /usr/src/lib/msun/src/s_log1p.c */
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+/* double log1p(double x)
+ * Return the natural logarithm of 1+x.
+ *
+ * Method :
+ *   1. Argument Reduction: find k and f such that
+ *                      1+x = 2^k * (1+f),
+ *         where  sqrt(2)/2 < 1+f < sqrt(2) .
+ *
+ *      Note. If k=0, then f=x is exact. However, if k!=0, then f
+ *      may not be representable exactly. In that case, a correction
+ *      term is need. Let u=1+x rounded. Let c = (1+x)-u, then
+ *      log(1+x) - log(u) ~ c/u. Thus, we proceed to compute log(u),
+ *      and add back the correction term c/u.
+ *      (Note: when x > 2**53, one can simply return log(x))
+ *
+ *   2. Approximation of log(1+f): See log.c
+ *
+ *   3. Finally, log1p(x) = k*ln2 + log(1+f) + c/u. See log.c
+ *
+ * Special cases:
+ *      log1p(x) is NaN with signal if x < -1 (including -INF) ;
+ *      log1p(+INF) is +INF; log1p(-1) is -INF with signal;
+ *      log1p(NaN) is that NaN with no signal.
+ *
+ * Accuracy:
+ *      according to an error analysis, the error is always less than
+ *      1 ulp (unit in the last place).
+ *
+ * Constants:
+ * The hexadecimal values are the intended ones for the following
+ * constants. The decimal values may be used, provided that the
+ * compiler will convert from decimal to binary accurately enough
+ * to produce the hexadecimal values shown.
+ *
+ * Note: Assuming log() return accurate answer, the following
+ *       algorithm can be used to compute log1p(x) to within a few ULP:
+ *
+ *              u = 1+x;
+ *              if(u==1.0) return x ; else
+ *                         return log(u)*(x/(u-1.0));
+ *
+ *       See HP-15C Advanced Functions Handbook, p.193.
+ */
+
+use core::f64;
+
+const LN2_HI: f64 = 6.93147180369123816490e-01; /* 3fe62e42 fee00000 */
+const LN2_LO: f64 = 1.90821492927058770002e-10; /* 3dea39ef 35793c76 */
+const LG1: f64 = 6.666666666666735130e-01; /* 3FE55555 55555593 */
+const LG2: f64 = 3.999999999940941908e-01; /* 3FD99999 9997FA04 */
+const LG3: f64 = 2.857142874366239149e-01; /* 3FD24924 94229359 */
+const LG4: f64 = 2.222219843214978396e-01; /* 3FCC71C5 1D8E78AF */
+const LG5: f64 = 1.818357216161805012e-01; /* 3FC74664 96CB03DE */
+const LG6: f64 = 1.531383769920937332e-01; /* 3FC39A09 D078C69F */
+const LG7: f64 = 1.479819860511658591e-01; /* 3FC2F112 DF3E5244 */
+
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn log1p(x: f64) -> f64 {
+    let mut ui: u64 = x.to_bits();
+    let hfsq: f64;
+    let mut f: f64 = 0.;
+    let mut c: f64 = 0.;
+    let s: f64;
+    let z: f64;
+    let r: f64;
+    let w: f64;
+    let t1: f64;
+    let t2: f64;
+    let dk: f64;
+    let hx: u32;
+    let mut hu: u32;
+    let mut k: i32;
+
+    hx = (ui >> 32) as u32;
+    k = 1;
+    if hx < 0x3fda827a || (hx >> 31) > 0 {
+        /* 1+x < sqrt(2)+ */
+        if hx >= 0xbff00000 {
+            /* x <= -1.0 */
+            if x == -1. {
+                return x / 0.0; /* log1p(-1) = -inf */
+            }
+            return (x - x) / 0.0; /* log1p(x<-1) = NaN */
+        }
+        if hx << 1 < 0x3ca00000 << 1 {
+            /* |x| < 2**-53 */
+            /* underflow if subnormal */
+            if (hx & 0x7ff00000) == 0 {
+                force_eval!(x as f32);
+            }
+            return x;
+        }
+        if hx <= 0xbfd2bec4 {
+            /* sqrt(2)/2- <= 1+x < sqrt(2)+ */
+            k = 0;
+            c = 0.;
+            f = x;
+        }
+    } else if hx >= 0x7ff00000 {
+        return x;
+    }
+    if k > 0 {
+        ui = (1. + x).to_bits();
+        hu = (ui >> 32) as u32;
+        hu += 0x3ff00000 - 0x3fe6a09e;
+        k = (hu >> 20) as i32 - 0x3ff;
+        /* correction term ~ log(1+x)-log(u), avoid underflow in c/u */
+        if k < 54 {
+            c = if k >= 2 {
+                1. - (f64::from_bits(ui) - x)
+            } else {
+                x - (f64::from_bits(ui) - 1.)
+            };
+            c /= f64::from_bits(ui);
+        } else {
+            c = 0.;
+        }
+        /* reduce u into [sqrt(2)/2, sqrt(2)] */
+        hu = (hu & 0x000fffff) + 0x3fe6a09e;
+        ui = (hu as u64) << 32 | (ui & 0xffffffff);
+        f = f64::from_bits(ui) - 1.;
+    }
+    hfsq = 0.5 * f * f;
+    s = f / (2.0 + f);
+    z = s * s;
+    w = z * z;
+    t1 = w * (LG2 + w * (LG4 + w * LG6));
+    t2 = z * (LG1 + w * (LG3 + w * (LG5 + w * LG7)));
+    r = t2 + t1;
+    dk = k as f64;
+    s * (hfsq + r) + (dk * LN2_LO + c) - hfsq + f + dk * LN2_HI
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/log1pf.rs.html b/src/libm/math/log1pf.rs.html new file mode 100644 index 000000000..58befba79 --- /dev/null +++ b/src/libm/math/log1pf.rs.html @@ -0,0 +1,201 @@ +log1pf.rs.html -- source
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+
+/* origin: FreeBSD /usr/src/lib/msun/src/s_log1pf.c */
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+use core::f32;
+
+const LN2_HI: f32 = 6.9313812256e-01; /* 0x3f317180 */
+const LN2_LO: f32 = 9.0580006145e-06; /* 0x3717f7d1 */
+/* |(log(1+s)-log(1-s))/s - Lg(s)| < 2**-34.24 (~[-4.95e-11, 4.97e-11]). */
+const LG1: f32 = 0.66666662693; /* 0xaaaaaa.0p-24 */
+const LG2: f32 = 0.40000972152; /* 0xccce13.0p-25 */
+const LG3: f32 = 0.28498786688; /* 0x91e9ee.0p-25 */
+const LG4: f32 = 0.24279078841; /* 0xf89e26.0p-26 */
+
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn log1pf(x: f32) -> f32 {
+    let mut ui: u32 = x.to_bits();
+    let hfsq: f32;
+    let mut f: f32 = 0.;
+    let mut c: f32 = 0.;
+    let s: f32;
+    let z: f32;
+    let r: f32;
+    let w: f32;
+    let t1: f32;
+    let t2: f32;
+    let dk: f32;
+    let ix: u32;
+    let mut iu: u32;
+    let mut k: i32;
+
+    ix = ui;
+    k = 1;
+    if ix < 0x3ed413d0 || (ix >> 31) > 0 {
+        /* 1+x < sqrt(2)+  */
+        if ix >= 0xbf800000 {
+            /* x <= -1.0 */
+            if x == -1. {
+                return x / 0.0; /* log1p(-1)=+inf */
+            }
+            return (x - x) / 0.0; /* log1p(x<-1)=NaN */
+        }
+        if ix << 1 < 0x33800000 << 1 {
+            /* |x| < 2**-24 */
+            /* underflow if subnormal */
+            if (ix & 0x7f800000) == 0 {
+                force_eval!(x * x);
+            }
+            return x;
+        }
+        if ix <= 0xbe95f619 {
+            /* sqrt(2)/2- <= 1+x < sqrt(2)+ */
+            k = 0;
+            c = 0.;
+            f = x;
+        }
+    } else if ix >= 0x7f800000 {
+        return x;
+    }
+    if k > 0 {
+        ui = (1. + x).to_bits();
+        iu = ui;
+        iu += 0x3f800000 - 0x3f3504f3;
+        k = (iu >> 23) as i32 - 0x7f;
+        /* correction term ~ log(1+x)-log(u), avoid underflow in c/u */
+        if k < 25 {
+            c = if k >= 2 {
+                1. - (f32::from_bits(ui) - x)
+            } else {
+                x - (f32::from_bits(ui) - 1.)
+            };
+            c /= f32::from_bits(ui);
+        } else {
+            c = 0.;
+        }
+        /* reduce u into [sqrt(2)/2, sqrt(2)] */
+        iu = (iu & 0x007fffff) + 0x3f3504f3;
+        ui = iu;
+        f = f32::from_bits(ui) - 1.;
+    }
+    s = f / (2.0 + f);
+    z = s * s;
+    w = z * z;
+    t1 = w * (LG2 + w * LG4);
+    t2 = z * (LG1 + w * LG3);
+    r = t2 + t1;
+    hfsq = 0.5 * f * f;
+    dk = k as f32;
+    s * (hfsq + r) + (dk * LN2_LO + c) - hfsq + f + dk * LN2_HI
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/log2.rs.html b/src/libm/math/log2.rs.html new file mode 100644 index 000000000..852460f8c --- /dev/null +++ b/src/libm/math/log2.rs.html @@ -0,0 +1,217 @@ +log2.rs.html -- source
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+
+/* origin: FreeBSD /usr/src/lib/msun/src/e_log2.c */
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunSoft, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+/*
+ * Return the base 2 logarithm of x.  See log.c for most comments.
+ *
+ * Reduce x to 2^k (1+f) and calculate r = log(1+f) - f + f*f/2
+ * as in log.c, then combine and scale in extra precision:
+ *    log2(x) = (f - f*f/2 + r)/log(2) + k
+ */
+
+use core::f64;
+
+const IVLN2HI: f64 = 1.44269504072144627571e+00; /* 0x3ff71547, 0x65200000 */
+const IVLN2LO: f64 = 1.67517131648865118353e-10; /* 0x3de705fc, 0x2eefa200 */
+const LG1: f64 = 6.666666666666735130e-01; /* 3FE55555 55555593 */
+const LG2: f64 = 3.999999999940941908e-01; /* 3FD99999 9997FA04 */
+const LG3: f64 = 2.857142874366239149e-01; /* 3FD24924 94229359 */
+const LG4: f64 = 2.222219843214978396e-01; /* 3FCC71C5 1D8E78AF */
+const LG5: f64 = 1.818357216161805012e-01; /* 3FC74664 96CB03DE */
+const LG6: f64 = 1.531383769920937332e-01; /* 3FC39A09 D078C69F */
+const LG7: f64 = 1.479819860511658591e-01; /* 3FC2F112 DF3E5244 */
+
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn log2(mut x: f64) -> f64 {
+    let x1p54 = f64::from_bits(0x4350000000000000); // 0x1p54 === 2 ^ 54
+
+    let mut ui: u64 = x.to_bits();
+    let hfsq: f64;
+    let f: f64;
+    let s: f64;
+    let z: f64;
+    let r: f64;
+    let mut w: f64;
+    let t1: f64;
+    let t2: f64;
+    let y: f64;
+    let mut hi: f64;
+    let lo: f64;
+    let mut val_hi: f64;
+    let mut val_lo: f64;
+    let mut hx: u32;
+    let mut k: i32;
+
+    hx = (ui >> 32) as u32;
+    k = 0;
+    if hx < 0x00100000 || (hx >> 31) > 0 {
+        if ui << 1 == 0 {
+            return -1. / (x * x); /* log(+-0)=-inf */
+        }
+        if (hx >> 31) > 0 {
+            return (x - x) / 0.0; /* log(-#) = NaN */
+        }
+        /* subnormal number, scale x up */
+        k -= 54;
+        x *= x1p54;
+        ui = x.to_bits();
+        hx = (ui >> 32) as u32;
+    } else if hx >= 0x7ff00000 {
+        return x;
+    } else if hx == 0x3ff00000 && ui << 32 == 0 {
+        return 0.;
+    }
+
+    /* reduce x into [sqrt(2)/2, sqrt(2)] */
+    hx += 0x3ff00000 - 0x3fe6a09e;
+    k += (hx >> 20) as i32 - 0x3ff;
+    hx = (hx & 0x000fffff) + 0x3fe6a09e;
+    ui = (hx as u64) << 32 | (ui & 0xffffffff);
+    x = f64::from_bits(ui);
+
+    f = x - 1.0;
+    hfsq = 0.5 * f * f;
+    s = f / (2.0 + f);
+    z = s * s;
+    w = z * z;
+    t1 = w * (LG2 + w * (LG4 + w * LG6));
+    t2 = z * (LG1 + w * (LG3 + w * (LG5 + w * LG7)));
+    r = t2 + t1;
+
+    /* hi+lo = f - hfsq + s*(hfsq+R) ~ log(1+f) */
+    hi = f - hfsq;
+    ui = hi.to_bits();
+    ui &= (-1i64 as u64) << 32;
+    hi = f64::from_bits(ui);
+    lo = f - hi - hfsq + s * (hfsq + r);
+
+    val_hi = hi * IVLN2HI;
+    val_lo = (lo + hi) * IVLN2LO + lo * IVLN2HI;
+
+    /* spadd(val_hi, val_lo, y), except for not using double_t: */
+    y = k.into();
+    w = y + val_hi;
+    val_lo += (y - w) + val_hi;
+    val_hi = w;
+
+    val_lo + val_hi
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/log2f.rs.html b/src/libm/math/log2f.rs.html new file mode 100644 index 000000000..7d8ca8715 --- /dev/null +++ b/src/libm/math/log2f.rs.html @@ -0,0 +1,179 @@ +log2f.rs.html -- source
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+
+/* origin: FreeBSD /usr/src/lib/msun/src/e_log2f.c */
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+/*
+ * See comments in log2.c.
+ */
+
+use core::f32;
+
+const IVLN2HI: f32 = 1.4428710938e+00; /* 0x3fb8b000 */
+const IVLN2LO: f32 = -1.7605285393e-04; /* 0xb9389ad4 */
+/* |(log(1+s)-log(1-s))/s - Lg(s)| < 2**-34.24 (~[-4.95e-11, 4.97e-11]). */
+const LG1: f32 = 0.66666662693; /* 0xaaaaaa.0p-24 */
+const LG2: f32 = 0.40000972152; /* 0xccce13.0p-25 */
+const LG3: f32 = 0.28498786688; /* 0x91e9ee.0p-25 */
+const LG4: f32 = 0.24279078841; /* 0xf89e26.0p-26 */
+
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn log2f(mut x: f32) -> f32 {
+    let x1p25f = f32::from_bits(0x4c000000); // 0x1p25f === 2 ^ 25
+
+    let mut ui: u32 = x.to_bits();
+    let hfsq: f32;
+    let f: f32;
+    let s: f32;
+    let z: f32;
+    let r: f32;
+    let w: f32;
+    let t1: f32;
+    let t2: f32;
+    let mut hi: f32;
+    let lo: f32;
+    let mut ix: u32;
+    let mut k: i32;
+
+    ix = ui;
+    k = 0;
+    if ix < 0x00800000 || (ix >> 31) > 0 {
+        /* x < 2**-126  */
+        if ix << 1 == 0 {
+            return -1. / (x * x); /* log(+-0)=-inf */
+        }
+        if (ix >> 31) > 0 {
+            return (x - x) / 0.0; /* log(-#) = NaN */
+        }
+        /* subnormal number, scale up x */
+        k -= 25;
+        x *= x1p25f;
+        ui = x.to_bits();
+        ix = ui;
+    } else if ix >= 0x7f800000 {
+        return x;
+    } else if ix == 0x3f800000 {
+        return 0.;
+    }
+
+    /* reduce x into [sqrt(2)/2, sqrt(2)] */
+    ix += 0x3f800000 - 0x3f3504f3;
+    k += (ix >> 23) as i32 - 0x7f;
+    ix = (ix & 0x007fffff) + 0x3f3504f3;
+    ui = ix;
+    x = f32::from_bits(ui);
+
+    f = x - 1.0;
+    s = f / (2.0 + f);
+    z = s * s;
+    w = z * z;
+    t1 = w * (LG2 + w * LG4);
+    t2 = z * (LG1 + w * LG3);
+    r = t2 + t1;
+    hfsq = 0.5 * f * f;
+
+    hi = f - hfsq;
+    ui = hi.to_bits();
+    ui &= 0xfffff000;
+    hi = f32::from_bits(ui);
+    lo = f - hi - hfsq + s * (hfsq + r);
+    (lo + hi) * IVLN2LO + lo * IVLN2HI + hi * IVLN2HI + k as f32
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/logf.rs.html b/src/libm/math/logf.rs.html new file mode 100644 index 000000000..51f2203d9 --- /dev/null +++ b/src/libm/math/logf.rs.html @@ -0,0 +1,135 @@ +logf.rs.html -- source
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+/* origin: FreeBSD /usr/src/lib/msun/src/e_logf.c */
+/*
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+const LN2_HI: f32 = 6.9313812256e-01; /* 0x3f317180 */
+const LN2_LO: f32 = 9.0580006145e-06; /* 0x3717f7d1 */
+/* |(log(1+s)-log(1-s))/s - Lg(s)| < 2**-34.24 (~[-4.95e-11, 4.97e-11]). */
+const LG1: f32 = 0.66666662693; /*  0xaaaaaa.0p-24*/
+const LG2: f32 = 0.40000972152; /*  0xccce13.0p-25 */
+const LG3: f32 = 0.28498786688; /*  0x91e9ee.0p-25 */
+const LG4: f32 = 0.24279078841; /*  0xf89e26.0p-26 */
+
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn logf(mut x: f32) -> f32 {
+    let x1p25 = f32::from_bits(0x4c000000); // 0x1p25f === 2 ^ 25
+
+    let mut ix = x.to_bits();
+    let mut k = 0i32;
+
+    if (ix < 0x00800000) || ((ix >> 31) != 0) {
+        /* x < 2**-126  */
+        if ix << 1 == 0 {
+            return -1. / (x * x); /* log(+-0)=-inf */
+        }
+        if (ix >> 31) != 0 {
+            return (x - x) / 0.; /* log(-#) = NaN */
+        }
+        /* subnormal number, scale up x */
+        k -= 25;
+        x *= x1p25;
+        ix = x.to_bits();
+    } else if ix >= 0x7f800000 {
+        return x;
+    } else if ix == 0x3f800000 {
+        return 0.;
+    }
+
+    /* reduce x into [sqrt(2)/2, sqrt(2)] */
+    ix += 0x3f800000 - 0x3f3504f3;
+    k += ((ix >> 23) as i32) - 0x7f;
+    ix = (ix & 0x007fffff) + 0x3f3504f3;
+    x = f32::from_bits(ix);
+
+    let f = x - 1.;
+    let s = f / (2. + f);
+    let z = s * s;
+    let w = z * z;
+    let t1 = w * (LG2 + w * LG4);
+    let t2 = z * (LG1 + w * LG3);
+    let r = t2 + t1;
+    let hfsq = 0.5 * f * f;
+    let dk = k as f32;
+    s * (hfsq + r) + dk * LN2_LO - hfsq + f + dk * LN2_HI
+}
+
+
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+
+macro_rules! force_eval {
+    ($e:expr) => {
+        unsafe {
+            ::core::ptr::read_volatile(&$e);
+        }
+    };
+}
+
+#[cfg(not(feature = "checked"))]
+macro_rules! i {
+    ($array:expr, $index:expr) => {
+        unsafe { *$array.get_unchecked($index) }
+    };
+    ($array:expr, $index:expr, = , $rhs:expr) => {
+        unsafe {
+            *$array.get_unchecked_mut($index) = $rhs;
+        }
+    };
+    ($array:expr, $index:expr, += , $rhs:expr) => {
+        unsafe {
+            *$array.get_unchecked_mut($index) += $rhs;
+        }
+    };
+    ($array:expr, $index:expr, -= , $rhs:expr) => {
+        unsafe {
+            *$array.get_unchecked_mut($index) -= $rhs;
+        }
+    };
+    ($array:expr, $index:expr, &= , $rhs:expr) => {
+        unsafe {
+            *$array.get_unchecked_mut($index) &= $rhs;
+        }
+    };
+    ($array:expr, $index:expr, == , $rhs:expr) => {
+        unsafe { *$array.get_unchecked_mut($index) == $rhs }
+    };
+}
+
+#[cfg(feature = "checked")]
+macro_rules! i {
+    ($array:expr, $index:expr) => {
+        *$array.get($index).unwrap()
+    };
+    ($array:expr, $index:expr, = , $rhs:expr) => {
+        *$array.get_mut($index).unwrap() = $rhs;
+    };
+    ($array:expr, $index:expr, -= , $rhs:expr) => {
+        *$array.get_mut($index).unwrap() -= $rhs;
+    };
+    ($array:expr, $index:expr, += , $rhs:expr) => {
+        *$array.get_mut($index).unwrap() += $rhs;
+    };
+    ($array:expr, $index:expr, &= , $rhs:expr) => {
+        *$array.get_mut($index).unwrap() &= $rhs;
+    };
+    ($array:expr, $index:expr, == , $rhs:expr) => {
+        *$array.get_mut($index).unwrap() == $rhs
+    };
+}
+
+macro_rules! llvm_intrinsically_optimized {
+    (#[cfg($($clause:tt)*)] $e:expr) => {
+        #[cfg(all(not(feature = "stable"), $($clause)*))]
+        {
+            if true { // thwart the dead code lint
+                $e
+            }
+        }
+    };
+}
+
+// Public modules
+mod acos;
+mod acosf;
+mod acosh;
+mod acoshf;
+mod asin;
+mod asinf;
+mod asinh;
+mod asinhf;
+mod atan;
+mod atan2;
+mod atan2f;
+mod atanf;
+mod atanh;
+mod atanhf;
+mod cbrt;
+mod cbrtf;
+mod ceil;
+mod ceilf;
+mod copysign;
+mod copysignf;
+mod cos;
+mod cosf;
+mod cosh;
+mod coshf;
+mod erf;
+mod erff;
+mod exp;
+mod exp10;
+mod exp10f;
+mod exp2;
+mod exp2f;
+mod expf;
+mod expm1;
+mod expm1f;
+mod fabs;
+mod fabsf;
+mod fdim;
+mod fdimf;
+mod floor;
+mod floorf;
+mod fma;
+mod fmaf;
+mod fmax;
+mod fmaxf;
+mod fmin;
+mod fminf;
+mod fmod;
+mod fmodf;
+mod frexp;
+mod frexpf;
+mod hypot;
+mod hypotf;
+mod ilogb;
+mod ilogbf;
+mod j0;
+mod j0f;
+mod j1;
+mod j1f;
+mod jn;
+mod jnf;
+mod ldexp;
+mod ldexpf;
+mod lgamma;
+mod lgamma_r;
+mod lgammaf;
+mod lgammaf_r;
+mod log;
+mod log10;
+mod log10f;
+mod log1p;
+mod log1pf;
+mod log2;
+mod log2f;
+mod logf;
+mod modf;
+mod modff;
+mod pow;
+mod powf;
+mod remquo;
+mod remquof;
+mod round;
+mod roundf;
+mod scalbn;
+mod scalbnf;
+mod sin;
+mod sincos;
+mod sincosf;
+mod sinf;
+mod sinh;
+mod sinhf;
+mod sqrt;
+mod sqrtf;
+mod tan;
+mod tanf;
+mod tanh;
+mod tanhf;
+mod tgamma;
+mod tgammaf;
+mod trunc;
+mod truncf;
+
+// Use separated imports instead of {}-grouped imports for easier merging.
+pub use self::acos::acos;
+pub use self::acosf::acosf;
+pub use self::acosh::acosh;
+pub use self::acoshf::acoshf;
+pub use self::asin::asin;
+pub use self::asinf::asinf;
+pub use self::asinh::asinh;
+pub use self::asinhf::asinhf;
+pub use self::atan::atan;
+pub use self::atan2::atan2;
+pub use self::atan2f::atan2f;
+pub use self::atanf::atanf;
+pub use self::atanh::atanh;
+pub use self::atanhf::atanhf;
+pub use self::cbrt::cbrt;
+pub use self::cbrtf::cbrtf;
+pub use self::ceil::ceil;
+pub use self::ceilf::ceilf;
+pub use self::copysign::copysign;
+pub use self::copysignf::copysignf;
+pub use self::cos::cos;
+pub use self::cosf::cosf;
+pub use self::cosh::cosh;
+pub use self::coshf::coshf;
+pub use self::erf::erf;
+pub use self::erf::erfc;
+pub use self::erff::erfcf;
+pub use self::erff::erff;
+pub use self::exp::exp;
+pub use self::exp10::exp10;
+pub use self::exp10f::exp10f;
+pub use self::exp2::exp2;
+pub use self::exp2f::exp2f;
+pub use self::expf::expf;
+pub use self::expm1::expm1;
+pub use self::expm1f::expm1f;
+pub use self::fabs::fabs;
+pub use self::fabsf::fabsf;
+pub use self::fdim::fdim;
+pub use self::fdimf::fdimf;
+pub use self::floor::floor;
+pub use self::floorf::floorf;
+pub use self::fma::fma;
+pub use self::fmaf::fmaf;
+pub use self::fmax::fmax;
+pub use self::fmaxf::fmaxf;
+pub use self::fmin::fmin;
+pub use self::fminf::fminf;
+pub use self::fmod::fmod;
+pub use self::fmodf::fmodf;
+pub use self::frexp::frexp;
+pub use self::frexpf::frexpf;
+pub use self::hypot::hypot;
+pub use self::hypotf::hypotf;
+pub use self::ilogb::ilogb;
+pub use self::ilogbf::ilogbf;
+pub use self::j0::j0;
+pub use self::j0::y0;
+pub use self::j0f::j0f;
+pub use self::j0f::y0f;
+pub use self::j1::j1;
+pub use self::j1::y1;
+pub use self::j1f::j1f;
+pub use self::j1f::y1f;
+pub use self::jn::jn;
+pub use self::jn::yn;
+pub use self::jnf::jnf;
+pub use self::jnf::ynf;
+pub use self::ldexp::ldexp;
+pub use self::ldexpf::ldexpf;
+pub use self::lgamma::lgamma;
+pub use self::lgamma_r::lgamma_r;
+pub use self::lgammaf::lgammaf;
+pub use self::lgammaf_r::lgammaf_r;
+pub use self::log::log;
+pub use self::log10::log10;
+pub use self::log10f::log10f;
+pub use self::log1p::log1p;
+pub use self::log1pf::log1pf;
+pub use self::log2::log2;
+pub use self::log2f::log2f;
+pub use self::logf::logf;
+pub use self::modf::modf;
+pub use self::modff::modff;
+pub use self::pow::pow;
+pub use self::powf::powf;
+pub use self::remquo::remquo;
+pub use self::remquof::remquof;
+pub use self::round::round;
+pub use self::roundf::roundf;
+pub use self::scalbn::scalbn;
+pub use self::scalbnf::scalbnf;
+pub use self::sin::sin;
+pub use self::sincos::sincos;
+pub use self::sincosf::sincosf;
+pub use self::sinf::sinf;
+pub use self::sinh::sinh;
+pub use self::sinhf::sinhf;
+pub use self::sqrt::sqrt;
+pub use self::sqrtf::sqrtf;
+pub use self::tan::tan;
+pub use self::tanf::tanf;
+pub use self::tanh::tanh;
+pub use self::tanhf::tanhf;
+pub use self::tgamma::tgamma;
+pub use self::tgammaf::tgammaf;
+pub use self::trunc::trunc;
+pub use self::truncf::truncf;
+
+// Private modules
+mod expo2;
+mod fenv;
+mod k_cos;
+mod k_cosf;
+mod k_expo2;
+mod k_expo2f;
+mod k_sin;
+mod k_sinf;
+mod k_tan;
+mod k_tanf;
+mod rem_pio2;
+mod rem_pio2_large;
+mod rem_pio2f;
+
+// Private re-imports
+use self::expo2::expo2;
+use self::k_cos::k_cos;
+use self::k_cosf::k_cosf;
+use self::k_expo2::k_expo2;
+use self::k_expo2f::k_expo2f;
+use self::k_sin::k_sin;
+use self::k_sinf::k_sinf;
+use self::k_tan::k_tan;
+use self::k_tanf::k_tanf;
+use self::rem_pio2::rem_pio2;
+use self::rem_pio2_large::rem_pio2_large;
+use self::rem_pio2f::rem_pio2f;
+
+#[inline]
+fn get_high_word(x: f64) -> u32 {
+    (x.to_bits() >> 32) as u32
+}
+
+#[inline]
+fn get_low_word(x: f64) -> u32 {
+    x.to_bits() as u32
+}
+
+#[inline]
+fn with_set_high_word(f: f64, hi: u32) -> f64 {
+    let mut tmp = f.to_bits();
+    tmp &= 0x00000000_ffffffff;
+    tmp |= (hi as u64) << 32;
+    f64::from_bits(tmp)
+}
+
+#[inline]
+fn with_set_low_word(f: f64, lo: u32) -> f64 {
+    let mut tmp = f.to_bits();
+    tmp &= 0xffffffff_00000000;
+    tmp |= lo as u64;
+    f64::from_bits(tmp)
+}
+
+#[inline]
+fn combine_words(hi: u32, lo: u32) -> f64 {
+    f64::from_bits((hi as u64) << 32 | lo as u64)
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/modf.rs.html b/src/libm/math/modf.rs.html new file mode 100644 index 000000000..5853c14e0 --- /dev/null +++ b/src/libm/math/modf.rs.html @@ -0,0 +1,71 @@ +modf.rs.html -- source
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+
+pub fn modf(x: f64) -> (f64, f64) {
+    let rv2: f64;
+    let mut u = x.to_bits();
+    let mask: u64;
+    let e = ((u >> 52 & 0x7ff) as i32) - 0x3ff;
+
+    /* no fractional part */
+    if e >= 52 {
+        rv2 = x;
+        if e == 0x400 && (u << 12) != 0 {
+            /* nan */
+            return (x, rv2);
+        }
+        u &= 1 << 63;
+        return (f64::from_bits(u), rv2);
+    }
+
+    /* no integral part*/
+    if e < 0 {
+        u &= 1 << 63;
+        rv2 = f64::from_bits(u);
+        return (x, rv2);
+    }
+
+    mask = ((!0) >> 12) >> e;
+    if (u & mask) == 0 {
+        rv2 = x;
+        u &= 1 << 63;
+        return (f64::from_bits(u), rv2);
+    }
+    u &= !mask;
+    rv2 = f64::from_bits(u);
+    return (x - rv2, rv2);
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/modff.rs.html b/src/libm/math/modff.rs.html new file mode 100644 index 000000000..d40c0af25 --- /dev/null +++ b/src/libm/math/modff.rs.html @@ -0,0 +1,69 @@ +modff.rs.html -- source
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+
+pub fn modff(x: f32) -> (f32, f32) {
+    let rv2: f32;
+    let mut u: u32 = x.to_bits();
+    let mask: u32;
+    let e = ((u >> 23 & 0xff) as i32) - 0x7f;
+
+    /* no fractional part */
+    if e >= 23 {
+        rv2 = x;
+        if e == 0x80 && (u << 9) != 0 {
+            /* nan */
+            return (x, rv2);
+        }
+        u &= 0x80000000;
+        return (f32::from_bits(u), rv2);
+    }
+    /* no integral part */
+    if e < 0 {
+        u &= 0x80000000;
+        rv2 = f32::from_bits(u);
+        return (x, rv2);
+    }
+
+    mask = 0x007fffff >> e;
+    if (u & mask) == 0 {
+        rv2 = x;
+        u &= 0x80000000;
+        return (f32::from_bits(u), rv2);
+    }
+    u &= !mask;
+    rv2 = f32::from_bits(u);
+    return (x - rv2, rv2);
+}
+
+
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+
+/* origin: FreeBSD /usr/src/lib/msun/src/e_pow.c */
+/*
+ * ====================================================
+ * Copyright (C) 2004 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+// pow(x,y) return x**y
+//
+//                    n
+// Method:  Let x =  2   * (1+f)
+//      1. Compute and return log2(x) in two pieces:
+//              log2(x) = w1 + w2,
+//         where w1 has 53-24 = 29 bit trailing zeros.
+//      2. Perform y*log2(x) = n+y' by simulating muti-precision
+//         arithmetic, where |y'|<=0.5.
+//      3. Return x**y = 2**n*exp(y'*log2)
+//
+// Special cases:
+//      1.  (anything) ** 0  is 1
+//      2.  1 ** (anything)  is 1
+//      3.  (anything except 1) ** NAN is NAN
+//      4.  NAN ** (anything except 0) is NAN
+//      5.  +-(|x| > 1) **  +INF is +INF
+//      6.  +-(|x| > 1) **  -INF is +0
+//      7.  +-(|x| < 1) **  +INF is +0
+//      8.  +-(|x| < 1) **  -INF is +INF
+//      9.  -1          ** +-INF is 1
+//      10. +0 ** (+anything except 0, NAN)               is +0
+//      11. -0 ** (+anything except 0, NAN, odd integer)  is +0
+//      12. +0 ** (-anything except 0, NAN)               is +INF, raise divbyzero
+//      13. -0 ** (-anything except 0, NAN, odd integer)  is +INF, raise divbyzero
+//      14. -0 ** (+odd integer) is -0
+//      15. -0 ** (-odd integer) is -INF, raise divbyzero
+//      16. +INF ** (+anything except 0,NAN) is +INF
+//      17. +INF ** (-anything except 0,NAN) is +0
+//      18. -INF ** (+odd integer) is -INF
+//      19. -INF ** (anything) = -0 ** (-anything), (anything except odd integer)
+//      20. (anything) ** 1 is (anything)
+//      21. (anything) ** -1 is 1/(anything)
+//      22. (-anything) ** (integer) is (-1)**(integer)*(+anything**integer)
+//      23. (-anything except 0 and inf) ** (non-integer) is NAN
+//
+// Accuracy:
+//      pow(x,y) returns x**y nearly rounded. In particular
+//                      pow(integer,integer)
+//      always returns the correct integer provided it is
+//      representable.
+//
+// Constants :
+// The hexadecimal values are the intended ones for the following
+// constants. The decimal values may be used, provided that the
+// compiler will convert from decimal to binary accurately enough
+// to produce the hexadecimal values shown.
+//
+use super::{fabs, get_high_word, scalbn, sqrt, with_set_high_word, with_set_low_word};
+
+const BP: [f64; 2] = [1.0, 1.5];
+const DP_H: [f64; 2] = [0.0, 5.84962487220764160156e-01]; /* 0x3fe2b803_40000000 */
+const DP_L: [f64; 2] = [0.0, 1.35003920212974897128e-08]; /* 0x3E4CFDEB, 0x43CFD006 */
+const TWO53: f64 = 9007199254740992.0; /* 0x43400000_00000000 */
+const HUGE: f64 = 1.0e300;
+const TINY: f64 = 1.0e-300;
+
+// poly coefs for (3/2)*(log(x)-2s-2/3*s**3:
+const L1: f64 = 5.99999999999994648725e-01; /* 0x3fe33333_33333303 */
+const L2: f64 = 4.28571428578550184252e-01; /* 0x3fdb6db6_db6fabff */
+const L3: f64 = 3.33333329818377432918e-01; /* 0x3fd55555_518f264d */
+const L4: f64 = 2.72728123808534006489e-01; /* 0x3fd17460_a91d4101 */
+const L5: f64 = 2.30660745775561754067e-01; /* 0x3fcd864a_93c9db65 */
+const L6: f64 = 2.06975017800338417784e-01; /* 0x3fca7e28_4a454eef */
+const P1: f64 = 1.66666666666666019037e-01; /* 0x3fc55555_5555553e */
+const P2: f64 = -2.77777777770155933842e-03; /* 0xbf66c16c_16bebd93 */
+const P3: f64 = 6.61375632143793436117e-05; /* 0x3f11566a_af25de2c */
+const P4: f64 = -1.65339022054652515390e-06; /* 0xbebbbd41_c5d26bf1 */
+const P5: f64 = 4.13813679705723846039e-08; /* 0x3e663769_72bea4d0 */
+const LG2: f64 = 6.93147180559945286227e-01; /* 0x3fe62e42_fefa39ef */
+const LG2_H: f64 = 6.93147182464599609375e-01; /* 0x3fe62e43_00000000 */
+const LG2_L: f64 = -1.90465429995776804525e-09; /* 0xbe205c61_0ca86c39 */
+const OVT: f64 = 8.0085662595372944372e-017; /* -(1024-log2(ovfl+.5ulp)) */
+const CP: f64 = 9.61796693925975554329e-01; /* 0x3feec709_dc3a03fd =2/(3ln2) */
+const CP_H: f64 = 9.61796700954437255859e-01; /* 0x3feec709_e0000000 =(float)cp */
+const CP_L: f64 = -7.02846165095275826516e-09; /* 0xbe3e2fe0_145b01f5 =tail of cp_h*/
+const IVLN2: f64 = 1.44269504088896338700e+00; /* 0x3ff71547_652b82fe =1/ln2 */
+const IVLN2_H: f64 = 1.44269502162933349609e+00; /* 0x3ff71547_60000000 =24b 1/ln2*/
+const IVLN2_L: f64 = 1.92596299112661746887e-08; /* 0x3e54ae0b_f85ddf44 =1/ln2 tail*/
+
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn pow(x: f64, y: f64) -> f64 {
+    let t1: f64;
+    let t2: f64;
+
+    let (hx, lx): (i32, u32) = ((x.to_bits() >> 32) as i32, x.to_bits() as u32);
+    let (hy, ly): (i32, u32) = ((y.to_bits() >> 32) as i32, y.to_bits() as u32);
+
+    let mut ix: i32 = (hx & 0x7fffffff) as i32;
+    let iy: i32 = (hy & 0x7fffffff) as i32;
+
+    /* x**0 = 1, even if x is NaN */
+    if ((iy as u32) | ly) == 0 {
+        return 1.0;
+    }
+
+    /* 1**y = 1, even if y is NaN */
+    if hx == 0x3ff00000 && lx == 0 {
+        return 1.0;
+    }
+
+    /* NaN if either arg is NaN */
+    if ix > 0x7ff00000
+        || (ix == 0x7ff00000 && lx != 0)
+        || iy > 0x7ff00000
+        || (iy == 0x7ff00000 && ly != 0)
+    {
+        return x + y;
+    }
+
+    /* determine if y is an odd int when x < 0
+     * yisint = 0       ... y is not an integer
+     * yisint = 1       ... y is an odd int
+     * yisint = 2       ... y is an even int
+     */
+    let mut yisint: i32 = 0;
+    let mut k: i32;
+    let mut j: i32;
+    if hx < 0 {
+        if iy >= 0x43400000 {
+            yisint = 2; /* even integer y */
+        } else if iy >= 0x3ff00000 {
+            k = (iy >> 20) - 0x3ff; /* exponent */
+
+            if k > 20 {
+                j = (ly >> (52 - k)) as i32;
+
+                if (j << (52 - k)) == (ly as i32) {
+                    yisint = 2 - (j & 1);
+                }
+            } else if ly == 0 {
+                j = iy >> (20 - k);
+
+                if (j << (20 - k)) == iy {
+                    yisint = 2 - (j & 1);
+                }
+            }
+        }
+    }
+
+    if ly == 0 {
+        /* special value of y */
+        if iy == 0x7ff00000 {
+            /* y is +-inf */
+
+            return if ((ix - 0x3ff00000) | (lx as i32)) == 0 {
+                /* (-1)**+-inf is 1 */
+                1.0
+            } else if ix >= 0x3ff00000 {
+                /* (|x|>1)**+-inf = inf,0 */
+                if hy >= 0 {
+                    y
+                } else {
+                    0.0
+                }
+            } else {
+                /* (|x|<1)**+-inf = 0,inf */
+                if hy >= 0 {
+                    0.0
+                } else {
+                    -y
+                }
+            };
+        }
+
+        if iy == 0x3ff00000 {
+            /* y is +-1 */
+            return if hy >= 0 { x } else { 1.0 / x };
+        }
+
+        if hy == 0x40000000 {
+            /* y is 2 */
+            return x * x;
+        }
+
+        if hy == 0x3fe00000 {
+            /* y is 0.5 */
+            if hx >= 0 {
+                /* x >= +0 */
+                return sqrt(x);
+            }
+        }
+    }
+
+    let mut ax: f64 = fabs(x);
+    if lx == 0 {
+        /* special value of x */
+        if ix == 0x7ff00000 || ix == 0 || ix == 0x3ff00000 {
+            /* x is +-0,+-inf,+-1 */
+            let mut z: f64 = ax;
+
+            if hy < 0 {
+                /* z = (1/|x|) */
+                z = 1.0 / z;
+            }
+
+            if hx < 0 {
+                if ((ix - 0x3ff00000) | yisint) == 0 {
+                    z = (z - z) / (z - z); /* (-1)**non-int is NaN */
+                } else if yisint == 1 {
+                    z = -z; /* (x<0)**odd = -(|x|**odd) */
+                }
+            }
+
+            return z;
+        }
+    }
+
+    let mut s: f64 = 1.0; /* sign of result */
+    if hx < 0 {
+        if yisint == 0 {
+            /* (x<0)**(non-int) is NaN */
+            return (x - x) / (x - x);
+        }
+
+        if yisint == 1 {
+            /* (x<0)**(odd int) */
+            s = -1.0;
+        }
+    }
+
+    /* |y| is HUGE */
+    if iy > 0x41e00000 {
+        /* if |y| > 2**31 */
+        if iy > 0x43f00000 {
+            /* if |y| > 2**64, must o/uflow */
+            if ix <= 0x3fefffff {
+                return if hy < 0 { HUGE * HUGE } else { TINY * TINY };
+            }
+
+            if ix >= 0x3ff00000 {
+                return if hy > 0 { HUGE * HUGE } else { TINY * TINY };
+            }
+        }
+
+        /* over/underflow if x is not close to one */
+        if ix < 0x3fefffff {
+            return if hy < 0 {
+                s * HUGE * HUGE
+            } else {
+                s * TINY * TINY
+            };
+        }
+        if ix > 0x3ff00000 {
+            return if hy > 0 {
+                s * HUGE * HUGE
+            } else {
+                s * TINY * TINY
+            };
+        }
+
+        /* now |1-x| is TINY <= 2**-20, suffice to compute
+        log(x) by x-x^2/2+x^3/3-x^4/4 */
+        let t: f64 = ax - 1.0; /* t has 20 trailing zeros */
+        let w: f64 = (t * t) * (0.5 - t * (0.3333333333333333333333 - t * 0.25));
+        let u: f64 = IVLN2_H * t; /* ivln2_h has 21 sig. bits */
+        let v: f64 = t * IVLN2_L - w * IVLN2;
+        t1 = with_set_low_word(u + v, 0);
+        t2 = v - (t1 - u);
+    } else {
+        // double ss,s2,s_h,s_l,t_h,t_l;
+        let mut n: i32 = 0;
+
+        if ix < 0x00100000 {
+            /* take care subnormal number */
+            ax *= TWO53;
+            n -= 53;
+            ix = get_high_word(ax) as i32;
+        }
+
+        n += (ix >> 20) - 0x3ff;
+        j = ix & 0x000fffff;
+
+        /* determine interval */
+        let k: i32;
+        ix = j | 0x3ff00000; /* normalize ix */
+        if j <= 0x3988E {
+            /* |x|<sqrt(3/2) */
+            k = 0;
+        } else if j < 0xBB67A {
+            /* |x|<sqrt(3)   */
+            k = 1;
+        } else {
+            k = 0;
+            n += 1;
+            ix -= 0x00100000;
+        }
+        ax = with_set_high_word(ax, ix as u32);
+
+        /* compute ss = s_h+s_l = (x-1)/(x+1) or (x-1.5)/(x+1.5) */
+        let u: f64 = ax - BP[k as usize]; /* bp[0]=1.0, bp[1]=1.5 */
+        let v: f64 = 1.0 / (ax + BP[k as usize]);
+        let ss: f64 = u * v;
+        let s_h = with_set_low_word(ss, 0);
+
+        /* t_h=ax+bp[k] High */
+        let t_h: f64 = with_set_high_word(
+            0.0,
+            ((ix as u32 >> 1) | 0x20000000) + 0x00080000 + ((k as u32) << 18),
+        );
+        let t_l: f64 = ax - (t_h - BP[k as usize]);
+        let s_l: f64 = v * ((u - s_h * t_h) - s_h * t_l);
+
+        /* compute log(ax) */
+        let s2: f64 = ss * ss;
+        let mut r: f64 = s2 * s2 * (L1 + s2 * (L2 + s2 * (L3 + s2 * (L4 + s2 * (L5 + s2 * L6)))));
+        r += s_l * (s_h + ss);
+        let s2: f64 = s_h * s_h;
+        let t_h: f64 = with_set_low_word(3.0 + s2 + r, 0);
+        let t_l: f64 = r - ((t_h - 3.0) - s2);
+
+        /* u+v = ss*(1+...) */
+        let u: f64 = s_h * t_h;
+        let v: f64 = s_l * t_h + t_l * ss;
+
+        /* 2/(3log2)*(ss+...) */
+        let p_h: f64 = with_set_low_word(u + v, 0);
+        let p_l = v - (p_h - u);
+        let z_h: f64 = CP_H * p_h; /* cp_h+cp_l = 2/(3*log2) */
+        let z_l: f64 = CP_L * p_h + p_l * CP + DP_L[k as usize];
+
+        /* log2(ax) = (ss+..)*2/(3*log2) = n + dp_h + z_h + z_l */
+        let t: f64 = n as f64;
+        t1 = with_set_low_word(((z_h + z_l) + DP_H[k as usize]) + t, 0);
+        t2 = z_l - (((t1 - t) - DP_H[k as usize]) - z_h);
+    }
+
+    /* split up y into y1+y2 and compute (y1+y2)*(t1+t2) */
+    let y1: f64 = with_set_low_word(y, 0);
+    let p_l: f64 = (y - y1) * t1 + y * t2;
+    let mut p_h: f64 = y1 * t1;
+    let z: f64 = p_l + p_h;
+    let mut j: i32 = (z.to_bits() >> 32) as i32;
+    let i: i32 = z.to_bits() as i32;
+    // let (j, i): (i32, i32) = ((z.to_bits() >> 32) as i32, z.to_bits() as i32);
+
+    if j >= 0x40900000 {
+        /* z >= 1024 */
+        if (j - 0x40900000) | i != 0 {
+            /* if z > 1024 */
+            return s * HUGE * HUGE; /* overflow */
+        }
+
+        if p_l + OVT > z - p_h {
+            return s * HUGE * HUGE; /* overflow */
+        }
+    } else if (j & 0x7fffffff) >= 0x4090cc00 {
+        /* z <= -1075 */
+        // FIXME: instead of abs(j) use unsigned j
+
+        if (((j as u32) - 0xc090cc00) | (i as u32)) != 0 {
+            /* z < -1075 */
+            return s * TINY * TINY; /* underflow */
+        }
+
+        if p_l <= z - p_h {
+            return s * TINY * TINY; /* underflow */
+        }
+    }
+
+    /* compute 2**(p_h+p_l) */
+    let i: i32 = j & (0x7fffffff as i32);
+    k = (i >> 20) - 0x3ff;
+    let mut n: i32 = 0;
+
+    if i > 0x3fe00000 {
+        /* if |z| > 0.5, set n = [z+0.5] */
+        n = j + (0x00100000 >> (k + 1));
+        k = ((n & 0x7fffffff) >> 20) - 0x3ff; /* new k for n */
+        let t: f64 = with_set_high_word(0.0, (n & !(0x000fffff >> k)) as u32);
+        n = ((n & 0x000fffff) | 0x00100000) >> (20 - k);
+        if j < 0 {
+            n = -n;
+        }
+        p_h -= t;
+    }
+
+    let t: f64 = with_set_low_word(p_l + p_h, 0);
+    let u: f64 = t * LG2_H;
+    let v: f64 = (p_l - (t - p_h)) * LG2 + t * LG2_L;
+    let mut z: f64 = u + v;
+    let w: f64 = v - (z - u);
+    let t: f64 = z * z;
+    let t1: f64 = z - t * (P1 + t * (P2 + t * (P3 + t * (P4 + t * P5))));
+    let r: f64 = (z * t1) / (t1 - 2.0) - (w + z * w);
+    z = 1.0 - (r - z);
+    j = get_high_word(z) as i32;
+    j += n << 20;
+
+    if (j >> 20) <= 0 {
+        /* subnormal output */
+        z = scalbn(z, n);
+    } else {
+        z = with_set_high_word(z, j as u32);
+    }
+
+    s * z
+}
+
+#[cfg(test)]
+mod tests {
+    extern crate core;
+
+    use self::core::f64::consts::{E, PI};
+    use self::core::f64::{EPSILON, INFINITY, MAX, MIN, MIN_POSITIVE, NAN, NEG_INFINITY};
+    use super::pow;
+
+    const POS_ZERO: &[f64] = &[0.0];
+    const NEG_ZERO: &[f64] = &[-0.0];
+    const POS_ONE: &[f64] = &[1.0];
+    const NEG_ONE: &[f64] = &[-1.0];
+    const POS_FLOATS: &[f64] = &[99.0 / 70.0, E, PI];
+    const NEG_FLOATS: &[f64] = &[-99.0 / 70.0, -E, -PI];
+    const POS_SMALL_FLOATS: &[f64] = &[(1.0 / 2.0), MIN_POSITIVE, EPSILON];
+    const NEG_SMALL_FLOATS: &[f64] = &[-(1.0 / 2.0), -MIN_POSITIVE, -EPSILON];
+    const POS_EVENS: &[f64] = &[2.0, 6.0, 8.0, 10.0, 22.0, 100.0, MAX];
+    const NEG_EVENS: &[f64] = &[MIN, -100.0, -22.0, -10.0, -8.0, -6.0, -2.0];
+    const POS_ODDS: &[f64] = &[3.0, 7.0];
+    const NEG_ODDS: &[f64] = &[-7.0, -3.0];
+    const NANS: &[f64] = &[NAN];
+    const POS_INF: &[f64] = &[INFINITY];
+    const NEG_INF: &[f64] = &[NEG_INFINITY];
+
+    const ALL: &[&[f64]] = &[
+        POS_ZERO,
+        NEG_ZERO,
+        NANS,
+        NEG_SMALL_FLOATS,
+        POS_SMALL_FLOATS,
+        NEG_FLOATS,
+        POS_FLOATS,
+        NEG_EVENS,
+        POS_EVENS,
+        NEG_ODDS,
+        POS_ODDS,
+        NEG_INF,
+        POS_INF,
+        NEG_ONE,
+        POS_ONE,
+    ];
+    const POS: &[&[f64]] = &[POS_ZERO, POS_ODDS, POS_ONE, POS_FLOATS, POS_EVENS, POS_INF];
+    const NEG: &[&[f64]] = &[NEG_ZERO, NEG_ODDS, NEG_ONE, NEG_FLOATS, NEG_EVENS, NEG_INF];
+
+    fn pow_test(base: f64, exponent: f64, expected: f64) {
+        let res = pow(base, exponent);
+        assert!(
+            if expected.is_nan() {
+                res.is_nan()
+            } else {
+                pow(base, exponent) == expected
+            },
+            "{} ** {} was {} instead of {}",
+            base,
+            exponent,
+            res,
+            expected
+        );
+    }
+
+    fn test_sets_as_base(sets: &[&[f64]], exponent: f64, expected: f64) {
+        sets.iter()
+            .for_each(|s| s.iter().for_each(|val| pow_test(*val, exponent, expected)));
+    }
+
+    fn test_sets_as_exponent(base: f64, sets: &[&[f64]], expected: f64) {
+        sets.iter()
+            .for_each(|s| s.iter().for_each(|val| pow_test(base, *val, expected)));
+    }
+
+    fn test_sets(sets: &[&[f64]], computed: &Fn(f64) -> f64, expected: &Fn(f64) -> f64) {
+        sets.iter().for_each(|s| {
+            s.iter().for_each(|val| {
+                let exp = expected(*val);
+                let res = computed(*val);
+
+                assert!(
+                    if exp.is_nan() {
+                        res.is_nan()
+                    } else {
+                        exp == res
+                    },
+                    "test for {} was {} instead of {}",
+                    val,
+                    res,
+                    exp
+                );
+            })
+        });
+    }
+
+    #[test]
+    fn zero_as_exponent() {
+        test_sets_as_base(ALL, 0.0, 1.0);
+        test_sets_as_base(ALL, -0.0, 1.0);
+    }
+
+    #[test]
+    fn one_as_base() {
+        test_sets_as_exponent(1.0, ALL, 1.0);
+    }
+
+    #[test]
+    fn nan_inputs() {
+        // NAN as the base:
+        // (NAN ^ anything *but 0* should be NAN)
+        test_sets_as_exponent(NAN, &ALL[2..], NAN);
+
+        // NAN as the exponent:
+        // (anything *but 1* ^ NAN should be NAN)
+        test_sets_as_base(&ALL[..(ALL.len() - 2)], NAN, NAN);
+    }
+
+    #[test]
+    fn infinity_as_base() {
+        // Positive Infinity as the base:
+        // (+Infinity ^ positive anything but 0 and NAN should be +Infinity)
+        test_sets_as_exponent(INFINITY, &POS[1..], INFINITY);
+
+        // (+Infinity ^ negative anything except 0 and NAN should be 0.0)
+        test_sets_as_exponent(INFINITY, &NEG[1..], 0.0);
+
+        // Negative Infinity as the base:
+        // (-Infinity ^ positive odd ints should be -Infinity)
+        test_sets_as_exponent(NEG_INFINITY, &[POS_ODDS], NEG_INFINITY);
+
+        // (-Infinity ^ anything but odd ints should be == -0 ^ (-anything))
+        // We can lump in pos/neg odd ints here because they don't seem to
+        // cause panics (div by zero) in release mode (I think).
+        test_sets(ALL, &|v: f64| pow(NEG_INFINITY, v), &|v: f64| pow(-0.0, -v));
+    }
+
+    #[test]
+    fn infinity_as_exponent() {
+        // Positive/Negative base greater than 1:
+        // (pos/neg > 1 ^ Infinity should be Infinity - note this excludes NAN as the base)
+        test_sets_as_base(&ALL[5..(ALL.len() - 2)], INFINITY, INFINITY);
+
+        // (pos/neg > 1 ^ -Infinity should be 0.0)
+        test_sets_as_base(&ALL[5..ALL.len() - 2], NEG_INFINITY, 0.0);
+
+        // Positive/Negative base less than 1:
+        let base_below_one = &[POS_ZERO, NEG_ZERO, NEG_SMALL_FLOATS, POS_SMALL_FLOATS];
+
+        // (pos/neg < 1 ^ Infinity should be 0.0 - this also excludes NAN as the base)
+        test_sets_as_base(base_below_one, INFINITY, 0.0);
+
+        // (pos/neg < 1 ^ -Infinity should be Infinity)
+        test_sets_as_base(base_below_one, NEG_INFINITY, INFINITY);
+
+        // Positive/Negative 1 as the base:
+        // (pos/neg 1 ^ Infinity should be 1)
+        test_sets_as_base(&[NEG_ONE, POS_ONE], INFINITY, 1.0);
+
+        // (pos/neg 1 ^ -Infinity should be 1)
+        test_sets_as_base(&[NEG_ONE, POS_ONE], NEG_INFINITY, 1.0);
+    }
+
+    #[test]
+    fn zero_as_base() {
+        // Positive Zero as the base:
+        // (+0 ^ anything positive but 0 and NAN should be +0)
+        test_sets_as_exponent(0.0, &POS[1..], 0.0);
+
+        // (+0 ^ anything negative but 0 and NAN should be Infinity)
+        // (this should panic because we're dividing by zero)
+        test_sets_as_exponent(0.0, &NEG[1..], INFINITY);
+
+        // Negative Zero as the base:
+        // (-0 ^ anything positive but 0, NAN, and odd ints should be +0)
+        test_sets_as_exponent(-0.0, &POS[3..], 0.0);
+
+        // (-0 ^ anything negative but 0, NAN, and odd ints should be Infinity)
+        // (should panic because of divide by zero)
+        test_sets_as_exponent(-0.0, &NEG[3..], INFINITY);
+
+        // (-0 ^ positive odd ints should be -0)
+        test_sets_as_exponent(-0.0, &[POS_ODDS], -0.0);
+
+        // (-0 ^ negative odd ints should be -Infinity)
+        // (should panic because of divide by zero)
+        test_sets_as_exponent(-0.0, &[NEG_ODDS], NEG_INFINITY);
+    }
+
+    #[test]
+    fn special_cases() {
+        // One as the exponent:
+        // (anything ^ 1 should be anything - i.e. the base)
+        test_sets(ALL, &|v: f64| pow(v, 1.0), &|v: f64| v);
+
+        // Negative One as the exponent:
+        // (anything ^ -1 should be 1/anything)
+        test_sets(ALL, &|v: f64| pow(v, -1.0), &|v: f64| 1.0 / v);
+
+        // Factoring -1 out:
+        // (negative anything ^ integer should be (-1 ^ integer) * (positive anything ^ integer))
+        &[POS_ZERO, NEG_ZERO, POS_ONE, NEG_ONE, POS_EVENS, NEG_EVENS]
+            .iter()
+            .for_each(|int_set| {
+                int_set.iter().for_each(|int| {
+                    test_sets(ALL, &|v: f64| pow(-v, *int), &|v: f64| {
+                        pow(-1.0, *int) * pow(v, *int)
+                    });
+                })
+            });
+
+        // Negative base (imaginary results):
+        // (-anything except 0 and Infinity ^ non-integer should be NAN)
+        &NEG[1..(NEG.len() - 1)].iter().for_each(|set| {
+            set.iter().for_each(|val| {
+                test_sets(&ALL[3..7], &|v: f64| pow(*val, v), &|_| NAN);
+            })
+        });
+    }
+
+    #[test]
+    fn normal_cases() {
+        assert_eq!(pow(2.0, 20.0), (1 << 20) as f64);
+        assert_eq!(pow(-1.0, 9.0), -1.0);
+        assert!(pow(-1.0, 2.2).is_nan());
+        assert!(pow(-1.0, -1.14).is_nan());
+    }
+}
+
+
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+
+/* origin: FreeBSD /usr/src/lib/msun/src/e_powf.c */
+/*
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+use super::{fabsf, scalbnf, sqrtf};
+
+const BP: [f32; 2] = [1.0, 1.5];
+const DP_H: [f32; 2] = [0.0, 5.84960938e-01]; /* 0x3f15c000 */
+const DP_L: [f32; 2] = [0.0, 1.56322085e-06]; /* 0x35d1cfdc */
+const TWO24: f32 = 16777216.0; /* 0x4b800000 */
+const HUGE: f32 = 1.0e30;
+const TINY: f32 = 1.0e-30;
+const L1: f32 = 6.0000002384e-01; /* 0x3f19999a */
+const L2: f32 = 4.2857143283e-01; /* 0x3edb6db7 */
+const L3: f32 = 3.3333334327e-01; /* 0x3eaaaaab */
+const L4: f32 = 2.7272811532e-01; /* 0x3e8ba305 */
+const L5: f32 = 2.3066075146e-01; /* 0x3e6c3255 */
+const L6: f32 = 2.0697501302e-01; /* 0x3e53f142 */
+const P1: f32 = 1.6666667163e-01; /* 0x3e2aaaab */
+const P2: f32 = -2.7777778450e-03; /* 0xbb360b61 */
+const P3: f32 = 6.6137559770e-05; /* 0x388ab355 */
+const P4: f32 = -1.6533901999e-06; /* 0xb5ddea0e */
+const P5: f32 = 4.1381369442e-08; /* 0x3331bb4c */
+const LG2: f32 = 6.9314718246e-01; /* 0x3f317218 */
+const LG2_H: f32 = 6.93145752e-01; /* 0x3f317200 */
+const LG2_L: f32 = 1.42860654e-06; /* 0x35bfbe8c */
+const OVT: f32 = 4.2995665694e-08; /* -(128-log2(ovfl+.5ulp)) */
+const CP: f32 = 9.6179670095e-01; /* 0x3f76384f =2/(3ln2) */
+const CP_H: f32 = 9.6191406250e-01; /* 0x3f764000 =12b cp */
+const CP_L: f32 = -1.1736857402e-04; /* 0xb8f623c6 =tail of cp_h */
+const IVLN2: f32 = 1.4426950216e+00;
+const IVLN2_H: f32 = 1.4426879883e+00;
+const IVLN2_L: f32 = 7.0526075433e-06;
+
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn powf(x: f32, y: f32) -> f32 {
+    let mut z: f32;
+    let mut ax: f32;
+    let z_h: f32;
+    let z_l: f32;
+    let mut p_h: f32;
+    let mut p_l: f32;
+    let y1: f32;
+    let mut t1: f32;
+    let t2: f32;
+    let mut r: f32;
+    let s: f32;
+    let mut sn: f32;
+    let mut t: f32;
+    let mut u: f32;
+    let mut v: f32;
+    let mut w: f32;
+    let i: i32;
+    let mut j: i32;
+    let mut k: i32;
+    let mut yisint: i32;
+    let mut n: i32;
+    let hx: i32;
+    let hy: i32;
+    let mut ix: i32;
+    let iy: i32;
+    let mut is: i32;
+
+    hx = x.to_bits() as i32;
+    hy = y.to_bits() as i32;
+
+    ix = hx & 0x7fffffff;
+    iy = hy & 0x7fffffff;
+
+    /* x**0 = 1, even if x is NaN */
+    if iy == 0 {
+        return 1.0;
+    }
+
+    /* 1**y = 1, even if y is NaN */
+    if hx == 0x3f800000 {
+        return 1.0;
+    }
+
+    /* NaN if either arg is NaN */
+    if ix > 0x7f800000 || iy > 0x7f800000 {
+        return x + y;
+    }
+
+    /* determine if y is an odd int when x < 0
+     * yisint = 0       ... y is not an integer
+     * yisint = 1       ... y is an odd int
+     * yisint = 2       ... y is an even int
+     */
+    yisint = 0;
+    if hx < 0 {
+        if iy >= 0x4b800000 {
+            yisint = 2; /* even integer y */
+        } else if iy >= 0x3f800000 {
+            k = (iy >> 23) - 0x7f; /* exponent */
+            j = iy >> (23 - k);
+            if (j << (23 - k)) == iy {
+                yisint = 2 - (j & 1);
+            }
+        }
+    }
+
+    /* special value of y */
+    if iy == 0x7f800000 {
+        /* y is +-inf */
+        if ix == 0x3f800000 {
+            /* (-1)**+-inf is 1 */
+            return 1.0;
+        } else if ix > 0x3f800000 {
+            /* (|x|>1)**+-inf = inf,0 */
+            return if hy >= 0 { y } else { 0.0 };
+        } else {
+            /* (|x|<1)**+-inf = 0,inf */
+            return if hy >= 0 { 0.0 } else { -y };
+        }
+    }
+    if iy == 0x3f800000 {
+        /* y is +-1 */
+        return if hy >= 0 { x } else { 1.0 / x };
+    }
+
+    if hy == 0x40000000 {
+        /* y is 2 */
+        return x * x;
+    }
+
+    if hy == 0x3f000000
+       /* y is  0.5 */
+       && hx >= 0
+    {
+        /* x >= +0 */
+        return sqrtf(x);
+    }
+
+    ax = fabsf(x);
+    /* special value of x */
+    if ix == 0x7f800000 || ix == 0 || ix == 0x3f800000 {
+        /* x is +-0,+-inf,+-1 */
+        z = ax;
+        if hy < 0 {
+            /* z = (1/|x|) */
+            z = 1.0 / z;
+        }
+
+        if hx < 0 {
+            if ((ix - 0x3f800000) | yisint) == 0 {
+                z = (z - z) / (z - z); /* (-1)**non-int is NaN */
+            } else if yisint == 1 {
+                z = -z; /* (x<0)**odd = -(|x|**odd) */
+            }
+        }
+        return z;
+    }
+
+    sn = 1.0; /* sign of result */
+    if hx < 0 {
+        if yisint == 0 {
+            /* (x<0)**(non-int) is NaN */
+            return (x - x) / (x - x);
+        }
+
+        if yisint == 1 {
+            /* (x<0)**(odd int) */
+            sn = -1.0;
+        }
+    }
+
+    /* |y| is HUGE */
+    if iy > 0x4d000000 {
+        /* if |y| > 2**27 */
+        /* over/underflow if x is not close to one */
+        if ix < 0x3f7ffff8 {
+            return if hy < 0 {
+                sn * HUGE * HUGE
+            } else {
+                sn * TINY * TINY
+            };
+        }
+
+        if ix > 0x3f800007 {
+            return if hy > 0 {
+                sn * HUGE * HUGE
+            } else {
+                sn * TINY * TINY
+            };
+        }
+
+        /* now |1-x| is TINY <= 2**-20, suffice to compute
+        log(x) by x-x^2/2+x^3/3-x^4/4 */
+        t = ax - 1.; /* t has 20 trailing zeros */
+        w = (t * t) * (0.5 - t * (0.333333333333 - t * 0.25));
+        u = IVLN2_H * t; /* IVLN2_H has 16 sig. bits */
+        v = t * IVLN2_L - w * IVLN2;
+        t1 = u + v;
+        is = t1.to_bits() as i32;
+        t1 = f32::from_bits(is as u32 & 0xfffff000);
+        t2 = v - (t1 - u);
+    } else {
+        let mut s2: f32;
+        let mut s_h: f32;
+        let s_l: f32;
+        let mut t_h: f32;
+        let mut t_l: f32;
+
+        n = 0;
+        /* take care subnormal number */
+        if ix < 0x00800000 {
+            ax *= TWO24;
+            n -= 24;
+            ix = ax.to_bits() as i32;
+        }
+        n += ((ix) >> 23) - 0x7f;
+        j = ix & 0x007fffff;
+        /* determine interval */
+        ix = j | 0x3f800000; /* normalize ix */
+        if j <= 0x1cc471 {
+            /* |x|<sqrt(3/2) */
+            k = 0;
+        } else if j < 0x5db3d7 {
+            /* |x|<sqrt(3)   */
+            k = 1;
+        } else {
+            k = 0;
+            n += 1;
+            ix -= 0x00800000;
+        }
+        ax = f32::from_bits(ix as u32);
+
+        /* compute s = s_h+s_l = (x-1)/(x+1) or (x-1.5)/(x+1.5) */
+        u = ax - BP[k as usize]; /* bp[0]=1.0, bp[1]=1.5 */
+        v = 1.0 / (ax + BP[k as usize]);
+        s = u * v;
+        s_h = s;
+        is = s_h.to_bits() as i32;
+        s_h = f32::from_bits(is as u32 & 0xfffff000);
+        /* t_h=ax+bp[k] High */
+        is = (((ix as u32 >> 1) & 0xfffff000) | 0x20000000) as i32;
+        t_h = f32::from_bits(is as u32 + 0x00400000 + ((k as u32) << 21));
+        t_l = ax - (t_h - BP[k as usize]);
+        s_l = v * ((u - s_h * t_h) - s_h * t_l);
+        /* compute log(ax) */
+        s2 = s * s;
+        r = s2 * s2 * (L1 + s2 * (L2 + s2 * (L3 + s2 * (L4 + s2 * (L5 + s2 * L6)))));
+        r += s_l * (s_h + s);
+        s2 = s_h * s_h;
+        t_h = 3.0 + s2 + r;
+        is = t_h.to_bits() as i32;
+        t_h = f32::from_bits(is as u32 & 0xfffff000);
+        t_l = r - ((t_h - 3.0) - s2);
+        /* u+v = s*(1+...) */
+        u = s_h * t_h;
+        v = s_l * t_h + t_l * s;
+        /* 2/(3log2)*(s+...) */
+        p_h = u + v;
+        is = p_h.to_bits() as i32;
+        p_h = f32::from_bits(is as u32 & 0xfffff000);
+        p_l = v - (p_h - u);
+        z_h = CP_H * p_h; /* cp_h+cp_l = 2/(3*log2) */
+        z_l = CP_L * p_h + p_l * CP + DP_L[k as usize];
+        /* log2(ax) = (s+..)*2/(3*log2) = n + dp_h + z_h + z_l */
+        t = n as f32;
+        t1 = ((z_h + z_l) + DP_H[k as usize]) + t;
+        is = t1.to_bits() as i32;
+        t1 = f32::from_bits(is as u32 & 0xfffff000);
+        t2 = z_l - (((t1 - t) - DP_H[k as usize]) - z_h);
+    };
+
+    /* split up y into y1+y2 and compute (y1+y2)*(t1+t2) */
+    is = y.to_bits() as i32;
+    y1 = f32::from_bits(is as u32 & 0xfffff000);
+    p_l = (y - y1) * t1 + y * t2;
+    p_h = y1 * t1;
+    z = p_l + p_h;
+    j = z.to_bits() as i32;
+    if j > 0x43000000 {
+        /* if z > 128 */
+        return sn * HUGE * HUGE; /* overflow */
+    } else if j == 0x43000000 {
+        /* if z == 128 */
+        if p_l + OVT > z - p_h {
+            return sn * HUGE * HUGE; /* overflow */
+        }
+    } else if (j & 0x7fffffff) > 0x43160000 {
+        /* z < -150 */
+        // FIXME: check should be  (uint32_t)j > 0xc3160000
+        return sn * TINY * TINY; /* underflow */
+    } else if j as u32 == 0xc3160000
+              /* z == -150 */
+              && p_l <= z - p_h
+    {
+        return sn * TINY * TINY; /* underflow */
+    }
+
+    /*
+     * compute 2**(p_h+p_l)
+     */
+    i = j & 0x7fffffff;
+    k = (i >> 23) - 0x7f;
+    n = 0;
+    if i > 0x3f000000 {
+        /* if |z| > 0.5, set n = [z+0.5] */
+        n = j + (0x00800000 >> (k + 1));
+        k = ((n & 0x7fffffff) >> 23) - 0x7f; /* new k for n */
+        t = f32::from_bits(n as u32 & !(0x007fffff >> k));
+        n = ((n & 0x007fffff) | 0x00800000) >> (23 - k);
+        if j < 0 {
+            n = -n;
+        }
+        p_h -= t;
+    }
+    t = p_l + p_h;
+    is = t.to_bits() as i32;
+    t = f32::from_bits(is as u32 & 0xffff8000);
+    u = t * LG2_H;
+    v = (p_l - (t - p_h)) * LG2 + t * LG2_L;
+    z = u + v;
+    w = v - (z - u);
+    t = z * z;
+    t1 = z - t * (P1 + t * (P2 + t * (P3 + t * (P4 + t * P5))));
+    r = (z * t1) / (t1 - 2.0) - (w + z * w);
+    z = 1.0 - (r - z);
+    j = z.to_bits() as i32;
+    j += n << 23;
+    if (j >> 23) <= 0 {
+        /* subnormal output */
+        z = scalbnf(z, n);
+    } else {
+        z = f32::from_bits(j as u32);
+    }
+    sn * z
+}
+
+
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+
+// origin: FreeBSD /usr/src/lib/msun/src/e_rem_pio2.c
+//
+// ====================================================
+// Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+//
+// Developed at SunPro, a Sun Microsystems, Inc. business.
+// Permission to use, copy, modify, and distribute this
+// software is freely granted, provided that this notice
+// is preserved.
+// ====================================================
+//
+// Optimized by Bruce D. Evans. */
+use super::rem_pio2_large;
+
+// #if FLT_EVAL_METHOD==0 || FLT_EVAL_METHOD==1
+// #define EPS DBL_EPSILON
+const EPS: f64 = 2.2204460492503131e-16;
+// #elif FLT_EVAL_METHOD==2
+// #define EPS LDBL_EPSILON
+// #endif
+
+// TODO: Support FLT_EVAL_METHOD?
+
+const TO_INT: f64 = 1.5 / EPS;
+/// 53 bits of 2/pi
+const INV_PIO2: f64 = 6.36619772367581382433e-01; /* 0x3FE45F30, 0x6DC9C883 */
+/// first 33 bits of pi/2
+const PIO2_1: f64 = 1.57079632673412561417e+00; /* 0x3FF921FB, 0x54400000 */
+/// pi/2 - PIO2_1
+const PIO2_1T: f64 = 6.07710050650619224932e-11; /* 0x3DD0B461, 0x1A626331 */
+/// second 33 bits of pi/2
+const PIO2_2: f64 = 6.07710050630396597660e-11; /* 0x3DD0B461, 0x1A600000 */
+/// pi/2 - (PIO2_1+PIO2_2)
+const PIO2_2T: f64 = 2.02226624879595063154e-21; /* 0x3BA3198A, 0x2E037073 */
+/// third 33 bits of pi/2
+const PIO2_3: f64 = 2.02226624871116645580e-21; /* 0x3BA3198A, 0x2E000000 */
+/// pi/2 - (PIO2_1+PIO2_2+PIO2_3)
+const PIO2_3T: f64 = 8.47842766036889956997e-32; /* 0x397B839A, 0x252049C1 */
+
+// return the remainder of x rem pi/2 in y[0]+y[1]
+// use rem_pio2_large() for large x
+//
+// caller must handle the case when reduction is not needed: |x| ~<= pi/4 */
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub(crate) fn rem_pio2(x: f64) -> (i32, f64, f64) {
+    let x1p24 = f64::from_bits(0x4170000000000000);
+
+    let sign = (f64::to_bits(x) >> 63) as i32;
+    let ix = (f64::to_bits(x) >> 32) as u32 & 0x7fffffff;
+
+    #[inline]
+    fn medium(x: f64, ix: u32) -> (i32, f64, f64) {
+        /* rint(x/(pi/2)), Assume round-to-nearest. */
+        let f_n = x as f64 * INV_PIO2 + TO_INT - TO_INT;
+        let n = f_n as i32;
+        let mut r = x - f_n * PIO2_1;
+        let mut w = f_n * PIO2_1T; /* 1st round, good to 85 bits */
+        let mut y0 = r - w;
+        let ui = f64::to_bits(y0);
+        let ey = (ui >> 52) as i32 & 0x7ff;
+        let ex = (ix >> 20) as i32;
+        if ex - ey > 16 {
+            /* 2nd round, good to 118 bits */
+            let t = r;
+            w = f_n * PIO2_2;
+            r = t - w;
+            w = f_n * PIO2_2T - ((t - r) - w);
+            y0 = r - w;
+            let ey = (f64::to_bits(y0) >> 52) as i32 & 0x7ff;
+            if ex - ey > 49 {
+                /* 3rd round, good to 151 bits, covers all cases */
+                let t = r;
+                w = f_n * PIO2_3;
+                r = t - w;
+                w = f_n * PIO2_3T - ((t - r) - w);
+                y0 = r - w;
+            }
+        }
+        let y1 = (r - y0) - w;
+        (n, y0, y1)
+    }
+
+    if ix <= 0x400f6a7a {
+        /* |x| ~<= 5pi/4 */
+        if (ix & 0xfffff) == 0x921fb {
+            /* |x| ~= pi/2 or 2pi/2 */
+            return medium(x, ix); /* cancellation -- use medium case */
+        }
+        if ix <= 0x4002d97c {
+            /* |x| ~<= 3pi/4 */
+            if sign == 0 {
+                let z = x - PIO2_1; /* one round good to 85 bits */
+                let y0 = z - PIO2_1T;
+                let y1 = (z - y0) - PIO2_1T;
+                return (1, y0, y1);
+            } else {
+                let z = x + PIO2_1;
+                let y0 = z + PIO2_1T;
+                let y1 = (z - y0) + PIO2_1T;
+                return (-1, y0, y1);
+            }
+        } else if sign == 0 {
+            let z = x - 2.0 * PIO2_1;
+            let y0 = z - 2.0 * PIO2_1T;
+            let y1 = (z - y0) - 2.0 * PIO2_1T;
+            return (2, y0, y1);
+        } else {
+            let z = x + 2.0 * PIO2_1;
+            let y0 = z + 2.0 * PIO2_1T;
+            let y1 = (z - y0) + 2.0 * PIO2_1T;
+            return (-2, y0, y1);
+        }
+    }
+    if ix <= 0x401c463b {
+        /* |x| ~<= 9pi/4 */
+        if ix <= 0x4015fdbc {
+            /* |x| ~<= 7pi/4 */
+            if ix == 0x4012d97c {
+                /* |x| ~= 3pi/2 */
+                return medium(x, ix);
+            }
+            if sign == 0 {
+                let z = x - 3.0 * PIO2_1;
+                let y0 = z - 3.0 * PIO2_1T;
+                let y1 = (z - y0) - 3.0 * PIO2_1T;
+                return (3, y0, y1);
+            } else {
+                let z = x + 3.0 * PIO2_1;
+                let y0 = z + 3.0 * PIO2_1T;
+                let y1 = (z - y0) + 3.0 * PIO2_1T;
+                return (-3, y0, y1);
+            }
+        } else {
+            if ix == 0x401921fb {
+                /* |x| ~= 4pi/2 */
+                return medium(x, ix);
+            }
+            if sign == 0 {
+                let z = x - 4.0 * PIO2_1;
+                let y0 = z - 4.0 * PIO2_1T;
+                let y1 = (z - y0) - 4.0 * PIO2_1T;
+                return (4, y0, y1);
+            } else {
+                let z = x + 4.0 * PIO2_1;
+                let y0 = z + 4.0 * PIO2_1T;
+                let y1 = (z - y0) + 4.0 * PIO2_1T;
+                return (-4, y0, y1);
+            }
+        }
+    }
+    if ix < 0x413921fb {
+        /* |x| ~< 2^20*(pi/2), medium size */
+        return medium(x, ix);
+    }
+    /*
+     * all other (large) arguments
+     */
+    if ix >= 0x7ff00000 {
+        /* x is inf or NaN */
+        let y0 = x - x;
+        let y1 = y0;
+        return (0, y0, y1);
+    }
+    /* set z = scalbn(|x|,-ilogb(x)+23) */
+    let mut ui = f64::to_bits(x);
+    ui &= (!1) >> 12;
+    ui |= (0x3ff + 23) << 52;
+    let mut z = f64::from_bits(ui);
+    let mut tx = [0.0; 3];
+    for i in 0..2 {
+        tx[i] = z as i32 as f64;
+        z = (z - tx[i]) * x1p24;
+    }
+    tx[2] = z;
+    /* skip zero terms, first term is non-zero */
+    let mut i = 2;
+    while i != 0 && tx[i] == 0.0 {
+        i -= 1;
+    }
+    let mut ty = [0.0; 3];
+    let n = rem_pio2_large(&tx[..=i], &mut ty, ((ix >> 20) - (0x3ff + 23)) as i32, 1);
+    if sign != 0 {
+        return (-n, -ty[0], -ty[1]);
+    }
+    (n, ty[0], ty[1])
+}
+
+#[test]
+fn test_near_pi() {
+    assert_eq!(
+        rem_pio2(3.141592025756836),
+        (2, -6.278329573009626e-7, -2.1125998133974653e-23)
+    );
+    assert_eq!(
+        rem_pio2(3.141592033207416),
+        (2, -6.20382377148128e-7, -2.1125998133974653e-23)
+    );
+    assert_eq!(
+        rem_pio2(3.141592144966125),
+        (2, -5.086236681942706e-7, -2.1125998133974653e-23)
+    );
+    assert_eq!(
+        rem_pio2(3.141592979431152),
+        (2, 3.2584135866119817e-7, -2.1125998133974653e-23)
+    );
+}
+
+
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+
+#![allow(unused_unsafe)]
+/* origin: FreeBSD /usr/src/lib/msun/src/k_rem_pio2.c */
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunSoft, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+use super::floor;
+use super::scalbn;
+
+// initial value for jk
+const INIT_JK: [usize; 4] = [3, 4, 4, 6];
+
+// Table of constants for 2/pi, 396 Hex digits (476 decimal) of 2/pi
+//
+//              integer array, contains the (24*i)-th to (24*i+23)-th
+//              bit of 2/pi after binary point. The corresponding
+//              floating value is
+//
+//                      ipio2[i] * 2^(-24(i+1)).
+//
+// NB: This table must have at least (e0-3)/24 + jk terms.
+//     For quad precision (e0 <= 16360, jk = 6), this is 686.
+#[cfg(target_pointer_width = "32")]
+const IPIO2: [i32; 66] = [
+    0xA2F983, 0x6E4E44, 0x1529FC, 0x2757D1, 0xF534DD, 0xC0DB62, 0x95993C, 0x439041, 0xFE5163,
+    0xABDEBB, 0xC561B7, 0x246E3A, 0x424DD2, 0xE00649, 0x2EEA09, 0xD1921C, 0xFE1DEB, 0x1CB129,
+    0xA73EE8, 0x8235F5, 0x2EBB44, 0x84E99C, 0x7026B4, 0x5F7E41, 0x3991D6, 0x398353, 0x39F49C,
+    0x845F8B, 0xBDF928, 0x3B1FF8, 0x97FFDE, 0x05980F, 0xEF2F11, 0x8B5A0A, 0x6D1F6D, 0x367ECF,
+    0x27CB09, 0xB74F46, 0x3F669E, 0x5FEA2D, 0x7527BA, 0xC7EBE5, 0xF17B3D, 0x0739F7, 0x8A5292,
+    0xEA6BFB, 0x5FB11F, 0x8D5D08, 0x560330, 0x46FC7B, 0x6BABF0, 0xCFBC20, 0x9AF436, 0x1DA9E3,
+    0x91615E, 0xE61B08, 0x659985, 0x5F14A0, 0x68408D, 0xFFD880, 0x4D7327, 0x310606, 0x1556CA,
+    0x73A8C9, 0x60E27B, 0xC08C6B,
+];
+
+#[cfg(target_pointer_width = "64")]
+const IPIO2: [i32; 690] = [
+    0xA2F983, 0x6E4E44, 0x1529FC, 0x2757D1, 0xF534DD, 0xC0DB62, 0x95993C, 0x439041, 0xFE5163,
+    0xABDEBB, 0xC561B7, 0x246E3A, 0x424DD2, 0xE00649, 0x2EEA09, 0xD1921C, 0xFE1DEB, 0x1CB129,
+    0xA73EE8, 0x8235F5, 0x2EBB44, 0x84E99C, 0x7026B4, 0x5F7E41, 0x3991D6, 0x398353, 0x39F49C,
+    0x845F8B, 0xBDF928, 0x3B1FF8, 0x97FFDE, 0x05980F, 0xEF2F11, 0x8B5A0A, 0x6D1F6D, 0x367ECF,
+    0x27CB09, 0xB74F46, 0x3F669E, 0x5FEA2D, 0x7527BA, 0xC7EBE5, 0xF17B3D, 0x0739F7, 0x8A5292,
+    0xEA6BFB, 0x5FB11F, 0x8D5D08, 0x560330, 0x46FC7B, 0x6BABF0, 0xCFBC20, 0x9AF436, 0x1DA9E3,
+    0x91615E, 0xE61B08, 0x659985, 0x5F14A0, 0x68408D, 0xFFD880, 0x4D7327, 0x310606, 0x1556CA,
+    0x73A8C9, 0x60E27B, 0xC08C6B, 0x47C419, 0xC367CD, 0xDCE809, 0x2A8359, 0xC4768B, 0x961CA6,
+    0xDDAF44, 0xD15719, 0x053EA5, 0xFF0705, 0x3F7E33, 0xE832C2, 0xDE4F98, 0x327DBB, 0xC33D26,
+    0xEF6B1E, 0x5EF89F, 0x3A1F35, 0xCAF27F, 0x1D87F1, 0x21907C, 0x7C246A, 0xFA6ED5, 0x772D30,
+    0x433B15, 0xC614B5, 0x9D19C3, 0xC2C4AD, 0x414D2C, 0x5D000C, 0x467D86, 0x2D71E3, 0x9AC69B,
+    0x006233, 0x7CD2B4, 0x97A7B4, 0xD55537, 0xF63ED7, 0x1810A3, 0xFC764D, 0x2A9D64, 0xABD770,
+    0xF87C63, 0x57B07A, 0xE71517, 0x5649C0, 0xD9D63B, 0x3884A7, 0xCB2324, 0x778AD6, 0x23545A,
+    0xB91F00, 0x1B0AF1, 0xDFCE19, 0xFF319F, 0x6A1E66, 0x615799, 0x47FBAC, 0xD87F7E, 0xB76522,
+    0x89E832, 0x60BFE6, 0xCDC4EF, 0x09366C, 0xD43F5D, 0xD7DE16, 0xDE3B58, 0x929BDE, 0x2822D2,
+    0xE88628, 0x4D58E2, 0x32CAC6, 0x16E308, 0xCB7DE0, 0x50C017, 0xA71DF3, 0x5BE018, 0x34132E,
+    0x621283, 0x014883, 0x5B8EF5, 0x7FB0AD, 0xF2E91E, 0x434A48, 0xD36710, 0xD8DDAA, 0x425FAE,
+    0xCE616A, 0xA4280A, 0xB499D3, 0xF2A606, 0x7F775C, 0x83C2A3, 0x883C61, 0x78738A, 0x5A8CAF,
+    0xBDD76F, 0x63A62D, 0xCBBFF4, 0xEF818D, 0x67C126, 0x45CA55, 0x36D9CA, 0xD2A828, 0x8D61C2,
+    0x77C912, 0x142604, 0x9B4612, 0xC459C4, 0x44C5C8, 0x91B24D, 0xF31700, 0xAD43D4, 0xE54929,
+    0x10D5FD, 0xFCBE00, 0xCC941E, 0xEECE70, 0xF53E13, 0x80F1EC, 0xC3E7B3, 0x28F8C7, 0x940593,
+    0x3E71C1, 0xB3092E, 0xF3450B, 0x9C1288, 0x7B20AB, 0x9FB52E, 0xC29247, 0x2F327B, 0x6D550C,
+    0x90A772, 0x1FE76B, 0x96CB31, 0x4A1679, 0xE27941, 0x89DFF4, 0x9794E8, 0x84E6E2, 0x973199,
+    0x6BED88, 0x365F5F, 0x0EFDBB, 0xB49A48, 0x6CA467, 0x427271, 0x325D8D, 0xB8159F, 0x09E5BC,
+    0x25318D, 0x3974F7, 0x1C0530, 0x010C0D, 0x68084B, 0x58EE2C, 0x90AA47, 0x02E774, 0x24D6BD,
+    0xA67DF7, 0x72486E, 0xEF169F, 0xA6948E, 0xF691B4, 0x5153D1, 0xF20ACF, 0x339820, 0x7E4BF5,
+    0x6863B2, 0x5F3EDD, 0x035D40, 0x7F8985, 0x295255, 0xC06437, 0x10D86D, 0x324832, 0x754C5B,
+    0xD4714E, 0x6E5445, 0xC1090B, 0x69F52A, 0xD56614, 0x9D0727, 0x50045D, 0xDB3BB4, 0xC576EA,
+    0x17F987, 0x7D6B49, 0xBA271D, 0x296996, 0xACCCC6, 0x5414AD, 0x6AE290, 0x89D988, 0x50722C,
+    0xBEA404, 0x940777, 0x7030F3, 0x27FC00, 0xA871EA, 0x49C266, 0x3DE064, 0x83DD97, 0x973FA3,
+    0xFD9443, 0x8C860D, 0xDE4131, 0x9D3992, 0x8C70DD, 0xE7B717, 0x3BDF08, 0x2B3715, 0xA0805C,
+    0x93805A, 0x921110, 0xD8E80F, 0xAF806C, 0x4BFFDB, 0x0F9038, 0x761859, 0x15A562, 0xBBCB61,
+    0xB989C7, 0xBD4010, 0x04F2D2, 0x277549, 0xF6B6EB, 0xBB22DB, 0xAA140A, 0x2F2689, 0x768364,
+    0x333B09, 0x1A940E, 0xAA3A51, 0xC2A31D, 0xAEEDAF, 0x12265C, 0x4DC26D, 0x9C7A2D, 0x9756C0,
+    0x833F03, 0xF6F009, 0x8C402B, 0x99316D, 0x07B439, 0x15200C, 0x5BC3D8, 0xC492F5, 0x4BADC6,
+    0xA5CA4E, 0xCD37A7, 0x36A9E6, 0x9492AB, 0x6842DD, 0xDE6319, 0xEF8C76, 0x528B68, 0x37DBFC,
+    0xABA1AE, 0x3115DF, 0xA1AE00, 0xDAFB0C, 0x664D64, 0xB705ED, 0x306529, 0xBF5657, 0x3AFF47,
+    0xB9F96A, 0xF3BE75, 0xDF9328, 0x3080AB, 0xF68C66, 0x15CB04, 0x0622FA, 0x1DE4D9, 0xA4B33D,
+    0x8F1B57, 0x09CD36, 0xE9424E, 0xA4BE13, 0xB52333, 0x1AAAF0, 0xA8654F, 0xA5C1D2, 0x0F3F0B,
+    0xCD785B, 0x76F923, 0x048B7B, 0x721789, 0x53A6C6, 0xE26E6F, 0x00EBEF, 0x584A9B, 0xB7DAC4,
+    0xBA66AA, 0xCFCF76, 0x1D02D1, 0x2DF1B1, 0xC1998C, 0x77ADC3, 0xDA4886, 0xA05DF7, 0xF480C6,
+    0x2FF0AC, 0x9AECDD, 0xBC5C3F, 0x6DDED0, 0x1FC790, 0xB6DB2A, 0x3A25A3, 0x9AAF00, 0x9353AD,
+    0x0457B6, 0xB42D29, 0x7E804B, 0xA707DA, 0x0EAA76, 0xA1597B, 0x2A1216, 0x2DB7DC, 0xFDE5FA,
+    0xFEDB89, 0xFDBE89, 0x6C76E4, 0xFCA906, 0x70803E, 0x156E85, 0xFF87FD, 0x073E28, 0x336761,
+    0x86182A, 0xEABD4D, 0xAFE7B3, 0x6E6D8F, 0x396795, 0x5BBF31, 0x48D784, 0x16DF30, 0x432DC7,
+    0x356125, 0xCE70C9, 0xB8CB30, 0xFD6CBF, 0xA200A4, 0xE46C05, 0xA0DD5A, 0x476F21, 0xD21262,
+    0x845CB9, 0x496170, 0xE0566B, 0x015299, 0x375550, 0xB7D51E, 0xC4F133, 0x5F6E13, 0xE4305D,
+    0xA92E85, 0xC3B21D, 0x3632A1, 0xA4B708, 0xD4B1EA, 0x21F716, 0xE4698F, 0x77FF27, 0x80030C,
+    0x2D408D, 0xA0CD4F, 0x99A520, 0xD3A2B3, 0x0A5D2F, 0x42F9B4, 0xCBDA11, 0xD0BE7D, 0xC1DB9B,
+    0xBD17AB, 0x81A2CA, 0x5C6A08, 0x17552E, 0x550027, 0xF0147F, 0x8607E1, 0x640B14, 0x8D4196,
+    0xDEBE87, 0x2AFDDA, 0xB6256B, 0x34897B, 0xFEF305, 0x9EBFB9, 0x4F6A68, 0xA82A4A, 0x5AC44F,
+    0xBCF82D, 0x985AD7, 0x95C7F4, 0x8D4D0D, 0xA63A20, 0x5F57A4, 0xB13F14, 0x953880, 0x0120CC,
+    0x86DD71, 0xB6DEC9, 0xF560BF, 0x11654D, 0x6B0701, 0xACB08C, 0xD0C0B2, 0x485551, 0x0EFB1E,
+    0xC37295, 0x3B06A3, 0x3540C0, 0x7BDC06, 0xCC45E0, 0xFA294E, 0xC8CAD6, 0x41F3E8, 0xDE647C,
+    0xD8649B, 0x31BED9, 0xC397A4, 0xD45877, 0xC5E369, 0x13DAF0, 0x3C3ABA, 0x461846, 0x5F7555,
+    0xF5BDD2, 0xC6926E, 0x5D2EAC, 0xED440E, 0x423E1C, 0x87C461, 0xE9FD29, 0xF3D6E7, 0xCA7C22,
+    0x35916F, 0xC5E008, 0x8DD7FF, 0xE26A6E, 0xC6FDB0, 0xC10893, 0x745D7C, 0xB2AD6B, 0x9D6ECD,
+    0x7B723E, 0x6A11C6, 0xA9CFF7, 0xDF7329, 0xBAC9B5, 0x5100B7, 0x0DB2E2, 0x24BA74, 0x607DE5,
+    0x8AD874, 0x2C150D, 0x0C1881, 0x94667E, 0x162901, 0x767A9F, 0xBEFDFD, 0xEF4556, 0x367ED9,
+    0x13D9EC, 0xB9BA8B, 0xFC97C4, 0x27A831, 0xC36EF1, 0x36C594, 0x56A8D8, 0xB5A8B4, 0x0ECCCF,
+    0x2D8912, 0x34576F, 0x89562C, 0xE3CE99, 0xB920D6, 0xAA5E6B, 0x9C2A3E, 0xCC5F11, 0x4A0BFD,
+    0xFBF4E1, 0x6D3B8E, 0x2C86E2, 0x84D4E9, 0xA9B4FC, 0xD1EEEF, 0xC9352E, 0x61392F, 0x442138,
+    0xC8D91B, 0x0AFC81, 0x6A4AFB, 0xD81C2F, 0x84B453, 0x8C994E, 0xCC2254, 0xDC552A, 0xD6C6C0,
+    0x96190B, 0xB8701A, 0x649569, 0x605A26, 0xEE523F, 0x0F117F, 0x11B5F4, 0xF5CBFC, 0x2DBC34,
+    0xEEBC34, 0xCC5DE8, 0x605EDD, 0x9B8E67, 0xEF3392, 0xB817C9, 0x9B5861, 0xBC57E1, 0xC68351,
+    0x103ED8, 0x4871DD, 0xDD1C2D, 0xA118AF, 0x462C21, 0xD7F359, 0x987AD9, 0xC0549E, 0xFA864F,
+    0xFC0656, 0xAE79E5, 0x362289, 0x22AD38, 0xDC9367, 0xAAE855, 0x382682, 0x9BE7CA, 0xA40D51,
+    0xB13399, 0x0ED7A9, 0x480569, 0xF0B265, 0xA7887F, 0x974C88, 0x36D1F9, 0xB39221, 0x4A827B,
+    0x21CF98, 0xDC9F40, 0x5547DC, 0x3A74E1, 0x42EB67, 0xDF9DFE, 0x5FD45E, 0xA4677B, 0x7AACBA,
+    0xA2F655, 0x23882B, 0x55BA41, 0x086E59, 0x862A21, 0x834739, 0xE6E389, 0xD49EE5, 0x40FB49,
+    0xE956FF, 0xCA0F1C, 0x8A59C5, 0x2BFA94, 0xC5C1D3, 0xCFC50F, 0xAE5ADB, 0x86C547, 0x624385,
+    0x3B8621, 0x94792C, 0x876110, 0x7B4C2A, 0x1A2C80, 0x12BF43, 0x902688, 0x893C78, 0xE4C4A8,
+    0x7BDBE5, 0xC23AC4, 0xEAF426, 0x8A67F7, 0xBF920D, 0x2BA365, 0xB1933D, 0x0B7CBD, 0xDC51A4,
+    0x63DD27, 0xDDE169, 0x19949A, 0x9529A8, 0x28CE68, 0xB4ED09, 0x209F44, 0xCA984E, 0x638270,
+    0x237C7E, 0x32B90F, 0x8EF5A7, 0xE75614, 0x08F121, 0x2A9DB5, 0x4D7E6F, 0x5119A5, 0xABF9B5,
+    0xD6DF82, 0x61DD96, 0x023616, 0x9F3AC4, 0xA1A283, 0x6DED72, 0x7A8D39, 0xA9B882, 0x5C326B,
+    0x5B2746, 0xED3400, 0x7700D2, 0x55F4FC, 0x4D5901, 0x8071E0,
+];
+
+const PIO2: [f64; 8] = [
+    1.57079625129699707031e+00, /* 0x3FF921FB, 0x40000000 */
+    7.54978941586159635335e-08, /* 0x3E74442D, 0x00000000 */
+    5.39030252995776476554e-15, /* 0x3CF84698, 0x80000000 */
+    3.28200341580791294123e-22, /* 0x3B78CC51, 0x60000000 */
+    1.27065575308067607349e-29, /* 0x39F01B83, 0x80000000 */
+    1.22933308981111328932e-36, /* 0x387A2520, 0x40000000 */
+    2.73370053816464559624e-44, /* 0x36E38222, 0x80000000 */
+    2.16741683877804819444e-51, /* 0x3569F31D, 0x00000000 */
+];
+
+// fn rem_pio2_large(x : &[f64], y : &mut [f64], e0 : i32, prec : usize) -> i32
+//
+// Input parameters:
+//      x[]     The input value (must be positive) is broken into nx
+//              pieces of 24-bit integers in double precision format.
+//              x[i] will be the i-th 24 bit of x. The scaled exponent
+//              of x[0] is given in input parameter e0 (i.e., x[0]*2^e0
+//              match x's up to 24 bits.
+//
+//              Example of breaking a double positive z into x[0]+x[1]+x[2]:
+//                      e0 = ilogb(z)-23
+//                      z  = scalbn(z,-e0)
+//              for i = 0,1,2
+//                      x[i] = floor(z)
+//                      z    = (z-x[i])*2**24
+//
+//      y[]     ouput result in an array of double precision numbers.
+//              The dimension of y[] is:
+//                      24-bit  precision       1
+//                      53-bit  precision       2
+//                      64-bit  precision       2
+//                      113-bit precision       3
+//              The actual value is the sum of them. Thus for 113-bit
+//              precison, one may have to do something like:
+//
+//              long double t,w,r_head, r_tail;
+//              t = (long double)y[2] + (long double)y[1];
+//              w = (long double)y[0];
+//              r_head = t+w;
+//              r_tail = w - (r_head - t);
+//
+//      e0      The exponent of x[0]. Must be <= 16360 or you need to
+//              expand the ipio2 table.
+//
+//      prec    an integer indicating the precision:
+//                      0       24  bits (single)
+//                      1       53  bits (double)
+//                      2       64  bits (extended)
+//                      3       113 bits (quad)
+//
+// Here is the description of some local variables:
+//
+//      jk      jk+1 is the initial number of terms of ipio2[] needed
+//              in the computation. The minimum and recommended value
+//              for jk is 3,4,4,6 for single, double, extended, and quad.
+//              jk+1 must be 2 larger than you might expect so that our
+//              recomputation test works. (Up to 24 bits in the integer
+//              part (the 24 bits of it that we compute) and 23 bits in
+//              the fraction part may be lost to cancelation before we
+//              recompute.)
+//
+//      jz      local integer variable indicating the number of
+//              terms of ipio2[] used.
+//
+//      jx      nx - 1
+//
+//      jv      index for pointing to the suitable ipio2[] for the
+//              computation. In general, we want
+//                      ( 2^e0*x[0] * ipio2[jv-1]*2^(-24jv) )/8
+//              is an integer. Thus
+//                      e0-3-24*jv >= 0 or (e0-3)/24 >= jv
+//              Hence jv = max(0,(e0-3)/24).
+//
+//      jp      jp+1 is the number of terms in PIo2[] needed, jp = jk.
+//
+//      q[]     double array with integral value, representing the
+//              24-bits chunk of the product of x and 2/pi.
+//
+//      q0      the corresponding exponent of q[0]. Note that the
+//              exponent for q[i] would be q0-24*i.
+//
+//      PIo2[]  double precision array, obtained by cutting pi/2
+//              into 24 bits chunks.
+//
+//      f[]     ipio2[] in floating point
+//
+//      iq[]    integer array by breaking up q[] in 24-bits chunk.
+//
+//      fq[]    final product of x*(2/pi) in fq[0],..,fq[jk]
+//
+//      ih      integer. If >0 it indicates q[] is >= 0.5, hence
+//              it also indicates the *sign* of the result.
+
+/// Return the last three digits of N with y = x - N*pi/2
+/// so that |y| < pi/2.
+///
+/// The method is to compute the integer (mod 8) and fraction parts of
+/// (2/pi)*x without doing the full multiplication. In general we
+/// skip the part of the product that are known to be a huge integer (
+/// more accurately, = 0 mod 8 ). Thus the number of operations are
+/// independent of the exponent of the input.
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub(crate) fn rem_pio2_large(x: &[f64], y: &mut [f64], e0: i32, prec: usize) -> i32 {
+    let x1p24 = f64::from_bits(0x4170000000000000); // 0x1p24 === 2 ^ 24
+    let x1p_24 = f64::from_bits(0x3e70000000000000); // 0x1p_24 === 2 ^ (-24)
+
+    #[cfg(all(target_pointer_width = "64", feature = "checked"))]
+    assert!(e0 <= 16360);
+
+    let nx = x.len();
+
+    let mut fw: f64;
+    let mut n: i32;
+    let mut ih: i32;
+    let mut z: f64;
+    let mut f: [f64; 20] = [0.; 20];
+    let mut fq: [f64; 20] = [0.; 20];
+    let mut q: [f64; 20] = [0.; 20];
+    let mut iq: [i32; 20] = [0; 20];
+
+    /* initialize jk*/
+    let jk = INIT_JK[prec];
+    let jp = jk;
+
+    /* determine jx,jv,q0, note that 3>q0 */
+    let jx = nx - 1;
+    let mut jv = (e0 - 3) / 24;
+    if jv < 0 {
+        jv = 0;
+    }
+    let mut q0 = e0 - 24 * (jv + 1);
+    let jv = jv as usize;
+
+    /* set up f[0] to f[jx+jk] where f[jx+jk] = ipio2[jv+jk] */
+    let mut j = (jv - jx) as i32;
+    let m = jx + jk;
+    for i in 0..=m {
+        i!(f, i, =, if j < 0 {
+            0.
+        } else {
+            i!(IPIO2, j as usize) as f64
+        });
+        j += 1;
+    }
+
+    /* compute q[0],q[1],...q[jk] */
+    for i in 0..=jk {
+        fw = 0f64;
+        for j in 0..=jx {
+            fw += i!(x, j) * i!(f, jx + i - j);
+        }
+        i!(q, i, =, fw);
+    }
+
+    let mut jz = jk;
+
+    'recompute: loop {
+        /* distill q[] into iq[] reversingly */
+        let mut i = 0i32;
+        z = i!(q, jz);
+        for j in (1..=jz).rev() {
+            fw = (x1p_24 * z) as i32 as f64;
+            i!(iq, i as usize, =, (z - x1p24 * fw) as i32);
+            z = i!(q, j - 1) + fw;
+            i += 1;
+        }
+
+        /* compute n */
+        z = scalbn(z, q0); /* actual value of z */
+        z -= 8.0 * floor(z * 0.125); /* trim off integer >= 8 */
+        n = z as i32;
+        z -= n as f64;
+        ih = 0;
+        if q0 > 0 {
+            /* need iq[jz-1] to determine n */
+            i = i!(iq, jz - 1) >> (24 - q0);
+            n += i;
+            i!(iq, jz - 1, -=, i << (24 - q0));
+            ih = i!(iq, jz - 1) >> (23 - q0);
+        } else if q0 == 0 {
+            ih = i!(iq, jz - 1) >> 23;
+        } else if z >= 0.5 {
+            ih = 2;
+        }
+
+        if ih > 0 {
+            /* q > 0.5 */
+            n += 1;
+            let mut carry = 0i32;
+            for i in 0..jz {
+                /* compute 1-q */
+                let j = i!(iq, i);
+                if carry == 0 {
+                    if j != 0 {
+                        carry = 1;
+                        i!(iq, i, =, 0x1000000 - j);
+                    }
+                } else {
+                    i!(iq, i, =, 0xffffff - j);
+                }
+            }
+            if q0 > 0 {
+                /* rare case: chance is 1 in 12 */
+                match q0 {
+                    1 => {
+                        i!(iq, jz - 1, &=, 0x7fffff);
+                    }
+                    2 => {
+                        i!(iq, jz - 1, &=, 0x3fffff);
+                    }
+                    _ => {}
+                }
+            }
+            if ih == 2 {
+                z = 1. - z;
+                if carry != 0 {
+                    z -= scalbn(1., q0);
+                }
+            }
+        }
+
+        /* check if recomputation is needed */
+        if z == 0. {
+            let mut j = 0;
+            for i in (jk..=jz - 1).rev() {
+                j |= i!(iq, i);
+            }
+            if j == 0 {
+                /* need recomputation */
+                let mut k = 1;
+                while i!(iq, jk - k, ==, 0) {
+                    k += 1; /* k = no. of terms needed */
+                }
+
+                for i in (jz + 1)..=(jz + k) {
+                    /* add q[jz+1] to q[jz+k] */
+                    i!(f, jx + i, =, i!(IPIO2, jv + i) as f64);
+                    fw = 0f64;
+                    for j in 0..=jx {
+                        fw += i!(x, j) * i!(f, jx + i - j);
+                    }
+                    i!(q, i, =, fw);
+                }
+                jz += k;
+                continue 'recompute;
+            }
+        }
+
+        break;
+    }
+
+    /* chop off zero terms */
+    if z == 0. {
+        jz -= 1;
+        q0 -= 24;
+        while i!(iq, jz) == 0 {
+            jz -= 1;
+            q0 -= 24;
+        }
+    } else {
+        /* break z into 24-bit if necessary */
+        z = scalbn(z, -q0);
+        if z >= x1p24 {
+            fw = (x1p_24 * z) as i32 as f64;
+            i!(iq, jz, =, (z - x1p24 * fw) as i32);
+            jz += 1;
+            q0 += 24;
+            i!(iq, jz, =, fw as i32);
+        } else {
+            i!(iq, jz, =, z as i32);
+        }
+    }
+
+    /* convert integer "bit" chunk to floating-point value */
+    fw = scalbn(1., q0);
+    for i in (0..=jz).rev() {
+        i!(q, i, =, fw * (i!(iq, i) as f64));
+        fw *= x1p_24;
+    }
+
+    /* compute PIo2[0,...,jp]*q[jz,...,0] */
+    for i in (0..=jz).rev() {
+        fw = 0f64;
+        let mut k = 0;
+        while (k <= jp) && (k <= jz - i) {
+            fw += i!(PIO2, k) * i!(q, i + k);
+            k += 1;
+        }
+        i!(fq, jz - i, =, fw);
+    }
+
+    /* compress fq[] into y[] */
+    match prec {
+        0 => {
+            fw = 0f64;
+            for i in (0..=jz).rev() {
+                fw += i!(fq, i);
+            }
+            i!(y, 0, =, if ih == 0 { fw } else { -fw });
+        }
+        1 | 2 => {
+            fw = 0f64;
+            for i in (0..=jz).rev() {
+                fw += i!(fq, i);
+            }
+            // TODO: drop excess precision here once double_t is used
+            fw = fw as f64;
+            i!(y, 0, =, if ih == 0 { fw } else { -fw });
+            fw = i!(fq, 0) - fw;
+            for i in 1..=jz {
+                fw += i!(fq, i);
+            }
+            i!(y, 1, =, if ih == 0 { fw } else { -fw });
+        }
+        3 => {
+            /* painful */
+            for i in (1..=jz).rev() {
+                fw = i!(fq, i - 1) + i!(fq, i);
+                i!(fq, i, +=, i!(fq, i - 1) - fw);
+                i!(fq, i - 1, =, fw);
+            }
+            for i in (2..=jz).rev() {
+                fw = i!(fq, i - 1) + i!(fq, i);
+                i!(fq, i, +=, i!(fq, i - 1) - fw);
+                i!(fq, i - 1, =, fw);
+            }
+            fw = 0f64;
+            for i in (2..=jz).rev() {
+                fw += i!(fq, i);
+            }
+            if ih == 0 {
+                i!(y, 0, =, i!(fq, 0));
+                i!(y, 1, =, i!(fq, 1));
+                i!(y, 2, =, fw);
+            } else {
+                i!(y, 0, =, -i!(fq, 0));
+                i!(y, 1, =, -i!(fq, 1));
+                i!(y, 2, =, -fw);
+            }
+        }
+        #[cfg(feature = "checked")]
+        _ => unreachable!(),
+        #[cfg(not(feature = "checked"))]
+        _ => {}
+    }
+    n & 7
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/rem_pio2f.rs.html b/src/libm/math/rem_pio2f.rs.html new file mode 100644 index 000000000..aa8d3fc46 --- /dev/null +++ b/src/libm/math/rem_pio2f.rs.html @@ -0,0 +1,129 @@ +rem_pio2f.rs.html -- source
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+/* origin: FreeBSD /usr/src/lib/msun/src/e_rem_pio2f.c */
+/*
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ * Debugged and optimized by Bruce D. Evans.
+ */
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+use super::rem_pio2_large;
+
+use core::f64;
+
+const TOINT: f64 = 1.5 / f64::EPSILON;
+
+/// 53 bits of 2/pi
+const INV_PIO2: f64 = 6.36619772367581382433e-01; /* 0x3FE45F30, 0x6DC9C883 */
+/// first 25 bits of pi/2
+const PIO2_1: f64 = 1.57079631090164184570e+00; /* 0x3FF921FB, 0x50000000 */
+/// pi/2 - pio2_1
+const PIO2_1T: f64 = 1.58932547735281966916e-08; /* 0x3E5110b4, 0x611A6263 */
+
+/// Return the remainder of x rem pi/2 in *y
+///
+/// use double precision for everything except passing x
+/// use __rem_pio2_large() for large x
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub(crate) fn rem_pio2f(x: f32) -> (i32, f64) {
+    let x64 = x as f64;
+
+    let mut tx: [f64; 1] = [0.];
+    let mut ty: [f64; 1] = [0.];
+
+    let ix = x.to_bits() & 0x7fffffff;
+    /* 25+53 bit pi is good enough for medium size */
+    if ix < 0x4dc90fdb {
+        /* |x| ~< 2^28*(pi/2), medium size */
+        /* Use a specialized rint() to get fn.  Assume round-to-nearest. */
+        let f_n = x64 * INV_PIO2 + TOINT - TOINT;
+        return (f_n as i32, x64 - f_n * PIO2_1 - f_n * PIO2_1T);
+    }
+    if ix >= 0x7f800000 {
+        /* x is inf or NaN */
+        return (0, x64 - x64);
+    }
+    /* scale x into [2^23, 2^24-1] */
+    let sign = (x.to_bits() >> 31) != 0;
+    let e0 = ((ix >> 23) - (0x7f + 23)) as i32; /* e0 = ilogb(|x|)-23, positive */
+    tx[0] = f32::from_bits(ix - (e0 << 23) as u32) as f64;
+    let n = rem_pio2_large(&tx, &mut ty, e0, 0);
+    if sign {
+        return (-n, -ty[0]);
+    }
+    (n, ty[0])
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/remquo.rs.html b/src/libm/math/remquo.rs.html new file mode 100644 index 000000000..94e767f7d --- /dev/null +++ b/src/libm/math/remquo.rs.html @@ -0,0 +1,197 @@ +remquo.rs.html -- source
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+
+pub fn remquo(mut x: f64, mut y: f64) -> (f64, i32) {
+    let ux: u64 = x.to_bits();
+    let mut uy: u64 = y.to_bits();
+    let mut ex = ((ux >> 52) & 0x7ff) as i32;
+    let mut ey = ((uy >> 52) & 0x7ff) as i32;
+    let sx = (ux >> 63) != 0;
+    let sy = (uy >> 63) != 0;
+    let mut q: u32;
+    let mut i: u64;
+    let mut uxi: u64 = ux;
+
+    if (uy << 1) == 0 || y.is_nan() || ex == 0x7ff {
+        return ((x * y) / (x * y), 0);
+    }
+    if (ux << 1) == 0 {
+        return (x, 0);
+    }
+
+    /* normalize x and y */
+    if ex == 0 {
+        i = uxi << 12;
+        while (i >> 63) == 0 {
+            ex -= 1;
+            i <<= 1;
+        }
+        uxi <<= -ex + 1;
+    } else {
+        uxi &= (!0) >> 12;
+        uxi |= 1 << 52;
+    }
+    if ey == 0 {
+        i = uy << 12;
+        while (i >> 63) == 0 {
+            ey -= 1;
+            i <<= 1;
+        }
+        uy <<= -ey + 1;
+    } else {
+        uy &= (!0) >> 12;
+        uy |= 1 << 52;
+    }
+
+    q = 0;
+
+    if ex + 1 != ey {
+        if ex < ey {
+            return (x, 0);
+        }
+        /* x mod y */
+        while ex > ey {
+            i = uxi.wrapping_sub(uy);
+            if (i >> 63) == 0 {
+                uxi = i;
+                q += 1;
+            }
+            uxi <<= 1;
+            q <<= 1;
+            ex -= 1;
+        }
+        i = uxi.wrapping_sub(uy);
+        if (i >> 63) == 0 {
+            uxi = i;
+            q += 1;
+        }
+        if uxi == 0 {
+            ex = -60;
+        } else {
+            while (uxi >> 52) == 0 {
+                uxi <<= 1;
+                ex -= 1;
+            }
+        }
+    }
+
+    /* scale result and decide between |x| and |x|-|y| */
+    if ex > 0 {
+        uxi -= 1 << 52;
+        uxi |= (ex as u64) << 52;
+    } else {
+        uxi >>= -ex + 1;
+    }
+    x = f64::from_bits(uxi);
+    if sy {
+        y = -y;
+    }
+    if ex == ey || (ex + 1 == ey && (2.0 * x > y || (2.0 * x == y && (q % 2) != 0))) {
+        x -= y;
+        q += 1;
+    }
+    q &= 0x7fffffff;
+    let quo = if sx ^ sy { -(q as i32) } else { q as i32 };
+    if sx {
+        (-x, quo)
+    } else {
+        (x, quo)
+    }
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/remquof.rs.html b/src/libm/math/remquof.rs.html new file mode 100644 index 000000000..a01429863 --- /dev/null +++ b/src/libm/math/remquof.rs.html @@ -0,0 +1,195 @@ +remquof.rs.html -- source
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+pub fn remquof(mut x: f32, mut y: f32) -> (f32, i32) {
+    let ux: u32 = x.to_bits();
+    let mut uy: u32 = y.to_bits();
+    let mut ex = ((ux >> 23) & 0xff) as i32;
+    let mut ey = ((uy >> 23) & 0xff) as i32;
+    let sx = (ux >> 31) != 0;
+    let sy = (uy >> 31) != 0;
+    let mut q: u32;
+    let mut i: u32;
+    let mut uxi: u32 = ux;
+
+    if (uy << 1) == 0 || y.is_nan() || ex == 0xff {
+        return ((x * y) / (x * y), 0);
+    }
+    if (ux << 1) == 0 {
+        return (x, 0);
+    }
+
+    /* normalize x and y */
+    if ex == 0 {
+        i = uxi << 9;
+        while (i >> 31) == 0 {
+            ex -= 1;
+            i <<= 1;
+        }
+        uxi <<= -ex + 1;
+    } else {
+        uxi &= (!0) >> 9;
+        uxi |= 1 << 23;
+    }
+    if ey == 0 {
+        i = uy << 9;
+        while (i >> 31) == 0 {
+            ey -= 1;
+            i <<= 1;
+        }
+        uy <<= -ey + 1;
+    } else {
+        uy &= (!0) >> 9;
+        uy |= 1 << 23;
+    }
+
+    q = 0;
+    if ex + 1 != ey {
+        if ex < ey {
+            return (x, 0);
+        }
+        /* x mod y */
+        while ex > ey {
+            i = uxi.wrapping_sub(uy);
+            if (i >> 31) == 0 {
+                uxi = i;
+                q += 1;
+            }
+            uxi <<= 1;
+            q <<= 1;
+            ex -= 1;
+        }
+        i = uxi.wrapping_sub(uy);
+        if (i >> 31) == 0 {
+            uxi = i;
+            q += 1;
+        }
+        if uxi == 0 {
+            ex = -30;
+        } else {
+            while (uxi >> 23) == 0 {
+                uxi <<= 1;
+                ex -= 1;
+            }
+        }
+    }
+
+    /* scale result and decide between |x| and |x|-|y| */
+    if ex > 0 {
+        uxi -= 1 << 23;
+        uxi |= (ex as u32) << 23;
+    } else {
+        uxi >>= -ex + 1;
+    }
+    x = f32::from_bits(uxi);
+    if sy {
+        y = -y;
+    }
+    if ex == ey || (ex + 1 == ey && (2.0 * x > y || (2.0 * x == y && (q % 2) != 0))) {
+        x -= y;
+        q += 1;
+    }
+    q &= 0x7fffffff;
+    let quo = if sx ^ sy { -(q as i32) } else { q as i32 };
+    if sx {
+        (-x, quo)
+    } else {
+        (x, quo)
+    }
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/round.rs.html b/src/libm/math/round.rs.html new file mode 100644 index 000000000..9fd15cb08 --- /dev/null +++ b/src/libm/math/round.rs.html @@ -0,0 +1,77 @@ +round.rs.html -- source
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+use core::f64;
+
+const TOINT: f64 = 1.0 / f64::EPSILON;
+
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn round(mut x: f64) -> f64 {
+    let (f, i) = (x, x.to_bits());
+    let e: u64 = i >> 52 & 0x7ff;
+    let mut y: f64;
+
+    if e >= 0x3ff + 52 {
+        return x;
+    }
+    if i >> 63 != 0 {
+        x = -x;
+    }
+    if e < 0x3ff - 1 {
+        // raise inexact if x!=0
+        force_eval!(x + TOINT);
+        return 0.0 * f;
+    }
+    y = x + TOINT - TOINT - x;
+    if y > 0.5 {
+        y = y + x - 1.0;
+    } else if y <= -0.5 {
+        y = y + x + 1.0;
+    } else {
+        y = y + x;
+    }
+
+    if i >> 63 != 0 {
+        -y
+    } else {
+        y
+    }
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/roundf.rs.html b/src/libm/math/roundf.rs.html new file mode 100644 index 000000000..25e8dd0ce --- /dev/null +++ b/src/libm/math/roundf.rs.html @@ -0,0 +1,73 @@ +roundf.rs.html -- source
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+use core::f32;
+
+const TOINT: f32 = 1.0 / f32::EPSILON;
+
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn roundf(mut x: f32) -> f32 {
+    let i = x.to_bits();
+    let e: u32 = i >> 23 & 0xff;
+    let mut y: f32;
+
+    if e >= 0x7f + 23 {
+        return x;
+    }
+    if i >> 31 != 0 {
+        x = -x;
+    }
+    if e < 0x7f - 1 {
+        force_eval!(x + TOINT);
+        return 0.0 * x;
+    }
+    y = x + TOINT - TOINT - x;
+    if y > 0.5f32 {
+        y = y + x - 1.0;
+    } else if y <= -0.5f32 {
+        y = y + x + 1.0;
+    } else {
+        y = y + x;
+    }
+    if i >> 31 != 0 {
+        -y
+    } else {
+        y
+    }
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/scalbn.rs.html b/src/libm/math/scalbn.rs.html new file mode 100644 index 000000000..0c5b27281 --- /dev/null +++ b/src/libm/math/scalbn.rs.html @@ -0,0 +1,71 @@ +scalbn.rs.html -- source
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+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn scalbn(x: f64, mut n: i32) -> f64 {
+    let x1p1023 = f64::from_bits(0x7fe0000000000000); // 0x1p1023 === 2 ^ 1023
+    let x1p53 = f64::from_bits(0x4340000000000000); // 0x1p53 === 2 ^ 53
+    let x1p_1022 = f64::from_bits(0x0010000000000000); // 0x1p-1022 === 2 ^ (-1022)
+
+    let mut y = x;
+
+    if n > 1023 {
+        y *= x1p1023;
+        n -= 1023;
+        if n > 1023 {
+            y *= x1p1023;
+            n -= 1023;
+            if n > 1023 {
+                n = 1023;
+            }
+        }
+    } else if n < -1022 {
+        /* make sure final n < -53 to avoid double
+        rounding in the subnormal range */
+        y *= x1p_1022 * x1p53;
+        n += 1022 - 53;
+        if n < -1022 {
+            y *= x1p_1022 * x1p53;
+            n += 1022 - 53;
+            if n < -1022 {
+                n = -1022;
+            }
+        }
+    }
+    y * f64::from_bits(((0x3ff + n) as u64) << 52)
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/scalbnf.rs.html b/src/libm/math/scalbnf.rs.html new file mode 100644 index 000000000..e9230f035 --- /dev/null +++ b/src/libm/math/scalbnf.rs.html @@ -0,0 +1,63 @@ +scalbnf.rs.html -- source
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+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn scalbnf(mut x: f32, mut n: i32) -> f32 {
+    let x1p127 = f32::from_bits(0x7f000000); // 0x1p127f === 2 ^ 127
+    let x1p_126 = f32::from_bits(0x800000); // 0x1p-126f === 2 ^ -126
+    let x1p24 = f32::from_bits(0x4b800000); // 0x1p24f === 2 ^ 24
+
+    if n > 127 {
+        x *= x1p127;
+        n -= 127;
+        if n > 127 {
+            x *= x1p127;
+            n -= 127;
+            if n > 127 {
+                n = 127;
+            }
+        }
+    } else if n < -126 {
+        x *= x1p_126 * x1p24;
+        n += 126 - 24;
+        if n < -126 {
+            x *= x1p_126 * x1p24;
+            n += 126 - 24;
+            if n < -126 {
+                n = -126;
+            }
+        }
+    }
+    x * f32::from_bits(((0x7f + n) as u32) << 23)
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/sin.rs.html b/src/libm/math/sin.rs.html new file mode 100644 index 000000000..2e177759a --- /dev/null +++ b/src/libm/math/sin.rs.html @@ -0,0 +1,175 @@ +sin.rs.html -- source
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+// origin: FreeBSD /usr/src/lib/msun/src/s_sin.c */
+//
+// ====================================================
+// Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+//
+// Developed at SunPro, a Sun Microsystems, Inc. business.
+// Permission to use, copy, modify, and distribute this
+// software is freely granted, provided that this notice
+// is preserved.
+// ====================================================
+
+use super::{k_cos, k_sin, rem_pio2};
+
+// sin(x)
+// Return sine function of x.
+//
+// kernel function:
+//      k_sin            ... sine function on [-pi/4,pi/4]
+//      k_cos            ... cose function on [-pi/4,pi/4]
+//      rem_pio2         ... argument reduction routine
+//
+// Method.
+//      Let S,C and T denote the sin, cos and tan respectively on
+//      [-PI/4, +PI/4]. Reduce the argument x to y1+y2 = x-k*pi/2
+//      in [-pi/4 , +pi/4], and let n = k mod 4.
+//      We have
+//
+//          n        sin(x)      cos(x)        tan(x)
+//     ----------------------------------------------------------
+//          0          S           C             T
+//          1          C          -S            -1/T
+//          2         -S          -C             T
+//          3         -C           S            -1/T
+//     ----------------------------------------------------------
+//
+// Special cases:
+//      Let trig be any of sin, cos, or tan.
+//      trig(+-INF)  is NaN, with signals;
+//      trig(NaN)    is that NaN;
+//
+// Accuracy:
+//      TRIG(x) returns trig(x) nearly rounded
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn sin(x: f64) -> f64 {
+    let x1p120 = f64::from_bits(0x4770000000000000); // 0x1p120f === 2 ^ 120
+
+    /* High word of x. */
+    let ix = (f64::to_bits(x) >> 32) as u32 & 0x7fffffff;
+
+    /* |x| ~< pi/4 */
+    if ix <= 0x3fe921fb {
+        if ix < 0x3e500000 {
+            /* |x| < 2**-26 */
+            /* raise inexact if x != 0 and underflow if subnormal*/
+            if ix < 0x00100000 {
+                force_eval!(x / x1p120);
+            } else {
+                force_eval!(x + x1p120);
+            }
+            return x;
+        }
+        return k_sin(x, 0.0, 0);
+    }
+
+    /* sin(Inf or NaN) is NaN */
+    if ix >= 0x7ff00000 {
+        return x - x;
+    }
+
+    /* argument reduction needed */
+    let (n, y0, y1) = rem_pio2(x);
+    match n & 3 {
+        0 => k_sin(y0, y1, 1),
+        1 => k_cos(y0, y1),
+        2 => -k_sin(y0, y1, 1),
+        _ => -k_cos(y0, y1),
+    }
+}
+
+#[test]
+fn test_near_pi() {
+    let x = f64::from_bits(0x400921fb000FD5DD); // 3.141592026217707
+    let sx = f64::from_bits(0x3ea50d15ced1a4a2); // 6.273720864039205e-7
+    assert_eq!(sin(x), sx);
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/sincos.rs.html b/src/libm/math/sincos.rs.html new file mode 100644 index 000000000..5c92d4c20 --- /dev/null +++ b/src/libm/math/sincos.rs.html @@ -0,0 +1,121 @@ +sincos.rs.html -- source
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+
+/* origin: FreeBSD /usr/src/lib/msun/src/s_sin.c */
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+use super::{get_high_word, k_cos, k_sin, rem_pio2};
+
+pub fn sincos(x: f64) -> (f64, f64) {
+    let s: f64;
+    let c: f64;
+    let mut ix: u32;
+
+    ix = get_high_word(x);
+    ix &= 0x7fffffff;
+
+    /* |x| ~< pi/4 */
+    if ix <= 0x3fe921fb {
+        /* if |x| < 2**-27 * sqrt(2) */
+        if ix < 0x3e46a09e {
+            /* raise inexact if x!=0 and underflow if subnormal */
+            let x1p120 = f64::from_bits(0x4770000000000000); // 0x1p120 == 2^120
+            if ix < 0x00100000 {
+                force_eval!(x / x1p120);
+            } else {
+                force_eval!(x + x1p120);
+            }
+            return (x, 1.0);
+        }
+        return (k_sin(x, 0.0, 0), k_cos(x, 0.0));
+    }
+
+    /* sincos(Inf or NaN) is NaN */
+    if ix >= 0x7ff00000 {
+        let rv = x - x;
+        return (rv, rv);
+    }
+
+    /* argument reduction needed */
+    let (n, y0, y1) = rem_pio2(x);
+    s = k_sin(y0, y1, 1);
+    c = k_cos(y0, y1);
+    match n & 3 {
+        0 => (s, c),
+        1 => (c, -s),
+        2 => (-s, -c),
+        3 => (-c, s),
+        #[cfg(feature = "checked")]
+        _ => unreachable!(),
+        #[cfg(not(feature = "checked"))]
+        _ => (0.0, 1.0),
+    }
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/sincosf.rs.html b/src/libm/math/sincosf.rs.html new file mode 100644 index 000000000..fcd3edf43 --- /dev/null +++ b/src/libm/math/sincosf.rs.html @@ -0,0 +1,249 @@ +sincosf.rs.html -- source
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+
+/* origin: FreeBSD /usr/src/lib/msun/src/s_sinf.c */
+/*
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ * Optimized by Bruce D. Evans.
+ */
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+use super::{k_cosf, k_sinf, rem_pio2f};
+
+/* Small multiples of pi/2 rounded to double precision. */
+const PI_2: f32 = 0.5 * 3.1415926535897931160E+00;
+const S1PIO2: f32 = 1.0 * PI_2; /* 0x3FF921FB, 0x54442D18 */
+const S2PIO2: f32 = 2.0 * PI_2; /* 0x400921FB, 0x54442D18 */
+const S3PIO2: f32 = 3.0 * PI_2; /* 0x4012D97C, 0x7F3321D2 */
+const S4PIO2: f32 = 4.0 * PI_2; /* 0x401921FB, 0x54442D18 */
+
+pub fn sincosf(x: f32) -> (f32, f32) {
+    let s: f32;
+    let c: f32;
+    let mut ix: u32;
+    let sign: bool;
+
+    ix = x.to_bits();
+    sign = (ix >> 31) != 0;
+    ix &= 0x7fffffff;
+
+    /* |x| ~<= pi/4 */
+    if ix <= 0x3f490fda {
+        /* |x| < 2**-12 */
+        if ix < 0x39800000 {
+            /* raise inexact if x!=0 and underflow if subnormal */
+
+            let x1p120 = f32::from_bits(0x7b800000); // 0x1p120 == 2^120
+            if ix < 0x00100000 {
+                force_eval!(x / x1p120);
+            } else {
+                force_eval!(x + x1p120);
+            }
+            return (x, 1.0);
+        }
+        return (k_sinf(x as f64), k_cosf(x as f64));
+    }
+
+    /* |x| ~<= 5*pi/4 */
+    if ix <= 0x407b53d1 {
+        if ix <= 0x4016cbe3 {
+            /* |x| ~<= 3pi/4 */
+            if sign {
+                s = -k_cosf((x + S1PIO2) as f64);
+                c = k_sinf((x + S1PIO2) as f64);
+            } else {
+                s = k_cosf((S1PIO2 - x) as f64);
+                c = k_sinf((S1PIO2 - x) as f64);
+            }
+        }
+        /* -sin(x+c) is not correct if x+c could be 0: -0 vs +0 */
+        else {
+            if sign {
+                s = k_sinf((x + S2PIO2) as f64);
+                c = k_cosf((x + S2PIO2) as f64);
+            } else {
+                s = k_sinf((x - S2PIO2) as f64);
+                c = k_cosf((x - S2PIO2) as f64);
+            }
+        }
+
+        return (s, c);
+    }
+
+    /* |x| ~<= 9*pi/4 */
+    if ix <= 0x40e231d5 {
+        if ix <= 0x40afeddf {
+            /* |x| ~<= 7*pi/4 */
+            if sign {
+                s = k_cosf((x + S3PIO2) as f64);
+                c = -k_sinf((x + S3PIO2) as f64);
+            } else {
+                s = -k_cosf((x - S3PIO2) as f64);
+                c = k_sinf((x - S3PIO2) as f64);
+            }
+        } else {
+            if sign {
+                s = k_cosf((x + S4PIO2) as f64);
+                c = k_sinf((x + S4PIO2) as f64);
+            } else {
+                s = k_cosf((x - S4PIO2) as f64);
+                c = k_sinf((x - S4PIO2) as f64);
+            }
+        }
+
+        return (s, c);
+    }
+
+    /* sin(Inf or NaN) is NaN */
+    if ix >= 0x7f800000 {
+        let rv = x - x;
+        return (rv, rv);
+    }
+
+    /* general argument reduction needed */
+    let (n, y) = rem_pio2f(x);
+    s = k_sinf(y);
+    c = k_cosf(y);
+    match n & 3 {
+        0 => (s, c),
+        1 => (c, -s),
+        2 => (-s, -c),
+        3 => (-c, s),
+        #[cfg(feature = "checked")]
+        _ => unreachable!(),
+        #[cfg(not(feature = "checked"))]
+        _ => (0.0, 1.0),
+    }
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/sinf.rs.html b/src/libm/math/sinf.rs.html new file mode 100644 index 000000000..9ad3bcd2d --- /dev/null +++ b/src/libm/math/sinf.rs.html @@ -0,0 +1,191 @@ +sinf.rs.html -- source
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+
+/* origin: FreeBSD /usr/src/lib/msun/src/s_sinf.c */
+/*
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ * Optimized by Bruce D. Evans.
+ */
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+use super::{k_cosf, k_sinf, rem_pio2f};
+
+use core::f64::consts::FRAC_PI_2;
+
+/* Small multiples of pi/2 rounded to double precision. */
+const S1_PIO2: f64 = 1. * FRAC_PI_2; /* 0x3FF921FB, 0x54442D18 */
+const S2_PIO2: f64 = 2. * FRAC_PI_2; /* 0x400921FB, 0x54442D18 */
+const S3_PIO2: f64 = 3. * FRAC_PI_2; /* 0x4012D97C, 0x7F3321D2 */
+const S4_PIO2: f64 = 4. * FRAC_PI_2; /* 0x401921FB, 0x54442D18 */
+
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn sinf(x: f32) -> f32 {
+    let x64 = x as f64;
+
+    let x1p120 = f32::from_bits(0x7b800000); // 0x1p120f === 2 ^ 120
+
+    let mut ix = x.to_bits();
+    let sign = (ix >> 31) != 0;
+    ix &= 0x7fffffff;
+
+    if ix <= 0x3f490fda {
+        /* |x| ~<= pi/4 */
+        if ix < 0x39800000 {
+            /* |x| < 2**-12 */
+            /* raise inexact if x!=0 and underflow if subnormal */
+            force_eval!(if ix < 0x00800000 {
+                x / x1p120
+            } else {
+                x + x1p120
+            });
+            return x;
+        }
+        return k_sinf(x64);
+    }
+    if ix <= 0x407b53d1 {
+        /* |x| ~<= 5*pi/4 */
+        if ix <= 0x4016cbe3 {
+            /* |x| ~<= 3pi/4 */
+            if sign {
+                return -k_cosf(x64 + S1_PIO2);
+            } else {
+                return k_cosf(x64 - S1_PIO2);
+            }
+        }
+        return k_sinf(if sign {
+            -(x64 + S2_PIO2)
+        } else {
+            -(x64 - S2_PIO2)
+        });
+    }
+    if ix <= 0x40e231d5 {
+        /* |x| ~<= 9*pi/4 */
+        if ix <= 0x40afeddf {
+            /* |x| ~<= 7*pi/4 */
+            if sign {
+                return k_cosf(x64 + S3_PIO2);
+            } else {
+                return -k_cosf(x64 - S3_PIO2);
+            }
+        }
+        return k_sinf(if sign { x64 + S4_PIO2 } else { x64 - S4_PIO2 });
+    }
+
+    /* sin(Inf or NaN) is NaN */
+    if ix >= 0x7f800000 {
+        return x - x;
+    }
+
+    /* general argument reduction needed */
+    let (n, y) = rem_pio2f(x);
+    match n & 3 {
+        0 => k_sinf(y),
+        1 => k_cosf(y),
+        2 => k_sinf(-y),
+        _ => -k_cosf(y),
+    }
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/sinh.rs.html b/src/libm/math/sinh.rs.html new file mode 100644 index 000000000..4395a5b92 --- /dev/null +++ b/src/libm/math/sinh.rs.html @@ -0,0 +1,103 @@ +sinh.rs.html -- source
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+use super::{expm1, expo2};
+
+// sinh(x) = (exp(x) - 1/exp(x))/2
+//         = (exp(x)-1 + (exp(x)-1)/exp(x))/2
+//         = x + x^3/6 + o(x^5)
+//
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn sinh(x: f64) -> f64 {
+    // union {double f; uint64_t i;} u = {.f = x};
+    // uint32_t w;
+    // double t, h, absx;
+
+    let mut uf: f64 = x;
+    let mut ui: u64 = f64::to_bits(uf);
+    let w: u32;
+    let t: f64;
+    let mut h: f64;
+    let absx: f64;
+
+    h = 0.5;
+    if ui >> 63 != 0 {
+        h = -h;
+    }
+    /* |x| */
+    ui &= !1 / 2;
+    uf = f64::from_bits(ui);
+    absx = uf;
+    w = (ui >> 32) as u32;
+
+    /* |x| < log(DBL_MAX) */
+    if w < 0x40862e42 {
+        t = expm1(absx);
+        if w < 0x3ff00000 {
+            if w < 0x3ff00000 - (26 << 20) {
+                /* note: inexact and underflow are raised by expm1 */
+                /* note: this branch avoids spurious underflow */
+                return x;
+            }
+            return h * (2.0 * t - t * t / (t + 1.0));
+        }
+        /* note: |x|>log(0x1p26)+eps could be just h*exp(x) */
+        return h * (t + t / (t + 1.0));
+    }
+
+    /* |x| > log(DBL_MAX) or nan */
+    /* note: the result is stored to handle overflow */
+    t = 2.0 * h * expo2(absx);
+    t
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/sinhf.rs.html b/src/libm/math/sinhf.rs.html new file mode 100644 index 000000000..f0b89d5d0 --- /dev/null +++ b/src/libm/math/sinhf.rs.html @@ -0,0 +1,65 @@ +sinhf.rs.html -- source
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+use super::expm1f;
+use super::k_expo2f;
+
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn sinhf(x: f32) -> f32 {
+    let mut h = 0.5f32;
+    let mut ix = x.to_bits();
+    if (ix >> 31) != 0 {
+        h = -h;
+    }
+    /* |x| */
+    ix &= 0x7fffffff;
+    let absx = f32::from_bits(ix);
+    let w = ix;
+
+    /* |x| < log(FLT_MAX) */
+    if w < 0x42b17217 {
+        let t = expm1f(absx);
+        if w < 0x3f800000 {
+            if w < (0x3f800000 - (12 << 23)) {
+                return x;
+            }
+            return h * (2. * t - t * t / (t + 1.));
+        }
+        return h * (t + t / (t + 1.));
+    }
+
+    /* |x| > logf(FLT_MAX) or nan */
+    2. * h * k_expo2f(absx)
+}
+
+
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+
+/* origin: FreeBSD /usr/src/lib/msun/src/e_sqrt.c */
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunSoft, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+/* sqrt(x)
+ * Return correctly rounded sqrt.
+ *           ------------------------------------------
+ *           |  Use the hardware sqrt if you have one |
+ *           ------------------------------------------
+ * Method:
+ *   Bit by bit method using integer arithmetic. (Slow, but portable)
+ *   1. Normalization
+ *      Scale x to y in [1,4) with even powers of 2:
+ *      find an integer k such that  1 <= (y=x*2^(2k)) < 4, then
+ *              sqrt(x) = 2^k * sqrt(y)
+ *   2. Bit by bit computation
+ *      Let q  = sqrt(y) truncated to i bit after binary point (q = 1),
+ *           i                                                   0
+ *                                     i+1         2
+ *          s  = 2*q , and      y  =  2   * ( y - q  ).         (1)
+ *           i      i            i                 i
+ *
+ *      To compute q    from q , one checks whether
+ *                  i+1       i
+ *
+ *                            -(i+1) 2
+ *                      (q + 2      ) <= y.                     (2)
+ *                        i
+ *                                                            -(i+1)
+ *      If (2) is false, then q   = q ; otherwise q   = q  + 2      .
+ *                             i+1   i             i+1   i
+ *
+ *      With some algebric manipulation, it is not difficult to see
+ *      that (2) is equivalent to
+ *                             -(i+1)
+ *                      s  +  2       <= y                      (3)
+ *                       i                i
+ *
+ *      The advantage of (3) is that s  and y  can be computed by
+ *                                    i      i
+ *      the following recurrence formula:
+ *          if (3) is false
+ *
+ *          s     =  s  ,       y    = y   ;                    (4)
+ *           i+1      i          i+1    i
+ *
+ *          otherwise,
+ *                         -i                     -(i+1)
+ *          s     =  s  + 2  ,  y    = y  -  s  - 2             (5)
+ *           i+1      i          i+1    i     i
+ *
+ *      One may easily use induction to prove (4) and (5).
+ *      Note. Since the left hand side of (3) contain only i+2 bits,
+ *            it does not necessary to do a full (53-bit) comparison
+ *            in (3).
+ *   3. Final rounding
+ *      After generating the 53 bits result, we compute one more bit.
+ *      Together with the remainder, we can decide whether the
+ *      result is exact, bigger than 1/2ulp, or less than 1/2ulp
+ *      (it will never equal to 1/2ulp).
+ *      The rounding mode can be detected by checking whether
+ *      huge + tiny is equal to huge, and whether huge - tiny is
+ *      equal to huge for some floating point number "huge" and "tiny".
+ *
+ * Special cases:
+ *      sqrt(+-0) = +-0         ... exact
+ *      sqrt(inf) = inf
+ *      sqrt(-ve) = NaN         ... with invalid signal
+ *      sqrt(NaN) = NaN         ... with invalid signal for signaling NaN
+ */
+
+use core::f64;
+use core::num::Wrapping;
+
+const TINY: f64 = 1.0e-300;
+
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn sqrt(x: f64) -> f64 {
+    // On wasm32 we know that LLVM's intrinsic will compile to an optimized
+    // `f64.sqrt` native instruction, so we can leverage this for both code size
+    // and speed.
+    llvm_intrinsically_optimized! {
+        #[cfg(target_arch = "wasm32")] {
+            return if x < 0.0 {
+                f64::NAN
+            } else {
+                unsafe { ::core::intrinsics::sqrtf64(x) }
+            }
+        }
+    }
+    let mut z: f64;
+    let sign: Wrapping<u32> = Wrapping(0x80000000);
+    let mut ix0: i32;
+    let mut s0: i32;
+    let mut q: i32;
+    let mut m: i32;
+    let mut t: i32;
+    let mut i: i32;
+    let mut r: Wrapping<u32>;
+    let mut t1: Wrapping<u32>;
+    let mut s1: Wrapping<u32>;
+    let mut ix1: Wrapping<u32>;
+    let mut q1: Wrapping<u32>;
+
+    ix0 = (x.to_bits() >> 32) as i32;
+    ix1 = Wrapping(x.to_bits() as u32);
+
+    /* take care of Inf and NaN */
+    if (ix0 & 0x7ff00000) == 0x7ff00000 {
+        return x * x + x; /* sqrt(NaN)=NaN, sqrt(+inf)=+inf, sqrt(-inf)=sNaN */
+    }
+    /* take care of zero */
+    if ix0 <= 0 {
+        if ((ix0 & !(sign.0 as i32)) | ix1.0 as i32) == 0 {
+            return x; /* sqrt(+-0) = +-0 */
+        }
+        if ix0 < 0 {
+            return (x - x) / (x - x); /* sqrt(-ve) = sNaN */
+        }
+    }
+    /* normalize x */
+    m = ix0 >> 20;
+    if m == 0 {
+        /* subnormal x */
+        while ix0 == 0 {
+            m -= 21;
+            ix0 |= (ix1 >> 11).0 as i32;
+            ix1 <<= 21;
+        }
+        i = 0;
+        while (ix0 & 0x00100000) == 0 {
+            i += 1;
+            ix0 <<= 1;
+        }
+        m -= i - 1;
+        ix0 |= (ix1 >> (32 - i) as usize).0 as i32;
+        ix1 = ix1 << i as usize;
+    }
+    m -= 1023; /* unbias exponent */
+    ix0 = (ix0 & 0x000fffff) | 0x00100000;
+    if (m & 1) == 1 {
+        /* odd m, double x to make it even */
+        ix0 += ix0 + ((ix1 & sign) >> 31).0 as i32;
+        ix1 += ix1;
+    }
+    m >>= 1; /* m = [m/2] */
+
+    /* generate sqrt(x) bit by bit */
+    ix0 += ix0 + ((ix1 & sign) >> 31).0 as i32;
+    ix1 += ix1;
+    q = 0; /* [q,q1] = sqrt(x) */
+    q1 = Wrapping(0);
+    s0 = 0;
+    s1 = Wrapping(0);
+    r = Wrapping(0x00200000); /* r = moving bit from right to left */
+
+    while r != Wrapping(0) {
+        t = s0 + r.0 as i32;
+        if t <= ix0 {
+            s0 = t + r.0 as i32;
+            ix0 -= t;
+            q += r.0 as i32;
+        }
+        ix0 += ix0 + ((ix1 & sign) >> 31).0 as i32;
+        ix1 += ix1;
+        r >>= 1;
+    }
+
+    r = sign;
+    while r != Wrapping(0) {
+        t1 = s1 + r;
+        t = s0;
+        if t < ix0 || (t == ix0 && t1 <= ix1) {
+            s1 = t1 + r;
+            if (t1 & sign) == sign && (s1 & sign) == Wrapping(0) {
+                s0 += 1;
+            }
+            ix0 -= t;
+            if ix1 < t1 {
+                ix0 -= 1;
+            }
+            ix1 -= t1;
+            q1 += r;
+        }
+        ix0 += ix0 + ((ix1 & sign) >> 31).0 as i32;
+        ix1 += ix1;
+        r >>= 1;
+    }
+
+    /* use floating add to find out rounding direction */
+    if (ix0 as u32 | ix1.0) != 0 {
+        z = 1.0 - TINY; /* raise inexact flag */
+        if z >= 1.0 {
+            z = 1.0 + TINY;
+            if q1.0 == 0xffffffff {
+                q1 = Wrapping(0);
+                q += 1;
+            } else if z > 1.0 {
+                if q1.0 == 0xfffffffe {
+                    q += 1;
+                }
+                q1 += Wrapping(2);
+            } else {
+                q1 += q1 & Wrapping(1);
+            }
+        }
+    }
+    ix0 = (q >> 1) + 0x3fe00000;
+    ix1 = q1 >> 1;
+    if (q & 1) == 1 {
+        ix1 |= sign;
+    }
+    ix0 += m << 20;
+    f64::from_bits((ix0 as u64) << 32 | ix1.0 as u64)
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/sqrtf.rs.html b/src/libm/math/sqrtf.rs.html new file mode 100644 index 000000000..348a68787 --- /dev/null +++ b/src/libm/math/sqrtf.rs.html @@ -0,0 +1,227 @@ +sqrtf.rs.html -- source
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+
+/* origin: FreeBSD /usr/src/lib/msun/src/e_sqrtf.c */
+/*
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ */
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+const TINY: f32 = 1.0e-30;
+
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn sqrtf(x: f32) -> f32 {
+    // On wasm32 we know that LLVM's intrinsic will compile to an optimized
+    // `f32.sqrt` native instruction, so we can leverage this for both code size
+    // and speed.
+    llvm_intrinsically_optimized! {
+        #[cfg(target_arch = "wasm32")] {
+            return if x < 0.0 {
+                ::core::f32::NAN
+            } else {
+                unsafe { ::core::intrinsics::sqrtf32(x) }
+            }
+        }
+    }
+    let mut z: f32;
+    let sign: i32 = 0x80000000u32 as i32;
+    let mut ix: i32;
+    let mut s: i32;
+    let mut q: i32;
+    let mut m: i32;
+    let mut t: i32;
+    let mut i: i32;
+    let mut r: u32;
+
+    ix = x.to_bits() as i32;
+
+    /* take care of Inf and NaN */
+    if (ix as u32 & 0x7f800000) == 0x7f800000 {
+        return x * x + x; /* sqrt(NaN)=NaN, sqrt(+inf)=+inf, sqrt(-inf)=sNaN */
+    }
+
+    /* take care of zero */
+    if ix <= 0 {
+        if (ix & !sign) == 0 {
+            return x; /* sqrt(+-0) = +-0 */
+        }
+        if ix < 0 {
+            return (x - x) / (x - x); /* sqrt(-ve) = sNaN */
+        }
+    }
+
+    /* normalize x */
+    m = ix >> 23;
+    if m == 0 {
+        /* subnormal x */
+        i = 0;
+        while ix & 0x00800000 == 0 {
+            ix <<= 1;
+            i = i + 1;
+        }
+        m -= i - 1;
+    }
+    m -= 127; /* unbias exponent */
+    ix = (ix & 0x007fffff) | 0x00800000;
+    if m & 1 == 1 {
+        /* odd m, double x to make it even */
+        ix += ix;
+    }
+    m >>= 1; /* m = [m/2] */
+
+    /* generate sqrt(x) bit by bit */
+    ix += ix;
+    q = 0;
+    s = 0;
+    r = 0x01000000; /* r = moving bit from right to left */
+
+    while r != 0 {
+        t = s + r as i32;
+        if t <= ix {
+            s = t + r as i32;
+            ix -= t;
+            q += r as i32;
+        }
+        ix += ix;
+        r >>= 1;
+    }
+
+    /* use floating add to find out rounding direction */
+    if ix != 0 {
+        z = 1.0 - TINY; /* raise inexact flag */
+        if z >= 1.0 {
+            z = 1.0 + TINY;
+            if z > 1.0 {
+                q += 2;
+            } else {
+                q += q & 1;
+            }
+        }
+    }
+
+    ix = (q >> 1) + 0x3f000000;
+    ix += m << 23;
+    f32::from_bits(ix as u32)
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/tan.rs.html b/src/libm/math/tan.rs.html new file mode 100644 index 000000000..a7a05be9a --- /dev/null +++ b/src/libm/math/tan.rs.html @@ -0,0 +1,145 @@ +tan.rs.html -- source
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+// origin: FreeBSD /usr/src/lib/msun/src/s_tan.c */
+//
+// ====================================================
+// Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+//
+// Developed at SunPro, a Sun Microsystems, Inc. business.
+// Permission to use, copy, modify, and distribute this
+// software is freely granted, provided that this notice
+// is preserved.
+// ====================================================
+
+use super::{k_tan, rem_pio2};
+
+// tan(x)
+// Return tangent function of x.
+//
+// kernel function:
+//      k_tan           ... tangent function on [-pi/4,pi/4]
+//      rem_pio2        ... argument reduction routine
+//
+// Method.
+//      Let S,C and T denote the sin, cos and tan respectively on
+//      [-PI/4, +PI/4]. Reduce the argument x to y1+y2 = x-k*pi/2
+//      in [-pi/4 , +pi/4], and let n = k mod 4.
+//      We have
+//
+//          n        sin(x)      cos(x)        tan(x)
+//     ----------------------------------------------------------
+//          0          S           C             T
+//          1          C          -S            -1/T
+//          2         -S          -C             T
+//          3         -C           S            -1/T
+//     ----------------------------------------------------------
+//
+// Special cases:
+//      Let trig be any of sin, cos, or tan.
+//      trig(+-INF)  is NaN, with signals;
+//      trig(NaN)    is that NaN;
+//
+// Accuracy:
+//      TRIG(x) returns trig(x) nearly rounded
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn tan(x: f64) -> f64 {
+    let x1p120 = f32::from_bits(0x7b800000); // 0x1p120f === 2 ^ 120
+
+    let ix = (f64::to_bits(x) >> 32) as u32 & 0x7fffffff;
+    /* |x| ~< pi/4 */
+    if ix <= 0x3fe921fb {
+        if ix < 0x3e400000 {
+            /* |x| < 2**-27 */
+            /* raise inexact if x!=0 and underflow if subnormal */
+            force_eval!(if ix < 0x00100000 {
+                x / x1p120 as f64
+            } else {
+                x + x1p120 as f64
+            });
+            return x;
+        }
+        return k_tan(x, 0.0, 0);
+    }
+
+    /* tan(Inf or NaN) is NaN */
+    if ix >= 0x7ff00000 {
+        return x - x;
+    }
+
+    /* argument reduction */
+    let (n, y0, y1) = rem_pio2(x);
+    k_tan(y0, y1, n & 1)
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/tanf.rs.html b/src/libm/math/tanf.rs.html new file mode 100644 index 000000000..9eba1280b --- /dev/null +++ b/src/libm/math/tanf.rs.html @@ -0,0 +1,161 @@ +tanf.rs.html -- source
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+/* origin: FreeBSD /usr/src/lib/msun/src/s_tanf.c */
+/*
+ * Conversion to float by Ian Lance Taylor, Cygnus Support, ian@cygnus.com.
+ * Optimized by Bruce D. Evans.
+ */
+/*
+ * ====================================================
+ * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved.
+ *
+ * Developed at SunPro, a Sun Microsystems, Inc. business.
+ * Permission to use, copy, modify, and distribute this
+ * software is freely granted, provided that this notice
+ * is preserved.
+ * ====================================================
+ */
+
+use super::{k_tanf, rem_pio2f};
+
+use core::f64::consts::FRAC_PI_2;
+
+/* Small multiples of pi/2 rounded to double precision. */
+const T1_PIO2: f64 = 1. * FRAC_PI_2; /* 0x3FF921FB, 0x54442D18 */
+const T2_PIO2: f64 = 2. * FRAC_PI_2; /* 0x400921FB, 0x54442D18 */
+const T3_PIO2: f64 = 3. * FRAC_PI_2; /* 0x4012D97C, 0x7F3321D2 */
+const T4_PIO2: f64 = 4. * FRAC_PI_2; /* 0x401921FB, 0x54442D18 */
+
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn tanf(x: f32) -> f32 {
+    let x64 = x as f64;
+
+    let x1p120 = f32::from_bits(0x7b800000); // 0x1p120f === 2 ^ 120
+
+    let mut ix = x.to_bits();
+    let sign = (ix >> 31) != 0;
+    ix &= 0x7fffffff;
+
+    if ix <= 0x3f490fda {
+        /* |x| ~<= pi/4 */
+        if ix < 0x39800000 {
+            /* |x| < 2**-12 */
+            /* raise inexact if x!=0 and underflow if subnormal */
+            force_eval!(if ix < 0x00800000 {
+                x / x1p120
+            } else {
+                x + x1p120
+            });
+            return x;
+        }
+        return k_tanf(x64, false);
+    }
+    if ix <= 0x407b53d1 {
+        /* |x| ~<= 5*pi/4 */
+        if ix <= 0x4016cbe3 {
+            /* |x| ~<= 3pi/4 */
+            return k_tanf(if sign { x64 + T1_PIO2 } else { x64 - T1_PIO2 }, true);
+        } else {
+            return k_tanf(if sign { x64 + T2_PIO2 } else { x64 - T2_PIO2 }, false);
+        }
+    }
+    if ix <= 0x40e231d5 {
+        /* |x| ~<= 9*pi/4 */
+        if ix <= 0x40afeddf {
+            /* |x| ~<= 7*pi/4 */
+            return k_tanf(if sign { x64 + T3_PIO2 } else { x64 - T3_PIO2 }, true);
+        } else {
+            return k_tanf(if sign { x64 + T4_PIO2 } else { x64 - T4_PIO2 }, false);
+        }
+    }
+
+    /* tan(Inf or NaN) is NaN */
+    if ix >= 0x7f800000 {
+        return x - x;
+    }
+
+    /* argument reduction */
+    let (n, y) = rem_pio2f(x);
+    k_tanf(y, n & 1 != 0)
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/tanh.rs.html b/src/libm/math/tanh.rs.html new file mode 100644 index 000000000..020b92b48 --- /dev/null +++ b/src/libm/math/tanh.rs.html @@ -0,0 +1,111 @@ +tanh.rs.html -- source
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+use super::expm1;
+
+/* tanh(x) = (exp(x) - exp(-x))/(exp(x) + exp(-x))
+ *         = (exp(2*x) - 1)/(exp(2*x) - 1 + 2)
+ *         = (1 - exp(-2*x))/(exp(-2*x) - 1 + 2)
+ */
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn tanh(mut x: f64) -> f64 {
+    let mut uf: f64 = x;
+    let mut ui: u64 = f64::to_bits(uf);
+
+    let w: u32;
+    let sign: bool;
+    let mut t: f64;
+
+    /* x = |x| */
+    sign = ui >> 63 != 0;
+    ui &= !1 / 2;
+    uf = f64::from_bits(ui);
+    x = uf;
+    w = (ui >> 32) as u32;
+
+    if w > 0x3fe193ea {
+        /* |x| > log(3)/2 ~= 0.5493 or nan */
+        if w > 0x40340000 {
+            /* |x| > 20 or nan */
+            /* note: this branch avoids raising overflow */
+            t = 1.0 - 0.0 / x;
+        } else {
+            t = expm1(2.0 * x);
+            t = 1.0 - 2.0 / (t + 2.0);
+        }
+    } else if w > 0x3fd058ae {
+        /* |x| > log(5/3)/2 ~= 0.2554 */
+        t = expm1(2.0 * x);
+        t = t / (t + 2.0);
+    } else if w >= 0x00100000 {
+        /* |x| >= 0x1p-1022, up to 2ulp error in [0.1,0.2554] */
+        t = expm1(-2.0 * x);
+        t = -t / (t + 2.0);
+    } else {
+        /* |x| is subnormal */
+        /* note: the branch above would not raise underflow in [0x1p-1023,0x1p-1022) */
+        force_eval!(x as f32);
+        t = x;
+    }
+
+    if sign {
+        -t
+    } else {
+        t
+    }
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/tanhf.rs.html b/src/libm/math/tanhf.rs.html new file mode 100644 index 000000000..8066b4059 --- /dev/null +++ b/src/libm/math/tanhf.rs.html @@ -0,0 +1,83 @@ +tanhf.rs.html -- source
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+use super::expm1f;
+
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn tanhf(mut x: f32) -> f32 {
+    /* x = |x| */
+    let mut ix = x.to_bits();
+    let sign = (ix >> 31) != 0;
+    ix &= 0x7fffffff;
+    x = f32::from_bits(ix);
+    let w = ix;
+
+    let tt = if w > 0x3f0c9f54 {
+        /* |x| > log(3)/2 ~= 0.5493 or nan */
+        if w > 0x41200000 {
+            /* |x| > 10 */
+            1. + 0. / x
+        } else {
+            let t = expm1f(2. * x);
+            1. - 2. / (t + 2.)
+        }
+    } else if w > 0x3e82c578 {
+        /* |x| > log(5/3)/2 ~= 0.2554 */
+        let t = expm1f(2. * x);
+        t / (t + 2.)
+    } else if w >= 0x00800000 {
+        /* |x| >= 0x1p-126 */
+        let t = expm1f(-2. * x);
+        -t / (t + 2.)
+    } else {
+        /* |x| is subnormal */
+        force_eval!(x * x);
+        x
+    };
+    if sign {
+        -tt
+    } else {
+        tt
+    }
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/tgamma.rs.html b/src/libm/math/tgamma.rs.html new file mode 100644 index 000000000..3751b87e0 --- /dev/null +++ b/src/libm/math/tgamma.rs.html @@ -0,0 +1,417 @@ +tgamma.rs.html -- source
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+
+/*
+"A Precision Approximation of the Gamma Function" - Cornelius Lanczos (1964)
+"Lanczos Implementation of the Gamma Function" - Paul Godfrey (2001)
+"An Analysis of the Lanczos Gamma Approximation" - Glendon Ralph Pugh (2004)
+
+approximation method:
+
+                        (x - 0.5)         S(x)
+Gamma(x) = (x + g - 0.5)         *  ----------------
+                                    exp(x + g - 0.5)
+
+with
+                 a1      a2      a3            aN
+S(x) ~= [ a0 + ----- + ----- + ----- + ... + ----- ]
+               x + 1   x + 2   x + 3         x + N
+
+with a0, a1, a2, a3,.. aN constants which depend on g.
+
+for x < 0 the following reflection formula is used:
+
+Gamma(x)*Gamma(-x) = -pi/(x sin(pi x))
+
+most ideas and constants are from boost and python
+*/
+extern crate core;
+use super::{exp, floor, k_cos, k_sin, pow};
+
+const PI: f64 = 3.141592653589793238462643383279502884;
+
+/* sin(pi x) with x > 0x1p-100, if sin(pi*x)==0 the sign is arbitrary */
+fn sinpi(mut x: f64) -> f64 {
+    let mut n: isize;
+
+    /* argument reduction: x = |x| mod 2 */
+    /* spurious inexact when x is odd int */
+    x = x * 0.5;
+    x = 2.0 * (x - floor(x));
+
+    /* reduce x into [-.25,.25] */
+    n = (4.0 * x) as isize;
+    n = (n + 1) / 2;
+    x -= (n as f64) * 0.5;
+
+    x *= PI;
+    match n {
+        1 => k_cos(x, 0.0),
+        2 => k_sin(-x, 0.0, 0),
+        3 => -k_cos(x, 0.0),
+        0 | _ => k_sin(x, 0.0, 0),
+    }
+}
+
+const N: usize = 12;
+//static const double g = 6.024680040776729583740234375;
+const GMHALF: f64 = 5.524680040776729583740234375;
+const SNUM: [f64; N + 1] = [
+    23531376880.410759688572007674451636754734846804940,
+    42919803642.649098768957899047001988850926355848959,
+    35711959237.355668049440185451547166705960488635843,
+    17921034426.037209699919755754458931112671403265390,
+    6039542586.3520280050642916443072979210699388420708,
+    1439720407.3117216736632230727949123939715485786772,
+    248874557.86205415651146038641322942321632125127801,
+    31426415.585400194380614231628318205362874684987640,
+    2876370.6289353724412254090516208496135991145378768,
+    186056.26539522349504029498971604569928220784236328,
+    8071.6720023658162106380029022722506138218516325024,
+    210.82427775157934587250973392071336271166969580291,
+    2.5066282746310002701649081771338373386264310793408,
+];
+const SDEN: [f64; N + 1] = [
+    0.0,
+    39916800.0,
+    120543840.0,
+    150917976.0,
+    105258076.0,
+    45995730.0,
+    13339535.0,
+    2637558.0,
+    357423.0,
+    32670.0,
+    1925.0,
+    66.0,
+    1.0,
+];
+/* n! for small integer n */
+const FACT: [f64; 23] = [
+    1.0,
+    1.0,
+    2.0,
+    6.0,
+    24.0,
+    120.0,
+    720.0,
+    5040.0,
+    40320.0,
+    362880.0,
+    3628800.0,
+    39916800.0,
+    479001600.0,
+    6227020800.0,
+    87178291200.0,
+    1307674368000.0,
+    20922789888000.0,
+    355687428096000.0,
+    6402373705728000.0,
+    121645100408832000.0,
+    2432902008176640000.0,
+    51090942171709440000.0,
+    1124000727777607680000.0,
+];
+
+/* S(x) rational function for positive x */
+fn s(x: f64) -> f64 {
+    let mut num: f64 = 0.0;
+    let mut den: f64 = 0.0;
+
+    /* to avoid overflow handle large x differently */
+    if x < 8.0 {
+        for i in (0..=N).rev() {
+            num = num * x + SNUM[i];
+            den = den * x + SDEN[i];
+        }
+    } else {
+        for i in 0..=N {
+            num = num / x + SNUM[i];
+            den = den / x + SDEN[i];
+        }
+    }
+    return num / den;
+}
+
+pub fn tgamma(mut x: f64) -> f64 {
+    let u: u64 = x.to_bits();
+    let absx: f64;
+    let mut y: f64;
+    let mut dy: f64;
+    let mut z: f64;
+    let mut r: f64;
+    let ix: u32 = ((u >> 32) as u32) & 0x7fffffff;
+    let sign: bool = (u >> 63) != 0;
+
+    /* special cases */
+    if ix >= 0x7ff00000 {
+        /* tgamma(nan)=nan, tgamma(inf)=inf, tgamma(-inf)=nan with invalid */
+        return x + core::f64::INFINITY;
+    }
+    if ix < ((0x3ff - 54) << 20) {
+        /* |x| < 2^-54: tgamma(x) ~ 1/x, +-0 raises div-by-zero */
+        return 1.0 / x;
+    }
+
+    /* integer arguments */
+    /* raise inexact when non-integer */
+    if x == floor(x) {
+        if sign {
+            return 0.0 / 0.0;
+        }
+        if x <= FACT.len() as f64 {
+            return FACT[(x as usize) - 1];
+        }
+    }
+
+    /* x >= 172: tgamma(x)=inf with overflow */
+    /* x =< -184: tgamma(x)=+-0 with underflow */
+    if ix >= 0x40670000 {
+        /* |x| >= 184 */
+        if sign {
+            let x1p_126 = f64::from_bits(0x3810000000000000); // 0x1p-126 == 2^-126
+            force_eval!((x1p_126 / x) as f32);
+            if floor(x) * 0.5 == floor(x * 0.5) {
+                return 0.0;
+            } else {
+                return -0.0;
+            }
+        }
+        let x1p1023 = f64::from_bits(0x7fe0000000000000); // 0x1p1023 == 2^1023
+        x *= x1p1023;
+        return x;
+    }
+
+    absx = if sign { -x } else { x };
+
+    /* handle the error of x + g - 0.5 */
+    y = absx + GMHALF;
+    if absx > GMHALF {
+        dy = y - absx;
+        dy -= GMHALF;
+    } else {
+        dy = y - GMHALF;
+        dy -= absx;
+    }
+
+    z = absx - 0.5;
+    r = s(absx) * exp(-y);
+    if x < 0.0 {
+        /* reflection formula for negative x */
+        /* sinpi(absx) is not 0, integers are already handled */
+        r = -PI / (sinpi(absx) * absx * r);
+        dy = -dy;
+        z = -z;
+    }
+    r += dy * (GMHALF + 0.5) * r / y;
+    z = pow(y, 0.5 * z);
+    y = r * z * z;
+    return y;
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/tgammaf.rs.html b/src/libm/math/tgammaf.rs.html new file mode 100644 index 000000000..cba6c5435 --- /dev/null +++ b/src/libm/math/tgammaf.rs.html @@ -0,0 +1,13 @@ +tgammaf.rs.html -- source
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+use super::tgamma;
+
+pub fn tgammaf(x: f32) -> f32 {
+    tgamma(x as f64) as f32
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/trunc.rs.html b/src/libm/math/trunc.rs.html new file mode 100644 index 000000000..cf67f2344 --- /dev/null +++ b/src/libm/math/trunc.rs.html @@ -0,0 +1,85 @@ +trunc.rs.html -- source
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+use core::f64;
+
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn trunc(x: f64) -> f64 {
+    // On wasm32 we know that LLVM's intrinsic will compile to an optimized
+    // `f64.trunc` native instruction, so we can leverage this for both code size
+    // and speed.
+    llvm_intrinsically_optimized! {
+        #[cfg(target_arch = "wasm32")] {
+            return unsafe { ::core::intrinsics::truncf64(x) }
+        }
+    }
+    let x1p120 = f64::from_bits(0x4770000000000000); // 0x1p120f === 2 ^ 120
+
+    let mut i: u64 = x.to_bits();
+    let mut e: i64 = (i >> 52 & 0x7ff) as i64 - 0x3ff + 12;
+    let m: u64;
+
+    if e >= 52 + 12 {
+        return x;
+    }
+    if e < 12 {
+        e = 1;
+    }
+    m = -1i64 as u64 >> e;
+    if (i & m) == 0 {
+        return x;
+    }
+    force_eval!(x + x1p120);
+    i &= !m;
+    f64::from_bits(i)
+}
+
+#[cfg(test)]
+mod tests {
+    #[test]
+    fn sanity_check() {
+        assert_eq!(super::trunc(1.1), 1.0);
+    }
+}
+
+
\ No newline at end of file diff --git a/src/libm/math/truncf.rs.html b/src/libm/math/truncf.rs.html new file mode 100644 index 000000000..6e02a1225 --- /dev/null +++ b/src/libm/math/truncf.rs.html @@ -0,0 +1,85 @@ +truncf.rs.html -- source
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+use core::f32;
+
+#[inline]
+#[cfg_attr(all(test, assert_no_panic), no_panic::no_panic)]
+pub fn truncf(x: f32) -> f32 {
+    // On wasm32 we know that LLVM's intrinsic will compile to an optimized
+    // `f32.trunc` native instruction, so we can leverage this for both code size
+    // and speed.
+    llvm_intrinsically_optimized! {
+        #[cfg(target_arch = "wasm32")] {
+            return unsafe { ::core::intrinsics::truncf32(x) }
+        }
+    }
+    let x1p120 = f32::from_bits(0x7b800000); // 0x1p120f === 2 ^ 120
+
+    let mut i: u32 = x.to_bits();
+    let mut e: i32 = (i >> 23 & 0xff) as i32 - 0x7f + 9;
+    let m: u32;
+
+    if e >= 23 + 9 {
+        return x;
+    }
+    if e < 9 {
+        e = 1;
+    }
+    m = -1i32 as u32 >> e;
+    if (i & m) == 0 {
+        return x;
+    }
+    force_eval!(x + x1p120);
+    i &= !m;
+    f32::from_bits(i)
+}
+
+#[cfg(test)]
+mod tests {
+    #[test]
+    fn sanity_check() {
+        assert_eq!(super::truncf(1.1), 1.0);
+    }
+}
+
+
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+
+//! Implements the Simd<[T; N]> APIs
+
+#[macro_use]
+mod bitmask;
+crate mod cast;
+#[macro_use]
+mod cmp;
+#[macro_use]
+mod default;
+#[macro_use]
+mod fmt;
+#[macro_use]
+mod from;
+#[macro_use]
+mod hash;
+#[macro_use]
+mod math;
+#[macro_use]
+mod minimal;
+#[macro_use]
+mod ops;
+#[macro_use]
+mod ptr;
+#[macro_use]
+mod reductions;
+#[macro_use]
+mod select;
+#[macro_use]
+mod shuffle;
+#[macro_use]
+mod shuffle1_dyn;
+#[macro_use]
+mod slice;
+#[macro_use]
+mod swap_bytes;
+#[macro_use]
+mod bit_manip;
+
+#[cfg(feature = "into_bits")]
+crate mod into_bits;
+
+macro_rules! impl_i {
+    ([$elem_ty:ident; $elem_n:expr]: $tuple_id:ident, $mask_ty:ident
+     | $ielem_ty:ident, $ibitmask_ty:ident | $test_tt:tt | $($elem_ids:ident),*
+     | From: $($from_vec_ty:ident),* | $(#[$doc:meta])*) => {
+        impl_minimal_iuf!([$elem_ty; $elem_n]: $tuple_id | $ielem_ty | $test_tt
+                          | $($elem_ids),* | $(#[$doc])*);
+        impl_ops_vector_arithmetic!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_ops_scalar_arithmetic!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_ops_vector_bitwise!(
+            [$elem_ty; $elem_n]: $tuple_id | $test_tt | (!(0 as $elem_ty), 0)
+        );
+        impl_ops_scalar_bitwise!(
+            [$elem_ty; $elem_n]: $tuple_id | $test_tt | (!(0 as $elem_ty), 0)
+        );
+        impl_ops_vector_shifts!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_ops_scalar_shifts!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_ops_vector_rotates!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_ops_vector_neg!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_ops_vector_int_min_max!(
+            [$elem_ty; $elem_n]: $tuple_id | $test_tt
+        );
+        impl_reduction_integer_arithmetic!(
+            [$elem_ty; $elem_n]: $tuple_id | $ielem_ty | $test_tt
+        );
+        impl_reduction_min_max!(
+            [$elem_ty; $elem_n]: $tuple_id | $ielem_ty | $test_tt
+        );
+        impl_reduction_bitwise!(
+            [$elem_ty; $elem_n]: $tuple_id | $ielem_ty | $test_tt
+            | (|x|{ x as $elem_ty }) | (!(0 as $elem_ty), 0)
+        );
+        impl_fmt_debug!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_fmt_lower_hex!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_fmt_upper_hex!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_fmt_octal!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_fmt_binary!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_from_array!([$elem_ty; $elem_n]: $tuple_id | $test_tt | (1, 1));
+        impl_from_vectors!(
+            [$elem_ty; $elem_n]: $tuple_id | $test_tt | $($from_vec_ty),*
+        );
+        impl_default!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_hash!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_slice_from_slice!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_slice_write_to_slice!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_swap_bytes!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_bit_manip!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_shuffle1_dyn!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_cmp_partial_eq!(
+            [$elem_ty; $elem_n]: $tuple_id | $test_tt | (0, 1)
+        );
+        impl_cmp_eq!([$elem_ty; $elem_n]: $tuple_id | $test_tt | (0, 1));
+        impl_cmp_vertical!(
+            [$elem_ty; $elem_n]: $tuple_id, $mask_ty, false, (1, 0) | $test_tt
+        );
+        impl_cmp_partial_ord!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_cmp_ord!([$elem_ty; $elem_n]: $tuple_id | $test_tt | (0, 1));
+        impl_bitmask!($tuple_id | $ibitmask_ty | (-1, 0) | $test_tt);
+
+        test_select!($elem_ty, $mask_ty, $tuple_id, (1, 2) | $test_tt);
+        test_cmp_partial_ord_int!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        test_shuffle1_dyn!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+    }
+}
+
+macro_rules! impl_u {
+    ([$elem_ty:ident; $elem_n:expr]: $tuple_id:ident, $mask_ty:ident
+     | $ielem_ty:ident, $ibitmask_ty:ident | $test_tt:tt | $($elem_ids:ident),*
+     | From: $($from_vec_ty:ident),* | $(#[$doc:meta])*) => {
+        impl_minimal_iuf!([$elem_ty; $elem_n]: $tuple_id | $ielem_ty | $test_tt
+                          | $($elem_ids),* | $(#[$doc])*);
+        impl_ops_vector_arithmetic!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_ops_scalar_arithmetic!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_ops_vector_bitwise!(
+            [$elem_ty; $elem_n]: $tuple_id | $test_tt | (!(0 as $elem_ty), 0)
+        );
+        impl_ops_scalar_bitwise!(
+            [$elem_ty; $elem_n]: $tuple_id | $test_tt | (!(0 as $elem_ty), 0)
+        );
+        impl_ops_vector_shifts!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_ops_scalar_shifts!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_ops_vector_rotates!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_ops_vector_int_min_max!(
+            [$elem_ty; $elem_n]: $tuple_id | $test_tt
+        );
+        impl_reduction_integer_arithmetic!(
+            [$elem_ty; $elem_n]: $tuple_id | $ielem_ty | $test_tt
+        );
+        impl_reduction_min_max!(
+            [$elem_ty; $elem_n]: $tuple_id | $ielem_ty | $test_tt
+        );
+        impl_reduction_bitwise!(
+            [$elem_ty; $elem_n]: $tuple_id | $ielem_ty | $test_tt
+            | (|x|{ x as $elem_ty }) | (!(0 as $elem_ty), 0)
+        );
+        impl_fmt_debug!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_fmt_lower_hex!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_fmt_upper_hex!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_fmt_octal!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_fmt_binary!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_from_array!([$elem_ty; $elem_n]: $tuple_id | $test_tt | (1, 1));
+        impl_from_vectors!(
+            [$elem_ty; $elem_n]: $tuple_id | $test_tt | $($from_vec_ty),*
+        );
+        impl_default!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_hash!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_slice_from_slice!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_slice_write_to_slice!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_swap_bytes!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_bit_manip!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_shuffle1_dyn!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_cmp_partial_eq!(
+            [$elem_ty; $elem_n]: $tuple_id | $test_tt | (1, 0)
+        );
+        impl_cmp_eq!([$elem_ty; $elem_n]: $tuple_id | $test_tt | (0, 1));
+        impl_cmp_vertical!(
+            [$elem_ty; $elem_n]: $tuple_id, $mask_ty, false, (1, 0) | $test_tt
+        );
+        impl_cmp_partial_ord!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_cmp_ord!([$elem_ty; $elem_n]: $tuple_id | $test_tt | (0, 1));
+        impl_bitmask!($tuple_id | $ibitmask_ty | ($ielem_ty::max_value(), 0) |
+                      $test_tt);
+
+        test_select!($elem_ty, $mask_ty, $tuple_id, (1, 2) | $test_tt);
+        test_cmp_partial_ord_int!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        test_shuffle1_dyn!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+    }
+}
+
+macro_rules! impl_f {
+    ([$elem_ty:ident; $elem_n:expr]: $tuple_id:ident, $mask_ty:ident
+     | $ielem_ty:ident | $test_tt:tt | $($elem_ids:ident),*
+     | From: $($from_vec_ty:ident),* | $(#[$doc:meta])*) => {
+        impl_minimal_iuf!([$elem_ty; $elem_n]: $tuple_id | $ielem_ty | $test_tt
+                          | $($elem_ids),* | $(#[$doc])*);
+        impl_ops_vector_arithmetic!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_ops_scalar_arithmetic!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_ops_vector_neg!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_ops_vector_float_min_max!(
+            [$elem_ty; $elem_n]: $tuple_id | $test_tt
+        );
+        impl_reduction_float_arithmetic!(
+            [$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_reduction_min_max!(
+            [$elem_ty; $elem_n]: $tuple_id | $ielem_ty | $test_tt
+        );
+        impl_fmt_debug!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_from_array!([$elem_ty; $elem_n]: $tuple_id | $test_tt | (1., 1.));
+        impl_from_vectors!(
+            [$elem_ty; $elem_n]: $tuple_id | $test_tt | $($from_vec_ty),*
+        );
+        impl_default!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_cmp_partial_eq!(
+            [$elem_ty; $elem_n]: $tuple_id | $test_tt | (1., 0.)
+        );
+        impl_slice_from_slice!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_slice_write_to_slice!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_shuffle1_dyn!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+
+        impl_float_consts!([$elem_ty; $elem_n]: $tuple_id);
+        impl_float_category!([$elem_ty; $elem_n]: $tuple_id, $mask_ty);
+
+        // floating-point math
+        impl_math_float_abs!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_math_float_cos!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_math_float_exp!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_math_float_ln!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_math_float_mul_add!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_math_float_mul_adde!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_math_float_powf!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_math_float_recpre!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_math_float_rsqrte!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_math_float_sin!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_math_float_sqrt!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_math_float_sqrte!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_math_float_tanh!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_cmp_vertical!(
+            [$elem_ty; $elem_n]: $tuple_id, $mask_ty, false, (1., 0.)
+                | $test_tt
+        );
+
+        test_select!($elem_ty, $mask_ty, $tuple_id, (1., 2.) | $test_tt);
+        test_reduction_float_min_max!(
+            [$elem_ty; $elem_n]: $tuple_id | $test_tt
+        );
+        test_shuffle1_dyn!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+    }
+}
+
+macro_rules! impl_m {
+    ([$elem_ty:ident; $elem_n:expr]: $tuple_id:ident
+     | $ielem_ty:ident, $ibitmask_ty:ident
+     | $test_tt:tt | $($elem_ids:ident),* | From: $($from_vec_ty:ident),*
+     | $(#[$doc:meta])*) => {
+        impl_minimal_mask!(
+            [$elem_ty; $elem_n]: $tuple_id | $ielem_ty | $test_tt
+            | $($elem_ids),* | $(#[$doc])*
+        );
+        impl_ops_vector_mask_bitwise!(
+            [$elem_ty; $elem_n]: $tuple_id | $test_tt | (true, false)
+        );
+        impl_ops_scalar_mask_bitwise!(
+            [$elem_ty; $elem_n]: $tuple_id | $test_tt | (true, false)
+        );
+        impl_reduction_bitwise!(
+            [bool; $elem_n]: $tuple_id | $ielem_ty | $test_tt
+                | (|x|{ x != 0 }) | (true, false)
+        );
+        impl_reduction_mask!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_fmt_debug!([bool; $elem_n]: $tuple_id | $test_tt);
+        impl_from_array!(
+            [$elem_ty; $elem_n]: $tuple_id | $test_tt
+            | (crate::$elem_ty::new(true), true)
+        );
+        impl_from_vectors!(
+            [$elem_ty; $elem_n]: $tuple_id | $test_tt | $($from_vec_ty),*
+        );
+        impl_default!([bool; $elem_n]: $tuple_id | $test_tt);
+        impl_cmp_partial_eq!(
+            [$elem_ty; $elem_n]: $tuple_id | $test_tt | (true, false)
+        );
+        impl_cmp_eq!(
+            [$elem_ty; $elem_n]: $tuple_id | $test_tt | (true, false)
+        );
+        impl_cmp_vertical!(
+            [$elem_ty; $elem_n]: $tuple_id, $tuple_id, true, (true, false)
+            | $test_tt
+        );
+        impl_select!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_cmp_partial_ord!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_cmp_ord!(
+            [$elem_ty; $elem_n]: $tuple_id | $test_tt | (false, true)
+        );
+        impl_shuffle1_dyn!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        impl_bitmask!($tuple_id | $ibitmask_ty | (true, false) | $test_tt);
+
+        test_cmp_partial_ord_mask!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+        test_shuffle1_dyn_mask!([$elem_ty; $elem_n]: $tuple_id | $test_tt);
+    }
+}
+
+macro_rules! impl_const_p {
+    ([$elem_ty:ty; $elem_n:expr]: $tuple_id:ident, $mask_ty:ident,
+     $usize_ty:ident, $isize_ty:ident
+     | $test_tt:tt | $($elem_ids:ident),*
+     | From: $($from_vec_ty:ident),* | $(#[$doc:meta])*) => {
+        impl_minimal_p!(
+            [$elem_ty; $elem_n]: $tuple_id, $mask_ty, $usize_ty, $isize_ty
+                | ref_ | $test_tt | $($elem_ids),*
+                | (1 as $elem_ty, 0 as $elem_ty) | $(#[$doc])*
+        );
+        impl_ptr_read!([$elem_ty; $elem_n]: $tuple_id, $mask_ty | $test_tt);
+    }
+}
+
+macro_rules! impl_mut_p {
+    ([$elem_ty:ty; $elem_n:expr]: $tuple_id:ident, $mask_ty:ident,
+     $usize_ty:ident, $isize_ty:ident
+     | $test_tt:tt | $($elem_ids:ident),*
+     | From: $($from_vec_ty:ident),* | $(#[$doc:meta])*) => {
+        impl_minimal_p!(
+            [$elem_ty; $elem_n]: $tuple_id, $mask_ty, $usize_ty, $isize_ty
+                | ref_mut_ | $test_tt | $($elem_ids),*
+                | (1 as $elem_ty, 0 as $elem_ty) | $(#[$doc])*
+        );
+        impl_ptr_read!([$elem_ty; $elem_n]: $tuple_id, $mask_ty | $test_tt);
+        impl_ptr_write!([$elem_ty; $elem_n]: $tuple_id, $mask_ty | $test_tt);
+    }
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/bit_manip.rs.html b/src/packed_simd/api/bit_manip.rs.html new file mode 100644 index 000000000..efc042592 --- /dev/null +++ b/src/packed_simd/api/bit_manip.rs.html @@ -0,0 +1,259 @@ +bit_manip.rs.html -- source
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+
+//! Bit manipulations.
+
+macro_rules! impl_bit_manip {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident | $test_tt:tt) => {
+        impl $id {
+            /// Returns the number of ones in the binary representation of
+            /// the lanes of `self`.
+            #[inline]
+            pub fn count_ones(self) -> Self {
+                super::codegen::bit_manip::BitManip::ctpop(self)
+            }
+
+            /// Returns the number of zeros in the binary representation of
+            /// the lanes of `self`.
+            #[inline]
+            pub fn count_zeros(self) -> Self {
+                super::codegen::bit_manip::BitManip::ctpop(!self)
+            }
+
+            /// Returns the number of leading zeros in the binary
+            /// representation of the lanes of `self`.
+            #[inline]
+            pub fn leading_zeros(self) -> Self {
+                super::codegen::bit_manip::BitManip::ctlz(self)
+            }
+
+            /// Returns the number of trailing zeros in the binary
+            /// representation of the lanes of `self`.
+            #[inline]
+            pub fn trailing_zeros(self) -> Self {
+                super::codegen::bit_manip::BitManip::cttz(self)
+            }
+        }
+
+        test_if! {
+            $test_tt:
+            paste::item_with_macros! {
+                #[allow(overflowing_literals)]
+                pub mod [<$id _bit_manip>] {
+                    use super::*;
+
+                    const LANE_WIDTH: usize = mem::size_of::<$elem_ty>() * 8;
+
+                    macro_rules! test_func {
+                        ($x:expr, $func:ident) => {{
+                            let mut actual = $x;
+                            for i in 0..$id::lanes() {
+                                actual = actual.replace(
+                                    i,
+                                    $x.extract(i).$func() as $elem_ty
+                                );
+                            }
+                            let expected = $x.$func();
+                            assert_eq!(actual, expected);
+                        }};
+                    }
+
+                    const BYTES: [u8; 64] = [
+                        0, 1, 2, 3, 4, 5, 6, 7,
+                        8, 9, 10, 11, 12, 13, 14, 15,
+                        16, 17, 18, 19, 20, 21, 22, 23,
+                        24, 25, 26, 27, 28, 29, 30, 31,
+                        32, 33, 34, 35, 36, 37, 38, 39,
+                        40, 41, 42, 43, 44, 45, 46, 47,
+                        48, 49, 50, 51, 52, 53, 54, 55,
+                        56, 57, 58, 59, 60, 61, 62, 63,
+                    ];
+
+                    fn load_bytes() -> $id {
+                        let elems: &mut [$elem_ty] = unsafe {
+                            slice::from_raw_parts_mut(
+                                BYTES.as_mut_ptr() as *mut $elem_ty,
+                                $id::lanes(),
+                            )
+                        };
+                        $id::from_slice_unaligned(elems)
+                    }
+
+                    #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn count_ones() {
+                        test_func!($id::splat(0), count_ones);
+                        test_func!($id::splat(!0), count_ones);
+                        test_func!(load_bytes(), count_ones);
+                    }
+
+                    #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn count_zeros() {
+                        test_func!($id::splat(0), count_zeros);
+                        test_func!($id::splat(!0), count_zeros);
+                        test_func!(load_bytes(), count_zeros);
+                    }
+
+                    #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn leading_zeros() {
+                        test_func!($id::splat(0), leading_zeros);
+                        test_func!($id::splat(1), leading_zeros);
+                        // some implementations use `pshufb` which has unique
+                        // behavior when the 8th bit is set.
+                        test_func!($id::splat(0b1000_0010), leading_zeros);
+                        test_func!($id::splat(!0), leading_zeros);
+                        test_func!(
+                            $id::splat(1 << (LANE_WIDTH - 1)),
+                            leading_zeros
+                        );
+                        test_func!(load_bytes(), leading_zeros);
+                    }
+
+                    #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn trailing_zeros() {
+                        test_func!($id::splat(0), trailing_zeros);
+                        test_func!($id::splat(1), trailing_zeros);
+                        test_func!($id::splat(0b1000_0010), trailing_zeros);
+                        test_func!($id::splat(!0), trailing_zeros);
+                        test_func!(
+                            $id::splat(1 << (LANE_WIDTH - 1)),
+                            trailing_zeros
+                        );
+                        test_func!(load_bytes(), trailing_zeros);
+                    }
+                }
+            }
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/bitmask.rs.html b/src/packed_simd/api/bitmask.rs.html new file mode 100644 index 000000000..63bcdc7a5 --- /dev/null +++ b/src/packed_simd/api/bitmask.rs.html @@ -0,0 +1,167 @@ +bitmask.rs.html -- source
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+//! Bitmask API
+
+macro_rules! impl_bitmask {
+    ($id:ident | $ibitmask_ty:ident | ($set:expr, $clear:expr)
+     | $test_tt:tt) => {
+        impl $id {
+            /// Creates a bitmask with the MSB of each vector lane.
+            ///
+            /// If the vector has less than 8 lanes, the bits that do not
+            /// correspond to any vector lanes are cleared.
+            #[inline]
+            pub fn bitmask(self) -> $ibitmask_ty {
+                unsafe { codegen::llvm::simd_bitmask(self.0) }
+            }
+        }
+
+        test_if! {
+            $test_tt:
+            paste::item! {
+                #[cfg(not(any(
+                    // FIXME: https://github.com/rust-lang-nursery/packed_simd/issues/210
+                    all(target_arch = "mips", target_endian = "big"),
+                    all(target_arch = "mips64", target_endian = "big"),
+                    target_arch = "sparc64",
+                    target_arch = "s390x",
+                )))]
+                pub mod [<$id _bitmask>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn bitmask() {
+                        // clear all lanes
+                        let vec = $id::splat($clear as _);
+                        let bitmask: $ibitmask_ty = 0;
+                        assert_eq!(vec.bitmask(), bitmask);
+
+                        // set even lanes
+                        let mut vec = $id::splat($clear as _);
+                        for i in 0..$id::lanes() {
+                            if i % 2 == 0 {
+                                vec = vec.replace(i, $set as _);
+                            }
+                        }
+                        // create bitmask with even lanes set:
+                        let mut bitmask: $ibitmask_ty = 0;
+                        for i in 0..$id::lanes() {
+                            if i % 2 == 0 {
+                                bitmask |= 1 << i;
+                            }
+                        }
+                        assert_eq!(vec.bitmask(), bitmask);
+
+
+                        // set odd lanes
+                        let mut vec = $id::splat($clear as _);
+                        for i in 0..$id::lanes() {
+                            if i % 2 != 0 {
+                                vec = vec.replace(i, $set as _);
+                            }
+                        }
+                        // create bitmask with odd lanes set:
+                        let mut bitmask: $ibitmask_ty = 0;
+                        for i in 0..$id::lanes() {
+                            if i % 2 != 0 {
+                                bitmask |= 1 << i;
+                            }
+                        }
+                        assert_eq!(vec.bitmask(), bitmask);
+
+                        // set all lanes
+                        let vec = $id::splat($set as _);
+                        let mut bitmask: $ibitmask_ty = 0;
+                        for i in 0..$id::lanes() {
+                            bitmask |= 1 << i;
+                        }
+                        assert_eq!(vec.bitmask(), bitmask);
+                    }
+                }
+            }
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/cast.rs.html b/src/packed_simd/api/cast.rs.html new file mode 100644 index 000000000..00ef828a7 --- /dev/null +++ b/src/packed_simd/api/cast.rs.html @@ -0,0 +1,219 @@ +cast.rs.html -- source
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+
+//! Implementation of `FromCast` and `IntoCast`.
+#![allow(clippy::module_name_repetitions)]
+
+/// Numeric cast from `T` to `Self`.
+///
+/// > Note: This is a temporary workaround until the conversion traits
+/// specified > in [RFC2484] are implemented.
+///
+/// Numeric cast between vectors with the same number of lanes, such that:
+///
+/// * casting integer vectors whose lane types have the same size (e.g. `i32xN`
+/// -> `u32xN`) is a **no-op**,
+///
+/// * casting from a larger integer to a smaller integer (e.g. `u32xN` ->
+/// `u8xN`) will **truncate**,
+///
+/// * casting from a smaller integer to a larger integer   (e.g. `u8xN` ->
+///   `u32xN`) will:
+///    * **zero-extend** if the source is unsigned, or
+///    * **sign-extend** if the source is signed,
+///
+/// * casting from a float to an integer will **round the float towards zero**,
+///
+/// * casting from an integer to float will produce the floating point
+/// representation of the integer, **rounding to nearest, ties to even**,
+///
+/// * casting from an `f32` to an `f64` is perfect and lossless,
+///
+/// * casting from an `f64` to an `f32` **rounds to nearest, ties to even**.
+///
+/// [RFC2484]: https://github.com/rust-lang/rfcs/pull/2484
+pub trait FromCast<T>: crate::marker::Sized {
+    /// Numeric cast from `T` to `Self`.
+    fn from_cast(_: T) -> Self;
+}
+
+/// Numeric cast from `Self` to `T`.
+///
+/// > Note: This is a temporary workaround until the conversion traits
+/// specified > in [RFC2484] are implemented.
+///
+/// Numeric cast between vectors with the same number of lanes, such that:
+///
+/// * casting integer vectors whose lane types have the same size (e.g. `i32xN`
+/// -> `u32xN`) is a **no-op**,
+///
+/// * casting from a larger integer to a smaller integer (e.g. `u32xN` ->
+/// `u8xN`) will **truncate**,
+///
+/// * casting from a smaller integer to a larger integer   (e.g. `u8xN` ->
+///   `u32xN`) will:
+///    * **zero-extend** if the source is unsigned, or
+///    * **sign-extend** if the source is signed,
+///
+/// * casting from a float to an integer will **round the float towards zero**,
+///
+/// * casting from an integer to float will produce the floating point
+/// representation of the integer, **rounding to nearest, ties to even**,
+///
+/// * casting from an `f32` to an `f64` is perfect and lossless,
+///
+/// * casting from an `f64` to an `f32` **rounds to nearest, ties to even**.
+///
+/// [RFC2484]: https://github.com/rust-lang/rfcs/pull/2484
+pub trait Cast<T>: crate::marker::Sized {
+    /// Numeric cast from `self` to `T`.
+    fn cast(self) -> T;
+}
+
+/// `FromCast` implies `Cast`.
+impl<T, U> Cast<U> for T
+where
+    U: FromCast<T>,
+{
+    #[inline]
+    fn cast(self) -> U {
+        U::from_cast(self)
+    }
+}
+
+/// `FromCast` and `Cast` are reflexive
+impl<T> FromCast<T> for T {
+    #[inline]
+    fn from_cast(t: Self) -> Self {
+        t
+    }
+}
+
+#[macro_use]
+mod macros;
+
+mod v16;
+pub use self::v16::*;
+
+mod v32;
+pub use self::v32::*;
+
+mod v64;
+pub use self::v64::*;
+
+mod v128;
+pub use self::v128::*;
+
+mod v256;
+pub use self::v256::*;
+
+mod v512;
+pub use self::v512::*;
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/cast/macros.rs.html b/src/packed_simd/api/cast/macros.rs.html new file mode 100644 index 000000000..99ce4d8f6 --- /dev/null +++ b/src/packed_simd/api/cast/macros.rs.html @@ -0,0 +1,167 @@ +macros.rs.html -- source
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+
+//! Macros implementing `FromCast`
+
+macro_rules! impl_from_cast_ {
+    ($id:ident[$test_tt:tt]: $from_ty:ident) => {
+        impl crate::api::cast::FromCast<$from_ty> for $id {
+            #[inline]
+            fn from_cast(x: $from_ty) -> Self {
+                use crate::llvm::simd_cast;
+                debug_assert_eq!($from_ty::lanes(), $id::lanes());
+                Simd(unsafe { simd_cast(x.0) })
+            }
+        }
+
+        test_if!{
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _from_cast_ $from_ty>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn test() {
+                        assert_eq!($id::lanes(), $from_ty::lanes());
+                    }
+                }
+            }
+        }
+    };
+}
+
+macro_rules! impl_from_cast {
+    ($id:ident[$test_tt:tt]: $($from_ty:ident),*) => {
+        $(
+            impl_from_cast_!($id[$test_tt]: $from_ty);
+        )*
+    }
+}
+
+macro_rules! impl_from_cast_mask_ {
+    ($id:ident[$test_tt:tt]: $from_ty:ident) => {
+        impl crate::api::cast::FromCast<$from_ty> for $id {
+            #[inline]
+            fn from_cast(x: $from_ty) -> Self {
+                debug_assert_eq!($from_ty::lanes(), $id::lanes());
+                x.ne($from_ty::default())
+                    .select($id::splat(true), $id::splat(false))
+            }
+        }
+
+        test_if!{
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _from_cast_ $from_ty>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn test() {
+                        assert_eq!($id::lanes(), $from_ty::lanes());
+
+                        let x = $from_ty::default();
+                        let m: $id = x.cast();
+                        assert!(m.none());
+                    }
+                }
+            }
+        }
+    };
+}
+
+macro_rules! impl_from_cast_mask {
+    ($id:ident[$test_tt:tt]: $($from_ty:ident),*) => {
+        $(
+            impl_from_cast_mask_!($id[$test_tt]: $from_ty);
+        )*
+    }
+}
+
+#[allow(unused)]
+macro_rules! impl_into_cast {
+    ($id:ident[$test_tt:tt]: $($from_ty:ident),*) => {
+        $(
+            impl_from_cast_!($from_ty[$test_tt]: $id);
+        )*
+    }
+}
+
+
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+
+//! `FromCast` and `IntoCast` implementations for portable 128-bit wide vectors
+#![rustfmt::skip]
+
+use crate::*;
+
+impl_from_cast!(
+    i8x16[test_v128]: u8x16, m8x16, i16x16, u16x16, m16x16, i32x16, u32x16, f32x16, m32x16
+);
+impl_from_cast!(
+    u8x16[test_v128]: i8x16, m8x16, i16x16, u16x16, m16x16, i32x16, u32x16, f32x16, m32x16
+);
+impl_from_cast_mask!(
+    m8x16[test_v128]: i8x16, u8x16, i16x16, u16x16, m16x16, i32x16, u32x16, f32x16, m32x16
+);
+
+impl_from_cast!(
+    i16x8[test_v128]: i8x8, u8x8, m8x8, u16x8, m16x8, i32x8, u32x8, f32x8, m32x8,
+    i64x8, u64x8, f64x8, m64x8, isizex8, usizex8, msizex8
+);
+impl_from_cast!(
+    u16x8[test_v128]: i8x8, u8x8, m8x8, i16x8, m16x8, i32x8, u32x8, f32x8, m32x8,
+    i64x8, u64x8, f64x8, m64x8, isizex8, usizex8, msizex8
+);
+impl_from_cast_mask!(
+    m16x8[test_v128]: i8x8, u8x8, m8x8, i16x8, u16x8, i32x8, u32x8, f32x8, m32x8,
+    i64x8, u64x8, f64x8, m64x8, isizex8, usizex8, msizex8
+);
+
+impl_from_cast!(
+    i32x4[test_v128]: i8x4, u8x4, m8x4, i16x4, u16x4, m16x4, u32x4, f32x4, m32x4,
+    i64x4, u64x4, f64x4, m64x4, i128x4, u128x4, m128x4, isizex4, usizex4, msizex4
+);
+impl_from_cast!(
+    u32x4[test_v128]: i8x4, u8x4, m8x4, i16x4, u16x4, m16x4, i32x4, f32x4, m32x4,
+    i64x4, u64x4, f64x4, m64x4, i128x4, u128x4, m128x4, isizex4, usizex4, msizex4
+);
+impl_from_cast!(
+    f32x4[test_v128]: i8x4, u8x4, m8x4, i16x4, u16x4, m16x4, i32x4, u32x4, m32x4,
+    i64x4, u64x4, f64x4, m64x4, i128x4, u128x4, m128x4, isizex4, usizex4, msizex4
+);
+impl_from_cast_mask!(
+    m32x4[test_v128]: i8x4, u8x4, m8x4, i16x4, u16x4, m16x4, i32x4, u32x4, f32x4,
+    i64x4, u64x4, f64x4, m64x4, i128x4, u128x4, m128x4, isizex4, usizex4, msizex4
+);
+
+impl_from_cast!(
+    i64x2[test_v128]: i8x2, u8x2, m8x2, i16x2, u16x2, m16x2, i32x2, u32x2, f32x2, m32x2,
+    u64x2, f64x2, m64x2, i128x2, u128x2, m128x2, isizex2, usizex2, msizex2
+);
+impl_from_cast!(
+    u64x2[test_v128]: i8x2, u8x2, m8x2, i16x2, u16x2, m16x2, i32x2, u32x2, f32x2, m32x2,
+    i64x2, f64x2, m64x2, i128x2, u128x2, m128x2, isizex2, usizex2, msizex2
+);
+impl_from_cast!(
+    f64x2[test_v128]: i8x2, u8x2, m8x2, i16x2, u16x2, m16x2, i32x2, u32x2, f32x2, m32x2,
+    i64x2, u64x2, m64x2, i128x2, u128x2, m128x2, isizex2, usizex2, msizex2
+);
+impl_from_cast_mask!(
+    m64x2[test_v128]: i8x2, u8x2, m8x2, i16x2, u16x2, m16x2, i32x2, u32x2, f32x2, m32x2,
+    i64x2, u64x2, f64x2, i128x2, u128x2, m128x2, isizex2, usizex2, msizex2
+);
+
+impl_from_cast!(
+    isizex2[test_v128]: i8x2, u8x2, m8x2, i16x2, u16x2, m16x2, i32x2, u32x2, f32x2, m32x2,
+    i64x2, u64x2, f64x2, m64x2, i128x2, u128x2, m128x2, usizex2, msizex2
+);
+impl_from_cast!(
+    usizex2[test_v128]: i8x2, u8x2, m8x2, i16x2, u16x2, m16x2, i32x2, u32x2, f32x2, m32x2,
+    i64x2, u64x2, f64x2, m64x2, i128x2, u128x2, m128x2, isizex2, msizex2
+);
+impl_from_cast_mask!(
+    msizex2[test_v128]: i8x2, u8x2, m8x2, i16x2, u16x2, m16x2, i32x2, u32x2, f32x2, m32x2,
+    i64x2, u64x2, f64x2, m64x2, i128x2, u128x2, m128x2, isizex2, usizex2
+);
+
+// FIXME[test_v128]: 64-bit single element vectors into_cast impls
+impl_from_cast!(i128x1[test_v128]: u128x1, m128x1);
+impl_from_cast!(u128x1[test_v128]: i128x1, m128x1);
+impl_from_cast!(m128x1[test_v128]: i128x1, u128x1);
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/cast/v16.rs.html b/src/packed_simd/api/cast/v16.rs.html new file mode 100644 index 000000000..1a4970055 --- /dev/null +++ b/src/packed_simd/api/cast/v16.rs.html @@ -0,0 +1,37 @@ +v16.rs.html -- source
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+
+//! `FromCast` and `IntoCast` implementations for portable 16-bit wide vectors
+#![rustfmt::skip]
+
+use crate::*;
+
+impl_from_cast!(
+    i8x2[test_v16]: u8x2, m8x2, i16x2, u16x2, m16x2, i32x2, u32x2, f32x2, m32x2,
+    i64x2, u64x2, f64x2, m64x2, i128x2, u128x2, m128x2, isizex2, usizex2, msizex2
+);
+impl_from_cast!(
+    u8x2[test_v16]: i8x2, m8x2, i16x2, u16x2, m16x2, i32x2, u32x2, f32x2, m32x2,
+    i64x2, u64x2, f64x2, m64x2, i128x2, u128x2, m128x2, isizex2, usizex2, msizex2
+);
+impl_from_cast_mask!(
+    m8x2[test_v16]: i8x2, u8x2, i16x2, u16x2, m16x2, i32x2, u32x2, f32x2, m32x2,
+    i64x2, u64x2, f64x2, m64x2, i128x2, u128x2, m128x2, isizex2, usizex2, msizex2
+);
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/cast/v256.rs.html b/src/packed_simd/api/cast/v256.rs.html new file mode 100644 index 000000000..548bbb82d --- /dev/null +++ b/src/packed_simd/api/cast/v256.rs.html @@ -0,0 +1,165 @@ +v256.rs.html -- source
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+
+//! `FromCast` and `IntoCast` implementations for portable 256-bit wide vectors
+#![rustfmt::skip]
+
+use crate::*;
+
+impl_from_cast!(i8x32[test_v256]: u8x32, m8x32, i16x32, u16x32, m16x32);
+impl_from_cast!(u8x32[test_v256]: i8x32, m8x32, i16x32, u16x32, m16x32);
+impl_from_cast_mask!(m8x32[test_v256]: i8x32, u8x32, i16x32, u16x32, m16x32);
+
+impl_from_cast!(
+    i16x16[test_v256]: i8x16, u8x16, m8x16, u16x16, m16x16,
+    i32x16, u32x16, f32x16, m32x16
+);
+impl_from_cast!(
+    u16x16[test_v256]: i8x16, u8x16, m8x16, i16x16, m16x16,
+    i32x16, u32x16, f32x16, m32x16
+);
+impl_from_cast_mask!(
+    m16x16[test_v256]: i8x16, u8x16, m8x16, i16x16, u16x16,
+    i32x16, u32x16, f32x16, m32x16
+);
+
+impl_from_cast!(
+    i32x8[test_v256]: i8x8, u8x8, m8x8, i16x8, u16x8, m16x8, u32x8, f32x8, m32x8,
+    i64x8, u64x8, f64x8, m64x8, isizex8, usizex8, msizex8
+);
+impl_from_cast!(
+    u32x8[test_v256]: i8x8, u8x8, m8x8, i16x8, u16x8, m16x8, i32x8, f32x8, m32x8,
+    i64x8, u64x8, f64x8, m64x8, isizex8, usizex8, msizex8
+);
+impl_from_cast!(
+    f32x8[test_v256]: i8x8, u8x8, m8x8, i16x8, u16x8, m16x8, i32x8, u32x8, m32x8,
+    i64x8, u64x8, f64x8, m64x8, isizex8, usizex8, msizex8
+);
+impl_from_cast_mask!(
+    m32x8[test_v256]: i8x8, u8x8, m8x8, i16x8, u16x8, m16x8, i32x8, u32x8, f32x8,
+    i64x8, u64x8, f64x8, m64x8, isizex8, usizex8, msizex8
+);
+
+impl_from_cast!(
+    i64x4[test_v256]: i8x4, u8x4, m8x4, i16x4, u16x4, m16x4, i32x4, u32x4, f32x4, m32x4,
+    u64x4, f64x4, m64x4, i128x4, u128x4, m128x4, isizex4, usizex4, msizex4
+);
+impl_from_cast!(
+    u64x4[test_v256]: i8x4, u8x4, m8x4, i16x4, u16x4, m16x4, i32x4, u32x4, f32x4, m32x4,
+    i64x4, f64x4, m64x4, i128x4, u128x4, m128x4, isizex4, usizex4, msizex4
+);
+impl_from_cast!(
+    f64x4[test_v256]: i8x4, u8x4, m8x4, i16x4, u16x4, m16x4, i32x4, u32x4, f32x4, m32x4,
+    i64x4, u64x4, m64x4, i128x4, u128x4, m128x4, isizex4, usizex4, msizex4
+);
+impl_from_cast_mask!(
+    m64x4[test_v256]: i8x4, u8x4, m8x4, i16x4, u16x4, m16x4, i32x4, u32x4, f32x4, m32x4,
+    i64x4, u64x4, f64x4, i128x4, u128x4, m128x4, isizex4, usizex4, msizex4
+);
+
+impl_from_cast!(
+    i128x2[test_v256]: i8x2, u8x2, m8x2, i16x2, u16x2, m16x2, i32x2, u32x2, f32x2, m32x2,
+    i64x2, u64x2, f64x2, m64x2, u128x2, m128x2, isizex2, usizex2, msizex2
+);
+impl_from_cast!(
+    u128x2[test_v256]: i8x2, u8x2, m8x2, i16x2, u16x2, m16x2, i32x2, u32x2, f32x2, m32x2,
+    i64x2, u64x2, f64x2, m64x2, i128x2, m128x2, isizex2, usizex2, msizex2
+);
+impl_from_cast_mask!(
+    m128x2[test_v256]: i8x2, u8x2, m8x2, i16x2, u16x2, m16x2, i32x2, u32x2, f32x2, m32x2,
+    i64x2, u64x2, m64x2, f64x2, i128x2, u128x2, isizex2, usizex2, msizex2
+);
+
+impl_from_cast!(
+    isizex4[test_v256]: i8x4, u8x4, m8x4, i16x4, u16x4, m16x4, i32x4, u32x4, f32x4, m32x4,
+    i64x4, u64x4, f64x4, m64x4, i128x4, u128x4, m128x4, usizex4, msizex4
+);
+impl_from_cast!(
+    usizex4[test_v256]: i8x4, u8x4, m8x4, i16x4, u16x4, m16x4, i32x4, u32x4, f32x4, m32x4,
+    i64x4, u64x4, f64x4, m64x4, i128x4, u128x4, m128x4, isizex4, msizex4
+);
+impl_from_cast_mask!(
+    msizex4[test_v256]: i8x4, u8x4, m8x4, i16x4, u16x4, m16x4, i32x4, u32x4, f32x4, m32x4,
+    i64x4, u64x4, f64x4, m64x4, i128x4, u128x4, m128x4, isizex4, usizex4
+);
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/cast/v32.rs.html b/src/packed_simd/api/cast/v32.rs.html new file mode 100644 index 000000000..d637518a6 --- /dev/null +++ b/src/packed_simd/api/cast/v32.rs.html @@ -0,0 +1,63 @@ +v32.rs.html -- source
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+
+//! `FromCast` and `IntoCast` implementations for portable 32-bit wide vectors
+#![rustfmt::skip]
+
+use crate::*;
+
+impl_from_cast!(
+    i8x4[test_v32]: u8x4, m8x4, i16x4, u16x4, m16x4, i32x4, u32x4, f32x4, m32x4,
+    i64x4, u64x4, f64x4, m64x4, i128x4, u128x4, m128x4, isizex4, usizex4, msizex4
+);
+impl_from_cast!(
+    u8x4[test_v32]: i8x4, m8x4, i16x4, u16x4, m16x4, i32x4, u32x4, f32x4, m32x4,
+    i64x4, u64x4, f64x4, m64x4, i128x4, u128x4, m128x4, isizex4, usizex4, msizex4
+);
+impl_from_cast_mask!(
+    m8x4[test_v32]: i8x4, u8x4, i16x4, u16x4, m16x4, i32x4, u32x4, f32x4, m32x4,
+    i64x4, u64x4, f64x4, m64x4, i128x4, u128x4, m128x4, isizex4, usizex4, msizex4
+);
+
+impl_from_cast!(
+    i16x2[test_v32]: i8x2, u8x2, m8x2, u16x2, m16x2, i32x2, u32x2, f32x2, m32x2,
+    i64x2, u64x2, f64x2, m64x2, i128x2, u128x2, m128x2, isizex2, usizex2, msizex2
+);
+impl_from_cast!(
+    u16x2[test_v32]: i8x2, u8x2, m8x2, i16x2, m16x2, i32x2, u32x2, f32x2, m32x2,
+    i64x2, u64x2, f64x2, m64x2, i128x2, u128x2, m128x2, isizex2, usizex2, msizex2
+);
+impl_from_cast_mask!(
+    m16x2[test_v32]: i8x2, u8x2, m8x2, i16x2, u16x2, i32x2, u32x2, f32x2, m32x2,
+    i64x2, u64x2, f64x2, m64x2, i128x2, u128x2, m128x2, isizex2, usizex2, msizex2
+);
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/cast/v512.rs.html b/src/packed_simd/api/cast/v512.rs.html new file mode 100644 index 000000000..85aef4d02 --- /dev/null +++ b/src/packed_simd/api/cast/v512.rs.html @@ -0,0 +1,139 @@ +v512.rs.html -- source
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+
+//! `FromCast` and `IntoCast` implementations for portable 512-bit wide vectors
+#![rustfmt::skip]
+
+use crate::*;
+
+impl_from_cast!(i8x64[test_v512]: u8x64, m8x64);
+impl_from_cast!(u8x64[test_v512]: i8x64, m8x64);
+impl_from_cast_mask!(m8x64[test_v512]: i8x64, u8x64);
+
+impl_from_cast!(i16x32[test_v512]: i8x32, u8x32, m8x32, u16x32, m16x32);
+impl_from_cast!(u16x32[test_v512]: i8x32, u8x32, m8x32, i16x32, m16x32);
+impl_from_cast_mask!(m16x32[test_v512]: i8x32, u8x32, m8x32, i16x32, u16x32);
+
+impl_from_cast!(
+    i32x16[test_v512]: i8x16, u8x16, m8x16, i16x16, u16x16, m16x16, u32x16, f32x16, m32x16
+);
+impl_from_cast!(
+    u32x16[test_v512]: i8x16, u8x16, m8x16, i16x16, u16x16, m16x16, i32x16, f32x16, m32x16
+);
+impl_from_cast!(
+    f32x16[test_v512]: i8x16, u8x16, m8x16, i16x16, u16x16, m16x16, i32x16, u32x16, m32x16
+);
+impl_from_cast_mask!(
+    m32x16[test_v512]: i8x16, u8x16, m8x16, i16x16, u16x16, m16x16, i32x16, u32x16, f32x16
+);
+
+impl_from_cast!(
+    i64x8[test_v512]: i8x8, u8x8, m8x8, i16x8, u16x8, m16x8, i32x8, u32x8, f32x8, m32x8,
+    u64x8, f64x8, m64x8, isizex8, usizex8, msizex8
+);
+impl_from_cast!(
+    u64x8[test_v512]: i8x8, u8x8, m8x8, i16x8, u16x8, m16x8, i32x8, u32x8, f32x8, m32x8,
+    i64x8, f64x8, m64x8, isizex8, usizex8, msizex8
+);
+impl_from_cast!(
+    f64x8[test_v512]: i8x8, u8x8, m8x8, i16x8, u16x8, m16x8, i32x8, u32x8, f32x8, m32x8,
+    i64x8, u64x8, m64x8, isizex8, usizex8, msizex8
+);
+impl_from_cast_mask!(
+    m64x8[test_v512]: i8x8, u8x8, m8x8, i16x8, u16x8, m16x8, i32x8, u32x8, f32x8, m32x8,
+    i64x8, u64x8, f64x8, isizex8, usizex8, msizex8
+);
+
+impl_from_cast!(
+    i128x4[test_v512]: i8x4, u8x4, m8x4, i16x4, u16x4, m16x4, i32x4, u32x4, f32x4, m32x4,
+    i64x4, u64x4, f64x4, m64x4, u128x4, m128x4, isizex4, usizex4, msizex4
+);
+impl_from_cast!(
+    u128x4[test_v512]: i8x4, u8x4, m8x4, i16x4, u16x4, m16x4, i32x4, u32x4, f32x4, m32x4,
+    i64x4, u64x4, f64x4, m64x4, i128x4, m128x4, isizex4, usizex4, msizex4
+);
+impl_from_cast_mask!(
+    m128x4[test_v512]: i8x4, u8x4, m8x4, i16x4, u16x4, m16x4, i32x4, u32x4, f32x4, m32x4,
+    i64x4, u64x4, m64x4, f64x4, i128x4, u128x4, isizex4, usizex4, msizex4
+);
+
+impl_from_cast!(
+    isizex8[test_v512]: i8x8, u8x8, m8x8, i16x8, u16x8, m16x8, i32x8, u32x8, f32x8, m32x8,
+    i64x8, u64x8, f64x8, m64x8, usizex8, msizex8
+);
+impl_from_cast!(
+    usizex8[test_v512]: i8x8, u8x8, m8x8, i16x8, u16x8, m16x8, i32x8, u32x8, f32x8, m32x8,
+    i64x8, u64x8, f64x8, m64x8, isizex8, msizex8
+);
+impl_from_cast_mask!(
+    msizex8[test_v512]: i8x8, u8x8, m8x8, i16x8, u16x8, m16x8, i32x8, u32x8, f32x8, m32x8,
+    i64x8, u64x8, f64x8, m64x8, isizex8, usizex8
+);
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/cast/v64.rs.html b/src/packed_simd/api/cast/v64.rs.html new file mode 100644 index 000000000..2a4ce9375 --- /dev/null +++ b/src/packed_simd/api/cast/v64.rs.html @@ -0,0 +1,97 @@ +v64.rs.html -- source
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+
+//! `FromCast` and `IntoCast` implementations for portable 64-bit wide vectors
+#![rustfmt::skip]
+
+use crate::*;
+
+impl_from_cast!(
+    i8x8[test_v64]: u8x8, m8x8, i16x8, u16x8, m16x8, i32x8, u32x8, f32x8, m32x8,
+    i64x8, u64x8, f64x8, m64x8, isizex8, usizex8, msizex8
+);
+impl_from_cast!(
+    u8x8[test_v64]: i8x8, m8x8, i16x8, u16x8, m16x8, i32x8, u32x8, f32x8, m32x8,
+    i64x8, u64x8, f64x8, m64x8, isizex8, usizex8, msizex8
+);
+impl_from_cast_mask!(
+    m8x8[test_v64]: i8x8, u8x8, i16x8, u16x8, m16x8, i32x8, u32x8, f32x8, m32x8,
+    i64x8, u64x8, f64x8, m64x8, isizex8, usizex8, msizex8
+);
+
+impl_from_cast!(
+    i16x4[test_v64]: i8x4, u8x4, m8x4, u16x4, m16x4, i32x4, u32x4, f32x4, m32x4,
+    i64x4, u64x4, f64x4, m64x4, i128x4, u128x4, m128x4, isizex4, usizex4, msizex4
+);
+impl_from_cast!(
+    u16x4[test_v64]: i8x4, u8x4, m8x4, i16x4, m16x4, i32x4, u32x4, f32x4, m32x4,
+    i64x4, u64x4, f64x4, m64x4, i128x4, u128x4, m128x4, isizex4, usizex4, msizex4
+);
+impl_from_cast_mask!(
+    m16x4[test_v64]: i8x4, u8x4, m8x4, i16x4, u16x4, i32x4, u32x4, f32x4, m32x4,
+    i64x4, u64x4, f64x4, m64x4, i128x4, u128x4, m128x4, isizex4, usizex4, msizex4
+);
+
+impl_from_cast!(
+    i32x2[test_v64]: i8x2, u8x2, m8x2, i16x2, u16x2, m16x2, u32x2, f32x2, m32x2,
+    i64x2, u64x2, f64x2, m64x2, i128x2, u128x2, m128x2, isizex2, usizex2, msizex2
+);
+impl_from_cast!(
+    u32x2[test_v64]: i8x2, u8x2, m8x2, i16x2, u16x2, m16x2, i32x2, f32x2, m32x2,
+    i64x2, u64x2, f64x2, m64x2, i128x2, u128x2, m128x2, isizex2, usizex2, msizex2
+);
+impl_from_cast!(
+    f32x2[test_v64]: i8x2, u8x2, m8x2, i16x2, u16x2, m16x2, i32x2, u32x2, m32x2,
+    i64x2, u64x2, f64x2, m64x2, i128x2, u128x2, m128x2, isizex2, usizex2, msizex2
+);
+impl_from_cast_mask!(
+    m32x2[test_v64]: i8x2, u8x2, m8x2, i16x2, u16x2, m16x2, i32x2, u32x2, f32x2,
+    i64x2, u64x2, f64x2, m64x2, i128x2, u128x2, m128x2, isizex2, usizex2, msizex2
+);
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/cmp.rs.html b/src/packed_simd/api/cmp.rs.html new file mode 100644 index 000000000..58bfafca1 --- /dev/null +++ b/src/packed_simd/api/cmp.rs.html @@ -0,0 +1,35 @@ +cmp.rs.html -- source
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+
+//! Implement cmp traits for vector types
+
+#[macro_use]
+mod partial_eq;
+
+#[macro_use]
+mod eq;
+
+#[macro_use]
+mod partial_ord;
+
+#[macro_use]
+mod ord;
+
+#[macro_use]
+mod vertical;
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/cmp/eq.rs.html b/src/packed_simd/api/cmp/eq.rs.html new file mode 100644 index 000000000..794892312 --- /dev/null +++ b/src/packed_simd/api/cmp/eq.rs.html @@ -0,0 +1,57 @@ +eq.rs.html -- source
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+
+//! Implements `Eq` for vector types.
+
+macro_rules! impl_cmp_eq {
+    (
+        [$elem_ty:ident; $elem_count:expr]:
+        $id:ident | $test_tt:tt |
+        ($true:expr, $false:expr)
+    ) => {
+        impl crate::cmp::Eq for $id {}
+        impl crate::cmp::Eq for LexicographicallyOrdered<$id> {}
+
+        test_if!{
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _cmp_eq>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn eq() {
+                        fn foo<E: crate::cmp::Eq>(_: E) {}
+                        let a = $id::splat($false);
+                        foo(a);
+                    }
+                }
+            }
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/cmp/ord.rs.html b/src/packed_simd/api/cmp/ord.rs.html new file mode 100644 index 000000000..89be885db --- /dev/null +++ b/src/packed_simd/api/cmp/ord.rs.html @@ -0,0 +1,89 @@ +ord.rs.html -- source
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+//! Implements `Ord` for vector types.
+
+macro_rules! impl_cmp_ord {
+    (
+        [$elem_ty:ident; $elem_count:expr]:
+        $id:ident | $test_tt:tt |
+        ($true:expr, $false:expr)
+    ) => {
+        impl $id {
+            /// Returns a wrapper that implements `Ord`.
+            #[inline]
+            pub fn lex_ord(&self) -> LexicographicallyOrdered<$id> {
+                LexicographicallyOrdered(*self)
+            }
+        }
+
+        impl crate::cmp::Ord for LexicographicallyOrdered<$id> {
+            #[inline]
+            fn cmp(&self, other: &Self) -> crate::cmp::Ordering {
+                match self.partial_cmp(other) {
+                    Some(x) => x,
+                    None => unsafe { crate::hint::unreachable_unchecked() },
+                }
+            }
+        }
+
+        test_if!{
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _cmp_ord>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn eq() {
+                        fn foo<E: crate::cmp::Ord>(_: E) {}
+                        let a = $id::splat($false);
+                        foo(a.partial_lex_ord());
+                        foo(a.lex_ord());
+                    }
+                }
+            }
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/cmp/partial_eq.rs.html b/src/packed_simd/api/cmp/partial_eq.rs.html new file mode 100644 index 000000000..e427f3654 --- /dev/null +++ b/src/packed_simd/api/cmp/partial_eq.rs.html @@ -0,0 +1,137 @@ +partial_eq.rs.html -- source
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+//! Implements `PartialEq` for vector types.
+
+macro_rules! impl_cmp_partial_eq {
+    (
+        [$elem_ty:ident; $elem_count:expr]:
+        $id:ident | $test_tt:tt |
+        ($true:expr, $false:expr)
+    ) => {
+        // FIXME: https://github.com/rust-lang-nursery/rust-clippy/issues/2892
+        #[allow(clippy::partialeq_ne_impl)]
+        impl crate::cmp::PartialEq<$id> for $id {
+            #[inline]
+            fn eq(&self, other: &Self) -> bool {
+                $id::eq(*self, *other).all()
+            }
+            #[inline]
+            fn ne(&self, other: &Self) -> bool {
+                $id::ne(*self, *other).any()
+            }
+        }
+
+        // FIXME: https://github.com/rust-lang-nursery/rust-clippy/issues/2892
+        #[allow(clippy::partialeq_ne_impl)]
+        impl crate::cmp::PartialEq<LexicographicallyOrdered<$id>>
+            for LexicographicallyOrdered<$id>
+        {
+            #[inline]
+            fn eq(&self, other: &Self) -> bool {
+                self.0 == other.0
+            }
+            #[inline]
+            fn ne(&self, other: &Self) -> bool {
+                self.0 != other.0
+            }
+        }
+
+        test_if! {
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _cmp_PartialEq>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn partial_eq() {
+                        let a = $id::splat($false);
+                        let b = $id::splat($true);
+
+                        assert!(a != b);
+                        assert!(!(a == b));
+                        assert!(a == a);
+                        assert!(!(a != a));
+
+                        if $id::lanes() > 1 {
+                            let a = $id::splat($false).replace(0, $true);
+                            let b = $id::splat($true);
+
+                            assert!(a != b);
+                            assert!(!(a == b));
+                            assert!(a == a);
+                            assert!(!(a != a));
+                        }
+                    }
+                }
+            }
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/cmp/partial_ord.rs.html b/src/packed_simd/api/cmp/partial_ord.rs.html new file mode 100644 index 000000000..319ed66b9 --- /dev/null +++ b/src/packed_simd/api/cmp/partial_ord.rs.html @@ -0,0 +1,471 @@ +partial_ord.rs.html -- source
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+
+//! Implements `PartialOrd` for vector types.
+//!
+//! This implements a lexicographical order.
+
+macro_rules! impl_cmp_partial_ord {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident | $test_tt:tt) => {
+        impl $id {
+            /// Returns a wrapper that implements `PartialOrd`.
+            #[inline]
+            pub fn partial_lex_ord(&self) -> LexicographicallyOrdered<$id> {
+                LexicographicallyOrdered(*self)
+            }
+        }
+
+        impl crate::cmp::PartialOrd<LexicographicallyOrdered<$id>>
+            for LexicographicallyOrdered<$id>
+        {
+            #[inline]
+            fn partial_cmp(
+                &self, other: &Self,
+            ) -> Option<crate::cmp::Ordering> {
+                if PartialEq::eq(self, other) {
+                    Some(crate::cmp::Ordering::Equal)
+                } else if PartialOrd::lt(self, other) {
+                    Some(crate::cmp::Ordering::Less)
+                } else if PartialOrd::gt(self, other) {
+                    Some(crate::cmp::Ordering::Greater)
+                } else {
+                    None
+                }
+            }
+            #[inline]
+            fn lt(&self, other: &Self) -> bool {
+                let m_lt = self.0.lt(other.0);
+                let m_eq = self.0.eq(other.0);
+                for i in 0..$id::lanes() {
+                    if m_eq.extract(i) {
+                        continue;
+                    }
+                    return m_lt.extract(i);
+                }
+                false
+            }
+            #[inline]
+            fn le(&self, other: &Self) -> bool {
+                self.lt(other) | PartialEq::eq(self, other)
+            }
+            #[inline]
+            fn ge(&self, other: &Self) -> bool {
+                self.gt(other) | PartialEq::eq(self, other)
+            }
+            #[inline]
+            fn gt(&self, other: &Self) -> bool {
+                let m_gt = self.0.gt(other.0);
+                let m_eq = self.0.eq(other.0);
+                for i in 0..$id::lanes() {
+                    if m_eq.extract(i) {
+                        continue;
+                    }
+                    return m_gt.extract(i);
+                }
+                false
+            }
+        }
+    };
+}
+
+macro_rules! test_cmp_partial_ord_int {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident | $test_tt:tt) => {
+        test_if!{
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _cmp_PartialOrd>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn partial_lex_ord() {
+                        use crate::testing::utils::{test_cmp};
+                        // constant values
+                        let a = $id::splat(0);
+                        let b = $id::splat(1);
+
+                        test_cmp(a.partial_lex_ord(), b.partial_lex_ord(),
+                                 Some(crate::cmp::Ordering::Less));
+                        test_cmp(b.partial_lex_ord(), a.partial_lex_ord(),
+                                 Some(crate::cmp::Ordering::Greater));
+                        test_cmp(a.partial_lex_ord(), a.partial_lex_ord(),
+                                 Some(crate::cmp::Ordering::Equal));
+                        test_cmp(b.partial_lex_ord(), b.partial_lex_ord(),
+                                 Some(crate::cmp::Ordering::Equal));
+
+                        // variable values: a = [0, 1, 2, 3]; b = [3, 2, 1, 0]
+                        let mut a = $id::splat(0);
+                        let mut b = $id::splat(0);
+                        for i in 0..$id::lanes() {
+                            a = a.replace(i, i as $elem_ty);
+                            b = b.replace(i, ($id::lanes() - i) as $elem_ty);
+                        }
+                        test_cmp(a.partial_lex_ord(), b.partial_lex_ord(),
+                                 Some(crate::cmp::Ordering::Less));
+                        test_cmp(b.partial_lex_ord(), a.partial_lex_ord(),
+                                 Some(crate::cmp::Ordering::Greater));
+                        test_cmp(a.partial_lex_ord(), a.partial_lex_ord(),
+                                 Some(crate::cmp::Ordering::Equal));
+                        test_cmp(b.partial_lex_ord(), b.partial_lex_ord(),
+                                 Some(crate::cmp::Ordering::Equal));
+
+                        // variable values: a = [0, 1, 2, 3]; b = [0, 1, 2, 4]
+                        let mut b = a;
+                        b = b.replace(
+                            $id::lanes() - 1,
+                            a.extract($id::lanes() - 1) + 1 as $elem_ty
+                        );
+                        test_cmp(a.partial_lex_ord(), b.partial_lex_ord(),
+                                 Some(crate::cmp::Ordering::Less));
+                        test_cmp(b.partial_lex_ord(), a.partial_lex_ord(),
+                                 Some(crate::cmp::Ordering::Greater));
+                        test_cmp(a.partial_lex_ord(), a.partial_lex_ord(),
+                                 Some(crate::cmp::Ordering::Equal));
+                        test_cmp(b.partial_lex_ord(), b.partial_lex_ord(),
+                                 Some(crate::cmp::Ordering::Equal));
+
+                        if $id::lanes() > 2 {
+                            // variable values a = [0, 1, 0, 0]; b = [0, 1, 2, 3]
+                            let b = a;
+                            let mut a = $id::splat(0);
+                            a = a.replace(1, 1 as $elem_ty);
+                            test_cmp(a.partial_lex_ord(), b.partial_lex_ord(),
+                                     Some(crate::cmp::Ordering::Less));
+                            test_cmp(b.partial_lex_ord(), a.partial_lex_ord(),
+                                     Some(crate::cmp::Ordering::Greater));
+                            test_cmp(a.partial_lex_ord(), a.partial_lex_ord(),
+                                     Some(crate::cmp::Ordering::Equal));
+                            test_cmp(b.partial_lex_ord(), b.partial_lex_ord(),
+                                     Some(crate::cmp::Ordering::Equal));
+
+                            // variable values: a = [0, 1, 2, 3]; b = [0, 1, 3, 2]
+                            let mut b = a;
+                            b = b.replace(
+                                2, a.extract($id::lanes() - 1) + 1 as $elem_ty
+                            );
+                            test_cmp(a.partial_lex_ord(), b.partial_lex_ord(),
+                                     Some(crate::cmp::Ordering::Less));
+                            test_cmp(b.partial_lex_ord(), a.partial_lex_ord(),
+                                     Some(crate::cmp::Ordering::Greater));
+                            test_cmp(a.partial_lex_ord(), a.partial_lex_ord(),
+                                     Some(crate::cmp::Ordering::Equal));
+                            test_cmp(b.partial_lex_ord(), b.partial_lex_ord(),
+                                     Some(crate::cmp::Ordering::Equal));
+                        }
+                    }
+                }
+            }
+        }
+    };
+}
+
+macro_rules! test_cmp_partial_ord_mask {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident | $test_tt:tt) => {
+        test_if!{
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _cmp_PartialOrd>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn partial_lex_ord() {
+                        use crate::testing::utils::{test_cmp};
+                        use crate::cmp::Ordering;
+
+                        // constant values
+                        let a = $id::splat(false);
+                        let b = $id::splat(true);
+
+                        test_cmp(a.partial_lex_ord(), b.partial_lex_ord(),
+                                 Some(Ordering::Less));
+                        test_cmp(b.partial_lex_ord(), a.partial_lex_ord(),
+                                 Some(Ordering::Greater));
+                        test_cmp(a.partial_lex_ord(), a.partial_lex_ord(),
+                                 Some(Ordering::Equal));
+                        test_cmp(b.partial_lex_ord(), b.partial_lex_ord(),
+                                 Some(Ordering::Equal));
+
+                        // variable values:
+                        // a = [false, false, false, false];
+                        // b = [false, false, false, true]
+                        let a = $id::splat(false);
+                        let mut b = $id::splat(false);
+                        b = b.replace($id::lanes() - 1, true);
+                        test_cmp(a.partial_lex_ord(), b.partial_lex_ord(),
+                                 Some(Ordering::Less));
+                        test_cmp(b.partial_lex_ord(), a.partial_lex_ord(),
+                                 Some(Ordering::Greater));
+                        test_cmp(a.partial_lex_ord(), a.partial_lex_ord(),
+                                 Some(Ordering::Equal));
+                        test_cmp(b.partial_lex_ord(), b.partial_lex_ord(),
+                                 Some(Ordering::Equal));
+
+                        // variable values:
+                        // a = [true, true, true, false];
+                        // b = [true, true, true, true]
+                        let mut a = $id::splat(true);
+                        let b = $id::splat(true);
+                        a = a.replace($id::lanes() - 1, false);
+                        test_cmp(a.partial_lex_ord(), b.partial_lex_ord(),
+                                 Some(Ordering::Less));
+                        test_cmp(b.partial_lex_ord(), a.partial_lex_ord(),
+                                 Some(Ordering::Greater));
+                        test_cmp(a.partial_lex_ord(), a.partial_lex_ord(),
+                                 Some(Ordering::Equal));
+                        test_cmp(b.partial_lex_ord(), b.partial_lex_ord(),
+                                 Some(Ordering::Equal));
+
+                        if $id::lanes() > 2 {
+                            // variable values
+                            // a = [false, true, false, false];
+                            // b = [false, true, true, true]
+                            let mut a = $id::splat(false);
+                            let mut b = $id::splat(true);
+                            a = a.replace(1, true);
+                            b = b.replace(0, false);
+                            test_cmp(a.partial_lex_ord(), b.partial_lex_ord(),
+                                     Some(Ordering::Less));
+                            test_cmp(b.partial_lex_ord(), a.partial_lex_ord(),
+                                     Some(Ordering::Greater));
+                            test_cmp(a.partial_lex_ord(), a.partial_lex_ord(),
+                                     Some(Ordering::Equal));
+                            test_cmp(b.partial_lex_ord(), b.partial_lex_ord(),
+                                     Some(Ordering::Equal));
+                        }
+                    }
+                }
+            }
+        }
+    };
+}
+
+
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+
+//! Vertical (lane-wise) vector comparisons returning vector masks.
+
+macro_rules! impl_cmp_vertical {
+    (
+        [$elem_ty:ident; $elem_count:expr]:
+        $id:ident,
+        $mask_ty:ident,
+        $is_mask:expr,($true:expr, $false:expr) | $test_tt:tt
+    ) => {
+        impl $id {
+            /// Lane-wise equality comparison.
+            #[inline]
+            pub fn eq(self, other: Self) -> $mask_ty {
+                use crate::llvm::simd_eq;
+                Simd(unsafe { simd_eq(self.0, other.0) })
+            }
+
+            /// Lane-wise inequality comparison.
+            #[inline]
+            pub fn ne(self, other: Self) -> $mask_ty {
+                use crate::llvm::simd_ne;
+                Simd(unsafe { simd_ne(self.0, other.0) })
+            }
+
+            /// Lane-wise less-than comparison.
+            #[inline]
+            pub fn lt(self, other: Self) -> $mask_ty {
+                use crate::llvm::{simd_gt, simd_lt};
+                if $is_mask {
+                    Simd(unsafe { simd_gt(self.0, other.0) })
+                } else {
+                    Simd(unsafe { simd_lt(self.0, other.0) })
+                }
+            }
+
+            /// Lane-wise less-than-or-equals comparison.
+            #[inline]
+            pub fn le(self, other: Self) -> $mask_ty {
+                use crate::llvm::{simd_ge, simd_le};
+                if $is_mask {
+                    Simd(unsafe { simd_ge(self.0, other.0) })
+                } else {
+                    Simd(unsafe { simd_le(self.0, other.0) })
+                }
+            }
+
+            /// Lane-wise greater-than comparison.
+            #[inline]
+            pub fn gt(self, other: Self) -> $mask_ty {
+                use crate::llvm::{simd_gt, simd_lt};
+                if $is_mask {
+                    Simd(unsafe { simd_lt(self.0, other.0) })
+                } else {
+                    Simd(unsafe { simd_gt(self.0, other.0) })
+                }
+            }
+
+            /// Lane-wise greater-than-or-equals comparison.
+            #[inline]
+            pub fn ge(self, other: Self) -> $mask_ty {
+                use crate::llvm::{simd_ge, simd_le};
+                if $is_mask {
+                    Simd(unsafe { simd_le(self.0, other.0) })
+                } else {
+                    Simd(unsafe { simd_ge(self.0, other.0) })
+                }
+            }
+        }
+        test_if!{
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _cmp_vertical>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn cmp() {
+                        let a = $id::splat($false);
+                        let b = $id::splat($true);
+
+                        let r = a.lt(b);
+                        let e = $mask_ty::splat(true);
+                        assert!(r == e);
+                        let r = a.le(b);
+                        assert!(r == e);
+
+                        let e = $mask_ty::splat(false);
+                        let r = a.gt(b);
+                        assert!(r == e);
+                        let r = a.ge(b);
+                        assert!(r == e);
+                        let r = a.eq(b);
+                        assert!(r == e);
+
+                        let mut a = a;
+                        let mut b = b;
+                        let mut e = e;
+                        for i in 0..$id::lanes() {
+                            if i % 2 == 0 {
+                                a = a.replace(i, $false);
+                                b = b.replace(i, $true);
+                                e = e.replace(i, true);
+                            } else {
+                                a = a.replace(i, $true);
+                                b = b.replace(i, $false);
+                                e = e.replace(i, false);
+                            }
+                        }
+                        let r = a.lt(b);
+                        assert!(r == e);
+                    }
+                }
+            }
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/default.rs.html b/src/packed_simd/api/default.rs.html new file mode 100644 index 000000000..2685d78b3 --- /dev/null +++ b/src/packed_simd/api/default.rs.html @@ -0,0 +1,59 @@ +default.rs.html -- source
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+//! Implements `Default` for vector types.
+
+macro_rules! impl_default {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident | $test_tt:tt) => {
+        impl Default for $id {
+            #[inline]
+            fn default() -> Self {
+                Self::splat($elem_ty::default())
+            }
+        }
+
+        test_if!{
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _default>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn default() {
+                        let a = $id::default();
+                        for i in 0..$id::lanes() {
+                            assert_eq!(a.extract(i), $elem_ty::default());
+                        }
+                    }
+                }
+            }
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/fmt.rs.html b/src/packed_simd/api/fmt.rs.html new file mode 100644 index 000000000..bebcda294 --- /dev/null +++ b/src/packed_simd/api/fmt.rs.html @@ -0,0 +1,27 @@ +fmt.rs.html -- source
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+//! Implements formatting APIs
+
+#[macro_use]
+mod debug;
+#[macro_use]
+mod lower_hex;
+#[macro_use]
+mod upper_hex;
+#[macro_use]
+mod octal;
+#[macro_use]
+mod binary;
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/fmt/binary.rs.html b/src/packed_simd/api/fmt/binary.rs.html new file mode 100644 index 000000000..5cd20c4a8 --- /dev/null +++ b/src/packed_simd/api/fmt/binary.rs.html @@ -0,0 +1,115 @@ +binary.rs.html -- source
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+//! Implement Octal formatting
+
+macro_rules! impl_fmt_binary {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident | $test_tt:tt) => {
+        impl crate::fmt::Binary for $id {
+            #[allow(clippy::missing_inline_in_public_items)]
+            fn fmt(
+                &self, f: &mut crate::fmt::Formatter<'_>,
+            ) -> crate::fmt::Result {
+                write!(f, "{}(", stringify!($id))?;
+                for i in 0..$elem_count {
+                    if i > 0 {
+                        write!(f, ", ")?;
+                    }
+                    self.extract(i).fmt(f)?;
+                }
+                write!(f, ")")
+            }
+        }
+        test_if! {
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _fmt_binary>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn binary() {
+                        use arrayvec::{ArrayString,ArrayVec};
+                        type TinyString = ArrayString<[u8; 512]>;
+
+                        use crate::fmt::Write;
+                        let v = $id::splat($elem_ty::default());
+                        let mut s = TinyString::new();
+                        write!(&mut s, "{:#b}", v).unwrap();
+
+                        let mut beg = TinyString::new();
+                        write!(&mut beg, "{}(", stringify!($id)).unwrap();
+                        assert!(s.starts_with(beg.as_str()));
+                        assert!(s.ends_with(")"));
+                        let s: ArrayVec<[TinyString; 64]>
+                            = s.replace(beg.as_str(), "")
+                            .replace(")", "").split(",")
+                            .map(|v| TinyString::from(v.trim()).unwrap())
+                            .collect();
+                        assert_eq!(s.len(), $id::lanes());
+                        for (index, ss) in s.into_iter().enumerate() {
+                            let mut e = TinyString::new();
+                            write!(&mut e, "{:#b}", v.extract(index)).unwrap();
+                            assert_eq!(ss, e);
+                        }
+                    }
+                }
+            }
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/fmt/debug.rs.html b/src/packed_simd/api/fmt/debug.rs.html new file mode 100644 index 000000000..e4d9488f1 --- /dev/null +++ b/src/packed_simd/api/fmt/debug.rs.html @@ -0,0 +1,127 @@ +debug.rs.html -- source
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+//! Implement debug formatting
+
+macro_rules! impl_fmt_debug_tests {
+    ([$elem_ty:ty; $elem_count:expr]: $id:ident | $test_tt:tt) => {
+        test_if! {
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _fmt_debug>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn debug() {
+                        use arrayvec::{ArrayString,ArrayVec};
+                        type TinyString = ArrayString<[u8; 512]>;
+
+                        use crate::fmt::Write;
+                        let v = $id::default();
+                        let mut s = TinyString::new();
+                        write!(&mut s, "{:?}", v).unwrap();
+
+                        let mut beg = TinyString::new();
+                        write!(&mut beg, "{}(", stringify!($id)).unwrap();
+                        assert!(s.starts_with(beg.as_str()));
+                        assert!(s.ends_with(")"));
+                        let s: ArrayVec<[TinyString; 64]>
+                            = s.replace(beg.as_str(), "")
+                            .replace(")", "").split(",")
+                            .map(|v| TinyString::from(v.trim()).unwrap())
+                            .collect();
+                        assert_eq!(s.len(), $id::lanes());
+                        for (index, ss) in s.into_iter().enumerate() {
+                            let mut e = TinyString::new();
+                            write!(&mut e, "{:?}", v.extract(index)).unwrap();
+                            assert_eq!(ss, e);
+                        }
+                    }
+                }
+            }
+        }
+    };
+}
+
+macro_rules! impl_fmt_debug {
+    ([$elem_ty:ty; $elem_count:expr]: $id:ident | $test_tt:tt) => {
+        impl crate::fmt::Debug for $id {
+            #[allow(clippy::missing_inline_in_public_items)]
+            fn fmt(
+                &self, f: &mut crate::fmt::Formatter<'_>,
+            ) -> crate::fmt::Result {
+                write!(f, "{}(", stringify!($id))?;
+                for i in 0..$elem_count {
+                    if i > 0 {
+                        write!(f, ", ")?;
+                    }
+                    self.extract(i).fmt(f)?;
+                }
+                write!(f, ")")
+            }
+        }
+        impl_fmt_debug_tests!([$elem_ty; $elem_count]: $id | $test_tt);
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/fmt/lower_hex.rs.html b/src/packed_simd/api/fmt/lower_hex.rs.html new file mode 100644 index 000000000..973f7d3c8 --- /dev/null +++ b/src/packed_simd/api/fmt/lower_hex.rs.html @@ -0,0 +1,115 @@ +lower_hex.rs.html -- source
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+//! Implement `LowerHex` formatting
+
+macro_rules! impl_fmt_lower_hex {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident | $test_tt:tt) => {
+        impl crate::fmt::LowerHex for $id {
+            #[allow(clippy::missing_inline_in_public_items)]
+            fn fmt(
+                &self, f: &mut crate::fmt::Formatter<'_>,
+            ) -> crate::fmt::Result {
+                write!(f, "{}(", stringify!($id))?;
+                for i in 0..$elem_count {
+                    if i > 0 {
+                        write!(f, ", ")?;
+                    }
+                    self.extract(i).fmt(f)?;
+                }
+                write!(f, ")")
+            }
+        }
+        test_if! {
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _fmt_lower_hex>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn lower_hex() {
+                        use arrayvec::{ArrayString,ArrayVec};
+                        type TinyString = ArrayString<[u8; 512]>;
+
+                        use crate::fmt::Write;
+                        let v = $id::splat($elem_ty::default());
+                        let mut s = TinyString::new();
+                        write!(&mut s, "{:#x}", v).unwrap();
+
+                        let mut beg = TinyString::new();
+                        write!(&mut beg, "{}(", stringify!($id)).unwrap();
+                        assert!(s.starts_with(beg.as_str()));
+                        assert!(s.ends_with(")"));
+                        let s: ArrayVec<[TinyString; 64]>
+                            = s.replace(beg.as_str(), "").replace(")", "")
+                            .split(",")
+                            .map(|v| TinyString::from(v.trim()).unwrap())
+                            .collect();
+                        assert_eq!(s.len(), $id::lanes());
+                        for (index, ss) in s.into_iter().enumerate() {
+                            let mut e = TinyString::new();
+                            write!(&mut e, "{:#x}", v.extract(index)).unwrap();
+                        assert_eq!(ss, e);
+                        }
+                    }
+                }
+            }
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/fmt/octal.rs.html b/src/packed_simd/api/fmt/octal.rs.html new file mode 100644 index 000000000..952e0ccba --- /dev/null +++ b/src/packed_simd/api/fmt/octal.rs.html @@ -0,0 +1,115 @@ +octal.rs.html -- source
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+
+//! Implement Octal formatting
+
+macro_rules! impl_fmt_octal {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident | $test_tt:tt) => {
+        impl crate::fmt::Octal for $id {
+            #[allow(clippy::missing_inline_in_public_items)]
+            fn fmt(
+                &self, f: &mut crate::fmt::Formatter<'_>,
+            ) -> crate::fmt::Result {
+                write!(f, "{}(", stringify!($id))?;
+                for i in 0..$elem_count {
+                    if i > 0 {
+                        write!(f, ", ")?;
+                    }
+                    self.extract(i).fmt(f)?;
+                }
+                write!(f, ")")
+            }
+        }
+        test_if! {
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _fmt_octal>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn octal_hex() {
+                        use arrayvec::{ArrayString,ArrayVec};
+                        type TinyString = ArrayString<[u8; 512]>;
+
+                        use crate::fmt::Write;
+                        let v = $id::splat($elem_ty::default());
+                        let mut s = TinyString::new();
+                        write!(&mut s, "{:#o}", v).unwrap();
+
+                        let mut beg = TinyString::new();
+                        write!(&mut beg, "{}(", stringify!($id)).unwrap();
+                        assert!(s.starts_with(beg.as_str()));
+                        assert!(s.ends_with(")"));
+                        let s: ArrayVec<[TinyString; 64]>
+                            = s.replace(beg.as_str(), "").replace(")", "")
+                            .split(",")
+                            .map(|v| TinyString::from(v.trim()).unwrap())
+                            .collect();
+                        assert_eq!(s.len(), $id::lanes());
+                        for (index, ss) in s.into_iter().enumerate() {
+                            let mut e = TinyString::new();
+                            write!(&mut e, "{:#o}", v.extract(index)).unwrap();
+                            assert_eq!(ss, e);
+                        }
+                    }
+                }
+            }
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/fmt/upper_hex.rs.html b/src/packed_simd/api/fmt/upper_hex.rs.html new file mode 100644 index 000000000..2bf323ca8 --- /dev/null +++ b/src/packed_simd/api/fmt/upper_hex.rs.html @@ -0,0 +1,115 @@ +upper_hex.rs.html -- source
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+//! Implement `UpperHex` formatting
+
+macro_rules! impl_fmt_upper_hex {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident | $test_tt:tt) => {
+        impl crate::fmt::UpperHex for $id {
+            #[allow(clippy::missing_inline_in_public_items)]
+            fn fmt(
+                &self, f: &mut crate::fmt::Formatter<'_>,
+            ) -> crate::fmt::Result {
+                write!(f, "{}(", stringify!($id))?;
+                for i in 0..$elem_count {
+                    if i > 0 {
+                        write!(f, ", ")?;
+                    }
+                    self.extract(i).fmt(f)?;
+                }
+                write!(f, ")")
+            }
+        }
+        test_if! {
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _fmt_upper_hex>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn upper_hex() {
+                        use arrayvec::{ArrayString,ArrayVec};
+                        type TinyString = ArrayString<[u8; 512]>;
+
+                        use crate::fmt::Write;
+                        let v = $id::splat($elem_ty::default());
+                        let mut s = TinyString::new();
+                        write!(&mut s, "{:#X}", v).unwrap();
+
+                        let mut beg = TinyString::new();
+                        write!(&mut beg, "{}(", stringify!($id)).unwrap();
+                        assert!(s.starts_with(beg.as_str()));
+                        assert!(s.ends_with(")"));
+                        let s: ArrayVec<[TinyString; 64]>
+                            = s.replace(beg.as_str(), "").replace(")", "")
+                            .split(",")
+                            .map(|v| TinyString::from(v.trim()).unwrap())
+                            .collect();
+                        assert_eq!(s.len(), $id::lanes());
+                        for (index, ss) in s.into_iter().enumerate() {
+                            let mut e = TinyString::new();
+                            write!(&mut e, "{:#X}", v.extract(index)).unwrap();
+                            assert_eq!(ss, e);
+                        }
+                    }
+                }
+            }
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/from.rs.html b/src/packed_simd/api/from.rs.html new file mode 100644 index 000000000..f0abe9994 --- /dev/null +++ b/src/packed_simd/api/from.rs.html @@ -0,0 +1,17 @@ +from.rs.html -- source
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+//! Implementations of the `From` and `Into` traits
+
+#[macro_use]
+mod from_array;
+
+#[macro_use]
+mod from_vector;
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/from/from_array.rs.html b/src/packed_simd/api/from/from_array.rs.html new file mode 100644 index 000000000..bea105543 --- /dev/null +++ b/src/packed_simd/api/from/from_array.rs.html @@ -0,0 +1,245 @@ +from_array.rs.html -- source
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+
+//! Implements `From<[T; N]>` and `Into<[T; N]>` for vector types.
+
+macro_rules! impl_from_array {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident | $test_tt:tt
+     | ($non_default_array:expr, $non_default_vec:expr)) => {
+        impl From<[$elem_ty; $elem_count]> for $id {
+            #[inline]
+            fn from(array: [$elem_ty; $elem_count]) -> Self {
+                union U {
+                    array: [$elem_ty; $elem_count],
+                    vec: $id,
+                }
+                unsafe { U { array }.vec }
+            }
+        }
+
+        impl From<$id> for [$elem_ty; $elem_count] {
+            #[inline]
+            fn from(vec: $id) -> Self {
+                union U {
+                    array: [$elem_ty; $elem_count],
+                    vec: $id,
+                }
+                unsafe { U { vec }.array }
+            }
+        }
+
+        // FIXME: `Into::into` is not inline, but due to
+        // the blanket impl in `std`, which is not
+        // marked `default`, we cannot override it here with
+        // specialization.
+        /*
+        impl Into<[$elem_ty; $elem_count]> for $id {
+            #[inline]
+            fn into(self) -> [$elem_ty; $elem_count] {
+                union U {
+                    array: [$elem_ty; $elem_count],
+                    vec: $id,
+                }
+                unsafe { U { vec: self }.array }
+            }
+        }
+
+        impl Into<$id> for [$elem_ty; $elem_count] {
+            #[inline]
+            fn into(self) -> $id {
+                union U {
+                    array: [$elem_ty; $elem_count],
+                    vec: $id,
+                }
+                unsafe { U { array: self }.vec }
+            }
+        }
+        */
+
+        test_if! {
+            $test_tt:
+            paste::item! {
+                mod [<$id _from>] {
+                    use super::*;
+                    #[test]
+                    fn array() {
+                        let vec: $id = Default::default();
+
+                        // FIXME: Workaround for arrays with more than 32
+                        // elements.
+                        //
+                        // Safe because we never take a reference to any
+                        // uninitialized element.
+                        union W {
+                            array: [$elem_ty; $elem_count],
+                            other: ()
+                        }
+                        let mut array = W { other: () };
+                        for i in 0..$elem_count {
+                            let default: $elem_ty = Default::default();
+                            // note: array.other is the active member and
+                            // initialized so we can take a reference to it:
+                            let p = unsafe {
+                                &mut array.other as *mut () as *mut $elem_ty
+                            };
+                            // note: default is a valid bit-pattern for
+                            // $elem_ty:
+                            unsafe {
+                                crate::ptr::write(p.wrapping_add(i), default)
+                            };
+                        }
+                        // note: the array variant of the union is properly
+                        // initialized:
+                        let mut array = unsafe {
+                            array.array
+                        };
+
+                        array[0] = $non_default_array;
+                        let vec = vec.replace(0, $non_default_vec);
+
+                        let vec_from_array = $id::from(array);
+                        assert_eq!(vec_from_array, vec);
+                        let array_from_vec
+                            = <[$elem_ty; $elem_count]>::from(vec);
+                        // FIXME: Workaround for arrays with more than 32
+                        // elements.
+                        for i in 0..$elem_count {
+                            assert_eq!(array_from_vec[i], array[i]);
+                        }
+
+                        let vec_from_into_array: $id = array.into();
+                        assert_eq!(vec_from_into_array, vec);
+                        let array_from_into_vec: [$elem_ty; $elem_count]
+                            = vec.into();
+                        // FIXME: Workaround for arrays with more than 32
+                        // elements.
+                        for i in 0..$elem_count {
+                            assert_eq!(array_from_into_vec[i], array[i]);
+                        }
+                    }
+                }
+            }
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/from/from_vector.rs.html b/src/packed_simd/api/from/from_vector.rs.html new file mode 100644 index 000000000..584be95a0 --- /dev/null +++ b/src/packed_simd/api/from/from_vector.rs.html @@ -0,0 +1,137 @@ +from_vector.rs.html -- source
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+//! Implements `From` and `Into` for vector types.
+
+macro_rules! impl_from_vector {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident | $test_tt:tt
+     | $source:ident) => {
+        impl From<$source> for $id {
+            #[inline]
+            fn from(source: $source) -> Self {
+                fn static_assert_same_number_of_lanes<T, U>()
+                where
+                    T: crate::sealed::Simd,
+                    U: crate::sealed::Simd<LanesType = T::LanesType>,
+                {
+                }
+                use crate::llvm::simd_cast;
+                static_assert_same_number_of_lanes::<$id, $source>();
+                Simd(unsafe { simd_cast(source.0) })
+            }
+        }
+
+        // FIXME: `Into::into` is not inline, but due to the blanket impl in
+        // `std`, which is not marked `default`, we cannot override it here
+        // with specialization.
+
+        /*
+           impl Into<$id> for $source {
+               #[inline]
+               fn into(self) -> $id {
+                   unsafe { simd_cast(self) }
+               }
+           }
+        */
+
+        test_if! {
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _from_ $source>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn from() {
+                        assert_eq!($id::lanes(), $source::lanes());
+                        let source: $source = Default::default();
+                        let vec: $id = Default::default();
+
+                        let e = $id::from(source);
+                        assert_eq!(e, vec);
+
+                        let e: $id = source.into();
+                        assert_eq!(e, vec);
+                    }
+                }
+            }
+        }
+    };
+}
+
+macro_rules! impl_from_vectors {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident | $test_tt:tt
+     | $($source:ident),*) => {
+        $(
+            impl_from_vector!(
+                [$elem_ty; $elem_count]: $id | $test_tt | $source
+            );
+        )*
+    }
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/hash.rs.html b/src/packed_simd/api/hash.rs.html new file mode 100644 index 000000000..6036997f8 --- /dev/null +++ b/src/packed_simd/api/hash.rs.html @@ -0,0 +1,97 @@ +hash.rs.html -- source
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+//! Implements `Hash` for vector types.
+
+macro_rules! impl_hash {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident | $test_tt:tt) => {
+        impl crate::hash::Hash for $id {
+            #[inline]
+            fn hash<H: crate::hash::Hasher>(&self, state: &mut H) {
+                unsafe {
+                    union A {
+                        data: [$elem_ty; $id::lanes()],
+                        vec: $id,
+                    }
+                    A { vec: *self }.data.hash(state)
+                }
+            }
+        }
+
+        test_if! {
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _hash>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn hash() {
+                        use crate::hash::{Hash, Hasher};
+                        #[allow(deprecated)]
+                        use crate::hash::{SipHasher13};
+                        type A = [$elem_ty; $id::lanes()];
+                        let a: A = [42 as $elem_ty; $id::lanes()];
+                        assert_eq!(
+                            crate::mem::size_of::<A>(),
+                            crate::mem::size_of::<$id>()
+                        );
+                        #[allow(deprecated)]
+                        let mut a_hash = SipHasher13::new();
+                        let mut v_hash = a_hash.clone();
+                        a.hash(&mut a_hash);
+
+                        let v = $id::splat(42 as $elem_ty);
+                        v.hash(&mut v_hash);
+                        assert_eq!(a_hash.finish(), v_hash.finish());
+                    }
+                }
+            }
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/into_bits.rs.html b/src/packed_simd/api/into_bits.rs.html new file mode 100644 index 000000000..d8ca0b302 --- /dev/null +++ b/src/packed_simd/api/into_bits.rs.html @@ -0,0 +1,121 @@ +into_bits.rs.html -- source
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+//! Implementation of `FromBits` and `IntoBits`.
+
+/// Safe lossless bitwise conversion from `T` to `Self`.
+pub trait FromBits<T>: crate::marker::Sized {
+    /// Safe lossless bitwise transmute from `T` to `Self`.
+    fn from_bits(t: T) -> Self;
+}
+
+/// Safe lossless bitwise conversion from `Self` to `T`.
+pub trait IntoBits<T>: crate::marker::Sized {
+    /// Safe lossless bitwise transmute from `self` to `T`.
+    fn into_bits(self) -> T;
+}
+
+/// `FromBits` implies `IntoBits`.
+impl<T, U> IntoBits<U> for T
+where
+    U: FromBits<T>,
+{
+    #[inline]
+    fn into_bits(self) -> U {
+        debug_assert!(
+            crate::mem::size_of::<Self>() == crate::mem::size_of::<U>()
+        );
+        U::from_bits(self)
+    }
+}
+
+/// `FromBits` and `IntoBits` are reflexive
+impl<T> FromBits<T> for T {
+    #[inline]
+    fn from_bits(t: Self) -> Self {
+        t
+    }
+}
+
+#[macro_use]
+mod macros;
+
+mod v16;
+pub use self::v16::*;
+
+mod v32;
+pub use self::v32::*;
+
+mod v64;
+pub use self::v64::*;
+
+mod v128;
+pub use self::v128::*;
+
+mod v256;
+pub use self::v256::*;
+
+mod v512;
+pub use self::v512::*;
+
+mod arch_specific;
+pub use self::arch_specific::*;
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/into_bits/arch_specific.rs.html b/src/packed_simd/api/into_bits/arch_specific.rs.html new file mode 100644 index 000000000..3278f1e49 --- /dev/null +++ b/src/packed_simd/api/into_bits/arch_specific.rs.html @@ -0,0 +1,383 @@ +arch_specific.rs.html -- source
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+
+//! `FromBits` and `IntoBits` between portable vector types and the
+//! architecture-specific vector types.
+#![rustfmt::skip]
+
+// FIXME: MIPS FromBits/IntoBits
+
+#[allow(unused)]
+use crate::*;
+
+/// This macro implements FromBits for the portable and the architecture
+/// specific vector types.
+///
+/// The "leaf" case is at the bottom, and the most generic case is at the top.
+/// The generic case is split into smaller cases recursively.
+macro_rules! impl_arch {
+    ([$arch_head_i:ident[$arch_head_tt:tt]: $($arch_head_ty:ident),*],
+     $([$arch_tail_i:ident[$arch_tail_tt:tt]: $($arch_tail_ty:ident),*]),* |
+     from: $($from_ty:ident),* | into: $($into_ty:ident),* |
+     test: $test_tt:tt) => {
+        impl_arch!(
+            [$arch_head_i[$arch_head_tt]: $($arch_head_ty),*] |
+            from: $($from_ty),* |
+            into: $($into_ty),* |
+            test: $test_tt
+        );
+        impl_arch!(
+            $([$arch_tail_i[$arch_tail_tt]: $($arch_tail_ty),*]),* |
+            from: $($from_ty),* |
+            into: $($into_ty),* |
+            test: $test_tt
+        );
+    };
+    ([$arch:ident[$arch_tt:tt]: $($arch_ty:ident),*] |
+     from: $($from_ty:ident),* | into: $($into_ty:ident),* |
+     test: $test_tt:tt) => {
+        // note: if target is "arm", "+v7,+neon" must be enabled
+        // and the std library must be recompiled with them
+        #[cfg(any(
+            not(target_arch = "arm"),
+            all(target_feature = "v7", target_feature = "neon",
+                any(feature = "core_arch", libcore_neon)))
+        )]
+        // note: if target is "powerpc", "altivec" must be enabled
+        // and the std library must be recompiled with it
+        #[cfg(any(
+            not(target_arch = "powerpc"),
+            all(target_feature = "altivec", feature = "core_arch"),
+        ))]
+        #[cfg(target_arch = $arch_tt)]
+        use crate::arch::$arch::{
+            $($arch_ty),*
+        };
+
+        #[cfg(any(
+            not(target_arch = "arm"),
+            all(target_feature = "v7", target_feature = "neon",
+                any(feature = "core_arch", libcore_neon)))
+        )]
+        #[cfg(any(
+            not(target_arch = "powerpc"),
+            all(target_feature = "altivec", feature = "core_arch"),
+        ))]
+        #[cfg(target_arch = $arch_tt)]
+        impl_arch!($($arch_ty),* | $($from_ty),* | $($into_ty),* |
+                   test: $test_tt);
+    };
+    ($arch_head:ident, $($arch_tail:ident),* | $($from_ty:ident),*
+     | $($into_ty:ident),* | test: $test_tt:tt) => {
+        impl_arch!($arch_head | $($from_ty),* | $($into_ty),* |
+                   test: $test_tt);
+        impl_arch!($($arch_tail),* | $($from_ty),* | $($into_ty),* |
+                   test: $test_tt);
+    };
+    ($arch_head:ident | $($from_ty:ident),* | $($into_ty:ident),* |
+     test: $test_tt:tt) => {
+        impl_from_bits!($arch_head[$test_tt]: $($from_ty),*);
+        impl_into_bits!($arch_head[$test_tt]: $($into_ty),*);
+    };
+}
+
+////////////////////////////////////////////////////////////////////////////////
+// Implementations for the 64-bit wide vector types:
+
+// FIXME: 64-bit single element types
+// FIXME: arm/aarch float16x4_t missing
+impl_arch!(
+    [x86["x86"]: __m64], [x86_64["x86_64"]: __m64],
+    [arm["arm"]: int8x8_t, uint8x8_t, poly8x8_t, int16x4_t, uint16x4_t,
+     poly16x4_t, int32x2_t, uint32x2_t, float32x2_t, int64x1_t,
+     uint64x1_t],
+    [aarch64["aarch64"]: int8x8_t, uint8x8_t, poly8x8_t, int16x4_t, uint16x4_t,
+     poly16x4_t, int32x2_t, uint32x2_t, float32x2_t, int64x1_t, uint64x1_t,
+     float64x1_t] |
+    from: i8x8, u8x8, m8x8, i16x4, u16x4, m16x4, i32x2, u32x2, f32x2, m32x2 |
+    into: i8x8, u8x8, i16x4, u16x4, i32x2, u32x2, f32x2 |
+    test: test_v64
+);
+
+////////////////////////////////////////////////////////////////////////////////
+// Implementations for the 128-bit wide vector types:
+
+// FIXME: arm/aarch float16x8_t missing
+// FIXME: ppc vector_pixel missing
+// FIXME: ppc64 vector_Float16 missing
+// FIXME: ppc64 vector_signed_long_long missing
+// FIXME: ppc64 vector_unsigned_long_long missing
+// FIXME: ppc64 vector_bool_long_long missing
+// FIXME: ppc64 vector_signed___int128 missing
+// FIXME: ppc64 vector_unsigned___int128 missing
+impl_arch!(
+    [x86["x86"]: __m128, __m128i, __m128d],
+    [x86_64["x86_64"]:  __m128, __m128i, __m128d],
+    [arm["arm"]: int8x16_t, uint8x16_t, poly8x16_t, int16x8_t, uint16x8_t,
+     poly16x8_t, int32x4_t, uint32x4_t, float32x4_t, int64x2_t, uint64x2_t],
+    [aarch64["aarch64"]: int8x16_t, uint8x16_t, poly8x16_t, int16x8_t,
+     uint16x8_t, poly16x8_t, int32x4_t, uint32x4_t, float32x4_t, int64x2_t,
+     uint64x2_t, float64x2_t],
+    [powerpc["powerpc"]: vector_signed_char, vector_unsigned_char,
+     vector_signed_short, vector_unsigned_short, vector_signed_int,
+     vector_unsigned_int, vector_float],
+    [powerpc64["powerpc64"]: vector_signed_char, vector_unsigned_char,
+     vector_signed_short, vector_unsigned_short, vector_signed_int,
+     vector_unsigned_int,  vector_float, vector_signed_long,
+     vector_unsigned_long, vector_double] |
+    from: i8x16, u8x16, m8x16, i16x8, u16x8, m16x8, i32x4, u32x4, f32x4, m32x4,
+    i64x2, u64x2, f64x2, m64x2, i128x1, u128x1, m128x1 |
+    into: i8x16, u8x16, i16x8, u16x8, i32x4, u32x4, f32x4, i64x2, u64x2, f64x2,
+    i128x1, u128x1 |
+    test: test_v128
+);
+
+impl_arch!(
+    [powerpc["powerpc"]: vector_bool_char],
+    [powerpc64["powerpc64"]: vector_bool_char] |
+    from: m8x16, m16x8, m32x4, m64x2, m128x1 |
+    into: i8x16, u8x16, i16x8, u16x8, i32x4, u32x4, f32x4,
+    i64x2, u64x2, f64x2, i128x1, u128x1,
+    // Masks:
+    m8x16 |
+    test: test_v128
+);
+
+impl_arch!(
+    [powerpc["powerpc"]: vector_bool_short],
+    [powerpc64["powerpc64"]: vector_bool_short] |
+    from: m16x8, m32x4, m64x2, m128x1 |
+    into: i8x16, u8x16, i16x8, u16x8, i32x4, u32x4, f32x4,
+    i64x2, u64x2, f64x2, i128x1, u128x1,
+    // Masks:
+    m8x16, m16x8 |
+    test: test_v128
+);
+
+impl_arch!(
+    [powerpc["powerpc"]: vector_bool_int],
+    [powerpc64["powerpc64"]: vector_bool_int] |
+    from: m32x4, m64x2, m128x1 |
+    into: i8x16, u8x16, i16x8, u16x8, i32x4, u32x4, f32x4,
+    i64x2, u64x2, f64x2, i128x1, u128x1,
+    // Masks:
+    m8x16, m16x8, m32x4 |
+    test: test_v128
+);
+
+impl_arch!(
+    [powerpc64["powerpc64"]: vector_bool_long] |
+    from: m64x2, m128x1 |
+    into: i8x16, u8x16, i16x8, u16x8, i32x4, u32x4, f32x4,
+    i64x2, u64x2, f64x2, i128x1, u128x1,
+    // Masks:
+    m8x16, m16x8, m32x4, m64x2 |
+    test: test_v128
+);
+
+////////////////////////////////////////////////////////////////////////////////
+// Implementations for the 256-bit wide vector types
+
+impl_arch!(
+    [x86["x86"]: __m256, __m256i, __m256d],
+    [x86_64["x86_64"]:  __m256, __m256i, __m256d] |
+    from: i8x32, u8x32, m8x32, i16x16, u16x16, m16x16,
+    i32x8, u32x8, f32x8, m32x8,
+    i64x4, u64x4, f64x4, m64x4, i128x2, u128x2, m128x2 |
+    into: i8x32, u8x32, i16x16, u16x16, i32x8, u32x8, f32x8,
+    i64x4, u64x4, f64x4, i128x2, u128x2 |
+    test: test_v256
+);
+
+////////////////////////////////////////////////////////////////////////////////
+// FIXME: Implementations for the 512-bit wide vector types
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/into_bits/macros.rs.html b/src/packed_simd/api/into_bits/macros.rs.html new file mode 100644 index 000000000..aa83c8121 --- /dev/null +++ b/src/packed_simd/api/into_bits/macros.rs.html @@ -0,0 +1,151 @@ +macros.rs.html -- source
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+//! Macros implementing `FromBits`
+
+macro_rules! impl_from_bits_ {
+    ($id:ident[$test_tt:tt]: $from_ty:ident) => {
+        impl crate::api::into_bits::FromBits<$from_ty> for $id {
+            #[inline]
+            fn from_bits(x: $from_ty) -> Self {
+                unsafe { crate::mem::transmute(x) }
+            }
+        }
+
+        test_if! {
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _from_bits_ $from_ty>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn test() {
+                        use crate::{
+                            ptr::{read_unaligned},
+                            mem::{size_of, zeroed}
+                        };
+                        use crate::IntoBits;
+                        assert_eq!(size_of::<$id>(),
+                                   size_of::<$from_ty>());
+                        // This is safe becasue we never create a reference to
+                        // uninitialized memory:
+                        let a: $from_ty = unsafe { zeroed() };
+
+                        let b_0: $id = crate::FromBits::from_bits(a);
+                        let b_1: $id = a.into_bits();
+
+                        // Check that these are byte-wise equal, that is,
+                        // that the bit patterns are identical:
+                        for i in 0..size_of::<$id>() {
+                            // This is safe because we only read initialized
+                            // memory in bounds. Also, taking a reference to
+                            // `b_i` is ok because the fields are initialized.
+                            unsafe {
+                                let b_0_v: u8 = read_unaligned(
+                                    (&b_0 as *const $id as *const u8)
+                                        .wrapping_add(i)
+                                );
+                                let b_1_v: u8 = read_unaligned(
+                                    (&b_1 as *const $id as *const u8)
+                                        .wrapping_add(i)
+                                );
+                                assert_eq!(b_0_v, b_1_v);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    };
+}
+
+macro_rules! impl_from_bits {
+    ($id:ident[$test_tt:tt]: $($from_ty:ident),*) => {
+        $(
+            impl_from_bits_!($id[$test_tt]: $from_ty);
+        )*
+    }
+}
+
+#[allow(unused)]
+macro_rules! impl_into_bits {
+    ($id:ident[$test_tt:tt]: $($from_ty:ident),*) => {
+        $(
+            impl_from_bits_!($from_ty[$test_tt]: $id);
+        )*
+    }
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/into_bits/v128.rs.html b/src/packed_simd/api/into_bits/v128.rs.html new file mode 100644 index 000000000..dd250b212 --- /dev/null +++ b/src/packed_simd/api/into_bits/v128.rs.html @@ -0,0 +1,59 @@ +v128.rs.html -- source
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+
+//! `FromBits` and `IntoBits` implementations for portable 128-bit wide vectors
+#![rustfmt::skip]
+
+#[allow(unused)]  // wasm_bindgen_test
+use crate::*;
+
+impl_from_bits!(i8x16[test_v128]: u8x16, m8x16, i16x8, u16x8, m16x8, i32x4, u32x4, f32x4, m32x4, i64x2, u64x2, f64x2, m64x2, i128x1, u128x1, m128x1);
+impl_from_bits!(u8x16[test_v128]: i8x16, m8x16, i16x8, u16x8, m16x8, i32x4, u32x4, f32x4, m32x4, i64x2, u64x2, f64x2, m64x2, i128x1, u128x1, m128x1);
+impl_from_bits!(m8x16[test_v128]: m16x8, m32x4, m64x2, m128x1);
+
+impl_from_bits!(i16x8[test_v128]: i8x16, u8x16, m8x16, u16x8, m16x8, i32x4, u32x4, f32x4, m32x4, i64x2, u64x2, f64x2, m64x2, i128x1, u128x1, m128x1);
+impl_from_bits!(u16x8[test_v128]: i8x16, u8x16, m8x16, i16x8, m16x8, i32x4, u32x4, f32x4, m32x4, i64x2, u64x2, f64x2, m64x2, i128x1, u128x1, m128x1);
+impl_from_bits!(m16x8[test_v128]: m32x4, m64x2, m128x1);
+
+impl_from_bits!(i32x4[test_v128]: i8x16, u8x16, m8x16, i16x8, u16x8, m16x8, u32x4, f32x4, m32x4, i64x2, u64x2, f64x2, m64x2, i128x1, u128x1, m128x1);
+impl_from_bits!(u32x4[test_v128]: i8x16, u8x16, m8x16, i16x8, u16x8, m16x8, i32x4, f32x4, m32x4, i64x2, u64x2, f64x2, m64x2, i128x1, u128x1, m128x1);
+impl_from_bits!(f32x4[test_v128]: i8x16, u8x16, m8x16, i16x8, u16x8, m16x8, i32x4, u32x4, m32x4, i64x2, u64x2, f64x2, m64x2, i128x1, u128x1, m128x1);
+impl_from_bits!(m32x4[test_v128]: m64x2, m128x1);
+
+impl_from_bits!(i64x2[test_v128]: i8x16, u8x16, m8x16, i16x8, u16x8, m16x8, i32x4, u32x4, f32x4, m32x4, u64x2, f64x2, m64x2, i128x1, u128x1, m128x1);
+impl_from_bits!(u64x2[test_v128]: i8x16, u8x16, m8x16, i16x8, u16x8, m16x8, i32x4, u32x4, f32x4, m32x4, i64x2, f64x2, m64x2, i128x1, u128x1, m128x1);
+impl_from_bits!(f64x2[test_v128]: i8x16, u8x16, m8x16, i16x8, u16x8, m16x8, i32x4, u32x4, f32x4, m32x4, i64x2, u64x2, m64x2, i128x1, u128x1, m128x1);
+impl_from_bits!(m64x2[test_v128]: m128x1);
+
+impl_from_bits!(i128x1[test_v128]: i8x16, u8x16, m8x16, i16x8, u16x8, m16x8, i32x4, u32x4, f32x4, m32x4, i64x2, u64x2, f64x2, m64x2, u128x1, m128x1);
+impl_from_bits!(u128x1[test_v128]: i8x16, u8x16, m8x16, i16x8, u16x8, m16x8, i32x4, u32x4, f32x4, m32x4, i64x2, u64x2, f64x2, m64x2, i128x1, m128x1);
+// note: m128x1 cannot be constructed from all the other masks bit patterns in here
+
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/into_bits/v16.rs.html b/src/packed_simd/api/into_bits/v16.rs.html new file mode 100644 index 000000000..0a72e11df --- /dev/null +++ b/src/packed_simd/api/into_bits/v16.rs.html @@ -0,0 +1,21 @@ +v16.rs.html -- source
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+
+//! `FromBits` and `IntoBits` implementations for portable 16-bit wide vectors
+#![rustfmt::skip]
+
+#[allow(unused)]  // wasm_bindgen_test
+use crate::*;
+
+impl_from_bits!(i8x2[test_v16]: u8x2, m8x2);
+impl_from_bits!(u8x2[test_v16]: i8x2, m8x2);
+// note: m8x2 cannot be constructed from all i8x2 or u8x2 bit patterns
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/into_bits/v256.rs.html b/src/packed_simd/api/into_bits/v256.rs.html new file mode 100644 index 000000000..acbc4a207 --- /dev/null +++ b/src/packed_simd/api/into_bits/v256.rs.html @@ -0,0 +1,57 @@ +v256.rs.html -- source
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+
+//! `FromBits` and `IntoBits` implementations for portable 256-bit wide vectors
+#![rustfmt::skip]
+
+#[allow(unused)]  // wasm_bindgen_test
+use crate::*;
+
+impl_from_bits!(i8x32[test_v256]: u8x32, m8x32, i16x16, u16x16, m16x16, i32x8, u32x8, f32x8, m32x8, i64x4, u64x4, f64x4, m64x4, i128x2, u128x2, m128x2);
+impl_from_bits!(u8x32[test_v256]: i8x32, m8x32, i16x16, u16x16, m16x16, i32x8, u32x8, f32x8, m32x8, i64x4, u64x4, f64x4, m64x4, i128x2, u128x2, m128x2);
+impl_from_bits!(m8x32[test_v256]: m16x16, m32x8, m64x4, m128x2);
+
+impl_from_bits!(i16x16[test_v256]: i8x32, u8x32, m8x32, u16x16, m16x16, i32x8, u32x8, f32x8, m32x8, i64x4, u64x4, f64x4, m64x4, i128x2, u128x2, m128x2);
+impl_from_bits!(u16x16[test_v256]: i8x32, u8x32, m8x32, i16x16, m16x16, i32x8, u32x8, f32x8, m32x8, i64x4, u64x4, f64x4, m64x4, i128x2, u128x2, m128x2);
+impl_from_bits!(m16x16[test_v256]: m32x8, m64x4, m128x2);
+
+impl_from_bits!(i32x8[test_v256]: i8x32, u8x32, m8x32, i16x16, u16x16, m16x16, u32x8, f32x8, m32x8, i64x4, u64x4, f64x4, m64x4, i128x2, u128x2, m128x2);
+impl_from_bits!(u32x8[test_v256]: i8x32, u8x32, m8x32, i16x16, u16x16, m16x16, i32x8, f32x8, m32x8, i64x4, u64x4, f64x4, m64x4, i128x2, u128x2, m128x2);
+impl_from_bits!(f32x8[test_v256]: i8x32, u8x32, m8x32, i16x16, u16x16, m16x16, i32x8, u32x8, m32x8, i64x4, u64x4, f64x4, m64x4, i128x2, u128x2, m128x2);
+impl_from_bits!(m32x8[test_v256]: m64x4, m128x2);
+
+impl_from_bits!(i64x4[test_v256]: i8x32, u8x32, m8x32, i16x16, u16x16, m16x16, i32x8, u32x8, f32x8, m32x8, u64x4, f64x4, m64x4, i128x2, u128x2, m128x2);
+impl_from_bits!(u64x4[test_v256]: i8x32, u8x32, m8x32, i16x16, u16x16, m16x16, i32x8, u32x8, f32x8, m32x8, i64x4, f64x4, m64x4, i128x2, u128x2, m128x2);
+impl_from_bits!(f64x4[test_v256]: i8x32, u8x32, m8x32, i16x16, u16x16, m16x16, i32x8, u32x8, f32x8, m32x8, i64x4, u64x4, m64x4, i128x2, u128x2, m128x2);
+impl_from_bits!(m64x4[test_v256]: m128x2);
+
+impl_from_bits!(i128x2[test_v256]: i8x32, u8x32, m8x32, i16x16, u16x16, m16x16, i32x8, u32x8, f32x8, m32x8, i64x4, u64x4, f64x4, m64x4, u128x2, m128x2);
+impl_from_bits!(u128x2[test_v256]: i8x32, u8x32, m8x32, i16x16, u16x16, m16x16, i32x8, u32x8, f32x8, m32x8, i64x4, u64x4, f64x4, m64x4, i128x2, m128x2);
+// note: m128x2 cannot be constructed from all the other masks bit patterns in here
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/into_bits/v32.rs.html b/src/packed_simd/api/into_bits/v32.rs.html new file mode 100644 index 000000000..6ba823846 --- /dev/null +++ b/src/packed_simd/api/into_bits/v32.rs.html @@ -0,0 +1,29 @@ +v32.rs.html -- source
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+//! `FromBits` and `IntoBits` implementations for portable 32-bit wide vectors
+#![rustfmt::skip]
+
+#[allow(unused)]  // wasm_bindgen_test
+use crate::*;
+
+impl_from_bits!(i8x4[test_v32]: u8x4, m8x4, i16x2, u16x2, m16x2);
+impl_from_bits!(u8x4[test_v32]: i8x4, m8x4, i16x2, u16x2, m16x2);
+impl_from_bits!(m8x4[test_v32]: m16x2);
+
+impl_from_bits!(i16x2[test_v32]: i8x4, u8x4, m8x4, u16x2, m16x2);
+impl_from_bits!(u16x2[test_v32]: i8x4, u8x4, m8x4, i16x2, m16x2);
+// note: m16x2 cannot be constructed from all m8x4 bit patterns
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/into_bits/v512.rs.html b/src/packed_simd/api/into_bits/v512.rs.html new file mode 100644 index 000000000..9bd9f9231 --- /dev/null +++ b/src/packed_simd/api/into_bits/v512.rs.html @@ -0,0 +1,57 @@ +v512.rs.html -- source
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+//! `FromBits` and `IntoBits` implementations for portable 512-bit wide vectors
+#![rustfmt::skip]
+
+#[allow(unused)]  // wasm_bindgen_test
+use crate::*;
+
+impl_from_bits!(i8x64[test_v512]: u8x64, m8x64, i16x32, u16x32, m16x32, i32x16, u32x16, f32x16, m32x16, i64x8, u64x8, f64x8, m64x8, i128x4, u128x4, m128x4);
+impl_from_bits!(u8x64[test_v512]: i8x64, m8x64, i16x32, u16x32, m16x32, i32x16, u32x16, f32x16, m32x16, i64x8, u64x8, f64x8, m64x8, i128x4, u128x4, m128x4);
+impl_from_bits!(m8x64[test_v512]: m16x32, m32x16, m64x8, m128x4);
+
+impl_from_bits!(i16x32[test_v512]: i8x64, u8x64, m8x64, u16x32, m16x32, i32x16, u32x16, f32x16, m32x16, i64x8, u64x8, f64x8, m64x8, i128x4, u128x4, m128x4);
+impl_from_bits!(u16x32[test_v512]: i8x64, u8x64, m8x64, i16x32, m16x32, i32x16, u32x16, f32x16, m32x16, i64x8, u64x8, f64x8, m64x8, i128x4, u128x4, m128x4);
+impl_from_bits!(m16x32[test_v512]: m32x16, m64x8, m128x4);
+
+impl_from_bits!(i32x16[test_v512]: i8x64, u8x64, m8x64, i16x32, u16x32, m16x32, u32x16, f32x16, m32x16, i64x8, u64x8, f64x8, m64x8, i128x4, u128x4, m128x4);
+impl_from_bits!(u32x16[test_v512]: i8x64, u8x64, m8x64, i16x32, u16x32, m16x32, i32x16, f32x16, m32x16, i64x8, u64x8, f64x8, m64x8, i128x4, u128x4, m128x4);
+impl_from_bits!(f32x16[test_v512]: i8x64, u8x64, m8x64, i16x32, u16x32, m16x32, i32x16, u32x16, m32x16, i64x8, u64x8, f64x8, m64x8, i128x4, u128x4, m128x4);
+impl_from_bits!(m32x16[test_v512]: m64x8, m128x4);
+
+impl_from_bits!(i64x8[test_v512]: i8x64, u8x64, m8x64, i16x32, u16x32, m16x32, i32x16, u32x16, f32x16, m32x16, u64x8, f64x8, m64x8, i128x4, u128x4, m128x4);
+impl_from_bits!(u64x8[test_v512]: i8x64, u8x64, m8x64, i16x32, u16x32, m16x32, i32x16, u32x16, f32x16, m32x16, i64x8, f64x8, m64x8, i128x4, u128x4, m128x4);
+impl_from_bits!(f64x8[test_v512]: i8x64, u8x64, m8x64, i16x32, u16x32, m16x32, i32x16, u32x16, f32x16, m32x16, i64x8, u64x8, m64x8, i128x4, u128x4, m128x4);
+impl_from_bits!(m64x8[test_v512]: m128x4);
+
+impl_from_bits!(i128x4[test_v512]: i8x64, u8x64, m8x64, i16x32, u16x32, m16x32, i32x16, u32x16, f32x16, m32x16, i64x8, u64x8, f64x8, m64x8, u128x4, m128x4);
+impl_from_bits!(u128x4[test_v512]: i8x64, u8x64, m8x64, i16x32, u16x32, m16x32, i32x16, u32x16, f32x16, m32x16, i64x8, u64x8, f64x8, m64x8, i128x4, m128x4);
+// note: m128x4 cannot be constructed from all the other masks bit patterns in here
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/into_bits/v64.rs.html b/src/packed_simd/api/into_bits/v64.rs.html new file mode 100644 index 000000000..811679851 --- /dev/null +++ b/src/packed_simd/api/into_bits/v64.rs.html @@ -0,0 +1,39 @@ +v64.rs.html -- source
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+//! `FromBits` and `IntoBits` implementations for portable 64-bit wide vectors
+#![rustfmt::skip]
+
+#[allow(unused)]  // wasm_bindgen_test
+use crate::*;
+
+impl_from_bits!(i8x8[test_v64]: u8x8, m8x8, i16x4, u16x4, m16x4, i32x2, u32x2, f32x2, m32x2);
+impl_from_bits!(u8x8[test_v64]: i8x8, m8x8, i16x4, u16x4, m16x4, i32x2, u32x2, f32x2, m32x2);
+impl_from_bits!(m8x8[test_v64]: m16x4, m32x2);
+
+impl_from_bits!(i16x4[test_v64]: i8x8, u8x8, m8x8, u16x4, m16x4, i32x2, u32x2, f32x2, m32x2);
+impl_from_bits!(u16x4[test_v64]: i8x8, u8x8, m8x8, i16x4, m16x4, i32x2, u32x2, f32x2, m32x2);
+impl_from_bits!(m16x4[test_v64]: m32x2);
+
+impl_from_bits!(i32x2[test_v64]: i8x8, u8x8, m8x8, i16x4, u16x4, m16x4, u32x2, f32x2, m32x2);
+impl_from_bits!(u32x2[test_v64]: i8x8, u8x8, m8x8, i16x4, u16x4, m16x4, i32x2, f32x2, m32x2);
+impl_from_bits!(f32x2[test_v64]: i8x8, u8x8, m8x8, i16x4, u16x4, m16x4, i32x2, u32x2, m32x2);
+// note: m32x2 cannot be constructed from all m16x4 or m8x8 bit patterns
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/math.rs.html b/src/packed_simd/api/math.rs.html new file mode 100644 index 000000000..3efd96a3e --- /dev/null +++ b/src/packed_simd/api/math.rs.html @@ -0,0 +1,11 @@ +math.rs.html -- source
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+//! Implements vertical math operations
+
+#[macro_use]
+mod float;
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/math/float.rs.html b/src/packed_simd/api/math/float.rs.html new file mode 100644 index 000000000..fb967d85c --- /dev/null +++ b/src/packed_simd/api/math/float.rs.html @@ -0,0 +1,131 @@ +float.rs.html -- source
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+
+//! Implements vertical floating-point math operations.
+
+#[macro_use]
+mod abs;
+
+#[macro_use]
+mod consts;
+
+#[macro_use]
+mod cos;
+
+#[macro_use]
+mod exp;
+
+#[macro_use]
+mod powf;
+
+#[macro_use]
+mod ln;
+
+#[macro_use]
+mod mul_add;
+
+#[macro_use]
+mod mul_adde;
+
+#[macro_use]
+mod recpre;
+
+#[macro_use]
+mod rsqrte;
+
+#[macro_use]
+mod sin;
+
+#[macro_use]
+mod sqrt;
+
+#[macro_use]
+mod sqrte;
+
+#[macro_use]
+mod tanh;
+
+macro_rules! impl_float_category {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident, $mask_ty:ident) => {
+        impl $id {
+            #[inline]
+            pub fn is_nan(self) -> $mask_ty {
+                self.ne(self)
+            }
+
+            #[inline]
+            pub fn is_infinite(self) -> $mask_ty {
+                self.eq(Self::INFINITY) | self.eq(Self::NEG_INFINITY)
+            }
+
+            #[inline]
+            pub fn is_finite(self) -> $mask_ty {
+                !(self.is_nan() | self.is_infinite())
+            }
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/math/float/abs.rs.html b/src/packed_simd/api/math/float/abs.rs.html new file mode 100644 index 000000000..ed1c2c6c1 --- /dev/null +++ b/src/packed_simd/api/math/float/abs.rs.html @@ -0,0 +1,65 @@ +abs.rs.html -- source
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+//! Implements vertical (lane-wise) floating-point `abs`.
+
+macro_rules! impl_math_float_abs {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident | $test_tt:tt) => {
+        impl $id {
+            /// Absolute value.
+            #[inline]
+            pub fn abs(self) -> Self {
+                use crate::codegen::math::float::abs::Abs;
+                Abs::abs(self)
+            }
+        }
+
+        test_if!{
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _math_abs>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn abs() {
+                        let o = $id::splat(1 as $elem_ty);
+                        assert_eq!(o, o.abs());
+
+                        let mo = $id::splat(-1 as $elem_ty);
+                        assert_eq!(o, mo.abs());
+                    }
+                }
+            }
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/math/float/consts.rs.html b/src/packed_simd/api/math/float/consts.rs.html new file mode 100644 index 000000000..a56b88d2d --- /dev/null +++ b/src/packed_simd/api/math/float/consts.rs.html @@ -0,0 +1,175 @@ +consts.rs.html -- source
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+macro_rules! impl_float_consts {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident) => {
+        impl $id {
+            /// Machine epsilon value.
+            pub const EPSILON: $id = $id::splat(core::$elem_ty::EPSILON);
+
+            /// Smallest finite value.
+            pub const MIN: $id = $id::splat(core::$elem_ty::MIN);
+
+            /// Smallest positive normal value.
+            pub const MIN_POSITIVE: $id =
+                $id::splat(core::$elem_ty::MIN_POSITIVE);
+
+            /// Largest finite value.
+            pub const MAX: $id = $id::splat(core::$elem_ty::MAX);
+
+            /// Not a Number (NaN).
+            pub const NAN: $id = $id::splat(core::$elem_ty::NAN);
+
+            /// Infinity (∞).
+            pub const INFINITY: $id = $id::splat(core::$elem_ty::INFINITY);
+
+            /// Negative infinity (-∞).
+            pub const NEG_INFINITY: $id =
+                $id::splat(core::$elem_ty::NEG_INFINITY);
+
+            /// Archimedes' constant (π)
+            pub const PI: $id = $id::splat(core::$elem_ty::consts::PI);
+
+            /// π/2
+            pub const FRAC_PI_2: $id =
+                $id::splat(core::$elem_ty::consts::FRAC_PI_2);
+
+            /// π/3
+            pub const FRAC_PI_3: $id =
+                $id::splat(core::$elem_ty::consts::FRAC_PI_3);
+
+            /// π/4
+            pub const FRAC_PI_4: $id =
+                $id::splat(core::$elem_ty::consts::FRAC_PI_4);
+
+            /// π/6
+            pub const FRAC_PI_6: $id =
+                $id::splat(core::$elem_ty::consts::FRAC_PI_6);
+
+            /// π/8
+            pub const FRAC_PI_8: $id =
+                $id::splat(core::$elem_ty::consts::FRAC_PI_8);
+
+            /// 1/π
+            pub const FRAC_1_PI: $id =
+                $id::splat(core::$elem_ty::consts::FRAC_1_PI);
+
+            /// 2/π
+            pub const FRAC_2_PI: $id =
+                $id::splat(core::$elem_ty::consts::FRAC_2_PI);
+
+            /// 2/sqrt(π)
+            pub const FRAC_2_SQRT_PI: $id =
+                $id::splat(core::$elem_ty::consts::FRAC_2_SQRT_PI);
+
+            /// sqrt(2)
+            pub const SQRT_2: $id = $id::splat(core::$elem_ty::consts::SQRT_2);
+
+            /// 1/sqrt(2)
+            pub const FRAC_1_SQRT_2: $id =
+                $id::splat(core::$elem_ty::consts::FRAC_1_SQRT_2);
+
+            /// Euler's number (e)
+            pub const E: $id = $id::splat(core::$elem_ty::consts::E);
+
+            /// log<sub>2</sub>(e)
+            pub const LOG2_E: $id = $id::splat(core::$elem_ty::consts::LOG2_E);
+
+            /// log<sub>10</sub>(e)
+            pub const LOG10_E: $id =
+                $id::splat(core::$elem_ty::consts::LOG10_E);
+
+            /// ln(2)
+            pub const LN_2: $id = $id::splat(core::$elem_ty::consts::LN_2);
+
+            /// ln(10)
+            pub const LN_10: $id = $id::splat(core::$elem_ty::consts::LN_10);
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/math/float/cos.rs.html b/src/packed_simd/api/math/float/cos.rs.html new file mode 100644 index 000000000..95373e1ec --- /dev/null +++ b/src/packed_simd/api/math/float/cos.rs.html @@ -0,0 +1,91 @@ +cos.rs.html -- source
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+//! Implements vertical (lane-wise) floating-point `cos`.
+
+macro_rules! impl_math_float_cos {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident | $test_tt:tt) => {
+        impl $id {
+            /// Cosine.
+            #[inline]
+            pub fn cos(self) -> Self {
+                use crate::codegen::math::float::cos::Cos;
+                Cos::cos(self)
+            }
+
+            /// Cosine of `self * PI`.
+            #[inline]
+            pub fn cos_pi(self) -> Self {
+                use crate::codegen::math::float::cos_pi::CosPi;
+                CosPi::cos_pi(self)
+            }
+        }
+
+        test_if!{
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _math_cos>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn cos() {
+                        use crate::$elem_ty::consts::PI;
+                        let z = $id::splat(0 as $elem_ty);
+                        let o = $id::splat(1 as $elem_ty);
+                        let p = $id::splat(PI as $elem_ty);
+                        let ph = $id::splat(PI as $elem_ty / 2.);
+                        let z_r = $id::splat((PI as $elem_ty / 2.).cos());
+                        let o_r = $id::splat((PI as $elem_ty).cos());
+
+                        assert_eq!(o, z.cos());
+                        assert_eq!(z_r, ph.cos());
+                        assert_eq!(o_r, p.cos());
+                    }
+                }
+            }
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/math/float/exp.rs.html b/src/packed_simd/api/math/float/exp.rs.html new file mode 100644 index 000000000..ec3d4743b --- /dev/null +++ b/src/packed_simd/api/math/float/exp.rs.html @@ -0,0 +1,69 @@ +exp.rs.html -- source
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+//! Implements vertical (lane-wise) floating-point `exp`.
+
+macro_rules! impl_math_float_exp {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident | $test_tt:tt) => {
+        impl $id {
+            /// Returns the exponential function of `self`: `e^(self)`.
+            #[inline]
+            pub fn exp(self) -> Self {
+                use crate::codegen::math::float::exp::Exp;
+                Exp::exp(self)
+            }
+        }
+
+        test_if!{
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _math_exp>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn exp() {
+                        let z = $id::splat(0 as $elem_ty);
+                        let o = $id::splat(1 as $elem_ty);
+                        assert_eq!(o, z.exp());
+
+                        let e = $id::splat(crate::f64::consts::E as $elem_ty);
+                        let tol = $id::splat(2.4e-4 as $elem_ty);
+                        assert!((e - o.exp()).abs().le(tol).all());
+                    }
+                }
+            }
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/math/float/ln.rs.html b/src/packed_simd/api/math/float/ln.rs.html new file mode 100644 index 000000000..4180f1d98 --- /dev/null +++ b/src/packed_simd/api/math/float/ln.rs.html @@ -0,0 +1,69 @@ +ln.rs.html -- source
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+//! Implements vertical (lane-wise) floating-point `ln`.
+
+macro_rules! impl_math_float_ln {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident | $test_tt:tt) => {
+        impl $id {
+            /// Returns the natural logarithm of `self`.
+            #[inline]
+            pub fn ln(self) -> Self {
+                use crate::codegen::math::float::ln::Ln;
+                Ln::ln(self)
+            }
+        }
+
+        test_if!{
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _math_ln>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn ln() {
+                        let z = $id::splat(0 as $elem_ty);
+                        let o = $id::splat(1 as $elem_ty);
+                        assert_eq!(z, o.ln());
+
+                        let e = $id::splat(crate::f64::consts::E as $elem_ty);
+                        let tol = $id::splat(2.4e-4 as $elem_ty);
+                        assert!((o - e.ln()).abs().le(tol).all());
+                    }
+                }
+            }
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/math/float/mul_add.rs.html b/src/packed_simd/api/math/float/mul_add.rs.html new file mode 100644 index 000000000..e467c893e --- /dev/null +++ b/src/packed_simd/api/math/float/mul_add.rs.html @@ -0,0 +1,91 @@ +mul_add.rs.html -- source
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+//! Implements vertical (lane-wise) floating-point `mul_add`.
+
+macro_rules! impl_math_float_mul_add {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident | $test_tt:tt) => {
+        impl $id {
+            /// Fused multiply add: `self * y + z`
+            #[inline]
+            pub fn mul_add(self, y: Self, z: Self) -> Self {
+                use crate::codegen::math::float::mul_add::MulAdd;
+                MulAdd::mul_add(self, y, z)
+            }
+        }
+
+        test_if!{
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _math_mul_add>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn mul_add() {
+                        let z = $id::splat(0 as $elem_ty);
+                        let o = $id::splat(1 as $elem_ty);
+                        let t = $id::splat(2 as $elem_ty);
+                        let t3 = $id::splat(3 as $elem_ty);
+                        let f = $id::splat(4 as $elem_ty);
+
+                        assert_eq!(z, z.mul_add(z, z));
+                        assert_eq!(o, o.mul_add(o, z));
+                        assert_eq!(o, o.mul_add(z, o));
+                        assert_eq!(o, z.mul_add(o, o));
+
+                        assert_eq!(t, o.mul_add(o, o));
+                        assert_eq!(t, o.mul_add(t, z));
+                        assert_eq!(t, t.mul_add(o, z));
+
+                        assert_eq!(f, t.mul_add(t, z));
+                        assert_eq!(f, t.mul_add(o, t));
+                        assert_eq!(t3, t.mul_add(o, o));
+                    }
+                }
+            }
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/math/float/mul_adde.rs.html b/src/packed_simd/api/math/float/mul_adde.rs.html new file mode 100644 index 000000000..a92daf836 --- /dev/null +++ b/src/packed_simd/api/math/float/mul_adde.rs.html @@ -0,0 +1,99 @@ +mul_adde.rs.html -- source
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+//! Implements vertical (lane-wise) floating-point `mul_adde`.
+
+macro_rules! impl_math_float_mul_adde {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident | $test_tt:tt) => {
+        impl $id {
+            /// Fused multiply add estimate: ~= `self * y + z`
+            ///
+            /// While fused multiply-add (`fma`) has infinite precision,
+            /// `mul_adde` has _at worst_ the same precision of a multiply followed by an add.
+            /// This might be more efficient on architectures that do not have an `fma` instruction.
+            #[inline]
+            pub fn mul_adde(self, y: Self, z: Self) -> Self {
+                use crate::codegen::math::float::mul_adde::MulAddE;
+                MulAddE::mul_adde(self, y, z)
+            }
+        }
+
+        test_if!{
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _math_mul_adde>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn mul_adde() {
+                        let z = $id::splat(0 as $elem_ty);
+                        let o = $id::splat(1 as $elem_ty);
+                        let t = $id::splat(2 as $elem_ty);
+                        let t3 = $id::splat(3 as $elem_ty);
+                        let f = $id::splat(4 as $elem_ty);
+
+                        assert_eq!(z, z.mul_adde(z, z));
+                        assert_eq!(o, o.mul_adde(o, z));
+                        assert_eq!(o, o.mul_adde(z, o));
+                        assert_eq!(o, z.mul_adde(o, o));
+
+                        assert_eq!(t, o.mul_adde(o, o));
+                        assert_eq!(t, o.mul_adde(t, z));
+                        assert_eq!(t, t.mul_adde(o, z));
+
+                        assert_eq!(f, t.mul_adde(t, z));
+                        assert_eq!(f, t.mul_adde(o, t));
+                        assert_eq!(t3, t.mul_adde(o, o));
+                    }
+                }
+            }
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/math/float/powf.rs.html b/src/packed_simd/api/math/float/powf.rs.html new file mode 100644 index 000000000..cc26fe4c3 --- /dev/null +++ b/src/packed_simd/api/math/float/powf.rs.html @@ -0,0 +1,75 @@ +powf.rs.html -- source
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+//! Implements vertical (lane-wise) floating-point `powf`.
+
+macro_rules! impl_math_float_powf {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident | $test_tt:tt) => {
+        impl $id {
+            /// Raises `self` number to the floating point power of `x`.
+            #[inline]
+            pub fn powf(self, x: Self) -> Self {
+                use crate::codegen::math::float::powf::Powf;
+                Powf::powf(self, x)
+            }
+        }
+
+        test_if!{
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _math_powf>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn powf() {
+                        let z = $id::splat(0 as $elem_ty);
+                        let o = $id::splat(1 as $elem_ty);
+                        let t = $id::splat(2 as $elem_ty);
+                        assert_eq!(o, o.powf(z));
+                        assert_eq!(o, t.powf(z));
+                        assert_eq!(o, o.powf(o));
+                        assert_eq!(t, t.powf(o));
+
+                        let f = $id::splat(4 as $elem_ty);
+                        assert_eq!(f, t.powf(t));
+                    }
+                }
+            }
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/math/float/recpre.rs.html b/src/packed_simd/api/math/float/recpre.rs.html new file mode 100644 index 000000000..696f4ed34 --- /dev/null +++ b/src/packed_simd/api/math/float/recpre.rs.html @@ -0,0 +1,75 @@ +recpre.rs.html -- source
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+//! Implements vertical (lane-wise) floating-point `recpre`.
+
+macro_rules! impl_math_float_recpre {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident | $test_tt:tt) => {
+        impl $id {
+            /// Reciprocal estimate: `~= 1. / self`.
+            ///
+            /// FIXME: The precision of the estimate is currently unspecified.
+            #[inline]
+            pub fn recpre(self) -> Self {
+                $id::splat(1.) / self
+            }
+        }
+
+        test_if!{
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _math_recpre>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn recpre() {
+                        let tol = $id::splat(2.4e-4 as $elem_ty);
+                        let o = $id::splat(1 as $elem_ty);
+                        let error = (o - o.recpre()).abs();
+                        assert!(error.le(tol).all());
+
+                        let t = $id::splat(2 as $elem_ty);
+                        let e = 0.5;
+                        let error = (e - t.recpre()).abs();
+                        assert!(error.le(tol).all());
+                    }
+                }
+            }
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/math/float/rsqrte.rs.html b/src/packed_simd/api/math/float/rsqrte.rs.html new file mode 100644 index 000000000..876231c5b --- /dev/null +++ b/src/packed_simd/api/math/float/rsqrte.rs.html @@ -0,0 +1,83 @@ +rsqrte.rs.html -- source
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+//! Implements vertical (lane-wise) floating-point `rsqrte`.
+
+macro_rules! impl_math_float_rsqrte {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident | $test_tt:tt) => {
+        impl $id {
+            /// Reciprocal square-root estimate: `~= 1. / self.sqrt()`.
+            ///
+            /// FIXME: The precision of the estimate is currently unspecified.
+            #[inline]
+            pub fn rsqrte(self) -> Self {
+                unsafe {
+                    use crate::llvm::simd_fsqrt;
+                    $id::splat(1.) / Simd(simd_fsqrt(self.0))
+                }
+            }
+        }
+
+        test_if!{
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _math_rsqrte>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn rsqrte() {
+                        use crate::$elem_ty::consts::SQRT_2;
+                        let tol = $id::splat(2.4e-4 as $elem_ty);
+                        let o = $id::splat(1 as $elem_ty);
+                        let error = (o - o.rsqrte()).abs();
+                        assert!(error.le(tol).all());
+
+                        let t = $id::splat(2 as $elem_ty);
+                        let e = 1. / SQRT_2;
+                        let error = (e - t.rsqrte()).abs();
+                        assert!(error.le(tol).all());
+                    }
+                }
+            }
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/math/float/sin.rs.html b/src/packed_simd/api/math/float/sin.rs.html new file mode 100644 index 000000000..5a35c7c48 --- /dev/null +++ b/src/packed_simd/api/math/float/sin.rs.html @@ -0,0 +1,103 @@ +sin.rs.html -- source
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+//! Implements vertical (lane-wise) floating-point `sin`.
+
+macro_rules! impl_math_float_sin {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident | $test_tt:tt) => {
+        impl $id {
+            /// Sine.
+            #[inline]
+            pub fn sin(self) -> Self {
+                use crate::codegen::math::float::sin::Sin;
+                Sin::sin(self)
+            }
+
+            /// Sine of `self * PI`.
+            #[inline]
+            pub fn sin_pi(self) -> Self {
+                use crate::codegen::math::float::sin_pi::SinPi;
+                SinPi::sin_pi(self)
+            }
+
+            /// Sine and cosine of `self * PI`.
+            #[inline]
+            pub fn sin_cos_pi(self) -> (Self, Self) {
+                use crate::codegen::math::float::sin_cos_pi::SinCosPi;
+                SinCosPi::sin_cos_pi(self)
+            }
+        }
+
+        test_if!{
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _math_sin>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn sin() {
+                        use crate::$elem_ty::consts::PI;
+                        let z = $id::splat(0 as $elem_ty);
+                        let p = $id::splat(PI as $elem_ty);
+                        let ph = $id::splat(PI as $elem_ty / 2.);
+                        let o_r = $id::splat((PI as $elem_ty / 2.).sin());
+                        let z_r = $id::splat((PI as $elem_ty).sin());
+
+                        assert_eq!(z, z.sin());
+                        assert_eq!(o_r, ph.sin());
+                        assert_eq!(z_r, p.sin());
+                    }
+                }
+            }
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/math/float/sqrt.rs.html b/src/packed_simd/api/math/float/sqrt.rs.html new file mode 100644 index 000000000..a73d0944a --- /dev/null +++ b/src/packed_simd/api/math/float/sqrt.rs.html @@ -0,0 +1,73 @@ +sqrt.rs.html -- source
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+//! Implements vertical (lane-wise) floating-point `sqrt`.
+
+macro_rules! impl_math_float_sqrt {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident | $test_tt:tt) => {
+        impl $id {
+            #[inline]
+            pub fn sqrt(self) -> Self {
+                use crate::codegen::math::float::sqrt::Sqrt;
+                Sqrt::sqrt(self)
+            }
+        }
+
+        test_if!{
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _math_sqrt>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn sqrt() {
+                        use crate::$elem_ty::consts::SQRT_2;
+                        let z = $id::splat(0 as $elem_ty);
+                        let o = $id::splat(1 as $elem_ty);
+                        assert_eq!(z, z.sqrt());
+                        assert_eq!(o, o.sqrt());
+
+                        let t = $id::splat(2 as $elem_ty);
+                        let e = $id::splat(SQRT_2);
+                        assert_eq!(e, t.sqrt());
+
+                    }
+                }
+            }
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/math/float/sqrte.rs.html b/src/packed_simd/api/math/float/sqrte.rs.html new file mode 100644 index 000000000..3cb07eb89 --- /dev/null +++ b/src/packed_simd/api/math/float/sqrte.rs.html @@ -0,0 +1,91 @@ +sqrte.rs.html -- source
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+//! Implements vertical (lane-wise) floating-point `sqrte`.
+
+macro_rules! impl_math_float_sqrte {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident | $test_tt:tt) => {
+        impl $id {
+            /// Square-root estimate.
+            ///
+            /// FIXME: The precision of the estimate is currently unspecified.
+            #[inline]
+            pub fn sqrte(self) -> Self {
+                use crate::codegen::math::float::sqrte::Sqrte;
+                Sqrte::sqrte(self)
+            }
+        }
+
+        test_if!{
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _math_sqrte>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn sqrte() {
+                        use crate::$elem_ty::consts::SQRT_2;
+                        let tol = $id::splat(2.4e-4 as $elem_ty);
+
+                        let z = $id::splat(0 as $elem_ty);
+                        let error = (z - z.sqrte()).abs();
+                        assert!(error.le(tol).all());
+
+                        let o = $id::splat(1 as $elem_ty);
+                        let error = (o - o.sqrte()).abs();
+                        assert!(error.le(tol).all());
+
+                        let t = $id::splat(2 as $elem_ty);
+                        let e = $id::splat(SQRT_2 as $elem_ty);
+                        let error = (e - t.sqrte()).abs();
+
+                        assert!(error.le(tol).all());
+                    }
+                }
+            }
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/math/float/tanh.rs.html b/src/packed_simd/api/math/float/tanh.rs.html new file mode 100644 index 000000000..026e5e029 --- /dev/null +++ b/src/packed_simd/api/math/float/tanh.rs.html @@ -0,0 +1,61 @@ +tanh.rs.html -- source
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+//! Implements vertical (lane-wise) floating-point `tanh`.
+
+macro_rules! impl_math_float_tanh {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident | $test_tt:tt) => {
+        impl $id {
+            /// Tanh.
+            #[inline]
+            pub fn tanh(self) -> Self {
+                use crate::codegen::math::float::tanh::Tanh;
+                Tanh::tanh(self)
+            }
+        }
+
+        test_if!{
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _math_tanh>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn tanh() {
+                        let z = $id::splat(0 as $elem_ty);
+
+                        assert_eq!(z, z.tanh());
+                    }
+                }
+            }
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/minimal.rs.html b/src/packed_simd/api/minimal.rs.html new file mode 100644 index 000000000..f7d2c4c94 --- /dev/null +++ b/src/packed_simd/api/minimal.rs.html @@ -0,0 +1,15 @@ +minimal.rs.html -- source
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+#[macro_use]
+mod iuf;
+#[macro_use]
+mod mask;
+#[macro_use]
+mod ptr;
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/minimal/iuf.rs.html b/src/packed_simd/api/minimal/iuf.rs.html new file mode 100644 index 000000000..32a392a80 --- /dev/null +++ b/src/packed_simd/api/minimal/iuf.rs.html @@ -0,0 +1,337 @@ +iuf.rs.html -- source
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+
+//! Minimal API of signed integer, unsigned integer, and floating-point
+//! vectors.
+
+macro_rules! impl_minimal_iuf {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident | $ielem_ty:ident |
+     $test_tt:tt | $($elem_name:ident),+ | $(#[$doc:meta])*) => {
+
+        $(#[$doc])*
+        pub type $id = Simd<[$elem_ty; $elem_count]>;
+
+        impl sealed::Simd for $id {
+            type Element = $elem_ty;
+            const LANES: usize = $elem_count;
+            type LanesType = [u32; $elem_count];
+        }
+
+        impl $id {
+            /// Creates a new instance with each vector elements initialized
+            /// with the provided values.
+            #[inline]
+            #[allow(clippy::too_many_arguments)]
+            pub const fn new($($elem_name: $elem_ty),*) -> Self {
+                Simd(codegen::$id($($elem_name as $ielem_ty),*))
+            }
+
+            /// Returns the number of vector lanes.
+            #[inline]
+            pub const fn lanes() -> usize {
+                $elem_count
+            }
+
+            /// Constructs a new instance with each element initialized to
+            /// `value`.
+            #[inline]
+            pub const fn splat(value: $elem_ty) -> Self {
+                Simd(codegen::$id($({
+                    #[allow(non_camel_case_types, dead_code)]
+                    struct $elem_name;
+                    value as $ielem_ty
+                }),*))
+            }
+
+            /// Extracts the value at `index`.
+            ///
+            /// # Panics
+            ///
+            /// If `index >= Self::lanes()`.
+            #[inline]
+            pub fn extract(self, index: usize) -> $elem_ty {
+                assert!(index < $elem_count);
+                unsafe { self.extract_unchecked(index) }
+            }
+
+            /// Extracts the value at `index`.
+            ///
+            /// # Precondition
+            ///
+            /// If `index >= Self::lanes()` the behavior is undefined.
+            #[inline]
+            pub unsafe fn extract_unchecked(self, index: usize) -> $elem_ty {
+                use crate::llvm::simd_extract;
+                let e: $ielem_ty = simd_extract(self.0, index as u32);
+                e as $elem_ty
+            }
+
+            /// Returns a new vector where the value at `index` is replaced by `new_value`.
+            ///
+            /// # Panics
+            ///
+            /// If `index >= Self::lanes()`.
+            #[inline]
+            #[must_use = "replace does not modify the original value - \
+                          it returns a new vector with the value at `index` \
+                          replaced by `new_value`d"
+            ]
+            pub fn replace(self, index: usize, new_value: $elem_ty) -> Self {
+                assert!(index < $elem_count);
+                unsafe { self.replace_unchecked(index, new_value) }
+            }
+
+            /// Returns a new vector where the value at `index` is replaced by `new_value`.
+            ///
+            /// # Precondition
+            ///
+            /// If `index >= Self::lanes()` the behavior is undefined.
+            #[inline]
+            #[must_use = "replace_unchecked does not modify the original value - \
+                          it returns a new vector with the value at `index` \
+                          replaced by `new_value`d"
+            ]
+            pub unsafe fn replace_unchecked(
+                self,
+                index: usize,
+                new_value: $elem_ty,
+            ) -> Self {
+                use crate::llvm::simd_insert;
+                Simd(simd_insert(self.0, index as u32, new_value as $ielem_ty))
+            }
+        }
+
+        test_if!{
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _minimal>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn minimal() {
+                        // lanes:
+                        assert_eq!($elem_count, $id::lanes());
+
+                        // splat and extract / extract_unchecked:
+                        const VAL: $elem_ty = 7 as $elem_ty;
+                        const VEC: $id = $id::splat(VAL);
+                        for i in 0..$id::lanes() {
+                            assert_eq!(VAL, VEC.extract(i));
+                            assert_eq!(
+                                VAL, unsafe { VEC.extract_unchecked(i) }
+                            );
+                        }
+
+                        // replace / replace_unchecked
+                        let new_vec = VEC.replace(0, 42 as $elem_ty);
+                        for i in 0..$id::lanes() {
+                            if i == 0 {
+                                assert_eq!(42 as $elem_ty, new_vec.extract(i));
+                            } else {
+                                assert_eq!(VAL, new_vec.extract(i));
+                            }
+                        }
+                        let new_vec = unsafe {
+                            VEC.replace_unchecked(0, 42 as $elem_ty)
+                        };
+                        for i in 0..$id::lanes() {
+                            if i == 0 {
+                                assert_eq!(42 as $elem_ty, new_vec.extract(i));
+                            } else {
+                                assert_eq!(VAL, new_vec.extract(i));
+                            }
+                        }
+                    }
+
+                    // FIXME: wasm-bindgen-test does not support #[should_panic]
+                    // #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    #[cfg(not(target_arch = "wasm32"))]
+                    #[test]
+                    #[should_panic]
+                    fn extract_panic_oob() {
+                        const VAL: $elem_ty = 7 as $elem_ty;
+                        const VEC: $id = $id::splat(VAL);
+                        let _ = VEC.extract($id::lanes());
+                    }
+                    // FIXME: wasm-bindgen-test does not support #[should_panic]
+                    // #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    #[cfg(not(target_arch = "wasm32"))]
+                    #[test]
+                    #[should_panic]
+                    fn replace_panic_oob() {
+                        const VAL: $elem_ty = 7 as $elem_ty;
+                        const VEC: $id = $id::splat(VAL);
+                        let _ = VEC.replace($id::lanes(), 42 as $elem_ty);
+                    }
+                }
+            }
+        }
+    }
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/minimal/mask.rs.html b/src/packed_simd/api/minimal/mask.rs.html new file mode 100644 index 000000000..4f14c492f --- /dev/null +++ b/src/packed_simd/api/minimal/mask.rs.html @@ -0,0 +1,351 @@ +mask.rs.html -- source
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+
+//! Minimal API of mask vectors.
+
+macro_rules! impl_minimal_mask {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident | $ielem_ty:ident
+    | $test_tt:tt | $($elem_name:ident),+ | $(#[$doc:meta])*) => {
+        $(#[$doc])*
+        pub type $id = Simd<[$elem_ty; $elem_count]>;
+
+        impl sealed::Simd for $id {
+            type Element = $elem_ty;
+            const LANES: usize = $elem_count;
+            type LanesType = [u32; $elem_count];
+        }
+
+        impl $id {
+            /// Creates a new instance with each vector elements initialized
+            /// with the provided values.
+            #[inline]
+            #[allow(clippy::too_many_arguments)]
+            pub const fn new($($elem_name: bool),*) -> Self {
+                Simd(codegen::$id($(Self::bool_to_internal($elem_name)),*))
+            }
+
+            /// Converts a boolean type into the type of the vector lanes.
+            #[inline]
+            #[allow(clippy::indexing_slicing)]
+            const fn bool_to_internal(x: bool) -> $ielem_ty {
+                [0 as $ielem_ty, !(0 as $ielem_ty)][x as usize]
+            }
+
+            /// Returns the number of vector lanes.
+            #[inline]
+            pub const fn lanes() -> usize {
+                $elem_count
+            }
+
+            /// Constructs a new instance with each element initialized to
+            /// `value`.
+            #[inline]
+            pub const fn splat(value: bool) -> Self {
+                Simd(codegen::$id($({
+                    #[allow(non_camel_case_types, dead_code)]
+                    struct $elem_name;
+                    Self::bool_to_internal(value)
+                }),*))
+            }
+
+            /// Extracts the value at `index`.
+            ///
+            /// # Panics
+            ///
+            /// If `index >= Self::lanes()`.
+            #[inline]
+            pub fn extract(self, index: usize) -> bool {
+                assert!(index < $elem_count);
+                unsafe { self.extract_unchecked(index) }
+            }
+
+            /// Extracts the value at `index`.
+            ///
+            /// If `index >= Self::lanes()` the behavior is undefined.
+            #[inline]
+            pub unsafe fn extract_unchecked(self, index: usize) -> bool {
+                use crate::llvm::simd_extract;
+                let x: $ielem_ty = simd_extract(self.0, index as u32);
+                x != 0
+            }
+
+            /// Returns a new vector where the value at `index` is replaced by
+            /// `new_value`.
+            ///
+            /// # Panics
+            ///
+            /// If `index >= Self::lanes()`.
+            #[inline]
+            #[must_use = "replace does not modify the original value - \
+                          it returns a new vector with the value at `index` \
+                          replaced by `new_value`d"
+            ]
+            pub fn replace(self, index: usize, new_value: bool) -> Self {
+                assert!(index < $elem_count);
+                unsafe { self.replace_unchecked(index, new_value) }
+            }
+
+            /// Returns a new vector where the value at `index` is replaced by
+            /// `new_value`.
+            ///
+            /// # Panics
+            ///
+            /// If `index >= Self::lanes()`.
+            #[inline]
+            #[must_use = "replace_unchecked does not modify the original value - \
+                          it returns a new vector with the value at `index` \
+                          replaced by `new_value`d"
+            ]
+            pub unsafe fn replace_unchecked(
+                self,
+                index: usize,
+                new_value: bool,
+            ) -> Self {
+                use crate::llvm::simd_insert;
+                Simd(simd_insert(self.0, index as u32,
+                                 Self::bool_to_internal(new_value)))
+            }
+        }
+
+        test_if!{
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _minimal>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn minimal() {
+                        // TODO: test new
+
+                        // lanes:
+                        assert_eq!($elem_count, $id::lanes());
+
+                        // splat and extract / extract_unchecked:
+                        let vec = $id::splat(true);
+                        for i in 0..$id::lanes() {
+                            assert_eq!(true, vec.extract(i));
+                            assert_eq!(true,
+                                       unsafe { vec.extract_unchecked(i) }
+                            );
+                        }
+
+                        // replace / replace_unchecked
+                        let new_vec = vec.replace(0, false);
+                        for i in 0..$id::lanes() {
+                            if i == 0 {
+                                assert_eq!(false, new_vec.extract(i));
+                            } else {
+                                assert_eq!(true, new_vec.extract(i));
+                            }
+                        }
+                        let new_vec = unsafe {
+                            vec.replace_unchecked(0, false)
+                        };
+                        for i in 0..$id::lanes() {
+                            if i == 0 {
+                                assert_eq!(false, new_vec.extract(i));
+                            } else {
+                                assert_eq!(true, new_vec.extract(i));
+                            }
+                        }
+                    }
+
+                    // FIXME: wasm-bindgen-test does not support #[should_panic]
+                    // #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    // #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    #[cfg(not(target_arch = "wasm32"))]
+                    #[test]
+                    #[should_panic]
+                    fn extract_panic_oob() {
+                        let vec = $id::splat(false);
+                        let _ = vec.extract($id::lanes());
+                    }
+                    // FIXME: wasm-bindgen-test does not support #[should_panic]
+                    // #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    // #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    #[cfg(not(target_arch = "wasm32"))]
+                    #[test]
+                    #[should_panic]
+                    fn replace_panic_oob() {
+                        let vec = $id::splat(false);
+                        let _ = vec.replace($id::lanes(), true);
+                    }
+                }
+            }
+        }
+    }
+}
+
+
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+
+//! Minimal API of pointer vectors.
+
+macro_rules! impl_minimal_p {
+    ([$elem_ty:ty; $elem_count:expr]: $id:ident, $mask_ty:ident,
+     $usize_ty:ident, $isize_ty:ident | $ref:ident | $test_tt:tt
+     | $($elem_name:ident),+ | ($true:expr, $false:expr) |
+     $(#[$doc:meta])*) => {
+
+        $(#[$doc])*
+        pub type $id<T> = Simd<[$elem_ty; $elem_count]>;
+
+        impl<T> sealed::Simd for $id<T> {
+            type Element = $elem_ty;
+            const LANES: usize = $elem_count;
+            type LanesType = [u32; $elem_count];
+        }
+
+        impl<T> $id<T> {
+            /// Creates a new instance with each vector elements initialized
+            /// with the provided values.
+            #[inline]
+            #[allow(clippy::too_many_arguments)]
+            pub const fn new($($elem_name: $elem_ty),*) -> Self {
+                Simd(codegen::$id($($elem_name),*))
+            }
+
+            /// Returns the number of vector lanes.
+            #[inline]
+            pub const fn lanes() -> usize {
+                $elem_count
+            }
+
+            /// Constructs a new instance with each element initialized to
+            /// `value`.
+            #[inline]
+            pub const fn splat(value: $elem_ty) -> Self {
+                Simd(codegen::$id($({
+                    #[allow(non_camel_case_types, dead_code)]
+                    struct $elem_name;
+                    value
+                }),*))
+            }
+
+            /// Constructs a new instance with each element initialized to
+            /// `null`.
+            #[inline]
+            pub const fn null() -> Self {
+                Self::splat(crate::ptr::null_mut() as $elem_ty)
+            }
+
+            /// Returns a mask that selects those lanes that contain `null`
+            /// pointers.
+            #[inline]
+            pub fn is_null(self) -> $mask_ty {
+                self.eq(Self::null())
+            }
+
+            /// Extracts the value at `index`.
+            ///
+            /// # Panics
+            ///
+            /// If `index >= Self::lanes()`.
+            #[inline]
+            pub fn extract(self, index: usize) -> $elem_ty {
+                assert!(index < $elem_count);
+                unsafe { self.extract_unchecked(index) }
+            }
+
+            /// Extracts the value at `index`.
+            ///
+            /// # Precondition
+            ///
+            /// If `index >= Self::lanes()` the behavior is undefined.
+            #[inline]
+            pub unsafe fn extract_unchecked(self, index: usize) -> $elem_ty {
+                use crate::llvm::simd_extract;
+                simd_extract(self.0, index as u32)
+            }
+
+            /// Returns a new vector where the value at `index` is replaced by
+            /// `new_value`.
+            ///
+            /// # Panics
+            ///
+            /// If `index >= Self::lanes()`.
+            #[inline]
+            #[must_use = "replace does not modify the original value - \
+                          it returns a new vector with the value at `index` \
+                          replaced by `new_value`d"
+            ]
+            #[allow(clippy::not_unsafe_ptr_arg_deref)]
+            pub fn replace(self, index: usize, new_value: $elem_ty) -> Self {
+                assert!(index < $elem_count);
+                unsafe { self.replace_unchecked(index, new_value) }
+            }
+
+            /// Returns a new vector where the value at `index` is replaced by `new_value`.
+            ///
+            /// # Precondition
+            ///
+            /// If `index >= Self::lanes()` the behavior is undefined.
+            #[inline]
+            #[must_use = "replace_unchecked does not modify the original value - \
+                          it returns a new vector with the value at `index` \
+                          replaced by `new_value`d"
+            ]
+            pub unsafe fn replace_unchecked(
+                self,
+                index: usize,
+                new_value: $elem_ty,
+            ) -> Self {
+                use crate::llvm::simd_insert;
+                Simd(simd_insert(self.0, index as u32, new_value))
+            }
+        }
+
+
+        test_if!{
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _minimal>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn minimal() {
+                        // lanes:
+                        assert_eq!($elem_count, $id::<i32>::lanes());
+
+                        // splat and extract / extract_unchecked:
+                        let VAL7: <$id<i32> as sealed::Simd>::Element
+                            = $ref!(7);
+                        let VAL42: <$id<i32> as sealed::Simd>::Element
+                            = $ref!(42);
+                        let VEC: $id<i32> = $id::splat(VAL7);
+                        for i in 0..$id::<i32>::lanes() {
+                            assert_eq!(VAL7, VEC.extract(i));
+                            assert_eq!(
+                                VAL7, unsafe { VEC.extract_unchecked(i) }
+                            );
+                        }
+
+                        // replace / replace_unchecked
+                        let new_vec = VEC.replace(0, VAL42);
+                        for i in 0..$id::<i32>::lanes() {
+                            if i == 0 {
+                                assert_eq!(VAL42, new_vec.extract(i));
+                            } else {
+                                assert_eq!(VAL7, new_vec.extract(i));
+                            }
+                        }
+                        let new_vec = unsafe {
+                            VEC.replace_unchecked(0, VAL42)
+                        };
+                        for i in 0..$id::<i32>::lanes() {
+                            if i == 0 {
+                                assert_eq!(VAL42, new_vec.extract(i));
+                            } else {
+                                assert_eq!(VAL7, new_vec.extract(i));
+                            }
+                        }
+
+                        let mut n = $id::<i32>::null();
+                        assert_eq!(
+                            n,
+                            $id::<i32>::splat(unsafe { crate::mem::zeroed() })
+                        );
+                        assert!(n.is_null().all());
+                        n = n.replace(
+                            0, unsafe { crate::mem::transmute(1_isize) }
+                        );
+                        assert!(!n.is_null().all());
+                        if $id::<i32>::lanes() > 1 {
+                            assert!(n.is_null().any());
+                        } else {
+                            assert!(!n.is_null().any());
+                        }
+                    }
+
+                    // FIXME: wasm-bindgen-test does not support #[should_panic]
+                    // #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    // #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    #[cfg(not(target_arch = "wasm32"))]
+                    #[test]
+                    #[should_panic]
+                    fn extract_panic_oob() {
+                        let VAL: <$id<i32> as sealed::Simd>::Element
+                            = $ref!(7);
+                        let VEC: $id<i32> = $id::splat(VAL);
+                        let _ = VEC.extract($id::<i32>::lanes());
+                    }
+
+                    // FIXME: wasm-bindgen-test does not support #[should_panic]
+                    // #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    // #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    #[cfg(not(target_arch = "wasm32"))]
+                    #[test]
+                    #[should_panic]
+                    fn replace_panic_oob() {
+                        let VAL: <$id<i32> as sealed::Simd>::Element
+                            = $ref!(7);
+                        let VAL42: <$id<i32> as sealed::Simd>::Element
+                            = $ref!(42);
+                        let VEC: $id<i32> = $id::splat(VAL);
+                        let _ = VEC.replace($id::<i32>::lanes(), VAL42);
+                    }
+                }
+            }
+        }
+
+        impl<T> crate::fmt::Debug for $id<T> {
+            #[allow(clippy::missing_inline_in_public_items)]
+            fn fmt(&self, f: &mut crate::fmt::Formatter<'_>)
+                   -> crate::fmt::Result {
+                write!(
+                    f,
+                    "{}<{}>(",
+                    stringify!($id),
+                    unsafe { crate::intrinsics::type_name::<T>() }
+                )?;
+                for i in 0..$elem_count {
+                    if i > 0 {
+                        write!(f, ", ")?;
+                    }
+                    self.extract(i).fmt(f)?;
+                }
+                write!(f, ")")
+            }
+        }
+
+         test_if!{
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _fmt_debug>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn debug() {
+                        use arrayvec::{ArrayString,ArrayVec};
+                        type TinyString = ArrayString<[u8; 512]>;
+
+                        use crate::fmt::Write;
+                        let v = $id::<i32>::default();
+                        let mut s = TinyString::new();
+                        write!(&mut s, "{:?}", v).unwrap();
+
+                        let mut beg = TinyString::new();
+                        write!(&mut beg, "{}<i32>(", stringify!($id)).unwrap();
+                        assert!(
+                            s.starts_with(beg.as_str()),
+                            "s = {} (should start with = {})", s, beg
+                        );
+                        assert!(s.ends_with(")"));
+                        let s: ArrayVec<[TinyString; 64]>
+                            = s.replace(beg.as_str(), "")
+                            .replace(")", "").split(",")
+                            .map(|v| TinyString::from(v.trim()).unwrap())
+                            .collect();
+                        assert_eq!(s.len(), $id::<i32>::lanes());
+                        for (index, ss) in s.into_iter().enumerate() {
+                            let mut e = TinyString::new();
+                            write!(&mut e, "{:?}", v.extract(index)).unwrap();
+                            assert_eq!(ss, e);
+                        }
+                    }
+                }
+            }
+         }
+
+        impl<T> Default for $id<T> {
+            #[inline]
+            fn default() -> Self {
+                // FIXME: ptrs do not implement default
+                Self::null()
+            }
+        }
+
+        test_if!{
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _default>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn default() {
+                        let a = $id::<i32>::default();
+                        for i in 0..$id::<i32>::lanes() {
+                            assert_eq!(
+                                a.extract(i), unsafe { crate::mem::zeroed() }
+                            );
+                        }
+                    }
+                }
+            }
+        }
+
+        impl<T> $id<T> {
+            /// Lane-wise equality comparison.
+            #[inline]
+            pub fn eq(self, other: Self) -> $mask_ty {
+                unsafe {
+                    use crate::llvm::simd_eq;
+                    let a: $usize_ty = crate::mem::transmute(self);
+                    let b: $usize_ty = crate::mem::transmute(other);
+                    Simd(simd_eq(a.0, b.0))
+                }
+            }
+
+            /// Lane-wise inequality comparison.
+            #[inline]
+            pub fn ne(self, other: Self) -> $mask_ty {
+                unsafe {
+                    use crate::llvm::simd_ne;
+                    let a: $usize_ty = crate::mem::transmute(self);
+                    let b: $usize_ty = crate::mem::transmute(other);
+                    Simd(simd_ne(a.0, b.0))
+                }
+            }
+
+            /// Lane-wise less-than comparison.
+            #[inline]
+            pub fn lt(self, other: Self) -> $mask_ty {
+                unsafe {
+                    use crate::llvm::simd_lt;
+                    let a: $usize_ty = crate::mem::transmute(self);
+                    let b: $usize_ty = crate::mem::transmute(other);
+                    Simd(simd_lt(a.0, b.0))
+                }
+            }
+
+            /// Lane-wise less-than-or-equals comparison.
+            #[inline]
+            pub fn le(self, other: Self) -> $mask_ty {
+                unsafe {
+                    use crate::llvm::simd_le;
+                    let a: $usize_ty = crate::mem::transmute(self);
+                    let b: $usize_ty = crate::mem::transmute(other);
+                    Simd(simd_le(a.0, b.0))
+                }
+            }
+
+            /// Lane-wise greater-than comparison.
+            #[inline]
+            pub fn gt(self, other: Self) -> $mask_ty {
+                unsafe {
+                    use crate::llvm::simd_gt;
+                    let a: $usize_ty = crate::mem::transmute(self);
+                    let b: $usize_ty = crate::mem::transmute(other);
+                    Simd(simd_gt(a.0, b.0))
+                }
+            }
+
+            /// Lane-wise greater-than-or-equals comparison.
+            #[inline]
+            pub fn ge(self, other: Self) -> $mask_ty {
+                unsafe {
+                    use crate::llvm::simd_ge;
+                    let a: $usize_ty = crate::mem::transmute(self);
+                    let b: $usize_ty = crate::mem::transmute(other);
+                    Simd(simd_ge(a.0, b.0))
+                }
+            }
+        }
+
+        test_if!{
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _cmp_vertical>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn cmp() {
+                        let a = $id::<i32>::null();
+                        let b = $id::<i32>::splat(unsafe {
+                            crate::mem::transmute(1_isize)
+                        });
+
+                        let r = a.lt(b);
+                        let e = $mask_ty::splat(true);
+                        assert!(r == e);
+                        let r = a.le(b);
+                        assert!(r == e);
+
+                        let e = $mask_ty::splat(false);
+                        let r = a.gt(b);
+                        assert!(r == e);
+                        let r = a.ge(b);
+                        assert!(r == e);
+                        let r = a.eq(b);
+                        assert!(r == e);
+
+                        let mut a = a;
+                        let mut b = b;
+                        let mut e = e;
+                        for i in 0..$id::<i32>::lanes() {
+                            if i % 2 == 0 {
+                                a = a.replace(
+                                    i,
+                                    unsafe { crate::mem::transmute(0_isize) }
+                                );
+                                b = b.replace(
+                                    i,
+                                    unsafe { crate::mem::transmute(1_isize) }
+                                );
+                                e = e.replace(i, true);
+                            } else {
+                                a = a.replace(
+                                    i,
+                                    unsafe { crate::mem::transmute(1_isize) }
+                                );
+                                b = b.replace(
+                                    i,
+                                    unsafe { crate::mem::transmute(0_isize) }
+                                );
+                                e = e.replace(i, false);
+                            }
+                        }
+                        let r = a.lt(b);
+                        assert!(r == e);
+                    }
+                }
+            }
+        }
+
+        #[allow(clippy::partialeq_ne_impl)]
+        impl<T> crate::cmp::PartialEq<$id<T>> for $id<T> {
+            #[inline]
+            fn eq(&self, other: &Self) -> bool {
+                $id::<T>::eq(*self, *other).all()
+            }
+            #[inline]
+            fn ne(&self, other: &Self) -> bool {
+                $id::<T>::ne(*self, *other).any()
+            }
+        }
+
+        // FIXME: https://github.com/rust-lang-nursery/rust-clippy/issues/2892
+        #[allow(clippy::partialeq_ne_impl)]
+        impl<T> crate::cmp::PartialEq<LexicographicallyOrdered<$id<T>>>
+            for LexicographicallyOrdered<$id<T>>
+        {
+            #[inline]
+            fn eq(&self, other: &Self) -> bool {
+                self.0 == other.0
+            }
+            #[inline]
+            fn ne(&self, other: &Self) -> bool {
+                self.0 != other.0
+            }
+        }
+
+        test_if!{
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _cmp_PartialEq>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn partial_eq() {
+                        let a = $id::<i32>::null();
+                        let b = $id::<i32>::splat(unsafe {
+                            crate::mem::transmute(1_isize)
+                        });
+
+                        assert!(a != b);
+                        assert!(!(a == b));
+                        assert!(a == a);
+                        assert!(!(a != a));
+
+                        if $id::<i32>::lanes() > 1 {
+                            let a = $id::<i32>::null().replace(0, unsafe {
+                                crate::mem::transmute(1_isize)
+                            });
+                            let b = $id::<i32>::splat(unsafe {
+                                crate::mem::transmute(1_isize)
+                            });
+
+                            assert!(a != b);
+                            assert!(!(a == b));
+                            assert!(a == a);
+                            assert!(!(a != a));
+                        }
+                    }
+                }
+            }
+        }
+
+        impl<T> crate::cmp::Eq for $id<T> {}
+        impl<T> crate::cmp::Eq for LexicographicallyOrdered<$id<T>> {}
+
+        test_if!{
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _cmp_eq>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn eq() {
+                        fn foo<E: crate::cmp::Eq>(_: E) {}
+                        let a = $id::<i32>::null();
+                        foo(a);
+                    }
+                }
+            }
+        }
+
+        impl<T> From<[$elem_ty; $elem_count]> for $id<T> {
+            #[inline]
+            fn from(array: [$elem_ty; $elem_count]) -> Self {
+                unsafe {
+                    // FIXME: unnecessary zeroing; better than UB.
+                    let mut u: Self = crate::mem::zeroed();
+                    crate::ptr::copy_nonoverlapping(
+                        &array as *const [$elem_ty; $elem_count] as *const u8,
+                        &mut u as *mut Self as *mut u8,
+                        crate::mem::size_of::<Self>()
+                    );
+                    u
+                }
+            }
+        }
+        impl<T> Into<[$elem_ty; $elem_count]> for $id<T> {
+            #[inline]
+            fn into(self) -> [$elem_ty; $elem_count] {
+                unsafe {
+                    // FIXME: unnecessary zeroing; better than UB.
+                    let mut u: [$elem_ty; $elem_count] = crate::mem::zeroed();
+                    crate::ptr::copy_nonoverlapping(
+                        &self as *const $id<T> as *const u8,
+                        &mut u as *mut [$elem_ty; $elem_count] as *mut u8,
+                        crate::mem::size_of::<Self>()
+                    );
+                    u
+                }
+            }
+        }
+
+        test_if!{
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _from>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn array() {
+                        let values = [1_i32; $elem_count];
+
+                        let mut vec: $id<i32> = Default::default();
+                        let mut array = [
+                            $id::<i32>::null().extract(0); $elem_count
+                        ];
+
+                        for i in 0..$elem_count {
+                            let ptr = unsafe {
+                                crate::mem::transmute(
+                                    &values[i] as *const i32
+                                )
+                            };
+                            vec = vec.replace(i, ptr);
+                            array[i] = ptr;
+                        }
+
+                        // FIXME: there is no impl of From<$id<T>> for [$elem_ty; N]
+                        // let a0 = From::from(vec);
+                        // assert_eq!(a0, array);
+                        #[allow(unused_assignments)]
+                        let mut a1 = array;
+                        a1 = vec.into();
+                        assert_eq!(a1, array);
+
+                        let v0: $id<i32> = From::from(array);
+                        assert_eq!(v0, vec);
+                        let v1: $id<i32> = array.into();
+                        assert_eq!(v1, vec);
+                    }
+                }
+            }
+        }
+
+        impl<T> $id<T> {
+            /// Instantiates a new vector with the values of the `slice`.
+            ///
+            /// # Panics
+            ///
+            /// If `slice.len() < Self::lanes()` or `&slice[0]` is not aligned
+            /// to an `align_of::<Self>()` boundary.
+            #[inline]
+            pub fn from_slice_aligned(slice: &[$elem_ty]) -> Self {
+                unsafe {
+                    assert!(slice.len() >= $elem_count);
+                    let target_ptr = slice.get_unchecked(0) as *const $elem_ty;
+                    assert!(
+                        target_ptr.align_offset(crate::mem::align_of::<Self>())
+                            == 0
+                    );
+                    Self::from_slice_aligned_unchecked(slice)
+                }
+            }
+
+            /// Instantiates a new vector with the values of the `slice`.
+            ///
+            /// # Panics
+            ///
+            /// If `slice.len() < Self::lanes()`.
+            #[inline]
+            pub fn from_slice_unaligned(slice: &[$elem_ty]) -> Self {
+                unsafe {
+                    assert!(slice.len() >= $elem_count);
+                    Self::from_slice_unaligned_unchecked(slice)
+                }
+            }
+
+            /// Instantiates a new vector with the values of the `slice`.
+            ///
+            /// # Precondition
+            ///
+            /// If `slice.len() < Self::lanes()` or `&slice[0]` is not aligned
+            /// to an `align_of::<Self>()` boundary, the behavior is undefined.
+            #[inline]
+            pub unsafe fn from_slice_aligned_unchecked(slice: &[$elem_ty])
+                                                       -> Self {
+                #[allow(clippy::cast_ptr_alignment)]
+                *(slice.get_unchecked(0) as *const $elem_ty as *const Self)
+            }
+
+            /// Instantiates a new vector with the values of the `slice`.
+            ///
+            /// # Precondition
+            ///
+            /// If `slice.len() < Self::lanes()` the behavior is undefined.
+            #[inline]
+            pub unsafe fn from_slice_unaligned_unchecked(
+                slice: &[$elem_ty],
+            ) -> Self {
+                use crate::mem::size_of;
+                let target_ptr =
+                    slice.get_unchecked(0) as *const $elem_ty as *const u8;
+                let mut x = Self::splat(crate::ptr::null_mut() as $elem_ty);
+                let self_ptr = &mut x as *mut Self as *mut u8;
+                crate::ptr::copy_nonoverlapping(
+                    target_ptr,
+                    self_ptr,
+                    size_of::<Self>(),
+                );
+                x
+            }
+        }
+
+        test_if!{
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _slice_from_slice>] {
+                    use super::*;
+                    use crate::iter::Iterator;
+
+                    #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn from_slice_unaligned() {
+                        let (null, non_null) = ptr_vals!($id<i32>);
+
+                        let mut unaligned = [
+                            non_null; $id::<i32>::lanes() + 1
+                        ];
+                        unaligned[0] = null;
+                        let vec = $id::<i32>::from_slice_unaligned(
+                            &unaligned[1..]
+                        );
+                        for (index, &b) in unaligned.iter().enumerate() {
+                            if index == 0 {
+                                assert_eq!(b, null);
+                            } else {
+                                assert_eq!(b, non_null);
+                                assert_eq!(b, vec.extract(index - 1));
+                            }
+                        }
+                    }
+
+                    // FIXME: wasm-bindgen-test does not support #[should_panic]
+                    // #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    // #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    #[cfg(not(target_arch = "wasm32"))]
+                    #[test]
+                    #[should_panic]
+                    fn from_slice_unaligned_fail() {
+                        let (_null, non_null) = ptr_vals!($id<i32>);
+                        let unaligned = [non_null; $id::<i32>::lanes() + 1];
+                        // the slice is not large enough => panic
+                        let _vec = $id::<i32>::from_slice_unaligned(
+                            &unaligned[2..]
+                        );
+                    }
+
+                    union A {
+                        data: [<$id<i32> as sealed::Simd>::Element;
+                               2 * $id::<i32>::lanes()],
+                        _vec: $id<i32>,
+                    }
+
+                    #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn from_slice_aligned() {
+                        let (null, non_null) = ptr_vals!($id<i32>);
+                        let mut aligned = A {
+                            data: [null; 2 * $id::<i32>::lanes()],
+                        };
+                        for i in
+                            $id::<i32>::lanes()..(2 * $id::<i32>::lanes()) {
+                            unsafe {
+                                aligned.data[i] = non_null;
+                            }
+                        }
+
+                        let vec = unsafe {
+                            $id::<i32>::from_slice_aligned(
+                                &aligned.data[$id::<i32>::lanes()..]
+                            )
+                        };
+                        for (index, &b) in unsafe {
+                            aligned.data.iter().enumerate()
+                        } {
+                            if index < $id::<i32>::lanes() {
+                                assert_eq!(b, null);
+                            } else {
+                                assert_eq!(b, non_null);
+                                assert_eq!(
+                                    b, vec.extract(index - $id::<i32>::lanes())
+                                );
+                            }
+                        }
+                    }
+
+                    // FIXME: wasm-bindgen-test does not support #[should_panic]
+                    // #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    // #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    #[cfg(not(target_arch = "wasm32"))]
+                    #[test]
+                    #[should_panic]
+                    fn from_slice_aligned_fail_lanes() {
+                        let (_null, non_null) = ptr_vals!($id<i32>);
+                        let aligned = A {
+                            data: [non_null; 2 * $id::<i32>::lanes()],
+                        };
+                        // the slice is not large enough => panic
+                        let _vec = unsafe {
+                            $id::<i32>::from_slice_aligned(
+                                &aligned.data[2 * $id::<i32>::lanes()..]
+                            )
+                        };
+                    }
+
+                    // FIXME: wasm-bindgen-test does not support #[should_panic]
+                    // #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    // #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    #[cfg(not(target_arch = "wasm32"))]
+                    #[test]
+                    #[should_panic]
+                    fn from_slice_aligned_fail_align() {
+                        unsafe {
+                            let (null, _non_null) = ptr_vals!($id<i32>);
+                            let aligned = A {
+                                data: [null; 2 * $id::<i32>::lanes()],
+                            };
+
+                            // get a pointer to the front of data
+                            let ptr = aligned.data.as_ptr();
+                            // offset pointer by one element
+                            let ptr = ptr.wrapping_add(1);
+
+                            if ptr.align_offset(
+                                crate::mem::align_of::<$id<i32>>()
+                            ) == 0 {
+                                // the pointer is properly aligned, so
+                                // from_slice_aligned won't fail here (e.g. this
+                                // can happen for i128x1). So we panic to make
+                                // the "should_fail" test pass:
+                                panic!("ok");
+                            }
+
+                            // create a slice - this is safe, because the
+                            // elements of the slice exist, are properly
+                            // initialized, and properly aligned:
+                            let s = slice::from_raw_parts(
+                                ptr, $id::<i32>::lanes()
+                            );
+                            // this should always panic because the slice
+                            // alignment does not match the alignment
+                            // requirements for the vector type:
+                            let _vec = $id::<i32>::from_slice_aligned(s);
+                        }
+                    }
+                }
+            }
+        }
+
+        impl<T> $id<T> {
+            /// Writes the values of the vector to the `slice`.
+            ///
+            /// # Panics
+            ///
+            /// If `slice.len() < Self::lanes()` or `&slice[0]` is not
+            /// aligned to an `align_of::<Self>()` boundary.
+            #[inline]
+            pub fn write_to_slice_aligned(self, slice: &mut [$elem_ty]) {
+                unsafe {
+                    assert!(slice.len() >= $elem_count);
+                    let target_ptr =
+                        slice.get_unchecked_mut(0) as *mut $elem_ty;
+                    assert!(
+                        target_ptr.align_offset(crate::mem::align_of::<Self>())
+                            == 0
+                    );
+                    self.write_to_slice_aligned_unchecked(slice);
+                }
+            }
+
+            /// Writes the values of the vector to the `slice`.
+            ///
+            /// # Panics
+            ///
+            /// If `slice.len() < Self::lanes()`.
+            #[inline]
+            pub fn write_to_slice_unaligned(self, slice: &mut [$elem_ty]) {
+                unsafe {
+                    assert!(slice.len() >= $elem_count);
+                    self.write_to_slice_unaligned_unchecked(slice);
+                }
+            }
+
+            /// Writes the values of the vector to the `slice`.
+            ///
+            /// # Precondition
+            ///
+            /// If `slice.len() < Self::lanes()` or `&slice[0]` is not
+            /// aligned to an `align_of::<Self>()` boundary, the behavior is
+            /// undefined.
+            #[inline]
+            pub unsafe fn write_to_slice_aligned_unchecked(
+                self, slice: &mut [$elem_ty],
+            ) {
+                #[allow(clippy::cast_ptr_alignment)]
+                *(slice.get_unchecked_mut(0) as *mut $elem_ty as *mut Self) =
+                    self;
+            }
+
+            /// Writes the values of the vector to the `slice`.
+            ///
+            /// # Precondition
+            ///
+            /// If `slice.len() < Self::lanes()` the behavior is undefined.
+            #[inline]
+            pub unsafe fn write_to_slice_unaligned_unchecked(
+                self, slice: &mut [$elem_ty],
+            ) {
+                let target_ptr =
+                    slice.get_unchecked_mut(0) as *mut $elem_ty as *mut u8;
+                let self_ptr = &self as *const Self as *const u8;
+                crate::ptr::copy_nonoverlapping(
+                    self_ptr,
+                    target_ptr,
+                    crate::mem::size_of::<Self>(),
+                );
+            }
+        }
+
+        test_if!{
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _slice_write_to_slice>] {
+                    use super::*;
+                    use crate::iter::Iterator;
+
+                    #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn write_to_slice_unaligned() {
+                        let (null, non_null) = ptr_vals!($id<i32>);
+                        let mut unaligned = [null; $id::<i32>::lanes() + 1];
+                        let vec = $id::<i32>::splat(non_null);
+                        vec.write_to_slice_unaligned(&mut unaligned[1..]);
+                        for (index, &b) in unaligned.iter().enumerate() {
+                            if index == 0 {
+                                assert_eq!(b, null);
+                            } else {
+                                assert_eq!(b, non_null);
+                                assert_eq!(b, vec.extract(index - 1));
+                            }
+                        }
+                    }
+
+                    // FIXME: wasm-bindgen-test does not support #[should_panic]
+                    // #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    // #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    #[cfg(not(target_arch = "wasm32"))]
+                    #[test]
+                    #[should_panic]
+                    fn write_to_slice_unaligned_fail() {
+                        let (null, non_null) = ptr_vals!($id<i32>);
+                        let mut unaligned = [null; $id::<i32>::lanes() + 1];
+                        let vec = $id::<i32>::splat(non_null);
+                        // the slice is not large enough => panic
+                        vec.write_to_slice_unaligned(&mut unaligned[2..]);
+                    }
+
+                    union A {
+                        data: [<$id<i32> as sealed::Simd>::Element;
+                               2 * $id::<i32>::lanes()],
+                        _vec: $id<i32>,
+                    }
+
+                    #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn write_to_slice_aligned() {
+                        let (null, non_null) = ptr_vals!($id<i32>);
+                        let mut aligned = A {
+                            data: [null; 2 * $id::<i32>::lanes()],
+                        };
+                        let vec = $id::<i32>::splat(non_null);
+                        unsafe {
+                            vec.write_to_slice_aligned(
+                                &mut aligned.data[$id::<i32>::lanes()..]
+                            )
+                        };
+                        for (index, &b) in
+                            unsafe { aligned.data.iter().enumerate() } {
+                            if index < $id::<i32>::lanes() {
+                                assert_eq!(b, null);
+                            } else {
+                                assert_eq!(b, non_null);
+                                assert_eq!(
+                                    b, vec.extract(index - $id::<i32>::lanes())
+                                );
+                            }
+                        }
+                    }
+
+                    // FIXME: wasm-bindgen-test does not support #[should_panic]
+                    // #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    // #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    #[cfg(not(target_arch = "wasm32"))]
+                    #[test]
+                    #[should_panic]
+                    fn write_to_slice_aligned_fail_lanes() {
+                        let (null, non_null) = ptr_vals!($id<i32>);
+                        let mut aligned = A {
+                            data: [null; 2 * $id::<i32>::lanes()],
+                        };
+                        let vec = $id::<i32>::splat(non_null);
+                        // the slice is not large enough => panic
+                        unsafe {
+                            vec.write_to_slice_aligned(
+                                &mut aligned.data[2 * $id::<i32>::lanes()..]
+                            )
+                        };
+                    }
+
+                    // FIXME: wasm-bindgen-test does not support #[should_panic]
+                    // #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    // #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    #[cfg(not(target_arch = "wasm32"))]
+                    #[test]
+                    #[should_panic]
+                    fn write_to_slice_aligned_fail_align() {
+                        let (null, non_null) = ptr_vals!($id<i32>);
+                        unsafe {
+                            let mut aligned = A {
+                                data: [null; 2 * $id::<i32>::lanes()],
+                            };
+
+                            // get a pointer to the front of data
+                            let ptr = aligned.data.as_mut_ptr();
+                            // offset pointer by one element
+                            let ptr = ptr.wrapping_add(1);
+
+                            if ptr.align_offset(
+                                crate::mem::align_of::<$id<i32>>()
+                            ) == 0 {
+                                // the pointer is properly aligned, so
+                                // write_to_slice_aligned won't fail here (e.g.
+                                // this can happen for i128x1). So we panic to
+                                // make the "should_fail" test pass:
+                                panic!("ok");
+                            }
+
+                            // create a slice - this is safe, because the
+                            // elements of the slice exist, are properly
+                            // initialized, and properly aligned:
+                            let s = slice::from_raw_parts_mut(
+                                ptr, $id::<i32>::lanes()
+                            );
+                            // this should always panic because the slice
+                            // alignment does not match the alignment
+                            // requirements for the vector type:
+                            let vec = $id::<i32>::splat(non_null);
+                            vec.write_to_slice_aligned(s);
+                        }
+                    }
+                }
+            }
+        }
+
+        impl<T> crate::hash::Hash for $id<T> {
+            #[inline]
+            fn hash<H: crate::hash::Hasher>(&self, state: &mut H) {
+                let s: $usize_ty = unsafe { crate::mem::transmute(*self) };
+                s.hash(state)
+            }
+        }
+
+        test_if! {
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _hash>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn hash() {
+                        use crate::hash::{Hash, Hasher};
+                        #[allow(deprecated)]
+                        use crate::hash::{SipHasher13};
+
+                        let values = [1_i32; $elem_count];
+
+                        let mut vec: $id<i32> = Default::default();
+                        let mut array = [
+                            $id::<i32>::null().extract(0);
+                            $elem_count
+                        ];
+
+                        for i in 0..$elem_count {
+                            let ptr = unsafe {
+                                crate::mem::transmute(
+                                    &values[i] as *const i32
+                                )
+                            };
+                            vec = vec.replace(i, ptr);
+                            array[i] = ptr;
+                        }
+
+                        #[allow(deprecated)]
+                        let mut a_hash = SipHasher13::new();
+                        let mut v_hash = a_hash.clone();
+                        array.hash(&mut a_hash);
+                        vec.hash(&mut v_hash);
+                        assert_eq!(a_hash.finish(), v_hash.finish());
+                    }
+                }
+            }
+        }
+
+        impl<T> $id<T> {
+            /// Calculates the offset from a pointer.
+            ///
+            /// `count` is in units of `T`; e.g. a count of `3` represents a
+            /// pointer offset of `3 * size_of::<T>()` bytes.
+            ///
+            /// # Safety
+            ///
+            /// If any of the following conditions are violated, the result is
+            /// Undefined Behavior:
+            ///
+            /// * Both the starting and resulting pointer must be either in
+            /// bounds or one byte past the end of an allocated object.
+            ///
+            /// * The computed offset, in bytes, cannot overflow an `isize`.
+            ///
+            /// * The offset being in bounds cannot rely on "wrapping around"
+            /// the address space. That is, the infinite-precision sum, in bytes
+            /// must fit in a `usize`.
+            ///
+            /// The compiler and standard library generally tries to ensure
+            /// allocations never reach a size where an offset is a concern. For
+            /// instance, `Vec` and `Box` ensure they never allocate more than
+            /// `isize::MAX` bytes, so `vec.as_ptr().offset(vec.len() as isize)`
+            /// is always safe.
+            ///
+            /// Most platforms fundamentally can't even construct such an
+            /// allocation. For instance, no known 64-bit platform can ever
+            /// serve a request for 263 bytes due to page-table limitations or
+            /// splitting the address space. However, some 32-bit and 16-bit
+            /// platforms may successfully serve a request for more than
+            /// `isize::MAX` bytes with things like Physical Address Extension.
+            /// As such, memory acquired directly from allocators or memory
+            /// mapped files may be too large to handle with this function.
+            ///
+            /// Consider using `wrapping_offset` instead if these constraints
+            /// are difficult to satisfy. The only advantage of this method is
+            /// that it enables more aggressive compiler optimizations.
+            #[inline]
+            pub unsafe fn offset(self, count: $isize_ty) -> Self {
+                // FIXME: should use LLVM's `add nsw nuw`
+                self.wrapping_offset(count)
+            }
+
+            /// Calculates the offset from a pointer using wrapping arithmetic.
+            ///
+            /// `count` is in units of `T`; e.g. a count of `3` represents a
+            /// pointer offset of `3 * size_of::<T>()` bytes.
+            ///
+            /// # Safety
+            ///
+            /// The resulting pointer does not need to be in bounds, but it is
+            /// potentially hazardous to dereference (which requires unsafe).
+            ///
+            /// Always use `.offset(count)` instead when possible, because
+            /// offset allows the compiler to optimize better.
+            #[inline]
+            pub fn wrapping_offset(self, count: $isize_ty) -> Self {
+                unsafe {
+                    let x: $isize_ty = crate::mem::transmute(self);
+                    // note: {+,*} currently performs a `wrapping_{add, mul}`
+                    crate::mem::transmute(
+                        x + (count * crate::mem::size_of::<T>() as isize)
+                    )
+                }
+            }
+
+            /// Calculates the distance between two pointers.
+            ///
+            /// The returned value is in units of `T`: the distance in bytes is
+            /// divided by `mem::size_of::<T>()`.
+            ///
+            /// This function is the inverse of offset.
+            ///
+            /// # Safety
+            ///
+            /// If any of the following conditions are violated, the result is
+            /// Undefined Behavior:
+            ///
+            /// * Both the starting and other pointer must be either in bounds
+            /// or one byte past the end of the same allocated object.
+            ///
+            /// * The distance between the pointers, in bytes, cannot overflow
+            /// an `isize`.
+            ///
+            /// * The distance between the pointers, in bytes, must be an exact
+            /// multiple of the size of `T`.
+            ///
+            /// * The distance being in bounds cannot rely on "wrapping around"
+            /// the address space.
+            ///
+            /// The compiler and standard library generally try to ensure
+            /// allocations never reach a size where an offset is a concern. For
+            /// instance, `Vec` and `Box` ensure they never allocate more than
+            /// `isize::MAX` bytes, so `ptr_into_vec.offset_from(vec.as_ptr())`
+            /// is always safe.
+            ///
+            /// Most platforms fundamentally can't even construct such an
+            /// allocation. For instance, no known 64-bit platform can ever
+            /// serve a request for 263 bytes due to page-table limitations or
+            /// splitting the address space. However, some 32-bit and 16-bit
+            /// platforms may successfully serve a request for more than
+            /// `isize::MAX` bytes with things like Physical Address Extension.
+            /// As such, memory acquired directly from allocators or memory
+            /// mapped files may be too large to handle with this function.
+            ///
+            /// Consider using wrapping_offset_from instead if these constraints
+            /// are difficult to satisfy. The only advantage of this method is
+            /// that it enables more aggressive compiler optimizations.
+            #[inline]
+            pub unsafe fn offset_from(self, origin: Self) -> $isize_ty {
+                // FIXME: should use LLVM's `sub nsw nuw`.
+                self.wrapping_offset_from(origin)
+            }
+
+            /// Calculates the distance between two pointers.
+            ///
+            /// The returned value is in units of `T`: the distance in bytes is
+            /// divided by `mem::size_of::<T>()`.
+            ///
+            /// If the address different between the two pointers is not a
+            /// multiple of `mem::size_of::<T>()` then the result of the
+            /// division is rounded towards zero.
+            ///
+            /// Though this method is safe for any two pointers, note that its
+            /// result will be mostly useless if the two pointers aren't into
+            /// the same allocated object, for example if they point to two
+            /// different local variables.
+            #[inline]
+            pub fn wrapping_offset_from(self, origin: Self) -> $isize_ty {
+                let x: $isize_ty = unsafe { crate::mem::transmute(self) };
+                let y: $isize_ty = unsafe { crate::mem::transmute(origin) };
+                // note: {-,/} currently perform wrapping_{sub, div}
+                (y - x) / (crate::mem::size_of::<T>() as isize)
+            }
+
+            /// Calculates the offset from a pointer (convenience for
+            /// `.offset(count as isize)`).
+            ///
+            /// `count` is in units of `T`; e.g. a count of 3 represents a
+            /// pointer offset of `3 * size_of::<T>()` bytes.
+            ///
+            /// # Safety
+            ///
+            /// If any of the following conditions are violated, the result is
+            /// Undefined Behavior:
+            ///
+            /// * Both the starting and resulting pointer must be either in
+            /// bounds or one byte past the end of an allocated object.
+            ///
+            /// * The computed offset, in bytes, cannot overflow an `isize`.
+            ///
+            /// * The offset being in bounds cannot rely on "wrapping around"
+            /// the address space. That is, the infinite-precision sum must fit
+            /// in a `usize`.
+            ///
+            /// The compiler and standard library generally tries to ensure
+            /// allocations never reach a size where an offset is a concern. For
+            /// instance, `Vec` and `Box` ensure they never allocate more than
+            /// `isize::MAX` bytes, so `vec.as_ptr().add(vec.len())` is always
+            /// safe.
+            ///
+            /// Most platforms fundamentally can't even construct such an
+            /// allocation. For instance, no known 64-bit platform can ever
+            /// serve a request for 263 bytes due to page-table limitations or
+            /// splitting the address space. However, some 32-bit and 16-bit
+            /// platforms may successfully serve a request for more than
+            /// `isize::MAX` bytes with things like Physical Address Extension.
+            /// As such, memory acquired directly from allocators or memory
+            /// mapped files may be too large to handle with this function.
+            ///
+            /// Consider using `wrapping_offset` instead if these constraints
+            /// are difficult to satisfy. The only advantage of this method is
+            /// that it enables more aggressive compiler optimizations.
+            #[inline]
+            #[allow(clippy::should_implement_trait)]
+            pub unsafe fn add(self, count: $usize_ty) -> Self {
+                self.offset(count.cast())
+            }
+
+            /// Calculates the offset from a pointer (convenience for
+            /// `.offset((count as isize).wrapping_neg())`).
+            ///
+            /// `count` is in units of T; e.g. a `count` of 3 represents a
+            /// pointer offset of `3 * size_of::<T>()` bytes.
+            ///
+            /// # Safety
+            ///
+            /// If any of the following conditions are violated, the result is
+            /// Undefined Behavior:
+            ///
+            /// * Both the starting and resulting pointer must be either in
+            /// bounds or one byte past the end of an allocated object.
+            ///
+            /// * The computed offset cannot exceed `isize::MAX` **bytes**.
+            ///
+            /// * The offset being in bounds cannot rely on "wrapping around"
+            /// the address space. That is, the infinite-precision sum must fit
+            /// in a usize.
+            ///
+            /// The compiler and standard library generally tries to ensure
+            /// allocations never reach a size where an offset is a concern. For
+            /// instance, `Vec` and `Box` ensure they never allocate more than
+            /// `isize::MAX` bytes, so
+            /// `vec.as_ptr().add(vec.len()).sub(vec.len())` is always safe.
+            ///
+            /// Most platforms fundamentally can't even construct such an
+            /// allocation. For instance, no known 64-bit platform can ever
+            /// serve a request for 2<sup>63</sup> bytes due to page-table
+            /// limitations or splitting the address space. However, some 32-bit
+            /// and 16-bit platforms may successfully serve a request for more
+            /// than `isize::MAX` bytes with things like Physical Address
+            /// Extension. As such, memory acquired directly from allocators or
+            /// memory mapped files *may* be too large to handle with this
+            /// function.
+            ///
+            /// Consider using `wrapping_offset` instead if these constraints
+            /// are difficult to satisfy. The only advantage of this method is
+            /// that it enables more aggressive compiler optimizations.
+            #[inline]
+            #[allow(clippy::should_implement_trait)]
+            pub unsafe fn sub(self, count: $usize_ty) -> Self {
+                let x: $isize_ty = count.cast();
+                // note: - is currently wrapping_neg
+                self.offset(-x)
+            }
+
+            /// Calculates the offset from a pointer using wrapping arithmetic.
+            /// (convenience for `.wrapping_offset(count as isize)`)
+            ///
+            /// `count` is in units of T; e.g. a `count` of 3 represents a
+            /// pointer offset of `3 * size_of::<T>()` bytes.
+            ///
+            /// # Safety
+            ///
+            /// The resulting pointer does not need to be in bounds, but it is
+            /// potentially hazardous to dereference (which requires `unsafe`).
+            ///
+            /// Always use `.add(count)` instead when possible, because `add`
+            /// allows the compiler to optimize better.
+            #[inline]
+            pub fn wrapping_add(self, count: $usize_ty) -> Self {
+                self.wrapping_offset(count.cast())
+            }
+
+            /// Calculates the offset from a pointer using wrapping arithmetic.
+            /// (convenience for `.wrapping_offset((count as
+            /// isize).wrapping_sub())`)
+            ///
+            /// `count` is in units of T; e.g. a `count` of 3 represents a
+            /// pointer offset of `3 * size_of::<T>()` bytes.
+            ///
+            /// # Safety
+            ///
+            /// The resulting pointer does not need to be in bounds, but it is
+            /// potentially hazardous to dereference (which requires `unsafe`).
+            ///
+            /// Always use `.sub(count)` instead when possible, because `sub`
+            /// allows the compiler to optimize better.
+            #[inline]
+            pub fn wrapping_sub(self, count: $usize_ty) -> Self {
+                let x: $isize_ty = count.cast();
+                self.wrapping_offset(-1 * x)
+            }
+        }
+
+        impl<T> $id<T> {
+            /// Shuffle vector elements according to `indices`.
+            #[inline]
+            pub fn shuffle1_dyn<I>(self, indices: I) -> Self
+                where
+                Self: codegen::shuffle1_dyn::Shuffle1Dyn<Indices = I>,
+            {
+                codegen::shuffle1_dyn::Shuffle1Dyn::shuffle1_dyn(self, indices)
+            }
+        }
+
+        test_if! {
+                $test_tt:
+            paste::item! {
+                pub mod [<$id _shuffle1_dyn>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn shuffle1_dyn() {
+                        let (null, non_null) = ptr_vals!($id<i32>);
+
+                        // alternating = [non_null, null, non_null, null, ...]
+                        let mut alternating = $id::<i32>::splat(null);
+                        for i in 0..$id::<i32>::lanes() {
+                            if i % 2 == 0 {
+                                alternating = alternating.replace(i, non_null);
+                            }
+                        }
+
+                        type Indices = <$id<i32>
+                            as codegen::shuffle1_dyn::Shuffle1Dyn>::Indices;
+                        // even = [0, 0, 2, 2, 4, 4, ..]
+                        let even = {
+                            let mut v = Indices::splat(0);
+                            for i in 0..$id::<i32>::lanes() {
+                                if i % 2 == 0 {
+                                    v = v.replace(i, (i as u8).into());
+                                } else {
+                                v = v.replace(i, (i as u8 - 1).into());
+                                }
+                            }
+                            v
+                        };
+                        // odd = [1, 1, 3, 3, 5, 5, ...]
+                        let odd = {
+                            let mut v = Indices::splat(0);
+                            for i in 0..$id::<i32>::lanes() {
+                                if i % 2 != 0 {
+                                    v = v.replace(i, (i as u8).into());
+                                } else {
+                                    v = v.replace(i, (i as u8 + 1).into());
+                                }
+                            }
+                            v
+                        };
+
+                        assert_eq!(
+                            alternating.shuffle1_dyn(even),
+                            $id::<i32>::splat(non_null)
+                        );
+                        if $id::<i32>::lanes() > 1 {
+                            assert_eq!(
+                                alternating.shuffle1_dyn(odd),
+                                $id::<i32>::splat(null)
+                            );
+                        }
+                    }
+                }
+            }
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/ops.rs.html b/src/packed_simd/api/ops.rs.html new file mode 100644 index 000000000..ffb79a56d --- /dev/null +++ b/src/packed_simd/api/ops.rs.html @@ -0,0 +1,67 @@ +ops.rs.html -- source
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+//! Implementation of the `ops` traits
+#[macro_use]
+mod vector_mask_bitwise;
+#[macro_use]
+mod scalar_mask_bitwise;
+
+#[macro_use]
+mod vector_arithmetic;
+#[macro_use]
+mod scalar_arithmetic;
+
+#[macro_use]
+mod vector_bitwise;
+#[macro_use]
+mod scalar_bitwise;
+
+#[macro_use]
+mod vector_shifts;
+#[macro_use]
+mod scalar_shifts;
+
+#[macro_use]
+mod vector_rotates;
+
+#[macro_use]
+mod vector_neg;
+
+#[macro_use]
+mod vector_int_min_max;
+
+#[macro_use]
+mod vector_float_min_max;
+
+
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+//! Vertical (lane-wise) vector-scalar / scalar-vector arithmetic operations.
+
+macro_rules! impl_ops_scalar_arithmetic {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident | $test_tt:tt) => {
+        impl crate::ops::Add<$elem_ty> for $id {
+            type Output = Self;
+            #[inline]
+            fn add(self, other: $elem_ty) -> Self {
+                self + $id::splat(other)
+            }
+        }
+        impl crate::ops::Add<$id> for $elem_ty {
+            type Output = $id;
+            #[inline]
+            fn add(self, other: $id) -> $id {
+                $id::splat(self) + other
+            }
+        }
+
+        impl crate::ops::Sub<$elem_ty> for $id {
+            type Output = Self;
+            #[inline]
+            fn sub(self, other: $elem_ty) -> Self {
+                self - $id::splat(other)
+            }
+        }
+        impl crate::ops::Sub<$id> for $elem_ty {
+            type Output = $id;
+            #[inline]
+            fn sub(self, other: $id) -> $id {
+                $id::splat(self) - other
+            }
+        }
+
+        impl crate::ops::Mul<$elem_ty> for $id {
+            type Output = Self;
+            #[inline]
+            fn mul(self, other: $elem_ty) -> Self {
+                self * $id::splat(other)
+            }
+        }
+        impl crate::ops::Mul<$id> for $elem_ty {
+            type Output = $id;
+            #[inline]
+            fn mul(self, other: $id) -> $id {
+                $id::splat(self) * other
+            }
+        }
+
+        impl crate::ops::Div<$elem_ty> for $id {
+            type Output = Self;
+            #[inline]
+            fn div(self, other: $elem_ty) -> Self {
+                self / $id::splat(other)
+            }
+        }
+        impl crate::ops::Div<$id> for $elem_ty {
+            type Output = $id;
+            #[inline]
+            fn div(self, other: $id) -> $id {
+                $id::splat(self) / other
+            }
+        }
+
+        impl crate::ops::Rem<$elem_ty> for $id {
+            type Output = Self;
+            #[inline]
+            fn rem(self, other: $elem_ty) -> Self {
+                self % $id::splat(other)
+            }
+        }
+        impl crate::ops::Rem<$id> for $elem_ty {
+            type Output = $id;
+            #[inline]
+            fn rem(self, other: $id) -> $id {
+                $id::splat(self) % other
+            }
+        }
+
+        impl crate::ops::AddAssign<$elem_ty> for $id {
+            #[inline]
+            fn add_assign(&mut self, other: $elem_ty) {
+                *self = *self + other;
+            }
+        }
+
+        impl crate::ops::SubAssign<$elem_ty> for $id {
+            #[inline]
+            fn sub_assign(&mut self, other: $elem_ty) {
+                *self = *self - other;
+            }
+        }
+
+        impl crate::ops::MulAssign<$elem_ty> for $id {
+            #[inline]
+            fn mul_assign(&mut self, other: $elem_ty) {
+                *self = *self * other;
+            }
+        }
+
+        impl crate::ops::DivAssign<$elem_ty> for $id {
+            #[inline]
+            fn div_assign(&mut self, other: $elem_ty) {
+                *self = *self / other;
+            }
+        }
+
+        impl crate::ops::RemAssign<$elem_ty> for $id {
+            #[inline]
+            fn rem_assign(&mut self, other: $elem_ty) {
+                *self = *self % other;
+            }
+        }
+
+        test_if!{
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _ops_scalar_arith>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn ops_scalar_arithmetic() {
+                        let zi = 0 as $elem_ty;
+                        let oi = 1 as $elem_ty;
+                        let ti = 2 as $elem_ty;
+                        let fi = 4 as $elem_ty;
+                        let z = $id::splat(zi);
+                        let o = $id::splat(oi);
+                        let t = $id::splat(ti);
+                        let f = $id::splat(fi);
+
+                        // add
+                        assert_eq!(zi + z, z);
+                        assert_eq!(z + zi, z);
+                        assert_eq!(oi + z, o);
+                        assert_eq!(o + zi, o);
+                        assert_eq!(ti + z, t);
+                        assert_eq!(t + zi, t);
+                        assert_eq!(ti + t, f);
+                        assert_eq!(t + ti, f);
+                        // sub
+                        assert_eq!(zi - z, z);
+                        assert_eq!(z - zi, z);
+                        assert_eq!(oi - z, o);
+                        assert_eq!(o - zi, o);
+                        assert_eq!(ti - z, t);
+                        assert_eq!(t - zi, t);
+                        assert_eq!(fi - t, t);
+                        assert_eq!(f - ti, t);
+                        assert_eq!(f - o - o, t);
+                        assert_eq!(f - oi - oi, t);
+                        // mul
+                        assert_eq!(zi * z, z);
+                        assert_eq!(z * zi, z);
+                        assert_eq!(zi * o, z);
+                        assert_eq!(z * oi, z);
+                        assert_eq!(zi * t, z);
+                        assert_eq!(z * ti, z);
+                        assert_eq!(oi * t, t);
+                        assert_eq!(o * ti, t);
+                        assert_eq!(ti * t, f);
+                        assert_eq!(t * ti, f);
+                        // div
+                        assert_eq!(zi / o, z);
+                        assert_eq!(z / oi, z);
+                        assert_eq!(ti / o, t);
+                        assert_eq!(t / oi, t);
+                        assert_eq!(fi / o, f);
+                        assert_eq!(f / oi, f);
+                        assert_eq!(ti / t, o);
+                        assert_eq!(t / ti, o);
+                        assert_eq!(fi / t, t);
+                        assert_eq!(f / ti, t);
+                        // rem
+                        assert_eq!(oi % o, z);
+                        assert_eq!(o % oi, z);
+                        assert_eq!(fi % t, z);
+                        assert_eq!(f % ti, z);
+
+                        {
+                            let mut v = z;
+                            assert_eq!(v, z);
+                            v += oi; // add_assign
+                            assert_eq!(v, o);
+                            v -= oi; // sub_assign
+                            assert_eq!(v, z);
+                            v = t;
+                            v *= oi; // mul_assign
+                            assert_eq!(v, t);
+                            v *= ti;
+                            assert_eq!(v, f);
+                            v /= oi; // div_assign
+                            assert_eq!(v, f);
+                            v /= ti;
+                            assert_eq!(v, t);
+                            v %= ti; // rem_assign
+                            assert_eq!(v, z);
+                        }
+                    }
+                }
+            }
+        }
+    };
+}
+
+
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+
+//! Vertical (lane-wise) vector-scalar / scalar-vector bitwise operations.
+
+macro_rules! impl_ops_scalar_bitwise {
+    (
+        [$elem_ty:ident; $elem_count:expr]:
+        $id:ident | $test_tt:tt |
+        ($true:expr, $false:expr)
+    ) => {
+        impl crate::ops::BitXor<$elem_ty> for $id {
+            type Output = Self;
+            #[inline]
+            fn bitxor(self, other: $elem_ty) -> Self {
+                self ^ $id::splat(other)
+            }
+        }
+        impl crate::ops::BitXor<$id> for $elem_ty {
+            type Output = $id;
+            #[inline]
+            fn bitxor(self, other: $id) -> $id {
+                $id::splat(self) ^ other
+            }
+        }
+
+        impl crate::ops::BitAnd<$elem_ty> for $id {
+            type Output = Self;
+            #[inline]
+            fn bitand(self, other: $elem_ty) -> Self {
+                self & $id::splat(other)
+            }
+        }
+        impl crate::ops::BitAnd<$id> for $elem_ty {
+            type Output = $id;
+            #[inline]
+            fn bitand(self, other: $id) -> $id {
+                $id::splat(self) & other
+            }
+        }
+
+        impl crate::ops::BitOr<$elem_ty> for $id {
+            type Output = Self;
+            #[inline]
+            fn bitor(self, other: $elem_ty) -> Self {
+                self | $id::splat(other)
+            }
+        }
+        impl crate::ops::BitOr<$id> for $elem_ty {
+            type Output = $id;
+            #[inline]
+            fn bitor(self, other: $id) -> $id {
+                $id::splat(self) | other
+            }
+        }
+
+        impl crate::ops::BitAndAssign<$elem_ty> for $id {
+            #[inline]
+            fn bitand_assign(&mut self, other: $elem_ty) {
+                *self = *self & other;
+            }
+        }
+        impl crate::ops::BitOrAssign<$elem_ty> for $id {
+            #[inline]
+            fn bitor_assign(&mut self, other: $elem_ty) {
+                *self = *self | other;
+            }
+        }
+        impl crate::ops::BitXorAssign<$elem_ty> for $id {
+            #[inline]
+            fn bitxor_assign(&mut self, other: $elem_ty) {
+                *self = *self ^ other;
+            }
+        }
+
+        test_if!{
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _ops_scalar_bitwise>] {
+                    use super::*;
+
+                    #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn ops_scalar_bitwise() {
+                        let zi = 0 as $elem_ty;
+                        let oi = 1 as $elem_ty;
+                        let ti = 2 as $elem_ty;
+                        let z = $id::splat(zi);
+                        let o = $id::splat(oi);
+                        let t = $id::splat(ti);
+
+                        // BitAnd:
+                        assert_eq!(oi & o, o);
+                        assert_eq!(o & oi, o);
+                        assert_eq!(oi & z, z);
+                        assert_eq!(o & zi, z);
+                        assert_eq!(zi & o, z);
+                        assert_eq!(z & oi, z);
+                        assert_eq!(zi & z, z);
+                        assert_eq!(z & zi, z);
+
+                        assert_eq!(ti & t, t);
+                        assert_eq!(t & ti, t);
+                        assert_eq!(ti & o, z);
+                        assert_eq!(t & oi, z);
+                        assert_eq!(oi & t, z);
+                        assert_eq!(o & ti, z);
+
+                        // BitOr:
+                        assert_eq!(oi | o, o);
+                        assert_eq!(o | oi, o);
+                        assert_eq!(oi | z, o);
+                        assert_eq!(o | zi, o);
+                        assert_eq!(zi | o, o);
+                        assert_eq!(z | oi, o);
+                        assert_eq!(zi | z, z);
+                        assert_eq!(z | zi, z);
+
+                        assert_eq!(ti | t, t);
+                        assert_eq!(t | ti, t);
+                        assert_eq!(zi | t, t);
+                        assert_eq!(z | ti, t);
+                        assert_eq!(ti | z, t);
+                        assert_eq!(t | zi, t);
+
+                        // BitXOR:
+                        assert_eq!(oi ^ o, z);
+                        assert_eq!(o ^ oi, z);
+                        assert_eq!(zi ^ z, z);
+                        assert_eq!(z ^ zi, z);
+                        assert_eq!(zi ^ o, o);
+                        assert_eq!(z ^ oi, o);
+                        assert_eq!(oi ^ z, o);
+                        assert_eq!(o ^ zi, o);
+
+                        assert_eq!(ti ^ t, z);
+                        assert_eq!(t ^ ti, z);
+                        assert_eq!(ti ^ z, t);
+                        assert_eq!(t ^ zi, t);
+                        assert_eq!(zi ^ t, t);
+                        assert_eq!(z ^ ti, t);
+
+                        {
+                            // AndAssign:
+                            let mut v = o;
+                            v &= ti;
+                            assert_eq!(v, z);
+                        }
+                        {
+                            // OrAssign:
+                            let mut v = z;
+                            v |= oi;
+                            assert_eq!(v, o);
+                        }
+                        {
+                            // XORAssign:
+                            let mut v = z;
+                            v ^= oi;
+                            assert_eq!(v, o);
+                        }
+                    }
+                }
+            }
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/ops/scalar_mask_bitwise.rs.html b/src/packed_simd/api/ops/scalar_mask_bitwise.rs.html new file mode 100644 index 000000000..814a4c6c3 --- /dev/null +++ b/src/packed_simd/api/ops/scalar_mask_bitwise.rs.html @@ -0,0 +1,283 @@ +scalar_mask_bitwise.rs.html -- source
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+//! Vertical (lane-wise) vector-vector bitwise operations.
+
+macro_rules! impl_ops_scalar_mask_bitwise {
+    (
+        [$elem_ty:ident; $elem_count:expr]:
+        $id:ident | $test_tt:tt |
+        ($true:expr, $false:expr)
+    ) => {
+        impl crate::ops::BitXor<bool> for $id {
+            type Output = Self;
+            #[inline]
+            fn bitxor(self, other: bool) -> Self {
+                self ^ $id::splat(other)
+            }
+        }
+        impl crate::ops::BitXor<$id> for bool {
+            type Output = $id;
+            #[inline]
+            fn bitxor(self, other: $id) -> $id {
+                $id::splat(self) ^ other
+            }
+        }
+
+        impl crate::ops::BitAnd<bool> for $id {
+            type Output = Self;
+            #[inline]
+            fn bitand(self, other: bool) -> Self {
+                self & $id::splat(other)
+            }
+        }
+        impl crate::ops::BitAnd<$id> for bool {
+            type Output = $id;
+            #[inline]
+            fn bitand(self, other: $id) -> $id {
+                $id::splat(self) & other
+            }
+        }
+
+        impl crate::ops::BitOr<bool> for $id {
+            type Output = Self;
+            #[inline]
+            fn bitor(self, other: bool) -> Self {
+                self | $id::splat(other)
+            }
+        }
+        impl crate::ops::BitOr<$id> for bool {
+            type Output = $id;
+            #[inline]
+            fn bitor(self, other: $id) -> $id {
+                $id::splat(self) | other
+            }
+        }
+
+        impl crate::ops::BitAndAssign<bool> for $id {
+            #[inline]
+            fn bitand_assign(&mut self, other: bool) {
+                *self = *self & other;
+            }
+        }
+        impl crate::ops::BitOrAssign<bool> for $id {
+            #[inline]
+            fn bitor_assign(&mut self, other: bool) {
+                *self = *self | other;
+            }
+        }
+        impl crate::ops::BitXorAssign<bool> for $id {
+            #[inline]
+            fn bitxor_assign(&mut self, other: bool) {
+                *self = *self ^ other;
+            }
+        }
+
+        test_if!{
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _ops_scalar_mask_bitwise>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn ops_scalar_mask_bitwise() {
+                        let ti = true;
+                        let fi = false;
+                        let t = $id::splat(ti);
+                        let f = $id::splat(fi);
+                        assert!(t != f);
+                        assert!(!(t == f));
+
+                        // BitAnd:
+                        assert_eq!(ti & f, f);
+                        assert_eq!(t & fi, f);
+                        assert_eq!(fi & t, f);
+                        assert_eq!(f & ti, f);
+                        assert_eq!(ti & t, t);
+                        assert_eq!(t & ti, t);
+                        assert_eq!(fi & f, f);
+                        assert_eq!(f & fi, f);
+
+                        // BitOr:
+                        assert_eq!(ti | f, t);
+                        assert_eq!(t | fi, t);
+                        assert_eq!(fi | t, t);
+                        assert_eq!(f | ti, t);
+                        assert_eq!(ti | t, t);
+                        assert_eq!(t | ti, t);
+                        assert_eq!(fi | f, f);
+                        assert_eq!(f | fi, f);
+
+                        // BitXOR:
+                        assert_eq!(ti ^ f, t);
+                        assert_eq!(t ^ fi, t);
+                        assert_eq!(fi ^ t, t);
+                        assert_eq!(f ^ ti, t);
+                        assert_eq!(ti ^ t, f);
+                        assert_eq!(t ^ ti, f);
+                        assert_eq!(fi ^ f, f);
+                        assert_eq!(f ^ fi, f);
+
+                        {
+                            // AndAssign:
+                            let mut v = f;
+                            v &= ti;
+                            assert_eq!(v, f);
+                        }
+                        {
+                            // OrAssign:
+                            let mut v = f;
+                            v |= ti;
+                            assert_eq!(v, t);
+                        }
+                        {
+                            // XORAssign:
+                            let mut v = f;
+                            v ^= ti;
+                            assert_eq!(v, t);
+                        }
+                    }
+                }
+            }
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/ops/scalar_shifts.rs.html b/src/packed_simd/api/ops/scalar_shifts.rs.html new file mode 100644 index 000000000..ce5d0c3b4 --- /dev/null +++ b/src/packed_simd/api/ops/scalar_shifts.rs.html @@ -0,0 +1,217 @@ +scalar_shifts.rs.html -- source
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+
+//! Vertical (lane-wise) vector-scalar shifts operations.
+
+macro_rules! impl_ops_scalar_shifts {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident | $test_tt:tt) => {
+        impl crate::ops::Shl<u32> for $id {
+            type Output = Self;
+            #[inline]
+            fn shl(self, other: u32) -> Self {
+                self << $id::splat(other as $elem_ty)
+            }
+        }
+        impl crate::ops::Shr<u32> for $id {
+            type Output = Self;
+            #[inline]
+            fn shr(self, other: u32) -> Self {
+                self >> $id::splat(other as $elem_ty)
+            }
+        }
+
+        impl crate::ops::ShlAssign<u32> for $id {
+            #[inline]
+            fn shl_assign(&mut self, other: u32) {
+                *self = *self << other;
+            }
+        }
+        impl crate::ops::ShrAssign<u32> for $id {
+            #[inline]
+            fn shr_assign(&mut self, other: u32) {
+                *self = *self >> other;
+            }
+        }
+        test_if!{
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _ops_scalar_shifts>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    #[cfg_attr(any(target_arch = "s390x", target_arch = "sparc64"),
+                               allow(unreachable_code,
+                                     unused_variables,
+                                     unused_mut)
+                    )]
+                    // ^^^ FIXME: https://github.com/rust-lang/rust/issues/55344
+                    fn ops_scalar_shifts() {
+                        let z = $id::splat(0 as $elem_ty);
+                        let o = $id::splat(1 as $elem_ty);
+                        let t = $id::splat(2 as $elem_ty);
+                        let f = $id::splat(4 as $elem_ty);
+
+                        {
+                            let zi = 0 as u32;
+                            let oi = 1 as u32;
+                            let ti = 2 as u32;
+                            let maxi
+                                = (mem::size_of::<$elem_ty>() * 8 - 1) as u32;
+
+                            // shr
+                            assert_eq!(z >> zi, z);
+                            assert_eq!(z >> oi, z);
+                            assert_eq!(z >> ti, z);
+                            assert_eq!(z >> ti, z);
+
+                            #[cfg(any(target_arch = "s390x", target_arch = "sparc64"))] {
+                                // FIXME: https://github.com/rust-lang-nursery/packed_simd/issues/13
+                                return;
+                            }
+
+                            assert_eq!(o >> zi, o);
+                            assert_eq!(t >> zi, t);
+                            assert_eq!(f >> zi, f);
+                            assert_eq!(f >> maxi, z);
+
+                            assert_eq!(o >> oi, z);
+                            assert_eq!(t >> oi, o);
+                            assert_eq!(t >> ti, z);
+                            assert_eq!(f >> oi, t);
+                            assert_eq!(f >> ti, o);
+                            assert_eq!(f >> maxi, z);
+
+                            // shl
+                            assert_eq!(z << zi, z);
+                            assert_eq!(o << zi, o);
+                            assert_eq!(t << zi, t);
+                            assert_eq!(f << zi, f);
+                            assert_eq!(f << maxi, z);
+
+                            assert_eq!(o << oi, t);
+                            assert_eq!(o << ti, f);
+                            assert_eq!(t << oi, f);
+
+                            {  // shr_assign
+                                let mut v = o;
+                                v >>= oi;
+                                assert_eq!(v, z);
+                            }
+                            {  // shl_assign
+                                let mut v = o;
+                                v <<= oi;
+                                assert_eq!(v, t);
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/ops/vector_arithmetic.rs.html b/src/packed_simd/api/ops/vector_arithmetic.rs.html new file mode 100644 index 000000000..39fd81564 --- /dev/null +++ b/src/packed_simd/api/ops/vector_arithmetic.rs.html @@ -0,0 +1,299 @@ +vector_arithmetic.rs.html -- source
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+
+//! Vertical (lane-wise) vector-vector arithmetic operations.
+
+macro_rules! impl_ops_vector_arithmetic {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident | $test_tt:tt) => {
+        impl crate::ops::Add for $id {
+            type Output = Self;
+            #[inline]
+            fn add(self, other: Self) -> Self {
+                use crate::llvm::simd_add;
+                unsafe { Simd(simd_add(self.0, other.0)) }
+            }
+        }
+
+        impl crate::ops::Sub for $id {
+            type Output = Self;
+            #[inline]
+            fn sub(self, other: Self) -> Self {
+                use crate::llvm::simd_sub;
+                unsafe { Simd(simd_sub(self.0, other.0)) }
+            }
+        }
+
+        impl crate::ops::Mul for $id {
+            type Output = Self;
+            #[inline]
+            fn mul(self, other: Self) -> Self {
+                use crate::llvm::simd_mul;
+                unsafe { Simd(simd_mul(self.0, other.0)) }
+            }
+        }
+
+        impl crate::ops::Div for $id {
+            type Output = Self;
+            #[inline]
+            fn div(self, other: Self) -> Self {
+                use crate::llvm::simd_div;
+                unsafe { Simd(simd_div(self.0, other.0)) }
+            }
+        }
+
+        impl crate::ops::Rem for $id {
+            type Output = Self;
+            #[inline]
+            fn rem(self, other: Self) -> Self {
+                use crate::llvm::simd_rem;
+                unsafe { Simd(simd_rem(self.0, other.0)) }
+            }
+        }
+
+        impl crate::ops::AddAssign for $id {
+            #[inline]
+            fn add_assign(&mut self, other: Self) {
+                *self = *self + other;
+            }
+        }
+
+        impl crate::ops::SubAssign for $id {
+            #[inline]
+            fn sub_assign(&mut self, other: Self) {
+                *self = *self - other;
+            }
+        }
+
+        impl crate::ops::MulAssign for $id {
+            #[inline]
+            fn mul_assign(&mut self, other: Self) {
+                *self = *self * other;
+            }
+        }
+
+        impl crate::ops::DivAssign for $id {
+            #[inline]
+            fn div_assign(&mut self, other: Self) {
+                *self = *self / other;
+            }
+        }
+
+        impl crate::ops::RemAssign for $id {
+            #[inline]
+            fn rem_assign(&mut self, other: Self) {
+                *self = *self % other;
+            }
+        }
+
+        test_if!{
+            $test_tt:
+            paste::item! {
+               pub mod [<$id _ops_vector_arith>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn ops_vector_arithmetic() {
+                        let z = $id::splat(0 as $elem_ty);
+                        let o = $id::splat(1 as $elem_ty);
+                        let t = $id::splat(2 as $elem_ty);
+                        let f = $id::splat(4 as $elem_ty);
+
+                        // add
+                        assert_eq!(z + z, z);
+                        assert_eq!(o + z, o);
+                        assert_eq!(t + z, t);
+                        assert_eq!(t + t, f);
+                        // sub
+                        assert_eq!(z - z, z);
+                        assert_eq!(o - z, o);
+                        assert_eq!(t - z, t);
+                        assert_eq!(f - t, t);
+                        assert_eq!(f - o - o, t);
+                        // mul
+                        assert_eq!(z * z, z);
+                        assert_eq!(z * o, z);
+                        assert_eq!(z * t, z);
+                        assert_eq!(o * t, t);
+                        assert_eq!(t * t, f);
+                        // div
+                        assert_eq!(z / o, z);
+                        assert_eq!(t / o, t);
+                        assert_eq!(f / o, f);
+                        assert_eq!(t / t, o);
+                        assert_eq!(f / t, t);
+                        // rem
+                        assert_eq!(o % o, z);
+                        assert_eq!(f % t, z);
+
+                        {
+                            let mut v = z;
+                            assert_eq!(v, z);
+                            v += o; // add_assign
+                            assert_eq!(v, o);
+                            v -= o; // sub_assign
+                            assert_eq!(v, z);
+                            v = t;
+                            v *= o; // mul_assign
+                            assert_eq!(v, t);
+                            v *= t;
+                            assert_eq!(v, f);
+                            v /= o; // div_assign
+                            assert_eq!(v, f);
+                            v /= t;
+                            assert_eq!(v, t);
+                            v %= t; // rem_assign
+                            assert_eq!(v, z);
+                        }
+                    }
+                }
+            }
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/ops/vector_bitwise.rs.html b/src/packed_simd/api/ops/vector_bitwise.rs.html new file mode 100644 index 000000000..233f876ba --- /dev/null +++ b/src/packed_simd/api/ops/vector_bitwise.rs.html @@ -0,0 +1,261 @@ +vector_bitwise.rs.html -- source
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+
+//! Vertical (lane-wise) vector-vector bitwise operations.
+
+macro_rules! impl_ops_vector_bitwise {
+    (
+        [$elem_ty:ident; $elem_count:expr]:
+        $id:ident | $test_tt:tt |
+        ($true:expr, $false:expr)
+    ) => {
+        impl crate::ops::Not for $id {
+            type Output = Self;
+            #[inline]
+            fn not(self) -> Self {
+                Self::splat($true) ^ self
+            }
+        }
+        impl crate::ops::BitXor for $id {
+            type Output = Self;
+            #[inline]
+            fn bitxor(self, other: Self) -> Self {
+                use crate::llvm::simd_xor;
+                unsafe { Simd(simd_xor(self.0, other.0)) }
+            }
+        }
+        impl crate::ops::BitAnd for $id {
+            type Output = Self;
+            #[inline]
+            fn bitand(self, other: Self) -> Self {
+                use crate::llvm::simd_and;
+                unsafe { Simd(simd_and(self.0, other.0)) }
+            }
+        }
+        impl crate::ops::BitOr for $id {
+            type Output = Self;
+            #[inline]
+            fn bitor(self, other: Self) -> Self {
+                use crate::llvm::simd_or;
+                unsafe { Simd(simd_or(self.0, other.0)) }
+            }
+        }
+        impl crate::ops::BitAndAssign for $id {
+            #[inline]
+            fn bitand_assign(&mut self, other: Self) {
+                *self = *self & other;
+            }
+        }
+        impl crate::ops::BitOrAssign for $id {
+            #[inline]
+            fn bitor_assign(&mut self, other: Self) {
+                *self = *self | other;
+            }
+        }
+        impl crate::ops::BitXorAssign for $id {
+            #[inline]
+            fn bitxor_assign(&mut self, other: Self) {
+                *self = *self ^ other;
+            }
+        }
+
+        test_if!{
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _ops_vector_bitwise>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn ops_vector_bitwise() {
+
+                        let z = $id::splat(0 as $elem_ty);
+                        let o = $id::splat(1 as $elem_ty);
+                        let t = $id::splat(2 as $elem_ty);
+                        let m = $id::splat(!z.extract(0));
+
+                        // Not:
+                        assert_eq!(!z, m);
+                        assert_eq!(!m, z);
+
+                        // BitAnd:
+                        assert_eq!(o & o, o);
+                        assert_eq!(o & z, z);
+                        assert_eq!(z & o, z);
+                        assert_eq!(z & z, z);
+
+                        assert_eq!(t & t, t);
+                        assert_eq!(t & o, z);
+                        assert_eq!(o & t, z);
+
+                        // BitOr:
+                        assert_eq!(o | o, o);
+                        assert_eq!(o | z, o);
+                        assert_eq!(z | o, o);
+                        assert_eq!(z | z, z);
+
+                        assert_eq!(t | t, t);
+                        assert_eq!(z | t, t);
+                        assert_eq!(t | z, t);
+
+                        // BitXOR:
+                        assert_eq!(o ^ o, z);
+                        assert_eq!(z ^ z, z);
+                        assert_eq!(z ^ o, o);
+                        assert_eq!(o ^ z, o);
+
+                        assert_eq!(t ^ t, z);
+                        assert_eq!(t ^ z, t);
+                        assert_eq!(z ^ t, t);
+
+                        {
+                            // AndAssign:
+                            let mut v = o;
+                            v &= t;
+                            assert_eq!(v, z);
+                        }
+                        {
+                            // OrAssign:
+                            let mut v = z;
+                            v |= o;
+                            assert_eq!(v, o);
+                        }
+                        {
+                            // XORAssign:
+                            let mut v = z;
+                            v ^= o;
+                            assert_eq!(v, o);
+                        }
+                    }
+                }
+            }
+        }
+    };
+}
+
+
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+//! Vertical (lane-wise) vector `min` and `max` for floating-point vectors.
+
+macro_rules! impl_ops_vector_float_min_max {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident | $test_tt:tt) => {
+        impl $id {
+            /// Minimum of two vectors.
+            ///
+            /// Returns a new vector containing the minimum value of each of
+            /// the input vector lanes.
+            #[inline]
+            pub fn min(self, x: Self) -> Self {
+                use crate::llvm::simd_fmin;
+                unsafe { Simd(simd_fmin(self.0, x.0)) }
+            }
+
+            /// Maximum of two vectors.
+            ///
+            /// Returns a new vector containing the maximum value of each of
+            /// the input vector lanes.
+            #[inline]
+            pub fn max(self, x: Self) -> Self {
+                use crate::llvm::simd_fmax;
+                unsafe { Simd(simd_fmax(self.0, x.0)) }
+            }
+        }
+        test_if!{
+            $test_tt:
+            paste::item! {
+                #[cfg(not(any(
+                    // FIXME: https://github.com/rust-lang-nursery/packed_simd/issues/223
+                    all(target_arch = "mips", target_endian = "big"),
+                    target_arch = "mips64",
+                )))]
+                pub mod [<$id _ops_vector_min_max>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn min_max() {
+                        let n = crate::$elem_ty::NAN;
+                        let o = $id::splat(1. as $elem_ty);
+                        let t = $id::splat(2. as $elem_ty);
+
+                        let mut m = o; // [1., 2., 1., 2., ...]
+                        let mut on = o;
+                        for i in 0..$id::lanes() {
+                            if i % 2 == 0 {
+                                m = m.replace(i, 2. as $elem_ty);
+                                on = on.replace(i, n);
+                            }
+                        }
+
+                        assert_eq!(o.min(t), o);
+                        assert_eq!(t.min(o), o);
+                        assert_eq!(m.min(o), o);
+                        assert_eq!(o.min(m), o);
+                        assert_eq!(m.min(t), m);
+                        assert_eq!(t.min(m), m);
+
+                        assert_eq!(o.max(t), t);
+                        assert_eq!(t.max(o), t);
+                        assert_eq!(m.max(o), m);
+                        assert_eq!(o.max(m), m);
+                        assert_eq!(m.max(t), t);
+                        assert_eq!(t.max(m), t);
+
+                        assert_eq!(on.min(o), o);
+                        assert_eq!(o.min(on), o);
+                        assert_eq!(on.max(o), o);
+                        assert_eq!(o.max(on), o);
+                    }
+                }
+            }
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/ops/vector_int_min_max.rs.html b/src/packed_simd/api/ops/vector_int_min_max.rs.html new file mode 100644 index 000000000..e4b046a12 --- /dev/null +++ b/src/packed_simd/api/ops/vector_int_min_max.rs.html @@ -0,0 +1,117 @@ +vector_int_min_max.rs.html -- source
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+//! Vertical (lane-wise) vector `min` and `max` for integer vectors.
+
+macro_rules! impl_ops_vector_int_min_max {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident | $test_tt:tt) => {
+        impl $id {
+            /// Minimum of two vectors.
+            ///
+            /// Returns a new vector containing the minimum value of each of
+            /// the input vector lanes.
+            #[inline]
+            pub fn min(self, x: Self) -> Self {
+                self.lt(x).select(self, x)
+            }
+
+            /// Maximum of two vectors.
+            ///
+            /// Returns a new vector containing the maximum value of each of
+            /// the input vector lanes.
+            #[inline]
+            pub fn max(self, x: Self) -> Self {
+                self.gt(x).select(self, x)
+            }
+        }
+        test_if!{$test_tt:
+        paste::item! {
+            pub mod [<$id _ops_vector_min_max>] {
+                use super::*;
+                #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                fn min_max() {
+                    let o = $id::splat(1 as $elem_ty);
+                    let t = $id::splat(2 as $elem_ty);
+
+                    let mut m = o;
+                    for i in 0..$id::lanes() {
+                        if i % 2 == 0 {
+                            m = m.replace(i, 2 as $elem_ty);
+                        }
+                    }
+                    assert_eq!(o.min(t), o);
+                    assert_eq!(t.min(o), o);
+                    assert_eq!(m.min(o), o);
+                    assert_eq!(o.min(m), o);
+                    assert_eq!(m.min(t), m);
+                    assert_eq!(t.min(m), m);
+
+                    assert_eq!(o.max(t), t);
+                    assert_eq!(t.max(o), t);
+                    assert_eq!(m.max(o), m);
+                    assert_eq!(o.max(m), m);
+                    assert_eq!(m.max(t), t);
+                    assert_eq!(t.max(m), t);
+                }
+            }
+        }
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/ops/vector_mask_bitwise.rs.html b/src/packed_simd/api/ops/vector_mask_bitwise.rs.html new file mode 100644 index 000000000..8c6bb3dd7 --- /dev/null +++ b/src/packed_simd/api/ops/vector_mask_bitwise.rs.html @@ -0,0 +1,235 @@ +vector_mask_bitwise.rs.html -- source
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+
+//! Vertical (lane-wise) vector-vector bitwise operations.
+
+macro_rules! impl_ops_vector_mask_bitwise {
+    (
+        [$elem_ty:ident; $elem_count:expr]:
+        $id:ident | $test_tt:tt |
+        ($true:expr, $false:expr)
+    ) => {
+        impl crate::ops::Not for $id {
+            type Output = Self;
+            #[inline]
+            fn not(self) -> Self {
+                Self::splat($true) ^ self
+            }
+        }
+        impl crate::ops::BitXor for $id {
+            type Output = Self;
+            #[inline]
+            fn bitxor(self, other: Self) -> Self {
+                use crate::llvm::simd_xor;
+                unsafe { Simd(simd_xor(self.0, other.0)) }
+            }
+        }
+        impl crate::ops::BitAnd for $id {
+            type Output = Self;
+            #[inline]
+            fn bitand(self, other: Self) -> Self {
+                use crate::llvm::simd_and;
+                unsafe { Simd(simd_and(self.0, other.0)) }
+            }
+        }
+        impl crate::ops::BitOr for $id {
+            type Output = Self;
+            #[inline]
+            fn bitor(self, other: Self) -> Self {
+                use crate::llvm::simd_or;
+                unsafe { Simd(simd_or(self.0, other.0)) }
+            }
+        }
+        impl crate::ops::BitAndAssign for $id {
+            #[inline]
+            fn bitand_assign(&mut self, other: Self) {
+                *self = *self & other;
+            }
+        }
+        impl crate::ops::BitOrAssign for $id {
+            #[inline]
+            fn bitor_assign(&mut self, other: Self) {
+                *self = *self | other;
+            }
+        }
+        impl crate::ops::BitXorAssign for $id {
+            #[inline]
+            fn bitxor_assign(&mut self, other: Self) {
+                *self = *self ^ other;
+            }
+        }
+
+        test_if!{
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _ops_vector_mask_bitwise>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn ops_vector_mask_bitwise() {
+                        let t = $id::splat(true);
+                        let f = $id::splat(false);
+                        assert!(t != f);
+                        assert!(!(t == f));
+
+                        // Not:
+                        assert_eq!(!t, f);
+                        assert_eq!(t, !f);
+
+                        // BitAnd:
+                        assert_eq!(t & f, f);
+                        assert_eq!(f & t, f);
+                        assert_eq!(t & t, t);
+                        assert_eq!(f & f, f);
+
+                        // BitOr:
+                        assert_eq!(t | f, t);
+                        assert_eq!(f | t, t);
+                        assert_eq!(t | t, t);
+                        assert_eq!(f | f, f);
+
+                        // BitXOR:
+                        assert_eq!(t ^ f, t);
+                        assert_eq!(f ^ t, t);
+                        assert_eq!(t ^ t, f);
+                        assert_eq!(f ^ f, f);
+
+                        {
+                            // AndAssign:
+                            let mut v = f;
+                            v &= t;
+                            assert_eq!(v, f);
+                        }
+                        {
+                            // OrAssign:
+                            let mut v = f;
+                            v |= t;
+                            assert_eq!(v, t);
+                        }
+                        {
+                            // XORAssign:
+                            let mut v = f;
+                            v ^= t;
+                            assert_eq!(v, t);
+                        }
+                    }
+                }
+            }
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/ops/vector_neg.rs.html b/src/packed_simd/api/ops/vector_neg.rs.html new file mode 100644 index 000000000..54a42ecb8 --- /dev/null +++ b/src/packed_simd/api/ops/vector_neg.rs.html @@ -0,0 +1,89 @@ +vector_neg.rs.html -- source
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+//! Vertical (lane-wise) vector `Neg`.
+
+macro_rules! impl_ops_vector_neg {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident | $test_tt:tt) => {
+        impl crate::ops::Neg for $id {
+            type Output = Self;
+            #[inline]
+            fn neg(self) -> Self {
+                Self::splat(-1 as $elem_ty) * self
+            }
+        }
+        test_if!{
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _ops_vector_neg>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn neg() {
+                        let z = $id::splat(0 as $elem_ty);
+                        let o = $id::splat(1 as $elem_ty);
+                        let t = $id::splat(2 as $elem_ty);
+                        let f = $id::splat(4 as $elem_ty);
+
+                        let nz = $id::splat(-(0 as $elem_ty));
+                        let no = $id::splat(-(1 as $elem_ty));
+                        let nt = $id::splat(-(2 as $elem_ty));
+                        let nf = $id::splat(-(4 as $elem_ty));
+
+                        assert_eq!(-z, nz);
+                        assert_eq!(-o, no);
+                        assert_eq!(-t, nt);
+                        assert_eq!(-f, nf);
+
+                        assert_eq!(z, -nz);
+                        assert_eq!(o, -no);
+                        assert_eq!(t, -nt);
+                        assert_eq!(f, -nf);
+                    }
+                }
+            }
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/ops/vector_rotates.rs.html b/src/packed_simd/api/ops/vector_rotates.rs.html new file mode 100644 index 000000000..192104591 --- /dev/null +++ b/src/packed_simd/api/ops/vector_rotates.rs.html @@ -0,0 +1,183 @@ +vector_rotates.rs.html -- source
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+//! Vertical (lane-wise) vector rotates operations.
+#![allow(unused)]
+
+macro_rules! impl_ops_vector_rotates {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident | $test_tt:tt) => {
+        impl $id {
+            /// Shifts the bits of each lane to the left by the specified
+            /// amount in the corresponding lane of `n`, wrapping the
+            /// truncated bits to the end of the resulting integer.
+            ///
+            /// Note: this is neither the same operation as `<<` nor equivalent
+            /// to `slice::rotate_left`.
+            #[inline]
+            pub fn rotate_left(self, n: $id) -> $id {
+                const LANE_WIDTH: $elem_ty =
+                    crate::mem::size_of::<$elem_ty>() as $elem_ty * 8;
+                // Protect against undefined behavior for over-long bit shifts
+                let n = n % LANE_WIDTH;
+                (self << n) | (self >> ((LANE_WIDTH - n) % LANE_WIDTH))
+            }
+
+            /// Shifts the bits of each lane to the right by the specified
+            /// amount in the corresponding lane of `n`, wrapping the
+            /// truncated bits to the beginning of the resulting integer.
+            ///
+            /// Note: this is neither the same operation as `<<` nor equivalent
+            /// to `slice::rotate_left`.
+            #[inline]
+            pub fn rotate_right(self, n: $id) -> $id {
+                const LANE_WIDTH: $elem_ty =
+                    crate::mem::size_of::<$elem_ty>() as $elem_ty * 8;
+                // Protect against undefined behavior for over-long bit shifts
+                let n = n % LANE_WIDTH;
+                (self >> n) | (self << ((LANE_WIDTH - n) % LANE_WIDTH))
+            }
+        }
+
+        test_if!{
+            $test_tt:
+            paste::item! {
+                // FIXME:
+                // https://github.com/rust-lang-nursery/packed_simd/issues/75
+                #[cfg(not(any(
+                    target_arch = "s390x",
+                    target_arch = "sparc64",
+                )))]
+                pub mod [<$id _ops_vector_rotate>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn rotate_ops() {
+                        let z = $id::splat(0 as $elem_ty);
+                        let o = $id::splat(1 as $elem_ty);
+                        let t = $id::splat(2 as $elem_ty);
+                        let f = $id::splat(4 as $elem_ty);
+
+                        let max = $id::splat(
+                            (mem::size_of::<$elem_ty>() * 8 - 1) as $elem_ty);
+
+                        // rotate_right
+                        assert_eq!(z.rotate_right(z), z);
+                        assert_eq!(z.rotate_right(o), z);
+                        assert_eq!(z.rotate_right(t), z);
+
+                        assert_eq!(o.rotate_right(z), o);
+                        assert_eq!(t.rotate_right(z), t);
+                        assert_eq!(f.rotate_right(z), f);
+                        assert_eq!(f.rotate_right(max), f << 1);
+
+                        assert_eq!(o.rotate_right(o), o << max);
+                        assert_eq!(t.rotate_right(o), o);
+                        assert_eq!(t.rotate_right(t), o << max);
+                        assert_eq!(f.rotate_right(o), t);
+                        assert_eq!(f.rotate_right(t), o);
+
+                        // rotate_left
+                        assert_eq!(z.rotate_left(z), z);
+                        assert_eq!(o.rotate_left(z), o);
+                        assert_eq!(t.rotate_left(z), t);
+                        assert_eq!(f.rotate_left(z), f);
+                        assert_eq!(f.rotate_left(max), t);
+
+                        assert_eq!(o.rotate_left(o), t);
+                        assert_eq!(o.rotate_left(t), f);
+                        assert_eq!(t.rotate_left(o), f);
+                    }
+                }
+            }
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/ops/vector_shifts.rs.html b/src/packed_simd/api/ops/vector_shifts.rs.html new file mode 100644 index 000000000..b98e6f209 --- /dev/null +++ b/src/packed_simd/api/ops/vector_shifts.rs.html @@ -0,0 +1,217 @@ +vector_shifts.rs.html -- source
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+
+//! Vertical (lane-wise) vector-vector shifts operations.
+
+macro_rules! impl_ops_vector_shifts {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident | $test_tt:tt) => {
+        impl crate::ops::Shl<$id> for $id {
+            type Output = Self;
+            #[inline]
+            fn shl(self, other: Self) -> Self {
+                use crate::llvm::simd_shl;
+                unsafe { Simd(simd_shl(self.0, other.0)) }
+            }
+        }
+        impl crate::ops::Shr<$id> for $id {
+            type Output = Self;
+            #[inline]
+            fn shr(self, other: Self) -> Self {
+                use crate::llvm::simd_shr;
+                unsafe { Simd(simd_shr(self.0, other.0)) }
+            }
+        }
+        impl crate::ops::ShlAssign<$id> for $id {
+            #[inline]
+            fn shl_assign(&mut self, other: Self) {
+                *self = *self << other;
+            }
+        }
+        impl crate::ops::ShrAssign<$id> for $id {
+            #[inline]
+            fn shr_assign(&mut self, other: Self) {
+                *self = *self >> other;
+            }
+        }
+        test_if!{
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _ops_vector_shifts>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    #[cfg_attr(any(target_arch = "s390x", target_arch = "sparc64"),
+                               allow(unreachable_code,
+                                     unused_variables,
+                                     unused_mut)
+                    )]
+                    // ^^^ FIXME: https://github.com/rust-lang/rust/issues/55344
+                    fn ops_vector_shifts() {
+                        let z = $id::splat(0 as $elem_ty);
+                        let o = $id::splat(1 as $elem_ty);
+                        let t = $id::splat(2 as $elem_ty);
+                        let f = $id::splat(4 as $elem_ty);
+
+                        let max =$id::splat(
+                            (mem::size_of::<$elem_ty>() * 8 - 1) as $elem_ty
+                        );
+
+                        // shr
+                        assert_eq!(z >> z, z);
+                        assert_eq!(z >> o, z);
+                        assert_eq!(z >> t, z);
+                        assert_eq!(z >> t, z);
+
+                        #[cfg(any(target_arch = "s390x", target_arch = "sparc64"))] {
+                            // FIXME: rust produces bad codegen for shifts:
+                            // https://github.com/rust-lang-nursery/packed_simd/issues/13
+                            return;
+                        }
+
+                        assert_eq!(o >> z, o);
+                        assert_eq!(t >> z, t);
+                        assert_eq!(f >> z, f);
+                        assert_eq!(f >> max, z);
+
+                        assert_eq!(o >> o, z);
+                        assert_eq!(t >> o, o);
+                        assert_eq!(t >> t, z);
+                        assert_eq!(f >> o, t);
+                        assert_eq!(f >> t, o);
+                        assert_eq!(f >> max, z);
+
+                        // shl
+                        assert_eq!(z << z, z);
+                        assert_eq!(o << z, o);
+                        assert_eq!(t << z, t);
+                        assert_eq!(f << z, f);
+                        assert_eq!(f << max, z);
+
+                        assert_eq!(o << o, t);
+                        assert_eq!(o << t, f);
+                        assert_eq!(t << o, f);
+
+                        {
+                            // shr_assign
+                            let mut v = o;
+                            v >>= o;
+                            assert_eq!(v, z);
+                        }
+                        {
+                            // shl_assign
+                            let mut v = o;
+                            v <<= o;
+                            assert_eq!(v, t);
+                        }
+                    }
+                }
+            }
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/ptr.rs.html b/src/packed_simd/api/ptr.rs.html new file mode 100644 index 000000000..139cfda76 --- /dev/null +++ b/src/packed_simd/api/ptr.rs.html @@ -0,0 +1,11 @@ +ptr.rs.html -- source
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+//! Vector of pointers
+
+#[macro_use]
+mod gather_scatter;
+
+
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+
+//! Implements masked gather and scatters for vectors of pointers
+
+macro_rules! impl_ptr_read {
+    ([$elem_ty:ty; $elem_count:expr]: $id:ident, $mask_ty:ident
+     | $test_tt:tt) => {
+        impl<T> $id<T>
+        where
+            [T; $elem_count]: sealed::SimdArray,
+        {
+            /// Reads selected vector elements from memory.
+            ///
+            /// Instantiates a new vector by reading the values from `self` for
+            /// those lanes whose `mask` is `true`, and using the elements of
+            /// `value` otherwise.
+            ///
+            /// No memory is accessed for those lanes of `self` whose `mask` is
+            /// `false`.
+            ///
+            /// # Safety
+            ///
+            /// This method is unsafe because it dereferences raw pointers. The
+            /// pointers must be aligned to `mem::align_of::<T>()`.
+            #[inline]
+            pub unsafe fn read<M>(
+                self, mask: Simd<[M; $elem_count]>,
+                value: Simd<[T; $elem_count]>,
+            ) -> Simd<[T; $elem_count]>
+            where
+                M: sealed::Mask,
+                [M; $elem_count]: sealed::SimdArray,
+            {
+                use crate::llvm::simd_gather;
+                Simd(simd_gather(value.0, self.0, mask.0))
+            }
+        }
+
+        test_if! {
+            $test_tt:
+            paste::item! {
+                mod [<$id _read>] {
+                    use super::*;
+                    #[test]
+                    fn read() {
+                        let mut v = [0_i32; $elem_count];
+                        for i in 0..$elem_count {
+                            v[i] = i as i32;
+                        }
+
+                        let mut ptr = $id::<i32>::null();
+
+                        for i in 0..$elem_count {
+                            ptr = ptr.replace(i, unsafe {
+                                crate::mem::transmute(&v[i] as *const i32)
+                            });
+                        }
+
+                        // all mask elements are true:
+                        let mask = $mask_ty::splat(true);
+                        let def = Simd::<[i32; $elem_count]>::splat(42_i32);
+                        let r: Simd<[i32; $elem_count]> = unsafe {
+                            ptr.read(mask, def)
+                        };
+                        assert_eq!(
+                            r,
+                            Simd::<[i32; $elem_count]>::from_slice_unaligned(
+                                &v
+                            )
+                        );
+
+                        let mut mask = mask;
+                        for i in 0..$elem_count {
+                            if i % 2 != 0 {
+                                mask = mask.replace(i, false);
+                            }
+                        }
+
+                        // even mask elements are true, odd ones are false:
+                        let r: Simd<[i32; $elem_count]> = unsafe {
+                            ptr.read(mask, def)
+                        };
+                        let mut e = v;
+                        for i in 0..$elem_count {
+                            if i % 2 != 0 {
+                                e[i] = 42;
+                            }
+                        }
+                        assert_eq!(
+                            r,
+                            Simd::<[i32; $elem_count]>::from_slice_unaligned(
+                                &e
+                            )
+                        );
+
+                        // all mask elements are false:
+                        let mask = $mask_ty::splat(false);
+                        let def = Simd::<[i32; $elem_count]>::splat(42_i32);
+                        let r: Simd<[i32; $elem_count]> = unsafe {
+                            ptr.read(mask, def) }
+                        ;
+                        assert_eq!(r, def);
+                    }
+                }
+            }
+        }
+    };
+}
+
+macro_rules! impl_ptr_write {
+    ([$elem_ty:ty; $elem_count:expr]: $id:ident, $mask_ty:ident
+     | $test_tt:tt) => {
+        impl<T> $id<T>
+        where
+            [T; $elem_count]: sealed::SimdArray,
+        {
+            /// Writes selected vector elements to memory.
+            ///
+            /// Writes the lanes of `values` for which the mask is `true` to
+            /// their corresponding memory addresses in `self`.
+            ///
+            /// No memory is accessed for those lanes of `self` whose `mask` is
+            /// `false`.
+            ///
+            /// Overlapping memory addresses of `self` are written to in order
+            /// from the lest-significant to the most-significant element.
+            ///
+            /// # Safety
+            ///
+            /// This method is unsafe because it dereferences raw pointers. The
+            /// pointers must be aligned to `mem::align_of::<T>()`.
+            #[inline]
+            pub unsafe fn write<M>(
+                self, mask: Simd<[M; $elem_count]>,
+                value: Simd<[T; $elem_count]>,
+            ) where
+                M: sealed::Mask,
+                [M; $elem_count]: sealed::SimdArray,
+            {
+                use crate::llvm::simd_scatter;
+                simd_scatter(value.0, self.0, mask.0)
+            }
+        }
+
+        test_if! {
+            $test_tt:
+            paste::item! {
+                mod [<$id _write>] {
+                    use super::*;
+                    #[test]
+                    fn write() {
+                        // fourty_two = [42, 42, 42, ...]
+                        let fourty_two
+                            = Simd::<[i32; $elem_count]>::splat(42_i32);
+
+                        // This test will write to this array
+                        let mut arr = [0_i32; $elem_count];
+                        for i in 0..$elem_count {
+                            arr[i] = i as i32;
+                        }
+                        // arr = [0, 1, 2, ...]
+
+                        let mut ptr = $id::<i32>::null();
+                        for i in 0..$elem_count {
+                            ptr = ptr.replace(i, unsafe {
+                                crate::mem::transmute(arr.as_ptr().add(i))
+                            });
+                        }
+                        // ptr = [&arr[0], &arr[1], ...]
+
+                        // write `fourty_two` to all elements of `v`
+                        {
+                            let backup = arr;
+                            unsafe {
+                                ptr.write($mask_ty::splat(true), fourty_two)
+                            };
+                            assert_eq!(arr, [42_i32; $elem_count]);
+                            arr = backup;  // arr = [0, 1, 2, ...]
+                        }
+
+                        // write 42 to even elements of arr:
+                        {
+                            // set odd elements of the mask to false
+                            let mut mask = $mask_ty::splat(true);
+                            for i in 0..$elem_count {
+                                if i % 2 != 0 {
+                                    mask = mask.replace(i, false);
+                                }
+                            }
+                            // mask = [true, false, true, false, ...]
+
+                            // expected result r = [42, 1, 42, 3, 42, 5, ...]
+                            let mut r = arr;
+                            for i in 0..$elem_count {
+                                if i % 2 == 0 {
+                                    r[i] = 42;
+                                }
+                            }
+
+                            let backup = arr;
+                            unsafe { ptr.write(mask, fourty_two) };
+                            assert_eq!(arr, r);
+                            arr = backup;  // arr = [0, 1, 2, 3, ...]
+                        }
+
+                        // write 42 to no elements of arr
+                        {
+                            let backup = arr;
+                            unsafe {
+                                ptr.write($mask_ty::splat(false), fourty_two)
+                            };
+                            assert_eq!(arr, backup);
+                        }
+                    }
+                }
+            }
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/reductions.rs.html b/src/packed_simd/api/reductions.rs.html new file mode 100644 index 000000000..a325f4e3a --- /dev/null +++ b/src/packed_simd/api/reductions.rs.html @@ -0,0 +1,27 @@ +reductions.rs.html -- source
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+//! Reductions
+
+#[macro_use]
+mod float_arithmetic;
+#[macro_use]
+mod integer_arithmetic;
+#[macro_use]
+mod bitwise;
+#[macro_use]
+mod mask;
+#[macro_use]
+mod min_max;
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/reductions/bitwise.rs.html b/src/packed_simd/api/reductions/bitwise.rs.html new file mode 100644 index 000000000..573377fa9 --- /dev/null +++ b/src/packed_simd/api/reductions/bitwise.rs.html @@ -0,0 +1,305 @@ +bitwise.rs.html -- source
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+
+//! Implements portable horizontal bitwise vector reductions.
+#![allow(unused)]
+
+macro_rules! impl_reduction_bitwise {
+    (
+        [$elem_ty:ident; $elem_count:expr]:
+        $id:ident | $ielem_ty:ident | $test_tt:tt |
+        ($convert:expr) |
+        ($true:expr, $false:expr)
+    ) => {
+        impl $id {
+            /// Lane-wise bitwise `and` of the vector elements.
+            ///
+            /// Note: if the vector has one lane, the first element of the
+            /// vector is returned.
+            #[inline]
+            pub fn and(self) -> $elem_ty {
+                #[cfg(not(target_arch = "aarch64"))]
+                {
+                    use crate::llvm::simd_reduce_and;
+                    let r: $ielem_ty = unsafe { simd_reduce_and(self.0) };
+                    $convert(r)
+                }
+                #[cfg(target_arch = "aarch64")]
+                {
+                    // FIXME: broken on aarch64
+                    // https://github.com/rust-lang-nursery/packed_simd/issues/15
+                    let mut x = self.extract(0) as $elem_ty;
+                    for i in 1..$id::lanes() {
+                        x &= self.extract(i) as $elem_ty;
+                    }
+                    x
+                }
+            }
+
+            /// Lane-wise bitwise `or` of the vector elements.
+            ///
+            /// Note: if the vector has one lane, the first element of the
+            /// vector is returned.
+            #[inline]
+            pub fn or(self) -> $elem_ty {
+                #[cfg(not(target_arch = "aarch64"))]
+                {
+                    use crate::llvm::simd_reduce_or;
+                    let r: $ielem_ty = unsafe { simd_reduce_or(self.0) };
+                    $convert(r)
+                }
+                #[cfg(target_arch = "aarch64")]
+                {
+                    // FIXME: broken on aarch64
+                    // https://github.com/rust-lang-nursery/packed_simd/issues/15
+                    let mut x = self.extract(0) as $elem_ty;
+                    for i in 1..$id::lanes() {
+                        x |= self.extract(i) as $elem_ty;
+                    }
+                    x
+                }
+            }
+
+            /// Lane-wise bitwise `xor` of the vector elements.
+            ///
+            /// Note: if the vector has one lane, the first element of the
+            /// vector is returned.
+            #[inline]
+            pub fn xor(self) -> $elem_ty {
+                #[cfg(not(target_arch = "aarch64"))]
+                {
+                    use crate::llvm::simd_reduce_xor;
+                    let r: $ielem_ty = unsafe { simd_reduce_xor(self.0) };
+                    $convert(r)
+                }
+                #[cfg(target_arch = "aarch64")]
+                {
+                    // FIXME: broken on aarch64
+                    // https://github.com/rust-lang-nursery/packed_simd/issues/15
+                    let mut x = self.extract(0) as $elem_ty;
+                    for i in 1..$id::lanes() {
+                        x ^= self.extract(i) as $elem_ty;
+                    }
+                    x
+                }
+            }
+        }
+
+        test_if!{
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _reduction_bitwise>] {
+                    use super::*;
+
+                    #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn and() {
+                        let v = $id::splat($false);
+                        assert_eq!(v.and(), $false);
+                        let v = $id::splat($true);
+                        assert_eq!(v.and(), $true);
+                        let v = $id::splat($false);
+                        let v = v.replace(0, $true);
+                        if $id::lanes() > 1 {
+                            assert_eq!(v.and(), $false);
+                        } else {
+                            assert_eq!(v.and(), $true);
+                        }
+                        let v = $id::splat($true);
+                        let v = v.replace(0, $false);
+                        assert_eq!(v.and(), $false);
+
+                    }
+                    #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn or() {
+                        let v = $id::splat($false);
+                        assert_eq!(v.or(), $false);
+                        let v = $id::splat($true);
+                        assert_eq!(v.or(), $true);
+                        let v = $id::splat($false);
+                        let v = v.replace(0, $true);
+                        assert_eq!(v.or(), $true);
+                        let v = $id::splat($true);
+                        let v = v.replace(0, $false);
+                        if $id::lanes() > 1 {
+                            assert_eq!(v.or(), $true);
+                        } else {
+                            assert_eq!(v.or(), $false);
+                        }
+                    }
+                    #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn xor() {
+                        let v = $id::splat($false);
+                        assert_eq!(v.xor(), $false);
+                        let v = $id::splat($true);
+                        if $id::lanes() > 1 {
+                            assert_eq!(v.xor(), $false);
+                        } else {
+                            assert_eq!(v.xor(), $true);
+                        }
+                        let v = $id::splat($false);
+                        let v = v.replace(0, $true);
+                        assert_eq!(v.xor(), $true);
+                        let v = $id::splat($true);
+                        let v = v.replace(0, $false);
+                        if $id::lanes() > 1 {
+                            assert_eq!(v.xor(), $true);
+                        } else {
+                            assert_eq!(v.xor(), $false);
+                        }
+                    }
+                }
+            }
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/reductions/float_arithmetic.rs.html b/src/packed_simd/api/reductions/float_arithmetic.rs.html new file mode 100644 index 000000000..11c43fc9e --- /dev/null +++ b/src/packed_simd/api/reductions/float_arithmetic.rs.html @@ -0,0 +1,627 @@ +float_arithmetic.rs.html -- source
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+
+//! Implements portable horizontal float vector arithmetic reductions.
+
+macro_rules! impl_reduction_float_arithmetic {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident | $test_tt:tt) => {
+        impl $id {
+            /// Horizontal sum of the vector elements.
+            ///
+            /// The intrinsic performs a tree-reduction of the vector elements.
+            /// That is, for an 8 element vector:
+            ///
+            /// > ((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))
+            ///
+            /// If one of the vector element is `NaN` the reduction returns
+            /// `NaN`. The resulting `NaN` is not required to be equal to any
+            /// of the `NaN`s in the vector.
+            #[inline]
+            pub fn sum(self) -> $elem_ty {
+                #[cfg(not(target_arch = "aarch64"))]
+                {
+                    use crate::llvm::simd_reduce_add_ordered;
+                    unsafe { simd_reduce_add_ordered(self.0, 0 as $elem_ty) }
+                }
+                #[cfg(target_arch = "aarch64")]
+                {
+                    // FIXME: broken on AArch64
+                    // https://github.com/rust-lang-nursery/packed_simd/issues/15
+                    let mut x = self.extract(0) as $elem_ty;
+                    for i in 1..$id::lanes() {
+                        x += self.extract(i) as $elem_ty;
+                    }
+                    x
+                }
+            }
+
+            /// Horizontal product of the vector elements.
+            ///
+            /// The intrinsic performs a tree-reduction of the vector elements.
+            /// That is, for an 8 element vector:
+            ///
+            /// > ((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))
+            ///
+            /// If one of the vector element is `NaN` the reduction returns
+            /// `NaN`. The resulting `NaN` is not required to be equal to any
+            /// of the `NaN`s in the vector.
+            #[inline]
+            pub fn product(self) -> $elem_ty {
+                #[cfg(not(target_arch = "aarch64"))]
+                {
+                    use crate::llvm::simd_reduce_mul_ordered;
+                    unsafe { simd_reduce_mul_ordered(self.0, 1 as $elem_ty) }
+                }
+                #[cfg(target_arch = "aarch64")]
+                {
+                    // FIXME: broken on AArch64
+                    // https://github.com/rust-lang-nursery/packed_simd/issues/15
+                    let mut x = self.extract(0) as $elem_ty;
+                    for i in 1..$id::lanes() {
+                        x *= self.extract(i) as $elem_ty;
+                    }
+                    x
+                }
+            }
+        }
+
+        impl crate::iter::Sum for $id {
+            #[inline]
+            fn sum<I: Iterator<Item = $id>>(iter: I) -> $id {
+                iter.fold($id::splat(0.), crate::ops::Add::add)
+            }
+        }
+
+        impl crate::iter::Product for $id {
+            #[inline]
+            fn product<I: Iterator<Item = $id>>(iter: I) -> $id {
+                iter.fold($id::splat(1.), crate::ops::Mul::mul)
+            }
+        }
+
+        impl<'a> crate::iter::Sum<&'a $id> for $id {
+            #[inline]
+            fn sum<I: Iterator<Item = &'a $id>>(iter: I) -> $id {
+                iter.fold($id::splat(0.), |a, b| crate::ops::Add::add(a, *b))
+            }
+        }
+
+        impl<'a> crate::iter::Product<&'a $id> for $id {
+            #[inline]
+            fn product<I: Iterator<Item = &'a $id>>(iter: I) -> $id {
+                iter.fold($id::splat(1.), |a, b| crate::ops::Mul::mul(a, *b))
+            }
+        }
+
+        test_if! {
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _reduction_float_arith>] {
+                    use super::*;
+                    fn alternating(x: usize) -> $id {
+                        let mut v = $id::splat(1 as $elem_ty);
+                        for i in 0..$id::lanes() {
+                            if i % x == 0 {
+                                v = v.replace(i, 2 as $elem_ty);
+                            }
+                        }
+                        v
+                    }
+
+                    #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn sum() {
+                        let v = $id::splat(0 as $elem_ty);
+                        assert_eq!(v.sum(), 0 as $elem_ty);
+                        let v = $id::splat(1 as $elem_ty);
+                        assert_eq!(v.sum(), $id::lanes() as $elem_ty);
+                        let v = alternating(2);
+                        assert_eq!(
+                            v.sum(),
+                            ($id::lanes() / 2 + $id::lanes()) as $elem_ty
+                        );
+                    }
+                    #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn product() {
+                        let v = $id::splat(0 as $elem_ty);
+                        assert_eq!(v.product(), 0 as $elem_ty);
+                        let v = $id::splat(1 as $elem_ty);
+                        assert_eq!(v.product(), 1 as $elem_ty);
+                        let f = match $id::lanes() {
+                            64 => 16,
+                            32 => 8,
+                            16 => 4,
+                            _ => 2,
+                        };
+                        let v = alternating(f);
+                        assert_eq!(
+                            v.product(),
+                            (2_usize.pow(($id::lanes() / f) as u32)
+                             as $elem_ty)
+                        );
+                    }
+
+                    #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    #[allow(unreachable_code)]
+                    #[allow(unused_mut)]
+                    // ^^^ FIXME: https://github.com/rust-lang/rust/issues/55344
+                    fn sum_nan() {
+                        // FIXME: https://bugs.llvm.org/show_bug.cgi?id=36732
+                        // https://github.com/rust-lang-nursery/packed_simd/issues/6
+                        return;
+
+                        let n0 = crate::$elem_ty::NAN;
+                        let v0 = $id::splat(-3.0);
+                        for i in 0..$id::lanes() {
+                            let mut v = v0.replace(i, n0);
+                            // If the vector contains a NaN the result is NaN:
+                            assert!(
+                                v.sum().is_nan(),
+                                "nan at {} => {} | {:?}",
+                                i,
+                                v.sum(),
+                                v
+                            );
+                            for j in 0..i {
+                                v = v.replace(j, n0);
+                                assert!(v.sum().is_nan());
+                            }
+                        }
+                        let v = $id::splat(n0);
+                        assert!(v.sum().is_nan(), "all nans | {:?}", v);
+                    }
+
+                    #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    #[allow(unreachable_code)]
+                    #[allow(unused_mut)]
+                    // ^^^ FIXME: https://github.com/rust-lang/rust/issues/55344
+                    fn product_nan() {
+                        // FIXME: https://bugs.llvm.org/show_bug.cgi?id=36732
+                        // https://github.com/rust-lang-nursery/packed_simd/issues/6
+                        return;
+
+                        let n0 = crate::$elem_ty::NAN;
+                        let v0 = $id::splat(-3.0);
+                        for i in 0..$id::lanes() {
+                            let mut v = v0.replace(i, n0);
+                            // If the vector contains a NaN the result is NaN:
+                            assert!(
+                                v.product().is_nan(),
+                                "nan at {} => {} | {:?}",
+                                i,
+                                v.product(),
+                                v
+                            );
+                            for j in 0..i {
+                                v = v.replace(j, n0);
+                                assert!(v.product().is_nan());
+                            }
+                        }
+                        let v = $id::splat(n0);
+                        assert!(v.product().is_nan(), "all nans | {:?}", v);
+                    }
+
+                    #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    #[allow(unused, dead_code)]
+                    fn sum_roundoff() {
+                        // Performs a tree-reduction
+                        fn tree_reduce_sum(a: &[$elem_ty]) -> $elem_ty {
+                            assert!(!a.is_empty());
+                            if a.len() == 1 {
+                                a[0]
+                            } else if a.len() == 2 {
+                                a[0] + a[1]
+                            } else {
+                                let mid = a.len() / 2;
+                                let (left, right) = a.split_at(mid);
+                                tree_reduce_sum(left) + tree_reduce_sum(right)
+                            }
+                        }
+
+                        let mut start = crate::$elem_ty::EPSILON;
+                        let mut scalar_reduction = 0. as $elem_ty;
+
+                        let mut v = $id::splat(0. as $elem_ty);
+                        for i in 0..$id::lanes() {
+                            let c = if i % 2 == 0 { 1e3 } else { -1. };
+                            start *= 3.14 * c;
+                            scalar_reduction += start;
+                            v = v.replace(i, start);
+                        }
+                        let simd_reduction = v.sum();
+
+                        let mut a = [0. as $elem_ty; $id::lanes()];
+                        v.write_to_slice_unaligned(&mut a);
+                        let tree_reduction = tree_reduce_sum(&a);
+
+                        // tolerate 1 ULP difference:
+                        let red_bits = simd_reduction.to_bits();
+                        let tree_bits = tree_reduction.to_bits();
+                        assert!(
+                            if red_bits > tree_bits {
+                                red_bits - tree_bits
+                            } else {
+                                tree_bits - red_bits
+                            } < 2,
+                            "vector: {:?} | simd_reduction: {:?} | \
+                             tree_reduction: {} | scalar_reduction: {}",
+                            v,
+                            simd_reduction,
+                            tree_reduction,
+                            scalar_reduction
+                        );
+                    }
+
+                    #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    #[allow(unused, dead_code)]
+                    fn product_roundoff() {
+                        // Performs a tree-reduction
+                        fn tree_reduce_product(a: &[$elem_ty]) -> $elem_ty {
+                            assert!(!a.is_empty());
+                            if a.len() == 1 {
+                                a[0]
+                            } else if a.len() == 2 {
+                                a[0] * a[1]
+                            } else {
+                                let mid = a.len() / 2;
+                                let (left, right) = a.split_at(mid);
+                                tree_reduce_product(left)
+                                    * tree_reduce_product(right)
+                            }
+                        }
+
+                        let mut start = crate::$elem_ty::EPSILON;
+                        let mut scalar_reduction = 1. as $elem_ty;
+
+                        let mut v = $id::splat(0. as $elem_ty);
+                        for i in 0..$id::lanes() {
+                            let c = if i % 2 == 0 { 1e3 } else { -1. };
+                            start *= 3.14 * c;
+                            scalar_reduction *= start;
+                            v = v.replace(i, start);
+                        }
+                        let simd_reduction = v.product();
+
+                        let mut a = [0. as $elem_ty; $id::lanes()];
+                        v.write_to_slice_unaligned(&mut a);
+                        let tree_reduction = tree_reduce_product(&a);
+
+                        // tolerate 1 ULP difference:
+                        let red_bits = simd_reduction.to_bits();
+                        let tree_bits = tree_reduction.to_bits();
+                        assert!(
+                            if red_bits > tree_bits {
+                                red_bits - tree_bits
+                            } else {
+                                tree_bits - red_bits
+                            } < 2,
+                            "vector: {:?} | simd_reduction: {:?} | \
+                             tree_reduction: {} | scalar_reduction: {}",
+                            v,
+                            simd_reduction,
+                            tree_reduction,
+                            scalar_reduction
+                        );
+                    }
+                }
+            }
+        }
+    };
+}
+
+
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+//! Implements portable horizontal integer vector arithmetic reductions.
+
+macro_rules! impl_reduction_integer_arithmetic {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident | $ielem_ty:ident
+     | $test_tt:tt) => {
+        impl $id {
+            /// Horizontal wrapping sum of the vector elements.
+            ///
+            /// The intrinsic performs a tree-reduction of the vector elements.
+            /// That is, for an 8 element vector:
+            ///
+            /// > ((x0 + x1) + (x2 + x3)) + ((x4 + x5) + (x6 + x7))
+            ///
+            /// If an operation overflows it returns the mathematical result
+            /// modulo `2^n` where `n` is the number of times it overflows.
+            #[inline]
+            pub fn wrapping_sum(self) -> $elem_ty {
+                #[cfg(not(target_arch = "aarch64"))]
+                {
+                    use crate::llvm::simd_reduce_add_ordered;
+                    let v: $ielem_ty = unsafe {
+                        simd_reduce_add_ordered(self.0, 0 as $ielem_ty)
+                    };
+                    v as $elem_ty
+                }
+                #[cfg(target_arch = "aarch64")]
+                {
+                    // FIXME: broken on AArch64
+                    // https://github.com/rust-lang-nursery/packed_simd/issues/15
+                    let mut x = self.extract(0) as $elem_ty;
+                    for i in 1..$id::lanes() {
+                        x = x.wrapping_add(self.extract(i) as $elem_ty);
+                    }
+                    x
+                }
+            }
+
+            /// Horizontal wrapping product of the vector elements.
+            ///
+            /// The intrinsic performs a tree-reduction of the vector elements.
+            /// That is, for an 8 element vector:
+            ///
+            /// > ((x0 * x1) * (x2 * x3)) * ((x4 * x5) * (x6 * x7))
+            ///
+            /// If an operation overflows it returns the mathematical result
+            /// modulo `2^n` where `n` is the number of times it overflows.
+            #[inline]
+            pub fn wrapping_product(self) -> $elem_ty {
+                #[cfg(not(target_arch = "aarch64"))]
+                {
+                    use crate::llvm::simd_reduce_mul_ordered;
+                    let v: $ielem_ty = unsafe {
+                        simd_reduce_mul_ordered(self.0, 1 as $ielem_ty)
+                    };
+                    v as $elem_ty
+                }
+                #[cfg(target_arch = "aarch64")]
+                {
+                    // FIXME: broken on AArch64
+                    // https://github.com/rust-lang-nursery/packed_simd/issues/15
+                    let mut x = self.extract(0) as $elem_ty;
+                    for i in 1..$id::lanes() {
+                        x = x.wrapping_mul(self.extract(i) as $elem_ty);
+                    }
+                    x
+                }
+            }
+        }
+
+        impl crate::iter::Sum for $id {
+            #[inline]
+            fn sum<I: Iterator<Item = $id>>(iter: I) -> $id {
+                iter.fold($id::splat(0), crate::ops::Add::add)
+            }
+        }
+
+        impl crate::iter::Product for $id {
+            #[inline]
+            fn product<I: Iterator<Item = $id>>(iter: I) -> $id {
+                iter.fold($id::splat(1), crate::ops::Mul::mul)
+            }
+        }
+
+        impl<'a> crate::iter::Sum<&'a $id> for $id {
+            #[inline]
+            fn sum<I: Iterator<Item = &'a $id>>(iter: I) -> $id {
+                iter.fold($id::splat(0), |a, b| crate::ops::Add::add(a, *b))
+            }
+        }
+
+        impl<'a> crate::iter::Product<&'a $id> for $id {
+            #[inline]
+            fn product<I: Iterator<Item = &'a $id>>(iter: I) -> $id {
+                iter.fold($id::splat(1), |a, b| crate::ops::Mul::mul(a, *b))
+            }
+        }
+
+        test_if! {
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _reduction_int_arith>] {
+                    use super::*;
+
+                    fn alternating(x: usize) -> $id {
+                        let mut v = $id::splat(1 as $elem_ty);
+                        for i in 0..$id::lanes() {
+                            if i % x == 0 {
+                                v = v.replace(i, 2 as $elem_ty);
+                            }
+                        }
+                        v
+                    }
+
+                    #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn wrapping_sum() {
+                        let v = $id::splat(0 as $elem_ty);
+                        assert_eq!(v.wrapping_sum(), 0 as $elem_ty);
+                        let v = $id::splat(1 as $elem_ty);
+                        assert_eq!(v.wrapping_sum(), $id::lanes() as $elem_ty);
+                        let v = alternating(2);
+                        if $id::lanes() > 1 {
+                            assert_eq!(
+                                v.wrapping_sum(),
+                                ($id::lanes() / 2 + $id::lanes()) as $elem_ty
+                            );
+                        } else {
+                            assert_eq!(
+                                v.wrapping_sum(),
+                                2 as $elem_ty
+                            );
+                        }
+                    }
+                    #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn wrapping_sum_overflow() {
+                        let start = $elem_ty::max_value()
+                            - ($id::lanes() as $elem_ty / 2);
+
+                        let v = $id::splat(start as $elem_ty);
+                        let vwrapping_sum = v.wrapping_sum();
+
+                        let mut wrapping_sum = start;
+                        for _ in 1..$id::lanes() {
+                            wrapping_sum = wrapping_sum.wrapping_add(start);
+                        }
+                        assert_eq!(wrapping_sum, vwrapping_sum, "v = {:?}", v);
+                    }
+
+                    #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn wrapping_product() {
+                        let v = $id::splat(0 as $elem_ty);
+                        assert_eq!(v.wrapping_product(), 0 as $elem_ty);
+                        let v = $id::splat(1 as $elem_ty);
+                        assert_eq!(v.wrapping_product(), 1 as $elem_ty);
+                        let f = match $id::lanes() {
+                            64 => 16,
+                            32 => 8,
+                            16 => 4,
+                            _ => 2,
+                        };
+                        let v = alternating(f);
+                        if $id::lanes() > 1 {
+                            assert_eq!(
+                                v.wrapping_product(),
+                                (2_usize.pow(($id::lanes() / f) as u32)
+                                 as $elem_ty)
+                            );
+                        } else {
+                            assert_eq!(
+                                v.wrapping_product(),
+                                2 as $elem_ty
+                            );
+                        }
+                    }
+
+                    #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn wrapping_product_overflow() {
+                        let start = $elem_ty::max_value()
+                            - ($id::lanes() as $elem_ty / 2);
+
+                        let v = $id::splat(start as $elem_ty);
+                        let vmul = v.wrapping_product();
+
+                        let mut mul = start;
+                        for _ in 1..$id::lanes() {
+                            mul = mul.wrapping_mul(start);
+                        }
+                        assert_eq!(mul, vmul, "v = {:?}", v);
+                    }
+                }
+            }
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/reductions/mask.rs.html b/src/packed_simd/api/reductions/mask.rs.html new file mode 100644 index 000000000..29f270a74 --- /dev/null +++ b/src/packed_simd/api/reductions/mask.rs.html @@ -0,0 +1,181 @@ +mask.rs.html -- source
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+//! Implements portable horizontal mask reductions.
+
+macro_rules! impl_reduction_mask {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident | $test_tt:tt) => {
+        impl $id {
+            /// Are `all` vector lanes `true`?
+            #[inline]
+            pub fn all(self) -> bool {
+                unsafe { crate::codegen::reductions::mask::All::all(self) }
+            }
+            /// Is `any` vector lane `true`?
+            #[inline]
+            pub fn any(self) -> bool {
+                unsafe { crate::codegen::reductions::mask::Any::any(self) }
+            }
+            /// Are `all` vector lanes `false`?
+            #[inline]
+            pub fn none(self) -> bool {
+                !self.any()
+            }
+        }
+
+        test_if! {
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _reduction>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn all() {
+                        let a = $id::splat(true);
+                        assert!(a.all());
+                        let a = $id::splat(false);
+                        assert!(!a.all());
+
+                        if $id::lanes() > 1 {
+                            for i in 0..$id::lanes() {
+                                let mut a = $id::splat(true);
+                                a = a.replace(i, false);
+                                assert!(!a.all());
+                                let mut a = $id::splat(false);
+                                a = a.replace(i, true);
+                                assert!(!a.all());
+                            }
+                        }
+                    }
+                    #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn any() {
+                        let a = $id::splat(true);
+                        assert!(a.any());
+                        let a = $id::splat(false);
+                        assert!(!a.any());
+
+                        if $id::lanes() > 1 {
+                            for i in 0..$id::lanes() {
+                                let mut a = $id::splat(true);
+                                a = a.replace(i, false);
+                                assert!(a.any());
+                                let mut a = $id::splat(false);
+                                a = a.replace(i, true);
+                                assert!(a.any());
+                            }
+                        }
+                    }
+                    #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn none() {
+                        let a = $id::splat(true);
+                        assert!(!a.none());
+                        let a = $id::splat(false);
+                        assert!(a.none());
+
+                        if $id::lanes() > 1 {
+                            for i in 0..$id::lanes() {
+                                let mut a = $id::splat(true);
+                                a = a.replace(i, false);
+                                assert!(!a.none());
+                                let mut a = $id::splat(false);
+                                a = a.replace(i, true);
+                                assert!(!a.none());
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/reductions/min_max.rs.html b/src/packed_simd/api/reductions/min_max.rs.html new file mode 100644 index 000000000..661f31d41 --- /dev/null +++ b/src/packed_simd/api/reductions/min_max.rs.html @@ -0,0 +1,757 @@ +min_max.rs.html -- source
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+
+//! Implements portable horizontal vector min/max reductions.
+
+macro_rules! impl_reduction_min_max {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident
+     | $ielem_ty:ident | $test_tt:tt) => {
+        impl $id {
+            /// Largest vector element value.
+            #[inline]
+            pub fn max_element(self) -> $elem_ty {
+                #[cfg(not(any(
+                    target_arch = "aarch64",
+                    target_arch = "arm",
+                    target_arch = "powerpc64",
+                    target_arch = "wasm32",
+                )))]
+                {
+                    use crate::llvm::simd_reduce_max;
+                    let v: $ielem_ty = unsafe { simd_reduce_max(self.0) };
+                    v as $elem_ty
+                }
+                #[cfg(any(
+                    target_arch = "aarch64",
+                    target_arch = "arm",
+                    target_arch = "powerpc64",
+                    target_arch = "wasm32",
+                ))]
+                {
+                    // FIXME: broken on AArch64
+                    // https://github.com/rust-lang-nursery/packed_simd/issues/15
+                    // FIXME: broken on WASM32
+                    // https://github.com/rust-lang-nursery/packed_simd/issues/91
+                    let mut x = self.extract(0);
+                    for i in 1..$id::lanes() {
+                        x = x.max(self.extract(i));
+                    }
+                    x
+                }
+            }
+
+            /// Smallest vector element value.
+            #[inline]
+            pub fn min_element(self) -> $elem_ty {
+                #[cfg(not(any(
+                    target_arch = "aarch64",
+                    target_arch = "arm",
+                    all(target_arch = "x86", not(target_feature = "sse2")),
+                    target_arch = "powerpc64",
+                    target_arch = "wasm32",
+                ),))]
+                {
+                    use crate::llvm::simd_reduce_min;
+                    let v: $ielem_ty = unsafe { simd_reduce_min(self.0) };
+                    v as $elem_ty
+                }
+                #[cfg(any(
+                    target_arch = "aarch64",
+                    target_arch = "arm",
+                    all(target_arch = "x86", not(target_feature = "sse2")),
+                    target_arch = "powerpc64",
+                    target_arch = "wasm32",
+                ))]
+                {
+                    // FIXME: broken on AArch64
+                    // https://github.com/rust-lang-nursery/packed_simd/issues/15
+                    // FIXME: broken on i586-unknown-linux-gnu
+                    // https://github.com/rust-lang-nursery/packed_simd/issues/22
+                    // FIXME: broken on WASM32
+                    // https://github.com/rust-lang-nursery/packed_simd/issues/91
+                    let mut x = self.extract(0);
+                    for i in 1..$id::lanes() {
+                        x = x.min(self.extract(i));
+                    }
+                    x
+                }
+            }
+        }
+        test_if! {$test_tt:
+        paste::item! {
+            pub mod [<$id _reduction_min_max>] {
+                use super::*;
+                #[cfg_attr(not(target_arch = "wasm32"), test)]
+                #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                pub fn max_element() {
+                    let v = $id::splat(0 as $elem_ty);
+                    assert_eq!(v.max_element(), 0 as $elem_ty);
+                    if $id::lanes() > 1 {
+                        let v = v.replace(1, 1 as $elem_ty);
+                        assert_eq!(v.max_element(), 1 as $elem_ty);
+                    }
+                    let v = v.replace(0, 2 as $elem_ty);
+                    assert_eq!(v.max_element(), 2 as $elem_ty);
+                }
+
+                #[cfg_attr(not(target_arch = "wasm32"), test)]
+                #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                pub fn min_element() {
+                    let v = $id::splat(0 as $elem_ty);
+                    assert_eq!(v.min_element(), 0 as $elem_ty);
+                    if $id::lanes() > 1 {
+                        let v = v.replace(1, 1 as $elem_ty);
+                        assert_eq!(v.min_element(), 0 as $elem_ty);
+                    }
+                    let v = $id::splat(1 as $elem_ty);
+                    let v = v.replace(0, 2 as $elem_ty);
+                    if $id::lanes() > 1 {
+                        assert_eq!(v.min_element(), 1 as $elem_ty);
+                    } else {
+                        assert_eq!(v.min_element(), 2 as $elem_ty);
+                    }
+                    if $id::lanes() > 1 {
+                        let v = $id::splat(2 as $elem_ty);
+                        let v = v.replace(1, 1 as $elem_ty);
+                        assert_eq!(v.min_element(), 1 as $elem_ty);
+                    }
+                }
+            }
+        }
+        }
+    };
+}
+
+macro_rules! test_reduction_float_min_max {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident | $test_tt:tt) => {
+        test_if!{
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _reduction_min_max_nan>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn min_element_test() {
+                        let n = crate::$elem_ty::NAN;
+
+                        assert_eq!(n.min(-3.), -3.);
+                        assert_eq!((-3. as $elem_ty).min(n), -3.);
+
+                        let v0 = $id::splat(-3.);
+
+                        let target_with_broken_last_lane_nan = !cfg!(any(
+                            target_arch = "arm", target_arch = "aarch64",
+                            all(target_arch = "x86",
+                                not(target_feature = "sse2")
+                            ),
+                            target_arch = "powerpc64",
+                            target_arch = "wasm32",
+                        ));
+
+                        // The vector is initialized to `-3.`s: [-3, -3, -3, -3]
+                        for i in 0..$id::lanes() {
+                            // We replace the i-th element of the vector with
+                            // `NaN`: [-3, -3, -3, NaN]
+                            let mut v = v0.replace(i, n);
+
+                            // If the NaN is in the last place, the LLVM
+                            // implementation of these methods is broken on some
+                            // targets:
+                            if i == $id::lanes() - 1 &&
+                                target_with_broken_last_lane_nan {
+                                // FIXME:
+                                // https://github.com/rust-lang-nursery/packed_simd/issues/5
+                                //
+                                // If there is a NaN, the result should always
+                                // the smallest element, but currently when the
+                                // last element is NaN the current
+                                // implementation incorrectly returns NaN.
+                                //
+                                // The targets mentioned above use different
+                                // codegen that produces the correct result.
+                                //
+                                // These asserts detect if this behavior changes
+                                    assert!(v.min_element().is_nan(),
+                                            // FIXME: ^^^ should be -3.
+                                            "[A]: nan at {} => {} | {:?}",
+                                            i, v.min_element(), v);
+
+                                // If we replace all the elements in the vector
+                                // up-to the `i-th` lane with `NaN`s, the result
+                                // is still always `-3.` unless all elements of
+                                // the vector are `NaN`s:
+                                //
+                                // This is also broken:
+                                for j in 0..i {
+                                    v = v.replace(j, n);
+                                    assert!(v.min_element().is_nan(),
+                                            // FIXME: ^^^ should be -3.
+                                            "[B]: nan at {} => {} | {:?}",
+                                            i, v.min_element(), v);
+                                }
+
+                                // We are done here, since we were in the last
+                                // lane which is the last iteration of the loop.
+                                break
+                            }
+
+                            // We are not in the last lane, and there is only
+                            // one `NaN` in the vector.
+
+                            // If the vector has one lane, the result is `NaN`:
+                            if $id::lanes() == 1 {
+                                assert!(v.min_element().is_nan(),
+                                        "[C]: all nans | v={:?} | min={} | \
+                                         is_nan: {}",
+                                        v, v.min_element(),
+                                        v.min_element().is_nan()
+                                );
+
+                                // And we are done, since the vector only has
+                                // one lane anyways.
+                                break;
+                            }
+
+                            // The vector has more than one lane, since there is
+                            // only one `NaN` in the vector, the result is
+                            // always `-3`.
+                            assert_eq!(v.min_element(), -3.,
+                                       "[D]: nan at {} => {} | {:?}",
+                                       i, v.min_element(), v);
+
+                            // If we replace all the elements in the vector
+                            // up-to the `i-th` lane with `NaN`s, the result is
+                            // still always `-3.` unless all elements of the
+                            // vector are `NaN`s:
+                            for j in 0..i {
+                                v = v.replace(j, n);
+
+                                if i == $id::lanes() - 1 && j == i - 1 {
+                                    // All elements of the vector are `NaN`s,
+                                    // therefore the result is NaN as well.
+                                    //
+                                    // Note: the #lanes of the vector is > 1, so
+                                    // "i - 1" does not overflow.
+                                    assert!(v.min_element().is_nan(),
+                                            "[E]: all nans | v={:?} | min={} | \
+                                             is_nan: {}",
+                                            v, v.min_element(),
+                                            v.min_element().is_nan());
+                                } else {
+                                    // There are non-`NaN` elements in the
+                                    // vector, therefore the result is `-3.`:
+                                    assert_eq!(v.min_element(), -3.,
+                                               "[F]: nan at {} => {} | {:?}",
+                                               i, v.min_element(), v);
+                                }
+                            }
+                        }
+
+                        // If the vector contains all NaNs the result is NaN:
+                        assert!($id::splat(n).min_element().is_nan(),
+                                "all nans | v={:?} | min={} | is_nan: {}",
+                                $id::splat(n), $id::splat(n).min_element(),
+                                $id::splat(n).min_element().is_nan());
+                    }
+                    #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn max_element_test() {
+                        let n = crate::$elem_ty::NAN;
+
+                        assert_eq!(n.max(-3.), -3.);
+                        assert_eq!((-3. as $elem_ty).max(n), -3.);
+
+                        let v0 = $id::splat(-3.);
+
+                        let target_with_broken_last_lane_nan = !cfg!(any(
+                            target_arch = "arm", target_arch = "aarch64",
+                            target_arch = "powerpc64", target_arch = "wasm32",
+                        ));
+
+                        // The vector is initialized to `-3.`s: [-3, -3, -3, -3]
+                        for i in 0..$id::lanes() {
+                            // We replace the i-th element of the vector with
+                            // `NaN`: [-3, -3, -3, NaN]
+                            let mut v = v0.replace(i, n);
+
+                            // If the NaN is in the last place, the LLVM
+                            // implementation of these methods is broken on some
+                            // targets:
+                            if i == $id::lanes() - 1 &&
+                              target_with_broken_last_lane_nan {
+                                // FIXME:
+                                // https://github.com/rust-lang-nursery/packed_simd/issues/5
+                                //
+                                // If there is a NaN, the result should
+                                // always the largest element, but currently
+                                // when the last element is NaN the current
+                                // implementation incorrectly returns NaN.
+                                //
+                                // The targets mentioned above use different
+                                // codegen that produces the correct result.
+                                //
+                                // These asserts detect if this behavior
+                                // changes
+                                assert!(v.max_element().is_nan(),
+                                        // FIXME: ^^^ should be -3.
+                                        "[A]: nan at {} => {} | {:?}",
+                                        i, v.max_element(), v);
+
+                                // If we replace all the elements in the vector
+                                // up-to the `i-th` lane with `NaN`s, the result
+                                // is still always `-3.` unless all elements of
+                                // the vector are `NaN`s:
+                                //
+                                // This is also broken:
+                                for j in 0..i {
+                                    v = v.replace(j, n);
+                                    assert!(v.max_element().is_nan(),
+                                            // FIXME: ^^^ should be -3.
+                                            "[B]: nan at {} => {} | {:?}",
+                                            i, v.max_element(), v);
+                                }
+
+                                // We are done here, since we were in the last
+                                // lane which is the last iteration of the loop.
+                                break
+                            }
+
+                            // We are not in the last lane, and there is only
+                            // one `NaN` in the vector.
+
+                            // If the vector has one lane, the result is `NaN`:
+                            if $id::lanes() == 1 {
+                                assert!(v.max_element().is_nan(),
+                                        "[C]: all nans | v={:?} | min={} | \
+                                         is_nan: {}",
+                                        v, v.max_element(),
+                                        v.max_element().is_nan());
+
+                                // And we are done, since the vector only has
+                                // one lane anyways.
+                                break;
+                            }
+
+                            // The vector has more than one lane, since there is
+                            // only one `NaN` in the vector, the result is
+                            // always `-3`.
+                            assert_eq!(v.max_element(), -3.,
+                                       "[D]: nan at {} => {} | {:?}",
+                                       i, v.max_element(), v);
+
+                            // If we replace all the elements in the vector
+                            // up-to the `i-th` lane with `NaN`s, the result is
+                            // still always `-3.` unless all elements of the
+                            // vector are `NaN`s:
+                            for j in 0..i {
+                                v = v.replace(j, n);
+
+                                if i == $id::lanes() - 1 && j == i - 1 {
+                                    // All elements of the vector are `NaN`s,
+                                    // therefore the result is NaN as well.
+                                    //
+                                    // Note: the #lanes of the vector is > 1, so
+                                    // "i - 1" does not overflow.
+                                    assert!(v.max_element().is_nan(),
+                                            "[E]: all nans | v={:?} | max={} | \
+                                             is_nan: {}",
+                                            v, v.max_element(),
+                                            v.max_element().is_nan());
+                                } else {
+                                    // There are non-`NaN` elements in the
+                                    // vector, therefore the result is `-3.`:
+                                    assert_eq!(v.max_element(), -3.,
+                                               "[F]: nan at {} => {} | {:?}",
+                                               i, v.max_element(), v);
+                                }
+                            }
+                        }
+
+                        // If the vector contains all NaNs the result is NaN:
+                        assert!($id::splat(n).max_element().is_nan(),
+                                "all nans | v={:?} | max={} | is_nan: {}",
+                                $id::splat(n), $id::splat(n).max_element(),
+                                $id::splat(n).max_element().is_nan());
+                    }
+                }
+            }
+        }
+    }
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/select.rs.html b/src/packed_simd/api/select.rs.html new file mode 100644 index 000000000..fb55462d9 --- /dev/null +++ b/src/packed_simd/api/select.rs.html @@ -0,0 +1,153 @@ +select.rs.html -- source
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+//! Implements mask's `select`.
+
+/// Implements mask select method
+macro_rules! impl_select {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident | $test_tt:tt) => {
+        impl $id {
+            /// Selects elements of `a` and `b` using mask.
+            ///
+            /// The lanes of the result for which the mask is `true` contain
+            /// the values of `a`. The remaining lanes contain the values of
+            /// `b`.
+            #[inline]
+            pub fn select<T>(self, a: Simd<T>, b: Simd<T>) -> Simd<T>
+            where
+                T: sealed::SimdArray<
+                    NT = <[$elem_ty; $elem_count] as sealed::SimdArray>::NT,
+                >,
+            {
+                use crate::llvm::simd_select;
+                Simd(unsafe { simd_select(self.0, a.0, b.0) })
+            }
+        }
+
+        test_select!(bool, $id, $id, (false, true) | $test_tt);
+    };
+}
+
+macro_rules! test_select {
+    (
+        $elem_ty:ident,
+        $mask_ty:ident,
+        $vec_ty:ident,($small:expr, $large:expr) |
+        $test_tt:tt
+    ) => {
+        test_if! {
+            $test_tt:
+            paste::item! {
+                pub mod [<$vec_ty _select>] {
+                    use super::*;
+
+                    #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn select() {
+                        let o = $small as $elem_ty;
+                        let t = $large as $elem_ty;
+
+                        let a = $vec_ty::splat(o);
+                        let b = $vec_ty::splat(t);
+                        let m = a.lt(b);
+                        assert_eq!(m.select(a, b), a);
+
+                        let m = b.lt(a);
+                        assert_eq!(m.select(b, a), a);
+
+                        let mut c = a;
+                        let mut d = b;
+                        let mut m_e = $mask_ty::splat(false);
+                        for i in 0..$vec_ty::lanes() {
+                            if i % 2 == 0 {
+                                let c_tmp = c.extract(i);
+                                c = c.replace(i, d.extract(i));
+                                d = d.replace(i, c_tmp);
+                            } else {
+                                m_e = m_e.replace(i, true);
+                            }
+                        }
+
+                        let m = c.lt(d);
+                        assert_eq!(m_e, m);
+                        assert_eq!(m.select(c, d), a);
+                    }
+                }
+            }
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/shuffle.rs.html b/src/packed_simd/api/shuffle.rs.html new file mode 100644 index 000000000..4dee2afaa --- /dev/null +++ b/src/packed_simd/api/shuffle.rs.html @@ -0,0 +1,383 @@ +shuffle.rs.html -- source
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+
+//! Implements portable vector shuffles with immediate indices.
+
+// FIXME: comprehensive tests
+// https://github.com/rust-lang-nursery/packed_simd/issues/20
+
+/// Shuffles vector elements.
+///
+/// This macro returns a new vector that contains a shuffle of the elements in
+/// one (`shuffle!(vec, [indices...])`) or two (`shuffle!(vec0, vec1,
+/// [indices...])`) input vectors.
+///
+/// The type of `vec0` and `vec1` must be equal, and the element type of the
+/// resulting vector is the element type of the input vector.
+///
+/// The number of `indices` must be a power-of-two in range `[0, 64)`, since
+/// currently, the largest vector supported by the library has 64 lanes. The
+/// length of the resulting vector equals the number of indices provided.
+///
+/// The indices must be in range `[0, M * N)` where `M` is the number of input
+/// vectors (`1` or `2`) and `N` is the number of lanes of the input vectors.
+/// The indices `i` in range `[0, N)` refer to the `i`-th element of `vec0`,
+/// while the indices in range `[N, 2*N)` refer to the `i - N`-th element of
+/// `vec1`.
+///
+/// # Examples
+///
+/// Shuffling elements of two vectors:
+///
+/// ```
+/// # #[macro_use]
+/// # extern crate packed_simd;
+/// # use packed_simd::*;
+/// # fn main() {
+/// // Shuffle allows reordering the elements:
+/// let x = i32x4::new(1, 2, 3, 4);
+/// let y = i32x4::new(5, 6, 7, 8);
+/// let r = shuffle!(x, y, [4, 0, 5, 1]);
+/// assert_eq!(r, i32x4::new(5, 1, 6, 2));
+///
+/// // The resulting vector can als be smaller than the input:
+/// let r = shuffle!(x, y, [1, 6]);
+/// assert_eq!(r, i32x2::new(2, 7));
+///
+/// // Or larger:
+/// let r = shuffle!(x, y, [1, 3, 4, 2, 1, 7, 2, 2]);
+/// assert_eq!(r, i32x8::new(2, 4, 5, 3, 2, 8, 3, 3));
+/// // At most 2 * the number of lanes in the input vector.
+/// # }
+/// ```
+///
+/// Shuffling elements of one vector:
+///
+/// ```
+/// # #[macro_use]
+/// # extern crate packed_simd;
+/// # use packed_simd::*;
+/// # fn main() {
+/// // Shuffle allows reordering the elements of a vector:
+/// let x = i32x4::new(1, 2, 3, 4);
+/// let r = shuffle!(x, [2, 1, 3, 0]);
+/// assert_eq!(r, i32x4::new(3, 2, 4, 1));
+///
+/// // The resulting vector can be smaller than the input:
+/// let r = shuffle!(x, [1, 3]);
+/// assert_eq!(r, i32x2::new(2, 4));
+///
+/// // Equal:
+/// let r = shuffle!(x, [1, 3, 2, 0]);
+/// assert_eq!(r, i32x4::new(2, 4, 3, 1));
+///
+/// // Or larger:
+/// let r = shuffle!(x, [1, 3, 2, 2, 1, 3, 2, 2]);
+/// assert_eq!(r, i32x8::new(2, 4, 3, 3, 2, 4, 3, 3));
+/// // At most 2 * the number of lanes in the input vector.
+/// # }
+/// ```
+#[macro_export]
+macro_rules! shuffle {
+    ($vec0:expr, $vec1:expr, [$l0:expr, $l1:expr]) => {{
+        #[allow(unused_unsafe)]
+        unsafe {
+            $crate::Simd($crate::__shuffle_vector2(
+                $vec0.0,
+                $vec1.0,
+                [$l0, $l1],
+            ))
+        }
+    }};
+    ($vec0:expr, $vec1:expr, [$l0:expr, $l1:expr, $l2:expr, $l3:expr]) => {{
+        #[allow(unused_unsafe)]
+        unsafe {
+            $crate::Simd($crate::__shuffle_vector4(
+                $vec0.0,
+                $vec1.0,
+                [$l0, $l1, $l2, $l3],
+            ))
+        }
+    }};
+    ($vec0:expr, $vec1:expr,
+     [$l0:expr, $l1:expr, $l2:expr, $l3:expr,
+      $l4:expr, $l5:expr, $l6:expr, $l7:expr]) => {{
+        #[allow(unused_unsafe)]
+        unsafe {
+            $crate::Simd($crate::__shuffle_vector8(
+                $vec0.0,
+                $vec1.0,
+                [$l0, $l1, $l2, $l3, $l4, $l5, $l6, $l7],
+            ))
+        }
+    }};
+    ($vec0:expr, $vec1:expr,
+     [$l0:expr, $l1:expr, $l2:expr, $l3:expr,
+      $l4:expr, $l5:expr, $l6:expr, $l7:expr,
+      $l8:expr, $l9:expr, $l10:expr, $l11:expr,
+      $l12:expr, $l13:expr, $l14:expr, $l15:expr]) => {{
+        #[allow(unused_unsafe)]
+        unsafe {
+            $crate::Simd($crate::__shuffle_vector16(
+                $vec0.0,
+                $vec1.0,
+                [
+                    $l0, $l1, $l2, $l3, $l4, $l5, $l6, $l7, $l8, $l9, $l10,
+                    $l11, $l12, $l13, $l14, $l15,
+                ],
+            ))
+        }
+    }};
+    ($vec0:expr, $vec1:expr,
+     [$l0:expr, $l1:expr, $l2:expr, $l3:expr,
+      $l4:expr, $l5:expr, $l6:expr, $l7:expr,
+      $l8:expr, $l9:expr, $l10:expr, $l11:expr,
+      $l12:expr, $l13:expr, $l14:expr, $l15:expr,
+      $l16:expr, $l17:expr, $l18:expr, $l19:expr,
+      $l20:expr, $l21:expr, $l22:expr, $l23:expr,
+      $l24:expr, $l25:expr, $l26:expr, $l27:expr,
+      $l28:expr, $l29:expr, $l30:expr, $l31:expr]) => {{
+        #[allow(unused_unsafe)]
+        unsafe {
+            $crate::Simd($crate::__shuffle_vector32(
+                $vec0.0,
+                $vec1.0,
+                [
+                    $l0, $l1, $l2, $l3, $l4, $l5, $l6, $l7, $l8, $l9, $l10,
+                    $l11, $l12, $l13, $l14, $l15, $l16, $l17, $l18, $l19,
+                    $l20, $l21, $l22, $l23, $l24, $l25, $l26, $l27, $l28,
+                    $l29, $l30, $l31,
+                ],
+            ))
+        }
+    }};
+    ($vec0:expr, $vec1:expr,
+     [$l0:expr, $l1:expr, $l2:expr, $l3:expr,
+      $l4:expr, $l5:expr, $l6:expr, $l7:expr,
+      $l8:expr, $l9:expr, $l10:expr, $l11:expr,
+      $l12:expr, $l13:expr, $l14:expr, $l15:expr,
+      $l16:expr, $l17:expr, $l18:expr, $l19:expr,
+      $l20:expr, $l21:expr, $l22:expr, $l23:expr,
+      $l24:expr, $l25:expr, $l26:expr, $l27:expr,
+      $l28:expr, $l29:expr, $l30:expr, $l31:expr,
+      $l32:expr, $l33:expr, $l34:expr, $l35:expr,
+      $l36:expr, $l37:expr, $l38:expr, $l39:expr,
+      $l40:expr, $l41:expr, $l42:expr, $l43:expr,
+      $l44:expr, $l45:expr, $l46:expr, $l47:expr,
+      $l48:expr, $l49:expr, $l50:expr, $l51:expr,
+      $l52:expr, $l53:expr, $l54:expr, $l55:expr,
+      $l56:expr, $l57:expr, $l58:expr, $l59:expr,
+      $l60:expr, $l61:expr, $l62:expr, $l63:expr]) => {{
+        #[allow(unused_unsafe)]
+        unsafe {
+            $crate::Simd($crate::__shuffle_vector64(
+                $vec0.0,
+                $vec1.0,
+                [
+                    $l0, $l1, $l2, $l3, $l4, $l5, $l6, $l7, $l8, $l9, $l10,
+                    $l11, $l12, $l13, $l14, $l15, $l16, $l17, $l18, $l19,
+                    $l20, $l21, $l22, $l23, $l24, $l25, $l26, $l27, $l28,
+                    $l29, $l30, $l31, $l32, $l33, $l34, $l35, $l36, $l37,
+                    $l38, $l39, $l40, $l41, $l42, $l43, $l44, $l45, $l46,
+                    $l47, $l48, $l49, $l50, $l51, $l52, $l53, $l54, $l55,
+                    $l56, $l57, $l58, $l59, $l60, $l61, $l62, $l63,
+                ],
+            ))
+        }
+     }};
+    ($vec:expr, [$($l:expr),*]) => {
+        match $vec {
+            v => shuffle!(v, v, [$($l),*])
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/shuffle1_dyn.rs.html b/src/packed_simd/api/shuffle1_dyn.rs.html new file mode 100644 index 000000000..6cb2cbe0c --- /dev/null +++ b/src/packed_simd/api/shuffle1_dyn.rs.html @@ -0,0 +1,321 @@ +shuffle1_dyn.rs.html -- source
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+
+//! Shuffle vector elements according to a dynamic vector of indices.
+
+macro_rules! impl_shuffle1_dyn {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident | $test_tt:tt) => {
+        impl $id {
+            /// Shuffle vector elements according to `indices`.
+            #[inline]
+            pub fn shuffle1_dyn<I>(self, indices: I) -> Self
+            where
+                Self: codegen::shuffle1_dyn::Shuffle1Dyn<Indices = I>,
+            {
+                codegen::shuffle1_dyn::Shuffle1Dyn::shuffle1_dyn(self, indices)
+            }
+        }
+    };
+}
+
+macro_rules! test_shuffle1_dyn {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident | $test_tt:tt) => {
+        test_if! {
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _shuffle1_dyn>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn shuffle1_dyn() {
+                        let increasing = {
+                            let mut v = $id::splat(0 as $elem_ty);
+                            for i in 0..$id::lanes() {
+                                v = v.replace(i, i as $elem_ty);
+                            }
+                            v
+                        };
+                        let decreasing = {
+                            let mut v = $id::splat(0 as $elem_ty);
+                            for i in 0..$id::lanes() {
+                                v = v.replace(
+                                    i,
+                                    ($id::lanes() - 1 - i) as $elem_ty
+                                );
+                            }
+                            v
+                        };
+
+                        type Indices = <
+                            $id as codegen::shuffle1_dyn::Shuffle1Dyn
+                            >::Indices;
+                        let increasing_ids: Indices = increasing.cast();
+                        let decreasing_ids: Indices = decreasing.cast();
+
+                        assert_eq!(
+                            increasing.shuffle1_dyn(increasing_ids),
+                            increasing,
+                            "(i,i)=>i"
+                        );
+                        assert_eq!(
+                            decreasing.shuffle1_dyn(increasing_ids),
+                            decreasing,
+                            "(d,i)=>d"
+                        );
+                        assert_eq!(
+                            increasing.shuffle1_dyn(decreasing_ids),
+                            decreasing,
+                            "(i,d)=>d"
+                        );
+                        assert_eq!(
+                            decreasing.shuffle1_dyn(decreasing_ids),
+                            increasing,
+                            "(d,d)=>i"
+                        );
+
+                        for i in 0..$id::lanes() {
+                            let v_ids: Indices
+                                = $id::splat(i as $elem_ty).cast();
+                            assert_eq!(increasing.shuffle1_dyn(v_ids),
+                                       $id::splat(increasing.extract(i))
+                            );
+                            assert_eq!(decreasing.shuffle1_dyn(v_ids),
+                                       $id::splat(decreasing.extract(i))
+                            );
+                            assert_eq!(
+                                $id::splat(i as $elem_ty)
+                                    .shuffle1_dyn(increasing_ids),
+                                $id::splat(i as $elem_ty)
+                            );
+                            assert_eq!(
+                                $id::splat(i as $elem_ty)
+                                    .shuffle1_dyn(decreasing_ids),
+                                $id::splat(i as $elem_ty)
+                            );
+                        }
+                    }
+                }
+            }
+        }
+    };
+}
+
+macro_rules! test_shuffle1_dyn_mask {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident | $test_tt:tt) => {
+        test_if! {
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _shuffle1_dyn>] {
+                    use super::*;
+                    #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn shuffle1_dyn() {
+                        // alternating = [true, false, true, false, ...]
+                        let mut alternating = $id::splat(false);
+                        for i in 0..$id::lanes() {
+                            if i % 2 == 0 {
+                                alternating = alternating.replace(i, true);
+                            }
+                        }
+
+                        type Indices = <
+                            $id as codegen::shuffle1_dyn::Shuffle1Dyn
+                            >::Indices;
+                        // even = [0, 0, 2, 2, 4, 4, ..]
+                        let even = {
+                            let mut v = Indices::splat(0);
+                            for i in 0..$id::lanes() {
+                                if i % 2 == 0 {
+                                    v = v.replace(i, (i as u8).into());
+                                } else {
+                                    v = v.replace(i, (i as u8 - 1).into());
+                                }
+                            }
+                            v
+                        };
+                        // odd = [1, 1, 3, 3, 5, 5, ...]
+                        let odd = {
+                            let mut v = Indices::splat(0);
+                            for i in 0..$id::lanes() {
+                                if i % 2 != 0 {
+                                    v = v.replace(i, (i as u8).into());
+                                } else {
+                                    v = v.replace(i, (i as u8 + 1).into());
+                                }
+                            }
+                            v
+                        };
+
+                        assert_eq!(
+                            alternating.shuffle1_dyn(even),
+                            $id::splat(true)
+                        );
+                        if $id::lanes() > 1 {
+                            assert_eq!(
+                                alternating.shuffle1_dyn(odd),
+                                $id::splat(false)
+                            );
+                        }
+                    }
+                }
+            }
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/slice.rs.html b/src/packed_simd/api/slice.rs.html new file mode 100644 index 000000000..090f75123 --- /dev/null +++ b/src/packed_simd/api/slice.rs.html @@ -0,0 +1,17 @@ +slice.rs.html -- source
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+//! Slice from/to methods
+
+#[macro_use]
+mod from_slice;
+
+#[macro_use]
+mod write_to_slice;
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/slice/from_slice.rs.html b/src/packed_simd/api/slice/from_slice.rs.html new file mode 100644 index 000000000..23a6c2b38 --- /dev/null +++ b/src/packed_simd/api/slice/from_slice.rs.html @@ -0,0 +1,435 @@ +from_slice.rs.html -- source
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+
+//! Implements methods to read a vector type from a slice.
+
+macro_rules! impl_slice_from_slice {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident | $test_tt:tt) => {
+        impl $id {
+            /// Instantiates a new vector with the values of the `slice`.
+            ///
+            /// # Panics
+            ///
+            /// If `slice.len() < Self::lanes()` or `&slice[0]` is not aligned
+            /// to an `align_of::<Self>()` boundary.
+            #[inline]
+            pub fn from_slice_aligned(slice: &[$elem_ty]) -> Self {
+                unsafe {
+                    assert!(slice.len() >= $elem_count);
+                    let target_ptr = slice.get_unchecked(0) as *const $elem_ty;
+                    assert_eq!(
+                        target_ptr
+                            .align_offset(crate::mem::align_of::<Self>()),
+                        0
+                    );
+                    Self::from_slice_aligned_unchecked(slice)
+                }
+            }
+
+            /// Instantiates a new vector with the values of the `slice`.
+            ///
+            /// # Panics
+            ///
+            /// If `slice.len() < Self::lanes()`.
+            #[inline]
+            pub fn from_slice_unaligned(slice: &[$elem_ty]) -> Self {
+                unsafe {
+                    assert!(slice.len() >= $elem_count);
+                    Self::from_slice_unaligned_unchecked(slice)
+                }
+            }
+
+            /// Instantiates a new vector with the values of the `slice`.
+            ///
+            /// # Precondition
+            ///
+            /// If `slice.len() < Self::lanes()` or `&slice[0]` is not aligned
+            /// to an `align_of::<Self>()` boundary, the behavior is undefined.
+            #[inline]
+            pub unsafe fn from_slice_aligned_unchecked(
+                slice: &[$elem_ty],
+            ) -> Self {
+                debug_assert!(slice.len() >= $elem_count);
+                let target_ptr = slice.get_unchecked(0) as *const $elem_ty;
+                debug_assert_eq!(
+                    target_ptr.align_offset(crate::mem::align_of::<Self>()),
+                    0
+                );
+
+                #[allow(clippy::cast_ptr_alignment)]
+                *(target_ptr as *const Self)
+            }
+
+            /// Instantiates a new vector with the values of the `slice`.
+            ///
+            /// # Precondition
+            ///
+            /// If `slice.len() < Self::lanes()` the behavior is undefined.
+            #[inline]
+            pub unsafe fn from_slice_unaligned_unchecked(
+                slice: &[$elem_ty],
+            ) -> Self {
+                use crate::mem::size_of;
+                debug_assert!(slice.len() >= $elem_count);
+                let target_ptr =
+                    slice.get_unchecked(0) as *const $elem_ty as *const u8;
+                let mut x = Self::splat(0 as $elem_ty);
+                let self_ptr = &mut x as *mut Self as *mut u8;
+                crate::ptr::copy_nonoverlapping(
+                    target_ptr,
+                    self_ptr,
+                    size_of::<Self>(),
+                );
+                x
+            }
+        }
+
+        test_if! {
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _slice_from_slice>] {
+                    use super::*;
+                    use crate::iter::Iterator;
+
+                    #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn from_slice_unaligned() {
+                        let mut unaligned = [42 as $elem_ty; $id::lanes() + 1];
+                        unaligned[0] = 0 as $elem_ty;
+                        let vec = $id::from_slice_unaligned(&unaligned[1..]);
+                        for (index, &b) in unaligned.iter().enumerate() {
+                            if index == 0 {
+                                assert_eq!(b, 0 as $elem_ty);
+                            } else {
+                                assert_eq!(b, 42 as $elem_ty);
+                                assert_eq!(b, vec.extract(index - 1));
+                            }
+                        }
+                    }
+
+                    // FIXME: wasm-bindgen-test does not support #[should_panic]
+                    // #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    // #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    #[cfg(not(target_arch = "wasm32"))]
+                    #[test]
+                    #[should_panic]
+                    fn from_slice_unaligned_fail() {
+                        let mut unaligned = [42 as $elem_ty; $id::lanes() + 1];
+                        unaligned[0] = 0 as $elem_ty;
+                        // the slice is not large enough => panic
+                        let _vec = $id::from_slice_unaligned(&unaligned[2..]);
+                    }
+
+                    union A {
+                        data: [$elem_ty; 2 * $id::lanes()],
+                        _vec: $id,
+                    }
+
+                    #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn from_slice_aligned() {
+                        let mut aligned = A {
+                            data: [0 as $elem_ty; 2 * $id::lanes()],
+                        };
+                        for i in $id::lanes()..(2 * $id::lanes()) {
+                            unsafe {
+                                aligned.data[i] = 42 as $elem_ty;
+                            }
+                        }
+
+                        let vec = unsafe {
+                            $id::from_slice_aligned(
+                                &aligned.data[$id::lanes()..]
+                            )
+                        };
+                        for (index, &b) in
+                            unsafe { aligned.data.iter().enumerate() } {
+                            if index < $id::lanes() {
+                                assert_eq!(b, 0 as $elem_ty);
+                            } else {
+                                assert_eq!(b, 42 as $elem_ty);
+                                assert_eq!(
+                                    b, vec.extract(index - $id::lanes())
+                                );
+                            }
+                        }
+                    }
+
+                    // FIXME: wasm-bindgen-test does not support #[should_panic]
+                    // #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    // #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    #[cfg(not(target_arch = "wasm32"))]
+                    #[test]
+                    #[should_panic]
+                    fn from_slice_aligned_fail_lanes() {
+                        let aligned = A {
+                            data: [0 as $elem_ty; 2 * $id::lanes()],
+                        };
+                        let _vec = unsafe {
+                            $id::from_slice_aligned(
+                                &aligned.data[2 * $id::lanes()..]
+                            )
+                        };
+                    }
+
+                    // FIXME: wasm-bindgen-test does not support #[should_panic]
+                    // #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    // #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    #[cfg(not(target_arch = "wasm32"))]
+                    #[test]
+                    #[should_panic]
+                    fn from_slice_aligned_fail_align() {
+                        unsafe {
+                            let aligned = A {
+                                data: [0 as $elem_ty; 2 * $id::lanes()],
+                            };
+
+                            // get a pointer to the front of data
+                            let ptr: *const $elem_ty = aligned.data.as_ptr()
+                                as *const $elem_ty;
+                            // offset pointer by one element
+                            let ptr = ptr.wrapping_add(1);
+
+                            if ptr.align_offset(
+                                crate::mem::align_of::<$id>()
+                            ) == 0 {
+                                // the pointer is properly aligned, so
+                                // from_slice_aligned won't fail here (e.g. this
+                                // can happen for i128x1). So we panic to make
+                                // the "should_fail" test pass:
+                                panic!("ok");
+                            }
+
+                            // create a slice - this is safe, because the
+                            // elements of the slice exist, are properly
+                            // initialized, and properly aligned:
+                            let s: &[$elem_ty] = slice::from_raw_parts(
+                                ptr, $id::lanes()
+                            );
+                            // this should always panic because the slice
+                            // alignment does not match the alignment
+                            // requirements for the vector type:
+                            let _vec = $id::from_slice_aligned(s);
+                        }
+                    }
+                }
+            }
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/api/slice/write_to_slice.rs.html b/src/packed_simd/api/slice/write_to_slice.rs.html new file mode 100644 index 000000000..2ccf6fbe7 --- /dev/null +++ b/src/packed_simd/api/slice/write_to_slice.rs.html @@ -0,0 +1,425 @@ +write_to_slice.rs.html -- source
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+
+//! Implements methods to write a vector type to a slice.
+
+macro_rules! impl_slice_write_to_slice {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident | $test_tt:tt) => {
+        impl $id {
+            /// Writes the values of the vector to the `slice`.
+            ///
+            /// # Panics
+            ///
+            /// If `slice.len() < Self::lanes()` or `&slice[0]` is not
+            /// aligned to an `align_of::<Self>()` boundary.
+            #[inline]
+            pub fn write_to_slice_aligned(self, slice: &mut [$elem_ty]) {
+                unsafe {
+                    assert!(slice.len() >= $elem_count);
+                    let target_ptr =
+                        slice.get_unchecked_mut(0) as *mut $elem_ty;
+                    assert_eq!(
+                        target_ptr
+                            .align_offset(crate::mem::align_of::<Self>()),
+                        0
+                    );
+                    self.write_to_slice_aligned_unchecked(slice);
+                }
+            }
+
+            /// Writes the values of the vector to the `slice`.
+            ///
+            /// # Panics
+            ///
+            /// If `slice.len() < Self::lanes()`.
+            #[inline]
+            pub fn write_to_slice_unaligned(self, slice: &mut [$elem_ty]) {
+                unsafe {
+                    assert!(slice.len() >= $elem_count);
+                    self.write_to_slice_unaligned_unchecked(slice);
+                }
+            }
+
+            /// Writes the values of the vector to the `slice`.
+            ///
+            /// # Precondition
+            ///
+            /// If `slice.len() < Self::lanes()` or `&slice[0]` is not
+            /// aligned to an `align_of::<Self>()` boundary, the behavior is
+            /// undefined.
+            #[inline]
+            pub unsafe fn write_to_slice_aligned_unchecked(
+                self, slice: &mut [$elem_ty],
+            ) {
+                debug_assert!(slice.len() >= $elem_count);
+                let target_ptr = slice.get_unchecked_mut(0) as *mut $elem_ty;
+                debug_assert_eq!(
+                    target_ptr.align_offset(crate::mem::align_of::<Self>()),
+                    0
+                );
+
+                                #[allow(clippy::cast_ptr_alignment)]
+                        #[allow(clippy::cast_ptr_alignment)]
+                #[allow(clippy::cast_ptr_alignment)]
+                #[allow(clippy::cast_ptr_alignment)]
+                *(target_ptr as *mut Self) = self;
+            }
+
+            /// Writes the values of the vector to the `slice`.
+            ///
+            /// # Precondition
+            ///
+            /// If `slice.len() < Self::lanes()` the behavior is undefined.
+            #[inline]
+            pub unsafe fn write_to_slice_unaligned_unchecked(
+                self, slice: &mut [$elem_ty],
+            ) {
+                debug_assert!(slice.len() >= $elem_count);
+                let target_ptr =
+                    slice.get_unchecked_mut(0) as *mut $elem_ty as *mut u8;
+                let self_ptr = &self as *const Self as *const u8;
+                crate::ptr::copy_nonoverlapping(
+                    self_ptr,
+                    target_ptr,
+                    crate::mem::size_of::<Self>(),
+                );
+            }
+        }
+
+        test_if! {
+            $test_tt:
+            paste::item! {
+                pub mod [<$id _slice_write_to_slice>] {
+                    use super::*;
+                    use crate::iter::Iterator;
+
+                    #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn write_to_slice_unaligned() {
+                        let mut unaligned = [0 as $elem_ty; $id::lanes() + 1];
+                        let vec = $id::splat(42 as $elem_ty);
+                        vec.write_to_slice_unaligned(&mut unaligned[1..]);
+                        for (index, &b) in unaligned.iter().enumerate() {
+                            if index == 0 {
+                                assert_eq!(b, 0 as $elem_ty);
+                            } else {
+                                assert_eq!(b, 42 as $elem_ty);
+                                assert_eq!(b, vec.extract(index - 1));
+                            }
+                        }
+                    }
+
+                    // FIXME: wasm-bindgen-test does not support #[should_panic]
+                    // #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    // #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    #[cfg(not(target_arch = "wasm32"))]
+                    #[test]
+                    #[should_panic]
+                    fn write_to_slice_unaligned_fail() {
+                        let mut unaligned = [0 as $elem_ty; $id::lanes() + 1];
+                        let vec = $id::splat(42 as $elem_ty);
+                        vec.write_to_slice_unaligned(&mut unaligned[2..]);
+                    }
+
+                    union A {
+                        data: [$elem_ty; 2 * $id::lanes()],
+                        _vec: $id,
+                    }
+
+                    #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn write_to_slice_aligned() {
+                        let mut aligned = A {
+                            data: [0 as $elem_ty; 2 * $id::lanes()],
+                        };
+                        let vec = $id::splat(42 as $elem_ty);
+                        unsafe {
+                            vec.write_to_slice_aligned(
+                                &mut aligned.data[$id::lanes()..]
+                            );
+                            for (idx, &b) in aligned.data.iter().enumerate() {
+                                if idx < $id::lanes() {
+                                    assert_eq!(b, 0 as $elem_ty);
+                                } else {
+                                    assert_eq!(b, 42 as $elem_ty);
+                                    assert_eq!(
+                                        b, vec.extract(idx - $id::lanes())
+                                    );
+                                }
+                            }
+                        }
+                    }
+
+                    // FIXME: wasm-bindgen-test does not support #[should_panic]
+                    // #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    // #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    #[cfg(not(target_arch = "wasm32"))]
+                    #[test]
+                    #[should_panic]
+                    fn write_to_slice_aligned_fail_lanes() {
+                        let mut aligned = A {
+                            data: [0 as $elem_ty; 2 * $id::lanes()],
+                        };
+                        let vec = $id::splat(42 as $elem_ty);
+                        unsafe {
+                            vec.write_to_slice_aligned(
+                                &mut aligned.data[2 * $id::lanes()..]
+                            )
+                        };
+                    }
+
+                    // FIXME: wasm-bindgen-test does not support #[should_panic]
+                    // #[cfg_attr(not(target_arch = "wasm32"), test)]
+                    // #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    #[cfg(not(target_arch = "wasm32"))]
+                    #[test]
+                    #[should_panic]
+                    fn write_to_slice_aligned_fail_align() {
+                        unsafe {
+                            let mut aligned = A {
+                                data: [0 as $elem_ty; 2 * $id::lanes()],
+                            };
+
+                            // get a pointer to the front of data
+                            let ptr: *mut $elem_ty
+                                = aligned.data.as_mut_ptr() as *mut $elem_ty;
+                            // offset pointer by one element
+                            let ptr = ptr.wrapping_add(1);
+
+                            if ptr.align_offset(crate::mem::align_of::<$id>())
+                                == 0 {
+                                // the pointer is properly aligned, so
+                                // write_to_slice_aligned won't fail here (e.g.
+                                // this can happen for i128x1). So we panic to
+                                // make the "should_fail" test pass:
+                                panic!("ok");
+                            }
+
+                            // create a slice - this is safe, because the
+                            // elements of the slice exist, are properly
+                            // initialized, and properly aligned:
+                            let s: &mut [$elem_ty]
+                                = slice::from_raw_parts_mut(ptr, $id::lanes());
+                            // this should always panic because the slice
+                            // alignment does not match the alignment
+                            // requirements for the vector type:
+                            let vec = $id::splat(42 as $elem_ty);
+                            vec.write_to_slice_aligned(s);
+                        }
+                    }
+                }
+            }
+        }
+    };
+}
+
+
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+
+//! Horizontal swap bytes
+
+macro_rules! impl_swap_bytes {
+    ([$elem_ty:ident; $elem_count:expr]: $id:ident | $test_tt:tt) => {
+        impl $id {
+            /// Reverses the byte order of the vector.
+            #[inline]
+            pub fn swap_bytes(self) -> Self {
+                super::codegen::swap_bytes::SwapBytes::swap_bytes(self)
+            }
+
+            /// Converts self to little endian from the target's endianness.
+            ///
+            /// On little endian this is a no-op. On big endian the bytes are
+            /// swapped.
+            #[inline]
+            pub fn to_le(self) -> Self {
+                #[cfg(target_endian = "little")]
+                {
+                    self
+                }
+                #[cfg(not(target_endian = "little"))]
+                {
+                    self.swap_bytes()
+                }
+            }
+
+            /// Converts self to big endian from the target's endianness.
+            ///
+            /// On big endian this is a no-op. On little endian the bytes are
+            /// swapped.
+            #[inline]
+            pub fn to_be(self) -> Self {
+                #[cfg(target_endian = "big")]
+                {
+                    self
+                }
+                #[cfg(not(target_endian = "big"))]
+                {
+                    self.swap_bytes()
+                }
+            }
+
+            /// Converts a vector from little endian to the target's endianness.
+            ///
+            /// On little endian this is a no-op. On big endian the bytes are
+            /// swapped.
+            #[inline]
+            pub fn from_le(x: Self) -> Self {
+                #[cfg(target_endian = "little")]
+                {
+                    x
+                }
+                #[cfg(not(target_endian = "little"))]
+                {
+                    x.swap_bytes()
+                }
+            }
+
+            /// Converts a vector from big endian to the target's endianness.
+            ///
+            /// On big endian this is a no-op. On little endian the bytes are
+            /// swapped.
+            #[inline]
+            pub fn from_be(x: Self) -> Self {
+                #[cfg(target_endian = "big")]
+                {
+                    x
+                }
+                #[cfg(not(target_endian = "big"))]
+                {
+                    x.swap_bytes()
+                }
+            }
+        }
+
+        test_if! {
+            $test_tt:
+            paste::item_with_macros! {
+                pub mod [<$id _swap_bytes>] {
+                    use super::*;
+
+                    const BYTES: [u8; 64] = [
+                        0, 1, 2, 3, 4, 5, 6, 7,
+                        8, 9, 10, 11, 12, 13, 14, 15,
+                        16, 17, 18, 19, 20, 21, 22, 23,
+                        24, 25, 26, 27, 28, 29, 30, 31,
+                        32, 33, 34, 35, 36, 37, 38, 39,
+                        40, 41, 42, 43, 44, 45, 46, 47,
+                        48, 49, 50, 51, 52, 53, 54, 55,
+                        56, 57, 58, 59, 60, 61, 62, 63,
+                    ];
+
+                    macro_rules! swap {
+                        ($func: ident) => {{
+                            // catch possible future >512 vectors
+                            assert!(mem::size_of::<$id>() <= 64);
+
+                            let mut actual = BYTES;
+                            let elems: &mut [$elem_ty] = unsafe {
+                                slice::from_raw_parts_mut(
+                                    actual.as_mut_ptr() as *mut $elem_ty,
+                                    $id::lanes(),
+                                )
+                            };
+
+                            let vec = $id::from_slice_unaligned(elems);
+                            $id::$func(vec).write_to_slice_unaligned(elems);
+
+                            actual
+                        }};
+                    }
+
+                    macro_rules! test_swap {
+                        ($func: ident) => {{
+                            let actual = swap!($func);
+                            let expected =
+                                BYTES.iter().rev()
+                                .skip(64 - crate::mem::size_of::<$id>());
+                            assert!(actual.iter().zip(expected)
+                                    .all(|(x, y)| x == y));
+                        }};
+                    }
+
+                    macro_rules! test_no_swap {
+                        ($func: ident) => {{
+                            let actual = swap!($func);
+                            let expected = BYTES.iter()
+                                .take(mem::size_of::<$id>());
+
+                            assert!(actual.iter().zip(expected)
+                                    .all(|(x, y)| x == y));
+                        }};
+                    }
+
+                    #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn swap_bytes() {
+                        test_swap!(swap_bytes);
+                    }
+
+                    #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn to_le() {
+                        #[cfg(target_endian = "little")]
+                        {
+                            test_no_swap!(to_le);
+                        }
+                        #[cfg(not(target_endian = "little"))]
+                        {
+                            test_swap!(to_le);
+                        }
+                    }
+
+                    #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn to_be() {
+                        #[cfg(target_endian = "big")]
+                        {
+                            test_no_swap!(to_be);
+                        }
+                        #[cfg(not(target_endian = "big"))]
+                        {
+                            test_swap!(to_be);
+                        }
+                    }
+
+                    #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn from_le() {
+                        #[cfg(target_endian = "little")]
+                        {
+                            test_no_swap!(from_le);
+                        }
+                        #[cfg(not(target_endian = "little"))]
+                        {
+                            test_swap!(from_le);
+                        }
+                    }
+
+                    #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)]
+                    fn from_be() {
+                        #[cfg(target_endian = "big")]
+                        {
+                            test_no_swap!(from_be);
+                        }
+                        #[cfg(not(target_endian = "big"))]
+                        {
+                            test_swap!(from_be);
+                        }
+                    }
+                }
+            }
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/codegen.rs.html b/src/packed_simd/codegen.rs.html new file mode 100644 index 000000000..a6bf2443e --- /dev/null +++ b/src/packed_simd/codegen.rs.html @@ -0,0 +1,127 @@ +codegen.rs.html -- source
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+//! Code-generation utilities
+
+crate mod bit_manip;
+crate mod llvm;
+crate mod math;
+crate mod reductions;
+crate mod shuffle;
+crate mod shuffle1_dyn;
+crate mod swap_bytes;
+
+macro_rules! impl_simd_array {
+    ([$elem_ty:ident; $elem_count:expr]:
+     $tuple_id:ident | $($elem_tys:ident),*) => {
+        #[derive(Copy, Clone)]
+        #[repr(simd)]
+        pub struct $tuple_id($(crate $elem_tys),*);
+        //^^^^^^^ leaked through SimdArray
+
+        impl crate::sealed::Seal for [$elem_ty; $elem_count] {}
+
+        impl crate::sealed::SimdArray for [$elem_ty; $elem_count] {
+            type Tuple = $tuple_id;
+            type T = $elem_ty;
+            const N: usize = $elem_count;
+            type NT = [u32; $elem_count];
+        }
+
+        impl crate::sealed::Seal for $tuple_id {}
+        impl crate::sealed::Simd for $tuple_id {
+            type Element = $elem_ty;
+            const LANES: usize = $elem_count;
+            type LanesType = [u32; $elem_count];
+        }
+
+    }
+}
+
+crate mod pointer_sized_int;
+
+crate mod v16;
+crate use self::v16::*;
+
+crate mod v32;
+crate use self::v32::*;
+
+crate mod v64;
+crate use self::v64::*;
+
+crate mod v128;
+crate use self::v128::*;
+
+crate mod v256;
+crate use self::v256::*;
+
+crate mod v512;
+crate use self::v512::*;
+
+crate mod vSize;
+crate use self::vSize::*;
+
+crate mod vPtr;
+crate use self::vPtr::*;
+
+
\ No newline at end of file diff --git a/src/packed_simd/codegen/bit_manip.rs.html b/src/packed_simd/codegen/bit_manip.rs.html new file mode 100644 index 000000000..a473ca511 --- /dev/null +++ b/src/packed_simd/codegen/bit_manip.rs.html @@ -0,0 +1,711 @@ +bit_manip.rs.html -- source
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+
+//! LLVM bit manipulation intrinsics.
+#![rustfmt::skip]
+
+use crate::*;
+
+#[allow(improper_ctypes, dead_code)]
+extern "C" {
+    #[link_name = "llvm.ctlz.v2i8"]
+    fn ctlz_u8x2(x: u8x2, is_zero_undef: bool) -> u8x2;
+    #[link_name = "llvm.ctlz.v4i8"]
+    fn ctlz_u8x4(x: u8x4, is_zero_undef: bool) -> u8x4;
+    #[link_name = "llvm.ctlz.v8i8"]
+    fn ctlz_u8x8(x: u8x8, is_zero_undef: bool) -> u8x8;
+    #[link_name = "llvm.ctlz.v16i8"]
+    fn ctlz_u8x16(x: u8x16, is_zero_undef: bool) -> u8x16;
+    #[link_name = "llvm.ctlz.v32i8"]
+    fn ctlz_u8x32(x: u8x32, is_zero_undef: bool) -> u8x32;
+    #[link_name = "llvm.ctlz.v64i8"]
+    fn ctlz_u8x64(x: u8x64, is_zero_undef: bool) -> u8x64;
+
+    #[link_name = "llvm.ctlz.v2i16"]
+    fn ctlz_u16x2(x: u16x2, is_zero_undef: bool) -> u16x2;
+    #[link_name = "llvm.ctlz.v4i16"]
+    fn ctlz_u16x4(x: u16x4, is_zero_undef: bool) -> u16x4;
+    #[link_name = "llvm.ctlz.v8i16"]
+    fn ctlz_u16x8(x: u16x8, is_zero_undef: bool) -> u16x8;
+    #[link_name = "llvm.ctlz.v16i16"]
+    fn ctlz_u16x16(x: u16x16, is_zero_undef: bool) -> u16x16;
+    #[link_name = "llvm.ctlz.v32i16"]
+    fn ctlz_u16x32(x: u16x32, is_zero_undef: bool) -> u16x32;
+
+    #[link_name = "llvm.ctlz.v2i32"]
+    fn ctlz_u32x2(x: u32x2, is_zero_undef: bool) -> u32x2;
+    #[link_name = "llvm.ctlz.v4i32"]
+    fn ctlz_u32x4(x: u32x4, is_zero_undef: bool) -> u32x4;
+    #[link_name = "llvm.ctlz.v8i32"]
+    fn ctlz_u32x8(x: u32x8, is_zero_undef: bool) -> u32x8;
+    #[link_name = "llvm.ctlz.v16i32"]
+    fn ctlz_u32x16(x: u32x16, is_zero_undef: bool) -> u32x16;
+
+    #[link_name = "llvm.ctlz.v2i64"]
+    fn ctlz_u64x2(x: u64x2, is_zero_undef: bool) -> u64x2;
+    #[link_name = "llvm.ctlz.v4i64"]
+    fn ctlz_u64x4(x: u64x4, is_zero_undef: bool) -> u64x4;
+    #[link_name = "llvm.ctlz.v8i64"]
+    fn ctlz_u64x8(x: u64x8, is_zero_undef: bool) -> u64x8;
+
+    #[link_name = "llvm.ctlz.v1i128"]
+    fn ctlz_u128x1(x: u128x1, is_zero_undef: bool) -> u128x1;
+    #[link_name = "llvm.ctlz.v2i128"]
+    fn ctlz_u128x2(x: u128x2, is_zero_undef: bool) -> u128x2;
+    #[link_name = "llvm.ctlz.v4i128"]
+    fn ctlz_u128x4(x: u128x4, is_zero_undef: bool) -> u128x4;
+
+    #[link_name = "llvm.cttz.v2i8"]
+    fn cttz_u8x2(x: u8x2, is_zero_undef: bool) -> u8x2;
+    #[link_name = "llvm.cttz.v4i8"]
+    fn cttz_u8x4(x: u8x4, is_zero_undef: bool) -> u8x4;
+    #[link_name = "llvm.cttz.v8i8"]
+    fn cttz_u8x8(x: u8x8, is_zero_undef: bool) -> u8x8;
+    #[link_name = "llvm.cttz.v16i8"]
+    fn cttz_u8x16(x: u8x16, is_zero_undef: bool) -> u8x16;
+    #[link_name = "llvm.cttz.v32i8"]
+    fn cttz_u8x32(x: u8x32, is_zero_undef: bool) -> u8x32;
+    #[link_name = "llvm.cttz.v64i8"]
+    fn cttz_u8x64(x: u8x64, is_zero_undef: bool) -> u8x64;
+
+    #[link_name = "llvm.cttz.v2i16"]
+    fn cttz_u16x2(x: u16x2, is_zero_undef: bool) -> u16x2;
+    #[link_name = "llvm.cttz.v4i16"]
+    fn cttz_u16x4(x: u16x4, is_zero_undef: bool) -> u16x4;
+    #[link_name = "llvm.cttz.v8i16"]
+    fn cttz_u16x8(x: u16x8, is_zero_undef: bool) -> u16x8;
+    #[link_name = "llvm.cttz.v16i16"]
+    fn cttz_u16x16(x: u16x16, is_zero_undef: bool) -> u16x16;
+    #[link_name = "llvm.cttz.v32i16"]
+    fn cttz_u16x32(x: u16x32, is_zero_undef: bool) -> u16x32;
+
+    #[link_name = "llvm.cttz.v2i32"]
+    fn cttz_u32x2(x: u32x2, is_zero_undef: bool) -> u32x2;
+    #[link_name = "llvm.cttz.v4i32"]
+    fn cttz_u32x4(x: u32x4, is_zero_undef: bool) -> u32x4;
+    #[link_name = "llvm.cttz.v8i32"]
+    fn cttz_u32x8(x: u32x8, is_zero_undef: bool) -> u32x8;
+    #[link_name = "llvm.cttz.v16i32"]
+    fn cttz_u32x16(x: u32x16, is_zero_undef: bool) -> u32x16;
+
+    #[link_name = "llvm.cttz.v2i64"]
+    fn cttz_u64x2(x: u64x2, is_zero_undef: bool) -> u64x2;
+    #[link_name = "llvm.cttz.v4i64"]
+    fn cttz_u64x4(x: u64x4, is_zero_undef: bool) -> u64x4;
+    #[link_name = "llvm.cttz.v8i64"]
+    fn cttz_u64x8(x: u64x8, is_zero_undef: bool) -> u64x8;
+
+    #[link_name = "llvm.cttz.v1i128"]
+    fn cttz_u128x1(x: u128x1, is_zero_undef: bool) -> u128x1;
+    #[link_name = "llvm.cttz.v2i128"]
+    fn cttz_u128x2(x: u128x2, is_zero_undef: bool) -> u128x2;
+    #[link_name = "llvm.cttz.v4i128"]
+    fn cttz_u128x4(x: u128x4, is_zero_undef: bool) -> u128x4;
+
+    #[link_name = "llvm.ctpop.v2i8"]
+    fn ctpop_u8x2(x: u8x2) -> u8x2;
+    #[link_name = "llvm.ctpop.v4i8"]
+    fn ctpop_u8x4(x: u8x4) -> u8x4;
+    #[link_name = "llvm.ctpop.v8i8"]
+    fn ctpop_u8x8(x: u8x8) -> u8x8;
+    #[link_name = "llvm.ctpop.v16i8"]
+    fn ctpop_u8x16(x: u8x16) -> u8x16;
+    #[link_name = "llvm.ctpop.v32i8"]
+    fn ctpop_u8x32(x: u8x32) -> u8x32;
+    #[link_name = "llvm.ctpop.v64i8"]
+    fn ctpop_u8x64(x: u8x64) -> u8x64;
+
+    #[link_name = "llvm.ctpop.v2i16"]
+    fn ctpop_u16x2(x: u16x2) -> u16x2;
+    #[link_name = "llvm.ctpop.v4i16"]
+    fn ctpop_u16x4(x: u16x4) -> u16x4;
+    #[link_name = "llvm.ctpop.v8i16"]
+    fn ctpop_u16x8(x: u16x8) -> u16x8;
+    #[link_name = "llvm.ctpop.v16i16"]
+    fn ctpop_u16x16(x: u16x16) -> u16x16;
+    #[link_name = "llvm.ctpop.v32i16"]
+    fn ctpop_u16x32(x: u16x32) -> u16x32;
+
+    #[link_name = "llvm.ctpop.v2i32"]
+    fn ctpop_u32x2(x: u32x2) -> u32x2;
+    #[link_name = "llvm.ctpop.v4i32"]
+    fn ctpop_u32x4(x: u32x4) -> u32x4;
+    #[link_name = "llvm.ctpop.v8i32"]
+    fn ctpop_u32x8(x: u32x8) -> u32x8;
+    #[link_name = "llvm.ctpop.v16i32"]
+    fn ctpop_u32x16(x: u32x16) -> u32x16;
+
+    #[link_name = "llvm.ctpop.v2i64"]
+    fn ctpop_u64x2(x: u64x2) -> u64x2;
+    #[link_name = "llvm.ctpop.v4i64"]
+    fn ctpop_u64x4(x: u64x4) -> u64x4;
+    #[link_name = "llvm.ctpop.v8i64"]
+    fn ctpop_u64x8(x: u64x8) -> u64x8;
+
+    #[link_name = "llvm.ctpop.v1i128"]
+    fn ctpop_u128x1(x: u128x1) -> u128x1;
+    #[link_name = "llvm.ctpop.v2i128"]
+    fn ctpop_u128x2(x: u128x2) -> u128x2;
+    #[link_name = "llvm.ctpop.v4i128"]
+    fn ctpop_u128x4(x: u128x4) -> u128x4;
+}
+
+crate trait BitManip {
+    fn ctpop(self) -> Self;
+    fn ctlz(self) -> Self;
+    fn cttz(self) -> Self;
+}
+
+macro_rules! impl_bit_manip {
+    (inner: $ty:ident, $scalar:ty, $uty:ident,
+     $ctpop:ident, $ctlz:ident, $cttz:ident) => {
+        // FIXME: several LLVM intrinsics break on s390x https://github.com/rust-lang-nursery/packed_simd/issues/192
+        #[cfg(target_arch = "s390x")]
+        impl_bit_manip! { scalar: $ty, $scalar }
+        #[cfg(not(target_arch = "s390x"))]
+        impl BitManip for $ty {
+            #[inline]
+            fn ctpop(self) -> Self {
+                let y: $uty = self.cast();
+                unsafe { $ctpop(y).cast() }
+            }
+
+            #[inline]
+            fn ctlz(self) -> Self {
+                let y: $uty = self.cast();
+                // the ctxx intrinsics need compile-time constant
+                // `is_zero_undef`
+                unsafe { $ctlz(y, false).cast() }
+            }
+
+            #[inline]
+            fn cttz(self) -> Self {
+                let y: $uty = self.cast();
+                unsafe { $cttz(y, false).cast() }
+            }
+        }
+    };
+    (sized_inner: $ty:ident, $scalar:ty, $uty:ident) => {
+        #[cfg(target_arch = "s390x")]
+        impl_bit_manip! { scalar: $ty, $scalar }
+        #[cfg(not(target_arch = "s390x"))]
+        impl BitManip for $ty {
+            #[inline]
+            fn ctpop(self) -> Self {
+                let y: $uty = self.cast();
+                $uty::ctpop(y).cast()
+            }
+
+            #[inline]
+            fn ctlz(self) -> Self {
+                let y: $uty = self.cast();
+                $uty::ctlz(y).cast()
+            }
+
+            #[inline]
+            fn cttz(self) -> Self {
+                let y: $uty = self.cast();
+                $uty::cttz(y).cast()
+            }
+        }
+    };
+    (scalar: $ty:ident, $scalar:ty) => {
+        impl BitManip for $ty {
+            #[inline]
+            fn ctpop(self) -> Self {
+                let mut ones = self;
+                for i in 0..Self::lanes() {
+                    ones = ones
+                        .replace(i, self.extract(i).count_ones() as $scalar);
+                }
+                ones
+            }
+
+            #[inline]
+            fn ctlz(self) -> Self {
+                let mut lz = self;
+                for i in 0..Self::lanes() {
+                    lz = lz.replace(
+                        i,
+                        self.extract(i).leading_zeros() as $scalar,
+                    );
+                }
+                lz
+            }
+
+            #[inline]
+            fn cttz(self) -> Self {
+                let mut tz = self;
+                for i in 0..Self::lanes() {
+                    tz = tz.replace(
+                        i,
+                        self.extract(i).trailing_zeros() as $scalar,
+                    );
+                }
+                tz
+            }
+        }
+    };
+    ($uty:ident, $uscalar:ty, $ity:ident, $iscalar:ty,
+     $ctpop:ident, $ctlz:ident, $cttz:ident) => {
+        impl_bit_manip! { inner: $uty, $uscalar, $uty, $ctpop, $ctlz, $cttz }
+        impl_bit_manip! { inner: $ity, $iscalar, $uty, $ctpop, $ctlz, $cttz }
+    };
+    (sized: $usize:ident, $uscalar:ty, $isize:ident,
+     $iscalar:ty, $ty:ident) => {
+        impl_bit_manip! { sized_inner: $usize, $uscalar, $ty }
+        impl_bit_manip! { sized_inner: $isize, $iscalar, $ty }
+    };
+}
+
+impl_bit_manip! { u8x2   ,   u8, i8x2, i8,   ctpop_u8x2,   ctlz_u8x2,   cttz_u8x2   }
+impl_bit_manip! { u8x4   ,   u8, i8x4, i8,   ctpop_u8x4,   ctlz_u8x4,   cttz_u8x4   }
+#[cfg(not(target_arch = "aarch64"))] // see below
+impl_bit_manip! { u8x8   ,   u8, i8x8, i8,   ctpop_u8x8,   ctlz_u8x8,   cttz_u8x8   }
+impl_bit_manip! { u8x16  ,  u8, i8x16, i8,  ctpop_u8x16,  ctlz_u8x16,  cttz_u8x16  }
+impl_bit_manip! { u8x32  ,  u8, i8x32, i8,  ctpop_u8x32,  ctlz_u8x32,  cttz_u8x32  }
+impl_bit_manip! { u8x64  ,  u8, i8x64, i8,  ctpop_u8x64,  ctlz_u8x64,  cttz_u8x64  }
+impl_bit_manip! { u16x2  ,  u16, i16x2, i16,  ctpop_u16x2,  ctlz_u16x2,  cttz_u16x2  }
+impl_bit_manip! { u16x4  ,  u16, i16x4, i16,  ctpop_u16x4,  ctlz_u16x4,  cttz_u16x4  }
+impl_bit_manip! { u16x8  ,  u16, i16x8, i16,  ctpop_u16x8,  ctlz_u16x8,  cttz_u16x8  }
+impl_bit_manip! { u16x16 , u16, i16x16, i16, ctpop_u16x16, ctlz_u16x16, cttz_u16x16 }
+impl_bit_manip! { u16x32 , u16, i16x32, i16, ctpop_u16x32, ctlz_u16x32, cttz_u16x32 }
+impl_bit_manip! { u32x2  ,  u32, i32x2, i32,  ctpop_u32x2,  ctlz_u32x2,  cttz_u32x2  }
+impl_bit_manip! { u32x4  ,  u32, i32x4, i32,  ctpop_u32x4,  ctlz_u32x4,  cttz_u32x4  }
+impl_bit_manip! { u32x8  ,  u32, i32x8, i32,  ctpop_u32x8,  ctlz_u32x8,  cttz_u32x8  }
+impl_bit_manip! { u32x16 , u32, i32x16, i32, ctpop_u32x16, ctlz_u32x16, cttz_u32x16 }
+impl_bit_manip! { u64x2  ,  u64, i64x2, i64,  ctpop_u64x2,  ctlz_u64x2,  cttz_u64x2  }
+impl_bit_manip! { u64x4  ,  u64, i64x4, i64,  ctpop_u64x4,  ctlz_u64x4,  cttz_u64x4  }
+impl_bit_manip! { u64x8  ,  u64, i64x8, i64,  ctpop_u64x8,  ctlz_u64x8,  cttz_u64x8  }
+impl_bit_manip! { u128x1 , u128, i128x1, i128, ctpop_u128x1, ctlz_u128x1, cttz_u128x1 }
+impl_bit_manip! { u128x2 , u128, i128x2, i128, ctpop_u128x2, ctlz_u128x2, cttz_u128x2 }
+impl_bit_manip! { u128x4 , u128, i128x4, i128, ctpop_u128x4, ctlz_u128x4, cttz_u128x4 }
+
+#[cfg(target_arch = "aarch64")]
+impl BitManip for u8x8 {
+    #[inline]
+    fn ctpop(self) -> Self {
+        let y: u8x8 = self.cast();
+        unsafe { ctpop_u8x8(y).cast() }
+    }
+
+    #[inline]
+    fn ctlz(self) -> Self {
+        let y: u8x8 = self.cast();
+        unsafe { ctlz_u8x8(y, false).cast() }
+    }
+
+    #[inline]
+    fn cttz(self) -> Self {
+        // FIXME: LLVM cttz.v8i8 broken on aarch64 https://github.com/rust-lang-nursery/packed_simd/issues/191
+        // OPTIMIZE: adapt the algorithm used for v8i16/etc to Rust's aarch64
+        // intrinsics
+        let mut tz = self;
+        for i in 0..Self::lanes() {
+            tz = tz.replace(i, self.extract(i).trailing_zeros() as u8);
+        }
+        tz
+    }
+}
+#[cfg(target_arch = "aarch64")]
+impl BitManip for i8x8 {
+    #[inline]
+    fn ctpop(self) -> Self {
+        let y: u8x8 = self.cast();
+        unsafe { ctpop_u8x8(y).cast() }
+    }
+
+    #[inline]
+    fn ctlz(self) -> Self {
+        let y: u8x8 = self.cast();
+        unsafe { ctlz_u8x8(y, false).cast() }
+    }
+
+    #[inline]
+    fn cttz(self) -> Self {
+        // FIXME: LLVM cttz.v8i8 broken on aarch64 https://github.com/rust-lang-nursery/packed_simd/issues/191
+        // OPTIMIZE: adapt the algorithm used for v8i16/etc to Rust's aarch64
+        // intrinsics
+        let mut tz = self;
+        for i in 0..Self::lanes() {
+            tz = tz.replace(i, self.extract(i).trailing_zeros() as i8);
+        }
+        tz
+    }
+}
+
+cfg_if! {
+    if #[cfg(target_pointer_width = "8")] {
+        impl_bit_manip! { sized: usizex2, usize, isizex2, isize, u8x2 }
+        impl_bit_manip! { sized: usizex4, usize, isizex4, isize, u8x4 }
+        impl_bit_manip! { sized: usizex8, usize, isizex8, isize, u8x8 }
+    } else if #[cfg(target_pointer_width = "16")] {
+        impl_bit_manip! { sized: usizex2, usize, isizex2, isize, u16x2 }
+        impl_bit_manip! { sized: usizex4, usize, isizex4, isize, u16x4 }
+        impl_bit_manip! { sized: usizex8, usize, isizex8, isize, u16x8 }
+    } else if #[cfg(target_pointer_width = "32")] {
+        impl_bit_manip! { sized: usizex2, usize, isizex2, isize, u32x2 }
+        impl_bit_manip! { sized: usizex4, usize, isizex4, isize, u32x4 }
+        impl_bit_manip! { sized: usizex8, usize, isizex8, isize, u32x8 }
+    } else if #[cfg(target_pointer_width = "64")] {
+        impl_bit_manip! { sized: usizex2, usize, isizex2, isize, u64x2 }
+        impl_bit_manip! { sized: usizex4, usize, isizex4, isize, u64x4 }
+        impl_bit_manip! { sized: usizex8, usize, isizex8, isize, u64x8 }
+    } else {
+        compile_error!("unsupported target_pointer_width");
+    }
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/codegen/llvm.rs.html b/src/packed_simd/codegen/llvm.rs.html new file mode 100644 index 000000000..a344a49a9 --- /dev/null +++ b/src/packed_simd/codegen/llvm.rs.html @@ -0,0 +1,205 @@ +llvm.rs.html -- source
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+
+//! LLVM's platform intrinsics
+#![allow(dead_code)]
+
+use crate::sealed::Shuffle;
+#[allow(unused_imports)] // FIXME: spurious warning?
+use crate::sealed::Simd;
+
+// Shuffle intrinsics: expanded in users' crates, therefore public.
+extern "platform-intrinsic" {
+    // FIXME: Passing this intrinsics an `idx` array with an index that is
+    // out-of-bounds will produce a monomorphization-time error.
+    // https://github.com/rust-lang-nursery/packed_simd/issues/21
+    pub fn simd_shuffle2<T, U>(x: T, y: T, idx: [u32; 2]) -> U
+    where
+        T: Simd,
+        <T as Simd>::Element: Shuffle<[u32; 2], Output = U>;
+
+    pub fn simd_shuffle4<T, U>(x: T, y: T, idx: [u32; 4]) -> U
+    where
+        T: Simd,
+        <T as Simd>::Element: Shuffle<[u32; 4], Output = U>;
+
+    pub fn simd_shuffle8<T, U>(x: T, y: T, idx: [u32; 8]) -> U
+    where
+        T: Simd,
+        <T as Simd>::Element: Shuffle<[u32; 8], Output = U>;
+
+    pub fn simd_shuffle16<T, U>(x: T, y: T, idx: [u32; 16]) -> U
+    where
+        T: Simd,
+        <T as Simd>::Element: Shuffle<[u32; 16], Output = U>;
+
+    pub fn simd_shuffle32<T, U>(x: T, y: T, idx: [u32; 32]) -> U
+    where
+        T: Simd,
+        <T as Simd>::Element: Shuffle<[u32; 32], Output = U>;
+
+    pub fn simd_shuffle64<T, U>(x: T, y: T, idx: [u32; 64]) -> U
+    where
+        T: Simd,
+        <T as Simd>::Element: Shuffle<[u32; 64], Output = U>;
+}
+
+pub use self::simd_shuffle16 as __shuffle_vector16;
+pub use self::simd_shuffle2 as __shuffle_vector2;
+pub use self::simd_shuffle32 as __shuffle_vector32;
+pub use self::simd_shuffle4 as __shuffle_vector4;
+pub use self::simd_shuffle64 as __shuffle_vector64;
+pub use self::simd_shuffle8 as __shuffle_vector8;
+
+extern "platform-intrinsic" {
+    crate fn simd_eq<T, U>(x: T, y: T) -> U;
+    crate fn simd_ne<T, U>(x: T, y: T) -> U;
+    crate fn simd_lt<T, U>(x: T, y: T) -> U;
+    crate fn simd_le<T, U>(x: T, y: T) -> U;
+    crate fn simd_gt<T, U>(x: T, y: T) -> U;
+    crate fn simd_ge<T, U>(x: T, y: T) -> U;
+
+    crate fn simd_insert<T, U>(x: T, idx: u32, val: U) -> T;
+    crate fn simd_extract<T, U>(x: T, idx: u32) -> U;
+
+    crate fn simd_cast<T, U>(x: T) -> U;
+
+    crate fn simd_add<T>(x: T, y: T) -> T;
+    crate fn simd_sub<T>(x: T, y: T) -> T;
+    crate fn simd_mul<T>(x: T, y: T) -> T;
+    crate fn simd_div<T>(x: T, y: T) -> T;
+    crate fn simd_rem<T>(x: T, y: T) -> T;
+    crate fn simd_shl<T>(x: T, y: T) -> T;
+    crate fn simd_shr<T>(x: T, y: T) -> T;
+    crate fn simd_and<T>(x: T, y: T) -> T;
+    crate fn simd_or<T>(x: T, y: T) -> T;
+    crate fn simd_xor<T>(x: T, y: T) -> T;
+
+    crate fn simd_reduce_add_unordered<T, U>(x: T) -> U;
+    crate fn simd_reduce_mul_unordered<T, U>(x: T) -> U;
+    crate fn simd_reduce_add_ordered<T, U>(x: T, acc: U) -> U;
+    crate fn simd_reduce_mul_ordered<T, U>(x: T, acc: U) -> U;
+    crate fn simd_reduce_min<T, U>(x: T) -> U;
+    crate fn simd_reduce_max<T, U>(x: T) -> U;
+    crate fn simd_reduce_min_nanless<T, U>(x: T) -> U;
+    crate fn simd_reduce_max_nanless<T, U>(x: T) -> U;
+    crate fn simd_reduce_and<T, U>(x: T) -> U;
+    crate fn simd_reduce_or<T, U>(x: T) -> U;
+    crate fn simd_reduce_xor<T, U>(x: T) -> U;
+    crate fn simd_reduce_all<T>(x: T) -> bool;
+    crate fn simd_reduce_any<T>(x: T) -> bool;
+
+    crate fn simd_select<M, T>(m: M, a: T, b: T) -> T;
+
+    crate fn simd_fmin<T>(a: T, b: T) -> T;
+    crate fn simd_fmax<T>(a: T, b: T) -> T;
+
+    crate fn simd_fsqrt<T>(a: T) -> T;
+    crate fn simd_fma<T>(a: T, b: T, c: T) -> T;
+
+    crate fn simd_gather<T, P, M>(value: T, pointers: P, mask: M) -> T;
+    crate fn simd_scatter<T, P, M>(value: T, pointers: P, mask: M);
+
+    crate fn simd_bitmask<T, U>(value: T) -> U;
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/codegen/math.rs.html b/src/packed_simd/codegen/math.rs.html new file mode 100644 index 000000000..cc887ed11 --- /dev/null +++ b/src/packed_simd/codegen/math.rs.html @@ -0,0 +1,9 @@ +math.rs.html -- source
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+//! Vertical math operations
+
+crate mod float;
+
+
\ No newline at end of file diff --git a/src/packed_simd/codegen/math/float.rs.html b/src/packed_simd/codegen/math/float.rs.html new file mode 100644 index 000000000..f3c17bb43 --- /dev/null +++ b/src/packed_simd/codegen/math/float.rs.html @@ -0,0 +1,41 @@ +float.rs.html -- source
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+
+//! Vertical floating-point math operations.
+#![allow(clippy::useless_transmute)]
+
+#[macro_use]
+crate mod macros;
+crate mod abs;
+crate mod cos;
+crate mod cos_pi;
+crate mod exp;
+crate mod ln;
+crate mod mul_add;
+crate mod mul_adde;
+crate mod powf;
+crate mod sin;
+crate mod sin_cos_pi;
+crate mod sin_pi;
+crate mod sqrt;
+crate mod sqrte;
+crate mod tanh;
+
+
\ No newline at end of file diff --git a/src/packed_simd/codegen/math/float/abs.rs.html b/src/packed_simd/codegen/math/float/abs.rs.html new file mode 100644 index 000000000..d6f8a81ef --- /dev/null +++ b/src/packed_simd/codegen/math/float/abs.rs.html @@ -0,0 +1,209 @@ +abs.rs.html -- source
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+
+//! Vertical floating-point `fabs`
+#![allow(unused)]
+
+// FIXME 64-bit 1 elem vectors fabs
+
+use crate::*;
+
+crate trait Abs {
+    fn abs(self) -> Self;
+}
+
+#[allow(improper_ctypes)]
+extern "C" {
+    #[link_name = "llvm.fabs.v2f32"]
+    fn fabs_v2f32(x: f32x2) -> f32x2;
+    #[link_name = "llvm.fabs.v4f32"]
+    fn fabs_v4f32(x: f32x4) -> f32x4;
+    #[link_name = "llvm.fabs.v8f32"]
+    fn fabs_v8f32(x: f32x8) -> f32x8;
+    #[link_name = "llvm.fabs.v16f32"]
+    fn fabs_v16f32(x: f32x16) -> f32x16;
+    /* FIXME 64-bit fabsgle elem vectors
+    #[link_name = "llvm.fabs.v1f64"]
+    fn fabs_v1f64(x: f64x1) -> f64x1;
+     */
+    #[link_name = "llvm.fabs.v2f64"]
+    fn fabs_v2f64(x: f64x2) -> f64x2;
+    #[link_name = "llvm.fabs.v4f64"]
+    fn fabs_v4f64(x: f64x4) -> f64x4;
+    #[link_name = "llvm.fabs.v8f64"]
+    fn fabs_v8f64(x: f64x8) -> f64x8;
+
+    #[link_name = "llvm.fabs.f32"]
+    fn fabs_f32(x: f32) -> f32;
+    #[link_name = "llvm.fabs.f64"]
+    fn fabs_f64(x: f64) -> f64;
+}
+
+gen_unary_impl_table!(Abs, abs);
+
+cfg_if! {
+    if #[cfg(target_arch = "s390x")] {
+        // FIXME: https://github.com/rust-lang-nursery/packed_simd/issues/14
+        impl_unary!(f32x2[f32; 2]: fabs_f32);
+        impl_unary!(f32x4[f32; 4]: fabs_f32);
+        impl_unary!(f32x8[f32; 8]: fabs_f32);
+        impl_unary!(f32x16[f32; 16]: fabs_f32);
+
+        impl_unary!(f64x2[f64; 2]: fabs_f64);
+        impl_unary!(f64x4[f64; 4]: fabs_f64);
+        impl_unary!(f64x8[f64; 8]: fabs_f64);
+    } else if #[cfg(all(target_arch = "x86_64", feature = "sleef-sys"))] {
+        use sleef_sys::*;
+        cfg_if! {
+            if #[cfg(target_feature = "avx2")] {
+                impl_unary!(f32x2[t => f32x4]: Sleef_fabsf4_avx2128);
+                impl_unary!(f32x16[h => f32x8]: Sleef_fabsf8_avx2);
+                impl_unary!(f64x8[h => f64x4]: Sleef_fabsd4_avx2);
+
+                impl_unary!(f32x4: Sleef_fabsf4_avx2128);
+                impl_unary!(f32x8: Sleef_fabsf8_avx2);
+                impl_unary!(f64x2: Sleef_fabsd2_avx2128);
+                impl_unary!(f64x4: Sleef_fabsd4_avx2);
+            } else if #[cfg(target_feature = "avx")] {
+                impl_unary!(f32x2[t => f32x4]: Sleef_fabsf4_sse4);
+                impl_unary!(f32x16[h => f32x8]: Sleef_fabsf8_avx);
+                impl_unary!(f64x8[h => f64x4]: Sleef_fabsd4_avx);
+
+                impl_unary!(f32x4: Sleef_fabsf4_sse4);
+                impl_unary!(f32x8: Sleef_fabsf8_avx);
+                impl_unary!(f64x2: Sleef_fabsd2_sse4);
+                impl_unary!(f64x4: Sleef_fabsd4_avx);
+            } else if #[cfg(target_feature = "sse4.2")] {
+                impl_unary!(f32x2[t => f32x4]: Sleef_fabsf4_sse4);
+                impl_unary!(f32x16[q => f32x4]: Sleef_fabsf4_sse4);
+                impl_unary!(f64x8[q => f64x2]: Sleef_fabsd2_sse4);
+
+                impl_unary!(f32x4: Sleef_fabsf4_sse4);
+                impl_unary!(f32x8[h => f32x4]: Sleef_fabsf4_sse4);
+                impl_unary!(f64x2: Sleef_fabsd2_sse4);
+                impl_unary!(f64x4[h => f64x2]: Sleef_fabsd2_sse4);
+            } else {
+                impl_unary!(f32x2[f32; 2]: fabs_f32);
+                impl_unary!(f32x16: fabs_v16f32);
+                impl_unary!(f64x8: fabs_v8f64);
+
+                impl_unary!(f32x4: fabs_v4f32);
+                impl_unary!(f32x8: fabs_v8f32);
+                impl_unary!(f64x2: fabs_v2f64);
+                impl_unary!(f64x4: fabs_v4f64);
+            }
+        }
+    } else {
+        impl_unary!(f32x2[f32; 2]: fabs_f32);
+        impl_unary!(f32x4: fabs_v4f32);
+        impl_unary!(f32x8: fabs_v8f32);
+        impl_unary!(f32x16: fabs_v16f32);
+
+        impl_unary!(f64x2: fabs_v2f64);
+        impl_unary!(f64x4: fabs_v4f64);
+        impl_unary!(f64x8: fabs_v8f64);
+    }
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/codegen/math/float/cos.rs.html b/src/packed_simd/codegen/math/float/cos.rs.html new file mode 100644 index 000000000..84e528626 --- /dev/null +++ b/src/packed_simd/codegen/math/float/cos.rs.html @@ -0,0 +1,209 @@ +cos.rs.html -- source
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+103
+
+//! Vertical floating-point `cos`
+#![allow(unused)]
+
+// FIXME 64-bit 1 elem vector cos
+
+use crate::*;
+
+crate trait Cos {
+    fn cos(self) -> Self;
+}
+
+#[allow(improper_ctypes)]
+extern "C" {
+    #[link_name = "llvm.cos.v2f32"]
+    fn cos_v2f32(x: f32x2) -> f32x2;
+    #[link_name = "llvm.cos.v4f32"]
+    fn cos_v4f32(x: f32x4) -> f32x4;
+    #[link_name = "llvm.cos.v8f32"]
+    fn cos_v8f32(x: f32x8) -> f32x8;
+    #[link_name = "llvm.cos.v16f32"]
+    fn cos_v16f32(x: f32x16) -> f32x16;
+    /* FIXME 64-bit cosgle elem vectors
+    #[link_name = "llvm.cos.v1f64"]
+    fn cos_v1f64(x: f64x1) -> f64x1;
+     */
+    #[link_name = "llvm.cos.v2f64"]
+    fn cos_v2f64(x: f64x2) -> f64x2;
+    #[link_name = "llvm.cos.v4f64"]
+    fn cos_v4f64(x: f64x4) -> f64x4;
+    #[link_name = "llvm.cos.v8f64"]
+    fn cos_v8f64(x: f64x8) -> f64x8;
+
+    #[link_name = "llvm.cos.f32"]
+    fn cos_f32(x: f32) -> f32;
+    #[link_name = "llvm.cos.f64"]
+    fn cos_f64(x: f64) -> f64;
+}
+
+gen_unary_impl_table!(Cos, cos);
+
+cfg_if! {
+    if #[cfg(target_arch = "s390x")] {
+        // FIXME: https://github.com/rust-lang-nursery/packed_simd/issues/14
+        impl_unary!(f32x2[f32; 2]: cos_f32);
+        impl_unary!(f32x4[f32; 4]: cos_f32);
+        impl_unary!(f32x8[f32; 8]: cos_f32);
+        impl_unary!(f32x16[f32; 16]: cos_f32);
+
+        impl_unary!(f64x2[f64; 2]: cos_f64);
+        impl_unary!(f64x4[f64; 4]: cos_f64);
+        impl_unary!(f64x8[f64; 8]: cos_f64);
+    } else if #[cfg(all(target_arch = "x86_64", feature = "sleef-sys"))] {
+        use sleef_sys::*;
+        cfg_if! {
+            if #[cfg(target_feature = "avx2")] {
+                impl_unary!(f32x2[t => f32x4]: Sleef_cosf4_u10avx2128);
+                impl_unary!(f32x16[h => f32x8]: Sleef_cosf8_u10avx2);
+                impl_unary!(f64x8[h => f64x4]: Sleef_cosd4_u10avx2);
+
+                impl_unary!(f32x4: Sleef_cosf4_u10avx2128);
+                impl_unary!(f32x8: Sleef_cosf8_u10avx2);
+                impl_unary!(f64x2: Sleef_cosd2_u10avx2128);
+                impl_unary!(f64x4: Sleef_cosd4_u10avx2);
+            } else if #[cfg(target_feature = "avx")] {
+                impl_unary!(f32x2[t => f32x4]: Sleef_cosf4_u10sse4);
+                impl_unary!(f32x16[h => f32x8]: Sleef_cosf8_u10avx);
+                impl_unary!(f64x8[h => f64x4]: Sleef_cosd4_u10avx);
+
+                impl_unary!(f32x4: Sleef_cosf4_u10sse4);
+                impl_unary!(f32x8: Sleef_cosf8_u10avx);
+                impl_unary!(f64x2: Sleef_cosd2_u10sse4);
+                impl_unary!(f64x4: Sleef_cosd4_u10avx);
+            } else if #[cfg(target_feature = "sse4.2")] {
+                impl_unary!(f32x2[t => f32x4]: Sleef_cosf4_u10sse4);
+                impl_unary!(f32x16[q => f32x4]: Sleef_cosf4_u10sse4);
+                impl_unary!(f64x8[q => f64x2]: Sleef_cosd2_u10sse4);
+
+                impl_unary!(f32x4: Sleef_cosf4_u10sse4);
+                impl_unary!(f32x8[h => f32x4]: Sleef_cosf4_u10sse4);
+                impl_unary!(f64x2: Sleef_cosd2_u10sse4);
+                impl_unary!(f64x4[h => f64x2]: Sleef_cosd2_u10sse4);
+            } else {
+                impl_unary!(f32x2[f32; 2]: cos_f32);
+                impl_unary!(f32x16: cos_v16f32);
+                impl_unary!(f64x8: cos_v8f64);
+
+                impl_unary!(f32x4: cos_v4f32);
+                impl_unary!(f32x8: cos_v8f32);
+                impl_unary!(f64x2: cos_v2f64);
+                impl_unary!(f64x4: cos_v4f64);
+            }
+        }
+    } else {
+        impl_unary!(f32x2[f32; 2]: cos_f32);
+        impl_unary!(f32x4: cos_v4f32);
+        impl_unary!(f32x8: cos_v8f32);
+        impl_unary!(f32x16: cos_v16f32);
+
+        impl_unary!(f64x2: cos_v2f64);
+        impl_unary!(f64x4: cos_v4f64);
+        impl_unary!(f64x8: cos_v8f64);
+    }
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/codegen/math/float/cos_pi.rs.html b/src/packed_simd/codegen/math/float/cos_pi.rs.html new file mode 100644 index 000000000..d756094ea --- /dev/null +++ b/src/packed_simd/codegen/math/float/cos_pi.rs.html @@ -0,0 +1,177 @@ +cos_pi.rs.html -- source
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+
+//! Vertical floating-point `cos`
+#![allow(unused)]
+
+// FIXME 64-bit 1 elem vectors cos_pi
+
+use crate::*;
+
+crate trait CosPi {
+    fn cos_pi(self) -> Self;
+}
+
+gen_unary_impl_table!(CosPi, cos_pi);
+
+macro_rules! impl_def {
+    ($vid:ident, $PI:path) => {
+        impl CosPi for $vid {
+            #[inline]
+            fn cos_pi(self) -> Self {
+                (self * Self::splat($PI)).cos()
+            }
+        }
+    };
+}
+macro_rules! impl_def32 {
+    ($vid:ident) => {
+        impl_def!($vid, crate::f32::consts::PI);
+    };
+}
+macro_rules! impl_def64 {
+    ($vid:ident) => {
+        impl_def!($vid, crate::f64::consts::PI);
+    };
+}
+
+cfg_if! {
+    if #[cfg(all(target_arch = "x86_64", feature = "sleef-sys"))] {
+        use sleef_sys::*;
+        cfg_if! {
+            if #[cfg(target_feature = "avx2")] {
+                impl_unary!(f32x2[t => f32x4]: Sleef_cospif4_u05avx2128);
+                impl_unary!(f32x16[h => f32x8]: Sleef_cospif8_u05avx2);
+                impl_unary!(f64x8[h => f64x4]: Sleef_cospid4_u05avx2);
+
+                impl_unary!(f32x4: Sleef_cospif4_u05avx2128);
+                impl_unary!(f32x8: Sleef_cospif8_u05avx2);
+                impl_unary!(f64x2: Sleef_cospid2_u05avx2128);
+                impl_unary!(f64x4: Sleef_cospid4_u05avx2);
+            } else if #[cfg(target_feature = "avx")] {
+                impl_unary!(f32x2[t => f32x4]: Sleef_cospif4_u05sse4);
+                impl_unary!(f32x16[h => f32x8]: Sleef_cospif8_u05avx);
+                impl_unary!(f64x8[h => f64x4]: Sleef_cospid4_u05avx);
+
+                impl_unary!(f32x4: Sleef_cospif4_u05sse4);
+                impl_unary!(f32x8: Sleef_cospif8_u05avx);
+                impl_unary!(f64x2: Sleef_cospid2_u05sse4);
+                impl_unary!(f64x4: Sleef_cospid4_u05avx);
+            } else if #[cfg(target_feature = "sse4.2")] {
+                impl_unary!(f32x2[t => f32x4]: Sleef_cospif4_u05sse4);
+                impl_unary!(f32x16[q => f32x4]: Sleef_cospif4_u05sse4);
+                impl_unary!(f64x8[q => f64x2]: Sleef_cospid2_u05sse4);
+
+                impl_unary!(f32x4: Sleef_cospif4_u05sse4);
+                impl_unary!(f32x8[h => f32x4]: Sleef_cospif4_u05sse4);
+                impl_unary!(f64x2: Sleef_cospid2_u05sse4);
+                impl_unary!(f64x4[h => f64x2]: Sleef_cospid2_u05sse4);
+            } else {
+                impl_def32!(f32x2);
+                impl_def32!(f32x4);
+                impl_def32!(f32x8);
+                impl_def32!(f32x16);
+
+                impl_def64!(f64x2);
+                impl_def64!(f64x4);
+                impl_def64!(f64x8);
+            }
+        }
+    } else {
+        impl_def32!(f32x2);
+        impl_def32!(f32x4);
+        impl_def32!(f32x8);
+        impl_def32!(f32x16);
+
+        impl_def64!(f64x2);
+        impl_def64!(f64x4);
+        impl_def64!(f64x8);
+    }
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/codegen/math/float/exp.rs.html b/src/packed_simd/codegen/math/float/exp.rs.html new file mode 100644 index 000000000..9e3d27457 --- /dev/null +++ b/src/packed_simd/codegen/math/float/exp.rs.html @@ -0,0 +1,227 @@ +exp.rs.html -- source
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+112
+
+//! Vertical floating-point `exp`
+#![allow(unused)]
+
+// FIXME 64-bit expgle elem vectors misexpg
+
+use crate::*;
+
+crate trait Exp {
+    fn exp(self) -> Self;
+}
+
+#[allow(improper_ctypes)]
+extern "C" {
+    #[link_name = "llvm.exp.v2f32"]
+    fn exp_v2f32(x: f32x2) -> f32x2;
+    #[link_name = "llvm.exp.v4f32"]
+    fn exp_v4f32(x: f32x4) -> f32x4;
+    #[link_name = "llvm.exp.v8f32"]
+    fn exp_v8f32(x: f32x8) -> f32x8;
+    #[link_name = "llvm.exp.v16f32"]
+    fn exp_v16f32(x: f32x16) -> f32x16;
+    /* FIXME 64-bit expgle elem vectors
+    #[link_name = "llvm.exp.v1f64"]
+    fn exp_v1f64(x: f64x1) -> f64x1;
+     */
+    #[link_name = "llvm.exp.v2f64"]
+    fn exp_v2f64(x: f64x2) -> f64x2;
+    #[link_name = "llvm.exp.v4f64"]
+    fn exp_v4f64(x: f64x4) -> f64x4;
+    #[link_name = "llvm.exp.v8f64"]
+    fn exp_v8f64(x: f64x8) -> f64x8;
+
+    #[link_name = "llvm.exp.f32"]
+    fn exp_f32(x: f32) -> f32;
+    #[link_name = "llvm.exp.f64"]
+    fn exp_f64(x: f64) -> f64;
+}
+
+gen_unary_impl_table!(Exp, exp);
+
+cfg_if! {
+    if #[cfg(target_arch = "s390x")] {
+        // FIXME: https://github.com/rust-lang-nursery/packed_simd/issues/14
+        impl_unary!(f32x2[f32; 2]: exp_f32);
+        impl_unary!(f32x4[f32; 4]: exp_f32);
+        impl_unary!(f32x8[f32; 8]: exp_f32);
+        impl_unary!(f32x16[f32; 16]: exp_f32);
+
+        impl_unary!(f64x2[f64; 2]: exp_f64);
+        impl_unary!(f64x4[f64; 4]: exp_f64);
+        impl_unary!(f64x8[f64; 8]: exp_f64);
+    } else if #[cfg(all(target_arch = "x86_64", feature = "sleef-sys"))] {
+        use sleef_sys::*;
+        cfg_if! {
+            if #[cfg(target_feature = "avx2")] {
+                impl_unary!(f32x2[t => f32x4]: Sleef_expf4_u10avx2128);
+                impl_unary!(f32x16[h => f32x8]: Sleef_expf8_u10avx2);
+                impl_unary!(f64x8[h => f64x4]: Sleef_expd4_u10avx2);
+
+                impl_unary!(f32x4: Sleef_expf4_u10avx2128);
+                impl_unary!(f32x8: Sleef_expf8_u10avx2);
+                impl_unary!(f64x2: Sleef_expd2_u10avx2128);
+                impl_unary!(f64x4: Sleef_expd4_u10avx2);
+            } else if #[cfg(target_feature = "avx")] {
+                impl_unary!(f32x2[t => f32x4]: Sleef_expf4_u10sse4);
+                impl_unary!(f32x16[h => f32x8]: Sleef_expf8_u10avx);
+                impl_unary!(f64x8[h => f64x4]: Sleef_expd4_u10avx);
+
+                impl_unary!(f32x4: Sleef_expf4_u10sse4);
+                impl_unary!(f32x8: Sleef_expf8_u10avx);
+                impl_unary!(f64x2: Sleef_expd2_u10sse4);
+                impl_unary!(f64x4: Sleef_expd4_u10avx);
+            } else if #[cfg(target_feature = "sse4.2")] {
+                impl_unary!(f32x2[t => f32x4]: Sleef_expf4_u10sse4);
+                impl_unary!(f32x16[q => f32x4]: Sleef_expf4_u10sse4);
+                impl_unary!(f64x8[q => f64x2]: Sleef_expd2_u10sse4);
+
+                impl_unary!(f32x4: Sleef_expf4_u10sse4);
+                impl_unary!(f32x8[h => f32x4]: Sleef_expf4_u10sse4);
+                impl_unary!(f64x2: Sleef_expd2_u10sse4);
+                impl_unary!(f64x4[h => f64x2]: Sleef_expd2_u10sse4);
+            } else if #[cfg(target_feature = "sse2")] {
+                impl_unary!(f32x2[t => f32x4]: Sleef_expf4_u10sse2);
+                impl_unary!(f32x16[q => f32x4]: Sleef_expf4_u10sse2);
+                impl_unary!(f64x8[q => f64x2]: Sleef_expd2_u10sse2);
+
+                impl_unary!(f32x4: Sleef_expf4_u10sse2);
+                impl_unary!(f32x8[h => f32x4]: Sleef_expf4_u10sse2);
+                impl_unary!(f64x2: Sleef_expd2_u10sse2);
+                impl_unary!(f64x4[h => f64x2]: Sleef_expd2_u10sse2);
+            } else {
+                impl_unary!(f32x2[f32; 2]: exp_f32);
+                impl_unary!(f32x16: exp_v16f32);
+                impl_unary!(f64x8: exp_v8f64);
+
+                impl_unary!(f32x4: exp_v4f32);
+                impl_unary!(f32x8: exp_v8f32);
+                impl_unary!(f64x2: exp_v2f64);
+                impl_unary!(f64x4: exp_v4f64);
+            }
+        }
+    } else {
+        impl_unary!(f32x2[f32; 2]: exp_f32);
+        impl_unary!(f32x4: exp_v4f32);
+        impl_unary!(f32x8: exp_v8f32);
+        impl_unary!(f32x16: exp_v16f32);
+
+        impl_unary!(f64x2: exp_v2f64);
+        impl_unary!(f64x4: exp_v4f64);
+        impl_unary!(f64x8: exp_v8f64);
+    }
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/codegen/math/float/ln.rs.html b/src/packed_simd/codegen/math/float/ln.rs.html new file mode 100644 index 000000000..d307a8cf3 --- /dev/null +++ b/src/packed_simd/codegen/math/float/ln.rs.html @@ -0,0 +1,227 @@ +ln.rs.html -- source
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+
+//! Vertical floating-point `ln`
+#![allow(unused)]
+
+// FIXME 64-bit lngle elem vectors mislng
+
+use crate::*;
+
+crate trait Ln {
+    fn ln(self) -> Self;
+}
+
+#[allow(improper_ctypes)]
+extern "C" {
+    #[link_name = "llvm.log.v2f32"]
+    fn ln_v2f32(x: f32x2) -> f32x2;
+    #[link_name = "llvm.log.v4f32"]
+    fn ln_v4f32(x: f32x4) -> f32x4;
+    #[link_name = "llvm.log.v8f32"]
+    fn ln_v8f32(x: f32x8) -> f32x8;
+    #[link_name = "llvm.log.v16f32"]
+    fn ln_v16f32(x: f32x16) -> f32x16;
+    /* FIXME 64-bit lngle elem vectors
+    #[link_name = "llvm.log.v1f64"]
+    fn ln_v1f64(x: f64x1) -> f64x1;
+     */
+    #[link_name = "llvm.log.v2f64"]
+    fn ln_v2f64(x: f64x2) -> f64x2;
+    #[link_name = "llvm.log.v4f64"]
+    fn ln_v4f64(x: f64x4) -> f64x4;
+    #[link_name = "llvm.log.v8f64"]
+    fn ln_v8f64(x: f64x8) -> f64x8;
+
+    #[link_name = "llvm.log.f32"]
+    fn ln_f32(x: f32) -> f32;
+    #[link_name = "llvm.log.f64"]
+    fn ln_f64(x: f64) -> f64;
+}
+
+gen_unary_impl_table!(Ln, ln);
+
+cfg_if! {
+    if #[cfg(target_arch = "s390x")] {
+        // FIXME: https://github.com/rust-lang-nursery/packed_simd/issues/14
+        impl_unary!(f32x2[f32; 2]: ln_f32);
+        impl_unary!(f32x4[f32; 4]: ln_f32);
+        impl_unary!(f32x8[f32; 8]: ln_f32);
+        impl_unary!(f32x16[f32; 16]: ln_f32);
+
+        impl_unary!(f64x2[f64; 2]: ln_f64);
+        impl_unary!(f64x4[f64; 4]: ln_f64);
+        impl_unary!(f64x8[f64; 8]: ln_f64);
+    } else if #[cfg(all(target_arch = "x86_64", feature = "sleef-sys"))] {
+        use sleef_sys::*;
+        cfg_if! {
+            if #[cfg(target_feature = "avx2")] {
+                impl_unary!(f32x2[t => f32x4]: Sleef_logf4_u10avx2128);
+                impl_unary!(f32x16[h => f32x8]: Sleef_logf8_u10avx2);
+                impl_unary!(f64x8[h => f64x4]: Sleef_logd4_u10avx2);
+
+                impl_unary!(f32x4: Sleef_logf4_u10avx2128);
+                impl_unary!(f32x8: Sleef_logf8_u10avx2);
+                impl_unary!(f64x2: Sleef_logd2_u10avx2128);
+                impl_unary!(f64x4: Sleef_logd4_u10avx2);
+            } else if #[cfg(target_feature = "avx")] {
+                impl_unary!(f32x2[t => f32x4]: Sleef_logf4_u10sse4);
+                impl_unary!(f32x16[h => f32x8]: Sleef_logf8_u10avx);
+                impl_unary!(f64x8[h => f64x4]: Sleef_logd4_u10avx);
+
+                impl_unary!(f32x4: Sleef_logf4_u10sse4);
+                impl_unary!(f32x8: Sleef_logf8_u10avx);
+                impl_unary!(f64x2: Sleef_logd2_u10sse4);
+                impl_unary!(f64x4: Sleef_logd4_u10avx);
+            } else if #[cfg(target_feature = "sse4.2")] {
+                impl_unary!(f32x2[t => f32x4]: Sleef_logf4_u10sse4);
+                impl_unary!(f32x16[q => f32x4]: Sleef_logf4_u10sse4);
+                impl_unary!(f64x8[q => f64x2]: Sleef_logd2_u10sse4);
+
+                impl_unary!(f32x4: Sleef_logf4_u10sse4);
+                impl_unary!(f32x8[h => f32x4]: Sleef_logf4_u10sse4);
+                impl_unary!(f64x2: Sleef_logd2_u10sse4);
+                impl_unary!(f64x4[h => f64x2]: Sleef_logd2_u10sse4);
+            } else if #[cfg(target_feature = "sse2")] {
+                impl_unary!(f32x2[t => f32x4]: Sleef_logf4_u10sse2);
+                impl_unary!(f32x16[q => f32x4]: Sleef_logf4_u10sse2);
+                impl_unary!(f64x8[q => f64x2]: Sleef_logd2_u10sse2);
+
+                impl_unary!(f32x4: Sleef_logf4_u10sse2);
+                impl_unary!(f32x8[h => f32x4]: Sleef_logf4_u10sse2);
+                impl_unary!(f64x2: Sleef_logd2_u10sse2);
+                impl_unary!(f64x4[h => f64x2]: Sleef_logd2_u10sse2);
+            } else {
+                impl_unary!(f32x2[f32; 2]: ln_f32);
+                impl_unary!(f32x16: ln_v16f32);
+                impl_unary!(f64x8: ln_v8f64);
+
+                impl_unary!(f32x4: ln_v4f32);
+                impl_unary!(f32x8: ln_v8f32);
+                impl_unary!(f64x2: ln_v2f64);
+                impl_unary!(f64x4: ln_v4f64);
+            }
+        }
+    } else {
+        impl_unary!(f32x2[f32; 2]: ln_f32);
+        impl_unary!(f32x4: ln_v4f32);
+        impl_unary!(f32x8: ln_v8f32);
+        impl_unary!(f32x16: ln_v16f32);
+
+        impl_unary!(f64x2: ln_v2f64);
+        impl_unary!(f64x4: ln_v4f64);
+        impl_unary!(f64x8: ln_v8f64);
+    }
+}
+
+
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+
+//! Utility macros
+#![allow(unused)]
+
+
+macro_rules! impl_unary_ {
+    // implementation mapping 1:1
+    (vec | $trait_id:ident, $trait_method:ident, $vec_id:ident,
+     $fun:ident) => {
+        impl $trait_id for $vec_id {
+            #[inline]
+            fn $trait_method(self) -> Self {
+                unsafe {
+                    use crate::mem::transmute;
+                    transmute($fun(transmute(self)))
+                }
+            }
+        }
+    };
+    // implementation mapping 1:1 for when `$fun` is a generic function
+    // like some of the fp math rustc intrinsics (e.g. `fn fun<T>(x: T) -> T`).
+    (gen | $trait_id:ident, $trait_method:ident, $vec_id:ident,
+     $fun:ident) => {
+        impl $trait_id for $vec_id {
+            #[inline]
+            fn $trait_method(self) -> Self {
+                unsafe {
+                    use crate::mem::transmute;
+                    transmute($fun(self.0))
+                }
+            }
+        }
+    };
+    (scalar | $trait_id:ident, $trait_method:ident,
+     $vec_id:ident, [$sid:ident; $scount:expr], $fun:ident) => {
+        impl $trait_id for $vec_id {
+            #[inline]
+            fn $trait_method(self) -> Self {
+                unsafe {
+                    union U {
+                        vec: $vec_id,
+                        scalars: [$sid; $scount],
+                    }
+                    let mut scalars = U { vec: self }.scalars;
+                    for i in &mut scalars {
+                        *i = $fun(*i);
+                    }
+                    U { scalars }.vec
+                }
+            }
+        }
+    };
+    // implementation calling fun twice on each of the vector halves:
+    (halves | $trait_id:ident, $trait_method:ident, $vec_id:ident,
+     $vech_id:ident, $fun:ident) => {
+        impl $trait_id for $vec_id {
+            #[inline]
+            fn $trait_method(self) -> Self {
+                unsafe {
+                    use crate::mem::transmute;
+                    union U {
+                        vec: $vec_id,
+                        halves: [$vech_id; 2],
+                    }
+
+                    let mut halves = U { vec: self }.halves;
+
+                    *halves.get_unchecked_mut(0) =
+                        transmute($fun(transmute(*halves.get_unchecked(0))));
+                    *halves.get_unchecked_mut(1) =
+                        transmute($fun(transmute(*halves.get_unchecked(1))));
+
+                    U { halves }.vec
+                }
+            }
+        }
+    };
+    // implementation calling fun four times on each of the vector quarters:
+    (quarter | $trait_id:ident, $trait_method:ident, $vec_id:ident,
+     $vecq_id:ident, $fun:ident) => {
+        impl $trait_id for $vec_id {
+            #[inline]
+            fn $trait_method(self) -> Self {
+                unsafe {
+                    use crate::mem::transmute;
+                    union U {
+                        vec: $vec_id,
+                        quarters: [$vecq_id; 4],
+                    }
+
+                    let mut quarters = U { vec: self }.quarters;
+
+                    *quarters.get_unchecked_mut(0) =
+                        transmute($fun(transmute(*quarters.get_unchecked(0))));
+                    *quarters.get_unchecked_mut(1) =
+                        transmute($fun(transmute(*quarters.get_unchecked(1))));
+                    *quarters.get_unchecked_mut(2) =
+                        transmute($fun(transmute(*quarters.get_unchecked(2))));
+                    *quarters.get_unchecked_mut(3) =
+                        transmute($fun(transmute(*quarters.get_unchecked(3))));
+
+                    U { quarters }.vec
+                }
+            }
+        }
+    };
+    // implementation calling fun once on a vector twice as large:
+    (twice | $trait_id:ident, $trait_method:ident, $vec_id:ident,
+     $vect_id:ident, $fun:ident) => {
+        impl $trait_id for $vec_id {
+            #[inline]
+            fn $trait_method(self) -> Self {
+                unsafe {
+                    use crate::mem::{transmute, uninitialized};
+
+                    union U {
+                        vec: [$vec_id; 2],
+                        twice: $vect_id,
+                    }
+
+                    let twice = U { vec: [self, uninitialized()] }.twice;
+                    let twice = transmute($fun(transmute(twice)));
+
+                    *(U { twice }.vec.get_unchecked(0))
+                }
+            }
+        }
+    };
+}
+
+macro_rules! gen_unary_impl_table {
+    ($trait_id:ident, $trait_method:ident) => {
+        macro_rules! impl_unary {
+            ($vid:ident: $fun:ident) => {
+                impl_unary_!(vec | $trait_id, $trait_method, $vid, $fun);
+            };
+            ($vid:ident[g]: $fun:ident) => {
+                impl_unary_!(gen | $trait_id, $trait_method, $vid, $fun);
+            };
+            ($vid:ident[$sid:ident; $sc:expr]: $fun:ident) => {
+                impl_unary_!(
+                    scalar | $trait_id,
+                    $trait_method,
+                    $vid,
+                    [$sid; $sc],
+                    $fun
+                );
+            };
+            ($vid:ident[s]: $fun:ident) => {
+                impl_unary_!(scalar | $trait_id, $trait_method, $vid, $fun);
+            };
+            ($vid:ident[h => $vid_h:ident]: $fun:ident) => {
+                impl_unary_!(
+                    halves | $trait_id,
+                    $trait_method,
+                    $vid,
+                    $vid_h,
+                    $fun
+                );
+            };
+            ($vid:ident[q => $vid_q:ident]: $fun:ident) => {
+                impl_unary_!(
+                    quarter | $trait_id,
+                    $trait_method,
+                    $vid,
+                    $vid_q,
+                    $fun
+                );
+            };
+            ($vid:ident[t => $vid_t:ident]: $fun:ident) => {
+                impl_unary_!(
+                    twice | $trait_id,
+                    $trait_method,
+                    $vid,
+                    $vid_t,
+                    $fun
+                );
+            };
+        }
+    };
+}
+
+macro_rules! impl_tertiary_ {
+    // implementation mapping 1:1
+    (vec | $trait_id:ident, $trait_method:ident, $vec_id:ident,
+     $fun:ident) => {
+        impl $trait_id for $vec_id {
+            #[inline]
+            fn $trait_method(self, y: Self, z: Self) -> Self {
+                unsafe {
+                    use crate::mem::transmute;
+                    transmute($fun(
+                        transmute(self),
+                        transmute(y),
+                        transmute(z),
+                    ))
+                }
+            }
+        }
+    };
+    (scalar | $trait_id:ident, $trait_method:ident,
+     $vec_id:ident, [$sid:ident; $scount:expr], $fun:ident) => {
+        impl $trait_id for $vec_id {
+            #[inline]
+            fn $trait_method(self, y: Self, z: Self) -> Self {
+                unsafe {
+                    union U {
+                        vec: $vec_id,
+                        scalars: [$sid; $scount],
+                    }
+                    let mut x = U { vec: self }.scalars;
+                    let y = U { vec: y }.scalars;
+                    let z = U { vec: z }.scalars;
+                    for (x, (y, z)) in (&mut scalars).zip(&y).zip(&z) {
+                        *i = $fun(*i, *y, *z);
+                    }
+                    U { vec: x }.vec
+                }
+            }
+        }
+    };
+    // implementation calling fun twice on each of the vector halves:
+    (halves | $trait_id:ident, $trait_method:ident, $vec_id:ident,
+     $vech_id:ident, $fun:ident) => {
+        impl $trait_id for $vec_id {
+            #[inline]
+            fn $trait_method(self, y: Self, z: Self) -> Self {
+                unsafe {
+                    use crate::mem::transmute;
+                    union U {
+                        vec: $vec_id,
+                        halves: [$vech_id; 2],
+                    }
+
+                    let mut x_halves = U { vec: self }.halves;
+                    let y_halves = U { vec: y }.halves;
+                    let z_halves = U { vec: z }.halves;
+
+                    *x_halves.get_unchecked_mut(0) = transmute($fun(
+                        transmute(*x_halves.get_unchecked(0)),
+                        transmute(*y_halves.get_unchecked(0)),
+                        transmute(*z_halves.get_unchecked(0)),
+                    ));
+                    *x_halves.get_unchecked_mut(1) = transmute($fun(
+                        transmute(*x_halves.get_unchecked(1)),
+                        transmute(*y_halves.get_unchecked(1)),
+                        transmute(*z_halves.get_unchecked(1)),
+                    ));
+
+                    U { halves: x_halves }.vec
+                }
+            }
+        }
+    };
+    // implementation calling fun four times on each of the vector quarters:
+    (quarter | $trait_id:ident, $trait_method:ident, $vec_id:ident,
+     $vecq_id:ident, $fun:ident) => {
+        impl $trait_id for $vec_id {
+            #[inline]
+            fn $trait_method(self, y: Self, z: Self) -> Self {
+                unsafe {
+                    use crate::mem::transmute;
+                    union U {
+                        vec: $vec_id,
+                        quarters: [$vecq_id; 4],
+                    }
+
+                    let mut x_quarters = U { vec: self }.quarters;
+                    let y_quarters = U { vec: y }.quarters;
+                    let z_quarters = U { vec: z }.quarters;
+
+                    *x_quarters.get_unchecked_mut(0) = transmute($fun(
+                        transmute(*x_quarters.get_unchecked(0)),
+                        transmute(*y_quarters.get_unchecked(0)),
+                        transmute(*z_quarters.get_unchecked(0)),
+                    ));
+
+                    *x_quarters.get_unchecked_mut(1) = transmute($fun(
+                        transmute(*x_quarters.get_unchecked(1)),
+                        transmute(*y_quarters.get_unchecked(1)),
+                        transmute(*z_quarters.get_unchecked(1)),
+                    ));
+
+                    *x_quarters.get_unchecked_mut(2) = transmute($fun(
+                        transmute(*x_quarters.get_unchecked(2)),
+                        transmute(*y_quarters.get_unchecked(2)),
+                        transmute(*z_quarters.get_unchecked(2)),
+                    ));
+
+                    *x_quarters.get_unchecked_mut(3) = transmute($fun(
+                        transmute(*x_quarters.get_unchecked(3)),
+                        transmute(*y_quarters.get_unchecked(3)),
+                        transmute(*z_quarters.get_unchecked(3)),
+                    ));
+
+                    U { quarters: x_quarters }.vec
+                }
+            }
+        }
+    };
+    // implementation calling fun once on a vector twice as large:
+    (twice | $trait_id:ident, $trait_method:ident, $vec_id:ident,
+     $vect_id:ident, $fun:ident) => {
+        impl $trait_id for $vec_id {
+            #[inline]
+            fn $trait_method(self, y: Self, z: Self) -> Self {
+                unsafe {
+                    use crate::mem::{transmute, uninitialized};
+
+                    union U {
+                        vec: [$vec_id; 2],
+                        twice: $vect_id,
+                    }
+
+                    let x_twice = U { vec: [self, uninitialized()] }.twice;
+                    let y_twice = U { vec: [y, uninitialized()] }.twice;
+                    let z_twice = U { vec: [z, uninitialized()] }.twice;
+                    let twice: $vect_id = transmute($fun(
+                        transmute(x_twice),
+                        transmute(y_twice),
+                        transmute(z_twice),
+                    ));
+
+                    *(U { twice }.vec.get_unchecked(0))
+                }
+            }
+        }
+    };
+}
+
+macro_rules! gen_tertiary_impl_table {
+    ($trait_id:ident, $trait_method:ident) => {
+        macro_rules! impl_tertiary {
+            ($vid:ident: $fun:ident) => {
+                impl_tertiary_!(vec | $trait_id, $trait_method, $vid, $fun);
+            };
+            ($vid:ident[$sid:ident; $sc:expr]: $fun:ident) => {
+                impl_tertiary_!(
+                    scalar | $trait_id,
+                    $trait_method,
+                    $vid,
+                    [$sid; $sc],
+                    $fun
+                );
+            };
+            ($vid:ident[s]: $fun:ident) => {
+                impl_tertiary_!(scalar | $trait_id, $trait_method, $vid, $fun);
+            };
+            ($vid:ident[h => $vid_h:ident]: $fun:ident) => {
+                impl_tertiary_!(
+                    halves | $trait_id,
+                    $trait_method,
+                    $vid,
+                    $vid_h,
+                    $fun
+                );
+            };
+            ($vid:ident[q => $vid_q:ident]: $fun:ident) => {
+                impl_tertiary_!(
+                    quarter | $trait_id,
+                    $trait_method,
+                    $vid,
+                    $vid_q,
+                    $fun
+                );
+            };
+            ($vid:ident[t => $vid_t:ident]: $fun:ident) => {
+                impl_tertiary_!(
+                    twice | $trait_id,
+                    $trait_method,
+                    $vid,
+                    $vid_t,
+                    $fun
+                );
+            };
+        }
+    };
+}
+
+macro_rules! impl_binary_ {
+    // implementation mapping 1:1
+    (vec | $trait_id:ident, $trait_method:ident, $vec_id:ident,
+     $fun:ident) => {
+        impl $trait_id for $vec_id {
+            #[inline]
+            fn $trait_method(self, y: Self) -> Self {
+                unsafe {
+                    use crate::mem::transmute;
+                    transmute($fun(transmute(self), transmute(y)))
+                }
+            }
+        }
+    };
+    (scalar | $trait_id:ident, $trait_method:ident,
+     $vec_id:ident, [$sid:ident; $scount:expr], $fun:ident) => {
+        impl $trait_id for $vec_id {
+            #[inline]
+            fn $trait_method(self, y: Self) -> Self {
+                unsafe {
+                    union U {
+                        vec: $vec_id,
+                        scalars: [$sid; $scount],
+                    }
+                    let mut x = U { vec: self }.scalars;
+                    let y = U { vec: y }.scalars;
+                    for (x, y) in x.iter_mut().zip(&y) {
+                        *x = $fun(*x, *y);
+                    }
+                    U { scalars: x }.vec
+                }
+            }
+        }
+    };
+    // implementation calling fun twice on each of the vector halves:
+    (halves | $trait_id:ident, $trait_method:ident, $vec_id:ident,
+     $vech_id:ident, $fun:ident) => {
+        impl $trait_id for $vec_id {
+            #[inline]
+            fn $trait_method(self, y: Self) -> Self {
+                unsafe {
+                    use crate::mem::transmute;
+                    union U {
+                        vec: $vec_id,
+                        halves: [$vech_id; 2],
+                    }
+
+                    let mut x_halves = U { vec: self }.halves;
+                    let y_halves = U { vec: y }.halves;
+
+                    *x_halves.get_unchecked_mut(0) = transmute($fun(
+                        transmute(*x_halves.get_unchecked(0)),
+                        transmute(*y_halves.get_unchecked(0)),
+                    ));
+                    *x_halves.get_unchecked_mut(1) = transmute($fun(
+                        transmute(*x_halves.get_unchecked(1)),
+                        transmute(*y_halves.get_unchecked(1)),
+                    ));
+
+                    U { halves: x_halves }.vec
+                }
+            }
+        }
+    };
+    // implementation calling fun four times on each of the vector quarters:
+    (quarter | $trait_id:ident, $trait_method:ident, $vec_id:ident,
+     $vecq_id:ident, $fun:ident) => {
+        impl $trait_id for $vec_id {
+            #[inline]
+            fn $trait_method(self, y: Self) -> Self {
+                unsafe {
+                    use crate::mem::transmute;
+                    union U {
+                        vec: $vec_id,
+                        quarters: [$vecq_id; 4],
+                    }
+
+                    let mut x_quarters = U { vec: self }.quarters;
+                    let y_quarters = U { vec: y }.quarters;
+
+                    *x_quarters.get_unchecked_mut(0) = transmute($fun(
+                        transmute(*x_quarters.get_unchecked(0)),
+                        transmute(*y_quarters.get_unchecked(0)),
+                    ));
+
+                    *x_quarters.get_unchecked_mut(1) = transmute($fun(
+                        transmute(*x_quarters.get_unchecked(1)),
+                        transmute(*y_quarters.get_unchecked(1)),
+                    ));
+
+                    *x_quarters.get_unchecked_mut(2) = transmute($fun(
+                        transmute(*x_quarters.get_unchecked(2)),
+                        transmute(*y_quarters.get_unchecked(2)),
+                    ));
+
+                    *x_quarters.get_unchecked_mut(3) = transmute($fun(
+                        transmute(*x_quarters.get_unchecked(3)),
+                        transmute(*y_quarters.get_unchecked(3)),
+                    ));
+
+                    U { quarters: x_quarters }.vec
+                }
+            }
+        }
+    };
+    // implementation calling fun once on a vector twice as large:
+    (twice | $trait_id:ident, $trait_method:ident, $vec_id:ident,
+     $vect_id:ident, $fun:ident) => {
+        impl $trait_id for $vec_id {
+            #[inline]
+            fn $trait_method(self, y: Self) -> Self {
+                unsafe {
+                    use crate::mem::{transmute, uninitialized};
+
+                    union U {
+                        vec: [$vec_id; 2],
+                        twice: $vect_id,
+                    }
+
+                    let x_twice = U { vec: [self, uninitialized()] }.twice;
+                    let y_twice = U { vec: [y, uninitialized()] }.twice;
+                    let twice: $vect_id = transmute($fun(
+                        transmute(x_twice),
+                        transmute(y_twice),
+                    ));
+
+                    *(U { twice }.vec.get_unchecked(0))
+                }
+            }
+        }
+    };
+}
+
+macro_rules! gen_binary_impl_table {
+    ($trait_id:ident, $trait_method:ident) => {
+        macro_rules! impl_binary {
+            ($vid:ident: $fun:ident) => {
+                impl_binary_!(vec | $trait_id, $trait_method, $vid, $fun);
+            };
+            ($vid:ident[$sid:ident; $sc:expr]: $fun:ident) => {
+                impl_binary_!(
+                    scalar | $trait_id,
+                    $trait_method,
+                    $vid,
+                    [$sid; $sc],
+                    $fun
+                );
+            };
+            ($vid:ident[s]: $fun:ident) => {
+                impl_binary_!(scalar | $trait_id, $trait_method, $vid, $fun);
+            };
+            ($vid:ident[h => $vid_h:ident]: $fun:ident) => {
+                impl_binary_!(
+                    halves | $trait_id,
+                    $trait_method,
+                    $vid,
+                    $vid_h,
+                    $fun
+                );
+            };
+            ($vid:ident[q => $vid_q:ident]: $fun:ident) => {
+                impl_binary_!(
+                    quarter | $trait_id,
+                    $trait_method,
+                    $vid,
+                    $vid_q,
+                    $fun
+                );
+            };
+            ($vid:ident[t => $vid_t:ident]: $fun:ident) => {
+                impl_binary_!(
+                    twice | $trait_id,
+                    $trait_method,
+                    $vid,
+                    $vid_t,
+                    $fun
+                );
+            };
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/codegen/math/float/mul_add.rs.html b/src/packed_simd/codegen/math/float/mul_add.rs.html new file mode 100644 index 000000000..5bca4fd69 --- /dev/null +++ b/src/packed_simd/codegen/math/float/mul_add.rs.html @@ -0,0 +1,221 @@ +mul_add.rs.html -- source
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+
+//! Vertical floating-point `mul_add`
+#![allow(unused)]
+use crate::*;
+
+// FIXME: 64-bit 1 element mul_add
+
+crate trait MulAdd {
+    fn mul_add(self, y: Self, z: Self) -> Self;
+}
+
+#[cfg(not(target_arch = "s390x"))]
+#[allow(improper_ctypes)]
+extern "C" {
+    #[link_name = "llvm.fma.v2f32"]
+    fn fma_v2f32(x: f32x2, y: f32x2, z: f32x2) -> f32x2;
+    #[link_name = "llvm.fma.v4f32"]
+    fn fma_v4f32(x: f32x4, y: f32x4, z: f32x4) -> f32x4;
+    #[link_name = "llvm.fma.v8f32"]
+    fn fma_v8f32(x: f32x8, y: f32x8, z: f32x8) -> f32x8;
+    #[link_name = "llvm.fma.v16f32"]
+    fn fma_v16f32(x: f32x16, y: f32x16, z: f32x16) -> f32x16;
+    /* FIXME 64-bit single elem vectors
+    #[link_name = "llvm.fma.v1f64"]
+    fn fma_v1f64(x: f64x1, y: f64x1, z: f64x1) -> f64x1;
+    */
+    #[link_name = "llvm.fma.v2f64"]
+    fn fma_v2f64(x: f64x2, y: f64x2, z: f64x2) -> f64x2;
+    #[link_name = "llvm.fma.v4f64"]
+    fn fma_v4f64(x: f64x4, y: f64x4, z: f64x4) -> f64x4;
+    #[link_name = "llvm.fma.v8f64"]
+    fn fma_v8f64(x: f64x8, y: f64x8, z: f64x8) -> f64x8;
+}
+
+gen_tertiary_impl_table!(MulAdd, mul_add);
+
+cfg_if! {
+    if #[cfg(target_arch = "s390x")] {
+        // FIXME: https://github.com/rust-lang-nursery/packed_simd/issues/14
+        macro_rules! impl_broken {
+            ($id:ident) => {
+                impl MulAdd for $id {
+                    #[inline]
+                    fn mul_add(self, y: Self, z: Self) -> Self {
+                        self * y + z
+                    }
+                }
+            };
+        }
+
+        impl_broken!(f32x2);
+        impl_broken!(f32x4);
+        impl_broken!(f32x8);
+        impl_broken!(f32x16);
+
+        impl_broken!(f64x2);
+        impl_broken!(f64x4);
+        impl_broken!(f64x8);
+    } else if #[cfg(all(target_arch = "x86_64", feature = "sleef-sys"))] {
+        use sleef_sys::*;
+        cfg_if! {
+            if #[cfg(target_feature = "avx2")] {
+                impl_tertiary!(f32x2[t => f32x4]: Sleef_fmaf4_avx2128);
+                impl_tertiary!(f32x16[h => f32x8]: Sleef_fmaf8_avx2);
+                impl_tertiary!(f64x8[h => f64x4]: Sleef_fmad4_avx2);
+
+                impl_tertiary!(f32x4: Sleef_fmaf4_avx2128);
+                impl_tertiary!(f32x8: Sleef_fmaf8_avx2);
+                impl_tertiary!(f64x2: Sleef_fmad2_avx2128);
+                impl_tertiary!(f64x4: Sleef_fmad4_avx2);
+            } else if #[cfg(target_feature = "avx")] {
+                impl_tertiary!(f32x2[t => f32x4]: Sleef_fmaf4_sse4);
+                impl_tertiary!(f32x16[h => f32x8]: Sleef_fmaf8_avx);
+                impl_tertiary!(f64x8[h => f64x4]: Sleef_fmad4_avx);
+
+                impl_tertiary!(f32x4: Sleef_fmaf4_sse4);
+                impl_tertiary!(f32x8: Sleef_fmaf8_avx);
+                impl_tertiary!(f64x2: Sleef_fmad2_sse4);
+                impl_tertiary!(f64x4: Sleef_fmad4_avx);
+            } else if #[cfg(target_feature = "sse4.2")] {
+                impl_tertiary!(f32x2[t => f32x4]: Sleef_fmaf4_sse4);
+                impl_tertiary!(f32x16[q => f32x4]: Sleef_fmaf4_sse4);
+                impl_tertiary!(f64x8[q => f64x2]: Sleef_fmad2_sse4);
+
+                impl_tertiary!(f32x4: Sleef_fmaf4_sse4);
+                impl_tertiary!(f32x8[h => f32x4]: Sleef_fmaf4_sse4);
+                impl_tertiary!(f64x2: Sleef_fmad2_sse4);
+                impl_tertiary!(f64x4[h => f64x2]: Sleef_fmad2_sse4);
+            } else {
+                impl_tertiary!(f32x2: fma_v2f32);
+                impl_tertiary!(f32x16: fma_v16f32);
+                impl_tertiary!(f64x8: fma_v8f64);
+
+                impl_tertiary!(f32x4: fma_v4f32);
+                impl_tertiary!(f32x8: fma_v8f32);
+                impl_tertiary!(f64x2: fma_v2f64);
+                impl_tertiary!(f64x4: fma_v4f64);
+            }
+        }
+    } else {
+        impl_tertiary!(f32x2: fma_v2f32);
+        impl_tertiary!(f32x4: fma_v4f32);
+        impl_tertiary!(f32x8: fma_v8f32);
+        impl_tertiary!(f32x16: fma_v16f32);
+        // impl_tertiary!(f64x1: fma_v1f64); // FIXME 64-bit fmagle elem vectors
+        impl_tertiary!(f64x2: fma_v2f64);
+        impl_tertiary!(f64x4: fma_v4f64);
+        impl_tertiary!(f64x8: fma_v8f64);
+    }
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/codegen/math/float/mul_adde.rs.html b/src/packed_simd/codegen/math/float/mul_adde.rs.html new file mode 100644 index 000000000..fab7f8241 --- /dev/null +++ b/src/packed_simd/codegen/math/float/mul_adde.rs.html @@ -0,0 +1,135 @@ +mul_adde.rs.html -- source
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+
+//! Approximation for floating-point `mul_add`
+use crate::*;
+
+// FIXME: 64-bit 1 element mul_adde
+
+crate trait MulAddE {
+    fn mul_adde(self, y: Self, z: Self) -> Self;
+}
+
+#[cfg(not(target_arch = "s390x"))]
+#[allow(improper_ctypes)]
+extern "C" {
+    #[link_name = "llvm.fmuladd.v2f32"]
+    fn fmuladd_v2f32(x: f32x2, y: f32x2, z: f32x2) -> f32x2;
+    #[link_name = "llvm.fmuladd.v4f32"]
+    fn fmuladd_v4f32(x: f32x4, y: f32x4, z: f32x4) -> f32x4;
+    #[link_name = "llvm.fmuladd.v8f32"]
+    fn fmuladd_v8f32(x: f32x8, y: f32x8, z: f32x8) -> f32x8;
+    #[link_name = "llvm.fmuladd.v16f32"]
+    fn fmuladd_v16f32(x: f32x16, y: f32x16, z: f32x16) -> f32x16;
+    /* FIXME 64-bit single elem vectors
+    #[link_name = "llvm.fmuladd.v1f64"]
+    fn fmuladd_v1f64(x: f64x1, y: f64x1, z: f64x1) -> f64x1;
+    */
+    #[link_name = "llvm.fmuladd.v2f64"]
+    fn fmuladd_v2f64(x: f64x2, y: f64x2, z: f64x2) -> f64x2;
+    #[link_name = "llvm.fmuladd.v4f64"]
+    fn fmuladd_v4f64(x: f64x4, y: f64x4, z: f64x4) -> f64x4;
+    #[link_name = "llvm.fmuladd.v8f64"]
+    fn fmuladd_v8f64(x: f64x8, y: f64x8, z: f64x8) -> f64x8;
+}
+
+macro_rules! impl_mul_adde {
+    ($id:ident : $fn:ident) => {
+        impl MulAddE for $id {
+            #[inline]
+            fn mul_adde(self, y: Self, z: Self) -> Self {
+                #[cfg(not(target_arch = "s390x"))]
+                {
+                    use crate::mem::transmute;
+                    unsafe {
+                        transmute($fn(
+                            transmute(self),
+                            transmute(y),
+                            transmute(z),
+                        ))
+                    }
+                }
+                #[cfg(target_arch = "s390x")]
+                {
+                    // FIXME: https://github.com/rust-lang-nursery/packed_simd/issues/14
+                    self * y + z
+                }
+            }
+        }
+    };
+}
+
+impl_mul_adde!(f32x2: fmuladd_v2f32);
+impl_mul_adde!(f32x4: fmuladd_v4f32);
+impl_mul_adde!(f32x8: fmuladd_v8f32);
+impl_mul_adde!(f32x16: fmuladd_v16f32);
+// impl_mul_adde!(f64x1: fma_v1f64); // FIXME 64-bit fmagle elem vectors
+impl_mul_adde!(f64x2: fmuladd_v2f64);
+impl_mul_adde!(f64x4: fmuladd_v4f64);
+impl_mul_adde!(f64x8: fmuladd_v8f64);
+
+
\ No newline at end of file diff --git a/src/packed_simd/codegen/math/float/powf.rs.html b/src/packed_simd/codegen/math/float/powf.rs.html new file mode 100644 index 000000000..813e8a6c2 --- /dev/null +++ b/src/packed_simd/codegen/math/float/powf.rs.html @@ -0,0 +1,227 @@ +powf.rs.html -- source
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+
+//! Vertical floating-point `powf`
+#![allow(unused)]
+
+// FIXME 64-bit powfgle elem vectors mispowfg
+
+use crate::*;
+
+crate trait Powf {
+    fn powf(self, x: Self) -> Self;
+}
+
+#[allow(improper_ctypes)]
+extern "C" {
+    #[link_name = "llvm.pow.v2f32"]
+    fn powf_v2f32(x: f32x2, y: f32x2) -> f32x2;
+    #[link_name = "llvm.pow.v4f32"]
+    fn powf_v4f32(x: f32x4, y: f32x4) -> f32x4;
+    #[link_name = "llvm.pow.v8f32"]
+    fn powf_v8f32(x: f32x8, y: f32x8) -> f32x8;
+    #[link_name = "llvm.pow.v16f32"]
+    fn powf_v16f32(x: f32x16, y: f32x16) -> f32x16;
+    /* FIXME 64-bit powfgle elem vectors
+    #[link_name = "llvm.pow.v1f64"]
+    fn powf_v1f64(x: f64x1, y: f64x1) -> f64x1;
+     */
+    #[link_name = "llvm.pow.v2f64"]
+    fn powf_v2f64(x: f64x2, y: f64x2) -> f64x2;
+    #[link_name = "llvm.pow.v4f64"]
+    fn powf_v4f64(x: f64x4, y: f64x4) -> f64x4;
+    #[link_name = "llvm.pow.v8f64"]
+    fn powf_v8f64(x: f64x8, y: f64x8) -> f64x8;
+
+    #[link_name = "llvm.pow.f32"]
+    fn powf_f32(x: f32, y: f32) -> f32;
+    #[link_name = "llvm.pow.f64"]
+    fn powf_f64(x: f64, y: f64) -> f64;
+}
+
+gen_binary_impl_table!(Powf, powf);
+
+cfg_if! {
+    if #[cfg(target_arch = "s390x")] {
+        // FIXME: https://github.com/rust-lang-nursery/packed_simd/issues/14
+        impl_binary!(f32x2[f32; 2]: powf_f32);
+        impl_binary!(f32x4[f32; 4]: powf_f32);
+        impl_binary!(f32x8[f32; 8]: powf_f32);
+        impl_binary!(f32x16[f32; 16]: powf_f32);
+
+        impl_binary!(f64x2[f64; 2]: powf_f64);
+        impl_binary!(f64x4[f64; 4]: powf_f64);
+        impl_binary!(f64x8[f64; 8]: powf_f64);
+    } else if #[cfg(all(target_arch = "x86_64", feature = "sleef-sys"))] {
+        use sleef_sys::*;
+        cfg_if! {
+            if #[cfg(target_feature = "avx2")] {
+                impl_binary!(f32x2[t => f32x4]: Sleef_powf4_u10avx2128);
+                impl_binary!(f32x16[h => f32x8]: Sleef_powf8_u10avx2);
+                impl_binary!(f64x8[h => f64x4]: Sleef_powd4_u10avx2);
+
+                impl_binary!(f32x4: Sleef_powf4_u10avx2128);
+                impl_binary!(f32x8: Sleef_powf8_u10avx2);
+                impl_binary!(f64x2: Sleef_powd2_u10avx2128);
+                impl_binary!(f64x4: Sleef_powd4_u10avx2);
+            } else if #[cfg(target_feature = "avx")] {
+                impl_binary!(f32x2[t => f32x4]: Sleef_powf4_u10sse4);
+                impl_binary!(f32x16[h => f32x8]: Sleef_powf8_u10avx);
+                impl_binary!(f64x8[h => f64x4]: Sleef_powd4_u10avx);
+
+                impl_binary!(f32x4: Sleef_powf4_u10sse4);
+                impl_binary!(f32x8: Sleef_powf8_u10avx);
+                impl_binary!(f64x2: Sleef_powd2_u10sse4);
+                impl_binary!(f64x4: Sleef_powd4_u10avx);
+            } else if #[cfg(target_feature = "sse4.2")] {
+                impl_binary!(f32x2[t => f32x4]: Sleef_powf4_u10sse4);
+                impl_binary!(f32x16[q => f32x4]: Sleef_powf4_u10sse4);
+                impl_binary!(f64x8[q => f64x2]: Sleef_powd2_u10sse4);
+
+                impl_binary!(f32x4: Sleef_powf4_u10sse4);
+                impl_binary!(f32x8[h => f32x4]: Sleef_powf4_u10sse4);
+                impl_binary!(f64x2: Sleef_powd2_u10sse4);
+                impl_binary!(f64x4[h => f64x2]: Sleef_powd2_u10sse4);
+            } else if #[cfg(target_feature = "sse2")] {
+                impl_binary!(f32x2[t => f32x4]: Sleef_powf4_u10sse2);
+                impl_binary!(f32x16[q => f32x4]: Sleef_powf4_u10sse2);
+                impl_binary!(f64x8[q => f64x2]: Sleef_powd2_u10sse2);
+
+                impl_binary!(f32x4: Sleef_powf4_u10sse2);
+                impl_binary!(f32x8[h => f32x4]: Sleef_powf4_u10sse2);
+                impl_binary!(f64x2: Sleef_powd2_u10sse2);
+                impl_binary!(f64x4[h => f64x2]: Sleef_powd2_u10sse2);
+            } else {
+                impl_binary!(f32x2[f32; 2]: powf_f32);
+                impl_binary!(f32x4: powf_v4f32);
+                impl_binary!(f32x8: powf_v8f32);
+                impl_binary!(f32x16: powf_v16f32);
+
+                impl_binary!(f64x2: powf_v2f64);
+                impl_binary!(f64x4: powf_v4f64);
+                impl_binary!(f64x8: powf_v8f64);
+            }
+        }
+    } else {
+        impl_binary!(f32x2[f32; 2]: powf_f32);
+        impl_binary!(f32x4: powf_v4f32);
+        impl_binary!(f32x8: powf_v8f32);
+        impl_binary!(f32x16: powf_v16f32);
+
+        impl_binary!(f64x2: powf_v2f64);
+        impl_binary!(f64x4: powf_v4f64);
+        impl_binary!(f64x8: powf_v8f64);
+    }
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/codegen/math/float/sin.rs.html b/src/packed_simd/codegen/math/float/sin.rs.html new file mode 100644 index 000000000..f876888de --- /dev/null +++ b/src/packed_simd/codegen/math/float/sin.rs.html @@ -0,0 +1,209 @@ +sin.rs.html -- source
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+
+//! Vertical floating-point `sin`
+#![allow(unused)]
+
+// FIXME 64-bit 1 elem vectors sin
+
+use crate::*;
+
+crate trait Sin {
+    fn sin(self) -> Self;
+}
+
+#[allow(improper_ctypes)]
+extern "C" {
+    #[link_name = "llvm.sin.v2f32"]
+    fn sin_v2f32(x: f32x2) -> f32x2;
+    #[link_name = "llvm.sin.v4f32"]
+    fn sin_v4f32(x: f32x4) -> f32x4;
+    #[link_name = "llvm.sin.v8f32"]
+    fn sin_v8f32(x: f32x8) -> f32x8;
+    #[link_name = "llvm.sin.v16f32"]
+    fn sin_v16f32(x: f32x16) -> f32x16;
+    /* FIXME 64-bit single elem vectors
+    #[link_name = "llvm.sin.v1f64"]
+    fn sin_v1f64(x: f64x1) -> f64x1;
+     */
+    #[link_name = "llvm.sin.v2f64"]
+    fn sin_v2f64(x: f64x2) -> f64x2;
+    #[link_name = "llvm.sin.v4f64"]
+    fn sin_v4f64(x: f64x4) -> f64x4;
+    #[link_name = "llvm.sin.v8f64"]
+    fn sin_v8f64(x: f64x8) -> f64x8;
+
+    #[link_name = "llvm.sin.f32"]
+    fn sin_f32(x: f32) -> f32;
+    #[link_name = "llvm.sin.f64"]
+    fn sin_f64(x: f64) -> f64;
+}
+
+gen_unary_impl_table!(Sin, sin);
+
+cfg_if! {
+    if #[cfg(target_arch = "s390x")] {
+        // FIXME: https://github.com/rust-lang-nursery/packed_simd/issues/14
+        impl_unary!(f32x2[f32; 2]: sin_f32);
+        impl_unary!(f32x4[f32; 4]: sin_f32);
+        impl_unary!(f32x8[f32; 8]: sin_f32);
+        impl_unary!(f32x16[f32; 16]: sin_f32);
+
+        impl_unary!(f64x2[f64; 2]: sin_f64);
+        impl_unary!(f64x4[f64; 4]: sin_f64);
+        impl_unary!(f64x8[f64; 8]: sin_f64);
+    } else if #[cfg(all(target_arch = "x86_64", feature = "sleef-sys"))] {
+        use sleef_sys::*;
+        cfg_if! {
+            if #[cfg(target_feature = "avx2")] {
+                impl_unary!(f32x2[t => f32x4]: Sleef_sinf4_u10avx2128);
+                impl_unary!(f32x16[h => f32x8]: Sleef_sinf8_u10avx2);
+                impl_unary!(f64x8[h => f64x4]: Sleef_sind4_u10avx2);
+
+                impl_unary!(f32x4: Sleef_sinf4_u10avx2128);
+                impl_unary!(f32x8: Sleef_sinf8_u10avx2);
+                impl_unary!(f64x2: Sleef_sind2_u10avx2128);
+                impl_unary!(f64x4: Sleef_sind4_u10avx2);
+            } else if #[cfg(target_feature = "avx")] {
+                impl_unary!(f32x2[t => f32x4]: Sleef_sinf4_u10sse4);
+                impl_unary!(f32x16[h => f32x8]: Sleef_sinf8_u10avx);
+                impl_unary!(f64x8[h => f64x4]: Sleef_sind4_u10avx);
+
+                impl_unary!(f32x4: Sleef_sinf4_u10sse4);
+                impl_unary!(f32x8: Sleef_sinf8_u10avx);
+                impl_unary!(f64x2: Sleef_sind2_u10sse4);
+                impl_unary!(f64x4: Sleef_sind4_u10avx);
+            } else if #[cfg(target_feature = "sse4.2")] {
+                impl_unary!(f32x2[t => f32x4]: Sleef_sinf4_u10sse4);
+                impl_unary!(f32x16[q => f32x4]: Sleef_sinf4_u10sse4);
+                impl_unary!(f64x8[q => f64x2]: Sleef_sind2_u10sse4);
+
+                impl_unary!(f32x4: Sleef_sinf4_u10sse4);
+                impl_unary!(f32x8[h => f32x4]: Sleef_sinf4_u10sse4);
+                impl_unary!(f64x2: Sleef_sind2_u10sse4);
+                impl_unary!(f64x4[h => f64x2]: Sleef_sind2_u10sse4);
+            } else {
+                impl_unary!(f32x2[f32; 2]: sin_f32);
+                impl_unary!(f32x16: sin_v16f32);
+                impl_unary!(f64x8: sin_v8f64);
+
+                impl_unary!(f32x4: sin_v4f32);
+                impl_unary!(f32x8: sin_v8f32);
+                impl_unary!(f64x2: sin_v2f64);
+                impl_unary!(f64x4: sin_v4f64);
+            }
+        }
+    } else {
+        impl_unary!(f32x2[f32; 2]: sin_f32);
+        impl_unary!(f32x4: sin_v4f32);
+        impl_unary!(f32x8: sin_v8f32);
+        impl_unary!(f32x16: sin_v16f32);
+
+        impl_unary!(f64x2: sin_v2f64);
+        impl_unary!(f64x4: sin_v4f64);
+        impl_unary!(f64x8: sin_v8f64);
+    }
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/codegen/math/float/sin_cos_pi.rs.html b/src/packed_simd/codegen/math/float/sin_cos_pi.rs.html new file mode 100644 index 000000000..11ff67cb2 --- /dev/null +++ b/src/packed_simd/codegen/math/float/sin_cos_pi.rs.html @@ -0,0 +1,393 @@ +sin_cos_pi.rs.html -- source
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+
+//! Vertical floating-point `sin_cos`
+#![allow(unused)]
+
+// FIXME 64-bit 1 elem vectors sin_cos
+
+use crate::*;
+
+crate trait SinCosPi: Sized {
+    type Output;
+    fn sin_cos_pi(self) -> Self::Output;
+}
+
+macro_rules! impl_def {
+    ($vid:ident, $PI:path) => {
+        impl SinCosPi for $vid {
+            type Output = (Self, Self);
+            #[inline]
+            fn sin_cos_pi(self) -> Self::Output {
+                let v = self * Self::splat($PI);
+                (v.sin(), v.cos())
+            }
+        }
+    };
+}
+
+macro_rules! impl_def32 {
+    ($vid:ident) => {
+        impl_def!($vid, crate::f32::consts::PI);
+    };
+}
+macro_rules! impl_def64 {
+    ($vid:ident) => {
+        impl_def!($vid, crate::f64::consts::PI);
+    };
+}
+
+macro_rules! impl_unary_t {
+    ($vid:ident: $fun:ident) => {
+        impl SinCosPi for $vid {
+            type Output = (Self, Self);
+            fn sin_cos_pi(self) -> Self::Output {
+                unsafe {
+                    use crate::mem::transmute;
+                    transmute($fun(transmute(self)))
+                }
+            }
+        }
+    };
+    ($vid:ident[t => $vid_t:ident]: $fun:ident) => {
+        impl SinCosPi for $vid {
+            type Output = (Self, Self);
+            fn sin_cos_pi(self) -> Self::Output {
+                unsafe {
+                    use crate::mem::{transmute, uninitialized};
+
+                    union U {
+                        vec: [$vid; 2],
+                        twice: $vid_t,
+                    }
+
+                    let twice = U { vec: [self, uninitialized()] }.twice;
+                    let twice = transmute($fun(transmute(twice)));
+
+                    union R {
+                        twice: ($vid_t, $vid_t),
+                        vecs: ([$vid; 2], [$vid; 2]),
+                    }
+                    let r = R { twice }.vecs;
+                    (*r.0.get_unchecked(0), *r.0.get_unchecked(1))
+                }
+            }
+        }
+    };
+    ($vid:ident[h => $vid_h:ident]: $fun:ident) => {
+        impl SinCosPi for $vid {
+            type Output = (Self, Self);
+            fn sin_cos_pi(self) -> Self::Output {
+                unsafe {
+                    use crate::mem::transmute;
+
+                    union U {
+                        vec: $vid,
+                        halves: [$vid_h; 2],
+                    }
+
+                    let halves = U { vec: self }.halves;
+
+                    let res_0: ($vid_h, $vid_h) =
+                        transmute($fun(transmute(*halves.get_unchecked(0))));
+                    let res_1: ($vid_h, $vid_h) =
+                        transmute($fun(transmute(*halves.get_unchecked(1))));
+
+                    union R {
+                        result: ($vid, $vid),
+                        halves: ([$vid_h; 2], [$vid_h; 2]),
+                    }
+                    R { halves: ([res_0.0, res_1.0], [res_0.1, res_1.1]) }
+                        .result
+                }
+            }
+        }
+    };
+    ($vid:ident[q => $vid_q:ident]: $fun:ident) => {
+        impl SinCosPi for $vid {
+            type Output = (Self, Self);
+            fn sin_cos_pi(self) -> Self::Output {
+                unsafe {
+                    use crate::mem::transmute;
+
+                    union U {
+                        vec: $vid,
+                        quarters: [$vid_q; 4],
+                    }
+
+                    let quarters = U { vec: self }.quarters;
+
+                    let res_0: ($vid_q, $vid_q) =
+                        transmute($fun(transmute(*quarters.get_unchecked(0))));
+                    let res_1: ($vid_q, $vid_q) =
+                        transmute($fun(transmute(*quarters.get_unchecked(1))));
+                    let res_2: ($vid_q, $vid_q) =
+                        transmute($fun(transmute(*quarters.get_unchecked(2))));
+                    let res_3: ($vid_q, $vid_q) =
+                        transmute($fun(transmute(*quarters.get_unchecked(3))));
+
+                    union R {
+                        result: ($vid, $vid),
+                        quarters: ([$vid_q; 4], [$vid_q; 4]),
+                    }
+                    R {
+                        quarters: (
+                            [res_0.0, res_1.0, res_2.0, res_3.0],
+                            [res_0.1, res_1.1, res_2.1, res_3.1],
+                        ),
+                    }
+                    .result
+                }
+            }
+        }
+    };
+}
+
+cfg_if! {
+    if #[cfg(all(target_arch = "x86_64", feature = "sleef-sys"))] {
+        use sleef_sys::*;
+        cfg_if! {
+            if #[cfg(target_feature = "avx2")] {
+                impl_unary_t!(f32x2[t => f32x4]: Sleef_sincospif4_u05avx2128);
+                impl_unary_t!(f32x16[h => f32x8]: Sleef_sincospif8_u05avx2);
+                impl_unary_t!(f64x8[h => f64x4]: Sleef_sincospid4_u05avx2);
+
+                impl_unary_t!(f32x4: Sleef_sincospif4_u05avx2128);
+                impl_unary_t!(f32x8: Sleef_sincospif8_u05avx2);
+                impl_unary_t!(f64x2: Sleef_sincospid2_u05avx2128);
+                impl_unary_t!(f64x4: Sleef_sincospid4_u05avx2);
+            } else if #[cfg(target_feature = "avx")] {
+                impl_unary_t!(f32x2[t => f32x4]: Sleef_sincospif4_u05sse4);
+                impl_unary_t!(f32x16[h => f32x8]: Sleef_sincospif8_u05avx);
+                impl_unary_t!(f64x8[h => f64x4]: Sleef_sincospid4_u05avx);
+
+                impl_unary_t!(f32x4: Sleef_sincospif4_u05sse4);
+                impl_unary_t!(f32x8: Sleef_sincospif8_u05avx);
+                impl_unary_t!(f64x2: Sleef_sincospid2_u05sse4);
+                impl_unary_t!(f64x4: Sleef_sincospid4_u05avx);
+            } else if #[cfg(target_feature = "sse4.2")] {
+                impl_unary_t!(f32x2[t => f32x4]: Sleef_sincospif4_u05sse4);
+                impl_unary_t!(f32x16[q => f32x4]: Sleef_sincospif4_u05sse4);
+                impl_unary_t!(f64x8[q => f64x2]: Sleef_sincospid2_u05sse4);
+
+                impl_unary_t!(f32x4: Sleef_sincospif4_u05sse4);
+                impl_unary_t!(f32x8[h => f32x4]: Sleef_sincospif4_u05sse4);
+                impl_unary_t!(f64x2: Sleef_sincospid2_u05sse4);
+                impl_unary_t!(f64x4[h => f64x2]: Sleef_sincospid2_u05sse4);
+            } else {
+                impl_def32!(f32x2);
+                impl_def32!(f32x4);
+                impl_def32!(f32x8);
+                impl_def32!(f32x16);
+
+                impl_def64!(f64x2);
+                impl_def64!(f64x4);
+                impl_def64!(f64x8);
+            }
+        }
+    } else {
+        impl_def32!(f32x2);
+        impl_def32!(f32x4);
+        impl_def32!(f32x8);
+        impl_def32!(f32x16);
+
+        impl_def64!(f64x2);
+        impl_def64!(f64x4);
+        impl_def64!(f64x8);
+    }
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/codegen/math/float/sin_pi.rs.html b/src/packed_simd/codegen/math/float/sin_pi.rs.html new file mode 100644 index 000000000..1a949d1ce --- /dev/null +++ b/src/packed_simd/codegen/math/float/sin_pi.rs.html @@ -0,0 +1,177 @@ +sin_pi.rs.html -- source
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+
+//! Vertical floating-point `sin_pi`
+#![allow(unused)]
+
+// FIXME 64-bit 1 elem vectors sin_pi
+
+use crate::*;
+
+crate trait SinPi {
+    fn sin_pi(self) -> Self;
+}
+
+gen_unary_impl_table!(SinPi, sin_pi);
+
+macro_rules! impl_def {
+    ($vid:ident, $PI:path) => {
+        impl SinPi for $vid {
+            #[inline]
+            fn sin_pi(self) -> Self {
+                (self * Self::splat($PI)).sin()
+            }
+        }
+    };
+}
+macro_rules! impl_def32 {
+    ($vid:ident) => {
+        impl_def!($vid, crate::f32::consts::PI);
+    };
+}
+macro_rules! impl_def64 {
+    ($vid:ident) => {
+        impl_def!($vid, crate::f64::consts::PI);
+    };
+}
+
+cfg_if! {
+    if #[cfg(all(target_arch = "x86_64", feature = "sleef-sys"))] {
+        use sleef_sys::*;
+        cfg_if! {
+            if #[cfg(target_feature = "avx2")] {
+                impl_unary!(f32x2[t => f32x4]: Sleef_sinpif4_u05avx2128);
+                impl_unary!(f32x16[h => f32x8]: Sleef_sinpif8_u05avx2);
+                impl_unary!(f64x8[h => f64x4]: Sleef_sinpid4_u05avx2);
+
+                impl_unary!(f32x4: Sleef_sinpif4_u05avx2128);
+                impl_unary!(f32x8: Sleef_sinpif8_u05avx2);
+                impl_unary!(f64x2: Sleef_sinpid2_u05avx2128);
+                impl_unary!(f64x4: Sleef_sinpid4_u05avx2);
+            } else if #[cfg(target_feature = "avx")] {
+                impl_unary!(f32x2[t => f32x4]: Sleef_sinpif4_u05sse4);
+                impl_unary!(f32x16[h => f32x8]: Sleef_sinpif8_u05avx);
+                impl_unary!(f64x8[h => f64x4]: Sleef_sinpid4_u05avx);
+
+                impl_unary!(f32x4: Sleef_sinpif4_u05sse4);
+                impl_unary!(f32x8: Sleef_sinpif8_u05avx);
+                impl_unary!(f64x2: Sleef_sinpid2_u05sse4);
+                impl_unary!(f64x4: Sleef_sinpid4_u05avx);
+            } else if #[cfg(target_feature = "sse4.2")] {
+                impl_unary!(f32x2[t => f32x4]: Sleef_sinpif4_u05sse4);
+                impl_unary!(f32x16[q => f32x4]: Sleef_sinpif4_u05sse4);
+                impl_unary!(f64x8[q => f64x2]: Sleef_sinpid2_u05sse4);
+
+                impl_unary!(f32x4: Sleef_sinpif4_u05sse4);
+                impl_unary!(f32x8[h => f32x4]: Sleef_sinpif4_u05sse4);
+                impl_unary!(f64x2: Sleef_sinpid2_u05sse4);
+                impl_unary!(f64x4[h => f64x2]: Sleef_sinpid2_u05sse4);
+            } else {
+                impl_def32!(f32x2);
+                impl_def32!(f32x4);
+                impl_def32!(f32x8);
+                impl_def32!(f32x16);
+
+                impl_def64!(f64x2);
+                impl_def64!(f64x4);
+                impl_def64!(f64x8);
+            }
+        }
+    } else {
+        impl_def32!(f32x2);
+        impl_def32!(f32x4);
+        impl_def32!(f32x8);
+        impl_def32!(f32x16);
+
+        impl_def64!(f64x2);
+        impl_def64!(f64x4);
+        impl_def64!(f64x8);
+    }
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/codegen/math/float/sqrt.rs.html b/src/packed_simd/codegen/math/float/sqrt.rs.html new file mode 100644 index 000000000..e368f2be0 --- /dev/null +++ b/src/packed_simd/codegen/math/float/sqrt.rs.html @@ -0,0 +1,209 @@ +sqrt.rs.html -- source
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+
+//! Vertical floating-point `sqrt`
+#![allow(unused)]
+
+// FIXME 64-bit 1 elem vectors sqrt
+
+use crate::*;
+
+crate trait Sqrt {
+    fn sqrt(self) -> Self;
+}
+
+#[allow(improper_ctypes)]
+extern "C" {
+    #[link_name = "llvm.sqrt.v2f32"]
+    fn sqrt_v2f32(x: f32x2) -> f32x2;
+    #[link_name = "llvm.sqrt.v4f32"]
+    fn sqrt_v4f32(x: f32x4) -> f32x4;
+    #[link_name = "llvm.sqrt.v8f32"]
+    fn sqrt_v8f32(x: f32x8) -> f32x8;
+    #[link_name = "llvm.sqrt.v16f32"]
+    fn sqrt_v16f32(x: f32x16) -> f32x16;
+    /* FIXME 64-bit sqrtgle elem vectors
+    #[link_name = "llvm.sqrt.v1f64"]
+    fn sqrt_v1f64(x: f64x1) -> f64x1;
+     */
+    #[link_name = "llvm.sqrt.v2f64"]
+    fn sqrt_v2f64(x: f64x2) -> f64x2;
+    #[link_name = "llvm.sqrt.v4f64"]
+    fn sqrt_v4f64(x: f64x4) -> f64x4;
+    #[link_name = "llvm.sqrt.v8f64"]
+    fn sqrt_v8f64(x: f64x8) -> f64x8;
+
+    #[link_name = "llvm.sqrt.f32"]
+    fn sqrt_f32(x: f32) -> f32;
+    #[link_name = "llvm.sqrt.f64"]
+    fn sqrt_f64(x: f64) -> f64;
+}
+
+gen_unary_impl_table!(Sqrt, sqrt);
+
+cfg_if! {
+    if #[cfg(target_arch = "s390x")] {
+        // FIXME: https://github.com/rust-lang-nursery/packed_simd/issues/14
+        impl_unary!(f32x2[f32; 2]: sqrt_f32);
+        impl_unary!(f32x4[f32; 4]: sqrt_f32);
+        impl_unary!(f32x8[f32; 8]: sqrt_f32);
+        impl_unary!(f32x16[f32; 16]: sqrt_f32);
+
+        impl_unary!(f64x2[f64; 2]: sqrt_f64);
+        impl_unary!(f64x4[f64; 4]: sqrt_f64);
+        impl_unary!(f64x8[f64; 8]: sqrt_f64);
+    } else if #[cfg(all(target_arch = "x86_64", feature = "sleef-sys"))] {
+        use sleef_sys::*;
+        cfg_if! {
+            if #[cfg(target_feature = "avx2")] {
+                impl_unary!(f32x2[t => f32x4]: Sleef_sqrtf4_avx2128);
+                impl_unary!(f32x16[h => f32x8]: Sleef_sqrtf8_avx2);
+                impl_unary!(f64x8[h => f64x4]: Sleef_sqrtd4_avx2);
+
+                impl_unary!(f32x4: Sleef_sqrtf4_avx2128);
+                impl_unary!(f32x8: Sleef_sqrtf8_avx2);
+                impl_unary!(f64x2: Sleef_sqrtd2_avx2128);
+                impl_unary!(f64x4: Sleef_sqrtd4_avx2);
+            } else if #[cfg(target_feature = "avx")] {
+                impl_unary!(f32x2[t => f32x4]: Sleef_sqrtf4_sse4);
+                impl_unary!(f32x16[h => f32x8]: Sleef_sqrtf8_avx);
+                impl_unary!(f64x8[h => f64x4]: Sleef_sqrtd4_avx);
+
+                impl_unary!(f32x4: Sleef_sqrtf4_sse4);
+                impl_unary!(f32x8: Sleef_sqrtf8_avx);
+                impl_unary!(f64x2: Sleef_sqrtd2_sse4);
+                impl_unary!(f64x4: Sleef_sqrtd4_avx);
+            } else if #[cfg(target_feature = "sse4.2")] {
+                impl_unary!(f32x2[t => f32x4]: Sleef_sqrtf4_sse4);
+                impl_unary!(f32x16[q => f32x4]: Sleef_sqrtf4_sse4);
+                impl_unary!(f64x8[q => f64x2]: Sleef_sqrtd2_sse4);
+
+                impl_unary!(f32x4: Sleef_sqrtf4_sse4);
+                impl_unary!(f32x8[h => f32x4]: Sleef_sqrtf4_sse4);
+                impl_unary!(f64x2: Sleef_sqrtd2_sse4);
+                impl_unary!(f64x4[h => f64x2]: Sleef_sqrtd2_sse4);
+            } else {
+                impl_unary!(f32x2[f32; 2]: sqrt_f32);
+                impl_unary!(f32x16: sqrt_v16f32);
+                impl_unary!(f64x8: sqrt_v8f64);
+
+                impl_unary!(f32x4: sqrt_v4f32);
+                impl_unary!(f32x8: sqrt_v8f32);
+                impl_unary!(f64x2: sqrt_v2f64);
+                impl_unary!(f64x4: sqrt_v4f64);
+            }
+        }
+    } else {
+        impl_unary!(f32x2[f32; 2]: sqrt_f32);
+        impl_unary!(f32x4: sqrt_v4f32);
+        impl_unary!(f32x8: sqrt_v8f32);
+        impl_unary!(f32x16: sqrt_v16f32);
+
+        impl_unary!(f64x2: sqrt_v2f64);
+        impl_unary!(f64x4: sqrt_v4f64);
+        impl_unary!(f64x8: sqrt_v8f64);
+    }
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/codegen/math/float/sqrte.rs.html b/src/packed_simd/codegen/math/float/sqrte.rs.html new file mode 100644 index 000000000..4d54e80fb --- /dev/null +++ b/src/packed_simd/codegen/math/float/sqrte.rs.html @@ -0,0 +1,137 @@ +sqrte.rs.html -- source
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+
+//! Vertical floating-point `sqrt`
+#![allow(unused)]
+
+// FIXME 64-bit 1 elem vectors sqrte
+
+use crate::llvm::simd_fsqrt;
+use crate::*;
+
+crate trait Sqrte {
+    fn sqrte(self) -> Self;
+}
+
+gen_unary_impl_table!(Sqrte, sqrte);
+
+cfg_if! {
+    if #[cfg(all(target_arch = "x86_64", feature = "sleef-sys"))] {
+        use sleef_sys::*;
+        cfg_if! {
+            if #[cfg(target_feature = "avx2")] {
+                impl_unary!(f32x2[t => f32x4]: Sleef_sqrtf4_u35avx2128);
+                impl_unary!(f32x16[h => f32x8]: Sleef_sqrtf8_u35avx2);
+                impl_unary!(f64x8[h => f64x4]: Sleef_sqrtd4_u35avx2);
+
+                impl_unary!(f32x4: Sleef_sqrtf4_u35avx2128);
+                impl_unary!(f32x8: Sleef_sqrtf8_u35avx2);
+                impl_unary!(f64x2: Sleef_sqrtd2_u35avx2128);
+                impl_unary!(f64x4: Sleef_sqrtd4_u35avx2);
+            } else if #[cfg(target_feature = "avx")] {
+                impl_unary!(f32x2[t => f32x4]: Sleef_sqrtf4_u35sse4);
+                impl_unary!(f32x16[h => f32x8]: Sleef_sqrtf8_u35avx);
+                impl_unary!(f64x8[h => f64x4]: Sleef_sqrtd4_u35avx);
+
+                impl_unary!(f32x4: Sleef_sqrtf4_u35sse4);
+                impl_unary!(f32x8: Sleef_sqrtf8_u35avx);
+                impl_unary!(f64x2: Sleef_sqrtd2_u35sse4);
+                impl_unary!(f64x4: Sleef_sqrtd4_u35avx);
+            } else if #[cfg(target_feature = "sse4.2")] {
+                impl_unary!(f32x2[t => f32x4]: Sleef_sqrtf4_u35sse4);
+                impl_unary!(f32x16[q => f32x4]: Sleef_sqrtf4_u35sse4);
+                impl_unary!(f64x8[q => f64x2]: Sleef_sqrtd2_u35sse4);
+
+                impl_unary!(f32x4: Sleef_sqrtf4_u35sse4);
+                impl_unary!(f32x8[h => f32x4]: Sleef_sqrtf4_u35sse4);
+                impl_unary!(f64x2: Sleef_sqrtd2_u35sse4);
+                impl_unary!(f64x4[h => f64x2]: Sleef_sqrtd2_u35sse4);
+            } else {
+                impl_unary!(f32x2[g]: simd_fsqrt);
+                impl_unary!(f32x16[g]: simd_fsqrt);
+                impl_unary!(f64x8[g]: simd_fsqrt);
+
+                impl_unary!(f32x4[g]: simd_fsqrt);
+                impl_unary!(f32x8[g]: simd_fsqrt);
+                impl_unary!(f64x2[g]: simd_fsqrt);
+                impl_unary!(f64x4[g]: simd_fsqrt);
+            }
+        }
+    } else {
+        impl_unary!(f32x2[g]: simd_fsqrt);
+        impl_unary!(f32x4[g]: simd_fsqrt);
+        impl_unary!(f32x8[g]: simd_fsqrt);
+        impl_unary!(f32x16[g]: simd_fsqrt);
+
+        impl_unary!(f64x2[g]: simd_fsqrt);
+        impl_unary!(f64x4[g]: simd_fsqrt);
+        impl_unary!(f64x8[g]: simd_fsqrt);
+    }
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/codegen/math/float/tanh.rs.html b/src/packed_simd/codegen/math/float/tanh.rs.html new file mode 100644 index 000000000..f9506af4b --- /dev/null +++ b/src/packed_simd/codegen/math/float/tanh.rs.html @@ -0,0 +1,237 @@ +tanh.rs.html -- source
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+
+//! Vertical floating-point `tanh`
+#![allow(unused)]
+
+// FIXME 64-bit 1 elem vectors tanh
+
+use crate::*;
+
+crate trait Tanh {
+    fn tanh(self) -> Self;
+}
+
+macro_rules! define_tanh {
+
+    ($name:ident, $basetype:ty, $simdtype:ty, $lanes:expr, $trait:path) => {
+        fn $name(x: $simdtype) -> $simdtype {
+            use core::intrinsics::transmute;
+            let mut buf: [$basetype; $lanes] = unsafe { transmute(x) };
+            for elem in &mut buf {
+                *elem = <$basetype as $trait>::tanh(*elem);
+            }
+            unsafe { transmute(buf) }
+        }
+    };
+
+    (f32 => $name:ident, $type:ty, $lanes:expr) => {
+        define_tanh!($name, f32, $type, $lanes, libm::F32Ext);
+    };
+
+    (f64 => $name:ident, $type:ty, $lanes:expr) => {
+        define_tanh!($name, f64, $type, $lanes, libm::F64Ext);
+    };
+}
+
+// llvm does not seem to expose the hyperbolic versions of trigonometric functions;
+// we thus call the classical rust versions on all of them (which stem from cmath).
+define_tanh!(f32 => tanh_v2f32, f32x2, 2);
+define_tanh!(f32 => tanh_v4f32, f32x4, 4);
+define_tanh!(f32 => tanh_v8f32, f32x8, 8);
+define_tanh!(f32 => tanh_v16f32, f32x16, 16);
+
+define_tanh!(f64 => tanh_v2f64, f64x2, 2);
+define_tanh!(f64 => tanh_v4f64, f64x4, 4);
+define_tanh!(f64 => tanh_v8f64, f64x8, 8);
+
+fn tanh_f32(x: f32) -> f32 {
+    libm::F32Ext::tanh(x)
+}
+
+fn tanh_f64(x: f64) -> f64 {
+    libm::F64Ext::tanh(x)
+}
+
+gen_unary_impl_table!(Tanh, tanh);
+
+cfg_if! {
+    if #[cfg(target_arch = "s390x")] {
+        // FIXME: https://github.com/rust-lang-nursery/packed_simd/issues/14
+        impl_unary!(f32x2[f32; 2]: tanh_f32);
+        impl_unary!(f32x4[f32; 4]: tanh_f32);
+        impl_unary!(f32x8[f32; 8]: tanh_f32);
+        impl_unary!(f32x16[f32; 16]: tanh_f32);
+
+        impl_unary!(f64x2[f64; 2]: tanh_f64);
+        impl_unary!(f64x4[f64; 4]: tanh_f64);
+        impl_unary!(f64x8[f64; 8]: tanh_f64);
+    } else if #[cfg(all(target_arch = "x86_64", feature = "sleef-sys"))] {
+        use sleef_sys::*;
+        cfg_if! {
+            if #[cfg(target_feature = "avx2")] {
+                impl_unary!(f32x2[t => f32x4]: Sleef_tanhf4_u10avx2128);
+                impl_unary!(f32x16[h => f32x8]: Sleef_tanhf8_u10avx2);
+                impl_unary!(f64x8[h => f64x4]: Sleef_tanhd4_u10avx2);
+
+                impl_unary!(f32x4: Sleef_tanhf4_u10avx2128);
+                impl_unary!(f32x8: Sleef_tanhf8_u10avx2);
+                impl_unary!(f64x2: Sleef_tanhd2_u10avx2128);
+                impl_unary!(f64x4: Sleef_tanhd4_u10avx2);
+            } else if #[cfg(target_feature = "avx")] {
+                impl_unary!(f32x2[t => f32x4]: Sleef_tanhf4_u10sse4);
+                impl_unary!(f32x16[h => f32x8]: Sleef_tanhf8_u10avx);
+                impl_unary!(f64x8[h => f64x4]: Sleef_tanhd4_u10avx);
+
+                impl_unary!(f32x4: Sleef_tanhf4_u10sse4);
+                impl_unary!(f32x8: Sleef_tanhf8_u10avx);
+                impl_unary!(f64x2: Sleef_tanhd2_u10sse4);
+                impl_unary!(f64x4: Sleef_tanhd4_u10avx);
+            } else if #[cfg(target_feature = "sse4.2")] {
+                impl_unary!(f32x2[t => f32x4]: Sleef_tanhf4_u10sse4);
+                impl_unary!(f32x16[q => f32x4]: Sleef_tanhf4_u10sse4);
+                impl_unary!(f64x8[q => f64x2]: Sleef_tanhd2_u10sse4);
+
+                impl_unary!(f32x4: Sleef_tanhf4_u10sse4);
+                impl_unary!(f32x8[h => f32x4]: Sleef_tanhf4_u10sse4);
+                impl_unary!(f64x2: Sleef_tanhd2_u10sse4);
+                impl_unary!(f64x4[h => f64x2]: Sleef_tanhd2_u10sse4);
+            } else {
+                impl_unary!(f32x2[f32; 2]: tanh_f32);
+                impl_unary!(f32x16: tanh_v16f32);
+                impl_unary!(f64x8: tanh_v8f64);
+
+                impl_unary!(f32x4: tanh_v4f32);
+                impl_unary!(f32x8: tanh_v8f32);
+                impl_unary!(f64x2: tanh_v2f64);
+                impl_unary!(f64x4: tanh_v4f64);
+            }
+        }
+    } else {
+        impl_unary!(f32x2[f32; 2]: tanh_f32);
+        impl_unary!(f32x4: tanh_v4f32);
+        impl_unary!(f32x8: tanh_v8f32);
+        impl_unary!(f32x16: tanh_v16f32);
+
+        impl_unary!(f64x2: tanh_v2f64);
+        impl_unary!(f64x4: tanh_v4f64);
+        impl_unary!(f64x8: tanh_v8f64);
+    }
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/codegen/pointer_sized_int.rs.html b/src/packed_simd/codegen/pointer_sized_int.rs.html new file mode 100644 index 000000000..ea08e7581 --- /dev/null +++ b/src/packed_simd/codegen/pointer_sized_int.rs.html @@ -0,0 +1,59 @@ +pointer_sized_int.rs.html -- source
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+//! Provides `isize` and `usize`
+
+use cfg_if::cfg_if;
+
+cfg_if! {
+    if #[cfg(target_pointer_width = "8")] {
+        crate type isize_ = i8;
+        crate type usize_ = u8;
+    } else if #[cfg(target_pointer_width = "16")] {
+        crate type isize_ = i16;
+        crate type usize_ = u16;
+    } else if #[cfg(target_pointer_width = "32")] {
+        crate type isize_ = i32;
+        crate type usize_ = u32;
+
+    } else if #[cfg(target_pointer_width = "64")] {
+        crate type isize_ = i64;
+        crate type usize_ = u64;
+    } else if #[cfg(target_pointer_width = "64")] {
+        crate type isize_ = i64;
+        crate type usize_ = u64;
+    } else if #[cfg(target_pointer_width = "128")] {
+        crate type isize_ = i128;
+        crate type usize_ = u128;
+    } else {
+        compile_error!("unsupported target_pointer_width");
+    }
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/codegen/reductions.rs.html b/src/packed_simd/codegen/reductions.rs.html new file mode 100644 index 000000000..bf26efc64 --- /dev/null +++ b/src/packed_simd/codegen/reductions.rs.html @@ -0,0 +1,5 @@ +reductions.rs.html -- source
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+crate mod mask;
+
+
\ No newline at end of file diff --git a/src/packed_simd/codegen/reductions/mask.rs.html b/src/packed_simd/codegen/reductions/mask.rs.html new file mode 100644 index 000000000..0982a6703 --- /dev/null +++ b/src/packed_simd/codegen/reductions/mask.rs.html @@ -0,0 +1,141 @@ +mask.rs.html -- source
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+//! Code generation workaround for `all()` mask horizontal reduction.
+//!
+//! Works arround [LLVM bug 36702].
+//!
+//! [LLVM bug 36702]: https://bugs.llvm.org/show_bug.cgi?id=36702
+#![allow(unused_macros)]
+
+use crate::*;
+
+crate trait All: crate::marker::Sized {
+    unsafe fn all(self) -> bool;
+}
+
+crate trait Any: crate::marker::Sized {
+    unsafe fn any(self) -> bool;
+}
+
+#[macro_use]
+mod fallback_impl;
+
+cfg_if! {
+    if #[cfg(any(target_arch = "x86", target_arch = "x86_64"))] {
+        #[macro_use]
+        mod x86;
+    } else if #[cfg(all(target_arch = "arm", target_feature = "v7",
+                        target_feature = "neon",
+                        any(feature = "core_arch", libcore_neon)))] {
+        #[macro_use]
+        mod arm;
+    } else if #[cfg(all(target_arch = "aarch64", target_feature = "neon"))] {
+        #[macro_use]
+        mod aarch64;
+    } else {
+        #[macro_use]
+        mod fallback;
+    }
+}
+
+impl_mask_reductions!(m8x2);
+impl_mask_reductions!(m8x4);
+impl_mask_reductions!(m8x8);
+impl_mask_reductions!(m8x16);
+impl_mask_reductions!(m8x32);
+impl_mask_reductions!(m8x64);
+
+impl_mask_reductions!(m16x2);
+impl_mask_reductions!(m16x4);
+impl_mask_reductions!(m16x8);
+impl_mask_reductions!(m16x16);
+impl_mask_reductions!(m16x32);
+
+impl_mask_reductions!(m32x2);
+impl_mask_reductions!(m32x4);
+impl_mask_reductions!(m32x8);
+impl_mask_reductions!(m32x16);
+
+// FIXME: 64-bit single element vector
+// impl_mask_reductions!(m64x1);
+impl_mask_reductions!(m64x2);
+impl_mask_reductions!(m64x4);
+impl_mask_reductions!(m64x8);
+
+impl_mask_reductions!(m128x1);
+impl_mask_reductions!(m128x2);
+impl_mask_reductions!(m128x4);
+
+impl_mask_reductions!(msizex2);
+impl_mask_reductions!(msizex4);
+impl_mask_reductions!(msizex8);
+
+
\ No newline at end of file diff --git a/src/packed_simd/codegen/reductions/mask/fallback_impl.rs.html b/src/packed_simd/codegen/reductions/mask/fallback_impl.rs.html new file mode 100644 index 000000000..6ef99680a --- /dev/null +++ b/src/packed_simd/codegen/reductions/mask/fallback_impl.rs.html @@ -0,0 +1,477 @@ +fallback_impl.rs.html -- source
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+
+//! Default implementation of a mask reduction for any target.
+
+macro_rules! fallback_to_other_impl {
+    ($id:ident, $other:ident) => {
+        impl All for $id {
+            #[inline]
+            unsafe fn all(self) -> bool {
+                let m: $other = crate::mem::transmute(self);
+                m.all()
+            }
+        }
+        impl Any for $id {
+            #[inline]
+            unsafe fn any(self) -> bool {
+                let m: $other = crate::mem::transmute(self);
+                m.any()
+            }
+        }
+    };
+}
+
+/// Fallback implementation.
+macro_rules! fallback_impl {
+    // 16-bit wide masks:
+    (m8x2) => {
+        impl All for m8x2 {
+            #[inline]
+            unsafe fn all(self) -> bool {
+                let i: u16 = crate::mem::transmute(self);
+                i == u16::max_value()
+            }
+        }
+        impl Any for m8x2 {
+            #[inline]
+            unsafe fn any(self) -> bool {
+                let i: u16 = crate::mem::transmute(self);
+                i != 0
+            }
+        }
+    };
+    // 32-bit wide masks
+    (m8x4) => {
+        impl All for m8x4 {
+            #[inline]
+            unsafe fn all(self) -> bool {
+                let i: u32 = crate::mem::transmute(self);
+                i == u32::max_value()
+            }
+        }
+        impl Any for m8x4 {
+            #[inline]
+            unsafe fn any(self) -> bool {
+                let i: u32 = crate::mem::transmute(self);
+                i != 0
+            }
+        }
+    };
+    (m16x2) => {
+        fallback_to_other_impl!(m16x2, m8x4);
+    };
+    // 64-bit wide masks:
+    (m8x8) => {
+        impl All for m8x8 {
+            #[inline]
+            unsafe fn all(self) -> bool {
+                let i: u64 = crate::mem::transmute(self);
+                i == u64::max_value()
+            }
+        }
+        impl Any for m8x8 {
+            #[inline]
+            unsafe fn any(self) -> bool {
+                let i: u64 = crate::mem::transmute(self);
+                i != 0
+            }
+        }
+    };
+    (m16x4) => {
+        fallback_to_other_impl!(m16x4, m8x8);
+    };
+    (m32x2) => {
+        fallback_to_other_impl!(m32x2, m16x4);
+    };
+    // FIXME: 64x1 maxk
+    // 128-bit wide masks:
+    (m8x16) => {
+        impl All for m8x16 {
+            #[inline]
+            unsafe fn all(self) -> bool {
+                let i: u128 = crate::mem::transmute(self);
+                i == u128::max_value()
+            }
+        }
+        impl Any for m8x16 {
+            #[inline]
+            unsafe fn any(self) -> bool {
+                let i: u128 = crate::mem::transmute(self);
+                i != 0
+            }
+        }
+    };
+    (m16x8) => {
+        fallback_to_other_impl!(m16x8, m8x16);
+    };
+    (m32x4) => {
+        fallback_to_other_impl!(m32x4, m16x8);
+    };
+    (m64x2) => {
+        fallback_to_other_impl!(m64x2, m32x4);
+    };
+    (m128x1) => {
+        fallback_to_other_impl!(m128x1, m64x2);
+    };
+    // 256-bit wide masks
+    (m8x32) => {
+        impl All for m8x32 {
+            #[inline]
+            unsafe fn all(self) -> bool {
+                let i: [u128; 2] = crate::mem::transmute(self);
+                let o: [u128; 2] = [u128::max_value(); 2];
+                i == o
+            }
+        }
+        impl Any for m8x32 {
+            #[inline]
+            unsafe fn any(self) -> bool {
+                let i: [u128; 2] = crate::mem::transmute(self);
+                let o: [u128; 2] = [0; 2];
+                i != o
+            }
+        }
+    };
+    (m16x16) => {
+        fallback_to_other_impl!(m16x16, m8x32);
+    };
+    (m32x8) => {
+        fallback_to_other_impl!(m32x8, m16x16);
+    };
+    (m64x4) => {
+        fallback_to_other_impl!(m64x4, m32x8);
+    };
+    (m128x2) => {
+        fallback_to_other_impl!(m128x2, m64x4);
+    };
+    // 512-bit wide masks
+    (m8x64) => {
+        impl All for m8x64 {
+            #[inline]
+            unsafe fn all(self) -> bool {
+                let i: [u128; 4] = crate::mem::transmute(self);
+                let o: [u128; 4] = [u128::max_value(); 4];
+                i == o
+            }
+        }
+        impl Any for m8x64 {
+            #[inline]
+            unsafe fn any(self) -> bool {
+                let i: [u128; 4] = crate::mem::transmute(self);
+                let o: [u128; 4] = [0; 4];
+                i != o
+            }
+        }
+    };
+    (m16x32) => {
+        fallback_to_other_impl!(m16x32, m8x64);
+    };
+    (m32x16) => {
+        fallback_to_other_impl!(m32x16, m16x32);
+    };
+    (m64x8) => {
+        fallback_to_other_impl!(m64x8, m32x16);
+    };
+    (m128x4) => {
+        fallback_to_other_impl!(m128x4, m64x8);
+    };
+    // Masks with pointer-sized elements64
+    (msizex2) => {
+        cfg_if! {
+            if #[cfg(target_pointer_width = "64")] {
+                fallback_to_other_impl!(msizex2, m64x2);
+            } else if #[cfg(target_pointer_width = "32")] {
+                fallback_to_other_impl!(msizex2, m32x2);
+            } else {
+                compile_error!("unsupported target_pointer_width");
+            }
+        }
+    };
+    (msizex4) => {
+        cfg_if! {
+            if #[cfg(target_pointer_width = "64")] {
+                fallback_to_other_impl!(msizex4, m64x4);
+            } else if #[cfg(target_pointer_width = "32")] {
+                fallback_to_other_impl!(msizex4, m32x4);
+            } else {
+                compile_error!("unsupported target_pointer_width");
+            }
+        }
+    };
+    (msizex8) => {
+        cfg_if! {
+            if #[cfg(target_pointer_width = "64")] {
+                fallback_to_other_impl!(msizex8, m64x8);
+            } else if #[cfg(target_pointer_width = "32")] {
+                fallback_to_other_impl!(msizex8, m32x8);
+            } else {
+                compile_error!("unsupported target_pointer_width");
+            }
+        }
+    };
+}
+
+macro_rules! recurse_half {
+    ($vid:ident, $vid_h:ident) => {
+        impl All for $vid {
+            #[inline]
+            unsafe fn all(self) -> bool {
+                union U {
+                    halves: ($vid_h, $vid_h),
+                    vec: $vid,
+                }
+                let halves = U { vec: self }.halves;
+                halves.0.all() && halves.1.all()
+            }
+        }
+        impl Any for $vid {
+            #[inline]
+            unsafe fn any(self) -> bool {
+                union U {
+                    halves: ($vid_h, $vid_h),
+                    vec: $vid,
+                }
+                let halves = U { vec: self }.halves;
+                halves.0.any() || halves.1.any()
+            }
+        }
+    };
+}
+
+
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+
+//! Mask reductions implementation for `x86` and `x86_64` targets
+
+#[cfg(target_feature = "sse")]
+#[macro_use]
+mod sse;
+
+#[cfg(target_feature = "sse2")]
+#[macro_use]
+mod sse2;
+
+#[cfg(target_feature = "avx")]
+#[macro_use]
+mod avx;
+
+#[cfg(target_feature = "avx2")]
+#[macro_use]
+mod avx2;
+
+/// x86 64-bit m8x8 implementation
+macro_rules! x86_m8x8_impl {
+    ($id:ident) => {
+        cfg_if! {
+            if #[cfg(all(target_arch = "x86_64", target_feature = "sse"))] {
+                x86_m8x8_sse_impl!($id);
+            } else {
+                fallback_impl!($id);
+            }
+        }
+    };
+}
+
+/// x86 128-bit m8x16 implementation
+macro_rules! x86_m8x16_impl {
+    ($id:ident) => {
+        cfg_if! {
+            if #[cfg(target_feature = "sse2")] {
+                x86_m8x16_sse2_impl!($id);
+            } else {
+                fallback_impl!($id);
+            }
+        }
+    };
+}
+
+/// x86 128-bit m32x4 implementation
+macro_rules! x86_m32x4_impl {
+    ($id:ident) => {
+        cfg_if! {
+            if #[cfg(target_feature = "sse")] {
+                x86_m32x4_sse_impl!($id);
+            } else {
+                fallback_impl!($id);
+            }
+        }
+    };
+}
+
+/// x86 128-bit m64x2 implementation
+macro_rules! x86_m64x2_impl {
+    ($id:ident) => {
+        cfg_if! {
+            if #[cfg(target_feature = "sse2")] {
+                x86_m64x2_sse2_impl!($id);
+            } else if #[cfg(target_feature = "sse")] {
+                x86_m32x4_sse_impl!($id);
+            } else {
+                fallback_impl!($id);
+            }
+        }
+    };
+}
+
+/// x86 256-bit m8x32 implementation
+macro_rules! x86_m8x32_impl {
+    ($id:ident, $half_id:ident) => {
+        cfg_if! {
+            if #[cfg(target_feature = "avx2")] {
+                x86_m8x32_avx2_impl!($id);
+            } else if #[cfg(target_feature = "avx")] {
+                x86_m8x32_avx_impl!($id);
+            } else if #[cfg(target_feature = "sse2")] {
+                recurse_half!($id, $half_id);
+            } else {
+                fallback_impl!($id);
+            }
+        }
+    };
+}
+
+/// x86 256-bit m32x8 implementation
+macro_rules! x86_m32x8_impl {
+    ($id:ident, $half_id:ident) => {
+        cfg_if! {
+            if #[cfg(target_feature = "avx")] {
+                x86_m32x8_avx_impl!($id);
+            } else if #[cfg(target_feature = "sse")] {
+                recurse_half!($id, $half_id);
+            } else {
+                fallback_impl!($id);
+            }
+        }
+    };
+}
+
+/// x86 256-bit m64x4 implementation
+macro_rules! x86_m64x4_impl {
+    ($id:ident, $half_id:ident) => {
+        cfg_if! {
+            if #[cfg(target_feature = "avx")] {
+                x86_m64x4_avx_impl!($id);
+            } else if #[cfg(target_feature = "sse")] {
+                recurse_half!($id, $half_id);
+            } else {
+                fallback_impl!($id);
+            }
+        }
+    };
+}
+
+/// Fallback implementation.
+macro_rules! x86_intr_impl {
+    ($id:ident) => {
+    impl All for $id {
+        #[inline]
+        unsafe fn all(self) -> bool {
+        use crate::llvm::simd_reduce_all;
+            simd_reduce_all(self.0)
+        }
+    }
+        impl Any for $id {
+            #[inline]
+            unsafe fn any(self) -> bool {
+            use crate::llvm::simd_reduce_any;
+                simd_reduce_any(self.0)
+            }
+        }
+    };
+}
+
+/// Mask reduction implementation for `x86` and `x86_64` targets
+macro_rules! impl_mask_reductions {
+    // 64-bit wide masks
+    (m8x8) => { x86_m8x8_impl!(m8x8); };
+    (m16x4) => { x86_m8x8_impl!(m16x4); };
+    (m32x2) => { x86_m8x8_impl!(m32x2); };
+    // 128-bit wide masks
+    (m8x16) => { x86_m8x16_impl!(m8x16); };
+    (m16x8) => { x86_m8x16_impl!(m16x8); };
+    (m32x4) => { x86_m32x4_impl!(m32x4); };
+    (m64x2) => { x86_m64x2_impl!(m64x2); };
+    (m128x1) => { x86_intr_impl!(m128x1); };
+    // 256-bit wide masks:
+    (m8x32) => { x86_m8x32_impl!(m8x32, m8x16); };
+    (m16x16) => { x86_m8x32_impl!(m16x16, m16x8); };
+    (m32x8) => { x86_m32x8_impl!(m32x8, m32x4); };
+    (m64x4) => { x86_m64x4_impl!(m64x4, m64x2); };
+    (m128x2) => { x86_intr_impl!(m128x2); };
+    (msizex2) => {
+        cfg_if! {
+            if #[cfg(target_pointer_width = "64")] {
+                fallback_to_other_impl!(msizex2, m64x2);
+            } else if #[cfg(target_pointer_width = "32")] {
+                fallback_to_other_impl!(msizex2, m32x2);
+            } else {
+                compile_error!("unsupported target_pointer_width");
+            }
+        }
+    };
+    (msizex4) => {
+        cfg_if! {
+            if #[cfg(target_pointer_width = "64")] {
+                fallback_to_other_impl!(msizex4, m64x4);
+            } else if #[cfg(target_pointer_width = "32")] {
+                fallback_to_other_impl!(msizex4, m32x4);
+            } else {
+                compile_error!("unsupported target_pointer_width");
+            }
+        }
+    };
+    (msizex8) => {
+        cfg_if! {
+            if #[cfg(target_pointer_width = "64")] {
+                fallback_to_other_impl!(msizex8, m64x8);
+            } else if #[cfg(target_pointer_width = "32")] {
+                fallback_to_other_impl!(msizex8, m32x8);
+            } else {
+                compile_error!("unsupported target_pointer_width");
+            }
+        }
+    };
+
+    // Fallback to LLVM's default code-generation:
+    ($id:ident) => { fallback_impl!($id); };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/codegen/reductions/mask/x86/sse.rs.html b/src/packed_simd/codegen/reductions/mask/x86/sse.rs.html new file mode 100644 index 000000000..c986863c7 --- /dev/null +++ b/src/packed_simd/codegen/reductions/mask/x86/sse.rs.html @@ -0,0 +1,139 @@ +sse.rs.html -- source
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+//! Mask reductions implementation for `x86` and `x86_64` targets with `SSE`.
+#![allow(unused)]
+
+/// `x86`/`x86_64` 128-bit `m32x4` `SSE` implementation
+macro_rules! x86_m32x4_sse_impl {
+    ($id:ident) => {
+        impl All for $id {
+            #[inline]
+            #[target_feature(enable = "sse")]
+            unsafe fn all(self) -> bool {
+                #[cfg(target_arch = "x86")]
+                use crate::arch::x86::_mm_movemask_ps;
+                #[cfg(target_arch = "x86_64")]
+                use crate::arch::x86_64::_mm_movemask_ps;
+                // _mm_movemask_ps(a) creates a 4bit mask containing the
+                // most significant bit of each lane of `a`. If all
+                // bits are set, then all 4 lanes of the mask are
+                // true.
+                _mm_movemask_ps(crate::mem::transmute(self))
+                    == 0b_1111_i32
+            }
+        }
+        impl Any for $id {
+            #[inline]
+            #[target_feature(enable = "sse")]
+            unsafe fn any(self) -> bool {
+                #[cfg(target_arch = "x86")]
+                use crate::arch::x86::_mm_movemask_ps;
+                #[cfg(target_arch = "x86_64")]
+                use crate::arch::x86_64::_mm_movemask_ps;
+
+                _mm_movemask_ps(crate::mem::transmute(self)) != 0
+            }
+        }
+    };
+}
+
+macro_rules! x86_m8x8_sse_impl {
+    ($id:ident) => {
+        impl All for $id {
+            #[inline]
+            #[target_feature(enable = "sse")]
+            unsafe fn all(self) -> bool {
+                #[cfg(target_arch = "x86")]
+                use crate::arch::x86::_mm_movemask_pi8;
+                #[cfg(target_arch = "x86_64")]
+                use crate::arch::x86_64::_mm_movemask_pi8;
+                // _mm_movemask_pi8(a) creates an 8bit mask containing the most
+                // significant bit of each byte of `a`. If all bits are set,
+                // then all 8 lanes of the mask are true.
+                _mm_movemask_pi8(crate::mem::transmute(self))
+                    == u8::max_value() as i32
+            }
+        }
+        impl Any for $id {
+            #[inline]
+            #[target_feature(enable = "sse")]
+            unsafe fn any(self) -> bool {
+                #[cfg(target_arch = "x86")]
+                use crate::arch::x86::_mm_movemask_pi8;
+                #[cfg(target_arch = "x86_64")]
+                use crate::arch::x86_64::_mm_movemask_pi8;
+
+                _mm_movemask_pi8(crate::mem::transmute(self)) != 0
+            }
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/codegen/reductions/mask/x86/sse2.rs.html b/src/packed_simd/codegen/reductions/mask/x86/sse2.rs.html new file mode 100644 index 000000000..ab1ead281 --- /dev/null +++ b/src/packed_simd/codegen/reductions/mask/x86/sse2.rs.html @@ -0,0 +1,143 @@ +sse2.rs.html -- source
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+//! Mask reductions implementation for `x86` and `x86_64` targets with `SSE2`.
+#![allow(unused)]
+
+/// `x86`/`x86_64` 128-bit m64x2 `SSE2` implementation
+macro_rules! x86_m64x2_sse2_impl {
+    ($id:ident) => {
+        impl All for $id {
+            #[inline]
+            #[target_feature(enable = "sse")]
+            unsafe fn all(self) -> bool {
+                #[cfg(target_arch = "x86")]
+                use crate::arch::x86::_mm_movemask_pd;
+                #[cfg(target_arch = "x86_64")]
+                use crate::arch::x86_64::_mm_movemask_pd;
+                // _mm_movemask_pd(a) creates a 2bit mask containing the
+                // most significant bit of each lane of `a`. If all
+                // bits are set, then all 2 lanes of the mask are
+                // true.
+                _mm_movemask_pd(crate::mem::transmute(self))
+                    == 0b_11_i32
+            }
+        }
+        impl Any for $id {
+            #[inline]
+            #[target_feature(enable = "sse")]
+            unsafe fn any(self) -> bool {
+                #[cfg(target_arch = "x86")]
+                use crate::arch::x86::_mm_movemask_pd;
+                #[cfg(target_arch = "x86_64")]
+                use crate::arch::x86_64::_mm_movemask_pd;
+
+                _mm_movemask_pd(crate::mem::transmute(self)) != 0
+            }
+        }
+    };
+}
+
+/// `x86`/`x86_64` 128-bit m8x16 `SSE2` implementation
+macro_rules! x86_m8x16_sse2_impl {
+    ($id:ident) => {
+        impl All for $id {
+            #[inline]
+            #[target_feature(enable = "sse2")]
+            unsafe fn all(self) -> bool {
+                #[cfg(target_arch = "x86")]
+                use crate::arch::x86::_mm_movemask_epi8;
+                #[cfg(target_arch = "x86_64")]
+                use crate::arch::x86_64::_mm_movemask_epi8;
+                // _mm_movemask_epi8(a) creates a 16bit mask containing the
+                // most significant bit of each byte of `a`. If all
+                // bits are set, then all 16 lanes of the mask are
+                // true.
+                _mm_movemask_epi8(crate::mem::transmute(self))
+                    == i32::from(u16::max_value())
+            }
+        }
+        impl Any for $id {
+            #[inline]
+            #[target_feature(enable = "sse2")]
+            unsafe fn any(self) -> bool {
+                #[cfg(target_arch = "x86")]
+                use crate::arch::x86::_mm_movemask_epi8;
+                #[cfg(target_arch = "x86_64")]
+                use crate::arch::x86_64::_mm_movemask_epi8;
+
+                _mm_movemask_epi8(crate::mem::transmute(self)) != 0
+            }
+        }
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/codegen/shuffle.rs.html b/src/packed_simd/codegen/shuffle.rs.html new file mode 100644 index 000000000..30f6055cf --- /dev/null +++ b/src/packed_simd/codegen/shuffle.rs.html @@ -0,0 +1,303 @@ +shuffle.rs.html -- source
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+
+//! Implementations of the `ShuffleResult` trait for the different numbers of
+//! lanes and vector element types.
+
+use crate::masks::*;
+use crate::sealed::{Shuffle, Seal};
+
+macro_rules! impl_shuffle {
+    ($array:ty, $base:ty, $out:ty) => {
+        impl Seal<$array> for $base {}
+        impl Shuffle<$array> for $base {
+            type Output = $out;
+        }
+    }
+}
+
+impl_shuffle! { [u32; 2], i8, crate::codegen::i8x2 }
+impl_shuffle! { [u32; 4], i8, crate::codegen::i8x4 }
+impl_shuffle! { [u32; 8], i8, crate::codegen::i8x8 }
+impl_shuffle! { [u32; 16], i8, crate::codegen::i8x16 }
+impl_shuffle! { [u32; 32], i8, crate::codegen::i8x32 }
+impl_shuffle! { [u32; 64], i8, crate::codegen::i8x64 }
+
+impl_shuffle! { [u32; 2], u8, crate::codegen::u8x2 }
+impl_shuffle! { [u32; 4], u8, crate::codegen::u8x4 }
+impl_shuffle! { [u32; 8], u8, crate::codegen::u8x8 }
+impl_shuffle! { [u32; 16], u8, crate::codegen::u8x16 }
+impl_shuffle! { [u32; 32], u8, crate::codegen::u8x32 }
+impl_shuffle! { [u32; 64], u8, crate::codegen::u8x64 }
+
+impl_shuffle! { [u32; 2], m8, crate::codegen::m8x2 }
+impl_shuffle! { [u32; 4], m8, crate::codegen::m8x4 }
+impl_shuffle! { [u32; 8], m8, crate::codegen::m8x8 }
+impl_shuffle! { [u32; 16], m8, crate::codegen::m8x16 }
+impl_shuffle! { [u32; 32], m8, crate::codegen::m8x32 }
+impl_shuffle! { [u32; 64], m8, crate::codegen::m8x64 }
+
+impl_shuffle! { [u32; 2], i16, crate::codegen::i16x2 }
+impl_shuffle! { [u32; 4], i16, crate::codegen::i16x4 }
+impl_shuffle! { [u32; 8], i16, crate::codegen::i16x8 }
+impl_shuffle! { [u32; 16], i16, crate::codegen::i16x16 }
+impl_shuffle! { [u32; 32], i16, crate::codegen::i16x32 }
+
+impl_shuffle! { [u32; 2], u16, crate::codegen::u16x2 }
+impl_shuffle! { [u32; 4], u16, crate::codegen::u16x4 }
+impl_shuffle! { [u32; 8], u16, crate::codegen::u16x8 }
+impl_shuffle! { [u32; 16], u16, crate::codegen::u16x16 }
+impl_shuffle! { [u32; 32], u16, crate::codegen::u16x32 }
+
+impl_shuffle! { [u32; 2], m16, crate::codegen::m16x2 }
+impl_shuffle! { [u32; 4], m16, crate::codegen::m16x4 }
+impl_shuffle! { [u32; 8], m16, crate::codegen::m16x8 }
+impl_shuffle! { [u32; 16], m16, crate::codegen::m16x16 }
+
+impl_shuffle! { [u32; 2], i32, crate::codegen::i32x2 }
+impl_shuffle! { [u32; 4], i32, crate::codegen::i32x4 }
+impl_shuffle! { [u32; 8], i32, crate::codegen::i32x8 }
+impl_shuffle! { [u32; 16], i32, crate::codegen::i32x16 }
+
+impl_shuffle! { [u32; 2], u32, crate::codegen::u32x2 }
+impl_shuffle! { [u32; 4], u32, crate::codegen::u32x4 }
+impl_shuffle! { [u32; 8], u32, crate::codegen::u32x8 }
+impl_shuffle! { [u32; 16], u32, crate::codegen::u32x16 }
+
+impl_shuffle! { [u32; 2], f32, crate::codegen::f32x2 }
+impl_shuffle! { [u32; 4], f32, crate::codegen::f32x4 }
+impl_shuffle! { [u32; 8], f32, crate::codegen::f32x8 }
+impl_shuffle! { [u32; 16], f32, crate::codegen::f32x16 }
+
+impl_shuffle! { [u32; 2], m32, crate::codegen::m32x2 }
+impl_shuffle! { [u32; 4], m32, crate::codegen::m32x4 }
+impl_shuffle! { [u32; 8], m32, crate::codegen::m32x8 }
+impl_shuffle! { [u32; 16], m32, crate::codegen::m32x16 }
+
+/* FIXME: 64-bit single element vector
+impl_shuffle! { [u32; 1], i64, crate::codegen::i64x1 }
+*/
+impl_shuffle! { [u32; 2], i64, crate::codegen::i64x2 }
+impl_shuffle! { [u32; 4], i64, crate::codegen::i64x4 }
+impl_shuffle! { [u32; 8], i64, crate::codegen::i64x8 }
+
+/* FIXME: 64-bit single element vector
+impl_shuffle! { [u32; 1], i64, crate::codegen::i64x1 }
+*/
+impl_shuffle! { [u32; 2], u64, crate::codegen::u64x2 }
+impl_shuffle! { [u32; 4], u64, crate::codegen::u64x4 }
+impl_shuffle! { [u32; 8], u64, crate::codegen::u64x8 }
+
+/* FIXME: 64-bit single element vector
+impl_shuffle! { [u32; 1], i64, crate::codegen::i64x1 }
+*/
+impl_shuffle! { [u32; 2], f64, crate::codegen::f64x2 }
+impl_shuffle! { [u32; 4], f64, crate::codegen::f64x4 }
+impl_shuffle! { [u32; 8], f64, crate::codegen::f64x8 }
+
+/* FIXME: 64-bit single element vector
+impl_shuffle! { [u32; 1], i64, crate::codegen::i64x1 }
+*/
+impl_shuffle! { [u32; 2], m64, crate::codegen::m64x2 }
+impl_shuffle! { [u32; 4], m64, crate::codegen::m64x4 }
+impl_shuffle! { [u32; 8], m64, crate::codegen::m64x8 }
+
+impl_shuffle! { [u32; 2], isize, crate::codegen::isizex2 }
+impl_shuffle! { [u32; 4], isize, crate::codegen::isizex4 }
+impl_shuffle! { [u32; 8], isize, crate::codegen::isizex8 }
+
+impl_shuffle! { [u32; 2], usize, crate::codegen::usizex2 }
+impl_shuffle! { [u32; 4], usize, crate::codegen::usizex4 }
+impl_shuffle! { [u32; 8], usize, crate::codegen::usizex8 }
+
+impl_shuffle! { [u32; 2], msize, crate::codegen::msizex2 }
+impl_shuffle! { [u32; 4], msize, crate::codegen::msizex4 }
+impl_shuffle! { [u32; 8], msize, crate::codegen::msizex8 }
+
+impl<T> Seal<[u32; 2]> for *const T {}
+impl<T> Shuffle<[u32; 2]> for *const T {
+    type Output = crate::codegen::cptrx2<T>;
+}
+impl<T> Seal<[u32; 4]> for *const T {}
+impl<T> Shuffle<[u32; 4]> for *const T {
+    type Output = crate::codegen::cptrx4<T>;
+}
+impl<T> Seal<[u32; 8]> for *const T {}
+impl<T> Shuffle<[u32; 8]> for *const T {
+    type Output = crate::codegen::cptrx8<T>;
+}
+
+impl<T> Seal<[u32; 2]> for *mut T {}
+impl<T> Shuffle<[u32; 2]> for *mut T {
+    type Output = crate::codegen::mptrx2<T>;
+}
+impl<T> Seal<[u32; 4]> for *mut T {}
+impl<T> Shuffle<[u32; 4]> for *mut T {
+    type Output = crate::codegen::mptrx4<T>;
+}
+impl<T> Seal<[u32; 8]> for *mut T {}
+impl<T> Shuffle<[u32; 8]> for *mut T {
+    type Output = crate::codegen::mptrx8<T>;
+}
+
+impl_shuffle! { [u32; 1], i128, crate::codegen::i128x1 }
+impl_shuffle! { [u32; 2], i128, crate::codegen::i128x2 }
+impl_shuffle! { [u32; 4], i128, crate::codegen::i128x4 }
+
+impl_shuffle! { [u32; 1], u128, crate::codegen::u128x1 }
+impl_shuffle! { [u32; 2], u128, crate::codegen::u128x2 }
+impl_shuffle! { [u32; 4], u128, crate::codegen::u128x4 }
+
+impl_shuffle! { [u32; 1], m128, crate::codegen::m128x1 }
+impl_shuffle! { [u32; 2], m128, crate::codegen::m128x2 }
+impl_shuffle! { [u32; 4], m128, crate::codegen::m128x4 }
+
+
\ No newline at end of file diff --git a/src/packed_simd/codegen/shuffle1_dyn.rs.html b/src/packed_simd/codegen/shuffle1_dyn.rs.html new file mode 100644 index 000000000..b2b7c01ec --- /dev/null +++ b/src/packed_simd/codegen/shuffle1_dyn.rs.html @@ -0,0 +1,867 @@ +shuffle1_dyn.rs.html -- source
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+
+//! Shuffle vector lanes with run-time indices.
+
+use crate::*;
+
+pub trait Shuffle1Dyn {
+    type Indices;
+    fn shuffle1_dyn(self, _: Self::Indices) -> Self;
+}
+
+// Fallback implementation
+macro_rules! impl_fallback {
+    ($id:ident) => {
+        impl Shuffle1Dyn for $id {
+            type Indices = Self;
+            #[inline]
+            fn shuffle1_dyn(self, indices: Self::Indices) -> Self {
+                let mut result = Self::splat(0);
+                for i in 0..$id::lanes() {
+                    result = result
+                        .replace(i, self.extract(indices.extract(i) as usize));
+                }
+                result
+            }
+        }
+    };
+}
+
+macro_rules! impl_shuffle1_dyn {
+    (u8x8) => {
+        cfg_if! {
+            if #[cfg(all(any(target_arch = "x86", target_arch = "x86_64"),
+                         target_feature = "ssse3"))] {
+                impl Shuffle1Dyn for u8x8 {
+                    type Indices = Self;
+                    #[inline]
+                    fn shuffle1_dyn(self, indices: Self::Indices) -> Self {
+                        #[cfg(target_arch = "x86")]
+                        use crate::arch::x86::_mm_shuffle_pi8;
+                        #[cfg(target_arch = "x86_64")]
+                        use crate::arch::x86_64::_mm_shuffle_pi8;
+
+                        unsafe {
+                            crate::mem::transmute(
+                                _mm_shuffle_pi8(
+                                    crate::mem::transmute(self.0),
+                                    crate::mem::transmute(indices.0)
+                                )
+                            )
+                        }
+                    }
+                }
+            } else if #[cfg(all(
+                any(
+                    all(target_aarch = "aarch64", target_feature = "neon"),
+                    all(target_aarch = "arm", target_feature = "v7",
+                        target_feature = "neon")
+                ),
+                any(feature = "core_arch", libcore_neon)
+            )
+            )] {
+                impl Shuffle1Dyn for u8x8 {
+                    type Indices = Self;
+                    #[inline]
+                    fn shuffle1_dyn(self, indices: Self::Indices) -> Self {
+                        #[cfg(targt_arch = "aarch64")]
+                        use crate::arch::aarch64::vtbl1_u8;
+                        #[cfg(targt_arch = "arm")]
+                        use crate::arch::arm::vtbl1_u8;
+
+                        // This is safe because the binary is compiled with
+                        // neon enabled at compile-time and can therefore only
+                        // run on CPUs that have it enabled.
+                        unsafe {
+                            Simd(mem::transmute(
+                                vtbl1_u8(mem::transmute(self.0),
+                                        crate::mem::transmute(indices.0))
+                            ))
+                        }
+                    }
+                }
+            } else {
+                impl_fallback!(u8x8);
+            }
+        }
+    };
+    (u8x16) => {
+        cfg_if! {
+            if #[cfg(all(any(target_arch = "x86", target_arch = "x86_64"),
+                         target_feature = "ssse3"))] {
+                impl Shuffle1Dyn for u8x16 {
+                    type Indices = Self;
+                    #[inline]
+                    fn shuffle1_dyn(self, indices: Self::Indices) -> Self {
+                        #[cfg(target_arch = "x86")]
+                        use crate::arch::x86::_mm_shuffle_epi8;
+                        #[cfg(target_arch = "x86_64")]
+                        use crate::arch::x86_64::_mm_shuffle_epi8;
+                        // This is safe because the binary is compiled with
+                        // ssse3 enabled at compile-time and can therefore only
+                        // run on CPUs that have it enabled.
+                        unsafe {
+                            Simd(mem::transmute(
+                                _mm_shuffle_epi8(mem::transmute(self.0),
+                                                crate::mem::transmute(indices))
+                            ))
+                        }
+                    }
+                }
+            } else if #[cfg(all(target_aarch = "aarch64", target_feature = "neon",
+                                any(feature = "core_arch", libcore_neon)))] {
+                impl Shuffle1Dyn for u8x16 {
+                    type Indices = Self;
+                    #[inline]
+                    fn shuffle1_dyn(self, indices: Self::Indices) -> Self {
+                        use crate::arch::aarch64::vqtbl1q_u8;
+
+                        // This is safe because the binary is compiled with
+                        // neon enabled at compile-time and can therefore only
+                        // run on CPUs that have it enabled.
+                        unsafe {
+                            Simd(mem::transmute(
+                                vqtbl1q_u8(mem::transmute(self.0),
+                                          crate::mem::transmute(indices.0))
+                            ))
+                        }
+                    }
+                }
+            } else if #[cfg(all(target_aarch = "arm", target_feature = "v7",
+                                target_feature = "neon",
+                                any(feature = "core_arch", libcore_neon)))] {
+                impl Shuffle1Dyn for u8x16 {
+                    type Indices = Self;
+                    #[inline]
+                    fn shuffle1_dyn(self, indices: Self::Indices) -> Self {
+                        use crate::arch::arm::vtbl2_u8;
+
+                        // This is safe because the binary is compiled with
+                        // neon enabled at compile-time and can therefore only
+                        // run on CPUs that have it enabled.
+                        unsafe {
+                            union U {
+                                j: u8x16,
+                                s: (u8x8, u8x8),
+                            }
+
+                            let (i0, i1) = U { j: y }.s;
+
+                            let r0 = vtbl2_u8(
+                                mem::transmute(x),
+                                crate::mem::transmute(i0)
+                            );
+                            let r1 = vtbl2_u8(
+                                mem::transmute(x),
+                                crate::mem::transmute(i1)
+                            );
+
+                            let r = U { s: (r0, r1) }.j;
+
+                            Simd(mem::transmute(r))
+                        }
+                    }
+                }
+            } else {
+                impl_fallback!(u8x16);
+            }
+        }
+    };
+    (u16x8) => {
+        impl Shuffle1Dyn for u16x8 {
+            type Indices = Self;
+            #[inline]
+            fn shuffle1_dyn(self, indices: Self::Indices) -> Self {
+                let indices: u8x8 = (indices * 2).cast();
+                let indices: u8x16 = shuffle!(
+                    indices, [0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7]
+                );
+                let v = u8x16::new(
+                    0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1
+                );
+                let indices = indices + v;
+                unsafe {
+                    let s: u8x16 =crate::mem::transmute(self);
+                   crate::mem::transmute(s.shuffle1_dyn(indices))
+                }
+            }
+        }
+    };
+    (u32x4) => {
+        cfg_if! {
+            if #[cfg(all(any(target_arch = "x86", target_arch = "x86_64"),
+                         target_feature = "avx"))] {
+                impl Shuffle1Dyn for u32x4 {
+                    type Indices = Self;
+                    #[inline]
+                    fn shuffle1_dyn(self, indices: Self::Indices) -> Self {
+                        #[cfg(target_arch = "x86")]
+                        use crate::arch::x86::{_mm_permutevar_ps};
+                        #[cfg(target_arch = "x86_64")]
+                        use crate::arch::x86_64::{_mm_permutevar_ps};
+
+                        unsafe {
+                            crate::mem::transmute(
+                                _mm_permutevar_ps(
+                                    crate::mem::transmute(self.0),
+                                    crate::mem::transmute(indices.0)
+                                )
+                            )
+                        }
+                    }
+                }
+            } else {
+                impl Shuffle1Dyn for u32x4 {
+                    type Indices = Self;
+                    #[inline]
+                    fn shuffle1_dyn(self, indices: Self::Indices) -> Self {
+                        let indices: u8x4 = (indices * 4).cast();
+                        let indices: u8x16 = shuffle!(
+                            indices,
+                            [0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3]
+                        );
+                        let v = u8x16::new(
+                            0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3
+                        );
+                        let indices = indices + v;
+                        unsafe {
+                            let s: u8x16 =crate::mem::transmute(self);
+                           crate::mem::transmute(s.shuffle1_dyn(indices))
+                        }
+                    }
+                }
+            }
+        }
+    };
+    (u64x2) => {
+        cfg_if! {
+            if #[cfg(all(any(target_arch = "x86", target_arch = "x86_64"),
+                         target_feature = "avx"))] {
+                impl Shuffle1Dyn for u64x2 {
+                    type Indices = Self;
+                    #[inline]
+                    fn shuffle1_dyn(self, indices: Self::Indices) -> Self {
+                        #[cfg(target_arch = "x86")]
+                        use crate::arch::x86::{_mm_permutevar_pd};
+                        #[cfg(target_arch = "x86_64")]
+                        use crate::arch::x86_64::{_mm_permutevar_pd};
+                        // _mm_permutevar_pd uses the _second_ bit of each
+                        // element to perform the selection, that is: 0b00 => 0,
+                        // 0b10 => 1:
+                        let indices = indices << 1;
+                        unsafe {
+                            crate::mem::transmute(
+                                _mm_permutevar_pd(
+                                    crate::mem::transmute(self),
+                                    crate::mem::transmute(indices)
+                                )
+                            )
+                        }
+                    }
+                }
+            } else {
+                impl Shuffle1Dyn for u64x2 {
+                    type Indices = Self;
+                    #[inline]
+                    fn shuffle1_dyn(self, indices: Self::Indices) -> Self {
+                        let indices: u8x2 = (indices * 8).cast();
+                        let indices: u8x16 = shuffle!(
+                            indices,
+                            [0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1]
+                        );
+                        let v = u8x16::new(
+                            0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7
+                        );
+                        let indices = indices + v;
+                        unsafe {
+                            let s: u8x16 =crate::mem::transmute(self);
+                           crate::mem::transmute(s.shuffle1_dyn(indices))
+                        }
+                    }
+                }
+            }
+        }
+    };
+    (u128x1) => {
+        impl Shuffle1Dyn for u128x1 {
+            type Indices = Self;
+            #[inline]
+            fn shuffle1_dyn(self, _indices: Self::Indices) -> Self {
+                self
+            }
+        }
+    };
+    ($id:ident) => { impl_fallback!($id); }
+}
+
+impl_shuffle1_dyn!(u8x2);
+impl_shuffle1_dyn!(u8x4);
+impl_shuffle1_dyn!(u8x8);
+impl_shuffle1_dyn!(u8x16);
+impl_shuffle1_dyn!(u8x32);
+impl_shuffle1_dyn!(u8x64);
+
+impl_shuffle1_dyn!(u16x2);
+impl_shuffle1_dyn!(u16x4);
+impl_shuffle1_dyn!(u16x8);
+impl_shuffle1_dyn!(u16x16);
+impl_shuffle1_dyn!(u16x32);
+
+impl_shuffle1_dyn!(u32x2);
+impl_shuffle1_dyn!(u32x4);
+impl_shuffle1_dyn!(u32x8);
+impl_shuffle1_dyn!(u32x16);
+
+impl_shuffle1_dyn!(u64x2);
+impl_shuffle1_dyn!(u64x4);
+impl_shuffle1_dyn!(u64x8);
+
+impl_shuffle1_dyn!(usizex2);
+impl_shuffle1_dyn!(usizex4);
+impl_shuffle1_dyn!(usizex8);
+
+impl_shuffle1_dyn!(u128x1);
+impl_shuffle1_dyn!(u128x2);
+impl_shuffle1_dyn!(u128x4);
+
+// Implementation for non-unsigned vector types
+macro_rules! impl_shuffle1_dyn_non_u {
+    ($id:ident, $uid:ident) => {
+        impl Shuffle1Dyn for $id {
+            type Indices = $uid;
+            #[inline]
+            fn shuffle1_dyn(self, indices: Self::Indices) -> Self {
+                unsafe {
+                    let u: $uid = crate::mem::transmute(self);
+                    crate::mem::transmute(u.shuffle1_dyn(indices))
+                }
+            }
+        }
+    };
+}
+
+impl_shuffle1_dyn_non_u!(i8x2, u8x2);
+impl_shuffle1_dyn_non_u!(i8x4, u8x4);
+impl_shuffle1_dyn_non_u!(i8x8, u8x8);
+impl_shuffle1_dyn_non_u!(i8x16, u8x16);
+impl_shuffle1_dyn_non_u!(i8x32, u8x32);
+impl_shuffle1_dyn_non_u!(i8x64, u8x64);
+
+impl_shuffle1_dyn_non_u!(i16x2, u16x2);
+impl_shuffle1_dyn_non_u!(i16x4, u16x4);
+impl_shuffle1_dyn_non_u!(i16x8, u16x8);
+impl_shuffle1_dyn_non_u!(i16x16, u16x16);
+impl_shuffle1_dyn_non_u!(i16x32, u16x32);
+
+impl_shuffle1_dyn_non_u!(i32x2, u32x2);
+impl_shuffle1_dyn_non_u!(i32x4, u32x4);
+impl_shuffle1_dyn_non_u!(i32x8, u32x8);
+impl_shuffle1_dyn_non_u!(i32x16, u32x16);
+
+impl_shuffle1_dyn_non_u!(i64x2, u64x2);
+impl_shuffle1_dyn_non_u!(i64x4, u64x4);
+impl_shuffle1_dyn_non_u!(i64x8, u64x8);
+
+impl_shuffle1_dyn_non_u!(isizex2, usizex2);
+impl_shuffle1_dyn_non_u!(isizex4, usizex4);
+impl_shuffle1_dyn_non_u!(isizex8, usizex8);
+
+impl_shuffle1_dyn_non_u!(i128x1, u128x1);
+impl_shuffle1_dyn_non_u!(i128x2, u128x2);
+impl_shuffle1_dyn_non_u!(i128x4, u128x4);
+
+impl_shuffle1_dyn_non_u!(m8x2, u8x2);
+impl_shuffle1_dyn_non_u!(m8x4, u8x4);
+impl_shuffle1_dyn_non_u!(m8x8, u8x8);
+impl_shuffle1_dyn_non_u!(m8x16, u8x16);
+impl_shuffle1_dyn_non_u!(m8x32, u8x32);
+impl_shuffle1_dyn_non_u!(m8x64, u8x64);
+
+impl_shuffle1_dyn_non_u!(m16x2, u16x2);
+impl_shuffle1_dyn_non_u!(m16x4, u16x4);
+impl_shuffle1_dyn_non_u!(m16x8, u16x8);
+impl_shuffle1_dyn_non_u!(m16x16, u16x16);
+impl_shuffle1_dyn_non_u!(m16x32, u16x32);
+
+impl_shuffle1_dyn_non_u!(m32x2, u32x2);
+impl_shuffle1_dyn_non_u!(m32x4, u32x4);
+impl_shuffle1_dyn_non_u!(m32x8, u32x8);
+impl_shuffle1_dyn_non_u!(m32x16, u32x16);
+
+impl_shuffle1_dyn_non_u!(m64x2, u64x2);
+impl_shuffle1_dyn_non_u!(m64x4, u64x4);
+impl_shuffle1_dyn_non_u!(m64x8, u64x8);
+
+impl_shuffle1_dyn_non_u!(msizex2, usizex2);
+impl_shuffle1_dyn_non_u!(msizex4, usizex4);
+impl_shuffle1_dyn_non_u!(msizex8, usizex8);
+
+impl_shuffle1_dyn_non_u!(m128x1, u128x1);
+impl_shuffle1_dyn_non_u!(m128x2, u128x2);
+impl_shuffle1_dyn_non_u!(m128x4, u128x4);
+
+impl_shuffle1_dyn_non_u!(f32x2, u32x2);
+impl_shuffle1_dyn_non_u!(f32x4, u32x4);
+impl_shuffle1_dyn_non_u!(f32x8, u32x8);
+impl_shuffle1_dyn_non_u!(f32x16, u32x16);
+
+impl_shuffle1_dyn_non_u!(f64x2, u64x2);
+impl_shuffle1_dyn_non_u!(f64x4, u64x4);
+impl_shuffle1_dyn_non_u!(f64x8, u64x8);
+
+// Implementation for non-unsigned vector types
+macro_rules! impl_shuffle1_dyn_ptr {
+    ($id:ident, $uid:ident) => {
+        impl<T> Shuffle1Dyn for $id<T> {
+            type Indices = $uid;
+            #[inline]
+            fn shuffle1_dyn(self, indices: Self::Indices) -> Self {
+                unsafe {
+                    let u: $uid = crate::mem::transmute(self);
+                    crate::mem::transmute(u.shuffle1_dyn(indices))
+                }
+            }
+        }
+    };
+}
+
+impl_shuffle1_dyn_ptr!(cptrx2, usizex2);
+impl_shuffle1_dyn_ptr!(cptrx4, usizex4);
+impl_shuffle1_dyn_ptr!(cptrx8, usizex8);
+
+impl_shuffle1_dyn_ptr!(mptrx2, usizex2);
+impl_shuffle1_dyn_ptr!(mptrx4, usizex4);
+impl_shuffle1_dyn_ptr!(mptrx8, usizex8);
+
+
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+189
+
+//! Horizontal swap bytes reductions.
+
+// FIXME: investigate using `llvm.bswap`
+// https://github.com/rust-lang-nursery/packed_simd/issues/19
+
+use crate::*;
+
+crate trait SwapBytes {
+    fn swap_bytes(self) -> Self;
+}
+
+macro_rules! impl_swap_bytes {
+    (v16: $($id:ident,)+) => {
+        $(
+            impl SwapBytes for $id {
+                #[inline]
+                fn swap_bytes(self) -> Self {
+                    unsafe { shuffle!(self, [1, 0]) }
+                }
+            }
+        )+
+    };
+    (v32: $($id:ident,)+) => {
+        $(
+            impl SwapBytes for $id {
+                #[inline]
+                #[allow(clippy::useless_transmute)]
+                fn swap_bytes(self) -> Self {
+                    unsafe {
+                        let bytes: u8x4 = crate::mem::transmute(self);
+                        let result: u8x4 = shuffle!(bytes, [3, 2, 1, 0]);
+                        crate::mem::transmute(result)
+                    }
+                }
+            }
+        )+
+    };
+    (v64: $($id:ident,)+) => {
+        $(
+            impl SwapBytes for $id {
+                #[inline]
+                #[allow(clippy::useless_transmute)]
+                fn swap_bytes(self) -> Self {
+                    unsafe {
+                        let bytes: u8x8 = crate::mem::transmute(self);
+                        let result: u8x8 = shuffle!(
+                            bytes, [7, 6, 5, 4, 3, 2, 1, 0]
+                        );
+                        crate::mem::transmute(result)
+                    }
+                }
+            }
+        )+
+    };
+    (v128: $($id:ident,)+) => {
+        $(
+            impl SwapBytes for $id {
+                #[inline]
+                #[allow(clippy::useless_transmute)]
+                fn swap_bytes(self) -> Self {
+                    unsafe {
+                        let bytes: u8x16 = crate::mem::transmute(self);
+                        let result: u8x16 = shuffle!(bytes, [
+                            15, 14, 13, 12, 11, 10, 9, 8,
+                            7, 6, 5, 4, 3, 2, 1, 0
+                        ]);
+                        crate::mem::transmute(result)
+                    }
+                }
+            }
+        )+
+    };
+    (v256: $($id:ident,)+) => {
+        $(
+            impl SwapBytes for $id {
+                #[inline]
+                #[allow(clippy::useless_transmute)]
+                fn swap_bytes(self) -> Self {
+                    unsafe {
+                        let bytes: u8x32 = crate::mem::transmute(self);
+                        let result: u8x32 = shuffle!(bytes, [
+                            31, 30, 29, 28, 27, 26, 25, 24,
+                            23, 22, 21, 20, 19, 18, 17, 16,
+                            15, 14, 13, 12, 11, 10, 9,  8,
+                            7,  6,  5,  4,  3,  2,  1,  0
+                        ]);
+                        crate::mem::transmute(result)
+                    }
+                }
+            }
+        )+
+    };
+    (v512: $($id:ident,)+) => {
+        $(
+            impl SwapBytes for $id {
+                #[inline]
+                #[allow(clippy::useless_transmute)]
+                fn swap_bytes(self) -> Self {
+                    unsafe {
+                        let bytes: u8x64 = crate::mem::transmute(self);
+                        let result: u8x64 = shuffle!(bytes, [
+                            63, 62, 61, 60, 59, 58, 57, 56,
+                            55, 54, 53, 52, 51, 50, 49, 48,
+                            47, 46, 45, 44, 43, 42, 41, 40,
+                            39, 38, 37, 36, 35, 34, 33, 32,
+                            31, 30, 29, 28, 27, 26, 25, 24,
+                            23, 22, 21, 20, 19, 18, 17, 16,
+                            15, 14, 13, 12, 11, 10, 9,  8,
+                            7,  6,  5,  4,  3,  2,  1,  0
+                        ]);
+                        crate::mem::transmute(result)
+                    }
+                }
+            }
+        )+
+    };
+}
+
+impl_swap_bytes!(v16: u8x2, i8x2,);
+impl_swap_bytes!(v32: u8x4, i8x4, u16x2, i16x2,);
+// FIXME: 64-bit single element vector
+impl_swap_bytes!(
+    v64: u8x8,
+    i8x8,
+    u16x4,
+    i16x4,
+    u32x2,
+    i32x2, /* u64x1, i64x1, */
+);
+
+impl_swap_bytes!(
+    v128: u8x16,
+    i8x16,
+    u16x8,
+    i16x8,
+    u32x4,
+    i32x4,
+    u64x2,
+    i64x2,
+    u128x1,
+    i128x1,
+);
+impl_swap_bytes!(
+    v256: u8x32,
+    i8x32,
+    u16x16,
+    i16x16,
+    u32x8,
+    i32x8,
+    u64x4,
+    i64x4,
+    u128x2,
+    i128x2,
+);
+
+impl_swap_bytes!(
+    v512: u8x64,
+    i8x64,
+    u16x32,
+    i16x32,
+    u32x16,
+    i32x16,
+    u64x8,
+    i64x8,
+    u128x4,
+    i128x4,
+);
+
+cfg_if! {
+    if #[cfg(target_pointer_width = "8")] {
+        impl_swap_bytes!(v16: isizex2, usizex2,);
+        impl_swap_bytes!(v32: isizex4, usizex4,);
+        impl_swap_bytes!(v64: isizex8, usizex8,);
+    } else if #[cfg(target_pointer_width = "16")] {
+        impl_swap_bytes!(v32: isizex2, usizex2,);
+        impl_swap_bytes!(v64: isizex4, usizex4,);
+        impl_swap_bytes!(v128: isizex8, usizex8,);
+    } else if #[cfg(target_pointer_width = "32")] {
+        impl_swap_bytes!(v64: isizex2, usizex2,);
+        impl_swap_bytes!(v128: isizex4, usizex4,);
+        impl_swap_bytes!(v256: isizex8, usizex8,);
+    } else if #[cfg(target_pointer_width = "64")] {
+        impl_swap_bytes!(v128: isizex2, usizex2,);
+        impl_swap_bytes!(v256: isizex4, usizex4,);
+        impl_swap_bytes!(v512: isizex8, usizex8,);
+    } else {
+        compile_error!("unsupported target_pointer_width");
+    }
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/codegen/v128.rs.html b/src/packed_simd/codegen/v128.rs.html new file mode 100644 index 000000000..5ce1b0c8d --- /dev/null +++ b/src/packed_simd/codegen/v128.rs.html @@ -0,0 +1,95 @@ +v128.rs.html -- source
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+43
+44
+45
+46
+
+//! Internal 128-bit wide vector types
+
+use crate::masks::*;
+
+#[rustfmt::skip]
+impl_simd_array!(
+    [i8; 16]: i8x16 |
+    i8, i8, i8, i8,
+    i8, i8, i8, i8,
+    i8, i8, i8, i8,
+    i8, i8, i8, i8
+);
+#[rustfmt::skip]
+impl_simd_array!(
+    [u8; 16]: u8x16 |
+    u8, u8, u8, u8,
+    u8, u8, u8, u8,
+    u8, u8, u8, u8,
+    u8, u8, u8, u8
+);
+#[rustfmt::skip]
+impl_simd_array!(
+    [m8; 16]: m8x16 |
+    i8, i8, i8, i8,
+    i8, i8, i8, i8,
+    i8, i8, i8, i8,
+    i8, i8, i8, i8
+);
+
+impl_simd_array!([i16; 8]: i16x8 | i16, i16, i16, i16, i16, i16, i16, i16);
+impl_simd_array!([u16; 8]: u16x8 | u16, u16, u16, u16, u16, u16, u16, u16);
+impl_simd_array!([m16; 8]: m16x8 | i16, i16, i16, i16, i16, i16, i16, i16);
+
+impl_simd_array!([i32; 4]: i32x4 | i32, i32, i32, i32);
+impl_simd_array!([u32; 4]: u32x4 | u32, u32, u32, u32);
+impl_simd_array!([f32; 4]: f32x4 | f32, f32, f32, f32);
+impl_simd_array!([m32; 4]: m32x4 | i32, i32, i32, i32);
+
+impl_simd_array!([i64; 2]: i64x2 | i64, i64);
+impl_simd_array!([u64; 2]: u64x2 | u64, u64);
+impl_simd_array!([f64; 2]: f64x2 | f64, f64);
+impl_simd_array!([m64; 2]: m64x2 | i64, i64);
+
+impl_simd_array!([i128; 1]: i128x1 | i128);
+impl_simd_array!([u128; 1]: u128x1 | u128);
+impl_simd_array!([m128; 1]: m128x1 | i128);
+
+
\ No newline at end of file diff --git a/src/packed_simd/codegen/v16.rs.html b/src/packed_simd/codegen/v16.rs.html new file mode 100644 index 000000000..ca4afc878 --- /dev/null +++ b/src/packed_simd/codegen/v16.rs.html @@ -0,0 +1,17 @@ +v16.rs.html -- source
1
+2
+3
+4
+5
+6
+7
+
+//! Internal 16-bit wide vector types
+
+use crate::masks::*;
+
+impl_simd_array!([i8; 2]: i8x2 | i8, i8);
+impl_simd_array!([u8; 2]: u8x2 | u8, u8);
+impl_simd_array!([m8; 2]: m8x2 | i8, i8);
+
+
\ No newline at end of file diff --git a/src/packed_simd/codegen/v256.rs.html b/src/packed_simd/codegen/v256.rs.html new file mode 100644 index 000000000..7bdbe067b --- /dev/null +++ b/src/packed_simd/codegen/v256.rs.html @@ -0,0 +1,159 @@ +v256.rs.html -- source
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+68
+69
+70
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+72
+73
+74
+75
+76
+77
+78
+
+//! Internal 256-bit wide vector types
+
+use crate::masks::*;
+
+#[rustfmt::skip]
+impl_simd_array!(
+    [i8; 32]: i8x32 |
+    i8, i8, i8, i8,
+    i8, i8, i8, i8,
+    i8, i8, i8, i8,
+    i8, i8, i8, i8,
+    i8, i8, i8, i8,
+    i8, i8, i8, i8,
+    i8, i8, i8, i8,
+    i8, i8, i8, i8
+);
+#[rustfmt::skip]
+impl_simd_array!(
+    [u8; 32]: u8x32 |
+    u8, u8, u8, u8,
+    u8, u8, u8, u8,
+    u8, u8, u8, u8,
+    u8, u8, u8, u8,
+    u8, u8, u8, u8,
+    u8, u8, u8, u8,
+    u8, u8, u8, u8,
+    u8, u8, u8, u8
+);
+#[rustfmt::skip]
+impl_simd_array!(
+    [m8; 32]: m8x32 |
+    i8, i8, i8, i8,
+    i8, i8, i8, i8,
+    i8, i8, i8, i8,
+    i8, i8, i8, i8,
+    i8, i8, i8, i8,
+    i8, i8, i8, i8,
+    i8, i8, i8, i8,
+    i8, i8, i8, i8
+);
+#[rustfmt::skip]
+impl_simd_array!(
+    [i16; 16]: i16x16 |
+    i16, i16, i16, i16,
+    i16, i16, i16, i16,
+    i16, i16, i16, i16,
+    i16, i16, i16, i16
+);
+#[rustfmt::skip]
+impl_simd_array!(
+    [u16; 16]: u16x16 |
+    u16, u16, u16, u16,
+    u16, u16, u16, u16,
+    u16, u16, u16, u16,
+    u16, u16, u16, u16
+);
+#[rustfmt::skip]
+impl_simd_array!(
+    [m16; 16]: m16x16 |
+    i16, i16, i16, i16,
+    i16, i16, i16, i16,
+    i16, i16, i16, i16,
+    i16, i16, i16, i16
+);
+
+impl_simd_array!([i32; 8]: i32x8 | i32, i32, i32, i32, i32, i32, i32, i32);
+impl_simd_array!([u32; 8]: u32x8 | u32, u32, u32, u32, u32, u32, u32, u32);
+impl_simd_array!([f32; 8]: f32x8 | f32, f32, f32, f32, f32, f32, f32, f32);
+impl_simd_array!([m32; 8]: m32x8 | i32, i32, i32, i32, i32, i32, i32, i32);
+
+impl_simd_array!([i64; 4]: i64x4 | i64, i64, i64, i64);
+impl_simd_array!([u64; 4]: u64x4 | u64, u64, u64, u64);
+impl_simd_array!([f64; 4]: f64x4 | f64, f64, f64, f64);
+impl_simd_array!([m64; 4]: m64x4 | i64, i64, i64, i64);
+
+impl_simd_array!([i128; 2]: i128x2 | i128, i128);
+impl_simd_array!([u128; 2]: u128x2 | u128, u128);
+impl_simd_array!([m128; 2]: m128x2 | i128, i128);
+
+
\ No newline at end of file diff --git a/src/packed_simd/codegen/v32.rs.html b/src/packed_simd/codegen/v32.rs.html new file mode 100644 index 000000000..1724083bf --- /dev/null +++ b/src/packed_simd/codegen/v32.rs.html @@ -0,0 +1,25 @@ +v32.rs.html -- source
 1
+ 2
+ 3
+ 4
+ 5
+ 6
+ 7
+ 8
+ 9
+10
+11
+
+//! Internal 32-bit wide vector types
+
+use crate::masks::*;
+
+impl_simd_array!([i8; 4]: i8x4 | i8, i8, i8, i8);
+impl_simd_array!([u8; 4]: u8x4 | u8, u8, u8, u8);
+impl_simd_array!([m8; 4]: m8x4 | i8, i8, i8, i8);
+
+impl_simd_array!([i16; 2]: i16x2 | i16, i16);
+impl_simd_array!([u16; 2]: u16x2 | u16, u16);
+impl_simd_array!([m16; 2]: m16x2 | i16, i16);
+
+
\ No newline at end of file diff --git a/src/packed_simd/codegen/v512.rs.html b/src/packed_simd/codegen/v512.rs.html new file mode 100644 index 000000000..4d06fae14 --- /dev/null +++ b/src/packed_simd/codegen/v512.rs.html @@ -0,0 +1,293 @@ +v512.rs.html -- source
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+  2
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+  5
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+ 43
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+ 45
+ 46
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+ 48
+ 49
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+ 59
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+ 70
+ 71
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+ 73
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+ 86
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+ 89
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+ 98
+ 99
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+120
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+129
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+132
+133
+134
+135
+136
+137
+138
+139
+140
+141
+142
+143
+144
+145
+
+//! Internal 512-bit wide vector types
+
+use crate::masks::*;
+
+#[rustfmt::skip]
+impl_simd_array!(
+    [i8; 64]: i8x64 |
+    i8, i8, i8, i8,
+    i8, i8, i8, i8,
+    i8, i8, i8, i8,
+    i8, i8, i8, i8,
+    i8, i8, i8, i8,
+    i8, i8, i8, i8,
+    i8, i8, i8, i8,
+    i8, i8, i8, i8,
+
+    i8, i8, i8, i8,
+    i8, i8, i8, i8,
+    i8, i8, i8, i8,
+    i8, i8, i8, i8,
+    i8, i8, i8, i8,
+    i8, i8, i8, i8,
+    i8, i8, i8, i8,
+    i8, i8, i8, i8
+);
+#[rustfmt::skip]
+impl_simd_array!(
+    [u8; 64]: u8x64 |
+    u8, u8, u8, u8,
+    u8, u8, u8, u8,
+    u8, u8, u8, u8,
+    u8, u8, u8, u8,
+    u8, u8, u8, u8,
+    u8, u8, u8, u8,
+    u8, u8, u8, u8,
+    u8, u8, u8, u8,
+
+    u8, u8, u8, u8,
+    u8, u8, u8, u8,
+    u8, u8, u8, u8,
+    u8, u8, u8, u8,
+    u8, u8, u8, u8,
+    u8, u8, u8, u8,
+    u8, u8, u8, u8,
+    u8, u8, u8, u8
+);
+#[rustfmt::skip]
+impl_simd_array!(
+    [m8; 64]: m8x64 |
+    i8, i8, i8, i8,
+    i8, i8, i8, i8,
+    i8, i8, i8, i8,
+    i8, i8, i8, i8,
+    i8, i8, i8, i8,
+    i8, i8, i8, i8,
+    i8, i8, i8, i8,
+    i8, i8, i8, i8,
+
+    i8, i8, i8, i8,
+    i8, i8, i8, i8,
+    i8, i8, i8, i8,
+    i8, i8, i8, i8,
+    i8, i8, i8, i8,
+    i8, i8, i8, i8,
+    i8, i8, i8, i8,
+    i8, i8, i8, i8
+);
+#[rustfmt::skip]
+impl_simd_array!(
+    [i16; 32]: i16x32 |
+    i16, i16, i16, i16,
+    i16, i16, i16, i16,
+    i16, i16, i16, i16,
+    i16, i16, i16, i16,
+    i16, i16, i16, i16,
+    i16, i16, i16, i16,
+    i16, i16, i16, i16,
+    i16, i16, i16, i16
+);
+#[rustfmt::skip]
+impl_simd_array!(
+    [u16; 32]: u16x32 |
+    u16, u16, u16, u16,
+    u16, u16, u16, u16,
+    u16, u16, u16, u16,
+    u16, u16, u16, u16,
+    u16, u16, u16, u16,
+    u16, u16, u16, u16,
+    u16, u16, u16, u16,
+    u16, u16, u16, u16
+);
+#[rustfmt::skip]
+impl_simd_array!(
+    [m16; 32]: m16x32 |
+    i16, i16, i16, i16,
+    i16, i16, i16, i16,
+    i16, i16, i16, i16,
+    i16, i16, i16, i16,
+    i16, i16, i16, i16,
+    i16, i16, i16, i16,
+    i16, i16, i16, i16,
+    i16, i16, i16, i16
+);
+
+#[rustfmt::skip]
+impl_simd_array!(
+    [i32; 16]: i32x16 |
+    i32, i32, i32, i32,
+    i32, i32, i32, i32,
+    i32, i32, i32, i32,
+    i32, i32, i32, i32
+);
+#[rustfmt::skip]
+impl_simd_array!(
+    [u32; 16]: u32x16 |
+    u32, u32, u32, u32,
+    u32, u32, u32, u32,
+    u32, u32, u32, u32,
+    u32, u32, u32, u32
+);
+#[rustfmt::skip]
+impl_simd_array!(
+    [f32; 16]: f32x16 |
+    f32, f32, f32, f32,
+    f32, f32, f32, f32,
+    f32, f32, f32, f32,
+    f32, f32, f32, f32
+);
+#[rustfmt::skip]
+impl_simd_array!(
+    [m32; 16]: m32x16 |
+    i32, i32, i32, i32,
+    i32, i32, i32, i32,
+    i32, i32, i32, i32,
+    i32, i32, i32, i32
+);
+
+impl_simd_array!([i64; 8]: i64x8 | i64, i64, i64, i64, i64, i64, i64, i64);
+impl_simd_array!([u64; 8]: u64x8 | u64, u64, u64, u64, u64, u64, u64, u64);
+impl_simd_array!([f64; 8]: f64x8 | f64, f64, f64, f64, f64, f64, f64, f64);
+impl_simd_array!([m64; 8]: m64x8 | i64, i64, i64, i64, i64, i64, i64, i64);
+
+impl_simd_array!([i128; 4]: i128x4 | i128, i128, i128, i128);
+impl_simd_array!([u128; 4]: u128x4 | u128, u128, u128, u128);
+impl_simd_array!([m128; 4]: m128x4 | i128, i128, i128, i128);
+
+
\ No newline at end of file diff --git a/src/packed_simd/codegen/v64.rs.html b/src/packed_simd/codegen/v64.rs.html new file mode 100644 index 000000000..f196f6723 --- /dev/null +++ b/src/packed_simd/codegen/v64.rs.html @@ -0,0 +1,45 @@ +v64.rs.html -- source
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+//! Internal 64-bit wide vector types
+
+use crate::masks::*;
+
+impl_simd_array!([i8; 8]: i8x8 | i8, i8, i8, i8, i8, i8, i8, i8);
+impl_simd_array!([u8; 8]: u8x8 | u8, u8, u8, u8, u8, u8, u8, u8);
+impl_simd_array!([m8; 8]: m8x8 | i8, i8, i8, i8, i8, i8, i8, i8);
+
+impl_simd_array!([i16; 4]: i16x4 | i16, i16, i16, i16);
+impl_simd_array!([u16; 4]: u16x4 | u16, u16, u16, u16);
+impl_simd_array!([m16; 4]: m16x4 | i16, i16, i16, i16);
+
+impl_simd_array!([i32; 2]: i32x2 | i32, i32);
+impl_simd_array!([u32; 2]: u32x2 | u32, u32);
+impl_simd_array!([f32; 2]: f32x2 | f32, f32);
+impl_simd_array!([m32; 2]: m32x2 | i32, i32);
+
+impl_simd_array!([i64; 1]: i64x1 | i64);
+impl_simd_array!([u64; 1]: u64x1 | u64);
+impl_simd_array!([f64; 1]: f64x1 | f64);
+impl_simd_array!([m64; 1]: m64x1 | i64);
+
+
\ No newline at end of file diff --git a/src/packed_simd/codegen/vPtr.rs.html b/src/packed_simd/codegen/vPtr.rs.html new file mode 100644 index 000000000..0b36e6ae2 --- /dev/null +++ b/src/packed_simd/codegen/vPtr.rs.html @@ -0,0 +1,73 @@ +vPtr.rs.html -- source
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+
+//! Pointer vector types
+
+macro_rules! impl_simd_ptr {
+    ([$ptr_ty:ty; $elem_count:expr]: $tuple_id:ident | $ty:ident
+     | $($tys:ty),*) => {
+        #[derive(Copy, Clone)]
+        #[repr(simd)]
+        pub struct $tuple_id<$ty>($(crate $tys),*);
+        //^^^^^^^ leaked through SimdArray
+
+        impl<$ty> crate::sealed::Seal for [$ptr_ty; $elem_count] {}
+        impl<$ty> crate::sealed::SimdArray for [$ptr_ty; $elem_count] {
+            type Tuple = $tuple_id<$ptr_ty>;
+            type T = $ptr_ty;
+            const N: usize = $elem_count;
+            type NT = [u32; $elem_count];
+        }
+
+        impl<$ty> crate::sealed::Seal for $tuple_id<$ptr_ty> {}
+        impl<$ty> crate::sealed::Simd for $tuple_id<$ptr_ty> {
+            type Element = $ptr_ty;
+            const LANES: usize = $elem_count;
+            type LanesType = [u32; $elem_count];
+        }
+
+    }
+}
+
+impl_simd_ptr!([*const T; 2]: cptrx2 | T | T, T);
+impl_simd_ptr!([*const T; 4]: cptrx4 | T | T, T, T, T);
+impl_simd_ptr!([*const T; 8]: cptrx8 | T | T, T, T, T, T, T, T, T);
+
+impl_simd_ptr!([*mut T; 2]: mptrx2 | T | T, T);
+impl_simd_ptr!([*mut T; 4]: mptrx4 | T | T, T, T, T);
+impl_simd_ptr!([*mut T; 8]: mptrx8 | T | T, T, T, T, T, T, T, T);
+
+
\ No newline at end of file diff --git a/src/packed_simd/codegen/vSize.rs.html b/src/packed_simd/codegen/vSize.rs.html new file mode 100644 index 000000000..8d578a82c --- /dev/null +++ b/src/packed_simd/codegen/vSize.rs.html @@ -0,0 +1,89 @@ +vSize.rs.html -- source
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+
+//! Vector types with pointer-sized elements
+
+use crate::codegen::pointer_sized_int::{isize_, usize_};
+use crate::masks::*;
+
+impl_simd_array!([isize; 2]: isizex2 | isize_, isize_);
+impl_simd_array!([usize; 2]: usizex2 | usize_, usize_);
+impl_simd_array!([msize; 2]: msizex2 | isize_, isize_);
+
+impl_simd_array!([isize; 4]: isizex4 | isize_, isize_, isize_, isize_);
+impl_simd_array!([usize; 4]: usizex4 | usize_, usize_, usize_, usize_);
+impl_simd_array!([msize; 4]: msizex4 | isize_, isize_, isize_, isize_);
+
+impl_simd_array!(
+    [isize; 8]: isizex8 | isize_,
+    isize_,
+    isize_,
+    isize_,
+    isize_,
+    isize_,
+    isize_,
+    isize_
+);
+impl_simd_array!(
+    [usize; 8]: usizex8 | usize_,
+    usize_,
+    usize_,
+    usize_,
+    usize_,
+    usize_,
+    usize_,
+    usize_
+);
+impl_simd_array!(
+    [msize; 8]: msizex8 | isize_,
+    isize_,
+    isize_,
+    isize_,
+    isize_,
+    isize_,
+    isize_,
+    isize_
+);
+
+
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+
+//! # Portable packed SIMD vectors
+//!
+//! This crate is proposed for stabilization as `std::packed_simd` in [RFC2366:
+//! `std::simd`](https://github.com/rust-lang/rfcs/pull/2366) .
+//!
+//! The examples available in the
+//! [`examples/`](https://github.com/rust-lang-nursery/packed_simd/tree/master/examples)
+//! sub-directory of the crate showcase how to use the library in practice.
+//!
+//! ## Table of contents
+//!
+//! - [Introduction](#introduction)
+//! - [Vector types](#vector-types)
+//! - [Conditional operations](#conditional-operations)
+//! - [Conversions](#conversions)
+//! - [Performance
+//!   guide](https://rust-lang-nursery.github.io/packed_simd/perf-guide/)
+//!
+//! ## Introduction
+//!
+//! This crate exports [`Simd<[T; N]>`][`Simd`]: a packed vector of `N`
+//! elements of type `T` as well as many type aliases for this type: for
+//! example, [`f32x4`], which is just an alias for `Simd<[f32; 4]>`.
+//!
+//! The operations on packed vectors are, by default, "vertical", that is, they
+//! are applied to each vector lane in isolation of the others:
+//!
+//! ```
+//! # use packed_simd::*;
+//! let a = i32x4::new(1, 2, 3, 4);
+//! let b = i32x4::new(5, 6, 7, 8);
+//! assert_eq!(a + b, i32x4::new(6, 8, 10, 12));
+//! ```
+//!
+//! Many "horizontal" operations are also provided:
+//!
+//! ```
+//! # use packed_simd::*;
+//! # let a = i32x4::new(1, 2, 3, 4);
+//! assert_eq!(a.wrapping_sum(), 10);
+//! ```
+//!
+//! In virtually all architectures vertical operations are fast, while
+//! horizontal operations are, by comparison, much slower. That is, the
+//! most portably-efficient way of performing a reduction over a slice
+//! is to collect the results into a vector using vertical operations,
+//! and performing a single horizontal operation at the end:
+//!
+//! ```
+//! # use packed_simd::*;
+//! fn reduce(x: &[i32]) -> i32 {
+//!     assert!(x.len() % 4 == 0);
+//!     let mut sum = i32x4::splat(0); // [0, 0, 0, 0]
+//!     for i in (0..x.len()).step_by(4) {
+//!         sum += i32x4::from_slice_unaligned(&x[i..]);
+//!     }
+//!     sum.wrapping_sum()
+//! }
+//!
+//! let x = [0, 1, 2, 3, 4, 5, 6, 7];
+//! assert_eq!(reduce(&x), 28);
+//! ```
+//!
+//! ## Vector types
+//!
+//! The vector type aliases are named according to the following scheme:
+//!
+//! > `{element_type}x{number_of_lanes} == Simd<[element_type;
+//! number_of_lanes]>`
+//!
+//! where the following element types are supported:
+//!
+//! * `i{element_width}`: signed integer
+//! * `u{element_width}`: unsigned integer
+//! * `f{element_width}`: float
+//! * `m{element_width}`: mask (see below)
+//! * `*{const,mut} T`: `const` and `mut` pointers
+//!
+//! ## Basic operations
+//!
+//! ```
+//! # use packed_simd::*;
+//! // Sets all elements to `0`:
+//! let a = i32x4::splat(0);
+//!
+//! // Reads a vector from a slice:
+//! let mut arr = [0, 0, 0, 1, 2, 3, 4, 5];
+//! let b = i32x4::from_slice_unaligned(&arr);
+//!
+//! // Reads the 4-th element of a vector:
+//! assert_eq!(b.extract(3), 1);
+//!
+//! // Returns a new vector where the 4-th element is replaced with `1`:
+//! let a = a.replace(3, 1);
+//! assert_eq!(a, b);
+//!
+//! // Writes a vector to a slice:
+//! let a = a.replace(2, 1);
+//! a.write_to_slice_unaligned(&mut arr[4..]);
+//! assert_eq!(arr, [0, 0, 0, 1, 0, 0, 1, 1]);
+//! ```
+//!
+//! ## Conditional operations
+//!
+//! One often needs to perform an operation on some lanes of the vector. Vector
+//! masks, like `m32x4`, allow selecting on which vector lanes an operation is
+//! to be performed:
+//!
+//! ```
+//! # use packed_simd::*;
+//! let a = i32x4::new(1, 1, 2, 2);
+//!
+//! // Add `1` to the first two lanes of the vector.
+//! let m = m16x4::new(true, true, false, false);
+//! let a = m.select(a + 1, a);
+//! assert_eq!(a, i32x4::splat(2));
+//! ```
+//!
+//! The elements of a vector mask are either `true` or `false`. Here `true`
+//! means that a lane is "selected", while `false` means that a lane is not
+//! selected.
+//!
+//! All vector masks implement a `mask.select(a: T, b: T) -> T` method that
+//! works on all vectors that have the same number of lanes as the mask. The
+//! resulting vector contains the elements of `a` for those lanes for which the
+//! mask is `true`, and the elements of `b` otherwise.
+//!
+//! The example constructs a mask with the first two lanes set to `true` and
+//! the last two lanes set to `false`. This selects the first two lanes of `a +
+//! 1` and the last two lanes of `a`, producing a vector where the first two
+//! lanes have been incremented by `1`.
+//!
+//! > note: mask `select` can be used on vector types that have the same number
+//! > of lanes as the mask. The example shows this by using [`m16x4`] instead
+//! > of [`m32x4`]. It is _typically_ more performant to use a mask element
+//! > width equal to the element width of the vectors being operated upon.
+//! > This is, however, not true for 512-bit wide vectors when targetting
+//! > AVX-512, where the most efficient masks use only 1-bit per element.
+//!
+//! All vertical comparison operations returns masks:
+//!
+//! ```
+//! # use packed_simd::*;
+//! let a = i32x4::new(1, 1, 3, 3);
+//! let b = i32x4::new(2, 2, 0, 0);
+//!
+//! // ge: >= (Greater Eequal; see also lt, le, gt, eq, ne).
+//! let m = a.ge(i32x4::splat(2));
+//!
+//! if m.any() {
+//!     // all / any / none allow coherent control flow
+//!     let d = m.select(a, b);
+//!     assert_eq!(d, i32x4::new(2, 2, 3, 3));
+//! }
+//! ```
+//!
+//! ## Conversions
+//!
+//! * **lossless widening conversions**: [`From`]/[`Into`] are implemented for
+//!   vectors with the same number of lanes when the conversion is value
+//! preserving   (same as in `std`).
+//!
+//! * **safe bitwise conversions**: The cargo feature `into_bits` provides the
+//!   `IntoBits/FromBits` traits (`x.into_bits()`). These perform safe bitwise
+//!   `transmute`s when all bit patterns of the source type are valid bit
+//!   patterns of the target type and are also implemented for the
+//!   architecture-specific vector types of `std::arch`. For example, `let x:
+//!   u8x8 = m8x8::splat(true).into_bits();` is provided because all `m8x8` bit
+//!   patterns are valid `u8x8` bit patterns. However, the opposite is not
+//! true,   not all `u8x8` bit patterns are valid `m8x8` bit-patterns, so this
+//!   operation cannot be peformed safely using `x.into_bits()`; one needs to
+//!   use `unsafe { crate::mem::transmute(x) }` for that, making sure that the
+//!   value in the `u8x8` is a valid bit-pattern of `m8x8`.
+//!
+//! * **numeric casts** (`as`): are peformed using [`FromCast`]/[`Cast`]
+//! (`x.cast()`), just like `as`:
+//!
+//!   * casting integer vectors whose lane types have the same size (e.g.
+//! `i32xN`     -> `u32xN`) is a **no-op**,
+//!
+//!   * casting from a larger integer to a smaller integer (e.g. `u32xN` ->
+//! `u8xN`)     will **truncate**,
+//!
+//!   * casting from a smaller integer to a larger integer     (e.g. `u8xN` ->
+//!     `u32xN`) will:
+//!        * **zero-extend** if the source is unsigned, or
+//!        * **sign-extend** if the source is signed,
+//!
+//!   * casting from a float to an integer will **round the float towards
+//! zero**,
+//!
+//!   * casting from an integer to float will produce the floating point
+//!     representation of the integer, **rounding to nearest, ties to even**,
+//!
+//!   * casting from an `f32` to an `f64` is perfect and lossless,
+//!
+//!   * casting from an `f64` to an `f32` **rounds to nearest, ties to even**.
+//!
+//!   Numeric casts are not very "precise": sometimes lossy, sometimes value
+//!   preserving, etc.
+
+#![feature(
+    repr_simd,
+    const_fn,
+    platform_intrinsics,
+    stdsimd,
+    aarch64_target_feature,
+    arm_target_feature,
+    link_llvm_intrinsics,
+    core_intrinsics,
+    stmt_expr_attributes,
+    mmx_target_feature,
+    crate_visibility_modifier,
+    custom_inner_attributes
+)]
+#![allow(non_camel_case_types, non_snake_case,
+         clippy::cast_possible_truncation,
+         clippy::cast_lossless,
+         clippy::cast_possible_wrap,
+         clippy::cast_precision_loss,
+         // This lint is currently broken for generic code
+         // See https://github.com/rust-lang/rust-clippy/issues/3410
+         clippy::use_self
+)]
+#![cfg_attr(test, feature(hashmap_internals))]
+#![deny(rust_2018_idioms, clippy::missing_inline_in_public_items)]
+#![no_std]
+
+use cfg_if::cfg_if;
+
+cfg_if! {
+    if #[cfg(feature = "core_arch")] {
+        #[allow(unused_imports)]
+        use core_arch as arch;
+    } else {
+        #[allow(unused_imports)]
+        use core::arch;
+    }
+}
+
+#[cfg(all(target_arch = "wasm32", test))]
+use wasm_bindgen_test::*;
+
+#[allow(unused_imports)]
+use core::{
+    /* arch (handled above), */ cmp, f32, f64, fmt, hash, hint, i128,
+    i16, i32, i64, i8, intrinsics, isize, iter, marker, mem, ops, ptr, slice,
+    u128, u16, u32, u64, u8, usize,
+};
+
+#[macro_use]
+mod testing;
+#[macro_use]
+mod api;
+mod codegen;
+mod sealed;
+
+pub use crate::sealed::{Simd as SimdVector, Shuffle, SimdArray, Mask};
+
+/// Packed SIMD vector type.
+///
+/// # Examples
+///
+/// ```
+/// # use packed_simd::Simd;
+/// let v = Simd::<[i32; 4]>::new(0, 1, 2, 3);
+/// assert_eq!(v.extract(2), 2);
+/// ```
+#[repr(transparent)]
+#[derive(Copy, Clone)]
+pub struct Simd<A: sealed::SimdArray>(
+    // FIXME: this type should be private,
+    // but it currently must be public for the
+    // `shuffle!` macro to work: it needs to
+    // access the internal `repr(simd)` type
+    // to call the shuffle intrinsics.
+    #[doc(hidden)] pub <A as sealed::SimdArray>::Tuple,
+);
+
+impl<A: sealed::SimdArray> sealed::Seal for Simd<A> {}
+
+/// Wrapper over `T` implementing a lexicoraphical order via the `PartialOrd`
+/// and/or `Ord` traits.
+#[repr(transparent)]
+#[derive(Copy, Clone, Debug)]
+#[allow(clippy::missing_inline_in_public_items)]
+pub struct LexicographicallyOrdered<T>(T);
+
+mod masks;
+pub use self::masks::*;
+
+mod v16;
+pub use self::v16::*;
+
+mod v32;
+pub use self::v32::*;
+
+mod v64;
+pub use self::v64::*;
+
+mod v128;
+pub use self::v128::*;
+
+mod v256;
+pub use self::v256::*;
+
+mod v512;
+pub use self::v512::*;
+
+mod vSize;
+pub use self::vSize::*;
+
+mod vPtr;
+pub use self::vPtr::*;
+
+pub use self::api::cast::*;
+
+#[cfg(feature = "into_bits")]
+pub use self::api::into_bits::*;
+
+// Re-export the shuffle intrinsics required by the `shuffle!` macro.
+#[doc(hidden)]
+pub use self::codegen::llvm::{
+    __shuffle_vector16, __shuffle_vector2, __shuffle_vector32,
+    __shuffle_vector4, __shuffle_vector64, __shuffle_vector8,
+};
+
+crate mod llvm {
+    crate use crate::codegen::llvm::*;
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/masks.rs.html b/src/packed_simd/masks.rs.html new file mode 100644 index 000000000..edec6a6be --- /dev/null +++ b/src/packed_simd/masks.rs.html @@ -0,0 +1,261 @@ +masks.rs.html -- source
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+
+//! Mask types
+
+macro_rules! impl_mask_ty {
+    ($id:ident : $elem_ty:ident | #[$doc:meta]) => {
+        #[$doc]
+        #[derive(Copy, Clone)]
+        pub struct $id($elem_ty);
+
+        impl crate::sealed::Seal for $id {}
+        impl crate::sealed::Mask for $id {
+            fn test(&self) -> bool {
+                $id::test(self)
+            }
+        }
+
+        impl $id {
+            /// Instantiate a mask with `value`
+            #[inline]
+            pub fn new(x: bool) -> Self {
+                if x {
+                    $id(!0)
+                } else {
+                    $id(0)
+                }
+            }
+            /// Test if the mask is set
+            #[inline]
+            pub fn test(&self) -> bool {
+                self.0 != 0
+            }
+        }
+
+        impl Default for $id {
+            #[inline]
+            fn default() -> Self {
+                $id(0)
+            }
+        }
+
+        #[allow(clippy::partialeq_ne_impl)]
+        impl PartialEq<$id> for $id {
+            #[inline]
+            fn eq(&self, other: &Self) -> bool {
+                self.0 == other.0
+            }
+            #[inline]
+            fn ne(&self, other: &Self) -> bool {
+                self.0 != other.0
+            }
+        }
+
+        impl Eq for $id {}
+
+        impl PartialOrd<$id> for $id {
+            #[inline]
+            fn partial_cmp(
+                &self, other: &Self,
+            ) -> Option<crate::cmp::Ordering> {
+                use crate::cmp::Ordering;
+                if self == other {
+                    Some(Ordering::Equal)
+                } else if self.0 > other.0 {
+                    // Note:
+                    //  * false = 0_i
+                    //  * true == !0_i == -1_i
+                    Some(Ordering::Less)
+                } else {
+                    Some(Ordering::Greater)
+                }
+            }
+
+            #[inline]
+            fn lt(&self, other: &Self) -> bool {
+                self.0 > other.0
+            }
+            #[inline]
+            fn gt(&self, other: &Self) -> bool {
+                self.0 < other.0
+            }
+            #[inline]
+            fn le(&self, other: &Self) -> bool {
+                self.0 >= other.0
+            }
+            #[inline]
+            fn ge(&self, other: &Self) -> bool {
+                self.0 <= other.0
+            }
+        }
+
+        impl Ord for $id {
+            #[inline]
+            fn cmp(&self, other: &Self) -> crate::cmp::Ordering {
+                match self.partial_cmp(other) {
+                    Some(x) => x,
+                    None => unsafe { crate::hint::unreachable_unchecked() },
+                }
+            }
+        }
+
+        impl crate::hash::Hash for $id {
+            #[inline]
+            fn hash<H: crate::hash::Hasher>(&self, state: &mut H) {
+                (self.0 != 0).hash(state);
+            }
+        }
+
+        impl crate::fmt::Debug for $id {
+            #[inline]
+            fn fmt(
+                &self, fmtter: &mut crate::fmt::Formatter<'_>,
+            ) -> Result<(), crate::fmt::Error> {
+                write!(fmtter, "{}({})", stringify!($id), self.0 != 0)
+            }
+        }
+    };
+}
+
+impl_mask_ty!(m8: i8 | /// 8-bit wide mask.
+);
+impl_mask_ty!(m16: i16 | /// 16-bit wide mask.
+);
+impl_mask_ty!(m32: i32 | /// 32-bit wide mask.
+);
+impl_mask_ty!(m64: i64 | /// 64-bit wide mask.
+);
+impl_mask_ty!(m128: i128 | /// 128-bit wide mask.
+);
+impl_mask_ty!(msize: isize | /// isize-wide mask.
+);
+
+
\ No newline at end of file diff --git a/src/packed_simd/sealed.rs.html b/src/packed_simd/sealed.rs.html new file mode 100644 index 000000000..20e0fb2f7 --- /dev/null +++ b/src/packed_simd/sealed.rs.html @@ -0,0 +1,87 @@ +sealed.rs.html -- source
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+//! Sealed traits
+
+/// A sealed trait, this is logically private to the crate
+/// and will prevent implementations from outside the crate
+pub trait Seal<T = ()> {}
+
+/// Trait implemented by arrays that can be SIMD types.
+pub trait SimdArray: Seal {
+    /// The type of the #[repr(simd)] type.
+    type Tuple: Copy + Clone;
+    /// The element type of the vector.
+    type T;
+    /// The number of elements in the array.
+    const N: usize;
+    /// The type: `[u32; Self::N]`.
+    type NT;
+}
+
+/// This traits is used to constraint the arguments
+/// and result type of the portable shuffles.
+#[doc(hidden)]
+pub trait Shuffle<Lanes>: Seal<Lanes> {
+    // Lanes is a `[u32; N]` where `N` is the number of vector lanes
+
+    /// The result type of the shuffle.
+    type Output;
+}
+
+/// This trait is implemented by all SIMD vector types.
+pub trait Simd: Seal {
+    /// Element type of the SIMD vector
+    type Element;
+    /// The number of elements in the SIMD vector.
+    const LANES: usize;
+    /// The type: `[u32; Self::N]`.
+    type LanesType;
+}
+
+/// This trait is implemented by all mask types
+pub trait Mask: Seal {
+    fn test(&self) -> bool;
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/testing.rs.html b/src/packed_simd/testing.rs.html new file mode 100644 index 000000000..be396e787 --- /dev/null +++ b/src/packed_simd/testing.rs.html @@ -0,0 +1,19 @@ +testing.rs.html -- source
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+//! Testing macros and other utilities.
+
+#[macro_use]
+mod macros;
+
+#[cfg(test)]
+#[macro_use]
+crate mod utils;
+
+
\ No newline at end of file diff --git a/src/packed_simd/testing/macros.rs.html b/src/packed_simd/testing/macros.rs.html new file mode 100644 index 000000000..452e741d3 --- /dev/null +++ b/src/packed_simd/testing/macros.rs.html @@ -0,0 +1,91 @@ +macros.rs.html -- source
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+//! Testing macros
+
+macro_rules! test_if {
+    ($cfg_tt:tt: $it:item) => {
+        #[cfg(any(
+                            // Test everything if:
+                            //
+                            // * tests are enabled,
+                            // * no features about exclusively testing
+                            //   specific vector classes are enabled
+                            all(test, not(any(
+                                test_v16,
+                                test_v32,
+                                test_v64,
+                                test_v128,
+                                test_v256,
+                                test_v512,
+                                test_none,  // disables all tests
+                            ))),
+                            // Test if:
+                            //
+                            // * tests are enabled
+                            // * a particular cfg token tree returns true
+                            all(test, $cfg_tt),
+                        ))]
+        $it
+    };
+}
+
+#[cfg(test)]
+#[allow(unused)]
+macro_rules! ref_ {
+    ($anything:tt) => {
+        &$anything
+    };
+}
+
+#[cfg(test)]
+#[allow(unused)]
+macro_rules! ref_mut_ {
+    ($anything:tt) => {
+        &mut $anything
+    };
+}
+
+
\ No newline at end of file diff --git a/src/packed_simd/v128.rs.html b/src/packed_simd/v128.rs.html new file mode 100644 index 000000000..492dc771a --- /dev/null +++ b/src/packed_simd/v128.rs.html @@ -0,0 +1,163 @@ +v128.rs.html -- source
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+
+//! 128-bit wide vector types
+#![rustfmt::skip]
+
+use crate::*;
+
+impl_i!([i8; 16]: i8x16, m8x16 | i8, u16 | test_v128 |
+        x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15 |
+        From: |
+        /// A 128-bit vector with 16 `i8` lanes.
+);
+impl_u!([u8; 16]: u8x16, m8x16 | u8, u16 | test_v128 |
+        x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15 |
+        From: |
+        /// A 128-bit vector with 16 `u8` lanes.
+);
+impl_m!([m8; 16]: m8x16 | i8, u16 | test_v128 |
+        x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15 |
+        From: m16x16 |
+        /// A 128-bit vector mask with 16 `m8` lanes.
+);
+
+impl_i!([i16; 8]: i16x8, m16x8 | i16, u8 | test_v128 | x0, x1, x2, x3, x4, x5, x6, x7 |
+        From: i8x8, u8x8 |
+        /// A 128-bit vector with 8 `i16` lanes.
+);
+impl_u!([u16; 8]: u16x8, m16x8 | u16, u8 | test_v128 | x0, x1, x2, x3, x4, x5, x6, x7 |
+        From: u8x8 |
+        /// A 128-bit vector with 8 `u16` lanes.
+);
+impl_m!([m16; 8]: m16x8 | i16, u8 | test_v128 | x0, x1, x2, x3, x4, x5, x6, x7 |
+        From: m8x8, m32x8 |
+        /// A 128-bit vector mask with 8 `m16` lanes.
+);
+
+impl_i!([i32; 4]: i32x4, m32x4 | i32, u8 | test_v128 | x0, x1, x2, x3 |
+        From: i8x4, u8x4, i16x4, u16x4  |
+        /// A 128-bit vector with 4 `i32` lanes.
+);
+impl_u!([u32; 4]: u32x4, m32x4 | u32, u8 | test_v128 | x0, x1, x2, x3 |
+        From: u8x4, u16x4 |
+        /// A 128-bit vector with 4 `u32` lanes.
+);
+impl_f!([f32; 4]: f32x4, m32x4 | f32 | test_v128 | x0, x1, x2, x3 |
+        From: i8x4, u8x4, i16x4, u16x4 |
+        /// A 128-bit vector with 4 `f32` lanes.
+);
+impl_m!([m32; 4]: m32x4 | i32, u8 | test_v128 | x0, x1, x2, x3 |
+        From: m8x4, m16x4, m64x4 |
+        /// A 128-bit vector mask with 4 `m32` lanes.
+);
+
+impl_i!([i64; 2]: i64x2, m64x2 | i64, u8 | test_v128 | x0, x1 |
+        From: i8x2, u8x2, i16x2, u16x2, i32x2, u32x2 |
+        /// A 128-bit vector with 2 `i64` lanes.
+);
+impl_u!([u64; 2]: u64x2, m64x2 | u64, u8 | test_v128 | x0, x1 |
+        From: u8x2, u16x2, u32x2 |
+        /// A 128-bit vector with 2 `u64` lanes.
+);
+impl_f!([f64; 2]: f64x2, m64x2 | f64 | test_v128 | x0, x1 |
+        From: i8x2, u8x2, i16x2, u16x2, i32x2, u32x2, f32x2 |
+        /// A 128-bit vector with 2 `f64` lanes.
+);
+impl_m!([m64; 2]: m64x2 | i64, u8 | test_v128 | x0, x1 |
+        From: m8x2, m16x2, m32x2, m128x2 |
+        /// A 128-bit vector mask with 2 `m64` lanes.
+);
+
+impl_i!([i128; 1]: i128x1, m128x1 | i128, u8 | test_v128 | x0 |
+        From: /*i8x1, u8x1, i16x1, u16x1, i32x1, u32x1, i64x1, u64x1 */ | // FIXME: unary small vector types
+        /// A 128-bit vector with 1 `i128` lane.
+);
+impl_u!([u128; 1]: u128x1, m128x1 | u128, u8 | test_v128 | x0 |
+        From: /*u8x1, u16x1, u32x1, u64x1 */ | // FIXME: unary small vector types
+        /// A 128-bit vector with 1 `u128` lane.
+);
+impl_m!([m128; 1]: m128x1 | i128, u8 | test_v128 | x0 |
+        From: /*m8x1, m16x1, m32x1, m64x1 */ | // FIXME: unary small vector types
+        /// A 128-bit vector mask with 1 `m128` lane.
+);
+
+
\ No newline at end of file diff --git a/src/packed_simd/v16.rs.html b/src/packed_simd/v16.rs.html new file mode 100644 index 000000000..f681d9920 --- /dev/null +++ b/src/packed_simd/v16.rs.html @@ -0,0 +1,35 @@ +v16.rs.html -- source
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+//! 16-bit wide vector types
+
+use crate::*;
+
+impl_i!([i8; 2]: i8x2, m8x2 | i8, u8 | test_v16 | x0, x1 |
+        From: |
+        /// A 16-bit vector with 2 `i8` lanes.
+);
+impl_u!([u8; 2]: u8x2, m8x2 | u8, u8 | test_v16 | x0, x1 |
+        From: |
+        /// A 16-bit vector with 2 `u8` lanes.
+);
+impl_m!([m8; 2]: m8x2 | i8, u8 | test_v16 | x0, x1 |
+        From: m16x2, m32x2, m64x2, m128x2 |
+        /// A 16-bit vector mask with 2 `m8` lanes.
+);
+
+
\ No newline at end of file diff --git a/src/packed_simd/v256.rs.html b/src/packed_simd/v256.rs.html new file mode 100644 index 000000000..23dc81f67 --- /dev/null +++ b/src/packed_simd/v256.rs.html @@ -0,0 +1,175 @@ +v256.rs.html -- source
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+//! 256-bit wide vector types
+#![rustfmt::skip]
+
+use crate::*;
+
+impl_i!([i8; 32]: i8x32, m8x32 | i8, u32 | test_v256 |
+        x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15,
+        x16, x17, x18, x19, x20, x21, x22, x23, x24, x25, x26, x27, x28, x29, x30, x31 |
+        From: |
+        /// A 256-bit vector with 32 `i8` lanes.
+);
+impl_u!([u8; 32]: u8x32, m8x32 | u8, u32 | test_v256 |
+        x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15,
+        x16, x17, x18, x19, x20, x21, x22, x23, x24, x25, x26, x27, x28, x29, x30, x31 |
+        From: |
+        /// A 256-bit vector with 32 `u8` lanes.
+);
+impl_m!([m8; 32]: m8x32 | i8, u32 | test_v256 |
+        x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15,
+        x16, x17, x18, x19, x20, x21, x22, x23, x24, x25, x26, x27, x28, x29, x30, x31 |
+        From:  |
+        /// A 256-bit vector mask with 32 `m8` lanes.
+);
+
+impl_i!([i16; 16]: i16x16, m16x16 | i16, u16 | test_v256 |
+        x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15 |
+        From: i8x16, u8x16 |
+        /// A 256-bit vector with 16 `i16` lanes.
+);
+impl_u!([u16; 16]: u16x16, m16x16 | u16, u16 | test_v256 |
+        x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15 |
+        From: u8x16 |
+        /// A 256-bit vector with 16 `u16` lanes.
+);
+impl_m!([m16; 16]: m16x16 | i16, u16 | test_v256 |
+        x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15 |
+        From: m8x16 |
+        /// A 256-bit vector mask with 16 `m16` lanes.
+);
+
+impl_i!([i32; 8]: i32x8, m32x8 | i32, u8 | test_v256 | x0, x1, x2, x3, x4, x5, x6, x7  |
+        From: i8x8, u8x8, i16x8, u16x8 |
+        /// A 256-bit vector with 8 `i32` lanes.
+);
+impl_u!([u32; 8]: u32x8, m32x8 | u32, u8 | test_v256 | x0, x1, x2, x3, x4, x5, x6, x7 |
+        From: u8x8, u16x8 |
+        /// A 256-bit vector with 8 `u32` lanes.
+);
+impl_f!([f32; 8]: f32x8, m32x8 | f32 | test_v256 | x0, x1, x2, x3, x4, x5, x6, x7 |
+        From: i8x8, u8x8, i16x8, u16x8 |
+        /// A 256-bit vector with 8 `f32` lanes.
+);
+impl_m!([m32; 8]: m32x8 | i32, u8 | test_v256 | x0, x1, x2, x3, x4, x5, x6, x7 |
+        From: m8x8, m16x8 |
+        /// A 256-bit vector mask with 8 `m32` lanes.
+);
+
+impl_i!([i64; 4]: i64x4, m64x4 | i64, u8 | test_v256 | x0, x1, x2, x3 |
+        From: i8x4, u8x4, i16x4, u16x4, i32x4, u32x4 |
+        /// A 256-bit vector with 4 `i64` lanes.
+);
+impl_u!([u64; 4]: u64x4, m64x4 | u64, u8 | test_v256 | x0, x1, x2, x3 |
+        From: u8x4, u16x4, u32x4 |
+        /// A 256-bit vector with 4 `u64` lanes.
+);
+impl_f!([f64; 4]: f64x4, m64x4 | f64 | test_v256 | x0, x1, x2, x3 |
+        From: i8x4, u8x4, i16x4, u16x4, i32x4, u32x4, f32x4 |
+        /// A 256-bit vector with 4 `f64` lanes.
+);
+impl_m!([m64; 4]: m64x4 | i64, u8 | test_v256 | x0, x1, x2, x3 |
+        From: m8x4, m16x4, m32x4 |
+        /// A 256-bit vector mask with 4 `m64` lanes.
+);
+
+impl_i!([i128; 2]: i128x2, m128x2 | i128, u8 | test_v256 | x0, x1 |
+        From: i8x2, u8x2, i16x2, u16x2, i32x2, u32x2, i64x2, u64x2 |
+        /// A 256-bit vector with 2 `i128` lanes.
+);
+impl_u!([u128; 2]: u128x2, m128x2 | u128, u8 | test_v256 | x0, x1 |
+        From: u8x2, u16x2, u32x2, u64x2 |
+        /// A 256-bit vector with 2 `u128` lanes.
+);
+impl_m!([m128; 2]: m128x2 | i128, u8 | test_v256 | x0, x1 |
+        From: m8x2, m16x2, m32x2, m64x2 |
+        /// A 256-bit vector mask with 2 `m128` lanes.
+);
+
+
\ No newline at end of file diff --git a/src/packed_simd/v32.rs.html b/src/packed_simd/v32.rs.html new file mode 100644 index 000000000..21025bc31 --- /dev/null +++ b/src/packed_simd/v32.rs.html @@ -0,0 +1,61 @@ +v32.rs.html -- source
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+//! 32-bit wide vector types
+
+use crate::*;
+
+impl_i!([i8; 4]: i8x4, m8x4 | i8, u8 | test_v32 | x0, x1, x2, x3 |
+        From: |
+        /// A 32-bit vector with 4 `i8` lanes.
+);
+impl_u!([u8; 4]: u8x4, m8x4 | u8, u8 | test_v32 | x0, x1, x2, x3 |
+        From: |
+        /// A 32-bit vector with 4 `u8` lanes.
+);
+impl_m!([m8; 4]: m8x4 | i8, u8 | test_v32 | x0, x1, x2, x3 |
+        From: m16x4, m32x4, m64x4 |
+        /// A 32-bit vector mask with 4 `m8` lanes.
+);
+
+impl_i!([i16; 2]: i16x2, m16x2 | i16, u8 | test_v32 | x0, x1 |
+        From: i8x2, u8x2 |
+        /// A 32-bit vector with 2 `i16` lanes.
+);
+impl_u!([u16; 2]: u16x2, m16x2 | u16, u8 | test_v32 | x0, x1 |
+        From: u8x2 |
+        /// A 32-bit vector with 2 `u16` lanes.
+);
+impl_m!([m16; 2]: m16x2 | i16, u8 | test_v32 | x0, x1 |
+        From: m8x2, m32x2, m64x2, m128x2 |
+        /// A 32-bit vector mask with 2 `m16` lanes.
+);
+
+
\ No newline at end of file diff --git a/src/packed_simd/v512.rs.html b/src/packed_simd/v512.rs.html new file mode 100644 index 000000000..3df374904 --- /dev/null +++ b/src/packed_simd/v512.rs.html @@ -0,0 +1,201 @@ +v512.rs.html -- source
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+//! 512-bit wide vector types
+#![rustfmt::skip]
+
+use crate::*;
+
+impl_i!([i8; 64]: i8x64, m8x64 | i8, u64 | test_v512 |
+        x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15,
+        x16, x17, x18, x19, x20, x21, x22, x23, x24, x25, x26, x27, x28, x29, x30, x31,
+        x32, x33, x34, x35, x36, x37, x38, x39, x40, x41, x42, x43, x44, x45, x46, x47,
+        x48, x49, x50, x51, x52, x53, x54, x55, x56, x57, x58, x59, x60, x61, x62, x63 |
+        From: |
+        /// A 512-bit vector with 64 `i8` lanes.
+);
+impl_u!([u8; 64]: u8x64, m8x64 | u8, u64 | test_v512 |
+        x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15,
+        x16, x17, x18, x19, x20, x21, x22, x23, x24, x25, x26, x27, x28, x29, x30, x31,
+        x32, x33, x34, x35, x36, x37, x38, x39, x40, x41, x42, x43, x44, x45, x46, x47,
+        x48, x49, x50, x51, x52, x53, x54, x55, x56, x57, x58, x59, x60, x61, x62, x63 |
+        From: |
+        /// A 512-bit vector with 64 `u8` lanes.
+);
+impl_m!([m8; 64]: m8x64 | i8, u64 | test_v512 |
+        x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15,
+        x16, x17, x18, x19, x20, x21, x22, x23, x24, x25, x26, x27, x28, x29, x30, x31,
+        x32, x33, x34, x35, x36, x37, x38, x39, x40, x41, x42, x43, x44, x45, x46, x47,
+        x48, x49, x50, x51, x52, x53, x54, x55, x56, x57, x58, x59, x60, x61, x62, x63 |
+        From:  |
+        /// A 512-bit vector mask with 64 `m8` lanes.
+);
+
+impl_i!([i16; 32]: i16x32, m16x32 | i16, u32 | test_v512 |
+        x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15,
+        x16, x17, x18, x19, x20, x21, x22, x23, x24, x25, x26, x27, x28, x29, x30, x31 |
+        From: i8x32, u8x32 |
+        /// A 512-bit vector with 32 `i16` lanes.
+);
+impl_u!([u16; 32]: u16x32, m16x32 | u16, u32 | test_v512 |
+        x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15,
+        x16, x17, x18, x19, x20, x21, x22, x23, x24, x25, x26, x27, x28, x29, x30, x31 |
+        From: u8x32 |
+        /// A 512-bit vector with 32 `u16` lanes.
+);
+impl_m!([m16; 32]: m16x32 | i16, u32 | test_v512 |
+        x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15,
+        x16, x17, x18, x19, x20, x21, x22, x23, x24, x25, x26, x27, x28, x29, x30, x31 |
+        From: m8x32 |
+        /// A 512-bit vector mask with 32 `m16` lanes.
+);
+
+impl_i!([i32; 16]: i32x16, m32x16 | i32, u16 | test_v512 |
+        x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15 |
+        From: i8x16, u8x16, i16x16, u16x16 |
+        /// A 512-bit vector with 16 `i32` lanes.
+);
+impl_u!([u32; 16]: u32x16, m32x16 | u32, u16 | test_v512 |
+        x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15 |
+        From: u8x16, u16x16 |
+        /// A 512-bit vector with 16 `u32` lanes.
+);
+impl_f!([f32; 16]: f32x16, m32x16 | f32 | test_v512 |
+        x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15 |
+        From: i8x16, u8x16, i16x16, u16x16 |
+        /// A 512-bit vector with 16 `f32` lanes.
+);
+impl_m!([m32; 16]: m32x16 | i32, u16 | test_v512 |
+        x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15 |
+        From: m8x16, m16x16 |
+        /// A 512-bit vector mask with 16 `m32` lanes.
+);
+
+impl_i!([i64; 8]: i64x8, m64x8 | i64, u8 | test_v512 | x0, x1, x2, x3, x4, x5, x6, x7 |
+        From: i8x8, u8x8, i16x8, u16x8, i32x8, u32x8 |
+        /// A 512-bit vector with 8 `i64` lanes.
+);
+impl_u!([u64; 8]: u64x8, m64x8 | u64, u8 | test_v512 | x0, x1, x2, x3, x4, x5, x6, x7 |
+        From: u8x8, u16x8, u32x8 |
+        /// A 512-bit vector with 8 `u64` lanes.
+);
+impl_f!([f64; 8]: f64x8, m64x8 | f64 | test_v512 | x0, x1, x2, x3, x4, x5, x6, x7 |
+        From: i8x8, u8x8, i16x8, u16x8, i32x8, u32x8, f32x8 |
+        /// A 512-bit vector with 8 `f64` lanes.
+);
+impl_m!([m64; 8]: m64x8 | i64, u8 | test_v512 | x0, x1, x2, x3, x4, x5, x6, x7 |
+        From: m8x8, m16x8, m32x8 |
+        /// A 512-bit vector mask with 8 `m64` lanes.
+);
+
+impl_i!([i128; 4]: i128x4, m128x4 | i128, u8 | test_v512 | x0, x1, x2, x3 |
+        From: i8x4, u8x4, i16x4, u16x4, i32x4, u32x4, i64x4, u64x4 |
+        /// A 512-bit vector with 4 `i128` lanes.
+);
+impl_u!([u128; 4]: u128x4, m128x4 | u128, u8 | test_v512 | x0, x1, x2, x3 |
+        From: u8x4, u16x4, u32x4, u64x4 |
+        /// A 512-bit vector with 4 `u128` lanes.
+);
+impl_m!([m128; 4]: m128x4 | i128, u8 | test_v512 | x0, x1, x2, x3 |
+        From: m8x4, m16x4, m32x4, m64x4 |
+        /// A 512-bit vector mask with 4 `m128` lanes.
+);
+
+
\ No newline at end of file diff --git a/src/packed_simd/v64.rs.html b/src/packed_simd/v64.rs.html new file mode 100644 index 000000000..8832f96d0 --- /dev/null +++ b/src/packed_simd/v64.rs.html @@ -0,0 +1,135 @@ +v64.rs.html -- source
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+//! 64-bit wide vector types
+#![rustfmt::skip]
+
+use super::*;
+
+impl_i!([i8; 8]: i8x8, m8x8 | i8, u8 | test_v64 | x0, x1, x2, x3, x4, x5, x6, x7 |
+        From: |
+        /// A 64-bit vector with 8 `i8` lanes.
+);
+impl_u!([u8; 8]: u8x8, m8x8 | u8, u8 | test_v64 | x0, x1, x2, x3, x4, x5, x6, x7 |
+        From: |
+        /// A 64-bit vector with 8 `u8` lanes.
+);
+impl_m!([m8; 8]: m8x8 | i8, u8 | test_v64 | x0, x1, x2, x3, x4, x5, x6, x7 |
+        From: m16x8, m32x8 |
+        /// A 64-bit vector mask with 8 `m8` lanes.
+);
+
+impl_i!([i16; 4]: i16x4, m16x4 | i16, u8 | test_v64 | x0, x1, x2, x3 |
+        From: i8x4, u8x4 |
+        /// A 64-bit vector with 4 `i16` lanes.
+);
+impl_u!([u16; 4]: u16x4, m16x4 | u16, u8 | test_v64 | x0, x1, x2, x3 |
+        From: u8x4 |
+        /// A 64-bit vector with 4 `u16` lanes.
+);
+impl_m!([m16; 4]: m16x4 | i16, u8 | test_v64 | x0, x1, x2, x3 |
+        From: m8x4, m32x4, m64x4 |
+        /// A 64-bit vector mask with 4 `m16` lanes.
+);
+
+impl_i!([i32; 2]: i32x2, m32x2 | i32, u8 | test_v64 | x0, x1 |
+        From: i8x2, u8x2, i16x2, u16x2 |
+        /// A 64-bit vector with 2 `i32` lanes.
+);
+impl_u!([u32; 2]: u32x2, m32x2 | u32, u8 | test_v64 | x0, x1 |
+        From: u8x2, u16x2 |
+        /// A 64-bit vector with 2 `u32` lanes.
+);
+impl_m!([m32; 2]: m32x2 | i32, u8 | test_v64 | x0, x1 |
+        From: m8x2, m16x2, m64x2, m128x2 |
+        /// A 64-bit vector mask with 2 `m32` lanes.
+);
+impl_f!([f32; 2]: f32x2, m32x2 | f32 | test_v64 | x0, x1 |
+        From: i8x2, u8x2, i16x2, u16x2 |
+        /// A 64-bit vector with 2 `f32` lanes.
+);
+
+/*
+impl_i!([i64; 1]: i64x1, m64x1 | i64, u8 | test_v64 | x0 |
+        From: /*i8x1, u8x1, i16x1, u16x1, i32x1, u32x1*/ |  // FIXME: primitive to vector conversion
+        /// A 64-bit vector with 1 `i64` lanes.
+);
+impl_u!([u64; 1]: u64x1, m64x1 | u64, u8 | test_v64 | x0 |
+        From: /*u8x1, u16x1, u32x1*/ | // FIXME: primitive to vector conversion
+        /// A 64-bit vector with 1 `u64` lanes.
+);
+impl_m!([m64; 1]: m64x1 | i64, u8 | test_v64 | x0 |
+        From: /*m8x1, m16x1, m32x1, */ m128x1 | // FIXME: unary small vector types
+        /// A 64-bit vector mask with 1 `m64` lanes.
+);
+impl_f!([f64; 1]: f64x1, m64x1 | f64 | test_v64 | x0 |
+        From: /*i8x1, u8x1, i16x1, u16x1, i32x1, u32x1, f32x1*/ | // FIXME: unary small vector types
+        /// A 64-bit vector with 1 `f64` lanes.
+);
+*/
+
+
\ No newline at end of file diff --git a/src/packed_simd/vPtr.rs.html b/src/packed_simd/vPtr.rs.html new file mode 100644 index 000000000..f2a82e228 --- /dev/null +++ b/src/packed_simd/vPtr.rs.html @@ -0,0 +1,71 @@ +vPtr.rs.html -- source
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+//! Vectors of pointers
+#![rustfmt::skip]
+
+use crate::*;
+
+impl_const_p!(
+    [*const T; 2]: cptrx2, msizex2, usizex2, isizex2 | test_v128 | x0, x1 | From: |
+    /// A vector with 2 `*const T` lanes
+);
+
+impl_mut_p!(
+    [*mut T; 2]: mptrx2, msizex2, usizex2, isizex2 | test_v128 | x0, x1 | From: |
+    /// A vector with 2 `*mut T` lanes
+);
+
+impl_const_p!(
+    [*const T; 4]: cptrx4, msizex4, usizex4, isizex4 | test_v256 | x0, x1, x2, x3 | From: |
+    /// A vector with 4 `*const T` lanes
+);
+
+impl_mut_p!(
+    [*mut T; 4]: mptrx4, msizex4, usizex4, isizex4 | test_v256 | x0, x1, x2, x3 | From: |
+    /// A vector with 4 `*mut T` lanes
+);
+
+impl_const_p!(
+    [*const T; 8]: cptrx8, msizex8, usizex8, isizex8 | test_v512 | x0, x1, x2, x3, x4, x5, x6, x7 | From: |
+    /// A vector with 8 `*const T` lanes
+);
+
+impl_mut_p!(
+    [*mut T; 8]: mptrx8, msizex8, usizex8, isizex8 | test_v512 | x0, x1, x2, x3, x4, x5, x6, x7 | From: |
+    /// A vector with 8 `*mut T` lanes
+);
+
+
\ No newline at end of file diff --git a/src/packed_simd/vSize.rs.html b/src/packed_simd/vSize.rs.html new file mode 100644 index 000000000..f1fe797f8 --- /dev/null +++ b/src/packed_simd/vSize.rs.html @@ -0,0 +1,109 @@ +vSize.rs.html -- source
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+//! Vectors with pointer-sized elements
+
+use crate::codegen::pointer_sized_int::{isize_, usize_};
+use crate::*;
+
+impl_i!([isize; 2]: isizex2, msizex2 | isize_, u8 | test_v128 |
+        x0, x1|
+        From: |
+        /// A vector with 2 `isize` lanes.
+);
+
+impl_u!([usize; 2]: usizex2, msizex2 | usize_, u8 | test_v128 |
+        x0, x1|
+        From: |
+        /// A vector with 2 `usize` lanes.
+);
+impl_m!([msize; 2]: msizex2 | isize_, u8 | test_v128 |
+        x0, x1 |
+        From: |
+        /// A vector mask with 2 `msize` lanes.
+);
+
+impl_i!([isize; 4]: isizex4, msizex4 | isize_, u8 | test_v256 |
+        x0, x1, x2, x3 |
+        From: |
+        /// A vector with 4 `isize` lanes.
+);
+impl_u!([usize; 4]: usizex4, msizex4 | usize_, u8 | test_v256 |
+        x0, x1, x2, x3|
+        From: |
+        /// A vector with 4 `usize` lanes.
+);
+impl_m!([msize; 4]: msizex4 | isize_, u8 | test_v256 |
+        x0, x1, x2, x3 |
+        From: |
+        /// A vector mask with 4 `msize` lanes.
+);
+
+impl_i!([isize; 8]: isizex8, msizex8 | isize_, u8 | test_v512 |
+        x0, x1, x2, x3, x4, x5, x6, x7 |
+        From: |
+        /// A vector with 4 `isize` lanes.
+);
+impl_u!([usize; 8]: usizex8, msizex8 | usize_, u8 | test_v512 |
+        x0, x1, x2, x3, x4, x5, x6, x7 |
+        From: |
+        /// A vector with 8 `usize` lanes.
+);
+impl_m!([msize; 8]: msizex8 | isize_, u8 | test_v512 |
+        x0, x1, x2, x3, x4, x5, x6, x7 |
+        From: |
+        /// A vector mask with 8 `msize` lanes.
+);
+
+
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