From d30f210e5d20e3a03a015f95324021fb711cfc58 Mon Sep 17 00:00:00 2001 From: DianQK Date: Thu, 21 Sep 2023 12:29:20 +0800 Subject: [PATCH 1/3] Increasing the SIMD size improves the vectorization possibilities Change the simd-wide-sum.rs to pass the LLVM main branching test. --- tests/codegen/simd/simd-wide-sum.rs | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/tests/codegen/simd/simd-wide-sum.rs b/tests/codegen/simd/simd-wide-sum.rs index 3116f9597bcdb..3dc0a3ec03979 100644 --- a/tests/codegen/simd/simd-wide-sum.rs +++ b/tests/codegen/simd/simd-wide-sum.rs @@ -11,14 +11,14 @@ #![feature(portable_simd)] use std::simd::{Simd, SimdUint}; -const N: usize = 8; +const N: usize = 16; #[no_mangle] // CHECK-LABEL: @wider_reduce_simd pub fn wider_reduce_simd(x: Simd) -> u16 { - // CHECK: zext <8 x i8> - // CHECK-SAME: to <8 x i16> - // CHECK: call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> + // CHECK: zext <16 x i8> + // CHECK-SAME: to <16 x i16> + // CHECK: call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> let x: Simd = x.cast(); x.reduce_sum() } @@ -26,9 +26,9 @@ pub fn wider_reduce_simd(x: Simd) -> u16 { #[no_mangle] // CHECK-LABEL: @wider_reduce_loop pub fn wider_reduce_loop(x: Simd) -> u16 { - // CHECK: zext <8 x i8> - // CHECK-SAME: to <8 x i16> - // CHECK: call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> + // CHECK: zext <16 x i8> + // CHECK-SAME: to <16 x i16> + // CHECK: call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> let mut sum = 0_u16; for i in 0..N { sum += u16::from(x[i]); @@ -39,9 +39,9 @@ pub fn wider_reduce_loop(x: Simd) -> u16 { #[no_mangle] // CHECK-LABEL: @wider_reduce_iter pub fn wider_reduce_iter(x: Simd) -> u16 { - // CHECK: zext <8 x i8> - // CHECK-SAME: to <8 x i16> - // CHECK: call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> + // CHECK: zext <16 x i8> + // CHECK-SAME: to <16 x i16> + // CHECK: call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> x.as_array().iter().copied().map(u16::from).sum() } @@ -52,8 +52,8 @@ pub fn wider_reduce_iter(x: Simd) -> u16 { #[no_mangle] // CHECK-LABEL: @wider_reduce_into_iter pub fn wider_reduce_into_iter(x: Simd) -> u16 { - // CHECK: zext <8 x i8> - // CHECK-SAME: to <8 x i16> - // CHECK: call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> + // CHECK: zext <16 x i8> + // CHECK-SAME: to <16 x i16> + // CHECK: call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> x.to_array().into_iter().map(u16::from).sum() } From 910674f1c4d1551ffab71627e1821cf8298f3669 Mon Sep 17 00:00:00 2001 From: DianQK Date: Sun, 24 Sep 2023 09:46:04 +0800 Subject: [PATCH 2/3] Only check for successful vectorization on wider_reduce_into_iter Different vectorization results are due to different LLVM versions. --- tests/codegen/simd/simd-wide-sum.rs | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/tests/codegen/simd/simd-wide-sum.rs b/tests/codegen/simd/simd-wide-sum.rs index 3dc0a3ec03979..f80e957641c1e 100644 --- a/tests/codegen/simd/simd-wide-sum.rs +++ b/tests/codegen/simd/simd-wide-sum.rs @@ -52,8 +52,6 @@ pub fn wider_reduce_iter(x: Simd) -> u16 { #[no_mangle] // CHECK-LABEL: @wider_reduce_into_iter pub fn wider_reduce_into_iter(x: Simd) -> u16 { - // CHECK: zext <16 x i8> - // CHECK-SAME: to <16 x i16> - // CHECK: call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> + // CHECK: call i16 @llvm.vector.reduce.add x.to_array().into_iter().map(u16::from).sum() } From e300847864faf93538354b418da0a1612efd36f4 Mon Sep 17 00:00:00 2001 From: scottmcm Date: Fri, 6 Oct 2023 07:05:09 +0000 Subject: [PATCH 3/3] Add a wishlist FIXME --- tests/codegen/simd/simd-wide-sum.rs | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/codegen/simd/simd-wide-sum.rs b/tests/codegen/simd/simd-wide-sum.rs index f80e957641c1e..6e7d3d9316a77 100644 --- a/tests/codegen/simd/simd-wide-sum.rs +++ b/tests/codegen/simd/simd-wide-sum.rs @@ -52,6 +52,8 @@ pub fn wider_reduce_iter(x: Simd) -> u16 { #[no_mangle] // CHECK-LABEL: @wider_reduce_into_iter pub fn wider_reduce_into_iter(x: Simd) -> u16 { + // FIXME: It would be nice if this was exactly the same as the above tests, + // but at the time of writing this comment, that didn't happen on LLVM main. // CHECK: call i16 @llvm.vector.reduce.add x.to_array().into_iter().map(u16::from).sum() }