Tracking issue for FastISel

[pcwalton]

We are currently falling off FastISel to the optimized SelectionDAG instruction selector in pretty much every function, hurting our codegen time in debug builds. You can verify this by running llc -O0 -fast-isel -fast-isel-abort. We have the following issues:

• FastISel does not support the invoke instruction. Proposed solution: Add this support to LLVM.
• FastISel does not support the switch instruction. Proposed solution: Add this support to LLVM.
• FastISel does not support comparisons on i1. Proposed solution: Add this support to LLVM.
• FastISel does not support the llvm.assume intrinsic. Proposed solution: Ignore that intrinsic in LLVM.
• FastISel does not allow first-class aggregates to be used, but we use first-class aggregates when loading and storing slices (e.g. store { i8*, i32 } %1, %2). Proposed solution: Stop doing this in trans.

[dotdash]

Did #26595 fix the FCA problem?

[cmr]

We should add a test for this in-tree as well. A good strategy is probably going to be adding those LLVM arguments with the -Z flag and building run-pass tests with it...

[cmr]

@pcwalton Are you working on an upstream patch or is that free to be taken?

[jonas-schievink]

Triage:

fn main() {
    Vec::<u8>::new();
}

(this creates an absurd amount of code)
With rustc --emit=llvm-ir -Zno-landing-pads test.rs

llc -O0 -fast-isel -fast-isel-abort 1 test.ll gives, using the llc shipped with the current Rust master:

FastISel missed terminator:   switch i1 %29, label %match_else [
    i1 true, label %match_case
    i1 false, label %match_case3
  ]
FastISel missed terminator:   ret { i8*, i64 } %20
FastISel missed terminator:   ret { i8*, i64 } %7
FastISel miss:   %24 = icmp eq i1 %23, true
LLVM ERROR: FastISel didn't select the entire block

And with the llc of LLVM 3.7.1:

FastISel missed terminator:   switch i1 %29, label %match_else [
    i1 true, label %match_case
    i1 false, label %match_case3
  ]
FastISel missed call:   call void @llvm.assume(i1 %25)
FastISel missed terminator:   ret { i8*, i64 } %20
FastISel missed terminator:   ret { i8*, i64 } %7
FastISel missed call:   call void @llvm.assume(i1 %28)
FastISel missed call:   call void @llvm.assume(i1 %20)
FastISel miss:   %24 = icmp eq i1 %23, true
LLVM ERROR: FastISel didn't select the entire block

(on x86_64 Arch Linux)

Rust's own llc is better probably because of rust-lang/llvm@e37f45f, but I'm not sure why the icmp still isn't selected. @pcwalton any thoughts?

The switch i1 is just silly, it could be replaced by a br i1, but that's #4353

[arielb1]

Yes trans is sure to load and store every value quite a bit of times.

[nox]

Cc @rust-lang/wg-compiler-performance.

[nox]

Note that FastISel is apparently intended to be replaced by GlobalISel in the future.

[rkruppe]

But also note that it will be many years until GlobalISel is production quality for all the architectures we care about.

[ishitatsuyuki]

I think the switch part is now handled in at least LLVM 5+, can anybody verify?

[steveklabnik]

Triage: i just tried @jonas-schievink 's example on godbolt's llvm-trunk, and got

LLVM ERROR: FastISel missed:   store { i64, i64 } %2, { i64, i64 }* %_5, align 8 (in function: _ZN49_$LT$alloc..raw_vec..RawVec$LT$T$C$$u20$A$GT$$GT$14dealloc_buffer17h67e71990b9ebed9cE)

Compiler returned: 1