diff --git a/compiler/rustc_codegen_llvm/src/back/write.rs b/compiler/rustc_codegen_llvm/src/back/write.rs
index fde7dd6ef7a85..df75541c787b9 100644
--- a/compiler/rustc_codegen_llvm/src/back/write.rs
+++ b/compiler/rustc_codegen_llvm/src/back/write.rs
@@ -1189,7 +1189,12 @@ fn embed_bitcode(
         llvm::set_linkage(llglobal, llvm::Linkage::PrivateLinkage);
     } else {
         // We need custom section flags, so emit module-level inline assembly.
-        let section_flags = if cgcx.is_pe_coff { "n" } else { "e" };
+        // The "n" flags is currently not supported on RISC-V
+        let mut section_flags = "";
+        if cgcx.target_arch != "riscv64"
+        {
+        	if cgcx.is_pe_coff { section_flags = "n" } else { section_flags = "e" };
+        }
         let asm = create_section_with_flags_asm(".llvmbc", section_flags, bitcode);
         llvm::append_module_inline_asm(llmod, &asm);
         let asm = create_section_with_flags_asm(".llvmcmd", section_flags, &[]);
diff --git a/compiler/rustc_codegen_ssa/src/back/metadata.rs b/compiler/rustc_codegen_ssa/src/back/metadata.rs
index 6dff79374f20f..fc8281ae121d6 100644
--- a/compiler/rustc_codegen_ssa/src/back/metadata.rs
+++ b/compiler/rustc_codegen_ssa/src/back/metadata.rs
@@ -20,7 +20,7 @@ use rustc_metadata::fs::METADATA_FILENAME;
 use rustc_middle::bug;
 use rustc_session::Session;
 use rustc_span::sym;
-use rustc_target::spec::{Abi, Os, RelocModel, Target, ef_avr_arch};
+use rustc_target::spec::{Abi, Arch, Os, RelocModel, Target, ef_avr_arch};
 use tracing::debug;
 
 use super::apple;
@@ -211,6 +211,12 @@ pub(crate) fn create_object_file(sess: &Session) -> Option<write::Object<'static
         return None;
     };
     let binary_format = sess.target.binary_format.to_object();
+    
+    if sess.target.arch == Arch::RiscV64 && binary_format == BinaryFormat::Coff {
+        // Return None to use the fallback mechanism in create_wrapper_file
+        // Use this fallback specifically for RISC-V 64 UEFI
+        return None;
+    }
 
     let mut file = write::Object::new(binary_format, architecture, endianness);
     file.set_sub_architecture(sub_architecture);
diff --git a/compiler/rustc_target/src/spec/mod.rs b/compiler/rustc_target/src/spec/mod.rs
index 62d3809c2c64e..fa86113393c5c 100644
--- a/compiler/rustc_target/src/spec/mod.rs
+++ b/compiler/rustc_target/src/spec/mod.rs
@@ -1708,6 +1708,7 @@ supported_targets! {
     ("x86_64-unknown-uefi", x86_64_unknown_uefi),
     ("i686-unknown-uefi", i686_unknown_uefi),
     ("aarch64-unknown-uefi", aarch64_unknown_uefi),
+    ("riscv64gc-unknown-uefi", riscv64gc_unknown_uefi),
 
     ("nvptx64-nvidia-cuda", nvptx64_nvidia_cuda),
 
diff --git a/compiler/rustc_target/src/spec/targets/riscv64gc_unknown_uefi.rs b/compiler/rustc_target/src/spec/targets/riscv64gc_unknown_uefi.rs
new file mode 100644
index 0000000000000..ff31d9ad8dbf0
--- /dev/null
+++ b/compiler/rustc_target/src/spec/targets/riscv64gc_unknown_uefi.rs
@@ -0,0 +1,31 @@
+use crate::spec::{
+	Arch, Target, TargetMetadata, base
+};
+
+pub(crate) fn target() -> Target {
+    // Get the base UEFI configuration
+    let mut base = base::uefi_msvc::opts();
+    
+    // Override with RISC-V specific settings
+    base.cpu = "generic-rv64".into();
+    base.features = "+m,+a,+f,+d,+c".into();
+    base.max_atomic_width = Some(64);
+    base.atomic_cas = true;
+    base.disable_redzone = true;
+    base.llvm_abiname = "lp64d".into();
+
+    Target {
+        llvm_target: "riscv64-unknown-windows".into(),
+        metadata: TargetMetadata {
+            description: Some("Bare RISC-V (RV64IMAFDC ISA) UEFI".into()),
+            tier: Some(3),
+            host_tools: Some(false),
+            std: None,
+        },
+        pointer_width: 64,
+        data_layout: "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128".into(),
+        arch: Arch::RiscV64,
+        
+        options: base,
+    }
+}
diff --git a/src/bootstrap/src/core/sanity.rs b/src/bootstrap/src/core/sanity.rs
index 78cd7ab2539fc..1f05e49b2965d 100644
--- a/src/bootstrap/src/core/sanity.rs
+++ b/src/bootstrap/src/core/sanity.rs
@@ -41,6 +41,7 @@ const STAGE0_MISSING_TARGETS: &[&str] = &[
     "sparc64-unknown-helenos",
     // just a dummy comment so the list doesn't get onelined
     "riscv64gc-unknown-redox",
+    "riscv64gc-unknown-uefi",
 ];
 
 /// Minimum version threshold for libstdc++ required when using prebuilt LLVM
diff --git a/src/doc/rustc/src/platform-support.md b/src/doc/rustc/src/platform-support.md
index 39bf9c7776401..e22c279e97bf0 100644
--- a/src/doc/rustc/src/platform-support.md
+++ b/src/doc/rustc/src/platform-support.md
@@ -397,6 +397,7 @@ target | std | host | notes
 [`riscv64gc-unknown-nuttx-elf`](platform-support/nuttx.md) | ✓ |  | RISC-V 64bit with NuttX
 [`riscv64gc-unknown-openbsd`](platform-support/openbsd.md) | ✓ | ✓ | OpenBSD/riscv64
 [`riscv64gc-unknown-redox`](platform-support/redox.md) | ✓ |  | RISC-V 64bit Redox OS
+[`riscv64gc-unknown-uefi`](platform-support/unknown-uefi.md) | ? | RISC-V 64bit UEFI
 [`riscv64imac-unknown-nuttx-elf`](platform-support/nuttx.md) | ✓ |  | RISC-V 64bit with NuttX
 [`riscv64a23-unknown-linux-gnu`](platform-support/riscv64a23-unknown-linux-gnu.md) | ✓ | ✓ | RISC-V Linux (kernel 6.8.0+, glibc 2.39)
 [`s390x-unknown-linux-musl`](platform-support/s390x-unknown-linux-musl.md) | ✓ |  | S390x Linux (kernel 3.2, musl 1.2.5)
diff --git a/src/doc/rustc/src/platform-support/unknown-uefi.md b/src/doc/rustc/src/platform-support/unknown-uefi.md
index e8989616b844b..0d3643a12df9e 100644
--- a/src/doc/rustc/src/platform-support/unknown-uefi.md
+++ b/src/doc/rustc/src/platform-support/unknown-uefi.md
@@ -1,21 +1,28 @@
 # `*-unknown-uefi`
 
-**Tier: 2**
-
 Unified Extensible Firmware Interface (UEFI) targets for application, driver,
 and core UEFI binaries.
 
+**Tier: 2**
+
 Available targets:
 
 - `aarch64-unknown-uefi`
 - `i686-unknown-uefi`
 - `x86_64-unknown-uefi`
 
+**Tier: 3**
+
+Available targets:
+
+- `riscv64gc-unknown-uefi`
+
 ## Target maintainers
 
 - [@dvdhrm](https://github.com/dvdhrm)
 - [@nicholasbishop](https://github.com/nicholasbishop)
 - (for `aarch64-unknown-uefi` only) [@rust-lang/arm-maintainers][arm_maintainers] ([rust@arm.com][arm_email])
+- (for `riscv64gc-unknown-uefi` only) [@gjbauer](https://github.com/gjbauer)
 
 [arm_maintainers]: https://github.com/rust-lang/team/blob/master/teams/arm-maintainers.toml
 [arm_email]: mailto:rust@arm.com