From 0f1a19a7f7bfcd9a91e581622bd64db1927cb423 Mon Sep 17 00:00:00 2001 From: Gabriel Bauer Date: Fri, 14 Nov 2025 22:43:41 -0500 Subject: [PATCH 01/11] target file --- .../spec/targets/riscv64gc_unknown_uefi.rs | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 compiler/rustc_target/src/spec/targets/riscv64gc_unknown_uefi.rs diff --git a/compiler/rustc_target/src/spec/targets/riscv64gc_unknown_uefi.rs b/compiler/rustc_target/src/spec/targets/riscv64gc_unknown_uefi.rs new file mode 100644 index 0000000000000..48a4f66738bf6 --- /dev/null +++ b/compiler/rustc_target/src/spec/targets/riscv64gc_unknown_uefi.rs @@ -0,0 +1,45 @@ +use crate::spec::{ + Arch, CodeModel, LinkerFlavor, Lld, PanicStrategy, RelocModel, + Target, TargetOptions, TargetMetadata, Os +}; + +pub(crate) fn target() -> Target { + Target { + data_layout: "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128".into(), + metadata: TargetMetadata { + description: Some("Bare RISC-V (RV64IMAFDC ISA) UEFI".into()), + tier: Some(3), + host_tools: Some(false), + std: Some(false), + }, + llvm_target: "riscv64gc-unknown-windows".into(), + pointer_width: 64, + arch: Arch::RiscV64, + + options: TargetOptions { + os: Os::Uefi, + vendor: "unknown".into(), + linker_flavor: LinkerFlavor::Msvc(Lld::No), + + // UEFI characteristics + executables: true, + is_like_windows: true, + panic_strategy: PanicStrategy::Abort, + relocation_model: RelocModel::Pic, + + // RISC-V features + cpu: "generic-rv64".into(), + features: "+m,+a,+f,+d,+c".into(), + + // These are the current correct field names: + is_like_aix: false, + is_like_android: false, + is_like_msvc: true, + + // Codegen options + code_model: Some(CodeModel::Medium), + disable_redzone: true, + ..Default::default() + }, + } +} From 4c1ba832ee46e12ab9d1c22d5a0804b2048fbf09 Mon Sep 17 00:00:00 2001 From: gjbauer Date: Fri, 14 Nov 2025 23:03:09 -0500 Subject: [PATCH 02/11] Add riscv64gc-unknown-uefi target specification --- compiler/rustc_target/src/spec/mod.rs | 1 + 1 file changed, 1 insertion(+) diff --git a/compiler/rustc_target/src/spec/mod.rs b/compiler/rustc_target/src/spec/mod.rs index 62d3809c2c64e..fa86113393c5c 100644 --- a/compiler/rustc_target/src/spec/mod.rs +++ b/compiler/rustc_target/src/spec/mod.rs @@ -1708,6 +1708,7 @@ supported_targets! { ("x86_64-unknown-uefi", x86_64_unknown_uefi), ("i686-unknown-uefi", i686_unknown_uefi), ("aarch64-unknown-uefi", aarch64_unknown_uefi), + ("riscv64gc-unknown-uefi", riscv64gc_unknown_uefi), ("nvptx64-nvidia-cuda", nvptx64_nvidia_cuda), From cc2e0aa0279618a3af971b58af1f2e1e695a94d1 Mon Sep 17 00:00:00 2001 From: gjbauer Date: Sun, 16 Nov 2025 11:54:17 -0500 Subject: [PATCH 03/11] Update UEFI targets with riscv64gc-unknown-uefi Added riscv64gc-unknown-uefi as a Tier 3 target. --- src/doc/rustc/src/platform-support/unknown-uefi.md | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/src/doc/rustc/src/platform-support/unknown-uefi.md b/src/doc/rustc/src/platform-support/unknown-uefi.md index e8989616b844b..0d3643a12df9e 100644 --- a/src/doc/rustc/src/platform-support/unknown-uefi.md +++ b/src/doc/rustc/src/platform-support/unknown-uefi.md @@ -1,21 +1,28 @@ # `*-unknown-uefi` -**Tier: 2** - Unified Extensible Firmware Interface (UEFI) targets for application, driver, and core UEFI binaries. +**Tier: 2** + Available targets: - `aarch64-unknown-uefi` - `i686-unknown-uefi` - `x86_64-unknown-uefi` +**Tier: 3** + +Available targets: + +- `riscv64gc-unknown-uefi` + ## Target maintainers - [@dvdhrm](https://github.com/dvdhrm) - [@nicholasbishop](https://github.com/nicholasbishop) - (for `aarch64-unknown-uefi` only) [@rust-lang/arm-maintainers][arm_maintainers] ([rust@arm.com][arm_email]) +- (for `riscv64gc-unknown-uefi` only) [@gjbauer](https://github.com/gjbauer) [arm_maintainers]: https://github.com/rust-lang/team/blob/master/teams/arm-maintainers.toml [arm_email]: mailto:rust@arm.com From 915715907ca16c48e81ca622e92081848841d058 Mon Sep 17 00:00:00 2001 From: gjbauer Date: Sun, 16 Nov 2025 11:57:00 -0500 Subject: [PATCH 04/11] Add support for RISC-V 64bit UEFI platform --- src/doc/rustc/src/platform-support.md | 1 + 1 file changed, 1 insertion(+) diff --git a/src/doc/rustc/src/platform-support.md b/src/doc/rustc/src/platform-support.md index 39bf9c7776401..e22c279e97bf0 100644 --- a/src/doc/rustc/src/platform-support.md +++ b/src/doc/rustc/src/platform-support.md @@ -397,6 +397,7 @@ target | std | host | notes [`riscv64gc-unknown-nuttx-elf`](platform-support/nuttx.md) | ✓ | | RISC-V 64bit with NuttX [`riscv64gc-unknown-openbsd`](platform-support/openbsd.md) | ✓ | ✓ | OpenBSD/riscv64 [`riscv64gc-unknown-redox`](platform-support/redox.md) | ✓ | | RISC-V 64bit Redox OS +[`riscv64gc-unknown-uefi`](platform-support/unknown-uefi.md) | ? | RISC-V 64bit UEFI [`riscv64imac-unknown-nuttx-elf`](platform-support/nuttx.md) | ✓ | | RISC-V 64bit with NuttX [`riscv64a23-unknown-linux-gnu`](platform-support/riscv64a23-unknown-linux-gnu.md) | ✓ | ✓ | RISC-V Linux (kernel 6.8.0+, glibc 2.39) [`s390x-unknown-linux-musl`](platform-support/s390x-unknown-linux-musl.md) | ✓ | | S390x Linux (kernel 3.2, musl 1.2.5) From 05b624fd99a386ddff39ef709f3bcf188f3a5917 Mon Sep 17 00:00:00 2001 From: gjbauer Date: Sun, 16 Nov 2025 12:23:18 -0500 Subject: [PATCH 05/11] Add riscv64gc-unknown-uefi to supported targets --- src/bootstrap/src/core/sanity.rs | 1 + 1 file changed, 1 insertion(+) diff --git a/src/bootstrap/src/core/sanity.rs b/src/bootstrap/src/core/sanity.rs index 78cd7ab2539fc..1f05e49b2965d 100644 --- a/src/bootstrap/src/core/sanity.rs +++ b/src/bootstrap/src/core/sanity.rs @@ -41,6 +41,7 @@ const STAGE0_MISSING_TARGETS: &[&str] = &[ "sparc64-unknown-helenos", // just a dummy comment so the list doesn't get onelined "riscv64gc-unknown-redox", + "riscv64gc-unknown-uefi", ]; /// Minimum version threshold for libstdc++ required when using prebuilt LLVM From 3aeb7eda5709d80966100190ebd4d28f1dc50eb0 Mon Sep 17 00:00:00 2001 From: gjbauer Date: Sun, 16 Nov 2025 16:07:21 -0500 Subject: [PATCH 06/11] Refactor RISC-V UEFI target configuration --- .../spec/targets/riscv64gc_unknown_uefi.rs | 45 +++++++------------ 1 file changed, 15 insertions(+), 30 deletions(-) diff --git a/compiler/rustc_target/src/spec/targets/riscv64gc_unknown_uefi.rs b/compiler/rustc_target/src/spec/targets/riscv64gc_unknown_uefi.rs index 48a4f66738bf6..be81a887c1863 100644 --- a/compiler/rustc_target/src/spec/targets/riscv64gc_unknown_uefi.rs +++ b/compiler/rustc_target/src/spec/targets/riscv64gc_unknown_uefi.rs @@ -1,45 +1,30 @@ use crate::spec::{ - Arch, CodeModel, LinkerFlavor, Lld, PanicStrategy, RelocModel, - Target, TargetOptions, TargetMetadata, Os + Arch, Target, TargetMetadata, base }; pub(crate) fn target() -> Target { + // Get the base UEFI configuration + let mut base = base::uefi_msvc::opts(); + + // Override with RISC-V specific settings + base.cpu = "generic-rv64".into(); + base.features = "+m,+a,+f,+d,+c".into(); + base.max_atomic_width = Some(64); + base.atomic_cas = true; + base.disable_redzone = true; + Target { - data_layout: "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128".into(), + llvm_target: "riscv64".into(), metadata: TargetMetadata { description: Some("Bare RISC-V (RV64IMAFDC ISA) UEFI".into()), tier: Some(3), host_tools: Some(false), - std: Some(false), + std: None, }, - llvm_target: "riscv64gc-unknown-windows".into(), pointer_width: 64, + data_layout: "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128".into(), arch: Arch::RiscV64, - options: TargetOptions { - os: Os::Uefi, - vendor: "unknown".into(), - linker_flavor: LinkerFlavor::Msvc(Lld::No), - - // UEFI characteristics - executables: true, - is_like_windows: true, - panic_strategy: PanicStrategy::Abort, - relocation_model: RelocModel::Pic, - - // RISC-V features - cpu: "generic-rv64".into(), - features: "+m,+a,+f,+d,+c".into(), - - // These are the current correct field names: - is_like_aix: false, - is_like_android: false, - is_like_msvc: true, - - // Codegen options - code_model: Some(CodeModel::Medium), - disable_redzone: true, - ..Default::default() - }, + options: base, } } From 8a6f78f7afa25f779d690d90a681e675b1597fbe Mon Sep 17 00:00:00 2001 From: gjbauer Date: Sun, 16 Nov 2025 16:23:01 -0500 Subject: [PATCH 07/11] Set LLVM ABI name to 'lp64d' for RISC-V target --- compiler/rustc_target/src/spec/targets/riscv64gc_unknown_uefi.rs | 1 + 1 file changed, 1 insertion(+) diff --git a/compiler/rustc_target/src/spec/targets/riscv64gc_unknown_uefi.rs b/compiler/rustc_target/src/spec/targets/riscv64gc_unknown_uefi.rs index be81a887c1863..a5ca249127002 100644 --- a/compiler/rustc_target/src/spec/targets/riscv64gc_unknown_uefi.rs +++ b/compiler/rustc_target/src/spec/targets/riscv64gc_unknown_uefi.rs @@ -12,6 +12,7 @@ pub(crate) fn target() -> Target { base.max_atomic_width = Some(64); base.atomic_cas = true; base.disable_redzone = true; + base.llvm_abiname = "lp64d".into(); Target { llvm_target: "riscv64".into(), From b343aa43bb9c814ea72027b6948ad4da814f4f05 Mon Sep 17 00:00:00 2001 From: gjbauer Date: Mon, 17 Nov 2025 12:10:01 -0500 Subject: [PATCH 08/11] Adjust section flags for RISC-V architecture --- compiler/rustc_codegen_llvm/src/back/write.rs | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/compiler/rustc_codegen_llvm/src/back/write.rs b/compiler/rustc_codegen_llvm/src/back/write.rs index fde7dd6ef7a85..0af5d6bff718b 100644 --- a/compiler/rustc_codegen_llvm/src/back/write.rs +++ b/compiler/rustc_codegen_llvm/src/back/write.rs @@ -1189,7 +1189,8 @@ fn embed_bitcode( llvm::set_linkage(llglobal, llvm::Linkage::PrivateLinkage); } else { // We need custom section flags, so emit module-level inline assembly. - let section_flags = if cgcx.is_pe_coff { "n" } else { "e" }; + // The "n" flags is currently not supported on RISC-V + let section_flags = if cgcx.is_pe_coff && cgcx.target_arch != "riscv64" { "n" } else { "e" }; let asm = create_section_with_flags_asm(".llvmbc", section_flags, bitcode); llvm::append_module_inline_asm(llmod, &asm); let asm = create_section_with_flags_asm(".llvmcmd", section_flags, &[]); From c2080d8f162e88e047c9d3d185903dab64bebc53 Mon Sep 17 00:00:00 2001 From: gjbauer Date: Mon, 17 Nov 2025 12:33:22 -0500 Subject: [PATCH 09/11] Refactor section_flags assignment for clarity --- compiler/rustc_codegen_llvm/src/back/write.rs | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/compiler/rustc_codegen_llvm/src/back/write.rs b/compiler/rustc_codegen_llvm/src/back/write.rs index 0af5d6bff718b..df75541c787b9 100644 --- a/compiler/rustc_codegen_llvm/src/back/write.rs +++ b/compiler/rustc_codegen_llvm/src/back/write.rs @@ -1190,7 +1190,11 @@ fn embed_bitcode( } else { // We need custom section flags, so emit module-level inline assembly. // The "n" flags is currently not supported on RISC-V - let section_flags = if cgcx.is_pe_coff && cgcx.target_arch != "riscv64" { "n" } else { "e" }; + let mut section_flags = ""; + if cgcx.target_arch != "riscv64" + { + if cgcx.is_pe_coff { section_flags = "n" } else { section_flags = "e" }; + } let asm = create_section_with_flags_asm(".llvmbc", section_flags, bitcode); llvm::append_module_inline_asm(llmod, &asm); let asm = create_section_with_flags_asm(".llvmcmd", section_flags, &[]); From fed1d012bcd5ae7a03eca7d71d74de056df62cf0 Mon Sep 17 00:00:00 2001 From: gjbauer Date: Mon, 17 Nov 2025 13:01:20 -0500 Subject: [PATCH 10/11] Update architecture handling for RISC-V 64 UEFI --- compiler/rustc_codegen_ssa/src/back/metadata.rs | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/compiler/rustc_codegen_ssa/src/back/metadata.rs b/compiler/rustc_codegen_ssa/src/back/metadata.rs index 6dff79374f20f..fc8281ae121d6 100644 --- a/compiler/rustc_codegen_ssa/src/back/metadata.rs +++ b/compiler/rustc_codegen_ssa/src/back/metadata.rs @@ -20,7 +20,7 @@ use rustc_metadata::fs::METADATA_FILENAME; use rustc_middle::bug; use rustc_session::Session; use rustc_span::sym; -use rustc_target::spec::{Abi, Os, RelocModel, Target, ef_avr_arch}; +use rustc_target::spec::{Abi, Arch, Os, RelocModel, Target, ef_avr_arch}; use tracing::debug; use super::apple; @@ -211,6 +211,12 @@ pub(crate) fn create_object_file(sess: &Session) -> Option Date: Mon, 17 Nov 2025 13:24:37 -0500 Subject: [PATCH 11/11] Change llvm_target to 'riscv64-unknown-windows' --- .../rustc_target/src/spec/targets/riscv64gc_unknown_uefi.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/rustc_target/src/spec/targets/riscv64gc_unknown_uefi.rs b/compiler/rustc_target/src/spec/targets/riscv64gc_unknown_uefi.rs index a5ca249127002..ff31d9ad8dbf0 100644 --- a/compiler/rustc_target/src/spec/targets/riscv64gc_unknown_uefi.rs +++ b/compiler/rustc_target/src/spec/targets/riscv64gc_unknown_uefi.rs @@ -15,7 +15,7 @@ pub(crate) fn target() -> Target { base.llvm_abiname = "lp64d".into(); Target { - llvm_target: "riscv64".into(), + llvm_target: "riscv64-unknown-windows".into(), metadata: TargetMetadata { description: Some("Bare RISC-V (RV64IMAFDC ISA) UEFI".into()), tier: Some(3),