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Miri and miri-related code contains repetitions of `(n << amt) >> amt` #56233

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@kenta7777
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kenta7777 commented Nov 26, 2018

I reduced some code repetitions contains (n << amt) >> amt.
This pull request is related to #49937.

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rust-highfive commented Nov 26, 2018

r? @eddyb

(rust_highfive has picked a reviewer for you, use r? to override)

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rust-highfive commented Nov 26, 2018

⚠️ Warning ⚠️

  • These commits modify submodules.
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rust-highfive commented Nov 26, 2018

The job x86_64-gnu-llvm-5.0 of your PR failed on Travis (raw log). Through arcane magic we have determined that the following fragments from the build log may contain information about the problem.

Click to expand the log.
travis_time:end:0c46d970:start=1543235043781394757,finish=1543235045700239299,duration=1918844542
$ git checkout -qf FETCH_HEAD
travis_fold:end:git.checkout

Encrypted environment variables have been removed for security reasons.
See https://docs.travis-ci.com/user/pull-requests/#Pull-Requests-and-Security-Restrictions
$ export SCCACHE_BUCKET=rust-lang-ci-sccache2
$ export SCCACHE_REGION=us-west-1
Setting environment variables from .travis.yml
$ export IMAGE=x86_64-gnu-llvm-5.0
---
[00:03:59] tidy error: /checkout/src/librustc_lint/types.rs:383: trailing whitespace
[00:04:01] some tidy checks failed
[00:04:01] 
[00:04:01] 
[00:04:01] command did not execute successfully: "/checkout/obj/build/x86_64-unknown-linux-gnu/stage0-tools-bin/tidy" "/checkout/src" "/checkout/obj/build/x86_64-unknown-linux-gnu/stage0/bin/cargo" "--no-vendor" "--quiet"
[00:04:01] 
[00:04:01] 
[00:04:01] failed to run: /checkout/obj/build/bootstrap/debug/bootstrap test src/tools/tidy
[00:04:01] Build completed unsuccessfully in 0:01:04
[00:04:01] Build completed unsuccessfully in 0:01:04
[00:04:01] Makefile:79: recipe for target 'tidy' failed
[00:04:01] make: *** [tidy] Error 1
The command "stamp sh -x -c "$RUN_SCRIPT"" exited with 2.
travis_time:start:05677c10
$ date && (curl -fs --head https://google.com | grep ^Date: | sed 's/Date: //g' || true)
Mon Nov 26 12:28:16 UTC 2018
---
travis_time:end:00677a24:start=1543235296990015081,finish=1543235296994796790,duration=4781709
travis_fold:end:after_failure.3
travis_fold:start:after_failure.4
travis_time:start:1efe883c
$ ln -s . checkout && for CORE in obj/cores/core.*; do EXE=$(echo $CORE | sed 's|obj/cores/core\.[0-9]*\.!checkout!\(.*\)|\1|;y|!|/|'); if [ -f "$EXE" ]; then printf travis_fold":start:crashlog\n\033[31;1m%s\033[0m\n" "$CORE"; gdb --batch -q -c "$CORE" "$EXE" -iex 'set auto-load off' -iex 'dir src/' -iex 'set sysroot .' -ex bt -ex q; echo travis_fold":"end:crashlog; fi; done || true
travis_fold:end:after_failure.4
travis_fold:start:after_failure.5
travis_time:start:04f58583
travis_time:start:04f58583
$ cat ./obj/build/x86_64-unknown-linux-gnu/native/asan/build/lib/asan/clang_rt.asan-dynamic-i386.vers || true
cat: ./obj/build/x86_64-unknown-linux-gnu/native/asan/build/lib/asan/clang_rt.asan-dynamic-i386.vers: No such file or directory
travis_fold:end:after_failure.5
travis_fold:start:after_failure.6
travis_time:start:27e9619c
$ dmesg | grep -i kill

I'm a bot! I can only do what humans tell me to, so if this was not helpful or you have suggestions for improvements, please ping or otherwise contact @TimNN. (Feature Requests)

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eddyb commented Nov 26, 2018

You have accidental submodule changes. Please use git gui's amend mode to remove them from the commit, and run git submodule update, then force push the fixed commit.

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eddyb commented Nov 26, 2018

@rust-highfive rust-highfive assigned oli-obk and unassigned eddyb Nov 26, 2018

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eddyb commented Nov 26, 2018

(Oh, you have multiple commits, you'll have to use git rebase -i HEAD~3 to edit them)

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rust-highfive commented Nov 26, 2018

The job x86_64-gnu-llvm-5.0 of your PR failed on Travis (raw log). Through arcane magic we have determined that the following fragments from the build log may contain information about the problem.

Click to expand the log.
travis_time:end:01e387b0:start=1543237076849265517,finish=1543237077852153167,duration=1002887650
$ git checkout -qf FETCH_HEAD
travis_fold:end:git.checkout

Encrypted environment variables have been removed for security reasons.
See https://docs.travis-ci.com/user/pull-requests/#Pull-Requests-and-Security-Restrictions
$ export SCCACHE_BUCKET=rust-lang-ci-sccache2
$ export SCCACHE_REGION=us-west-1
Setting environment variables from .travis.yml
$ export IMAGE=x86_64-gnu-llvm-5.0
---
[00:17:58]    Compiling build_helper v0.1.0 (/checkout/src/build_helper)
[00:18:04] error[E0432]: unresolved import `slice::SliceExt`
[00:18:04]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:15:21
[00:18:04]    |
[00:18:04] 15 |                   use slice::SliceExt;
[00:18:04]    |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:18:04]    | 
[00:18:04]   ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:3:1
[00:18:04]    |
[00:18:04] 3  | / simd_i_ty! {
[00:18:04] 4  | |     i8x16: 16, i8, m8x16, i8x16_tests, test_v128 |
[00:18:04] 5  | |     i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8  |
[00:18:04] 6  | |     x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15 |
[00:18:04] 7  | |     /// A 128-bit vector with 16 `i8` lanes.
[00:18:04]    | |_- in this macro invocation
[00:18:04] 
[00:18:04] error[E0432]: unresolved import `slice::SliceExt`
[00:18:04]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:35:21
[00:18:04]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:35:21
[00:18:04]    |
[00:18:04] 35 |                   use slice::SliceExt;
[00:18:04]    |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:18:04]    | 
[00:18:04]   ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:3:1
[00:18:04]    |
[00:18:04] 3  | / simd_i_ty! {
[00:18:04] 4  | |     i8x16: 16, i8, m8x16, i8x16_tests, test_v128 |
[00:18:04] 5  | |     i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8  |
[00:18:04] 6  | |     x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15 |
[00:18:04] 7  | |     /// A 128-bit vector with 16 `i8` lanes.
[00:18:04]    | |_- in this macro invocation
[00:18:04] 
[00:18:04] error[E0432]: unresolved import `slice::SliceExt`
[00:18:04]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:53:21
[00:18:04]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:53:21
[00:18:04]    |
[00:18:04] 53 |                   use slice::SliceExt;
[00:18:04]    |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:18:04]    | 
[00:18:04]   ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:3:1
[00:18:04]    |
[00:18:04] 3  | / simd_i_ty! {
[00:18:04] 4  | |     i8x16: 16, i8, m8x16, i8x16_tests, test_v128 |
[00:18:04] 5  | |     i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8  |
[00:18:04] 6  | |     x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15 |
[00:18:04] 7  | |     /// A 128-bit vector with 16 `i8` lanes.
[00:18:04]    | |_- in this macro invocation
[00:18:04] 
[00:18:04] error[E0432]: unresolved import `slice::SliceExt`
[00:18:04]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:67:21
[00:18:04]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:67:21
[00:18:04]    |
[00:18:04] 67 |                   use slice::SliceExt;
[00:18:04]    |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:18:04]    | 
[00:18:04]   ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:3:1
[00:18:04]    |
[00:18:04] 3  | / simd_i_ty! {
[00:18:04] 4  | |     i8x16: 16, i8, m8x16, i8x16_tests, test_v128 |
[00:18:04] 5  | |     i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8  |
[00:18:04] 6  | |     x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15 |
[00:18:04] 7  | |     /// A 128-bit vector with 16 `i8` lanes.
[00:18:04]    | |_- in this macro invocation
[00:18:04] 
[00:18:04] error[E0432]: unresolved import `slice::SliceExt`
[00:18:04]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:87:25
[00:18:04]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:87:25
[00:18:04]    |
[00:18:04] 87 |                       use slice::SliceExt;
[00:18:04]    |                           ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:18:04]    | 
[00:18:04]   ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:3:1
[00:18:04]    |
[00:18:04] 3  | / simd_i_ty! {
[00:18:04] 4  | |     i8x16: 16, i8, m8x16, i8x16_tests, test_v128 |
[00:18:04] 5  | |     i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8  |
[00:18:04] 6  | |     x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15 |
[00:18:04] 7  | |     /// A 128-bit vector with 16 `i8` lanes.
[00:18:04]    | |_- in this macro invocation
[00:18:04] 
[00:18:04] error[E0432]: unresolved import `slice::SliceExt`
[00:18:04]    --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:105:21
[00:18:04]    --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:105:21
[00:18:04]     |
[00:18:04] 105 |                   use slice::SliceExt;
[00:18:04]     |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:18:04]     | 
[00:18:04]    ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:3:1
[00:18:04]     |
[00:18:04] 3   | / simd_i_ty! {
[00:18:04] 4   | |     i8x16: 16, i8, m8x16, i8x16_tests, test_v128 |
[00:18:04] 5   | |     i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8  |
[00:18:04] 6   | |     x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15 |
[00:18:04] 7   | |     /// A 128-bit vector with 16 `i8` lanes.
[00:18:04]     | |_- in this macro invocation
[00:18:04] 
[00:18:04] error[E0432]: unresolved import `slice::SliceExt`
[00:18:04]    --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:120:21
[00:18:04]    --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:120:21
[00:18:04]     |
[00:18:04] 120 |                   use slice::SliceExt;
[00:18:04]     |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:18:04]     | 
[00:18:04]    ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:3:1
[00:18:04]     |
[00:18:04] 3   | / simd_i_ty! {
[00:18:04] 4   | |     i8x16: 16, i8, m8x16, i8x16_tests, test_v128 |
[00:18:04] 5   | |     i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8  |
[00:18:04] 6   | |     x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15 |
[00:18:04] 7   | |     /// A 128-bit vector with 16 `i8` lanes.
[00:18:04]     | |_- in this macro invocation
[00:18:04] 
[00:18:04] error[E0432]: unresolved import `slice::SliceExt`
[00:18:04]    --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:134:21
[00:18:04]    --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:134:21
[00:18:04]     |
[00:18:04] 134 |                   use slice::SliceExt;
[00:18:04]     |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:18:04]     | 
[00:18:04]    ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:3:1
[00:18:04]     |
[00:18:04] 3   | / simd_i_ty! {
[00:18:04] 4   | |     i8x16: 16, i8, m8x16, i8x16_tests, test_v128 |
[00:18:04] 5   | |     i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8  |
[00:18:04] 6   | |     x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15 |
[00:18:04] 7   | |     /// A 128-bit vector with 16 `i8` lanes.
[00:18:04]     | |_- in this macro invocation
[00:18:04] 
[00:18:04] error[E0432]: unresolved import `slice::SliceExt`
[00:18:04]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:15:21
[00:18:04]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:15:21
[00:18:04]    |
[00:18:04] 15 |                   use slice::SliceExt;
[00:18:04]    |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:18:04]    | 
[00:18:04]   ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:10:1
[00:18:04]    |
[00:18:04] 10 | / simd_u_ty! {
[00:18:04] 11 | |     u8x16: 16, u8, m8x16, u8x16_tests, test_v128 |
[00:18:04] 12 | |     u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8 |
[00:18:04] 13 | |     x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15 |
[00:18:04] 14 | |     /// A 128-bit vector with 16 `u8` lanes.
[00:18:04]    | |_- in this macro invocation
[00:18:04] 
[00:18:04] error[E0432]: unresolved import `slice::SliceExt`
[00:18:04]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:35:21
[00:18:04]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:35:21
[00:18:04]    |
[00:18:04] 35 |                   use slice::SliceExt;
[00:18:04]    |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:18:04]    | 
[00:18:04]   ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:10:1
[00:18:04]    |
[00:18:04] 10 | / simd_u_ty! {
[00:18:04] 11 | |     u8x16: 16, u8, m8x16, u8x16_tests, test_v128 |
[00:18:04] 12 | |     u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8 |
[00:18:04] 13 | |     x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15 |
[00:18:04] 14 | |     /// A 128-bit vector with 16 `u8` lanes.
[00:18:04]    | |_- in this macro invocation
[00:18:04] 
[00:18:04] error[E0432]: unresolved import `slice::SliceExt`
[00:18:04]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:53:21
[00:18:04]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:53:21
[00:18:04]    |
[00:18:04] 53 |                   use slice::SliceExt;
[00:18:04]    |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:18:04]    | 
[00:18:04]   ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:10:1
[00:18:04]    |
[00:18:04] 10 | / simd_u_ty! {
[00:18:04] 11 | |     u8x16: 16, u8, m8x16, u8x16_tests, test_v128 |
[00:18:04] 12 | |     u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8 |
[00:18:04] 13 | |     x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15 |
[00:18:04] 14 | |     /// A 128-bit vector with 16 `u8` lanes.
[00:18:04]    | |_- in this macro invocation
[00:18:04] 
[00:18:04] error[E0432]: unresolved import `slice::SliceExt`
[00:18:04]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:67:21
[00:18:04]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:67:21
[00:18:04]    |
[00:18:04] 67 |                   use slice::SliceExt;
[00:18:04]    |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:18:04]    | 
[00:18:04]   ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:10:1
[00:18:04]    |
[00:18:04] 10 | / simd_u_ty! {
[00:18:04] 11 | |     u8x16: 16, u8, m8x16, u8x16_tests, test_v128 |
[00:18:04] 12 | |     u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8 |
[00:18:04] 13 | |     x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15 |
[00:18:04] 14 | |     /// A 128-bit vector with 16 `u8` lanes.
[00:18:04]    | |_- in this macro invocation
[00:18:04] 
[00:18:04] error[E0432]: unresolved import `slice::SliceExt`
[00:18:04]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:87:25
[00:18:04]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:87:25
[00:18:04]    |
[00:18:04] 87 |                       use slice::SliceExt;
[00:18:04]    |                           ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:18:04]    | 
[00:18:04]   ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:10:1
[00:18:04]    |
[00:18:04] 10 | / simd_u_ty! {
[00:18:04] 11 | |     u8x16: 16, u8, m8x16, u8x16_tests, test_v128 |
[00:18:04] 12 | |     u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8 |
[00:18:04] 13 | |     x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15 |
[00:18:04] 14 | |     /// A 128-bit vector with 16 `u8` lanes.
[00:18:04]    | |_- in this macro invocation
[00:18:04] 
[00:18:04] error[E0432]: unresolved import `slice::SliceExt`
[00:18:04]    --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:105:21
[00:18:04]    --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:105:21
[00:18:04]     |
[00:18:04] 105 |                   use slice::SliceExt;
[00:18:04]     |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:18:04]     | 
[00:18:04]    ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:10:1
[00:18:04]     |
[00:18:04] 10  | / simd_u_ty! {
[00:18:04] 11  | |     u8x16: 16, u8, m8x16, u8x16_tests, test_v128 |
[00:18:04] 12  | |     u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8 |
[00:18:04] 13  | |     x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15 |
[00:18:04] 14  | |     /// A 128-bit vector with 16 `u8` lanes.
[00:18:04]     | |_- in this macro invocation
[00:18:04] 
[00:18:04] error[E0432]: unresolved import `slice::SliceExt`
[00:18:04]    --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:120:21
[00:18:04]    --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:120:21
[00:18:04]     |
[00:18:04] 120 |                   use slice::SliceExt;
[00:18:04]     |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:18:04]     | 
[00:18:04]    ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:10:1
[00:18:04]     |
[00:18:04] 10  | / simd_u_ty! {
[00:18:04] 11  | |     u8x16: 16, u8, m8x16, u8x16_tests, test_v128 |
[00:18:04] 12  | |     u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8 |
[00:18:04] 13  | |     x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15 |
[00:18:04] 14  | |     /// A 128-bit vector with 16 `u8` lanes.
[00:18:04]     | |_- in this macro invocation
[00:18:04] 
[00:18:04] error[E0432]: unresolved import `slice::SliceExt`
[00:18:04]    --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:134:21
[00:18:04]    --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:134:21
[00:18:04]     |
[00:18:04] 134 |                   use slice::SliceExt;
[00:18:04]     |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:18:04]     | 
[00:18:04]    ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:10:1
[00:18:04]     |
[00:18:04] 10  | / simd_u_ty! {
[00:18:04] 11  | |     u8x16: 16, u8, m8x16, u8x16_tests, test_v128 |
[00:18:04] 12  | |     u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8 |
[00:18:04] 13  | |     x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15 |
[00:18:04] 14  | |     /// A 128-bit vector with 16 `u8` lanes.
[00:18:04]     | |_- in this macro invocation
[00:18:04] 
[00:18:04] error[E0432]: unresolved import `slice::SliceExt`
[00:18:04]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:15:21
[00:18:04]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:15:21
[00:18:04]    |
[00:18:04] 15 |                   use slice::SliceExt;
[00:18:04]    |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:18:04]    | 
[00:18:04]   ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:24:1
[00:18:04]    |
[00:18:04] 24 | / simd_i_ty! {
[00:18:04] 25 | |     i16x8: 8, i16, m16x8, i16x8_tests, test_v128 |
[00:18:04] 26 | |     i16, i16, i16, i16, i16, i16, i16, i16 |
[00:18:04] 27 | |     x0, x1, x2, x3, x4, x5, x6, x7 |
[00:18:04] 28 | |     /// A 128-bit vector with 8 `i16` lanes.
[00:18:04]    | |_- in this macro invocation
[00:18:04] 
[00:18:04] error[E0432]: unresolved import `slice::SliceExt`
[00:18:04]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:35:21
[00:18:04]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:35:21
[00:18:04]    |
[00:18:04] 35 |                   use slice::SliceExt;
[00:18:04]    |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:18:04]    | 
[00:18:04]   ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:24:1
[00:18:04]    |
[00:18:04] 24 | / simd_i_ty! {
[00:18:04] 25 | |     i16x8: 8, i16, m16x8, i16x8_tests, test_v128 |
[00:18:04] 26 | |     i16, i16, i16, i16, i16, i16, i16, i16 |
[00:18:04] 27 | |     x0, x1, x2, x3, x4, x5, x6, x7 |
[00:18:04] 28 | |     /// A 128-bit vector with 8 `i16` lanes.
[00:18:04]    | |_- in this macro invocation
[00:18:04] 
[00:18:04] error[E0432]: unresolved import `slice::SliceExt`
[00:18:04]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:53:21
[00:18:04]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:53:21
[00:18:04]    |
[00:18:04] 53 |                   use slice::SliceExt;
[00:18:04]    |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:18:04]    | 
[00:18:04]   ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:24:1
[00:18:04]    |
[00:18:04] 24 | / simd_i_ty! {
[00:18:04] 25 | |     i16x8: 8, i16, m16x8, i16x8_tests, test_v128 |
[00:18:04] 26 | |     i16, i16, i16, i16, i16, i16, i16, i16 |
[00:18:04] 27 | |     x0, x1, x2, x3, x4, x5, x6, x7 |
[00:18:04] 28 | |     /// A 128-bit vector with 8 `i16` lanes.
[00:18:04]    | |_- in this macro invocation
[00:18:04] 
[00:18:04] error[E0432]: unresolved import `slice::SliceExt`
[00:18:04]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:67:21
[00:18:04]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:67:21
[00:18:04]    |
[00:18:04] 67 |                   use slice::SliceExt;
[00:18:04]    |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:18:04]    | 
[00:18:04]   ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:24:1
[00:18:04]    |
[00:18:04] 24 | / simd_i_ty! {
[00:18:04] 25 | |     i16x8: 8, i16, m16x8, i16x8_tests, test_v128 |
[00:18:04] 26 | |     i16, i16, i16, i16, i16, i16, i16, i16 |
[00:18:04] 27 | |     x0, x1, x2, x3, x4, x5, x6, x7 |
[00:18:04] 28 | |     /// A 128-bit vector with 8 `i16` lanes.
[00:18:04]    | |_- in this macro invocation
[00:18:04] 
[00:18:04] error[E0432]: unresolved import `slice::SliceExt`
[00:18:04]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:87:25
[00:18:04]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:87:25
[00:18:04]    |
[00:18:04] 87 |                       use slice::SliceExt;
[00:18:04]    |                           ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:18:04]    | 
[00:18:04]   ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:24:1
[00:18:04]    |
[00:18:04] 24 | / simd_i_ty! {
[00:18:04] 25 | |     i16x8: 8, i16, m16x8, i16x8_tests, test_v128 |
[00:18:04] 26 | |     i16, i16, i16, i16, i16, i16, i16, i16 |
[00:18:04] 27 | |     x0, x1, x2, x3, x4, x5, x6, x7 |
[00:18:04] 28 | |     /// A 128-bit vector with 8 `i16` lanes.
[00:18:04]    | |_- in this macro invocation
[00:18:04] 
[00:18:04] error[E0432]: unresolved import `slice::SliceExt`
[00:18:04]    --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:105:21
[00:18:04]    --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:105:21
[00:18:04]     |
[00:18:04] 105 |                   use slice::SliceExt;
[00:18:04]     |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:18:04]     | 
[00:18:04]    ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:24:1
[00:18:04]     |
[00:18:04] 24  | / simd_i_ty! {
[00:18:04] 25  | |     i16x8: 8, i16, m16x8, i16x8_tests, test_v128 |
[00:18:04] 26  | |     i16, i16, i16, i16, i16, i16, i16, i16 |
[00:18:04] 27  | |     x0, x1, x2, x3, x4, x5, x6, x7 |
[00:18:04] 28  | |     /// A 128-bit vector with 8 `i16` lanes.
[00:18:04]     | |_- in this macro invocation
[00:18:04] 
[00:18:04] error[E0432]: unresolved import `slice::SliceExt`
[00:18:04]    --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:120:21
[00:18:04]    --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:120:21
[00:18:04]     |
[00:18:04] 120 |                   use slice::SliceExt;
[00:18:04]     |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:18:04]     | 
[00:18:04]    ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:24:1
[00:18:04]     |
[00:18:04] 24  | / simd_i_ty! {
[00:18:04] 25  | |     i16x8: 8, i16, m16x8, i16x8_tests, test_v128 |
[00:18:04] 26  | |     i16, i16, i16, i16, i16, i16, i16, i16 |
[00:18:04] 27  | |     x0, x1, x2, x3, x4, x5, x6, x7 |
[00:18:04] 28  | |     /// A 128-bit vector with 8 `i16` lanes.
[00:18:04]     | |_- in this macro invocation
[00:18:04] 
[00:18:04] error[E0432]: unresolved import `slice::SliceExt`
[00:18:04]    --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:134:21
[00:18:04]    --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:134:21
[00:18:04]     |
[00:18:04] 134 |                   use slice::SliceExt;
[00:18:04]     |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:18:04]     | 
[00:18:04]    ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:24:1
[00:18:04]     |
[00:18:04] 24  | / simd_i_ty! {
[00:18:04] 25  | |     i16x8: 8, i16, m16x8, i16x8_tests, test_v128 |
[00:18:04] 26  | |     i16, i16, i16, i16, i16, i16, i16, i16 |
[00:18:04] 27  | |     x0, x1, x2, x3, x4, x5, x6, x7 |
[00:18:04] 28  | |     /// A 128-bit vector with 8 `i16` lanes.
[00:18:04]     | |_- in this macro invocation
[00:18:04] 
[00:18:04] error[E0432]: unresolved import `slice::SliceExt`
[00:18:04]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:15:21
[00:18:04]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:15:21
[00:18:04]    |
[00:18:04] 15 |                   use slice::SliceExt;
[00:18:04]    |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:18:04]    | 
[00:18:04]   ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:31:1
[00:18:04]    |
[00:18:04] 31 | / simd_u_ty! {
[00:18:04] 32 | |     u16x8: 8, u16, m16x8, u16x8_tests, test_v128 |
[00:18:04] 33 | |     u16, u16, u16, u16, u16, u16, u16, u16 |
[00:18:04] 34 | |     x0, x1, x2, x3, x4, x5, x6, x7 |
[00:18:04] 35 | |     /// A 128-bit vector with 8 `u16` lanes.
[00:18:04]    | |_- in this macro invocation
[00:18:04] 
[00:18:04] error[E0432]: unresolved import `slice::SliceExt`
[00:18:04]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:35:21
[00:18:04]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:35:21
[00:18:04]    |
[00:18:04] 35 |                   use slice::SliceExt;
[00:18:04]    |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:18:04]    | 
[00:18:04]   ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:31:1
[00:18:04]    |
[00:18:04] 31 | / simd_u_ty! {
[00:18:04] 32 | |     u16x8: 8, u16, m16x8, u16x8_tests, test_v128 |
[00:18:04] 33 | |     u16, u16, u16, u16, u16, u16, u16, u16 |
[00:18:04] 34 | |     x0, x1, x2, x3, x4, x5, x6, x7 |
[00:18:04] 35 | |     /// A 128-bit vector with 8 `u16` lanes.
[00:18:04]    | |_- in this macro invocation
[00:18:04] 
[00:18:04] error[E0432]: unresolved import `slice::SliceExt`
[00:18:04]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:53:21
[00:18:04]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:53:21
[00:18:04]    |
[00:18:04] 53 |                   use slice::SliceExt;
[00:18:04]    |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:18:04]    | 
[00:18:04]   ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:31:1
[00:18:04]    |
[00:18:04] 31 | / simd_u_ty! {
[00:18:04] 32 | |     u16x8: 8, u16, m16x8, u16x8_tests, test_v128 |
[00:18:04] 33 | |     u16, u16, u16, u16, u16, u16, u16, u16 |
[00:18:04] 34 | |     x0, x1, x2, x3, x4, x5, x6, x7 |
[00:18:04] 35 | |     /// A 128-bit vector with 8 `u16` lanes.
[00:18:04]    | |_- in this macro invocation
[00:18:04] 
[00:18:04] error[E0432]: unresolved import `slice::SliceExt`
[00:18:04]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:67:21
[00:18:04]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:67:21
[00:18:04]    |
[00:18:04] 67 |                   use slice::SliceExt;
[00:18:04]    |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:18:04]    | 
[00:18:04]   ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:31:1
[00:18:04]    |
[00:18:04] 31 | / simd_u_ty! {
[00:18:04] 32 | |     u16x8: 8, u16, m16x8, u16x8_tests, test_v128 |
[00:18:04] 33 | |     u16, u16, u16, u16, u16, u16, u16, u16 |
[00:18:04] 34 | |     x0, x1, x2, x3, x4, x5, x6, x7 |
[00:18:04] 35 | |     /// A 128-bit vector with 8 `u16` lanes.
[00:18:04]    | |_- in this macro invocation
[00:18:04] 
[00:18:04] error[E0432]: unresolved import `slice::SliceExt`
[00:18:04]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:87:25
[00:18:04]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:87:25
[00:18:04]    |
[00:18:04] 87 |                       use slice::SliceExt;
[00:18:04]    |                           ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:18:04]    | 
[00:18:04]   ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:31:1
[00:18:04]    |
[00:18:04] 31 | / simd_u_ty! {
[00:18:04] 32 | |     u16x8: 8, u16, m16x8, u16x8_tests, test_v128 |
[00:18:04] 33 | |     u16, u16, u16, u16, u16, u16, u16, u16 |
[00:18:04] 34 | |     x0, x1, x2, x3, x4, x5, x6, x7 |
[00:18:04] 35 | |     /// A 128-bit vector with 8 `u16` lanes.
[00:18:04]    | |_- in this macro invocation
[00:18:04] 
[00:18:04] error[E0432]: unresolved import `slice::SliceExt`
[00:18:04]    --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:105:21
[00:18:04]    --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:105:21
[00:18:04]     |
[00:18:04] 105 |                   use slice::SliceExt;
[00:18:04]     |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:18:04]     | 
[00:18:04]    ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:31:1
[00:18:04]     |
[00:18:04] 31  | / simd_u_ty! {
[00:18:04] 32  | |     u16x8: 8, u16, m16x8, u16x8_tests, test_v128 |
[00:18:04] 33  | |     u16, u16, u16, u16, u16, u16, u16, u16 |
[00:18:04] 34  | |     x0, x1, x2, x3, x4, x5, x6, x7 |
[00:18:04] 35  | |     /// A 128-bit vector with 8 `u16` lanes.
[00:18:04]     | |_- in this macro invocation
[00:18:04] 
[00:18:04] error[E0432]: unresolved import `slice::SliceExt`
[00:18:04]    --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:120:21
[00:18:04]    --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:120:21
[00:18:04]     |
[00:18:04] 120 |                   use slice::SliceExt;
[00:18:04]     |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:18:04]     | 
[00:18:04]    ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:31:1
[00:18:04]     |
[00:18:04] 31  | / simd_u_ty! {
[00:18:04] 32  | |     u16x8: 8, u16, m16x8, u16x8_tests, test_v128 |
[00:18:04] 33  | |     u16, u16, u16, u16, u16, u16, u16, u16 |
[00:18:04] 34  | |     x0, x1, x2, x3, x4, x5, x6, x7 |
[00:18:04] 35  | |     /// A 128-bit vector with 8 `u16` lanes.
[00:18:04]     | |_- in this macro invocation
[00:18:04] 
[00:18:04] error[E0432]: unresolved import `slice::SliceExt`
[00:18:04]    --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:134:21
[00:18:04]    --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:134:21
[00:18:04]     |

I'm a bot! I can only do what humans tell me to, so if this was not helpful or you have suggestions for improvements, please ping or otherwise contact @TimNN. (Feature Requests)

@kenta7777

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kenta7777 commented Nov 26, 2018

@eddyb Thank you for your advice. I updated submodules and pushed again.

@eddyb

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eddyb commented Nov 26, 2018

@kenta7777 When I said HEAD~3 I meant "3 commits", looks like you did it with a different number than 3.
You should do git pull --rebase https://github.com/rust-lang/rust master, maybe that will fix it.

@rust-highfive

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rust-highfive commented Nov 26, 2018

The job x86_64-gnu-llvm-5.0 of your PR failed on Travis (raw log). Through arcane magic we have determined that the following fragments from the build log may contain information about the problem.

Click to expand the log.
travis_time:end:0cb28db6:start=1543238767752384310,finish=1543238824646921054,duration=56894536744
$ git checkout -qf FETCH_HEAD
travis_fold:end:git.checkout

Encrypted environment variables have been removed for security reasons.
See https://docs.travis-ci.com/user/pull-requests/#Pull-Requests-and-Security-Restrictions
$ export SCCACHE_BUCKET=rust-lang-ci-sccache2
$ export SCCACHE_REGION=us-west-1
Setting environment variables from .travis.yml
$ export IMAGE=x86_64-gnu-llvm-5.0
---
[00:19:53]    Compiling std v0.0.0 (/checkout/src/libstd)
[00:19:53] error[E0432]: unresolved import `slice::SliceExt`
[00:19:53]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:15:21
[00:19:53]    |
[00:19:53] 15 |                   use slice::SliceExt;
[00:19:53]    |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:19:53]    | 
[00:19:53]   ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:3:1
[00:19:53]    |
[00:19:53] 3  | / simd_i_ty! {
[00:19:53] 4  | |     i8x16: 16, i8, m8x16, i8x16_tests, test_v128 |
[00:19:53] 5  | |     i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8  |
[00:19:53] 6  | |     x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15 |
[00:19:53] 7  | |     /// A 128-bit vector with 16 `i8` lanes.
[00:19:53]    | |_- in this macro invocation
[00:19:53] 
[00:19:53] error[E0432]: unresolved import `slice::SliceExt`
[00:19:53]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:35:21
[00:19:53]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:35:21
[00:19:53]    |
[00:19:53] 35 |                   use slice::SliceExt;
[00:19:53]    |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:19:53]    | 
[00:19:53]   ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:3:1
[00:19:53]    |
[00:19:53] 3  | / simd_i_ty! {
[00:19:53] 4  | |     i8x16: 16, i8, m8x16, i8x16_tests, test_v128 |
[00:19:53] 5  | |     i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8  |
[00:19:53] 6  | |     x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15 |
[00:19:53] 7  | |     /// A 128-bit vector with 16 `i8` lanes.
[00:19:53]    | |_- in this macro invocation
[00:19:53] 
[00:19:53] error[E0432]: unresolved import `slice::SliceExt`
[00:19:53]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:53:21
[00:19:53]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:53:21
[00:19:53]    |
[00:19:53] 53 |                   use slice::SliceExt;
[00:19:53]    |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:19:53]    | 
[00:19:53]   ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:3:1
[00:19:53]    |
[00:19:53] 3  | / simd_i_ty! {
[00:19:53] 4  | |     i8x16: 16, i8, m8x16, i8x16_tests, test_v128 |
[00:19:53] 5  | |     i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8  |
[00:19:53] 6  | |     x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15 |
[00:19:53] 7  | |     /// A 128-bit vector with 16 `i8` lanes.
[00:19:53]    | |_- in this macro invocation
[00:19:53] 
[00:19:53] error[E0432]: unresolved import `slice::SliceExt`
[00:19:53]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:67:21
[00:19:53]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:67:21
[00:19:53]    |
[00:19:53] 67 |                   use slice::SliceExt;
[00:19:53]    |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:19:53]    | 
[00:19:53]   ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:3:1
[00:19:53]    |
[00:19:53] 3  | / simd_i_ty! {
[00:19:53] 4  | |     i8x16: 16, i8, m8x16, i8x16_tests, test_v128 |
[00:19:53] 5  | |     i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8  |
[00:19:53] 6  | |     x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15 |
[00:19:53] 7  | |     /// A 128-bit vector with 16 `i8` lanes.
[00:19:53]    | |_- in this macro invocation
[00:19:53] 
[00:19:53] error[E0432]: unresolved import `slice::SliceExt`
[00:19:53]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:87:25
[00:19:53]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:87:25
[00:19:53]    |
[00:19:53] 87 |                       use slice::SliceExt;
[00:19:53]    |                           ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:19:53]    | 
[00:19:53]   ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:3:1
[00:19:53]    |
[00:19:53] 3  | / simd_i_ty! {
[00:19:53] 4  | |     i8x16: 16, i8, m8x16, i8x16_tests, test_v128 |
[00:19:53] 5  | |     i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8  |
[00:19:53] 6  | |     x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15 |
[00:19:53] 7  | |     /// A 128-bit vector with 16 `i8` lanes.
[00:19:53]    | |_- in this macro invocation
[00:19:53] 
[00:19:53] error[E0432]: unresolved import `slice::SliceExt`
[00:19:53]    --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:105:21
[00:19:53]    --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:105:21
[00:19:53]     |
[00:19:53] 105 |                   use slice::SliceExt;
[00:19:53]     |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:19:53]     | 
[00:19:53]    ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:3:1
[00:19:53]     |
[00:19:53] 3   | / simd_i_ty! {
[00:19:53] 4   | |     i8x16: 16, i8, m8x16, i8x16_tests, test_v128 |
[00:19:53] 5   | |     i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8  |
[00:19:53] 6   | |     x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15 |
[00:19:53] 7   | |     /// A 128-bit vector with 16 `i8` lanes.
[00:19:53]     | |_- in this macro invocation
[00:19:53] 
[00:19:53] error[E0432]: unresolved import `slice::SliceExt`
[00:19:53]    --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:120:21
[00:19:53]    --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:120:21
[00:19:53]     |
[00:19:53] 120 |                   use slice::SliceExt;
[00:19:53]     |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:19:53]     | 
[00:19:53]    ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:3:1
[00:19:53]     |
[00:19:53] 3   | / simd_i_ty! {
[00:19:53] 4   | |     i8x16: 16, i8, m8x16, i8x16_tests, test_v128 |
[00:19:53] 5   | |     i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8  |
[00:19:53] 6   | |     x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15 |
[00:19:53] 7   | |     /// A 128-bit vector with 16 `i8` lanes.
[00:19:53]     | |_- in this macro invocation
[00:19:53] 
[00:19:53] error[E0432]: unresolved import `slice::SliceExt`
[00:19:53]    --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:134:21
[00:19:53]    --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:134:21
[00:19:53]     |
[00:19:53] 134 |                   use slice::SliceExt;
[00:19:53]     |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:19:53]     | 
[00:19:53]    ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:3:1
[00:19:53]     |
[00:19:53] 3   | / simd_i_ty! {
[00:19:53] 4   | |     i8x16: 16, i8, m8x16, i8x16_tests, test_v128 |
[00:19:53] 5   | |     i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8  |
[00:19:53] 6   | |     x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15 |
[00:19:53] 7   | |     /// A 128-bit vector with 16 `i8` lanes.
[00:19:53]     | |_- in this macro invocation
[00:19:53] 
[00:19:53] error[E0432]: unresolved import `slice::SliceExt`
[00:19:53]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:15:21
[00:19:53]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:15:21
[00:19:53]    |
[00:19:53] 15 |                   use slice::SliceExt;
[00:19:53]    |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:19:53]    | 
[00:19:53]   ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:10:1
[00:19:53]    |
[00:19:53] 10 | / simd_u_ty! {
[00:19:53] 11 | |     u8x16: 16, u8, m8x16, u8x16_tests, test_v128 |
[00:19:53] 12 | |     u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8 |
[00:19:53] 13 | |     x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15 |
[00:19:53] 14 | |     /// A 128-bit vector with 16 `u8` lanes.
[00:19:53]    | |_- in this macro invocation
[00:19:53] 
[00:19:53] error[E0432]: unresolved import `slice::SliceExt`
[00:19:53]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:35:21
[00:19:53]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:35:21
[00:19:53]    |
[00:19:53] 35 |                   use slice::SliceExt;
[00:19:53]    |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:19:53]    | 
[00:19:53]   ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:10:1
[00:19:53]    |
[00:19:53] 10 | / simd_u_ty! {
[00:19:53] 11 | |     u8x16: 16, u8, m8x16, u8x16_tests, test_v128 |
[00:19:53] 12 | |     u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8 |
[00:19:53] 13 | |     x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15 |
[00:19:53] 14 | |     /// A 128-bit vector with 16 `u8` lanes.
[00:19:53]    | |_- in this macro invocation
[00:19:53] 
[00:19:53] error[E0432]: unresolved import `slice::SliceExt`
[00:19:53]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:53:21
[00:19:53]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:53:21
[00:19:53]    |
[00:19:53] 53 |                   use slice::SliceExt;
[00:19:53]    |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:19:53]    | 
[00:19:53]   ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:10:1
[00:19:53]    |
[00:19:53] 10 | / simd_u_ty! {
[00:19:53] 11 | |     u8x16: 16, u8, m8x16, u8x16_tests, test_v128 |
[00:19:53] 12 | |     u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8 |
[00:19:53] 13 | |     x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15 |
[00:19:53] 14 | |     /// A 128-bit vector with 16 `u8` lanes.
[00:19:53]    | |_- in this macro invocation
[00:19:53] 
[00:19:53] error[E0432]: unresolved import `slice::SliceExt`
[00:19:53]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:67:21
[00:19:53]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:67:21
[00:19:53]    |
[00:19:53] 67 |                   use slice::SliceExt;
[00:19:53]    |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:19:53]    | 
[00:19:53]   ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:10:1
[00:19:53]    |
[00:19:53] 10 | / simd_u_ty! {
[00:19:53] 11 | |     u8x16: 16, u8, m8x16, u8x16_tests, test_v128 |
[00:19:53] 12 | |     u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8 |
[00:19:53] 13 | |     x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15 |
[00:19:53] 14 | |     /// A 128-bit vector with 16 `u8` lanes.
[00:19:53]    | |_- in this macro invocation
[00:19:53] 
[00:19:53] error[E0432]: unresolved import `slice::SliceExt`
[00:19:53]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:87:25
[00:19:53]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:87:25
[00:19:53]    |
[00:19:53] 87 |                       use slice::SliceExt;
[00:19:53]    |                           ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:19:53]    | 
[00:19:53]   ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:10:1
[00:19:53]    |
[00:19:53] 10 | / simd_u_ty! {
[00:19:53] 11 | |     u8x16: 16, u8, m8x16, u8x16_tests, test_v128 |
[00:19:53] 12 | |     u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8 |
[00:19:53] 13 | |     x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15 |
[00:19:53] 14 | |     /// A 128-bit vector with 16 `u8` lanes.
[00:19:53]    | |_- in this macro invocation
[00:19:53] 
[00:19:53] error[E0432]: unresolved import `slice::SliceExt`
[00:19:53]    --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:105:21
[00:19:53]    --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:105:21
[00:19:53]     |
[00:19:53] 105 |                   use slice::SliceExt;
[00:19:53]     |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:19:53]     | 
[00:19:53]    ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:10:1
[00:19:53]     |
[00:19:53] 10  | / simd_u_ty! {
[00:19:53] 11  | |     u8x16: 16, u8, m8x16, u8x16_tests, test_v128 |
[00:19:53] 12  | |     u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8 |
[00:19:53] 13  | |     x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15 |
[00:19:53] 14  | |     /// A 128-bit vector with 16 `u8` lanes.
[00:19:53]     | |_- in this macro invocation
[00:19:53] 
[00:19:53] error[E0432]: unresolved import `slice::SliceExt`
[00:19:53]    --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:120:21
[00:19:53]    --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:120:21
[00:19:53]     |
[00:19:53] 120 |                   use slice::SliceExt;
[00:19:53]     |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:19:53]     | 
[00:19:53]    ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:10:1
[00:19:53]     |
[00:19:53] 10  | / simd_u_ty! {
[00:19:53] 11  | |     u8x16: 16, u8, m8x16, u8x16_tests, test_v128 |
[00:19:53] 12  | |     u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8 |
[00:19:53] 13  | |     x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15 |
[00:19:53] 14  | |     /// A 128-bit vector with 16 `u8` lanes.
[00:19:53]     | |_- in this macro invocation
[00:19:53] 
[00:19:53] error[E0432]: unresolved import `slice::SliceExt`
[00:19:53]    --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:134:21
[00:19:53]    --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:134:21
[00:19:53]     |
[00:19:53] 134 |                   use slice::SliceExt;
[00:19:53]     |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:19:53]     | 
[00:19:53]    ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:10:1
[00:19:53]     |
[00:19:53] 10  | / simd_u_ty! {
[00:19:53] 11  | |     u8x16: 16, u8, m8x16, u8x16_tests, test_v128 |
[00:19:53] 12  | |     u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8, u8 |
[00:19:53] 13  | |     x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15 |
[00:19:53] 14  | |     /// A 128-bit vector with 16 `u8` lanes.
[00:19:53]     | |_- in this macro invocation
[00:19:53] 
[00:19:53] error[E0432]: unresolved import `slice::SliceExt`
[00:19:53]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:15:21
[00:19:53]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:15:21
[00:19:53]    |
[00:19:53] 15 |                   use slice::SliceExt;
[00:19:53]    |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:19:53]    | 
[00:19:53]   ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:24:1
[00:19:53]    |
[00:19:53] 24 | / simd_i_ty! {
[00:19:53] 25 | |     i16x8: 8, i16, m16x8, i16x8_tests, test_v128 |
[00:19:53] 26 | |     i16, i16, i16, i16, i16, i16, i16, i16 |
[00:19:53] 27 | |     x0, x1, x2, x3, x4, x5, x6, x7 |
[00:19:53] 28 | |     /// A 128-bit vector with 8 `i16` lanes.
[00:19:53]    | |_- in this macro invocation
[00:19:53] 
[00:19:53] error[E0432]: unresolved import `slice::SliceExt`
[00:19:53]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:35:21
[00:19:53]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:35:21
[00:19:53]    |
[00:19:53] 35 |                   use slice::SliceExt;
[00:19:53]    |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:19:53]    | 
[00:19:53]   ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:24:1
[00:19:53]    |
[00:19:53] 24 | / simd_i_ty! {
[00:19:53] 25 | |     i16x8: 8, i16, m16x8, i16x8_tests, test_v128 |
[00:19:53] 26 | |     i16, i16, i16, i16, i16, i16, i16, i16 |
[00:19:53] 27 | |     x0, x1, x2, x3, x4, x5, x6, x7 |
[00:19:53] 28 | |     /// A 128-bit vector with 8 `i16` lanes.
[00:19:53]    | |_- in this macro invocation
[00:19:53] 
[00:19:53] error[E0432]: unresolved import `slice::SliceExt`
[00:19:53]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:53:21
[00:19:53]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:53:21
[00:19:53]    |
[00:19:53] 53 |                   use slice::SliceExt;
[00:19:53]    |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:19:53]    | 
[00:19:53]   ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:24:1
[00:19:53]    |
[00:19:53] 24 | / simd_i_ty! {
[00:19:53] 25 | |     i16x8: 8, i16, m16x8, i16x8_tests, test_v128 |
[00:19:53] 26 | |     i16, i16, i16, i16, i16, i16, i16, i16 |
[00:19:53] 27 | |     x0, x1, x2, x3, x4, x5, x6, x7 |
[00:19:53] 28 | |     /// A 128-bit vector with 8 `i16` lanes.
[00:19:53]    | |_- in this macro invocation
[00:19:53] 
[00:19:53] error[E0432]: unresolved import `slice::SliceExt`
[00:19:53]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:67:21
[00:19:53]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:67:21
[00:19:53]    |
[00:19:53] 67 |                   use slice::SliceExt;
[00:19:53]    |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:19:53]    | 
[00:19:53]   ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:24:1
[00:19:53]    |
[00:19:53] 24 | / simd_i_ty! {
[00:19:53] 25 | |     i16x8: 8, i16, m16x8, i16x8_tests, test_v128 |
[00:19:53] 26 | |     i16, i16, i16, i16, i16, i16, i16, i16 |
[00:19:53] 27 | |     x0, x1, x2, x3, x4, x5, x6, x7 |
[00:19:53] 28 | |     /// A 128-bit vector with 8 `i16` lanes.
[00:19:53]    | |_- in this macro invocation
[00:19:53] 
[00:19:53] error[E0432]: unresolved import `slice::SliceExt`
[00:19:53]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:87:25
[00:19:53]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:87:25
[00:19:53]    |
[00:19:53] 87 |                       use slice::SliceExt;
[00:19:53]    |                           ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:19:53]    | 
[00:19:53]   ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:24:1
[00:19:53]    |
[00:19:53] 24 | / simd_i_ty! {
[00:19:53] 25 | |     i16x8: 8, i16, m16x8, i16x8_tests, test_v128 |
[00:19:53] 26 | |     i16, i16, i16, i16, i16, i16, i16, i16 |
[00:19:53] 27 | |     x0, x1, x2, x3, x4, x5, x6, x7 |
[00:19:53] 28 | |     /// A 128-bit vector with 8 `i16` lanes.
[00:19:53]    | |_- in this macro invocation
[00:19:53] 
[00:19:53] error[E0432]: unresolved import `slice::SliceExt`
[00:19:53]    --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:105:21
[00:19:53]    --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:105:21
[00:19:53]     |
[00:19:53] 105 |                   use slice::SliceExt;
[00:19:53]     |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:19:53]     | 
[00:19:53]    ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:24:1
[00:19:53]     |
[00:19:53] 24  | / simd_i_ty! {
[00:19:53] 25  | |     i16x8: 8, i16, m16x8, i16x8_tests, test_v128 |
[00:19:53] 26  | |     i16, i16, i16, i16, i16, i16, i16, i16 |
[00:19:53] 27  | |     x0, x1, x2, x3, x4, x5, x6, x7 |
[00:19:53] 28  | |     /// A 128-bit vector with 8 `i16` lanes.
[00:19:53]     | |_- in this macro invocation
[00:19:53] 
[00:19:53] error[E0432]: unresolved import `slice::SliceExt`
[00:19:53]    --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:120:21
[00:19:53]    --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:120:21
[00:19:53]     |
[00:19:53] 120 |                   use slice::SliceExt;
[00:19:53]     |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:19:53]     | 
[00:19:53]    ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:24:1
[00:19:53]     |
[00:19:53] 24  | / simd_i_ty! {
[00:19:53] 25  | |     i16x8: 8, i16, m16x8, i16x8_tests, test_v128 |
[00:19:53] 26  | |     i16, i16, i16, i16, i16, i16, i16, i16 |
[00:19:53] 27  | |     x0, x1, x2, x3, x4, x5, x6, x7 |
[00:19:53] 28  | |     /// A 128-bit vector with 8 `i16` lanes.
[00:19:53]     | |_- in this macro invocation
[00:19:53] 
[00:19:53] error[E0432]: unresolved import `slice::SliceExt`
[00:19:53]    --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:134:21
[00:19:53]    --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:134:21
[00:19:53]     |
[00:19:53] 134 |                   use slice::SliceExt;
[00:19:53]     |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:19:53]     | 
[00:19:53]    ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:24:1
[00:19:53]     |
[00:19:53] 24  | / simd_i_ty! {
[00:19:53] 25  | |     i16x8: 8, i16, m16x8, i16x8_tests, test_v128 |
[00:19:53] 26  | |     i16, i16, i16, i16, i16, i16, i16, i16 |
[00:19:53] 27  | |     x0, x1, x2, x3, x4, x5, x6, x7 |
[00:19:53] 28  | |     /// A 128-bit vector with 8 `i16` lanes.
[00:19:53]     | |_- in this macro invocation
[00:19:53] 
[00:19:53] error[E0432]: unresolved import `slice::SliceExt`
[00:19:53]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:15:21
[00:19:53]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:15:21
[00:19:53]    |
[00:19:53] 15 |                   use slice::SliceExt;
[00:19:53]    |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:19:53]    | 
[00:19:53]   ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:31:1
[00:19:53]    |
[00:19:53] 31 | / simd_u_ty! {
[00:19:53] 32 | |     u16x8: 8, u16, m16x8, u16x8_tests, test_v128 |
[00:19:53] 33 | |     u16, u16, u16, u16, u16, u16, u16, u16 |
[00:19:53] 34 | |     x0, x1, x2, x3, x4, x5, x6, x7 |
[00:19:53] 35 | |     /// A 128-bit vector with 8 `u16` lanes.
[00:19:53]    | |_- in this macro invocation
[00:19:53] 
[00:19:53] error[E0432]: unresolved import `slice::SliceExt`
[00:19:53]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:35:21
[00:19:53]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:35:21
[00:19:53]    |
[00:19:53] 35 |                   use slice::SliceExt;
[00:19:53]    |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:19:53]    | 
[00:19:53]   ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:31:1
[00:19:53]    |
[00:19:53] 31 | / simd_u_ty! {
[00:19:53] 32 | |     u16x8: 8, u16, m16x8, u16x8_tests, test_v128 |
[00:19:53] 33 | |     u16, u16, u16, u16, u16, u16, u16, u16 |
[00:19:53] 34 | |     x0, x1, x2, x3, x4, x5, x6, x7 |
[00:19:53] 35 | |     /// A 128-bit vector with 8 `u16` lanes.
[00:19:53]    | |_- in this macro invocation
[00:19:53] 
[00:19:53] error[E0432]: unresolved import `slice::SliceExt`
[00:19:53]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:53:21
[00:19:53]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:53:21
[00:19:53]    |
[00:19:53] 53 |                   use slice::SliceExt;
[00:19:53]    |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:19:53]    | 
[00:19:53]   ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:31:1
[00:19:53]    |
[00:19:53] 31 | / simd_u_ty! {
[00:19:53] 32 | |     u16x8: 8, u16, m16x8, u16x8_tests, test_v128 |
[00:19:53] 33 | |     u16, u16, u16, u16, u16, u16, u16, u16 |
[00:19:53] 34 | |     x0, x1, x2, x3, x4, x5, x6, x7 |
[00:19:53] 35 | |     /// A 128-bit vector with 8 `u16` lanes.
[00:19:53]    | |_- in this macro invocation
[00:19:53] 
[00:19:53] error[E0432]: unresolved import `slice::SliceExt`
[00:19:53]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:67:21
[00:19:53]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:67:21
[00:19:53]    |
[00:19:53] 67 |                   use slice::SliceExt;
[00:19:53]    |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:19:53]    | 
[00:19:53]   ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:31:1
[00:19:53]    |
[00:19:53] 31 | / simd_u_ty! {
[00:19:53] 32 | |     u16x8: 8, u16, m16x8, u16x8_tests, test_v128 |
[00:19:53] 33 | |     u16, u16, u16, u16, u16, u16, u16, u16 |
[00:19:53] 34 | |     x0, x1, x2, x3, x4, x5, x6, x7 |
[00:19:53] 35 | |     /// A 128-bit vector with 8 `u16` lanes.
[00:19:53]    | |_- in this macro invocation
[00:19:53] 
[00:19:53] error[E0432]: unresolved import `slice::SliceExt`
[00:19:53]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:87:25
[00:19:53]   --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:87:25
[00:19:53]    |
[00:19:53] 87 |                       use slice::SliceExt;
[00:19:53]    |                           ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:19:53]    | 
[00:19:53]   ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:31:1
[00:19:53]    |
[00:19:53] 31 | / simd_u_ty! {
[00:19:53] 32 | |     u16x8: 8, u16, m16x8, u16x8_tests, test_v128 |
[00:19:53] 33 | |     u16, u16, u16, u16, u16, u16, u16, u16 |
[00:19:53] 34 | |     x0, x1, x2, x3, x4, x5, x6, x7 |
[00:19:53] 35 | |     /// A 128-bit vector with 8 `u16` lanes.
[00:19:53]    | |_- in this macro invocation
[00:19:53] 
[00:19:53] error[E0432]: unresolved import `slice::SliceExt`
[00:19:53]    --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:105:21
[00:19:53]    --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:105:21
[00:19:53]     |
[00:19:53] 105 |                   use slice::SliceExt;
[00:19:53]     |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:19:53]     | 
[00:19:53]    ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:31:1
[00:19:53]     |
[00:19:53] 31  | / simd_u_ty! {
[00:19:53] 32  | |     u16x8: 8, u16, m16x8, u16x8_tests, test_v128 |
[00:19:53] 33  | |     u16, u16, u16, u16, u16, u16, u16, u16 |
[00:19:53] 34  | |     x0, x1, x2, x3, x4, x5, x6, x7 |
[00:19:53] 35  | |     /// A 128-bit vector with 8 `u16` lanes.
[00:19:53]     | |_- in this macro invocation
[00:19:53] 
[00:19:53] error[E0432]: unresolved import `slice::SliceExt`
[00:19:53]    --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:120:21
[00:19:53]    --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:120:21
[00:19:53]     |
[00:19:53] 120 |                   use slice::SliceExt;
[00:19:53]     |                       ^^^^^^^^^^^^^^^ no `SliceExt` in `slice`
[00:19:53]     | 
[00:19:53]    ::: src/libcore/../stdsimd/coresimd/ppsv/v128.rs:31:1
[00:19:53]     |
[00:19:53] 31  | / simd_u_ty! {
[00:19:53] 32  | |     u16x8: 8, u16, m16x8, u16x8_tests, test_v128 |
[00:19:53] 33  | |     u16, u16, u16, u16, u16, u16, u16, u16 |
[00:19:53] 34  | |     x0, x1, x2, x3, x4, x5, x6, x7 |
[00:19:53] 35  | |     /// A 128-bit vector with 8 `u16` lanes.
[00:19:53]     | |_- in this macro invocation
[00:19:53] 
[00:19:53] error[E0432]: unresolved import `slice::SliceExt`
[00:19:53]    --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:134:21
[00:19:53]    --> src/libcore/../stdsimd/coresimd/ppsv/api/load_store.rs:134:21
[00:19:53]     |

I'm a bot! I can only do what humans tell me to, so if this was not helpful or you have suggestions for improvements, please ping or otherwise contact @TimNN. (Feature Requests)

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Dylan-DPC commented Dec 3, 2018

Pinging from triage @kenta7777 any updates on this?

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eddyb commented Dec 3, 2018

@oli-obk

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oli-obk commented Dec 3, 2018

The implementation looks good to me.

@kenta7777 can you do another rebase and remove the submodule changes from your second commit?

You can git reset HEAD~1 to undo the second commit and then use git add to only add the changes in the file that you actually wanted to commit.

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bors commented Dec 3, 2018

☔️ The latest upstream changes (presumably #56305) made this pull request unmergeable. Please resolve the merge conflicts.

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kenta7777 commented Dec 9, 2018

@oli-obk I apologize for the delay in replying to you. I'll revise my commits following your advice.

@kenta7777 kenta7777 force-pushed the kenta7777:kenta7777#49937 branch from 712ed93 to 70e85ad Dec 10, 2018

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oli-obk commented Dec 11, 2018

@kenta7777 looks like you got some commits from another PR in here again. This time around a

git fetch origin
git rebase -i origin/master

and removing all commits that are not yours should work

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rust-highfive commented Dec 11, 2018

The job x86_64-gnu-llvm-5.0 of your PR failed on Travis (raw log). Through arcane magic we have determined that the following fragments from the build log may contain information about the problem.

Click to expand the log.
travis_time:end:0a4510a0:start=1544535642361679425,finish=1544535700833933589,duration=58472254164
$ git checkout -qf FETCH_HEAD
travis_fold:end:git.checkout

Encrypted environment variables have been removed for security reasons.
See https://docs.travis-ci.com/user/pull-requests/#Pull-Requests-and-Security-Restrictions
$ export SCCACHE_BUCKET=rust-lang-ci-sccache2
$ export SCCACHE_REGION=us-west-1
Setting environment variables from .travis.yml
$ export IMAGE=x86_64-gnu-llvm-5.0
---
[00:04:09] 
[00:04:09] error: This node does not have a stability attribute
[00:04:09]     --> src/libcore/num/mod.rs:4866:5
[00:04:09]      |
[00:04:09] 4866 | /     pub fn kind(self) -> IntErrorKind {
[00:04:09] 4867 | |         self.kind
[00:04:09]      | |_____^
[00:04:09] 
[00:04:10] error: aborting due to previous error
[00:04:10] 
---
184272 ./obj/build/cache/2018-10-30
153272 ./src/tools/clang
150704 ./obj/build/bootstrap/debug/incremental
135104 ./obj/build/bootstrap/debug/incremental/bootstrap-2pgjvb3usndhe
135100 ./obj/build/bootstrap/debug/incremental/bootstrap-2pgjvb3usndhe/s-f7hpylm673-vezc7z-e1ql6nnu93qh
134556 ./.git/modules/src
115356 ./src/llvm/test/CodeGen
107888 ./obj/build/x86_64-unknown-linux-gnu/stage0/lib/rustlib/x86_64-unknown-linux-gnu/codegen-backends
107416 ./src/tools/lldb
---
travis_time:end:0094e783:start=1544535960749111580,finish=1544535960756219755,duration=7108175
travis_fold:end:after_failure.3
travis_fold:start:after_failure.4
travis_time:start:03d0d0a6
$ ln -s . checkout && for CORE in obj/cores/core.*; do EXE=$(echo $CORE | sed 's|obj/cores/core\.[0-9]*\.!checkout!\(.*\)|\1|;y|!|/|'); if [ -f "$EXE" ]; then printf travis_fold":start:crashlog\n\033[31;1m%s\033[0m\n" "$CORE"; gdb --batch -q -c "$CORE" "$EXE" -iex 'set auto-load off' -iex 'dir src/' -iex 'set sysroot .' -ex bt -ex q; echo travis_fold":"end:crashlog; fi; done || true
travis_fold:end:after_failure.4
travis_fold:start:after_failure.5
travis_time:start:01736f7b
travis_time:start:01736f7b
$ cat ./obj/build/x86_64-unknown-linux-gnu/native/asan/build/lib/asan/clang_rt.asan-dynamic-i386.vers || true
cat: ./obj/build/x86_64-unknown-linux-gnu/native/asan/build/lib/asan/clang_rt.asan-dynamic-i386.vers: No such file or directory
travis_fold:end:after_failure.5
travis_fold:start:after_failure.6
travis_time:start:02f33083
$ dmesg | grep -i kill

I'm a bot! I can only do what humans tell me to, so if this was not helpful or you have suggestions for improvements, please ping or otherwise contact @TimNN. (Feature Requests)

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kenta7777 commented Dec 11, 2018

@oli-obk I'm truly sorry. I had made my branch dirty and Could I remake a new PR related to #49937 ?

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oli-obk commented Dec 11, 2018

Don't worry about it, everything is fixable with git! No need to open a new PR.

Can you show me the output of git remote -v?

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kenta7777 commented Dec 11, 2018

This is an output of git remote -v.

origin	git@github.com:kenta7777/rust.git (fetch)
origin	git@github.com:kenta7777/rust.git (push)
upstream	git@github.com:rust-lang/rust.git (fetch)
upstream	git@github.com:rust-lang/rust.git (push)
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oli-obk commented Dec 11, 2018

Ok, great! So the following commands should get you back to business:

git fetch upstream
git rebase -i upstream/master

Remember to remove any commits that are not yours from the list that shows up

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kenta7777 commented Dec 11, 2018

@oli-obk Thank you for your advice. I rebased following your advice. After that, This output is the first three commit log.

commit dcbd573f5014c28610c0e6e3476d40e5042bc844
Author: kenta7777 <k.hasegw7@gmail.com>
Date:   Mon Dec 10 23:45:33 2018 +0900

    reduce some code repetitions

commit 3499575282b5cda1e98220baae4f6c87e1863926
Merge: 3a31213 c28c287
Author: bors <bors@rust-lang.org>
Date:   Tue Dec 11 14:04:15 2018 +0000

    Auto merge of #56243 - RalfJung:test-deterministic, r=alexcrichton
    
    libtest: Use deterministic HashMap, avoid spawning thread if there is no concurrency
    
    It seems desirable to make a test and bench runner deterministic, which this achieves by using a deterministic hasher. Also, we we only have 1 thread, we don't bother spawning one and just use the main thread.
    
    The motivation for this is to be able to run the test harness in miri, where we can neither access the OS RNG, nor spawn threads.

commit c28c28779c082b6e1d0e7007a222392dc5d6c052
Author: Ralf Jung <post@ralfj.de>
Date:   Tue Dec 11 11:02:23 2018 +0100

    use an enum instead of bool

But, This is the output of git status. My branch and the remote branch is diverged.
Could you give me some advice how I modify this problem?

On branch kenta7777#49937
Your branch and 'origin/kenta7777#49937' have diverged,
and have 621 and 10 different commits each, respectively.
  (use "git pull" to merge the remote branch into yours)
Changes not staged for commit:
  (use "git add <file>..." to update what will be committed)
  (use "git checkout -- <file>..." to discard changes in working directory)

	modified:   src/dlmalloc (new commits)
	modified:   src/doc/book (new commits)
	modified:   src/doc/nomicon (new commits)
	modified:   src/doc/rustc-guide (new commits)
	modified:   src/libcompiler_builtins (new commits)
	modified:   src/liblibc (new commits)
	modified:   src/llvm (new commits)
	modified:   src/stdsimd (new commits)
	modified:   src/tools/cargo (new commits)
	modified:   src/tools/clippy (new commits)
	modified:   src/tools/miri (new commits)
	modified:   src/tools/rls (new commits)
	modified:   src/tools/rustfmt (new commits)

no changes added to commit (use "git add" and/or "git commit -a")

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oli-obk commented Dec 12, 2018

You can now use git push origin --force-with-lease to update this PR

@kenta7777 kenta7777 force-pushed the kenta7777:kenta7777#49937 branch from 36617d4 to dcbd573 Dec 12, 2018

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rust-highfive commented Dec 12, 2018

The job x86_64-gnu-llvm-5.0 of your PR failed on Travis (raw log). Through arcane magic we have determined that the following fragments from the build log may contain information about the problem.

Click to expand the log.
travis_time:end:22dc9a82:start=1544631727719459948,finish=1544631841905408414,duration=114185948466
$ git checkout -qf FETCH_HEAD
travis_fold:end:git.checkout

Encrypted environment variables have been removed for security reasons.
See https://docs.travis-ci.com/user/pull-requests/#Pull-Requests-and-Security-Restrictions
$ export SCCACHE_BUCKET=rust-lang-ci-sccache2
$ export SCCACHE_REGION=us-west-1
Setting environment variables from .travis.yml
$ export IMAGE=x86_64-gnu-llvm-5.0
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---
[00:50:21] 
[00:50:21] ---- [ui] ui/lint/type-overflow.rs stdout ----
[00:50:21] diff of stderr:
[00:50:21] 
[00:50:21] 12 LL |     let fail = 0b1000_0001i8; //~WARNING literal out of range for i8
[00:50:21] 13    |                ^^^^^^^^^^^^^ help: consider using `u8` instead: `0b1000_0001u8`
[00:50:21] 14    |
[00:50:21] -    = note: the literal `0b1000_0001i8` (decimal `129`) does not fit into an `i8` and will become `-127i8`
[00:50:21] +    = note: the literal `0b1000_0001i8` (decimal `129`) does not fit into an `i8` and will become `340282366920938463463374607431768211329i8`
[00:50:21] 16 
[00:50:21] 17 warning: literal out of range for i64
[00:50:21] 
[00:50:21] 
[00:50:21] 20 LL |     let fail = 0x8000_0000_0000_0000i64; //~WARNING literal out of range for i64
[00:50:21] 21    |                ^^^^^^^^^^^^^^^^^^^^^^^^ help: consider using `u64` instead: `0x8000_0000_0000_0000u64`
[00:50:21] 22    |
[00:50:21] -    = note: the literal `0x8000_0000_0000_0000i64` (decimal `9223372036854775808`) does not fit into an `i64` and will become `-9223372036854775808i64`
[00:50:21] +    = note: the literal `0x8000_0000_0000_0000i64` (decimal `9223372036854775808`) does not fit into an `i64` and will become `340282366920938463454151235394913435648i64`
[00:50:21] 24 
[00:50:21] 25 warning: literal out of range for u32
[00:50:21] 
[00:50:21] 
[00:50:21] 36 LL |     let fail: i128 = 0x8000_0000_0000_0000_0000_0000_0000_0000;
[00:50:21] 38    |
[00:50:21] 38    |
[00:50:21] -    = note: the literal `0x8000_0000_0000_0000_0000_0000_0000_0000` (decimal `170141183460469231731687303715884105728`) does not fit into an `i128` and will become `-170141183460469231731687303715884105728i128`
[00:50:21] +    = note: the literal `0x8000_0000_0000_0000_0000_0000_0000_0000` (decimal `170141183460469231731687303715884105728`) does not fit into an `i128` and will become `170141183460469231731687303715884105728i128`
[00:50:21] 40    = help: consider using `u128` instead
[00:50:21] 41 
[00:50:21] 42 warning: literal out of range for i32
[00:50:21] 
[00:50:21] 45 LL |     let fail = 0x8FFF_FFFF_FFFF_FFFE; //~WARNING literal out of range for i32
[00:50:21] 47    |
[00:50:21] 47    |
[00:50:21] -    = note: the literal `0x8FFF_FFFF_FFFF_FFFE` (decimal `10376293541461622782`) does not fit into an `i32` and will become `-2i32`
[00:50:21] +    = note: the literal `0x8FFF_FFFF_FFFF_FFFE` (decimal `10376293541461622782`) does not fit into an `i32` and will become `340282366920938463463374607431768211454i32`
[00:50:21] 49    = help: consider using `i128` instead
[00:50:21] 50 
[00:50:21] 51 warning: literal out of range for i8
[00:50:21] 
[00:50:21] 54 LL |     let fail = -0b1111_1111i8; //~WARNING literal out of range for i8
[00:50:21] 55    |                 ^^^^^^^^^^^^^ help: consider using `i16` instead: `0b1111_1111i16`
[00:50:21] 56    |
[00:50:21] -    = note: the literal `0b1111_1111i8` (decimal `255`) does not fit into an `i8` and will become `-1i8`
[00:50:21] +    = note: the literal `0b1111_1111i8` (decimal `255`) does not fit into an `i8` and will become `340282366920938463463374607431768211455i8`
[00:50:21] 59 
[00:50:21] 
[00:50:21] 
[00:50:21] The actual stderr differed from the expected stderr.
[00:50:21] The actual stderr differed from the expected stderr.
[00:50:21] Actual stderr saved to /checkout/obj/build/x86_64-unknown-linux-gnu/test/ui/lint/type-overflow/type-overflow.stderr
[00:50:21] To update references, rerun the tests and pass the `--bless` flag
[00:50:21] To only update this specific test, also pass `--test-args lint/type-overflow.rs`
[00:50:21] error: 1 errors occurred comparing output.
[00:50:21] status: exit code: 0
[00:50:21] status: exit code: 0
[00:50:21] command: "/checkout/obj/build/x86_64-unknown-linux-gnu/stage2/bin/rustc" "/checkout/src/test/ui/lint/type-overflow.rs" "--target=x86_64-unknown-linux-gnu" "--error-format" "json" "-Zui-testing" "-C" "prefer-dynamic" "-o" "/checkout/obj/build/x86_64-unknown-linux-gnu/test/ui/lint/type-overflow/a" "-Crpath" "-O" "-Zunstable-options" "-Lnative=/checkout/obj/build/x86_64-unknown-linux-gnu/native/rust-test-helpers" "-L" "/checkout/obj/build/x86_64-unknown-linux-gnu/test/ui/lint/type-overflow/auxiliary" "-A" "unused"
[00:50:21] ------------------------------------------
[00:50:21] 
[00:50:21] ------------------------------------------
[00:50:21] stderr:
[00:50:21] stderr:
[00:50:21] ------------------------------------------
[00:50:21] {"message":"literal out of range for i8","code":{"code":"overflowing_literals","explanation":null},"level":"warning","spans":[{"file_name":"/checkout/src/test/ui/lint/type-overflow.rs","byte_start":512,"byte_end":517,"line_start":14,"line_end":14,"column_start":17,"column_end":22,"is_primary":true,"text":[{"text":"    let error = 255i8; //~WARNING literal out of range for i8","highlight_start":17,"highlight_end":22}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[{"message":"#[warn(overflowing_literals)] on by default","code":null,"level":"note","spans":[],"children":[],"rendered":null}],"rendered":"warning: literal out of range for i8\n  --> /checkout/src/test/ui/lint/type-overflow.rs:14:17\n   |\nLL |     let error = 255i8; //~WARNING literal out of range for i8\n   |                 ^^^^^\n   |\n   = note: #[warn(overflowing_literals)] on by default\n\n"}
[00:50:21] {"message":"literal out of range for i8","code":{"code":"overflowing_literals","explanation":null},"level":"warning","spans":[{"file_name":"/checkout/src/test/ui/lintl":"warning","spans":[{"file_name":"/checkout/src/test/ui/lint/type-overflow.rs","byte_start":747,"byte_end":771,"line_start":21,"line_end":21,"column_start":16,"column_end":40,"is_primary":true,"text":[{"text":"    let fail = 0x8000_0000_0000_0000i64; //~WARNING literal out of range for i64","highlight_start":16,"highlight_end":40}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[{"message":"the literal `0x8000_0000_0000_0000i64` (decimal `9223372036854775808`) does not fit into an `i64` and will become `340282366920938463454151235394913435648i64`","code":null,"level":"note","spans":[],"children":[],"rendered":null},{"message":"consider using `u64` instead","code":null,"level":"help","spans":[{"file_name":"/checkout/src/test/ui/lint/type-overflow.rs","byte_start":747,"byte_end":771,"line_start":21,"line_end":21,"column_start":16,"column_end":40,"is_primary":true,"text":[{"text":"    let fail = 0x8000_0000_0000_0000i64; //~WARNING literal out of range for i64","highlight_start":16,"highlight_end":40}],"label":null,"suggested_replacement":"0x8000_0000_0000_0000u64","suggestion_applicability":"MachineApplicable","expansion":null}],"children":[],"rendered":null}],"rendered":"warning: literal out of range for i64\n  --> /checkout/src/test/ui/lint/type-overflow.rs:21:16\n   |\nLL |     let fail = 0x8000_0000_0000_0000i64; //~WARNING literal out of range for i64\n   |                ^^^^^^^^^^^^^^^^^^^^^^^^ help: consider using `u64` instead: `0x8000_0000_0000_0000u64`\n   |\n   = note: the literal `0x8000_0000_0000_0000i64` (decimal `9223372036854775808`) does not fit into an `i64` and will become `340282366920938463454151235394913435648i64`\n\n"}
[00:50:21] {"message":"literal out of range for u32","code":{"code":"overflowing_literals","explanation":null},"level":"warning","spans":[{"file_name":"/checkout/src/test/ui/lint/type-overflow.rs","byte_start":829,"byte_end":845,"line_start":23,"line_end":23,"column_start":16,"column_end":32,"is_primary":true,"text":[{"text":"    let fail = 0x1_FFFF_FFFFu32; //~WARNING literal out of range for u32","highlight_start":16,"highlight_end":32}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[{"message":"the literal `0x1_FFFF_FFFFu32` (decimal `8589934591`) does not fit into an `u32` and will become `4294967295u32`","code":null,"level":"note","spans":[],"children":[],"rendered":null},{"message":"consider using `u64` instead","code":null,"level":"help","spans":[{"file_name":"/checkout/src/test/ui/lint/type-overflow.rs","byte_start":829,"byte_end":845,"line_start":23,"line_end":23,"column_start":16,"column_end":32,"is_primary":true,"text":[{"text":"    let fail = 0x1_FFFF_FFFFu32; //~WARNING literal out of range for u32","highlight_start":16,"highlight_end":32}],"label":null,"suggested_replacement":"0x1_FFFF_FFFFu64","suggestion_applicability":"MachineApplicable","expansion":null}],"children":[],"rendered":null}],"rendered":"warning: literal out of range for u32\n  --> /checkout/src/test/ui/lint/type-overflow.rs:23:16\n   |\nLL |     let fail = 0x1_FFFF_FFFFu32; //~WARNING literal out of range for u32\n   |                ^^^^^^^^^^^^^^^^ help: consider using `u64` instead: `0x1_FFFF_FFFFu64`\n   |\n   = note: the literal `0x1_FFFF_FFFFu32` (decimal `8589934591`) does not fit into an `u32` and will become `4294967295u32`\n\n"}
[00:50:21] {"message":"literal out of range for i128","code":{"code":"overflowing_literals","explanation":null},"level":"warning","spans":[{"file_name":"/checkout/src/test/ui/lint/type-overflow.rs","byte_start":909,"byte_end":950,"line_start":25,"line_end":25,"column_start":22,"column_end":63,"is_primary":true,"text":[{"text":"    let fail: i128 = 0x8000_0000_0000_0000_0000_0000_0000_0000;","highlight_start":22,"highlight_end":63}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[{"message":"the literal `0x8000_0000_0000_0000_0000_0000_0000_0000` (decimal `170141183460469231731687303715884105728`) does not fit into an `i128` and will become `170141183460469231731687303715884105728i128`","code":null,"level":"note","spans":[],"children":[],"rendered":null},{"message":"consider using `u128` instead","code":null,"level":"help","spans":[],"children":[],"rendered":null}],"rendered":"warning: literal out of range for i128\n  --> /checkout/src/test/ui/lint/type-overflow.rs:25:22\n   |\nLL |     let fail: i128 = 0x8000_0000_0000_0000_0000_0000_0000_0000;\n   |                      ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n   |\n   = note: the literal `0x8000_0000_0000_0000_0000_0000_0000_0000` (decimal `170141183460469231731687303715884105728`) does not fit into an `i128` and will become `170141183460469231731687303715884105728i128`\n   = help: consider using `u128` instead\n\n"}
[00:50:21] {"message":"literal out of range for i32","code":{"code":"over11i8; //~WARNING literal out of range for i8","highlight_start":17,"highlight_end":30}],"label":null,"suggested_replacement":null,"suggestion_applicability":null,"expansion":null}],"children":[{"message":"the literal `0b1111_1111i8` (decimal `255`) does not fit into an `i8` and will become `340282366920938463463374607431768211455i8`","code":null,"level":"note","spans":[],"children":[],"rendered":null},{"message":"consider using `i16` instead","code":null,"level":"help","spans":[{"file_name":"/checkout/src/test/ui/lint/type-overflow.rs","byte_start":1095,"byte_end":1108,"line_start":30,"line_end":30,"column_start":17,"column_end":30,"is_primary":true,"text":[{"text":"    let fail = -0b1111_1111i8; //~WARNING literal out of range for i8","highlight_start":17,"highlight_end":30}],"label":null,"suggested_replacement":"0b1111_1111i16","suggestion_applicability":"MachineApplicable","expansion":null}],"children":[],"rendered":null}],"rendered":"warning: literal out of range for i8\n  --> /checkout/src/test/ui/lint/type-overflow.rs:30:17\n   |\nLL |     let fail = -0b1111_1111i8; //~WARNING literal out of range for i8\n   |                 ^^^^^^^^^^^^^ help: consider using `i16` instead: `0b1111_1111i16`\n   |\n   = note: the literal `0b1111_1111i8` (decimal `255`) does not fit into an `i8` and will become `340282366920938463463374607431768211455i8`\n\n"}
[00:50:21] ------------------------------------------
[00:50:21] 
[00:50:21] thread '[ui] ui/lint/type-overflow.rs' panicked at 'explicit panic', src/tools/compiletest/src/runtest.rs:3252:9
[00:50:21] note: Run with `RUST_BACKTRACE=1` for a backtrace.
---
[00:50:21] 
[00:50:21] thread 'main' panicked at 'Some tests failed', src/tools/compiletest/src/main.rs:503:22
[00:50:21] 
[00:50:21] 
[00:50:21] command did not execute successfully: "/checkout/obj/build/x86_64-unknown-linux-gnu/stage0-tools-bin/compiletest" "--compile-lib-path" "/checkout/obj/build/x86_64-unknown-linux-gnu/stage2/lib" "--run-lib-path" "/checkout/obj/build/x86_64-unknown-linux-gnu/stage2/lib/rustlib/x86_64-unknown-linux-gnu/lib" "--rustc-path" "/checkout/obj/build/x86_64-unknown-linux-gnu/stage2/bin/rustc" "--src-base" "/checkout/src/test/ui" "--build-base" "/checkout/obj/build/x86_64-unknown-linux-gnu/test/ui" "--stage-id" "stage2-x86_64-unknown-linux-gnu" "--mode" "ui" "--target" "x86_64-unknown-linux-gnu" "--host" "x86_64-unknown-linux-gnu" "--llvm-filecheck" "/usr/lib/llvm-5.0/bin/FileCheck" "--host-rustcflags" "-Crpath -O -Zunstable-options  -Lnative=/checkout/obj/build/x86_64-unknown-linux-gnu/native/rust-test-helpers" "--target-rustcflags" "-Crpath -O -Zunstable-options  -Lnative=/checkout/obj/build/x86_64-unknown-linux-gnu/native/rust-test-helpers" "--docck-python" "/usr/bin/python2.7" "--lldb-python" "/usr/bin/python2.7" "--gdb" "/usr/bin/gdb" "--quiet" "--llvm-version" "5.0.0\n" "--system-llvm" "--cc" "" "--cxx" "" "--cflags" "" "--llvm-components" "" "--llvm-cxxflags" "" "--adb-path" "adb" "--adb-test-dir" "/data/tmp/work" "--android-cross-path" "" "--color" "always"

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