From e7c1f1235d2a2fb70385799ec35f7f5644cb85fb Mon Sep 17 00:00:00 2001 From: Tsukasa OI Date: Fri, 21 Mar 2025 03:48:43 +0000 Subject: [PATCH 1/3] reorder all RISC-V features for maintenance All RISC-V Features are reordered for better maintainability. The author has a plan to add many RISC-V ratified extensions (mainly discoverable from Linux) and this is a part of preparation. Sections are divided as follows: * Base ISAs * "I"-related * Extensions formerly a part of the base "I" extension but divided later (now all of them are ratified). * Other user-mode extensions "Zi*". * "M"-related (currently "M" only) * "A"-related "A", "Za*" and "Ztso" which is named differently but absolutely related to memory operations. * Base FP extensions * Base FP extensions using integer registers * "C"-related (currently "C" only) * "B"-related (except cryptography-related "Zbk*") * Scalar cryptography extensions (including "Zbk*") * Base Vector extensions (currently "V" only) * Ratified privileged extensions * Non-extensions and non-ratified extensions which is *not* going to be ratified, at least in the draft form The last section needs some explanation. "S" is not an extension (although some buggy implementations such as QEMU up to 7.0 emitted this character as well as "U" as an extension) and the DeviceTree parser in the Linux kernel explicitly workarounds this issue. There's no plan for ratification of the single-letter "J" extension (there's a room for redefinition like the "B" extension but unlikely). Instead, pointer masking extensions including "Supm" is one of the results of the task group discussing J extension*s*. There's also an instruction in the "Zfa" extension which accelerates FP-to-int conversion matching JavaScript semantics. "P" is being actively discussed (and will result in a single-letter "P" extension and various "Zp*" extensions) but it seems there needs some time until ratification. And there's one Rust-specific issue: Rust implements Packed-SIMD intrinsics based on an early draft of the "P" extension and they are *very unlikely* kept as-is. For instance, `add16` does not follow standard RISC-V instruction naming (ADD16 is the name from the Andes' proposal) and going to be renamed. Before moving "P" to above, we have to clearly understand what the final "P" extension will be and resolve existing intrinsics. --- crates/std_detect/src/detect/arch/riscv.rs | 110 +++++++++++---------- 1 file changed, 59 insertions(+), 51 deletions(-) diff --git a/crates/std_detect/src/detect/arch/riscv.rs b/crates/std_detect/src/detect/arch/riscv.rs index 7ecda95d07..2d9505611e 100644 --- a/crates/std_detect/src/detect/arch/riscv.rs +++ b/crates/std_detect/src/detect/arch/riscv.rs @@ -89,22 +89,20 @@ features! { /// /// [ISA manual]: https://github.com/riscv/riscv-isa-manual/ #[stable(feature = "riscv_ratified", since = "1.78.0")] + @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv32i: "rv32i"; without cfg check: true; /// RV32I Base Integer Instruction Set - @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zifencei: "zifencei"; - without cfg check: true; - /// "Zifencei" Instruction-Fetch Fence - @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zihintpause: "zihintpause"; + @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv32e: "rv32e"; without cfg check: true; - /// "Zihintpause" Pause Hint + /// RV32E Base Integer Instruction Set @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv64i: "rv64i"; without cfg check: true; /// RV64I Base Integer Instruction Set - @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] m: "m"; - /// "M" Standard Extension for Integer Multiplication and Division - @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] a: "a"; - /// "A" Standard Extension for Atomic Instructions + @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv128i: "rv128i"; + without cfg check: true; + /// RV128I Base Integer Instruction Set + @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zicsr: "zicsr"; without cfg check: true; /// "Zicsr", Control and Status Register (CSR) Instructions @@ -114,6 +112,26 @@ features! { @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zihpm: "zihpm"; without cfg check: true; /// "Zihpm", Standard Extension for Hardware Performance Counters + + @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zifencei: "zifencei"; + without cfg check: true; + /// "Zifencei" Instruction-Fetch Fence + @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zihintpause: "zihintpause"; + without cfg check: true; + /// "Zihintpause" Pause Hint + + @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] m: "m"; + /// "M" Standard Extension for Integer Multiplication and Division + + @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] a: "a"; + /// "A" Standard Extension for Atomic Instructions + @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zam: "zam"; + without cfg check: true; + /// "Zam" Standard Extension for Misaligned Atomics + @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] ztso: "ztso"; + without cfg check: true; + /// "Ztso" Standard Extension for Total Store Ordering + @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] f: "f"; /// "F" Standard Extension for Single-Precision Floating-Point @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] d: "d"; @@ -121,8 +139,10 @@ features! { @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] q: "q"; without cfg check: true; /// "Q" Standard Extension for Quad-Precision Floating-Point - @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] c: "c"; - /// "C" Standard Extension for Compressed Instructions + @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfh: "zfh"; + /// "Zfh" Standard Extension for 16-Bit Half-Precision Floating-Point + @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfhmin: "zfhmin"; + /// "Zfhmin" Standard Extension for Minimal Half-Precision Floating-Point Support @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfinx: "zfinx"; /// "Zfinx" Standard Extension for Single-Precision Floating-Point in Integer Registers @@ -132,47 +152,9 @@ features! { /// "Zhinx" Standard Extension for Half-Precision Floating-Point in Integer Registers @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zhinxmin: "zhinxmin"; /// "Zhinxmin" Standard Extension for Minimal Half-Precision Floating-Point in Integer Registers - @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] ztso: "ztso"; - without cfg check: true; - /// "Ztso" Standard Extension for Total Store Ordering - - @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv32e: "rv32e"; - without cfg check: true; - /// RV32E Base Integer Instruction Set - @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv128i: "rv128i"; - without cfg check: true; - /// RV128I Base Integer Instruction Set - @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfh: "zfh"; - /// "Zfh" Standard Extension for 16-Bit Half-Precision Floating-Point - @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfhmin: "zfhmin"; - /// "Zfhmin" Standard Extension for Minimal Half-Precision Floating-Point Support - @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] j: "j"; - without cfg check: true; - /// "J" Standard Extension for Dynamically Translated Languages - @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] p: "p"; - without cfg check: true; - /// "P" Standard Extension for Packed-SIMD Instructions - @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] v: "v"; - /// "V" Standard Extension for Vector Operations - @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zam: "zam"; - without cfg check: true; - /// "Zam" Standard Extension for Misaligned Atomics - @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] s: "s"; - without cfg check: true; - /// Supervisor-Level ISA - @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] svnapot: "svnapot"; - without cfg check: true; - /// "Svnapot" Standard Extension for NAPOT Translation Contiguity - @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] svpbmt: "svpbmt"; - without cfg check: true; - /// "Svpbmt" Standard Extension for Page-Based Memory Types - @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] svinval: "svinval"; - without cfg check: true; - /// "Svinval" Standard Extension for Fine-Grained Address-Translation Cache Invalidation - @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] h: "h"; - without cfg check: true; - /// Hypervisor Extension + @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] c: "c"; + /// "C" Standard Extension for Compressed Instructions @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zba: "zba"; /// "Zba" Standard Extension for Address Generation Instructions @@ -209,4 +191,30 @@ features! { /// "Zk" Standard Extension for Standard scalar cryptography extension @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zkt: "zkt"; /// "Zkt" Standard Extension for Data Independent Execution Latency + + @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] v: "v"; + /// "V" Standard Extension for Vector Operations + + @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] svnapot: "svnapot"; + without cfg check: true; + /// "Svnapot" Standard Extension for NAPOT Translation Contiguity + @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] svpbmt: "svpbmt"; + without cfg check: true; + /// "Svpbmt" Standard Extension for Page-Based Memory Types + @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] svinval: "svinval"; + without cfg check: true; + /// "Svinval" Standard Extension for Fine-Grained Address-Translation Cache Invalidation + @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] h: "h"; + without cfg check: true; + /// Hypervisor Extension + + @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] s: "s"; + without cfg check: true; + /// Supervisor-Level ISA + @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] j: "j"; + without cfg check: true; + /// "J" Standard Extension for Dynamically Translated Languages + @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] p: "p"; + without cfg check: true; + /// "P" Standard Extension for Packed-SIMD Instructions } From 8f28efe597bae8023d75481795e14519287702a3 Mon Sep 17 00:00:00 2001 From: Tsukasa OI Date: Fri, 21 Mar 2025 03:48:43 +0000 Subject: [PATCH 2/3] reword RISC-V feature documentation As the version 20240411 of the RISC-V ISA Manual changed wording to describe many of the standard extensions, this commit largely follows this scheme in general. In many cases, words "Standard Extension" are replaced with "Extension" following the latest ratified ISA Manual. Some RISC-V extensions had tentative summary but it also fixes that (e.g. "Zihintpause"). Following extensions are described in parity with corresponding extensions using floating-point registers: * "Zfinx" Extension for Single-Precision Floating-Point in Integer Registers * "Zdinx" Extension for Double-Precision Floating-Point in Integer Registers * "Zhinx" Extension for Half-Precision Floating-Point in Integer Registers * "Zhinxmin" Extension for Minimal Half-Precision Floating-Point in Integer Registers Following extensions are named against the ISA Manual naming but considered inconsistency inside the ISA manual: * "Zfhmin" Extension for Minimal Half-Precision Floating-Point ISA Manual: "Zfhmin" Standard Extension for Minimal Half-Precision Floating-Point * "V" Extension for Vector Operations ISA Manual: "V" Standard Extension for Vector Operations Following extension is removed from the latest ratified ISA Manual but named like others: * "Zam" Extension for Misaligned Atomics "Zb*" extensions are described like "Extension for ..." using partial summary per extension (including cryptography-related "Zbk*" extensions). "Zk*" extensions are described like "Cryptography Extension for ..." using partial summary per extension (e.g. 'Zkne - NIST Suite: AES Encryption' in the ISA Manual to '"Zkne" Cryptography Extension for NIST Suite: AES Encryption') except following extensions: * "Zkr" Entropy Source Extension Following the general rule will make the description redundant. * "Zk" Cryptography Extension for Standard scalar cryptography The last word "extension" is removed as seemed redundant. Link: (ISA Specifications, Version 20240411; published in May 2024) --- crates/std_detect/src/detect/arch/riscv.rs | 86 +++++++++++----------- 1 file changed, 43 insertions(+), 43 deletions(-) diff --git a/crates/std_detect/src/detect/arch/riscv.rs b/crates/std_detect/src/detect/arch/riscv.rs index 2d9505611e..dd3f0522dd 100644 --- a/crates/std_detect/src/detect/arch/riscv.rs +++ b/crates/std_detect/src/detect/arch/riscv.rs @@ -105,116 +105,116 @@ features! { @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zicsr: "zicsr"; without cfg check: true; - /// "Zicsr", Control and Status Register (CSR) Instructions + /// "Zicsr" Extension for Control and Status Register (CSR) Instructions @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zicntr: "zicntr"; without cfg check: true; - /// "Zicntr", Standard Extension for Base Counters and Timers + /// "Zicntr" Extension for Base Counters and Timers @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zihpm: "zihpm"; without cfg check: true; - /// "Zihpm", Standard Extension for Hardware Performance Counters + /// "Zihpm" Extension for Hardware Performance Counters @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zifencei: "zifencei"; without cfg check: true; - /// "Zifencei" Instruction-Fetch Fence + /// "Zifencei" Extension for Instruction-Fetch Fence @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zihintpause: "zihintpause"; without cfg check: true; - /// "Zihintpause" Pause Hint + /// "Zihintpause" Extension for Pause Hint @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] m: "m"; - /// "M" Standard Extension for Integer Multiplication and Division + /// "M" Extension for Integer Multiplication and Division @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] a: "a"; - /// "A" Standard Extension for Atomic Instructions + /// "A" Extension for Atomic Instructions @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zam: "zam"; without cfg check: true; - /// "Zam" Standard Extension for Misaligned Atomics + /// "Zam" Extension for Misaligned Atomics @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] ztso: "ztso"; without cfg check: true; - /// "Ztso" Standard Extension for Total Store Ordering + /// "Ztso" Extension for Total Store Ordering @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] f: "f"; - /// "F" Standard Extension for Single-Precision Floating-Point + /// "F" Extension for Single-Precision Floating-Point @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] d: "d"; - /// "D" Standard Extension for Double-Precision Floating-Point + /// "D" Extension for Double-Precision Floating-Point @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] q: "q"; without cfg check: true; - /// "Q" Standard Extension for Quad-Precision Floating-Point + /// "Q" Extension for Quad-Precision Floating-Point @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfh: "zfh"; - /// "Zfh" Standard Extension for 16-Bit Half-Precision Floating-Point + /// "Zfh" Extension for Half-Precision Floating-Point @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfhmin: "zfhmin"; - /// "Zfhmin" Standard Extension for Minimal Half-Precision Floating-Point Support + /// "Zfhmin" Extension for Minimal Half-Precision Floating-Point @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfinx: "zfinx"; - /// "Zfinx" Standard Extension for Single-Precision Floating-Point in Integer Registers + /// "Zfinx" Extension for Single-Precision Floating-Point in Integer Registers @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zdinx: "zdinx"; - /// "Zdinx" Standard Extension for Double-Precision Floating-Point in Integer Registers + /// "Zdinx" Extension for Double-Precision Floating-Point in Integer Registers @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zhinx: "zhinx"; - /// "Zhinx" Standard Extension for Half-Precision Floating-Point in Integer Registers + /// "Zhinx" Extension for Half-Precision Floating-Point in Integer Registers @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zhinxmin: "zhinxmin"; - /// "Zhinxmin" Standard Extension for Minimal Half-Precision Floating-Point in Integer Registers + /// "Zhinxmin" Extension for Minimal Half-Precision Floating-Point in Integer Registers @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] c: "c"; - /// "C" Standard Extension for Compressed Instructions + /// "C" Extension for Compressed Instructions @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zba: "zba"; - /// "Zba" Standard Extension for Address Generation Instructions + /// "Zba" Extension for Address Generation @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zbb: "zbb"; - /// "Zbb" Standard Extension for Basic Bit-Manipulation + /// "Zbb" Extension for Basic Bit-Manipulation @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zbc: "zbc"; - /// "Zbc" Standard Extension for Carry-less Multiplication + /// "Zbc" Extension for Carry-less Multiplication @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zbs: "zbs"; - /// "Zbs" Standard Extension for Single-Bit instructions + /// "Zbs" Extension for Single-Bit instructions @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zbkb: "zbkb"; - /// "Zbkb" Standard Extension for Bitmanip instructions for Cryptography + /// "Zbkb" Extension for Bit-manipulation for Cryptography @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zbkc: "zbkc"; - /// "Zbkc" Standard Extension for Carry-less multiply instructions + /// "Zbkc" Extension for Carry-less multiplication for Cryptography @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zbkx: "zbkx"; - /// "Zbkx" Standard Extension for Crossbar permutation instructions + /// "Zbkx" Extension for Crossbar permutations @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zknd: "zknd"; - /// "Zknd" Standard Extension for NIST Suite: AES Decryption + /// "Zknd" Cryptography Extension for NIST Suite: AES Decryption @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zkne: "zkne"; - /// "Zkne" Standard Extension for NIST Suite: AES Encryption + /// "Zkne" Cryptography Extension for NIST Suite: AES Encryption @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zknh: "zknh"; - /// "Zknh" Standard Extension for NIST Suite: Hash Function Instructions + /// "Zknh" Cryptography Extension for NIST Suite: Hash Function Instructions @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zksed: "zksed"; - /// "Zksed" Standard Extension for ShangMi Suite: SM4 Block Cipher Instructions + /// "Zksed" Cryptography Extension for ShangMi Suite: SM4 Block Cipher Instructions @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zksh: "zksh"; - /// "Zksh" Standard Extension for ShangMi Suite: SM3 Hash Function Instructions + /// "Zksh" Cryptography Extension for ShangMi Suite: SM3 Hash Function Instructions @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zkr: "zkr"; - /// "Zkr" Standard Extension for Entropy Source Extension + /// "Zkr" Entropy Source Extension @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zkn: "zkn"; - /// "Zkn" Standard Extension for NIST Algorithm Suite + /// "Zkn" Cryptography Extension for NIST Algorithm Suite @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zks: "zks"; - /// "Zks" Standard Extension for ShangMi Algorithm Suite + /// "Zks" Cryptography Extension for ShangMi Algorithm Suite @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zk: "zk"; - /// "Zk" Standard Extension for Standard scalar cryptography extension + /// "Zk" Cryptography Extension for Standard scalar cryptography @FEATURE: #[stable(feature = "riscv_ratified", since = "1.78.0")] zkt: "zkt"; - /// "Zkt" Standard Extension for Data Independent Execution Latency + /// "Zkt" Cryptography Extension for Data Independent Execution Latency @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] v: "v"; - /// "V" Standard Extension for Vector Operations + /// "V" Extension for Vector Operations @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] svnapot: "svnapot"; without cfg check: true; - /// "Svnapot" Standard Extension for NAPOT Translation Contiguity + /// "Svnapot" Extension for NAPOT Translation Contiguity @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] svpbmt: "svpbmt"; without cfg check: true; - /// "Svpbmt" Standard Extension for Page-Based Memory Types + /// "Svpbmt" Extension for Page-Based Memory Types @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] svinval: "svinval"; without cfg check: true; - /// "Svinval" Standard Extension for Fine-Grained Address-Translation Cache Invalidation + /// "Svinval" Extension for Fine-Grained Address-Translation Cache Invalidation @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] h: "h"; without cfg check: true; - /// Hypervisor Extension + /// "H" Extension for Hypervisor Support @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] s: "s"; without cfg check: true; /// Supervisor-Level ISA @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] j: "j"; without cfg check: true; - /// "J" Standard Extension for Dynamically Translated Languages + /// "J" Extension for Dynamically Translated Languages @FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] p: "p"; without cfg check: true; - /// "P" Standard Extension for Packed-SIMD Instructions + /// "P" Extension for Packed-SIMD Instructions } From dcf4f02e4e7697c8027ad69c0f94ca8239ee4c6e Mon Sep 17 00:00:00 2001 From: Tsukasa OI Date: Fri, 21 Mar 2025 12:10:41 +0000 Subject: [PATCH 3/3] tentatively remove the "B" RISC-V extension from the documentation Although the "B" extension is redefined and ratified, keeping this in the documentation as-is have two issues: * "B" extension is not added to `riscv.rs` yet (to be added later). * "B" extension is ratified as a combination of "Zba", "Zbb" and "Zbs" extensions and "Zbc" is *not* a part of "B" itself (despite that it is listed under "B"), which makes the documentation misleading. This commit tentatively removes the reference to the "B" extension and replaced with "Bit Manipulation Extensions" without an extension name. --- crates/std_detect/src/detect/arch/riscv.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/crates/std_detect/src/detect/arch/riscv.rs b/crates/std_detect/src/detect/arch/riscv.rs index dd3f0522dd..2368131fea 100644 --- a/crates/std_detect/src/detect/arch/riscv.rs +++ b/crates/std_detect/src/detect/arch/riscv.rs @@ -28,7 +28,7 @@ features! { /// * RV32I: `"rv32i"` /// * RV64I: `"rv64i"` /// * A: `"a"` - /// * B: `"b"` + /// * Bit-Manipulation Extensions: /// * Zba: `"zba"` /// * Zbb: `"zbb"` /// * Zbc: `"zbc"`