From a2621f328207b55f448d67c34f76aa4cca56f3eb Mon Sep 17 00:00:00 2001
From: Woshiluo Luo <woshiluo.luo@outlook.com>
Date: Wed, 28 May 2025 23:54:50 +0800
Subject: [PATCH] docs: uart_sifive

Signed-off-by: Woshiluo Luo <woshiluo.luo@outlook.com>
---
 uart_sifive/src/uart.rs | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/uart_sifive/src/uart.rs b/uart_sifive/src/uart.rs
index 22bf8b9..ad34b92 100644
--- a/uart_sifive/src/uart.rs
+++ b/uart_sifive/src/uart.rs
@@ -85,97 +85,118 @@ impl MmioUartSifive {
         self.reg().rx.read()
     }
 
+    /// Read Tx Status
     #[inline]
     pub fn read_tx(&self) -> u32 {
         self.reg().tx.read()
     }
 
+    /// Write Tx FIFO
     #[inline]
     pub fn write_tx(&self, value: u32) {
         unsafe { self.reg().tx.write(value) }
     }
 
+    /// Read RxCtrl
     #[inline]
     pub fn read_rxctrl(&self) -> u32 {
         self.reg().rxctrl.read()
     }
 
+    /// Write RxCtrl
     #[inline]
     pub fn write_rxctrl(&self, value: u32) {
         unsafe { self.reg().rxctrl.write(value) }
     }
 
+    /// Read TxCtrl
     #[inline]
     pub fn read_txctrl(&self) -> u32 {
         self.reg().txctrl.read()
     }
 
+    /// Write TxCtrl
     #[inline]
     pub fn write_txctrl(&self, value: u32) {
         unsafe { self.reg().txctrl.write(value) }
     }
 
+    /// Read ip register
     #[inline]
     pub fn read_ip(&self) -> InterruptRegister {
         InterruptRegister::from_bits_truncate(self.reg().ip.read())
     }
 
+    /// Read ie register
     #[inline]
     pub fn read_ie(&self) -> InterruptRegister {
         InterruptRegister::from_bits_truncate(self.reg().ie.read())
     }
 
+    /// Write ie register
     #[inline]
     pub fn write_ie(&self, value: u32) {
         unsafe { self.reg().ie.write(value) }
     }
 
+    /// Read div register
     #[inline]
     pub fn read_div(&self) -> u32 {
         self.reg().div.read()
     }
 
+    /// Write div register
     #[inline]
     pub fn write_div(&self, value: u32) {
         unsafe { self.reg().div.write(value) }
     }
 
+    /// Check if tx FIFO is full
     pub fn is_tx_fifo_full(&self) -> bool {
         TxData::from_bits_truncate(self.read_tx()).contains(TxData::FULL)
     }
 
+    /// Check if read interrupt has been enable
     pub fn is_read_interrupt_enabled(&self) -> bool {
         self.read_ie().contains(InterruptRegister::RXWM)
     }
 
+    /// Check if write interrupt has been enable
     pub fn is_write_interrupt_enabled(&self) -> bool {
         self.read_ie().contains(InterruptRegister::TXWM)
     }
 
+    /// Enable write
     pub fn enable_write(&self) {
         self.write_txctrl(self.read_txctrl() | TxControl::ENABLE.bits())
     }
 
+    /// Enable read
     pub fn enable_read(&self) {
         self.write_rxctrl(self.read_rxctrl() | RxControl::ENABLE.bits())
     }
 
+    /// Disable write
     pub fn disable_write(&self) {
         self.write_txctrl(self.read_txctrl() & !TxControl::ENABLE.bits())
     }
 
+    /// Disable read
     pub fn disable_read(&self) {
         self.write_rxctrl(self.read_rxctrl() & !RxControl::ENABLE.bits())
     }
 
+    /// Disable all interrupt
     pub fn disable_interrupt(&self) {
         self.write_ie(0)
     }
 
+    /// Enable read interrupt (and keep other bit in ie register)
     pub fn enable_read_interrupt(&self) {
         self.write_ie((self.read_ie() | InterruptRegister::RXWM).bits() as u32)
     }
 
+    /// Enable write interrupt (and keep other bit in ie register)
     pub fn enable_write_interrupt(&self) {
         self.write_ie((self.read_ie() | InterruptRegister::TXWM).bits() as u32)
     }