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CPUFreq:Recert original!

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1 parent c628c99 commit c4178ef7bed9e155fb1087258825d62a84481a4c @HomuHomu HomuHomu committed Apr 9, 2012
Showing with 51 additions and 541 deletions.
  1. +44 −235 arch/arm/mach-exynos/cpufreq-4210.c
  2. +7 −92 arch/arm/mach-exynos/cpufreq.c
  3. +0 −214 drivers/cpufreq/cpufreq.c
View
279 arch/arm/mach-exynos/cpufreq-4210.c
@@ -23,7 +23,7 @@
#include <plat/clock.h>
-#define CPUFREQ_LEVEL_END L19
+#define CPUFREQ_LEVEL_END L6
static int max_support_idx;
static int min_support_idx = (CPUFREQ_LEVEL_END - 1);
@@ -37,28 +37,15 @@ struct cpufreq_clkdiv {
unsigned int clkdiv;
};
-extern int exynos4210_volt_table[CPUFREQ_LEVEL_END];
+static unsigned int exynos4210_volt_table[CPUFREQ_LEVEL_END];
static struct cpufreq_frequency_table exynos4210_freq_table[] = {
- {L0, 2000*1000},
- {L1, 1600*1000},
- {L2, 1500*1000},
- {L3, 1400*1000},
- {L4, 1300*1000},
- {L5, 1200*1000},
- {L6, 1100*1000},
- {L7, 1000*1000},
- {L8, 900*1000},
- {L9, 800*1000},
- {L10, 700*1000},
- {L11, 600*1000},
- {L12, 500*1000},
- {L13, 400*1000},
- {L14, 300*1000},
- {L15, 200*1000},
- {L16, 100*1000},
- {L17, 50*1000},
- {L18, 25*1000},
+ {L0, 1400*1000},
+ {L1, 1200*1000},
+ {L2, 1000*1000},
+ {L3, 800*1000},
+ {L4, 500*1000},
+ {L5, 200*1000},
{0, CPUFREQ_TABLE_END},
};
@@ -69,19 +56,6 @@ static struct cpufreq_clkdiv exynos4210_clkdiv_table[] = {
{L3, 0},
{L4, 0},
{L5, 0},
- {L6, 0},
- {L7, 0},
- {L8, 0},
- {L9, 0},
- {L10, 0},
- {L11, 0},
- {L12, 0},
- {L13, 0},
- {L14, 0},
- {L15, 0},
- {L16, 0},
- {L17, 0},
- {L18, 0},
};
static unsigned int clkdiv_cpu0[CPUFREQ_LEVEL_END][7] = {
@@ -90,183 +64,66 @@ static unsigned int clkdiv_cpu0[CPUFREQ_LEVEL_END][7] = {
* { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH,
* DIVATB, DIVPCLK_DBG, DIVAPLL }
*/
- /* ARM L0: 2000MHz */
+ /* ARM L0: 1400MHz */
{ 0, 3, 7, 3, 4, 1, 7 },
- /* ARM L1: 1600MHz */
+ /* ARM L1: 1200MHz */
{ 0, 3, 7, 3, 4, 1, 7 },
- /* ARM L2: 1500MHz */
+ /* ARM L2: 1000MHz */
{ 0, 3, 7, 3, 4, 1, 7 },
- /* ARM L3: 1400MHz */
- { 0, 3, 7, 3, 4, 1, 7 },
-
- /* ARM L4: 1300MHz */
- { 0, 3, 7, 3, 4, 1, 7 },
-
- /* ARM L5: 1200MHz */
- { 0, 3, 7, 3, 4, 1, 7 },
-
- /* ARM L6: 1100MHz */
- { 0, 3, 7, 3, 4, 1, 7 },
-
- /* ARM L7: 1000MHz */
- { 0, 3, 7, 3, 4, 1, 7 },
-
- /* ARM L8: 900MHz */
- { 0, 3, 7, 3, 4, 1, 7 },
-
- /* ARM L9: 800MHz */
- { 0, 3, 7, 3, 3, 1, 7 },
-
- /* ARM L10: 700MHz */
- { 0, 3, 7, 3, 3, 1, 7 },
-
- /* ARM L11: 600MHz */
+ /* ARM L3: 800MHz */
{ 0, 3, 7, 3, 3, 1, 7 },
- /* ARM L12: 500MHz */
+ /* ARM L4: 500MHz */
{ 0, 3, 7, 3, 3, 1, 7 },
- /* ARM L13: 400MHz */
- { 0, 3, 7, 3, 3, 1, 7 },
-
- /* ARM L14: 300MHz */
- { 0, 3, 7, 3, 3, 1, 7 },
-
- /* ARM L15: 200MHz */
- { 0, 1, 3, 1, 3, 1, 0 },
-
- /* ARM L16: 100MHz */
- { 0, 1, 3, 1, 3, 1, 0 },
-
- /* ARM L17: 50MHz */
- { 0, 1, 3, 1, 3, 1, 0 },
-
- /* ARM L18: 25MHz */
+ /* ARM L5: 200MHz */
{ 0, 1, 3, 1, 3, 1, 0 },
};
static unsigned int clkdiv_cpu1[CPUFREQ_LEVEL_END][2] = {
/* Clock divider value for following
* { DIVCOPY, DIVHPM }
*/
- /* ARM L0: 2000MHz */
- { 5, 0 },
-
- /* ARM L1: 1600MHz */
- { 5, 0 },
-
- /* ARM L2: 1500MHz */
- { 5, 0 },
-
- /* ARM L3: 1400MHz */
- { 5, 0 },
-
- /* ARM L4: 1300MHz */
+ /* ARM L0: 1400MHz */
{ 5, 0 },
- /* ARM L5: 1200MHz */
+ /* ARM L1: 1200MHz */
{ 5, 0 },
- /* ARM L6: 1100MHz */
- { 5, 0 },
-
- /* ARM L7: 1000MHz */
- { 4, 0 },
-
- /* ARM L8: 900MHz */
+ /* ARM L2: 1000MHz */
{ 4, 0 },
- /* ARM L9: 800MHz */
- { 3, 0 },
-
- /* ARM L10: 700MHz */
- { 3, 0 },
-
- /* ARM L11: 600MHz */
- { 3, 0 },
-
- /* ARM L12: 500MHz */
- { 3, 0 },
-
- /* ARM L13: 400MHz */
- { 3, 0 },
-
- /* ARM L14: 300MHz */
- { 3, 0 },
-
- /* ARM L15: 200MHz */
- { 3, 0 },
-
- /* ARM L16: 100MHz */
+ /* ARM L3: 800MHz */
{ 3, 0 },
- /* ARM L17: 50MHz */
+ /* ARM L4: 500MHz */
{ 3, 0 },
- /* ARM L18: 25MHz */
+ /* ARM L5: 200MHz */
{ 3, 0 },
};
static unsigned int exynos4_apll_pms_table[CPUFREQ_LEVEL_END] = {
- /* APLL FOUT L0: 2000MHz */
- ((250<<16)|(3<<8)|(0x1)),
+ /* APLL FOUT L0: 1400MHz */
+ ((350<<16)|(6<<8)|(0x1)),
- /* APLL FOUT L1: 1600MHz */
- ((200<<16)|(3<<8)|(0x1)),
-
- /* APLL FOUT L2: 1500MHz */
- ((375<<16)|(6<<8)|(0x1)),
-
- /* APLL FOUT L3: 1400MHz */
- ((175<<16)|(3<<8)|(0x1)),
-
- /* APLL FOUT L4: 1300MHz */
- ((325<<16)|(6<<8)|(0x1)),
-
- /* APLL FOUT L5: 1200MHz */
+ /* APLL FOUT L1: 1200MHz */
((150<<16)|(3<<8)|(0x1)),
- /* APLL FOUT L6: 1100MHz */
- ((275<<16)|(6<<8)|(0x1)),
-
- /* APLL FOUT L7: 1000MHz */
+ /* APLL FOUT L2: 1000MHz */
((250<<16)|(6<<8)|(0x1)),
- /* APLL FOUT L8: 900MHz */
- ((225<<16)|(6<<8)|(0x1)),
-
- /* APLL FOUT L9: 800MHz */
+ /* APLL FOUT L3: 800MHz */
((200<<16)|(6<<8)|(0x1)),
- /* APLL FOUT L10: 700MHz */
- ((175<<16)|(6<<8)|(0x1)),
-
- /* APLL FOUT L11: 600MHz */
- ((150<<16)|(6<<8)|(0x1)),
-
- /* APLL FOUT L12: 500MHz */
+ /* APLL FOUT L4: 500MHz */
((250<<16)|(6<<8)|(0x2)),
- /* APLL FOUT L13: 400MHz */
- ((200<<16)|(6<<8)|(0x2)),
-
- /* APLL FOUT L14: 300MHz */
- ((150<<16)|(6<<8)|(0x2)),
-
- /* APLL FOUT L15: 200MHz */
+ /* APLL FOUT L5: 200MHz */
((200<<16)|(6<<8)|(0x3)),
-
- /* APLL FOUT L16: 100MHz */
- ((100<<16)|(6<<8)|(0x3)),
-
- /* APLL FOUT L17: 50MHz */
- ((50<<16)|(6<<8)|(0x3)),
-
- /* APLL FOUT L18: 25MHz */
- ((25<<16)|(6<<8)|(0x3)),
};
/*
@@ -277,86 +134,38 @@ static const unsigned int asv_voltage_A[CPUFREQ_LEVEL_END][8] = {
/*
* SS, A1, A2, B1, B2, C1, C2, D
* @Dummy:
- * @1600 :
- * @1500 :
- * @1400 :
- * @1300 :
* @1200 :
- * @1100 :
* @1000 :
- * @900 :
* @800 : ASV_VOLTAGE_TABLE
- * @700 :
- * @600 :
* @500 :
- * @400 :
- * @300 :
* @200 :
- * @100 :
- * @50 :
- * @25 :
*/
{ 0, 0, 0, 0, 0, 0, 0, 0 },
- { 1500000, 1475000, 1450000, 1425000, 1400000, 1375000, 1350000, 1325000 },//1600MHz
- { 1450000, 1425000, 1400000, 1375000, 1350000, 1325000, 1300000, 1275000 },//1500MHz
- { 1400000, 1375000, 1350000, 1325000, 1300000, 1275000, 1250000, 1225000 },//1400MHz
- { 1350000, 1325000, 1300000, 1275000, 1250000, 1225000, 1200000, 1175000 },//1300MHz
- { 1300000, 1275000, 1250000, 1225000, 1200000, 1175000, 1150000, 1125000 },//1200MHz
- { 1275000, 1250000, 1225000, 1200000, 1175000, 1150000, 1125000, 1100000 },//1100MHz
- { 1250000, 1225000, 1200000, 1175000, 1150000, 1125000, 1100000, 1075000 },//1000MHz
- { 1225000, 1200000, 1175000, 1150000, 1125000, 1100000, 1075000, 1050000 },//900MHz
- { 1200000, 1175000, 1150000, 1125000, 1100000, 1075000, 1050000, 1025000 },//800MHz
- { 1175000, 1150000, 1125000, 1100000, 1075000, 1050000, 1025000, 1000000 },//600MHz
- { 1150000, 1125000, 1100000, 1075000, 1050000, 1025000, 1000000, 975000 },//600MHz
- { 1125000, 1100000, 1075000, 1050000, 1025000, 1000000, 975000, 950000 },//500MHz
- { 1100000, 1075000, 1050000, 1025000, 1000000, 975000, 950000, 925000 },//400MHz
- { 1075000, 1050000, 1025000, 1000000, 975000, 950000, 925000, 900000 },//300MHz
- { 1050000, 1025000, 1000000, 975000, 950000, 925000, 900000, 875000 },//200MHz
- { 1025000, 1000000, 975000, 950000, 925000, 900000, 875000, 850000 },//100MHz
- { 1000000, 975000, 950000, 925000, 900000, 875000, 850000, 825000 },//50MHz
- { 975000, 950000, 925000, 900000, 875000, 850000, 825000, 800000 },//25MHz
+ { 1350000, 1350000, 1300000, 1275000, 1250000, 1225000, 1200000, 1175000 },
+ { 1300000, 1250000, 1200000, 1175000, 1150000, 1125000, 1100000, 1075000 },
+ { 1200000, 1150000, 1100000, 1075000, 1050000, 1025000, 1000000, 975000 },
+ { 1100000, 1050000, 1000000, 975000, 975000, 950000, 925000, 925000 },
+ { 1050000, 1000000, 975000, 950000, 950000, 925000, 925000, 925000 },
+
};
static const unsigned int asv_voltage_B[CPUFREQ_LEVEL_END][5] = {
/*
* S, A, B, C, D
- * @1600 :
- * @1500 :
* @1400 :
- * @1300 :
* @1200 :
- * @1100 :
* @1000 :
- * @900 :
* @800 : ASV_VOLTAGE_TABLE
- * @700 :
- * @600 :
* @500 :
- * @400 :
- * @300 :
* @200 :
- * @100 :
- * @50 :
- * @25 :
*/
- { 1325000, 1300000, 1275000, 1250000, 1225000 },//1600MHz
- { 1300000, 1275000, 1250000, 1225000, 1200000 },//1500MHz
- { 1275000, 1250000, 1225000, 1200000, 1175000 },//1400MHz
- { 1250000, 1225000, 1200000, 1175000, 1150000 },//1300MHz
- { 1225000, 1200000, 1175000, 1150000, 1125000 },//1200MHz
- { 1200000, 1175000, 1150000, 1125000, 1100000 },//1100MHz
- { 1175000, 1150000, 1125000, 1100000, 1075000 },//1000MHz
- { 1150000, 1125000, 1100000, 1075000, 1050000 },//900MHz
- { 1125000, 1100000, 1075000, 1050000, 1025000 },//800MHz
- { 1100000, 1075000, 1050000, 1025000, 1000000 },//700MHz
- { 1075000, 1050000, 1025000, 1000000, 975000 },//600MHz
- { 1050000, 1025000, 1000000, 975000, 950000 },//500MHz
- { 1025000, 1000000, 975000, 950000, 925000 },//400MHz
- { 1000000, 975000, 950000, 925000, 900000 },//300MHz
- { 975000, 950000, 925000, 900000, 875000 },//200MHz
- { 950000, 925000, 900000, 875000, 850000 },//100MHz
- { 925000, 900000, 875000, 850000, 825000 },//50MHz
- { 900000, 875000, 850000, 825000, 800000 },//25MHz
+ { 1350000, 1350000, 1300000, 1250000, 1225000 },
+ { 1325000, 1275000, 1225000, 1175000, 1150000 },
+ { 1225000, 1175000, 1125000, 1075000, 1050000 },
+ { 1150000, 1100000, 1050000, 1000000, 975000 },
+ { 1050000, 1000000, 950000, 950000, 950000 },
+ { 1025000, 975000, 950000, 950000, 950000 },
+
};
static void set_clkdiv(unsigned int div_index)
@@ -501,11 +310,11 @@ static void __init set_volt_table(void)
break;
case SUPPORT_1000MHZ:
for_1000 = true;
- max_support_idx = L7;
+ max_support_idx = L2;
break;
default:
for_1000 = true;
- max_support_idx = L7;
+ max_support_idx = L2;
break;
}
@@ -605,8 +414,8 @@ int exynos4210_cpufreq_init(struct exynos_dvfs_info *info)
}
info->mpll_freq_khz = rate;
- info->pm_lock_idx = L9;
- info->pll_safe_idx = L7;
+ info->pm_lock_idx = L3;
+ info->pll_safe_idx = L2;
info->max_support_idx = max_support_idx;
info->min_support_idx = min_support_idx;
info->cpu_clk = cpu_clk;
View
99 arch/arm/mach-exynos/cpufreq.c
@@ -100,42 +100,18 @@ static int exynos_target(struct cpufreq_policy *policy,
if (exynos_cpufreq_disable)
goto out;
- freqs.old = exynos_getspeed(policy->cpu);
-
- if(policy->max < freqs.old || policy->min > freqs.old)
- {
- struct cpufreq_policy policytemp;
- memcpy(&policytemp, policy, sizeof(struct cpufreq_policy));
- if(policytemp.max < freqs.old)
- policytemp.max = freqs.old;
- if(policytemp.min > freqs.old)
- policytemp.min = freqs.old;
- if (cpufreq_frequency_table_target(&policytemp, freq_table,
- freqs.old, relation, &old_index)) {
- ret = -EINVAL;
- goto out;
- }
- } else
- {
- if (cpufreq_frequency_table_target(policy, freq_table,
- freqs.old, relation, &old_index)) {
- ret = -EINVAL;
- goto out;
- }
- }
+ freqs.old = policy->cur;
if (cpufreq_frequency_table_target(policy, freq_table,
- target_freq, relation, &index)) {
+ freqs.old, relation, &old_index)) {
ret = -EINVAL;
goto out;
}
- /* prevent freqs going above max policy - netarchy */
- /* Do this before lock checks or the locks won't behave - A. Dodd */
- if (freq_table[index].frequency > policy->max) {
- while (freq_table[index].frequency > policy-> max) {
- index += 1;
- }
+ if (cpufreq_frequency_table_target(policy, freq_table,
+ target_freq, relation, &index)) {
+ ret = -EINVAL;
+ goto out;
}
/* Need to set performance limitation */
@@ -150,11 +126,6 @@ static int exynos_target(struct cpufreq_policy *policy,
if (index == exynos_info->max_support_idx && old_index > 3)
index = 3;
#endif
-/* prevent freqs going above max policy - netarchy */
- while (exynos_info->freq_table[index].frequency > policy->max) {
- index += 1;
- }
-
freqs.new = freq_table[index].frequency;
freqs.cpu = policy->cpu;
@@ -519,7 +490,6 @@ static int exynos_cpufreq_notifier_event(struct notifier_block *this,
static struct notifier_block exynos_cpufreq_notifier = {
.notifier_call = exynos_cpufreq_notifier_event,
- .priority = INT_MIN, /* done last */
};
static int exynos_cpufreq_policy_notifier_call(struct notifier_block *this,
@@ -574,11 +544,7 @@ static int exynos_cpufreq_cpu_init(struct cpufreq_policy *policy)
cpumask_setall(policy->cpus);
}
- cpufreq_frequency_table_cpuinfo(policy, exynos_info->freq_table);
- /* Safe default startup limits */
- policy->max = 1200000;
- policy->min = 200000;
- return 0;
+ return cpufreq_frequency_table_cpuinfo(policy, exynos_info->freq_table);
}
static int exynos_cpufreq_reboot_notifier_call(struct notifier_block *this,
@@ -598,20 +564,13 @@ static struct notifier_block exynos_cpufreq_reboot_notifier = {
.notifier_call = exynos_cpufreq_reboot_notifier_call,
};
-/* Make sure we populate scaling_available_freqs in sysfs - netarchy */
-static struct freq_attr *exynos_cpufreq_attr[] = {
- &cpufreq_freq_attr_scaling_available_freqs,
- NULL,
-};
-
static struct cpufreq_driver exynos_driver = {
.flags = CPUFREQ_STICKY,
.verify = exynos_verify_speed,
.target = exynos_target,
.get = exynos_getspeed,
.init = exynos_cpufreq_cpu_init,
.name = "exynos_cpufreq",
- .attr = exynos_cpufreq_attr,
#ifdef CONFIG_PM
.suspend = exynos_cpufreq_suspend,
.resume = exynos_cpufreq_resume,
@@ -686,47 +645,3 @@ static int __init exynos_cpufreq_init(void)
return -EINVAL;
}
late_initcall(exynos_cpufreq_init);
-
-
-/* vdd_levels interface for TEGRAK OC compatibility - thx to gm */
-#define VREF_SEL 1 /* 0: 0.625V (50mV step), 1: 0.3125V (25mV step). */
-#define V_STEP (25 * (2 - VREF_SEL)) /* Minimum voltage step size. */
-#define VREG_DATA (VREG_CONFIG | (VREF_SEL << 5))
-#define VREG_CONFIG (BIT(7) | BIT(6)) /* Enable VREG, pull-down if disabled. */
-/* Cause a compile error if the voltage is not a multiple of the step size. */
-#define MV(mv) ((mv) / (!((mv) % V_STEP)))
-
-ssize_t acpuclk_get_vdd_levels_str(char *buf)
-{
- int i, len = 0;
-
- if (buf)
- {
- for (i = exynos_info->max_support_idx; i<=exynos_info->min_support_idx; i++)
- {
- if(exynos_info->freq_table[i].frequency==CPUFREQ_ENTRY_INVALID) continue;
- len += sprintf(buf + len, "%8u: %4d\n", exynos_info->freq_table[i].frequency, exynos_info->volt_table[i]);
- }
- }
-
- return len;
-}
-
-void acpuclk_set_vdd(unsigned int khz, int vdd)
-{
- int i;
- unsigned int new_vdd;
- vdd = vdd / V_STEP * V_STEP;
-
- for (i = exynos_info->max_support_idx; i<=exynos_info->min_support_idx; i++)
- {
- if(exynos_info->freq_table[i].frequency==CPUFREQ_ENTRY_INVALID) continue;
- if (khz == 0)
- new_vdd = min(max((unsigned int)(exynos_info->volt_table[i] + vdd), (unsigned int)CPU_UV_MV_MIN), (unsigned int)CPU_UV_MV_MAX);
- else if (exynos_info->freq_table[i].frequency == khz)
- new_vdd = min(max((unsigned int)vdd, (unsigned int)CPU_UV_MV_MIN), (unsigned int)CPU_UV_MV_MAX);
- else continue;
-
- exynos_info->volt_table[i] = new_vdd;
- }
-}
View
214 drivers/cpufreq/cpufreq.c
@@ -32,8 +32,6 @@
#include <trace/events/power.h>
-int exynos4210_volt_table[19];
-
/**
* The "cpufreq driver" - the arch- or hardware-dependent low
* level driver of CPUFreq support, and its spinlock. This lock
@@ -555,212 +553,6 @@ static ssize_t show_scaling_setspeed(struct cpufreq_policy *policy, char *buf)
return policy->governor->show_setspeed(policy, buf);
}
-/* sysfs interface for UV control */
-ssize_t show_UV_mV_table(struct cpufreq_policy *policy, char *buf) {
-
- return sprintf(buf,
- "1600mhz: %d mV\n\
- 1500mhz: %d mV\n\
- 1400mhz: %d mV\n\
- 1300mhz: %d mV\n\
- 1200mhz: %d mV\n\
- 1100mhz: %d mV\n\
- 1000mhz: %d mV\n\
- 900mhz: %d mV\n\
- 800mhz: %d mV\n\
- 700mhz: %d mV\n\
- 600mhz: %d mV\n\
- 500mhz: %d mV\n\
- 400mhz: %d mV\n\
- 300mhz: %d mV\n\
- 200mhz: %d mV\n\
- 100mhz: %d mV\n\
- 50mhz: %d mV\n\
- 25mhz: %d mV\n",
- exynos4210_volt_table[1]/1000,
- exynos4210_volt_table[2]/1000,
- exynos4210_volt_table[3]/1000,
- exynos4210_volt_table[4]/1000,
- exynos4210_volt_table[5]/1000,
- exynos4210_volt_table[6]/1000,
- exynos4210_volt_table[7]/1000,
- exynos4210_volt_table[8]/1000,
- exynos4210_volt_table[9]/1000,
- exynos4210_volt_table[10]/1000,
- exynos4210_volt_table[11]/1000,
- exynos4210_volt_table[12]/1000,
- exynos4210_volt_table[13]/1000,
- exynos4210_volt_table[14]/1000,
- exynos4210_volt_table[15]/1000,
- exynos4210_volt_table[16]/1000,
- exynos4210_volt_table[17]/1000,
- exynos4210_volt_table[18]/1000);
-
-}
-
-ssize_t store_UV_mV_table(struct cpufreq_policy *policy,
- const char *buf, size_t count) {
-
- unsigned int ret = -EINVAL;
- int i = 0;
- int u[18];
- ret = sscanf(buf, "%d %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d",
- &u[0], &u[1], &u[2], &u[3], &u[4], &u[5], &u[6], &u[7], &u[8],
- &u[9], &u[10], &u[11], &u[12], &u[13], &u[14], &u[15], &u[16], &u[17]);
- if(ret != 18) {
- ret = sscanf(buf, "%d %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d",
- &u[0], &u[1], &u[2], &u[3], &u[4], &u[5], &u[6], &u[7], &u[8],
- &u[9], &u[10], &u[11], &u[12], &u[13], &u[14], &u[15], &u[16]);
- if(ret != 17) {
- ret = sscanf(buf, "%d %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d",
- &u[0], &u[1], &u[2], &u[3], &u[4], &u[5], &u[6], &u[7], &u[8],
- &u[9], &u[10], &u[11], &u[12], &u[13], &u[14], &u[15]);
- if(ret != 16) {
- ret = sscanf(buf, "%d %d %d %d %d %d %d %d %d %d %d %d %d %d %d",
- &u[0], &u[1], &u[2], &u[3], &u[4], &u[5], &u[6], &u[7],
- &u[8], &u[9], &u[10], &u[11], &u[12], &u[13], &u[14]);
- if(ret != 15) {
- ret = sscanf(buf, "%d %d %d %d %d %d %d %d %d %d %d %d %d %d",
- &u[0], &u[1], &u[2], &u[3], &u[4], &u[5], &u[6], &u[7],
- &u[8], &u[9], &u[10], &u[11], &u[12], &u[13]);
- if(ret != 14) {
- ret = sscanf(buf, "%d %d %d %d %d %d %d %d %d %d %d %d %d",
- &u[0], &u[1], &u[2], &u[3], &u[4], &u[5], &u[6],
- &u[7], &u[8], &u[9], &u[10], &u[11], &u[12]);
- if(ret != 13) {
- ret = sscanf(buf, "%d %d %d %d %d %d %d %d %d %d %d %d",
- &u[0], &u[1], &u[2], &u[3], &u[4], &u[5], &u[6],
- &u[7], &u[8], &u[9], &u[10], &u[11]);
- if(ret != 12) {
- ret = sscanf(buf, "%d %d %d %d %d %d %d %d %d %d %d",
- &u[0], &u[1], &u[2], &u[3], &u[4], &u[5], &u[6],
- &u[7], &u[8], &u[9], &u[10]);
- if(ret != 11) {
- ret = sscanf(buf, "%d %d %d %d %d %d %d %d %d %d",
- &u[0], &u[1], &u[2], &u[3], &u[4], &u[5], &u[6],
- &u[7],&u[8],&u[9]);
- if(ret != 10) {
- ret = sscanf(buf, "%d %d %d %d %d %d %d %d %d",
- &u[0], &u[1], &u[2], &u[3], &u[4], &u[5], &u[6],
- &u[7], &u[8]);
- if(ret != 9) {
- ret = sscanf(buf, "%d %d %d %d %d %d %d %d",
- &u[0], &u[1], &u[2], &u[3], &u[4], &u[5],
- &u[6], &u[7]);
- if(ret != 8) {
- ret = sscanf(buf, "%d %d %d %d %d %d %d",
- &u[0], &u[1], &u[2], &u[3], &u[4], &u[5],
- &u[6]);
- if(ret != 7) {
- ret = sscanf(buf, "%d %d %d %d %d %d",
- &u[0], &u[1], &u[2], &u[3], &u[4], &u[5]);
- if(ret != 6) {
- ret = sscanf(buf, "%d %d %d %d %d",
- &u[0], &u[1], &u[2], &u[3], &u[4]);
- if(ret != 5) {
- ret = sscanf(buf, "%d %d %d %d",
- &u[0], &u[1], &u[2], &u[3]);
- if(ret != 4) return -EINVAL;
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- }
- for( i = 0; i < 18; i++ )
- {
- if (u[i] > CPU_UV_MV_MAX / 1000)
- {
- u[i] = CPU_UV_MV_MAX / 1000;
- }
- else if (u[i] < CPU_UV_MV_MIN / 1000)
- {
- u[i] = CPU_UV_MV_MIN / 1000;
- }
- }
-
- for( i = 0; i < 18; i++ )
- {
- exynos4210_volt_table[i+1] = u[i] * 1000;
- }
-
- return count;
-}
-
-/* vdd_levels interface for TEGRAK OC - thx to gm */
-
-extern ssize_t acpuclk_get_vdd_levels_str(char *buf);
-
-static ssize_t show_vdd_levels(struct cpufreq_policy *policy, char *buf)
-{
- return acpuclk_get_vdd_levels_str(buf);
-}
-
-extern void acpuclk_set_vdd(unsigned acpu_khz, int vdd);
-
-static ssize_t store_vdd_levels(struct cpufreq_policy *policy, const char *buf, size_t count)
-{
- int i = 0, j;
- int pair[2] = { 0, 0 };
- int sign = 0;
-
- if (count < 1)
- return 0;
- if (buf[0] == '-')
- {
- sign = -1;
- i++;
- }
- else if (buf[0] == '+')
- {
- sign = 1;
- i++;
- }
-
- for (j = 0; i < count; i++)
- {
- char c = buf[i];
- if ((c >= '0') && (c <= '9'))
- {
- pair[j] *= 10;
- pair[j] += (c - '0');
- }
- else if ((c == ' ') || (c == '\t'))
- {
- if (pair[j] != 0)
- {
- j++;
- if ((sign != 0) || (j > 1))
- break;
- }
- }
- else
- break;
- }
-
- if (sign != 0)
- {
- if (pair[0] > 0)
- acpuclk_set_vdd(0, sign * pair[0]);
- }
- else
- {
- if ((pair[0] > 0) && (pair[1] > 0))
- acpuclk_set_vdd((unsigned)pair[0], pair[1]);
- else
- return -EINVAL;
- }
- return count;
-}
-
/**
* show_scaling_driver - show the current cpufreq HW/BIOS limitation
*/
@@ -790,10 +582,6 @@ cpufreq_freq_attr_rw(scaling_min_freq);
cpufreq_freq_attr_rw(scaling_max_freq);
cpufreq_freq_attr_rw(scaling_governor);
cpufreq_freq_attr_rw(scaling_setspeed);
-/* UV table */
-cpufreq_freq_attr_rw(UV_mV_table);
-/* vdd_levels */
-cpufreq_freq_attr_rw(vdd_levels);
static struct attribute *default_attrs[] = {
&cpuinfo_min_freq.attr,
@@ -807,8 +595,6 @@ static struct attribute *default_attrs[] = {
&scaling_driver.attr,
&scaling_available_governors.attr,
&scaling_setspeed.attr,
- &UV_mV_table.attr,
- &vdd_levels.attr,
NULL
};

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