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CPUFreq:Recert original!

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HomuHomu committed Apr 9, 2012
1 parent c628c99 commit c4178ef7bed9e155fb1087258825d62a84481a4c
Showing with 51 additions and 541 deletions.
  1. +44 −235 arch/arm/mach-exynos/cpufreq-4210.c
  2. +7 −92 arch/arm/mach-exynos/cpufreq.c
  3. +0 −214 drivers/cpufreq/cpufreq.c
@@ -23,7 +23,7 @@
#include <plat/clock.h>
-#define CPUFREQ_LEVEL_END L19
+#define CPUFREQ_LEVEL_END L6
static int max_support_idx;
static int min_support_idx = (CPUFREQ_LEVEL_END - 1);
@@ -37,28 +37,15 @@ struct cpufreq_clkdiv {
unsigned int clkdiv;
};
-extern int exynos4210_volt_table[CPUFREQ_LEVEL_END];
+static unsigned int exynos4210_volt_table[CPUFREQ_LEVEL_END];
static struct cpufreq_frequency_table exynos4210_freq_table[] = {
- {L0, 2000*1000},
- {L1, 1600*1000},
- {L2, 1500*1000},
- {L3, 1400*1000},
- {L4, 1300*1000},
- {L5, 1200*1000},
- {L6, 1100*1000},
- {L7, 1000*1000},
- {L8, 900*1000},
- {L9, 800*1000},
- {L10, 700*1000},
- {L11, 600*1000},
- {L12, 500*1000},
- {L13, 400*1000},
- {L14, 300*1000},
- {L15, 200*1000},
- {L16, 100*1000},
- {L17, 50*1000},
- {L18, 25*1000},
+ {L0, 1400*1000},
+ {L1, 1200*1000},
+ {L2, 1000*1000},
+ {L3, 800*1000},
+ {L4, 500*1000},
+ {L5, 200*1000},
{0, CPUFREQ_TABLE_END},
};
@@ -69,19 +56,6 @@ static struct cpufreq_clkdiv exynos4210_clkdiv_table[] = {
{L3, 0},
{L4, 0},
{L5, 0},
- {L6, 0},
- {L7, 0},
- {L8, 0},
- {L9, 0},
- {L10, 0},
- {L11, 0},
- {L12, 0},
- {L13, 0},
- {L14, 0},
- {L15, 0},
- {L16, 0},
- {L17, 0},
- {L18, 0},
};
static unsigned int clkdiv_cpu0[CPUFREQ_LEVEL_END][7] = {
@@ -90,183 +64,66 @@ static unsigned int clkdiv_cpu0[CPUFREQ_LEVEL_END][7] = {
* { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH,
* DIVATB, DIVPCLK_DBG, DIVAPLL }
*/
- /* ARM L0: 2000MHz */
+ /* ARM L0: 1400MHz */
{ 0, 3, 7, 3, 4, 1, 7 },
- /* ARM L1: 1600MHz */
+ /* ARM L1: 1200MHz */
{ 0, 3, 7, 3, 4, 1, 7 },
- /* ARM L2: 1500MHz */
+ /* ARM L2: 1000MHz */
{ 0, 3, 7, 3, 4, 1, 7 },
- /* ARM L3: 1400MHz */
- { 0, 3, 7, 3, 4, 1, 7 },
-
- /* ARM L4: 1300MHz */
- { 0, 3, 7, 3, 4, 1, 7 },
-
- /* ARM L5: 1200MHz */
- { 0, 3, 7, 3, 4, 1, 7 },
-
- /* ARM L6: 1100MHz */
- { 0, 3, 7, 3, 4, 1, 7 },
-
- /* ARM L7: 1000MHz */
- { 0, 3, 7, 3, 4, 1, 7 },
-
- /* ARM L8: 900MHz */
- { 0, 3, 7, 3, 4, 1, 7 },
-
- /* ARM L9: 800MHz */
- { 0, 3, 7, 3, 3, 1, 7 },
-
- /* ARM L10: 700MHz */
- { 0, 3, 7, 3, 3, 1, 7 },
-
- /* ARM L11: 600MHz */
+ /* ARM L3: 800MHz */
{ 0, 3, 7, 3, 3, 1, 7 },
- /* ARM L12: 500MHz */
+ /* ARM L4: 500MHz */
{ 0, 3, 7, 3, 3, 1, 7 },
- /* ARM L13: 400MHz */
- { 0, 3, 7, 3, 3, 1, 7 },
-
- /* ARM L14: 300MHz */
- { 0, 3, 7, 3, 3, 1, 7 },
-
- /* ARM L15: 200MHz */
- { 0, 1, 3, 1, 3, 1, 0 },
-
- /* ARM L16: 100MHz */
- { 0, 1, 3, 1, 3, 1, 0 },
-
- /* ARM L17: 50MHz */
- { 0, 1, 3, 1, 3, 1, 0 },
-
- /* ARM L18: 25MHz */
+ /* ARM L5: 200MHz */
{ 0, 1, 3, 1, 3, 1, 0 },
};
static unsigned int clkdiv_cpu1[CPUFREQ_LEVEL_END][2] = {
/* Clock divider value for following
* { DIVCOPY, DIVHPM }
*/
- /* ARM L0: 2000MHz */
- { 5, 0 },
-
- /* ARM L1: 1600MHz */
- { 5, 0 },
-
- /* ARM L2: 1500MHz */
- { 5, 0 },
-
- /* ARM L3: 1400MHz */
- { 5, 0 },
-
- /* ARM L4: 1300MHz */
+ /* ARM L0: 1400MHz */
{ 5, 0 },
- /* ARM L5: 1200MHz */
+ /* ARM L1: 1200MHz */
{ 5, 0 },
- /* ARM L6: 1100MHz */
- { 5, 0 },
-
- /* ARM L7: 1000MHz */
- { 4, 0 },
-
- /* ARM L8: 900MHz */
+ /* ARM L2: 1000MHz */
{ 4, 0 },
- /* ARM L9: 800MHz */
- { 3, 0 },
-
- /* ARM L10: 700MHz */
- { 3, 0 },
-
- /* ARM L11: 600MHz */
- { 3, 0 },
-
- /* ARM L12: 500MHz */
- { 3, 0 },
-
- /* ARM L13: 400MHz */
- { 3, 0 },
-
- /* ARM L14: 300MHz */
- { 3, 0 },
-
- /* ARM L15: 200MHz */
- { 3, 0 },
-
- /* ARM L16: 100MHz */
+ /* ARM L3: 800MHz */
{ 3, 0 },
- /* ARM L17: 50MHz */
+ /* ARM L4: 500MHz */
{ 3, 0 },
- /* ARM L18: 25MHz */
+ /* ARM L5: 200MHz */
{ 3, 0 },
};
static unsigned int exynos4_apll_pms_table[CPUFREQ_LEVEL_END] = {
- /* APLL FOUT L0: 2000MHz */
- ((250<<16)|(3<<8)|(0x1)),
+ /* APLL FOUT L0: 1400MHz */
+ ((350<<16)|(6<<8)|(0x1)),
- /* APLL FOUT L1: 1600MHz */
- ((200<<16)|(3<<8)|(0x1)),
-
- /* APLL FOUT L2: 1500MHz */
- ((375<<16)|(6<<8)|(0x1)),
-
- /* APLL FOUT L3: 1400MHz */
- ((175<<16)|(3<<8)|(0x1)),
-
- /* APLL FOUT L4: 1300MHz */
- ((325<<16)|(6<<8)|(0x1)),
-
- /* APLL FOUT L5: 1200MHz */
+ /* APLL FOUT L1: 1200MHz */
((150<<16)|(3<<8)|(0x1)),
- /* APLL FOUT L6: 1100MHz */
- ((275<<16)|(6<<8)|(0x1)),
-
- /* APLL FOUT L7: 1000MHz */
+ /* APLL FOUT L2: 1000MHz */
((250<<16)|(6<<8)|(0x1)),
- /* APLL FOUT L8: 900MHz */
- ((225<<16)|(6<<8)|(0x1)),
-
- /* APLL FOUT L9: 800MHz */
+ /* APLL FOUT L3: 800MHz */
((200<<16)|(6<<8)|(0x1)),
- /* APLL FOUT L10: 700MHz */
- ((175<<16)|(6<<8)|(0x1)),
-
- /* APLL FOUT L11: 600MHz */
- ((150<<16)|(6<<8)|(0x1)),
-
- /* APLL FOUT L12: 500MHz */
+ /* APLL FOUT L4: 500MHz */
((250<<16)|(6<<8)|(0x2)),
- /* APLL FOUT L13: 400MHz */
- ((200<<16)|(6<<8)|(0x2)),
-
- /* APLL FOUT L14: 300MHz */
- ((150<<16)|(6<<8)|(0x2)),
-
- /* APLL FOUT L15: 200MHz */
+ /* APLL FOUT L5: 200MHz */
((200<<16)|(6<<8)|(0x3)),
-
- /* APLL FOUT L16: 100MHz */
- ((100<<16)|(6<<8)|(0x3)),
-
- /* APLL FOUT L17: 50MHz */
- ((50<<16)|(6<<8)|(0x3)),
-
- /* APLL FOUT L18: 25MHz */
- ((25<<16)|(6<<8)|(0x3)),
};
/*
@@ -277,86 +134,38 @@ static const unsigned int asv_voltage_A[CPUFREQ_LEVEL_END][8] = {
/*
* SS, A1, A2, B1, B2, C1, C2, D
* @Dummy:
- * @1600 :
- * @1500 :
- * @1400 :
- * @1300 :
* @1200 :
- * @1100 :
* @1000 :
- * @900 :
* @800 : ASV_VOLTAGE_TABLE
- * @700 :
- * @600 :
* @500 :
- * @400 :
- * @300 :
* @200 :
- * @100 :
- * @50 :
- * @25 :
*/
{ 0, 0, 0, 0, 0, 0, 0, 0 },
- { 1500000, 1475000, 1450000, 1425000, 1400000, 1375000, 1350000, 1325000 },//1600MHz
- { 1450000, 1425000, 1400000, 1375000, 1350000, 1325000, 1300000, 1275000 },//1500MHz
- { 1400000, 1375000, 1350000, 1325000, 1300000, 1275000, 1250000, 1225000 },//1400MHz
- { 1350000, 1325000, 1300000, 1275000, 1250000, 1225000, 1200000, 1175000 },//1300MHz
- { 1300000, 1275000, 1250000, 1225000, 1200000, 1175000, 1150000, 1125000 },//1200MHz
- { 1275000, 1250000, 1225000, 1200000, 1175000, 1150000, 1125000, 1100000 },//1100MHz
- { 1250000, 1225000, 1200000, 1175000, 1150000, 1125000, 1100000, 1075000 },//1000MHz
- { 1225000, 1200000, 1175000, 1150000, 1125000, 1100000, 1075000, 1050000 },//900MHz
- { 1200000, 1175000, 1150000, 1125000, 1100000, 1075000, 1050000, 1025000 },//800MHz
- { 1175000, 1150000, 1125000, 1100000, 1075000, 1050000, 1025000, 1000000 },//600MHz
- { 1150000, 1125000, 1100000, 1075000, 1050000, 1025000, 1000000, 975000 },//600MHz
- { 1125000, 1100000, 1075000, 1050000, 1025000, 1000000, 975000, 950000 },//500MHz
- { 1100000, 1075000, 1050000, 1025000, 1000000, 975000, 950000, 925000 },//400MHz
- { 1075000, 1050000, 1025000, 1000000, 975000, 950000, 925000, 900000 },//300MHz
- { 1050000, 1025000, 1000000, 975000, 950000, 925000, 900000, 875000 },//200MHz
- { 1025000, 1000000, 975000, 950000, 925000, 900000, 875000, 850000 },//100MHz
- { 1000000, 975000, 950000, 925000, 900000, 875000, 850000, 825000 },//50MHz
- { 975000, 950000, 925000, 900000, 875000, 850000, 825000, 800000 },//25MHz
+ { 1350000, 1350000, 1300000, 1275000, 1250000, 1225000, 1200000, 1175000 },
+ { 1300000, 1250000, 1200000, 1175000, 1150000, 1125000, 1100000, 1075000 },
+ { 1200000, 1150000, 1100000, 1075000, 1050000, 1025000, 1000000, 975000 },
+ { 1100000, 1050000, 1000000, 975000, 975000, 950000, 925000, 925000 },
+ { 1050000, 1000000, 975000, 950000, 950000, 925000, 925000, 925000 },
+
};
static const unsigned int asv_voltage_B[CPUFREQ_LEVEL_END][5] = {
/*
* S, A, B, C, D
- * @1600 :
- * @1500 :
* @1400 :
- * @1300 :
* @1200 :
- * @1100 :
* @1000 :
- * @900 :
* @800 : ASV_VOLTAGE_TABLE
- * @700 :
- * @600 :
* @500 :
- * @400 :
- * @300 :
* @200 :
- * @100 :
- * @50 :
- * @25 :
*/
- { 1325000, 1300000, 1275000, 1250000, 1225000 },//1600MHz
- { 1300000, 1275000, 1250000, 1225000, 1200000 },//1500MHz
- { 1275000, 1250000, 1225000, 1200000, 1175000 },//1400MHz
- { 1250000, 1225000, 1200000, 1175000, 1150000 },//1300MHz
- { 1225000, 1200000, 1175000, 1150000, 1125000 },//1200MHz
- { 1200000, 1175000, 1150000, 1125000, 1100000 },//1100MHz
- { 1175000, 1150000, 1125000, 1100000, 1075000 },//1000MHz
- { 1150000, 1125000, 1100000, 1075000, 1050000 },//900MHz
- { 1125000, 1100000, 1075000, 1050000, 1025000 },//800MHz
- { 1100000, 1075000, 1050000, 1025000, 1000000 },//700MHz
- { 1075000, 1050000, 1025000, 1000000, 975000 },//600MHz
- { 1050000, 1025000, 1000000, 975000, 950000 },//500MHz
- { 1025000, 1000000, 975000, 950000, 925000 },//400MHz
- { 1000000, 975000, 950000, 925000, 900000 },//300MHz
- { 975000, 950000, 925000, 900000, 875000 },//200MHz
- { 950000, 925000, 900000, 875000, 850000 },//100MHz
- { 925000, 900000, 875000, 850000, 825000 },//50MHz
- { 900000, 875000, 850000, 825000, 800000 },//25MHz
+ { 1350000, 1350000, 1300000, 1250000, 1225000 },
+ { 1325000, 1275000, 1225000, 1175000, 1150000 },
+ { 1225000, 1175000, 1125000, 1075000, 1050000 },
+ { 1150000, 1100000, 1050000, 1000000, 975000 },
+ { 1050000, 1000000, 950000, 950000, 950000 },
+ { 1025000, 975000, 950000, 950000, 950000 },
+
};
static void set_clkdiv(unsigned int div_index)
@@ -501,11 +310,11 @@ static void __init set_volt_table(void)
break;
case SUPPORT_1000MHZ:
for_1000 = true;
- max_support_idx = L7;
+ max_support_idx = L2;
break;
default:
for_1000 = true;
- max_support_idx = L7;
+ max_support_idx = L2;
break;
}
@@ -605,8 +414,8 @@ int exynos4210_cpufreq_init(struct exynos_dvfs_info *info)
}
info->mpll_freq_khz = rate;
- info->pm_lock_idx = L9;
- info->pll_safe_idx = L7;
+ info->pm_lock_idx = L3;
+ info->pll_safe_idx = L2;
info->max_support_idx = max_support_idx;
info->min_support_idx = min_support_idx;
info->cpu_clk = cpu_clk;
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