This project simulates the designed Pulse Width Modulated Wave Generator with Variable Duty Cycle. We can generate PWM wave and varry its DUTYCYCLE in steps of 10%
Note: Circuit requires further optimization to improve performance. Design yet to be modified.
Pulse Width Modulation is a famous technique used to create modulated electronic pulses of the desired width. The duty cycle is the ratio of how long that PWM signal stays at the high position to the total time period.
Pulse Width Modulated Wave Generator can be used to
- control the brightness of the LED
- drive buzzers at different loudnes
- control the angle of the servo motor
- encode messages in telecommunication
- used in speed controlers of motors
This PWM generator generates 10Mhz signal. We can control duty cycles in steps of 10%. The default duty cycle is 50%. Along with clock signal we provide another two external signals to increase and decrease the duty cycle.
In this specific circuit, we mainly require a n-bit counter and comparator. Duty given to the comparator is compared with the current value of the counter. If current value of counter is lower than duty then comparator results in output high. Similarly, If current value of counter is higher than duty is then comparator results in output low. As counter starts at zero, initially comparator gives high output and when counter crosses duty it becomes low. Hence by controlling duty, we can control duty cycle.
As the comparator is a combinational circuit and the counter is sequential, while counting from 011 to 100 due to improper delays there might be an intermediate state like 111 which might be higher or lower than duty. This might cause a glitch. To avoid these glitches output of the comparator is passed through a D flipflop.
Icarus Verilog is an implementation of the Verilog hardware description language.
GTKWave is a fully featured GTK+ v1. 2 based wave viewer for Unix and Win32 which reads Ver Structural Verilog Compiler generated AET files as well as standard Verilog VCD/EVCD files and allows their viewing
Open your terminal and type the following to install iverilog and GTKWave
$ sudo apt-get update
$ sudo apt-get install iverilog gtkwave
To clone the Repository and download the Netlist files for Simulation, enter the following commands in your terminal.
$ sudo apt install -y git
$ git clone https://github.com/sanampudig/iiitb_pwm_gen
$ cd iiitb_pwm_gen
$ iverilog iiitb_pwm_gen.v iiitb_pwm_gen_tb.v
$ ./a.out
$ gtkwave pwm.vcd
Simulation Results while increasing Dutycycle
Simulation Results while decreasing Dutycycle
Synthesis: Synthesis transforms the simple RTL design into a gate-level netlist with all the constraints as specified by the designer. In simple language, Synthesis is a process that converts the abstract form of design to a properly implemented chip in terms of logic gates.
Synthesis takes place in multiple steps:
- Converting RTL into simple logic gates.
- Mapping those gates to actual technology-dependent logic gates available in the technology libraries.
- Optimizing the mapped netlist keeping the constraints set by the designer intact.
Synthesizer: It is a tool we use to convert out RTL design code to netlist. Yosys is the tool I've used in this project.
Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
- more at https://yosyshq.net/yosys/
To install yosys follow the instructions in this github repository
https://github.com/YosysHQ/yosys
Now you need to create a yosys_run.sh file , which is the yosys script file used to run the synthesis. The contents of the yosys_run file are given below:
- note: Identify the .lib file path in cloned folder and change the path in highlighted text to indentified path
Now, in the terminal of your verilog files folder, run the following commands:
- Run the following commands to syhthesize
$ yosys
$ yosys> script yosys_run.sh
- To see diffarent types of cells after synthesys
$ yosys> stat
- To generate schematics
$ yosys> show
Now the synthesized netlist is written in iiitb_pwm_gen_synth.v file.
GLS is generating the simulation output by running test bench with netlist file generated from synthesis as design under test. Netlist is logically same as RTL code, therefore, same test bench can be used for it.We perform this to verify logical correctness of the design after synthesizing it. Also ensuring the timing of the design is met.
Folllowing are the commands to run the GLS simulation:
iverilog -DFUNCTIONAL -DUNIT_DELAY=#1 ../verilog_model/primitives.v ../verilog_model/sky130_fd_sc_hd.v iiitb_pwm_gen_synth.v iiitb_pwm_gen_tb.v
./a.out
gtkwave pwm.vcd
The gtkwave output for the netlist should match the output waveform for the RTL design file. As netlist and design code have same set of inputs and outputs, we can use the same testbench and compare the waveforms.
- Simulation Results while increasing Dutycycle
- Simulation Results while decreasing Dutycycle
Output characteristics of Functional simulation is matched with output of Gate Level Simulation.
Place and Route (PnR) is the core of any ASIC implementation and Openlane flow integrates into it several key open source tools which perform each of the respective stages of PnR. Below are the stages and the respective tools that are called by openlane for the functionalities as described:
OpenLANE utilises a variety of opensource tools in the execution of the ASIC flow:
| Task | Tool/s |
|---|---|
| RTL Synthesis & Technology Mapping | yosys, abc |
| Floorplan & PDN | init_fp, ioPlacer, pdn and tapcell |
| Placement | RePLace, Resizer, OpenPhySyn & OpenDP |
| Static Timing Analysis | OpenSTA |
| Clock Tree Synthesis | TritonCTS |
| Routing | FastRoute and TritonRoute |
| SPEF Extraction | SPEF-Extractor |
| DRC Checks, GDSII Streaming out | Magic, Klayout |
| LVS check | Netgen |
| Circuit validity checker | CVC |
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, CVC, SPEF-Extractor, CU-GR, Klayout and a number of custom scripts for design exploration and optimization. The flow performs full ASIC implementation steps from RTL all the way down to GDSII.
- Synthesis
yosys- Performs RTL synthesisabc- Performs technology mappingOpenSTA- Performs static timing analysis on the resulting netlist to generate timing reports
- Floorplan and PDN
init_fp- Defines the core area for the macro as well as the rows (used for placement) and the tracks (used for routing)ioplacer- Places the macro input and output portspdn- Generates the power distribution networktapcell- Inserts welltap and decap cells in the floorplan
- Placement
RePLace- Performs global placementResizer- Performs optional optimizations on the designOpenDP- Perfroms detailed placement to legalize the globally placed components
- CTS
TritonCTS- Synthesizes the clock distribution network (the clock tree)
- Routing
FastRoute- Performs global routing to generate a guide file for the detailed routerCU-GR- Another option for performing global routing.TritonRoute- Performs detailed routingSPEF-Extractor- Performs SPEF extraction
- GDSII Generation
Magic- Streams out the final GDSII layout file from the routed defKlayout- Streams out the final GDSII layout file from the routed def as a back-up
- Checks
Magic- Performs DRC Checks & Antenna ChecksKlayout- Performs DRC ChecksNetgen- Performs LVS ChecksCVC- Performs Circuit Validity Checks
more at https://github.com/The-OpenROAD-Project/OpenLane
$ apt install -y build-essential python3 python3-venv python3-pip
-
Docker installation process: https://docs.docker.com/engine/install/ubuntu/
-
Goto home directory->
$ git clone https://github.com/The-OpenROAD-Project/OpenLane.git
$ cd OpenLane/
$ sudo make
- To test the Openlane
$ sudo make test
It takes approximate time of 5min to complete. After 43 steps, if it ended with saying Basic test passed then open lane installed succesfully.
Magic is a venerable VLSI layout tool, written in the 1980's at Berkeley by John Ousterhout, now famous primarily for writing the scripting interpreter language Tcl. Due largely in part to its liberal Berkeley open-source license, magic has remained popular with universities and small companies. The open-source license has allowed VLSI engineers with a bent toward programming to implement clever ideas and help magic stay abreast of fabrication technology. However, it is the well thought-out core algorithms which lend to magic the greatest part of its popularity. Magic is widely cited as being the easiest tool to use for circuit layout, even for people who ultimately rely on commercial tools for their product design flow.
More about magic at http://opencircuitdesign.com/magic/index.html
Run following commands one by one to fulfill the system requirement.
$ sudo apt-get install m4
$ sudo apt-get install tcsh
$ sudo apt-get install csh
$ sudo apt-get install libx11-dev
$ sudo apt-get install tcl-dev tk-dev
$ sudo apt-get install libcairo2-dev
$ sudo apt-get install mesa-common-dev libglu1-mesa-dev
$ sudo apt-get install libncurses-dev
To install magic Goto home directory
$ git clone https://github.com/RTimothyEdwards/magic
$ cd magic/
$ ./configure
$ sudo make
$ sudo make install
Type magic terminal to check whether it installed succesfully or not. type exit to exit magic.
NON-INTERACTIVE MODE: Here we are generating the layout in the non-interactive mode or the automatic mode. In this we cant interact with the flow in the middle of each stage of the flow.The flow completes all the stages starting from synthesis until you obtain the final layout and the reports of various stages which specify the violations and problems if present during the flow.
- Open terminal in home directory
$ cd OpenLane/
$ cd designs/
$ mkdir iiitb_pwm_gen
$ cd iiitb_pwm_gen/
$ wget https://raw.githubusercontent.com/sanampudig/iiitb_pwm_gen/main/config.json
$ mkdir src
$ cd src/
$ wget https://raw.githubusercontent.com/sanampudig/iiitb_pwm_gen/main/iiitb_pwm_gen.v
$ cd ../../../
$ sudo make mount
$ ./flow.tcl -design iiitb_pwm_gen
To see the layout we use a tool called magic which we installed earlier.
Open terminal in home directory
$ cd OpenLane/designs/iiitb_pwm_gen/run
$ ls
Select most run directoy from list
Example:
$ cd RUN_2022.08.24_18.20.10
Run following instruction
$ cd results/final/def
Update the highlited text with appropriate path
$ magic -T /home/parallels/Desktop/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../../tmp/merged.max.lef def read iiitb_pwm_gen.def &
Layout will be open in new window
- The final layout obtained after the completion of the flow in non-interactive mode is shown below:
Here we are going to customise our layout by including our custom made sky130_vsdinv cell into our layout.
-
CREATING THE SKY130_VSDINV CELL LEF FILE
-You need to first get the git repository of the vsdstdccelldesign.To get the repository type the following command:
$ git clone https://github.com/nickson-jose/vsdstdcelldesign
-
Now you need to copy your tech file sky130A.tech to this folder.
-
Next run the magic command to open the sky130_vsdinv.mag file.Use the following command:
$ magic -T sky130A.tech sky130_inv.mag
- One can zoom into Magic layout by selecting an area with left and right mouse click followed by pressing "z" key.
- Various components can be identified by using the what command in tkcon window after making a selection on the component.
- The image showing the invoked magic tool using the above command:
- The next step is setting
port classandport useattributes. The "class" and "use" properties of the port have no internal meaning to magic but are used by the LEF and DEF format read and write routines, and match the LEF/DEF CLASS and USE properties for macro cell pins. These attributes are set in tkcon window (after selecting each port on layout window. A keyboard shortcut would be,repeatedly pressing s till that port gets highlighed).
The tkcon command window of the port classification is shown in the image below:
- In the next step, use
lef writecommand to write the LEF file with the same nomenclature as that of the layout.magfile. This will create a sky130_vsdinv.lef file in the same folder.
in tkcon terminal type the following command to generate .lef file
% lef write sky130_vsdinv
Copy the generated lef file to designs/iiit_pwm_gen/src Also copy lib files from vsdcelldesign/libs to designs/iiit_pwm_gen/src
- Next modify the
config.jsonfile in our design to folloing code:
{
"DESIGN_NAME": "iiitb_pwm_gen",
"VERILOG_FILES": "dir::src/iiitb_pwm_gen.v",
"CLOCK_PORT": "clk",
"CLOCK_NET": "clk",
"FP_SIZING": "relative",
"LIB_SYNTH" : "dir::src/sky130_fd_sc_hd__typical.lib",
"LIB_FASTEST" : "dir::src/sky130_fd_sc_hd__fast.lib",
"LIB_SLOWEST" : "dir::src/sky130_fd_sc_hd__slow.lib",
"LIB_TYPICAL":"dir::src/sky130_fd_sc_hd__typical.lib",
"TEST_EXTERNAL_GLOB":"dir::../sd_fsm/src/*",
"SYNTH_DRIVING_CELL":"sky130_vsdinv",
"pdk::sky130*": {
"FP_CORE_UTIL": 35,
"CLOCK_PERIOD": 24,
"scl::sky130_fd_sc_hd": {
"FP_CORE_UTIL": 30
}
}
}
this config file is avilable in repo under name config1.json.
Goto openlane directory and open terminal there
$ sudo make mount
-
INTERACTIVE MODE: We need to run the openlane now in the interactive mode to include our custom made lef file before synthesis.Such that the openlane recognises our lef files during the flow for mapping.
-
Running openlane in interactive mode: The commands to the run the flow in interactive mode is given below:
$ ./flow.tcl -interactive
Loading the package file
% package require openlane 0.9
- Preparing the design and including the lef files: The commands to prepare the design and overwite in a existing run folder the reports and results along with the command to include the lef files is given below:
% prep -design iiitb_pwm_gen
Include the below command to include the additional lef (i.e sky130_vsdinv) into the flow:
% set lefs [glob $::env(DESIGN_DIR)/src/*.lef]
% add_lefs -src $lefs
Logic synthesis uses the RTL netlist to perform HDL technology mapping. The synthesis process is normally performed in two major steps:
-
GTECH Mapping – Consists of mapping the HDL netlist to generic gates what are used to perform logical optimization based on AIGERs and other topologies created from the generic mapped netlist.
-
Technology Mapping – Consists of mapping the post-optimized GTECH netlist to standard cells described in the PDK
To synthesize the code run the following command
% run_synthesis
Post synthesis stat
Number of D Flip flops
Flop ratio = -------------------------
Total Number of cells
Goal is to plan the silicon area and create a robust power distribution network (PDN) to power each of the individual components of the synthesized netlist. In addition, macro placement and blockages must be defined before placement occurs to ensure a legalized GDS file. In power planning we create the ring which is connected to the pads which brings power around the edges of the chip. We also include power straps to bring power to the middle of the chip using higher metal layers which reduces IR drop and electro-migration problem.
-
- Importance of files in increasing priority order:
floorplan.tcl- System default envrionment variablesconifg.tclsky130A_sky130_fd_sc_hd_config.tcl -
- Floorplan envrionment variables or switches:
FP_CORE_UTIL- floorplan core utilisationFP_ASPECT_RATIO- floorplan aspect ratioFP_CORE_MARGIN- Core to die margin areaFP_IO_MODE- defines pin configurations (1 = equidistant/0 = not equidistant)FP_CORE_VMETAL- vertical metal layerFP_CORE_HMETAL- horizontal metal layer
-
Note: Usually, vertical metal layer and horizontal metal layer values will be 1 more than that specified in the file
-
Following command helps to run floorplan
% run_floorplan
-
Post the floorplan run, a .def file will have been created within the results/floorplan directory. We may review floorplan files by checking the floorplan.tcl. The system defaults will have been overriden by switches set in conifg.tcl and further overriden by switches set in sky130A_sky130_fd_sc_hd_config.tcl.
-
To view the floorplan: Magic is invoked after moving to the results/floorplan directory,then use the floowing command:
magic -T /home/parallels/Desktop/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.nom.lef def read iiitb_pwm_gen.def &
floorplan
Die area (post floor plan)
Core area (post floor plan)
Place the standard cells on the floorplane rows, aligned with sites defined in the technology lef file. Placement is done in two steps: Global and Detailed. In Global placement tries to find optimal position for all cells but they may be overlapping and not aligned to rows, detailed placement takes the global placement and legalizes all of the placements trying to adhere to what the global placement wants.
- The next step in the OpenLANE ASIC flow is placement. The synthesized netlist is to be placed on the floorplan. Placement is perfomed in 2 stages:
- Global Placement: It finds optimal position for all cells which may not be legal and cells may overlap. Optimization is done through reduction of half parameter wire length.
- Detailed Placement: It alters the position of cells post global placement so as to legalise them.
run the following command to run the placement
% run_placement
- Post placement: the design can be viewed on magic within
results/placementdirectory. Run the follwing command in that directory:
magic -T /home/parallels/Desktop/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.nom.lef def read iiitb_pwm_gen.def &
-
Clock tree synteshsis is used to create the clock distribution network that is used to deliver the clock to all sequential elements. The main goal is to create a network with minimal skew across the chip. H-trees are a common network topology that is used to achieve this goal.
-
The purpose of building a clock tree is enable the clock input to reach every element and to ensure a zero clock skew. H-tree is a common methodology followed in CTS. Before attempting a CTS run in TritonCTS tool, if the slack was attempted to be reduced in previous run, the netlist may have gotten modified by cell replacement techniques. Therefore, the verilog file needs to be modified using the
write_verilogcommand. Then, the synthesis, floorplan and placement is run again -
Run the following command to perform CTS
% run_cts
Implements the interconnect system between standard cells using the remaining available metal layers after CTS and PDN generation. The routing is performed on routing grids to ensure minimal DRC errors.
-
- OpenLANE uses the TritonRoute tool for routing. There are 2 stages of routing:
- Global routing: Routing region is divided into rectangle grids which are represented as course 3D routes (Fastroute tool).
- Detailed routing: Finer grids and routing guides used to implement physical wiring (TritonRoute tool).
- Features of TritonRoute:
- Honouring pre-processed route guides
- Assumes that each net satisfies inter guide connectivity
- Uses MILP based panel routing scheme
- Intra-layer parallel and inter-layer sequential routing framework
Run the following command to run the routing
% run_routing
Do know in routing stage
run_routing- To start the routing- The options for routing can be set in the
config.tclfile. The optimisations in routing can also be done by specifying the routing strategy to use different version ofTritonRoute Engine. There is a trade0ff between the optimised route and the runtime for routing. The routing stage must have theCURRENT_DEFset topdn.def. The two stages of routing are performed by the following engines: Global Route : Fast Route Detailed Route : Triton Route Fast Route generates the routing guides, whereas Triton Route uses the Global Route and then completes the routing with some strategies and optimisations for finding the best possible path connect the pins. - Layout in magic tool post routing: the design can be viewed on magic within
results/routingdirectory. Run the follwing command in that directory:
magic -T /home/parallels/Desktop/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.nom.lef def read iiitb_pwm_gen.def &
in tkcon type the follow command to check where sky130_vsdinv exist or not
% getcell sky130_vsdinv
Seven sky130_vsdinv cells present in design
sky130_vsdinv _ 138 _
sky130_vsdinv _ 158 _
sky130_vsdinv _ 167 _
sky130_vsdinv _ 169 _
sky130_vsdinv _ 170 _
sky130_vsdinv _ 171 _
sky130_vsdinv _ 172 _
Static timing analysis (STA) is a method of validating the timing performance of a design by checking all possible paths for timing violations. STA breaks a design down into timing paths, calculates the signal propagation delay along each path, and checks for violations of timing constraints inside the design and at the input/output interface.
How does STA work? When performing timing analysis, STA first breaks down the design into timing paths. Each timing path consists of the following elements:
Startpoint The start of a timing path where data is launched by a clock edge or where the data must be available at a specific time. Every startpoint must be either an input port or a register clock pin.
Combinational logic network Elements that have no memory or internal state. Combinational logic can contain AND, OR, XOR, and inverter elements, but cannot contain flip-flops, latches, registers, or RAM.
Endpoint The end of a timing path where data is captured by a clock edge or where the data must be available at a specific time. Every endpoint must be either a register data input pin or an output port.
- To run STA in
Openlaneand typestato enter openSTA
- Run the following commands
% read_liberty -min /home/parallels/Desktop/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v56.lib
% read_liberty -max /home/parallels/Desktop/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v56.lib
% read_verilog /home/parallels/Desktop/OpenLane/pdks/sky130A/iiitb_pwm_gen.v
% link_design iiitb_pwm_gen
% read_sdc /home/parallels/Desktop/OpenLane/pdks/sky130A/iiitb_pwm_gen.sdc
% set_propagated_clock [all_clocks]
% report_checks
- To report the particular path use the following command
% report_checks -from _247_ -to _244_
% report_check -from _247_ -to _245_
1
Maximum Possible Operating Frequency = -----------------------------
Clock period - Setup Slack
1
= ---------------------
65ns - 61.36ns
= 0.274725275 GHz
Number of cells: 179
Area=6586.0834 micrometre^2
Performance = 0.274725275 GHz
flip-flop to standard cell ratio = 40/179 = 0.2235
Total power = 0.137mW
The shuttle provides opportunities for designers to experiment and push the state-of-the-art without having to reconcile the risk associated with the cost of fabrication.
The shuttle program is open to anyone, provided that their project is fully open source and meets the other program requirements.
Costs for fabrication, packaging, evaluation boards and shipping are covered by Google for this program.
more at: https://efabless.com/open_shuttle_program
- Repo submitted to MPW7 program: https://github.com/sanampudig/efabless
- Tapeout link: https://platform.efabless.com/projects/1366
- Sanampudi Gopala Krishna Reddy
- Kunal Ghosh
- Kunal Ghosh, Director, VSD Corp. Pvt. Ltd.
- Nickson Jose, SoC Physical Design Engineer, Intel.
- Vinay Rayapati, Postgraduate Student, International Institute of Information Technology, Bangalore
- Gogireddy Ravi Kiran Reddy, Postgraduate Student, International Institute of Information Technology, Bangalore
- Sanampudi Gopala Krishna Reddy, Postgraduate Student, International Institute of Information Technology, Bangalore svgkr7@gmail.com
- Kunal Ghosh, Director, VSD Corp. Pvt. Ltd. kunalghosh@gmail.com