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Fix assembling ARM vst2 instructions with double-spaced registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153099 91177308-0d34-0410-b5e6-96231b3b80d8
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commit 9f2e160f7ae90a7a80b17e38ad06f2c706515115 1 parent 07cdd80
Kevin Enderby authored
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2  lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -1102,7 +1102,7 @@ class ARMOperand : public MCParsedAsmOperand {
}
bool isVecListDPairSpaced() const {
- if (!isSingleSpacedVectorList()) return false;
+ if (isSingleSpacedVectorList()) return false;
return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
.contains(VectorList.RegNum));
}
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4 test/MC/ARM/neon-vst-encoding.s
@@ -264,3 +264,7 @@
@ CHECK: vst1.8 {d4, d5}, [r2] @ encoding: [0x0f,0x4a,0x02,0xf4]
@ CHECK: vst1.8 {d4, d5}, [r2] @ encoding: [0x0f,0x4a,0x02,0xf4]
@ CHECK: vst1.32 {d4, d5}, [r2] @ encoding: [0x8f,0x4a,0x02,0xf4]
+
+@ rdar://11082188
+ vst2.8 {d8, d10}, [r4]
+@ CHECK: vst2.8 {d8, d10}, [r4] @ encoding: [0x0f,0x89,0x04,0xf4]
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4 test/MC/ARM/neont2-vst-encoding.s
@@ -101,3 +101,7 @@
vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0, :64]
@ CHECK: vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] @ encoding: [0x4f,0x1b,0xc0,0xf9]
vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0]
+
+@ rdar://11082188
+ vst2.8 {d8, d10}, [r4]
+@ CHECK: vst2.8 {d8, d10}, [r4] @ encoding: [0x04,0xf9,0x0f,0x89]
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