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Commits on Apr 8, 2012
  1. Draft.

Commits on Apr 7, 2012
  1. Turn avx2 vinserti128 intrinsic calls into INSERT_SUBVECTOR DAG nodes…

    Craig Topper authored
    … and remove patterns for selecting the intrinsic. Similar was already done for avx1.
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
  2. Move vinsertf128 patterns near the instruction definitions. Add Added…

    Craig Topper authored
    …Complexity to AVX2 vextracti128 patterns to give them priority over the integer versions of vextractf128 patterns.
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
  3. Remove 'else' after 'if' that ends in return.

    Craig Topper authored
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
  4. @nadavrot

    1. Remove the part of r153848 which optimizes shuffle-of-shuffle into…

    nadavrot authored
    … a new
       shuffle node because it could introduce new shuffle nodes that were not
       supported efficiently by the target.
    2. Add a more restrictive shuffle-of-shuffle optimization for cases where the
       second shuffle reverses the transformation of the first shuffle.
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
  5. @CunningBaldrick

    Convert floating point division by a constant into multiplication by the

    CunningBaldrick authored
    reciprocal if converting to the reciprocal is exact.  Do it even if inexact
    if -ffast-math.  This substantially speeds up ac.f90 from the polyhedron
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
  6. @chandlerc

    Perform partial SROA on the helper hashing structure. I really wish the

    chandlerc authored
    optimizers could do this for us, but expecting partial SROA of classes
    with template methods through cloning is probably expecting too much
    heroics. With this change, the begin/end pointer pairs which indicate
    the status of each loop iteration are actually passed directly into each
    layer of the combine_data calls, and the inliner has a chance to see
    when most of the combine_data function could be deleted by inlining.
    Similarly for 'length'.
    We have to be careful to limit the places where in/out reference
    parameters are used as those will also defeat the inliner / optimizers
    from properly propagating constants.
    With this change, LLVM is able to fully inline and unroll the hash
    computation of small sets of values, such as two or three pointers.
    These now decompose into essentially straight-line code with no loops or
    function calls.
    There is still one code quality problem to be solved with the hashing --
    LLVM is failing to nuke the alloca. It removes all loads from the
    alloca, leaving only lifetime intrinsics and dead(!!) stores to the
    alloca. =/ Very unfortunate.
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
  7. @chandlerc

    Fix ValueTracking to conclude that debug intrinsics are safe to

    chandlerc authored
    speculate. Without this, loop rotate (among many other places) would
    suddenly stop working in the presence of debug info. I found this
    looking at loop rotate, and have augmented its tests with a reduction
    out of a very hot loop in yacr2 where failing to do this rotation costs
    sometimes more than 10% in runtime performance, perturbing numerous
    downstream optimizations.
    This should have no impact on performance without debug info, but the
    change in performance when debug info is enabled can be extreme. As
    a consequence (and this how I got to this yak) any profiling of
    performance problems should be treated with deep suspicion -- they may
    have been wildly innacurate of debug info was enabled for profiling. =/
    Just a heads up.
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
  8. @d0k

    SCEV: When expanding a GEP the final addition to the base pointer has…

    d0k authored
    … NUW but not NSW.
    Found by inspection.
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
  9. Fix Thumb __builtin_longjmp with integrated assembler. <rdar://proble…

    Bob Wilson authored
    The tLDRr instruction with the last register operand set to the zero register
    prints in assembly as if no register was specified, and the assembler encodes
    it as a tLDRi instruction with a zero immediate.  With the integrated assembler,
    that zero register gets emitted as "r0", so we get "ldr rx, [ry, r0]" which
    is broken.  Emit the instruction as tLDRi with a zero immediate.  I don't
    know if there's a good way to write a testcase for this.  Suggestions welcome.
    Opportunities for follow-up work:
    1) The asm printer should complain if a non-optional register operand is set
       to the zero register, instead of silently dropping it.
    2) The integrated assembler should complain in the same situation, instead of
       silently emitting the operand as "r0".
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
  10. @etherzhhb
  11. @chapuni

    Target/X86/MCTargetDesc/X86MCAsmInfo.cpp: Enable DwarfCFI (aka DW2) o…

    chapuni authored
    …n Cygming.
    Cygwin-1.7 supports dw2. Some recent mingw distros support one, too.
    I have confirmed test-suite/SingleSource/Benchmarks/Shootout-C++/except.cpp can pass on Cygwin.
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
  12. @scshunt
  13. @scshunt

    Output UTF-8-encoded characters as identifier characters into assembly

    scshunt authored
    by default.
    This is a behaviour configurable in the MCAsmInfo. I've decided to turn
    it on by default in (possibly optimistic) hopes that most assemblers are
    reasonably sane. If this proves a problem, switching to default seems
    I'm not sure if this is the opportune place to test, but it seemed good
    to make sure it was tested somewhere.
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
Commits on Apr 6, 2012
  1. Tidy up. 80 columns.

    Jim Grosbach authored
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
  2. ARMPat is equivalent to Requires<[IsARM]>.

    Jakob Stoklund Olesen authored
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
  3. Eliminate iOS-specific tail call instructions.

    Jakob Stoklund Olesen authored
    After register masks were introdruced to represent the call clobbers, it
    is no longer necessary to have duplicate instruction for iOS.
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
  4. Add lines in global-address.ll to test N32 and N64 code generation.

    Akira Hatanaka authored
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
  5. @chandlerc

    There is no portable std::abs overload for int64_t, use the llvm::abs64

    chandlerc authored
    which exists for this purpose.
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
  6. Fixed two leaks in the MC disassembler. The MC

    Sean Callanan authored
    disassembler requires a MCSubtargetInfo and a
    MCInstrInfo to exist in order to initialize the
    instruction printer and disassembler; however,
    although the printer and disassembler keep
    references to these objects they do not own them.
    Previously, the MCSubtargetInfo and MCInstrInfo
    objects were just leaked.
    I have extended LLVMDisasmContext to own these
    objects and delete them when it is destroyed.
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
  7. Allow negative immediates in ARM and Thumb2 compares.

    Jakob Stoklund Olesen authored
    ARM and Thumb2 mode can use cmn instructions to compare against negative
    immediates. Thumb1 mode can't.
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
  8. Reintroduce InlineCostAnalyzer::getInlineCost() variant with explicit…

    David Chisnall authored
    … callee
    parameter until we have a more sensible API for doing the same thing.
    Reviewed by Chandler.
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
  9. @chandlerc

    Sink the collection of return instructions until after *all*

    chandlerc authored
    simplification has been performed. This is a bit less efficient
    (requires another ilist walk of the basic blocks) but shouldn't matter
    in practice. More importantly, it's just too much work to keep track of
    all the various ways the return instructions can be mutated while
    simplifying them. This fixes yet another crasher, reported by Daniel
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
  10. @chandlerc

    Tweak this test to ensure the inliner did indeed fire. Thanks to Richard

    chandlerc authored
    Smith for pointing this out in review.
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
  11. @CunningBaldrick

    Make GVN's propagateEquality non-recursive. No intended functionality…

    CunningBaldrick authored
    … change.
    The modifications are a lot more trivial than they appear to be in the diff!
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
  12. Test case for PR12413

    Craig Topper authored
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
  13. @d0k

    Fix narrowing conversion.

    d0k authored
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
  14. @d0k

    DenseMap: Perform the pod-like object optimization when the value typ…

    d0k authored
    …e is POD-like, not the DenseMapInfo for it.
    Purge now unused template arguments. This has been broken since r91421. Patch by Lubos Lunak!
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
  15. Allow 256-bit shuffles to be split if a 128-bit lane contains element…

    Craig Topper authored
    …s from a single source. This is a rewrite of the 256-bit shuffle splitting code based on similar code from legalize types. Fixes PR12413.
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
  16. Add the tests that were supposed to go with r153935 that I forgot svn…

    Craig Topper authored
    … add
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
  17. @chandlerc

    Actually finish this sentence in the comment the way I intended. Thanks

    chandlerc authored
    Matt for pointing this out.
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
  18. @chandlerc

    Sink the return instruction collection until after we're done deleting

    chandlerc authored
    dead code, including dead return instructions in some cases. Otherwise,
    we end up having a bogus poniter to a return instruction that blows up
    much further down the road.
    It turns out that this pattern is both simpler to code, easier to update
    in the face of enhancements to the inliner cleanup, and likely cheaper
    given that it won't add dead instructions to the list.
    Thanks to John Regehr's numerous test cases for teasing this out.
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
  19. Deduplicate ARM call-related instructions.

    Jakob Stoklund Olesen authored
    We had special instructions for iOS because r9 is call-clobbered, but
    that is represented dynamically by the register mask operands now, so
    there is no need for the pseudo-instructions.
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
Commits on Apr 5, 2012
  1. ARM: Don't form a t2LDRi8 or t2STRi8 with an offset of zero.

    Jim Grosbach authored
    The load/store optimizer splits LDRD/STRD into two instructions when the
    register pairing doesn't work out. For negative offsets in Thumb2, it uses
    t2STRi8 to do that. That's fine, except for the case when the offset is in
    the range [-4,-1]. In that case, we'll also form a second t2STRi8 with
    the original offset plus 4, resulting in a t2STRi8 with a non-negative
    offset, which ends up as if it were an STRT, which is completely bogus.
    Similarly for loads.
    No testcase, unfortunately, as any I've been able to construct is both large
    and extremely fragile.
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
  2. Fix the build breakage introduced by r154131.

    Kaelyn Uhrain authored
    The empty 1-argument operator delete is for the benefit of the
    destructor. A couple of spot checks of running yaml-bench under
    valgrind against a few of the files under test/YAMLParser did
    not reveal any leaks introduced by this change.
    git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
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