From 3fb3cec0128976ceebbbf286402e575d3f343fa1 Mon Sep 17 00:00:00 2001 From: Pirmin Vogel Date: Tue, 30 Nov 2021 16:59:51 +0100 Subject: [PATCH] Upgrade bitmanip v.0.92 to v.0.93, enable simultaneous use with v.1.00 The main changes implemented by this PR are: 1. Support for bitmanip draft v.0.92 is dropped. 2. Remaining bitmanip instructions not ratified as part of v.1.00 of the bitmanip spec are upgraded to the latest draft (v.0.93). 3. Simultaneous use of the v.1.00 bitmanip instructions and those instructions only part of draft v.0.93 is enabled. 4. Rename bext/bdep to bcompress/bdecompress. This is part of v.0.94. But it's needed as in v.0.93 as well as in v.1.00 sbext from Zbs is renamed to bext, leading to two completely different instructions having the same name. 5. Increase the MAX_INSTR_STR_LEN parameter to accomodate longer instruction names (bdecompressw has 12 characters). Signed-off-by: Pirmin Vogel --- src/isa/riscv_b_instr.sv | 213 +++------------- src/isa/rv32b_instr.sv | 89 +++---- src/isa/rv32zba_instr.sv | 3 +- src/isa/rv32zbb_instr.sv | 3 +- src/isa/rv32zbc_instr.sv | 3 +- src/isa/rv32zbs_instr.sv | 3 +- src/isa/rv64b_instr.sv | 65 ++--- src/isa/rv64zba_instr.sv | 3 +- src/isa/rv64zbb_instr.sv | 3 +- src/riscv_instr_cover_group.sv | 432 +++++++-------------------------- src/riscv_instr_gen_config.sv | 6 - src/riscv_instr_pkg.sv | 127 +++------- 12 files changed, 215 insertions(+), 735 deletions(-) mode change 100755 => 100644 src/isa/riscv_b_instr.sv diff --git a/src/isa/riscv_b_instr.sv b/src/isa/riscv_b_instr.sv old mode 100755 new mode 100644 index 22c7b7f7..335c5e42 --- a/src/isa/riscv_b_instr.sv +++ b/src/isa/riscv_b_instr.sv @@ -31,7 +31,7 @@ class riscv_b_instr extends riscv_instr; has_rs3 = 1'b0; case (format) inside R_FORMAT: begin - if (instr_name inside {CLZW, CTZW, PCNTW, SEXT_B, SEXT_H, CLZ, CTZ, PCNT, BMATFLIP, + if (instr_name inside {BMATFLIP, CRC32_B, CRC32_H, CRC32_W, CRC32C_B, CRC32C_H, CRC32C_W, CRC32_D, CRC32C_D}) begin has_rs2 = 1'b0; @@ -61,21 +61,12 @@ class riscv_b_instr extends riscv_instr; if (format inside {I_FORMAT}) begin if (category inside {SHIFT, LOGICAL}) begin - if (group == RV64B && !(instr_name inside {SLLIU_W})) begin - imm_len = $clog2(XLEN) - 1; - end else begin - imm_len = $clog2(XLEN); - end + imm_len = $clog2(XLEN); end - // ARITHMETIC RV32B if (instr_name inside {SHFLI, UNSHFLI}) begin imm_len = $clog2(XLEN) - 1; end - // ARITHMETIC RV64B - if (instr_name inside {ADDIWU}) begin - imm_len = 12; - end end imm_mask = imm_mask << imm_len; @@ -117,63 +108,38 @@ class riscv_b_instr extends riscv_instr; function bit [6:0] get_opcode(); case (instr_name) inside - ANDN, ORN, XNOR, GORC, SLO, SRO, ROL, ROR, SBCLR, SBSET, SBINV, SBEXT, - GREV: get_opcode = 7'b0110011; - SLOI, SROI, RORI, SBCLRI, SBSETI, SBINVI, SBEXTI, GORCI, GREVI, CMIX, CMOV, - FSL: get_opcode = 7'b0010011; - FSR, FSRI, CLZ, CTZ, PCNT, BMATFLIP, SEXT_B, SEXT_H, CRC32_B, CRC32_H, CRC32_W, CRC32C_B, - CRC32C_H: get_opcode = 7'b0010011; + GORC, SLO, SRO, GREV, XPERM_N, XPERM_B, XPERM_H, XPERM_W: get_opcode = 7'b0110011; + GORCI, SLOI, SROI, GREVI, CMIX, CMOV, FSL: get_opcode = 7'b0010011; + FSR, FSRI, BMATFLIP, CRC32_B, CRC32_H, CRC32_W, CRC32C_B, CRC32C_H: get_opcode = 7'b0010011; CRC32C_W, CRC32_D, CRC32C_D: get_opcode = 7'b0010011; - CLMUL, CLMULR, CLMULH, MIN, MAX, MINU, MAXU, SHFL, UNSHFL, BDEP, BEXT, PACK, PACKU, BMATOR, - BMATXOR, PACKH, BFP: get_opcode = 7'b0110011; + SHFL, UNSHFL, BCOMPRESS, BDECOMPRESS, PACK, PACKU, BMATOR, BMATXOR, PACKH, BFP: get_opcode + = 7'b0110011; SHFLI, UNSHFLI: get_opcode = 7'b0010011; - ADDIWU, SLLIU_W: get_opcode = 7'b0011011; - ADDWU, SUBWU, ADDU_W, SUBU_W, SLOW, SROW, ROLW, RORW, SBCLRW, SBSETW, SBINVW, SBEXTW, GORCW, - GREVW: get_opcode = 7'b0111011; - SLOIW, SROIW, RORIW, SBCLRIW, SBSETIW, SBINVIW, GORCIW, GREVIW: get_opcode = 7'b0011011; + SLOW, SROW, GORCW, GREVW: get_opcode = 7'b0111011; + SLOIW, SROIW, GORCIW, GREVIW: get_opcode = 7'b0011011; FSLW, FSRW: get_opcode = 7'b0111011; - FSRIW, CLZW, CTZW, PCNTW: get_opcode = 7'b0011011; - CLMULW, CLMULRW, CLMULHW, SHFLW, UNSHFLW, BDEPW, BEXTW, PACKW, PACKUW, - BFPW: get_opcode = 7'b0111011; + FSRIW: get_opcode = 7'b0011011; + SHFLW, UNSHFLW, BCOMPRESSW, BDECOMPRESSW, PACKW, PACKUW, BFPW: get_opcode = 7'b0111011; default: get_opcode = super.get_opcode(); endcase endfunction virtual function bit [2:0] get_func3(); case (instr_name) inside - ANDN: get_func3 = 3'b111; - ORN: get_func3 = 3'b110; - XNOR: get_func3 = 3'b100; GORC: get_func3 = 3'b101; + GORCI: get_func3 = 3'b101; SLO: get_func3 = 3'b001; SRO: get_func3 = 3'b101; - ROL: get_func3 = 3'b001; - ROR: get_func3 = 3'b101; - SBCLR: get_func3 = 3'b001; - SBSET: get_func3 = 3'b001; - SBINV: get_func3 = 3'b001; - SBEXT: get_func3 = 3'b101; - GREV: get_func3 = 3'b101; SLOI: get_func3 = 3'b001; SROI: get_func3 = 3'b101; - RORI: get_func3 = 3'b101; - SBCLRI: get_func3 = 3'b001; - SBSETI: get_func3 = 3'b001; - SBINVI: get_func3 = 3'b001; - SBEXTI: get_func3 = 3'b101; - GORCI: get_func3 = 3'b101; + GREV: get_func3 = 3'b101; GREVI: get_func3 = 3'b101; CMIX: get_func3 = 3'b001; CMOV: get_func3 = 3'b101; FSL: get_func3 = 3'b001; FSR: get_func3 = 3'b101; FSRI: get_func3 = 3'b101; - CLZ: get_func3 = 3'b001; - CTZ: get_func3 = 3'b001; - PCNT: get_func3 = 3'b001; BMATFLIP: get_func3 = 3'b001; - SEXT_B: get_func3 = 3'b001; - SEXT_H: get_func3 = 3'b001; CRC32_B: get_func3 = 3'b001; CRC32_H: get_func3 = 3'b001; CRC32_W: get_func3 = 3'b001; @@ -182,17 +148,10 @@ class riscv_b_instr extends riscv_instr; CRC32C_W: get_func3 = 3'b001; CRC32_D: get_func3 = 3'b001; CRC32C_D: get_func3 = 3'b001; - CLMUL: get_func3 = 3'b001; - CLMULR: get_func3 = 3'b010; - CLMULH: get_func3 = 3'b011; - MIN: get_func3 = 3'b100; - MAX: get_func3 = 3'b101; - MINU: get_func3 = 3'b110; - MAXU: get_func3 = 3'b111; SHFL: get_func3 = 3'b001; UNSHFL: get_func3 = 3'b101; - BDEP: get_func3 = 3'b110; - BEXT: get_func3 = 3'b110; + BCOMPRESS: get_func3 = 3'b110; + BDECOMPRESS: get_func3 = 3'b110; PACK: get_func3 = 3'b100; PACKU: get_func3 = 3'b100; BMATOR: get_func3 = 3'b011; @@ -201,46 +160,30 @@ class riscv_b_instr extends riscv_instr; BFP: get_func3 = 3'b111; SHFLI: get_func3 = 3'b001; UNSHFLI: get_func3 = 3'b101; - ADDIWU: get_func3 = 3'b100; - SLLIU_W: get_func3 = 3'b001; - ADDWU: get_func3 = 3'b000; - SUBWU: get_func3 = 3'b000; - ADDU_W: get_func3 = 3'b000; - SUBU_W: get_func3 = 3'b000; SLOW: get_func3 = 3'b001; SROW: get_func3 = 3'b101; ROLW: get_func3 = 3'b001; - RORW: get_func3 = 3'b101; - SBCLRW: get_func3 = 3'b001; - SBSETW: get_func3 = 3'b001; - SBINVW: get_func3 = 3'b001; - SBEXTW: get_func3 = 3'b101; GORCW: get_func3 = 3'b101; GREVW: get_func3 = 3'b101; SLOIW: get_func3 = 3'b001; SROIW: get_func3 = 3'b101; RORIW: get_func3 = 3'b101; - SBCLRIW: get_func3 = 3'b001; - SBSETIW: get_func3 = 3'b001; - SBINVIW: get_func3 = 3'b001; GORCIW: get_func3 = 3'b101; GREVIW: get_func3 = 3'b101; FSLW: get_func3 = 3'b001; FSRW: get_func3 = 3'b101; FSRIW: get_func3 = 3'b101; - CLZW: get_func3 = 3'b001; - CTZW: get_func3 = 3'b001; - PCNTW: get_func3 = 3'b001; - CLMULW: get_func3 = 3'b001; - CLMULRW: get_func3 = 3'b010; - CLMULHW: get_func3 = 3'b011; SHFLW: get_func3 = 3'b001; UNSHFLW: get_func3 = 3'b101; - BDEPW: get_func3 = 3'b110; - BEXTW: get_func3 = 3'b110; + BCOMPRESSW: get_func3 = 3'b110; + BDECOMPRESSW: get_func3 = 3'b110; PACKW: get_func3 = 3'b100; PACKUW: get_func3 = 3'b100; BFPW: get_func3 = 3'b111; + XPERM_N: get_func3 = 3'b010; + XPERM_B: get_func3 = 3'b100; + XPERM_H: get_func3 = 3'b110; + XPERM_W: get_func3 = 3'b000; default: get_func3 = super.get_func3(); endcase ; @@ -256,17 +199,8 @@ class riscv_b_instr extends riscv_instr; SRO: get_func7 = 7'b0010000; ROL: get_func7 = 7'b0110000; ROR: get_func7 = 7'b0110000; - SBCLR: get_func7 = 7'b0100100; - SBSET: get_func7 = 7'b0010100; - SBINV: get_func7 = 7'b0110100; - SBEXT: get_func7 = 7'b0100100; GREV: get_func7 = 7'b0110100; - CLZ: get_func7 = 7'b0110000; - CTZ: get_func7 = 7'b0110000; - PCNT: get_func7 = 7'b0110000; BMATFLIP: get_func7 = 7'b0110000; - SEXT_B: get_func7 = 7'b0110000; - SEXT_H: get_func7 = 7'b0110000; CRC32_B: get_func7 = 7'b0110000; CRC32_H: get_func7 = 7'b0110000; CRC32_W: get_func7 = 7'b0110000; @@ -275,58 +209,35 @@ class riscv_b_instr extends riscv_instr; CRC32C_W: get_func7 = 7'b0110000; CRC32_D: get_func7 = 7'b0110000; CRC32C_D: get_func7 = 7'b0110000; - CLMUL: get_func7 = 7'b0000101; - CLMULR: get_func7 = 7'b0000101; - CLMULH: get_func7 = 7'b0000101; - MIN: get_func7 = 7'b0000101; - MAX: get_func7 = 7'b0000101; - MINU: get_func7 = 7'b0000101; - MAXU: get_func7 = 7'b0000101; SHFL: get_func7 = 7'b0000100; UNSHFL: get_func7 = 7'b0000100; - BDEP: get_func7 = 7'b0100100; - BEXT: get_func7 = 7'b0000100; + BCOMPRESS: get_func7 = 7'b0000100; + BDECOMPRESS: get_func7 = 7'b0100100; PACK: get_func7 = 7'b0000100; PACKU: get_func7 = 7'b0100100; BMATOR: get_func7 = 7'b0000100; BMATXOR: get_func7 = 7'b0100100; PACKH: get_func7 = 7'b0000100; BFP: get_func7 = 7'b0100100; - ADDWU: get_func7 = 7'b0000101; - SUBWU: get_func7 = 7'b0100101; - ADDU_W: get_func7 = 7'b0000100; - SUBU_W: get_func7 = 7'b0100100; SLOW: get_func7 = 7'b0010000; SROW: get_func7 = 7'b0010000; - ROLW: get_func7 = 7'b0110000; - RORW: get_func7 = 7'b0110000; - SBCLRW: get_func7 = 7'b0100100; - SBSETW: get_func7 = 7'b0010100; - SBINVW: get_func7 = 7'b0110100; - SBEXTW: get_func7 = 7'b0100100; GORCW: get_func7 = 7'b0010100; + GORCIW: get_func7 = 7'b0010100; GREVW: get_func7 = 7'b0110100; + GREVIW: get_func7 = 7'b0110100; SLOIW: get_func7 = 7'b0010000; SROIW: get_func7 = 7'b0010000; - RORIW: get_func7 = 7'b0110000; - SBCLRIW: get_func7 = 7'b0100100; - SBSETIW: get_func7 = 7'b0010100; - SBINVIW: get_func7 = 7'b0110100; - GORCIW: get_func7 = 7'b0010100; - GREVIW: get_func7 = 7'b0110100; - CLZW: get_func7 = 7'b0110000; - CTZW: get_func7 = 7'b0110000; - PCNTW: get_func7 = 7'b0110000; - CLMULW: get_func7 = 7'b0000101; - CLMULRW: get_func7 = 7'b0000101; - CLMULHW: get_func7 = 7'b0000101; SHFLW: get_func7 = 7'b0000100; UNSHFLW: get_func7 = 7'b0000100; - BDEPW: get_func7 = 7'b0100100; - BEXTW: get_func7 = 7'b0000100; + BCOMPRESSW: get_func7 = 7'b0000100; + BDECOMPRESSW: get_func7 = 7'b0100100; PACKW: get_func7 = 7'b0000100; PACKUW: get_func7 = 7'b0100100; BFPW: get_func7 = 7'b0100100; + XPERM_N: get_func7 = 7'b0010100; + XPERM_B: get_func7 = 7'b0010100; + XPERM_H: get_func7 = 7'b0010100; + XPERM_W: get_func7 = 7'b0010100; default: get_func7 = super.get_func7(); endcase @@ -337,17 +248,9 @@ class riscv_b_instr extends riscv_instr; SLOI: get_func5 = 5'b00100; SROI: get_func5 = 5'b00100; RORI: get_func5 = 5'b01100; - SBCLRI: get_func5 = 5'b01001; - SBSETI: get_func5 = 5'b01001; - SBINVI: get_func5 = 5'b01101; - SBEXTI: get_func5 = 5'b01001; GORCI: get_func5 = 5'b00101; GREVI: get_func5 = 5'b01101; - CLZW: get_func5 = 5'b00000; - CTZW: get_func5 = 5'b00001; - PCNTW: get_func5 = 5'b00010; - CRC32_B: get_func5 = 5'b10000; CRC32_H: get_func5 = 5'b10001; CRC32_W: get_func5 = 5'b10010; @@ -357,12 +260,7 @@ class riscv_b_instr extends riscv_instr; CRC32_D: get_func5 = 5'b10011; CRC32C_D: get_func5 = 5'b11011; - CLZ: get_func5 = 5'b00000; - CTZ: get_func5 = 5'b00001; - PCNT: get_func5 = 5'b00010; BMATFLIP: get_func5 = 5'b00011; - SEXT_B: get_func5 = 5'b00100; - SEXT_H: get_func5 = 5'b00101; default: `uvm_fatal(`gfn, $sformatf("Unsupported instruction %0s", instr_name.name())) endcase endfunction @@ -385,23 +283,15 @@ class riscv_b_instr extends riscv_instr; string binary = ""; case (format) R_FORMAT: begin - if ((category inside {LOGICAL}) && (group == RV32B)) begin - if (instr_name inside {SEXT_B, SEXT_H}) begin - binary = - $sformatf("%8h", {get_func7(), get_func5(), rs1, get_func3(), rd, get_opcode()}); - end - end - if ((category inside {ARITHMETIC}) && (group == RV32B)) begin - if (instr_name inside {CRC32_B, CRC32_H, CRC32_W, CRC32C_B, CRC32C_H, CRC32C_W, CLZ, CTZ, - PCNT}) begin + if (instr_name inside {CRC32_B, CRC32_H, CRC32_W, CRC32C_B, CRC32C_H, CRC32C_W}) begin binary = $sformatf("%8h", {get_func7(), get_func5(), rs1, get_func3(), rd, get_opcode()}); end end if ((category inside {ARITHMETIC}) && (group == RV64B)) begin - if (instr_name inside {CLZW, CTZW, PCNTW, CRC32_D, CRC32C_D, BMATFLIP}) begin + if (instr_name inside {CRC32_D, CRC32C_D, BMATFLIP}) begin binary = $sformatf("%8h", {get_func7(), get_func5(), rs1, get_func3(), rd, get_opcode()}); end @@ -413,8 +303,6 @@ class riscv_b_instr extends riscv_instr; binary = $sformatf("%8h", {get_func5(), imm[6:0], rs1, get_func3(), rd, get_opcode()}); end else if ((category inside {SHIFT, LOGICAL}) && (group == RV64B)) begin binary = $sformatf("%8h", {get_func7(), imm[4:0], rs1, get_func3(), rd, get_opcode()}); - if (instr_name == SLLIU_W) - binary = $sformatf("%8h", {5'b0_0001, imm[6:0], rs1, get_func3(), rd, get_opcode()}); end if (instr_name inside {FSRI}) begin @@ -450,37 +338,19 @@ class riscv_b_instr extends riscv_instr; virtual function bit is_supported(riscv_instr_gen_config cfg); return cfg.enable_b_extension && ( - (ZBB inside {cfg.enable_bitmanip_groups} && instr_name inside { - CLZ, CTZ, CLZW, CTZW, PCNT, PCNTW, - SLO, SLOI, SLOW, SLOIW, - SRO, SROI, SROW, SROIW, - MIN, MINU, MAX, MAXU, - ADDWU, ADDIWU, SUBWU, - ADDU_W, SUBU_W, - SLLIU_W, - ANDN, ORN, - XNOR, PACK, PACKW, PACKU, PACKUW, PACKH, - ROL, ROLW, ROR, RORW, RORI, RORIW - }) || - (ZBS inside {cfg.enable_bitmanip_groups} && instr_name inside { - SBSET, SBSETW, SBSETI, SBSETIW, - SBCLR, SBCLRW, SBCLRI, SBCLRIW, - SBINV, SBINVW, SBINVI, SBINVIW, - SBEXT, SBEXTW, SBEXTI - }) || (ZBP inside {cfg.enable_bitmanip_groups} && instr_name inside { GREV, GREVW, GREVI, GREVIW, GORC, GORCW, GORCI, GORCIW, - SHFL, SHFLW, UNSHFL, UNSHFLW, SHFLI, UNSHFLI + SHFL, SHFLW, UNSHFL, UNSHFLW, SHFLI, UNSHFLI, + XPERM_N, XPERM_B, XPERM_H, XPERM_W, + SLO, SLOW, SLOI, SLOIW, + SRO, SROW, SROI, SROIW }) || (ZBE inside {cfg.enable_bitmanip_groups} && instr_name inside { - BEXT, BEXTW, - BDEP, BDEPW + BCOMPRESS, BCOMPRESSW, + BDECOMPRESS, BDECOMPRESSW }) || (ZBF inside {cfg.enable_bitmanip_groups} && instr_name inside {BFP, BFPW}) || - (ZBC inside {cfg.enable_bitmanip_groups} && instr_name inside { - CLMUL, CLMULW, CLMULH, CLMULHW, CLMULR, CLMULRW - }) || (ZBR inside {cfg.enable_bitmanip_groups} && instr_name inside { CRC32_B, CRC32_H, CRC32_W, CRC32_D, CRC32C_B, CRC32C_H, CRC32C_W, CRC32C_D @@ -490,10 +360,7 @@ class riscv_b_instr extends riscv_instr; }) || (ZBT inside {cfg.enable_bitmanip_groups} && instr_name inside { CMOV, CMIX, - FSL, FSLW, FSR, FSRW, FSRI, FSRIW}) || - // TODO, spec 0.92 doesn't categorize these 2 instr, put them in ZB_TMP #572 - (ZB_TMP inside {cfg.enable_bitmanip_groups} && instr_name inside { - SEXT_B, SEXT_H}) + FSL, FSLW, FSR, FSRW, FSRI, FSRIW}) ); endfunction diff --git a/src/isa/rv32b_instr.sv b/src/isa/rv32b_instr.sv index 9ea2ec13..4c568cce 100755 --- a/src/isa/rv32b_instr.sv +++ b/src/isa/rv32b_instr.sv @@ -14,64 +14,41 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -`ifdef BITMANIP_V0_9_2 + +// Remaining bitmanip instructions of draft v.0.93 not ratified in v.1.00 (Zba, Zbb, Zbc, Zbs). + // LOGICAL instructions -`DEFINE_B_INSTR(SEXT_B, R_FORMAT, LOGICAL, RV32B) -`DEFINE_B_INSTR(SEXT_H, R_FORMAT, LOGICAL, RV32B) -`DEFINE_B_INSTR(ANDN, R_FORMAT, LOGICAL, RV32B) -`DEFINE_B_INSTR(ORN , R_FORMAT, LOGICAL, RV32B) -`DEFINE_B_INSTR(XNOR, R_FORMAT, LOGICAL, RV32B) -`DEFINE_B_INSTR(GORC, R_FORMAT, LOGICAL, RV32B) -`DEFINE_B_INSTR(GORCI, I_FORMAT, LOGICAL, RV32B, UIMM) -`DEFINE_B_INSTR(CMIX, R4_FORMAT, LOGICAL, RV32B) -`DEFINE_B_INSTR(CMOV, R4_FORMAT, LOGICAL, RV32B) -`DEFINE_B_INSTR(PACK, R_FORMAT, LOGICAL, RV32B) -`DEFINE_B_INSTR(PACKU, R_FORMAT, LOGICAL, RV32B) -`DEFINE_B_INSTR(PACKH, R_FORMAT, LOGICAL, RV32B) +`DEFINE_B_INSTR(GORC, R_FORMAT, LOGICAL, RV32B) +`DEFINE_B_INSTR(GORCI, I_FORMAT, LOGICAL, RV32B, UIMM) +`DEFINE_B_INSTR(CMIX, R4_FORMAT, LOGICAL, RV32B) +`DEFINE_B_INSTR(CMOV, R4_FORMAT, LOGICAL, RV32B) +`DEFINE_B_INSTR(PACK, R_FORMAT, LOGICAL, RV32B) +`DEFINE_B_INSTR(PACKU, R_FORMAT, LOGICAL, RV32B) +`DEFINE_B_INSTR(PACKH, R_FORMAT, LOGICAL, RV32B) +`DEFINE_B_INSTR(XPERM_N, R_FORMAT, LOGICAL, RV32B) +`DEFINE_B_INSTR(XPERM_B, R_FORMAT, LOGICAL, RV32B) +`DEFINE_B_INSTR(XPERM_H, R_FORMAT, LOGICAL, RV32B) // SHIFT intructions -`DEFINE_B_INSTR(SLO, R_FORMAT, SHIFT, RV32B) -`DEFINE_B_INSTR(SRO, R_FORMAT, SHIFT, RV32B) -`DEFINE_B_INSTR(ROL, R_FORMAT, SHIFT, RV32B) -`DEFINE_B_INSTR(ROR, R_FORMAT, SHIFT, RV32B) -`DEFINE_B_INSTR(SBCLR, R_FORMAT, SHIFT, RV32B) -`DEFINE_B_INSTR(SBSET, R_FORMAT, SHIFT, RV32B) -`DEFINE_B_INSTR(SBINV, R_FORMAT, SHIFT, RV32B) -`DEFINE_B_INSTR(SBEXT, R_FORMAT, SHIFT, RV32B) -`DEFINE_B_INSTR(GREV, R_FORMAT, SHIFT, RV32B) -`DEFINE_B_INSTR(GREVI, I_FORMAT, SHIFT, RV32B , UIMM) -`DEFINE_B_INSTR(SLOI , I_FORMAT, SHIFT, RV32B ,UIMM) -`DEFINE_B_INSTR(SROI , I_FORMAT, SHIFT, RV32B ,UIMM) -`DEFINE_B_INSTR(RORI , I_FORMAT, SHIFT, RV32B ,UIMM) -`DEFINE_B_INSTR(SBCLRI , I_FORMAT, SHIFT, RV32B ,UIMM) -`DEFINE_B_INSTR(SBSETI , I_FORMAT, SHIFT, RV32B ,UIMM) -`DEFINE_B_INSTR(SBINVI , I_FORMAT, SHIFT, RV32B ,UIMM) -`DEFINE_B_INSTR(SBEXTI , I_FORMAT, SHIFT, RV32B ,UIMM) +`DEFINE_B_INSTR(SLO, R_FORMAT, SHIFT, RV32B) +`DEFINE_B_INSTR(SRO, R_FORMAT, SHIFT, RV32B) +`DEFINE_B_INSTR(SLOI, I_FORMAT, SHIFT, RV32B, UIMM) +`DEFINE_B_INSTR(SROI, I_FORMAT, SHIFT, RV32B, UIMM) +`DEFINE_B_INSTR(GREV, R_FORMAT, SHIFT, RV32B) +`DEFINE_B_INSTR(GREVI, I_FORMAT, SHIFT, RV32B, UIMM) `DEFINE_B_INSTR(FSL, R4_FORMAT, SHIFT, RV32B) `DEFINE_B_INSTR(FSR, R4_FORMAT, SHIFT, RV32B) -`DEFINE_B_INSTR(FSRI, I_FORMAT, SHIFT, RV32B ,UIMM) +`DEFINE_B_INSTR(FSRI, I_FORMAT, SHIFT, RV32B, UIMM) // ARITHMETIC intructions -`DEFINE_B_INSTR(CLZ, R_FORMAT, ARITHMETIC, RV32B) -`DEFINE_B_INSTR(CTZ, R_FORMAT, ARITHMETIC, RV32B) -`DEFINE_B_INSTR(PCNT, R_FORMAT, ARITHMETIC, RV32B) -`DEFINE_B_INSTR(CRC32_B, R_FORMAT, ARITHMETIC, RV32B) -`DEFINE_B_INSTR(CRC32_H, R_FORMAT, ARITHMETIC, RV32B) -`DEFINE_B_INSTR(CRC32_W, R_FORMAT, ARITHMETIC, RV32B) -`DEFINE_B_INSTR(CRC32C_B, R_FORMAT, ARITHMETIC, RV32B) -`DEFINE_B_INSTR(CRC32C_H, R_FORMAT, ARITHMETIC, RV32B) -`DEFINE_B_INSTR(CRC32C_W, R_FORMAT, ARITHMETIC, RV32B) -`DEFINE_B_INSTR(CLMUL, R_FORMAT, ARITHMETIC, RV32B) -`DEFINE_B_INSTR(CLMULR, R_FORMAT, ARITHMETIC, RV32B) -`DEFINE_B_INSTR(CLMULH, R_FORMAT, ARITHMETIC, RV32B) -`DEFINE_B_INSTR(MIN, R_FORMAT, ARITHMETIC, RV32B) -`DEFINE_B_INSTR(MAX, R_FORMAT, ARITHMETIC, RV32B) -`DEFINE_B_INSTR(MINU, R_FORMAT, ARITHMETIC, RV32B) -`DEFINE_B_INSTR(MAXU, R_FORMAT, ARITHMETIC, RV32B) -`DEFINE_B_INSTR(SHFL, R_FORMAT, ARITHMETIC, RV32B) -`DEFINE_B_INSTR(UNSHFL, R_FORMAT, ARITHMETIC, RV32B) -`DEFINE_B_INSTR(BDEP, R_FORMAT, ARITHMETIC, RV32B) -`DEFINE_B_INSTR(BEXT, R_FORMAT, ARITHMETIC, RV32B) -`DEFINE_B_INSTR(BFP, R_FORMAT, ARITHMETIC, RV32B) -`DEFINE_B_INSTR(SHFLI, I_FORMAT, ARITHMETIC, RV32B, UIMM) -`DEFINE_B_INSTR(UNSHFLI, I_FORMAT, ARITHMETIC, RV32B, UIMM) - - `endif +`DEFINE_B_INSTR(CRC32_B, R_FORMAT, ARITHMETIC, RV32B) +`DEFINE_B_INSTR(CRC32_H, R_FORMAT, ARITHMETIC, RV32B) +`DEFINE_B_INSTR(CRC32_W, R_FORMAT, ARITHMETIC, RV32B) +`DEFINE_B_INSTR(CRC32C_B, R_FORMAT, ARITHMETIC, RV32B) +`DEFINE_B_INSTR(CRC32C_H, R_FORMAT, ARITHMETIC, RV32B) +`DEFINE_B_INSTR(CRC32C_W, R_FORMAT, ARITHMETIC, RV32B) +`DEFINE_B_INSTR(SHFL, R_FORMAT, ARITHMETIC, RV32B) +`DEFINE_B_INSTR(UNSHFL, R_FORMAT, ARITHMETIC, RV32B) +`DEFINE_B_INSTR(SHFLI, I_FORMAT, ARITHMETIC, RV32B, UIMM) +`DEFINE_B_INSTR(UNSHFLI, I_FORMAT, ARITHMETIC, RV32B, UIMM) +`DEFINE_B_INSTR(BCOMPRESS, R_FORMAT, ARITHMETIC, RV32B) +`DEFINE_B_INSTR(BDECOMPRESS, R_FORMAT, ARITHMETIC, RV32B) +`DEFINE_B_INSTR(BFP, R_FORMAT, ARITHMETIC, RV32B) diff --git a/src/isa/rv32zba_instr.sv b/src/isa/rv32zba_instr.sv index e4712df3..91edfd1d 100644 --- a/src/isa/rv32zba_instr.sv +++ b/src/isa/rv32zba_instr.sv @@ -14,8 +14,7 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -`ifdef BITMANIP_V1_0_0 + `DEFINE_ZBA_INSTR(SH1ADD, R_FORMAT, ARITHMETIC, RV32ZBA); `DEFINE_ZBA_INSTR(SH2ADD, R_FORMAT, ARITHMETIC, RV32ZBA); `DEFINE_ZBA_INSTR(SH3ADD, R_FORMAT, ARITHMETIC, RV32ZBA); -`endif diff --git a/src/isa/rv32zbb_instr.sv b/src/isa/rv32zbb_instr.sv index f2cb4914..afa88d8b 100644 --- a/src/isa/rv32zbb_instr.sv +++ b/src/isa/rv32zbb_instr.sv @@ -14,7 +14,7 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -`ifdef BITMANIP_V1_0_0 + `DEFINE_ZBB_INSTR(ANDN, R_FORMAT, LOGICAL, RV32ZBB); `DEFINE_ZBB_INSTR(CLZ, I_FORMAT, ARITHMETIC, RV32ZBB); `DEFINE_ZBB_INSTR(CPOP, I_FORMAT, ARITHMETIC, RV32ZBB); @@ -33,4 +33,3 @@ `DEFINE_ZBB_INSTR(SEXT_H, I_FORMAT, ARITHMETIC, RV32ZBB); `DEFINE_ZBB_INSTR(XNOR, R_FORMAT, LOGICAL, RV32ZBB); `DEFINE_ZBB_INSTR(ZEXT_H, R_FORMAT, ARITHMETIC, RV32ZBB); -`endif diff --git a/src/isa/rv32zbc_instr.sv b/src/isa/rv32zbc_instr.sv index 3e810788..032e18ae 100644 --- a/src/isa/rv32zbc_instr.sv +++ b/src/isa/rv32zbc_instr.sv @@ -14,8 +14,7 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -`ifdef BITMANIP_V1_0_0 + `DEFINE_ZBC_INSTR(CLMUL, R_FORMAT, ARITHMETIC, RV32ZBC) `DEFINE_ZBC_INSTR(CLMULH, R_FORMAT, ARITHMETIC, RV32ZBC) `DEFINE_ZBC_INSTR(CLMULR, R_FORMAT, ARITHMETIC, RV32ZBC) -`endif diff --git a/src/isa/rv32zbs_instr.sv b/src/isa/rv32zbs_instr.sv index da5546a2..9cbc0b22 100644 --- a/src/isa/rv32zbs_instr.sv +++ b/src/isa/rv32zbs_instr.sv @@ -14,7 +14,7 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -`ifdef BITMANIP_V1_0_0 + `DEFINE_ZBS_INSTR(BCLR, R_FORMAT, SHIFT, RV32ZBS) `DEFINE_ZBS_INSTR(BCLRI, I_FORMAT, SHIFT, RV32ZBS, UIMM) `DEFINE_ZBS_INSTR(BEXT, R_FORMAT, SHIFT, RV32ZBS) @@ -23,4 +23,3 @@ `DEFINE_ZBS_INSTR(BINVI, I_FORMAT, SHIFT, RV32ZBS, UIMM) `DEFINE_ZBS_INSTR(BSET, R_FORMAT, SHIFT, RV32ZBS) `DEFINE_ZBS_INSTR(BSETI, I_FORMAT, SHIFT, RV32ZBS, UIMM) -`endif diff --git a/src/isa/rv64b_instr.sv b/src/isa/rv64b_instr.sv index 2db900ef..7cafd68f 100755 --- a/src/isa/rv64b_instr.sv +++ b/src/isa/rv64b_instr.sv @@ -15,57 +15,32 @@ * limitations under the License. */ -`ifdef BITMANIP_V0_9_2 +// Remaining bitmanip instructions of draft v.0.93 not ratified in v.1.00 (Zba, Zbb, Zbc, Zbs). // ARITHMETIC intructions -`DEFINE_B_INSTR(BMATOR, R_FORMAT, ARITHMETIC, RV64B) -`DEFINE_B_INSTR(BMATXOR, R_FORMAT, ARITHMETIC, RV64B) -`DEFINE_B_INSTR(BMATFLIP, R_FORMAT, ARITHMETIC, RV64B) -`DEFINE_B_INSTR(CRC32_D, R_FORMAT, ARITHMETIC, RV64B) -`DEFINE_B_INSTR(CRC32C_D, R_FORMAT, ARITHMETIC, RV64B) -`DEFINE_B_INSTR(ADDIWU, I_FORMAT, ARITHMETIC, RV64B) -`DEFINE_B_INSTR(ADDWU, R_FORMAT, ARITHMETIC, RV64B) -`DEFINE_B_INSTR(SUBWU, R_FORMAT, ARITHMETIC, RV64B) -`DEFINE_B_INSTR(ADDU_W, R_FORMAT, ARITHMETIC, RV64B) -`DEFINE_B_INSTR(SUBU_W, R_FORMAT, ARITHMETIC, RV64B) -`DEFINE_B_INSTR(CLZW, R_FORMAT, ARITHMETIC, RV64B) -`DEFINE_B_INSTR(CTZW, R_FORMAT, ARITHMETIC, RV64B) -`DEFINE_B_INSTR(PCNTW, R_FORMAT, ARITHMETIC, RV64B) -`DEFINE_B_INSTR(CLMULW, R_FORMAT, ARITHMETIC, RV64B) -`DEFINE_B_INSTR(CLMULRW, R_FORMAT, ARITHMETIC, RV64B) -`DEFINE_B_INSTR(CLMULHW, R_FORMAT, ARITHMETIC, RV64B) -`DEFINE_B_INSTR(SHFLW, R_FORMAT, ARITHMETIC, RV64B) -`DEFINE_B_INSTR(UNSHFLW, R_FORMAT, ARITHMETIC, RV64B) -`DEFINE_B_INSTR(BDEPW, R_FORMAT, ARITHMETIC, RV64B) -`DEFINE_B_INSTR(BEXTW, R_FORMAT, ARITHMETIC, RV64B) -`DEFINE_B_INSTR(BFPW, R_FORMAT, ARITHMETIC, RV64B) - +`DEFINE_B_INSTR(BMATOR, R_FORMAT, ARITHMETIC, RV64B) +`DEFINE_B_INSTR(BMATXOR, R_FORMAT, ARITHMETIC, RV64B) +`DEFINE_B_INSTR(BMATFLIP, R_FORMAT, ARITHMETIC, RV64B) +`DEFINE_B_INSTR(CRC32_D, R_FORMAT, ARITHMETIC, RV64B) +`DEFINE_B_INSTR(CRC32C_D, R_FORMAT, ARITHMETIC, RV64B) +`DEFINE_B_INSTR(SHFLW, R_FORMAT, ARITHMETIC, RV64B) +`DEFINE_B_INSTR(UNSHFLW, R_FORMAT, ARITHMETIC, RV64B) +`DEFINE_B_INSTR(BCOMPRESSW, R_FORMAT, ARITHMETIC, RV64B) +`DEFINE_B_INSTR(BDECOMPRESSW, R_FORMAT, ARITHMETIC, RV64B) +`DEFINE_B_INSTR(BFPW, R_FORMAT, ARITHMETIC, RV64B) // SHIFT intructions -`DEFINE_B_INSTR(SLLIU_W, I_FORMAT, SHIFT, RV64B, UIMM) `DEFINE_B_INSTR(SLOW, R_FORMAT, SHIFT, RV64B) `DEFINE_B_INSTR(SROW, R_FORMAT, SHIFT, RV64B) -`DEFINE_B_INSTR(ROLW, R_FORMAT, SHIFT, RV64B) -`DEFINE_B_INSTR(RORW, R_FORMAT, SHIFT, RV64B) -`DEFINE_B_INSTR(SBCLRW, R_FORMAT, SHIFT, RV64B) -`DEFINE_B_INSTR(SBSETW, R_FORMAT, SHIFT, RV64B) -`DEFINE_B_INSTR(SBINVW, R_FORMAT, SHIFT, RV64B) -`DEFINE_B_INSTR(SBEXTW, R_FORMAT, SHIFT, RV64B) -`DEFINE_B_INSTR(GREVW, R_FORMAT, SHIFT, RV64B) -`DEFINE_B_INSTR(SLOIW , I_FORMAT, SHIFT, RV64B, UIMM) -`DEFINE_B_INSTR(SROIW , I_FORMAT, SHIFT, RV64B, UIMM) -`DEFINE_B_INSTR(RORIW , I_FORMAT, SHIFT, RV64B, UIMM) -`DEFINE_B_INSTR(SBCLRIW , I_FORMAT, SHIFT, RV64B, UIMM) -`DEFINE_B_INSTR(SBSETIW , I_FORMAT, SHIFT, RV64B, UIMM) -`DEFINE_B_INSTR(SBINVIW , I_FORMAT, SHIFT, RV64B, UIMM) -`DEFINE_B_INSTR(GREVIW, I_FORMAT, SHIFT, RV64B, UIMM) +`DEFINE_B_INSTR(SLOIW, I_FORMAT, SHIFT, RV64B, UIMM) +`DEFINE_B_INSTR(SROIW, I_FORMAT, SHIFT, RV64B, UIMM) +`DEFINE_B_INSTR(GREVW, R_FORMAT, SHIFT, RV64B) +`DEFINE_B_INSTR(GREVIW, I_FORMAT, SHIFT, RV64B, UIMM) `DEFINE_B_INSTR(FSLW, R4_FORMAT, SHIFT, RV64B) `DEFINE_B_INSTR(FSRW, R4_FORMAT, SHIFT, RV64B) `DEFINE_B_INSTR(FSRIW, I_FORMAT, SHIFT, RV64B, UIMM) - // LOGICAL instructions -`DEFINE_B_INSTR(GORCW, R_FORMAT, LOGICAL, RV64B) -`DEFINE_B_INSTR(GORCIW, I_FORMAT, LOGICAL, RV64B, UIMM) -`DEFINE_B_INSTR(PACKW, R_FORMAT, LOGICAL, RV64B) -`DEFINE_B_INSTR(PACKUW, R_FORMAT, LOGICAL, RV64B) - -`endif +`DEFINE_B_INSTR(GORCW, R_FORMAT, LOGICAL, RV64B) +`DEFINE_B_INSTR(GORCIW, I_FORMAT, LOGICAL, RV64B, UIMM) +`DEFINE_B_INSTR(PACKW, R_FORMAT, LOGICAL, RV64B) +`DEFINE_B_INSTR(PACKUW, R_FORMAT, LOGICAL, RV64B) +`DEFINE_B_INSTR(XPERM_W, R_FORMAT, LOGICAL, RV64B) diff --git a/src/isa/rv64zba_instr.sv b/src/isa/rv64zba_instr.sv index 1da06123..e3544304 100644 --- a/src/isa/rv64zba_instr.sv +++ b/src/isa/rv64zba_instr.sv @@ -14,10 +14,9 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -`ifdef BITMANIP_V1_0_0 + `DEFINE_ZBA_INSTR(ADD_UW, R_FORMAT, ARITHMETIC, RV64ZBA); `DEFINE_ZBA_INSTR(SH1ADD_UW, R_FORMAT, ARITHMETIC, RV64ZBA); `DEFINE_ZBA_INSTR(SH2ADD_UW, R_FORMAT, ARITHMETIC, RV64ZBA); `DEFINE_ZBA_INSTR(SH3ADD_UW, R_FORMAT, ARITHMETIC, RV64ZBA); `DEFINE_ZBA_INSTR(SLLI_UW, I_FORMAT, SHIFT, RV64ZBA, UIMM); -`endif diff --git a/src/isa/rv64zbb_instr.sv b/src/isa/rv64zbb_instr.sv index ee3bb798..e1c278c2 100644 --- a/src/isa/rv64zbb_instr.sv +++ b/src/isa/rv64zbb_instr.sv @@ -14,11 +14,10 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -`ifdef BITMANIP_V1_0_0 + `DEFINE_ZBB_INSTR(CLZW, I_FORMAT, ARITHMETIC, RV64ZBB); `DEFINE_ZBB_INSTR(CPOPW, I_FORMAT, ARITHMETIC, RV64ZBB); `DEFINE_ZBB_INSTR(CTZW, I_FORMAT, ARITHMETIC, RV64ZBB); `DEFINE_ZBB_INSTR(ROLW, R_FORMAT, SHIFT, RV64ZBB); `DEFINE_ZBB_INSTR(RORW, R_FORMAT, SHIFT, RV64ZBB); `DEFINE_ZBB_INSTR(RORIW, I_FORMAT, SHIFT, RV64ZBB, UIMM); -`endif diff --git a/src/riscv_instr_cover_group.sv b/src/riscv_instr_cover_group.sv index c73709f4..badc423d 100644 --- a/src/riscv_instr_cover_group.sv +++ b/src/riscv_instr_cover_group.sv @@ -913,8 +913,7 @@ class riscv_instr_cover_group; `FCLASS_INSTR_CG_BEGIN(fclass_d, D) `CG_END - // B extension -`ifdef BITMANIP_V1_0_0 + // B extension instructions ratified in v.1.00 (Zba, Zbb, Zbc, Zbs). `ZBA_R_INSTR_CG_BEGIN(sh1add) `CG_END `ZBA_R_INSTR_CG_BEGIN(sh2add) @@ -1083,44 +1082,8 @@ class riscv_instr_cover_group; `ZBS_I_INSTR_CG_BEGIN(bseti) `CP_VALUE_RANGE(bit_location, instr.imm, 0, XLEN-1) `CG_END -`endif // BITMANIP_V1_0_0 - -`ifdef BITMANIP_V0_9_2 - `B_R_INSTR_NO_RS2_CG_BEGIN(clz) - `CP_VALUE_RANGE(num_leading_zeros, instr.rd_value, 0, XLEN-1) - `CG_END - - `B_R_INSTR_NO_RS2_CG_BEGIN(ctz) - `CP_VALUE_RANGE(num_trailing_zeros, instr.rd_value, 0, XLEN-1) - `CG_END - - `B_R_INSTR_NO_RS2_CG_BEGIN(clzw) - `CP_VALUE_RANGE(num_leading_zeros, instr.rd_value, 0, XLEN/2-1) - `CG_END - - `B_R_INSTR_NO_RS2_CG_BEGIN(ctzw) - `CP_VALUE_RANGE(num_trailing_zeros, instr.rd_value, 0, XLEN/2-1) - `CG_END - - // Count Bits Set (pcnt) - `B_R_INSTR_NO_RS2_CG_BEGIN(pcnt) - `CP_VALUE_RANGE(num_set_bits, instr.rd_value, 0, XLEN-1) - `CG_END - - `B_R_INSTR_NO_RS2_CG_BEGIN(pcntw) - `CP_VALUE_RANGE(num_set_bits, instr.rd_value, 0, XLEN/2-1) - `CG_END - - // Logic-with-negate (andn, orn, xnor) - `B_R_INSTR_CG_BEGIN(andn) - `CG_END - - `B_R_INSTR_CG_BEGIN(orn) - `CG_END - - `B_R_INSTR_CG_BEGIN(xnor) - `CG_END + // Remaining bitmanip instructions of draft v.0.93 not ratified in v.1.00 (Zba, Zbb, Zbc, Zbs). // Pack two words in one register (pack, packu, packh) `B_R_INSTR_CG_BEGIN(pack) `CG_END @@ -1137,75 +1100,6 @@ class riscv_instr_cover_group; `B_R_INSTR_CG_BEGIN(packuw) `CG_END - // Min/max instructions (min, max, minu, maxu) - `B_R_INSTR_CG_BEGIN(min) - cp_rs1_gt_rs2 : coverpoint (longint'(instr.rs1_value) > longint'(instr.rs2_value)); - cp_rs1_eq_rs2 : coverpoint (instr.rs1_value == instr.rs2_value) { - bins equal = {1}; - } - `CG_END - - `B_R_INSTR_CG_BEGIN(max) - cp_rs1_gt_rs2 : coverpoint (longint'(instr.rs1_value) > longint'(instr.rs2_value)); - cp_rs1_eq_rs2 : coverpoint (instr.rs1_value == instr.rs2_value) { - bins equal = {1}; - } - `CG_END - - `B_R_INSTR_CG_BEGIN(minu) - cp_rs1_gt_rs2 : coverpoint (instr.rs1_value > instr.rs2_value); - cp_rs1_eq_rs2 : coverpoint (instr.rs1_value == instr.rs2_value) { - bins equal = {1}; - } - `CG_END - - `B_R_INSTR_CG_BEGIN(maxu) - cp_rs1_gt_rs2 : coverpoint (instr.rs1_value > instr.rs2_value); - cp_rs1_eq_rs2 : coverpoint (instr.rs1_value == instr.rs2_value) { - bins equal = {1}; - } - `CG_END - - // Sign-extend instructions (sext.b, sext.h) - `B_R_INSTR_NO_RS2_CG_BEGIN(sext_b) - `CG_END - - `B_R_INSTR_NO_RS2_CG_BEGIN(sext_h) - `CG_END - - // Single-bit instructions (sbset, sbclr, sbinv, sbext) - `B_R_INSTR_CG_BEGIN(sbset) - `CP_VALUE_RANGE(bit_location, instr.rs2_value, 0, XLEN-1) - `CG_END - - `B_R_INSTR_CG_BEGIN(sbclr) - `CP_VALUE_RANGE(bit_location, instr.rs2_value, 0, XLEN-1) - `CG_END - - `B_R_INSTR_CG_BEGIN(sbinv) - `CP_VALUE_RANGE(bit_location, instr.rs2_value, 0, XLEN-1) - `CG_END - - `B_R_INSTR_CG_BEGIN(sbext) - `CP_VALUE_RANGE(bit_location, instr.rs2_value, 0, XLEN-1) - `CG_END - - `B_I_INSTR_CG_BEGIN(sbseti) - `CP_VALUE_RANGE(bit_location, instr.imm, 0, XLEN-1) - `CG_END - - `B_I_INSTR_CG_BEGIN(sbclri) - `CP_VALUE_RANGE(bit_location, instr.imm, 0, XLEN-1) - `CG_END - - `B_I_INSTR_CG_BEGIN(sbinvi) - `CP_VALUE_RANGE(bit_location, instr.imm, 0, XLEN-1) - `CG_END - - `B_I_INSTR_CG_BEGIN(sbexti) - `CP_VALUE_RANGE(bit_location, instr.imm, 0, XLEN-1) - `CG_END - // Shift Ones (Left/Right) (slo, sloi, sro, sroi) `B_R_INSTR_CG_BEGIN(slo) `CP_VALUE_RANGE(num_ones_shift, instr.rs2_value, 0, XLEN-1) @@ -1239,31 +1133,6 @@ class riscv_instr_cover_group; `CP_VALUE_RANGE(num_ones_shift, instr.imm, 0, XLEN/2-1) `CG_END - // Rotate (Left/Right) (rol, ror, rori) - `B_R_INSTR_CG_BEGIN(ror) - `CP_VALUE_RANGE(num_bit_rotate, instr.rs2_value, 0, XLEN-1) - `CG_END - - `B_R_INSTR_CG_BEGIN(rol) - `CP_VALUE_RANGE(num_bit_rotate, instr.rs2_value, 0, XLEN-1) - `CG_END - - `B_I_INSTR_CG_BEGIN(rori) - `CP_VALUE_RANGE(num_bit_rotate, instr.imm, 0, XLEN-1) - `CG_END - - `B_R_INSTR_CG_BEGIN(rorw) - `CP_VALUE_RANGE(num_bit_rotate, instr.rs2_value, 0, XLEN/2-1) - `CG_END - - `B_R_INSTR_CG_BEGIN(rolw) - `CP_VALUE_RANGE(num_bit_rotate, instr.rs2_value, 0, XLEN/2-1) - `CG_END - - `B_I_INSTR_CG_BEGIN(roriw) - `CP_VALUE_RANGE(num_bit_rotate, instr.imm, 0, XLEN/2-1) - `CG_END - // Generalized Reverse (grev, grevi, rev) `B_R_INSTR_CG_BEGIN(grev) `CP_VALUE_RANGE(reverse_mode, instr.rs2_value, 0, XLEN-1) @@ -1362,35 +1231,16 @@ class riscv_instr_cover_group; `CP_VALUE_RANGE(offset, instr.rs2_value[20:16], 0, XLEN/2-1) `CG_END - `B_R_INSTR_CG_BEGIN(bext) - `CG_END - - `B_R_INSTR_CG_BEGIN(bextw) - `CG_END - - `B_R_INSTR_CG_BEGIN(bdep) - `CG_END - - `B_R_INSTR_CG_BEGIN(bdepw) - `CG_END - - // Multiplication - `B_R_INSTR_CG_BEGIN(clmul) - `CG_END - - `B_R_INSTR_CG_BEGIN(clmulh) + `B_R_INSTR_CG_BEGIN(bcompress) `CG_END - `B_R_INSTR_CG_BEGIN(clmulr) + `B_R_INSTR_CG_BEGIN(bcompressw) `CG_END - `B_R_INSTR_CG_BEGIN(clmulw) + `B_R_INSTR_CG_BEGIN(bdecompress) `CG_END - `B_R_INSTR_CG_BEGIN(clmulhw) - `CG_END - - `B_R_INSTR_CG_BEGIN(clmulrw) + `B_R_INSTR_CG_BEGIN(bdecompressw) `CG_END `B_R_INSTR_NO_RS2_CG_BEGIN(crc32_b) @@ -1458,26 +1308,6 @@ class riscv_instr_cover_group; `CP_VALUE_RANGE(num_shift, instr.imm, 0, XLEN/2-1) `CG_END - `B_R_INSTR_CG_BEGIN(addwu) - `CG_END - - `B_R_INSTR_CG_BEGIN(subwu) - `CG_END - - `B_I_INSTR_CG_BEGIN(addiwu) - `CG_END - - `B_R_INSTR_CG_BEGIN(addu_w) - `CG_END - - `B_R_INSTR_CG_BEGIN(subu_w) - `CG_END - - `B_I_INSTR_CG_BEGIN(slliu_w) - `CP_VALUE_RANGE(num_shift, instr.imm, 0, XLEN-1) - `CG_END -`endif // BITMANIP_V0_9_2 - // CSR instructions `CSR_INSTR_CG_BEGIN(csrrw) cp_rs1 : coverpoint instr.rs1; @@ -2200,7 +2030,6 @@ class riscv_instr_cover_group; fcvt_d_lu_cg = new(); `CG_SELECTOR_END -`ifdef BITMANIP_V1_0_0 `CG_SELECTOR_BEGIN(RV32ZBA) sh1add_cg = new(); sh2add_cg = new(); @@ -2241,68 +2070,38 @@ class riscv_instr_cover_group; bset_cg = new(); bseti_cg = new(); `CG_SELECTOR_END -`endif // BITMANIP_V1_0_0 -`ifdef BITMANIP_V0_9_2 `CG_SELECTOR_BEGIN(RV32B) - clz_cg = new(); - ctz_cg = new(); - pcnt_cg = new(); - andn_cg = new(); - orn_cg = new(); - xnor_cg = new(); - pack_cg = new(); - packh_cg = new(); - min_cg = new(); - max_cg = new(); - minu_cg = new(); - maxu_cg = new(); - sext_b_cg = new(); - sext_h_cg = new(); - sbset_cg = new(); - sbclr_cg = new(); - sbinv_cg = new(); - sbext_cg = new(); - sbseti_cg = new(); - sbclri_cg = new(); - sbinvi_cg = new(); - sbexti_cg = new(); - slo_cg = new(); - sro_cg = new(); - sloi_cg = new(); - sroi_cg = new(); - ror_cg = new(); - rol_cg = new(); - rori_cg = new(); - grev_cg = new(); - grevi_cg = new(); - shfli_cg = new(); - unshfli_cg = new(); - shfl_cg = new(); - unshfl_cg = new(); - gorc_cg = new(); - gorci_cg = new(); - bfp_cg = new(); - bext_cg = new(); - bdep_cg = new(); - clmul_cg = new(); - clmulh_cg = new(); - clmulr_cg = new(); - crc32_b_cg = new(); - crc32_h_cg = new(); - crc32_w_cg = new(); - crc32c_b_cg = new(); - crc32c_h_cg = new(); - crc32c_w_cg = new(); - cmix_cg = new(); - cmov_cg = new(); - fsl_cg = new(); - fsr_cg = new(); - fsri_cg = new(); + pack_cg = new(); + packh_cg = new(); + slo_cg = new(); + sro_cg = new(); + sloi_cg = new(); + sroi_cg = new(); + grev_cg = new(); + grevi_cg = new(); + shfli_cg = new(); + unshfli_cg = new(); + shfl_cg = new(); + unshfl_cg = new(); + gorc_cg = new(); + gorci_cg = new(); + bfp_cg = new(); + bcompress_cg = new(); + bdecompress_cg = new(); + crc32_b_cg = new(); + crc32_h_cg = new(); + crc32_w_cg = new(); + crc32c_b_cg = new(); + crc32c_h_cg = new(); + crc32c_w_cg = new(); + cmix_cg = new(); + cmov_cg = new(); + fsl_cg = new(); + fsr_cg = new(); + fsri_cg = new(); `CG_SELECTOR_END -`endif -`ifdef BITMANIP_V1_0_0 `CG_SELECTOR_BEGIN(RV64ZBA) add_uw_cg = new(); sh1add_uw_cg = new(); @@ -2318,50 +2117,32 @@ class riscv_instr_cover_group; rorw_cg = new(); roriw_cg = new(); `CG_SELECTOR_END -`endif -`ifdef BITMANIP_V0_9_2 `CG_SELECTOR_BEGIN(RV64B) - clzw_cg = new(); - ctzw_cg = new(); - pcntw_cg = new(); - packw_cg = new(); - packuw_cg = new(); - slow_cg = new(); - srow_cg = new(); - sloiw_cg = new(); - sroiw_cg = new(); - rorw_cg = new(); - rolw_cg = new(); - roriw_cg = new(); - grevw_cg = new(); - greviw_cg = new(); - shflw_cg = new(); - unshflw_cg = new(); - gorcw_cg = new(); - gorciw_cg = new(); - bfpw_cg = new(); - bextw_cg = new(); - bdepw_cg = new(); - clmulw_cg = new(); - clmulhw_cg = new(); - clmulrw_cg = new(); - crc32_d_cg = new(); - crc32c_d_cg = new(); - bmator_cg = new(); - bmatxor_cg = new(); - bmatflip_cg = new(); - fslw_cg = new(); - fsrw_cg = new(); - fsriw_cg = new(); - addwu_cg = new(); - subwu_cg = new(); - addiwu_cg = new(); - addu_w_cg = new(); - subu_w_cg = new(); - slliu_w_cg = new(); + packw_cg = new(); + packuw_cg = new(); + slow_cg = new(); + srow_cg = new(); + sloiw_cg = new(); + sroiw_cg = new(); + grevw_cg = new(); + greviw_cg = new(); + shflw_cg = new(); + unshflw_cg = new(); + gorcw_cg = new(); + gorciw_cg = new(); + bfpw_cg = new(); + bcompressw_cg = new(); + bdecompressw_cg = new(); + crc32_d_cg = new(); + crc32c_d_cg = new(); + bmator_cg = new(); + bmatxor_cg = new(); + bmatflip_cg = new(); + fslw_cg = new(); + fsrw_cg = new(); + fsriw_cg = new(); `CG_SELECTOR_END -`endif // Ignore the exception which cannot be covered when running with ISS if (iss_mode) begin @@ -2579,7 +2360,6 @@ class riscv_instr_cover_group; FLE_D : `SAMPLE_F(fle_d_cg, instr) FCLASS_S : `SAMPLE_F(fclass_s_cg, instr) FCLASS_D : `SAMPLE_F(fclass_d_cg, instr) -`ifdef BITMANIP_V1_0_0 // RV32ZBA SH1ADD : `SAMPLE_ZBA(sh1add_cg, instr) SH2ADD : `SAMPLE_ZBA(sh2add_cg, instr) @@ -2616,38 +2396,13 @@ class riscv_instr_cover_group; BINVI : `SAMPLE_ZBS(binvi_cg, instr) BSET : `SAMPLE_ZBS(bset_cg, instr) BSETI : `SAMPLE_ZBS(bseti_cg, instr) -`endif -`ifdef BITMANIP_V0_9_2 // RV32B - CLZ : `SAMPLE_B(clz_cg, instr) - CTZ : `SAMPLE_B(ctz_cg, instr) - PCNT : `SAMPLE_B(pcnt_cg, instr) - ANDN : `SAMPLE_B(andn_cg, instr) - ORN : `SAMPLE_B(orn_cg, instr) - XNOR : `SAMPLE_B(xnor_cg, instr) PACK : `SAMPLE_B(pack_cg, instr) PACKH : `SAMPLE_B(packh_cg, instr) - MIN : `SAMPLE_B(min_cg, instr) - MAX : `SAMPLE_B(max_cg, instr) - MINU : `SAMPLE_B(minu_cg, instr) - MAXU : `SAMPLE_B(maxu_cg, instr) - SEXT_B : `SAMPLE_B(sext_b_cg, instr) - SEXT_H : `SAMPLE_B(sext_h_cg, instr) - SBSET : `SAMPLE_B(sbset_cg, instr) - SBCLR : `SAMPLE_B(sbclr_cg, instr) - SBINV : `SAMPLE_B(sbinv_cg, instr) - SBEXT : `SAMPLE_B(sbext_cg, instr) - SBSETI : `SAMPLE_B(sbseti_cg, instr) - SBCLRI : `SAMPLE_B(sbclri_cg, instr) - SBINVI : `SAMPLE_B(sbinvi_cg, instr) - SBEXTI : `SAMPLE_B(sbexti_cg, instr) SLO : `SAMPLE_B(slo_cg, instr) SRO : `SAMPLE_B(sro_cg, instr) SLOI : `SAMPLE_B(sloi_cg, instr) SROI : `SAMPLE_B(sroi_cg, instr) - ROR : `SAMPLE_B(ror_cg, instr) - ROL : `SAMPLE_B(rol_cg, instr) - RORI : `SAMPLE_B(rori_cg, instr) GREV : `SAMPLE_B(grev_cg, instr) GREVI : `SAMPLE_B(grevi_cg, instr) SHFLI : `SAMPLE_B(shfli_cg, instr) @@ -2657,11 +2412,8 @@ class riscv_instr_cover_group; GORC : `SAMPLE_B(gorc_cg, instr) GORCI : `SAMPLE_B(gorci_cg, instr) BFP : `SAMPLE_B(bfp_cg, instr) - BEXT : `SAMPLE_B(bext_cg, instr) - BDEP : `SAMPLE_B(bdep_cg, instr) - CLMUL : `SAMPLE_B(clmul_cg, instr) - CLMULH : `SAMPLE_B(clmulh_cg, instr) - CLMULR : `SAMPLE_B(clmulr_cg, instr) + BCOMPRESS : `SAMPLE_B(bcompress_cg, instr) + BDECOMPRESS: `SAMPLE_B(bdecompress_cg, instr) CRC32_B : `SAMPLE_B(crc32_b_cg, instr) CRC32_H : `SAMPLE_B(crc32_h_cg, instr) CRC32_W : `SAMPLE_B(crc32_w_cg, instr) @@ -2673,8 +2425,6 @@ class riscv_instr_cover_group; FSL : `SAMPLE_B(fsl_cg, instr) FSR : `SAMPLE_B(fsr_cg, instr) FSRI : `SAMPLE_B(fsri_cg, instr) -`endif // BITMANIP_V0_9_2 -`ifdef BITMANIP_V1_0_0 // RV64ZBA ADD_UW : `SAMPLE_ZBA(add_uw_cg, instr) SH1ADD_UW : `SAMPLE_ZBA(sh1add_uw_cg, instr) @@ -2688,48 +2438,30 @@ class riscv_instr_cover_group; ROLW : `SAMPLE_ZBB(rolw_cg, instr) RORW : `SAMPLE_ZBB(rorw_cg, instr) RORIW : `SAMPLE_ZBB(roriw_cg, instr) -`endif // BITMANIP_V1_0_0 -`ifdef BITMANIP_V0_9_2 // RV64B - CLZW : `SAMPLE_B(clzw_cg, instr) - CTZW : `SAMPLE_B(ctzw_cg, instr) - PCNTW : `SAMPLE_B(pcntw_cg, instr) - PACKW : `SAMPLE_B(packw_cg, instr) - PACKUW : `SAMPLE_B(packuw_cg, instr) - SLOW : `SAMPLE_B(slow_cg, instr) - SROW : `SAMPLE_B(srow_cg, instr) - SLOIW : `SAMPLE_B(sloiw_cg, instr) - SROIW : `SAMPLE_B(sroiw_cg, instr) - RORW : `SAMPLE_B(rorw_cg, instr) - ROLW : `SAMPLE_B(rolw_cg, instr) - RORIW : `SAMPLE_B(roriw_cg, instr) - GREVW : `SAMPLE_B(grevw_cg, instr) - GREVIW : `SAMPLE_B(greviw_cg, instr) - SHFLW : `SAMPLE_B(shflw_cg, instr) - UNSHFLW : `SAMPLE_B(unshflw_cg, instr) - GORCW : `SAMPLE_B(gorcw_cg, instr) - GORCIW : `SAMPLE_B(gorciw_cg, instr) - BFPW : `SAMPLE_B(bfpw_cg, instr) - BEXTW : `SAMPLE_B(bextw_cg, instr) - BDEPW : `SAMPLE_B(bdepw_cg, instr) - CLMULW : `SAMPLE_B(clmulw_cg, instr) - CLMULHW : `SAMPLE_B(clmulhw_cg, instr) - CLMULRW : `SAMPLE_B(clmulrw_cg, instr) - CRC32_D : `SAMPLE_B(crc32_d_cg, instr) - CRC32C_D : `SAMPLE_B(crc32c_d_cg, instr) - BMATOR : `SAMPLE_B(bmator_cg, instr) - BMATXOR : `SAMPLE_B(bmatxor_cg, instr) - BMATFLIP : `SAMPLE_B(bmatflip_cg, instr) - FSLW : `SAMPLE_B(fslw_cg, instr) - FSRW : `SAMPLE_B(fsrw_cg, instr) - FSRIW : `SAMPLE_B(fsriw_cg, instr) - ADDWU : `SAMPLE_B(addwu_cg, instr) - SUBWU : `SAMPLE_B(subwu_cg, instr) - ADDIWU : `SAMPLE_B(addiwu_cg, instr) - ADDU_W : `SAMPLE_B(addu_w_cg, instr) - SUBU_W : `SAMPLE_B(subu_w_cg, instr) - SLLIU_W : `SAMPLE_B(slliu_w_cg, instr) -`endif // BITMANIP_V0_9_2 + PACKW : `SAMPLE_B(packw_cg, instr) + PACKUW : `SAMPLE_B(packuw_cg, instr) + SLOW : `SAMPLE_B(slow_cg, instr) + SROW : `SAMPLE_B(srow_cg, instr) + SLOIW : `SAMPLE_B(sloiw_cg, instr) + SROIW : `SAMPLE_B(sroiw_cg, instr) + GREVW : `SAMPLE_B(grevw_cg, instr) + GREVIW : `SAMPLE_B(greviw_cg, instr) + SHFLW : `SAMPLE_B(shflw_cg, instr) + UNSHFLW : `SAMPLE_B(unshflw_cg, instr) + GORCW : `SAMPLE_B(gorcw_cg, instr) + GORCIW : `SAMPLE_B(gorciw_cg, instr) + BFPW : `SAMPLE_B(bfpw_cg, instr) + BCOMPRESSW : `SAMPLE_B(bcompressw_cg, instr) + BDECOMPRESSW : `SAMPLE_B(bdecompressw_cg, instr) + CRC32_D : `SAMPLE_B(crc32_d_cg, instr) + CRC32C_D : `SAMPLE_B(crc32c_d_cg, instr) + BMATOR : `SAMPLE_B(bmator_cg, instr) + BMATXOR : `SAMPLE_B(bmatxor_cg, instr) + BMATFLIP : `SAMPLE_B(bmatflip_cg, instr) + FSLW : `SAMPLE_B(fslw_cg, instr) + FSRW : `SAMPLE_B(fsrw_cg, instr) + FSRIW : `SAMPLE_B(fsriw_cg, instr) `VECTOR_INCLUDE("riscv_instr_cover_group_inc_cg_sample.sv") default: begin if (instr.group == RV32I) begin diff --git a/src/riscv_instr_gen_config.sv b/src/riscv_instr_gen_config.sv index e4329d5b..9a2fdd18 100644 --- a/src/riscv_instr_gen_config.sv +++ b/src/riscv_instr_gen_config.sv @@ -635,12 +635,6 @@ class riscv_instr_gen_config extends uvm_object; enable_zbs_extension = 0; end - // Disable old b-extension if any of the Zb* extensions are enabled - if (enable_zba_extension || enable_zbb_extension || enable_zbc_extension || enable_zbs_extension) begin - enable_b_extension = 0; - enable_bitmanip_groups = {}; - end - vector_cfg = riscv_vector_cfg::type_id::create("vector_cfg"); pmp_cfg = riscv_pmp_cfg::type_id::create("pmp_cfg"); pmp_cfg.rand_mode(pmp_cfg.pmp_randomize); diff --git a/src/riscv_instr_pkg.sv b/src/riscv_instr_pkg.sv index 68d47de5..0524f66d 100644 --- a/src/riscv_instr_pkg.sv +++ b/src/riscv_instr_pkg.sv @@ -18,8 +18,6 @@ package riscv_instr_pkg; - `define BITMANIP_V1_0_0 - `include "dv_defines.svh" `include "riscv_defines.svh" `include "uvm_macros.svh" @@ -164,11 +162,11 @@ package riscv_instr_pkg; CSRRWI, CSRRSI, CSRRCI, - // RV32B instructions -`ifdef BITMANIP_V1_0_0 + // RV32ZBA instructions SH1ADD, SH2ADD, SH3ADD, + // RV32ZBB instructions ANDN, CLZ, CPOP, @@ -187,9 +185,11 @@ package riscv_instr_pkg; SEXT_H, XNOR, ZEXT_H, + // RV32ZBC instructions CLMUL, CLMULH, CLMULR, + // RV32ZBS instructions BCLR, BCLRI, BEXT, @@ -198,68 +198,40 @@ package riscv_instr_pkg; BINVI, BSET, BSETI, -`endif // BITMANIP_V1_0_0 -`ifdef BITMANIP_V0_9_2 - ANDN, - ORN, - XNOR, + // RV32B instructions + // Remaining bitmanip instructions of draft v.0.93 not ratified in v.1.00 (Zba, Zbb, Zbc, Zbs). GORC, + GORCI, + CMIX, + CMOV, + PACK, + PACKU, + PACKH, + XPERM_N, + XPERM_B, + XPERM_H, SLO, SRO, - ROL, - ROR, - SBCLR, - SBSET, - SBINV, - SBEXT, - GREV, SLOI, SROI, - RORI, - SBCLRI, - SBSETI, - SBINVI, - SBEXTI, - GORCI, + GREV, GREVI, - CMIX, - CMOV, FSL, FSR, FSRI, - CLZ, - CTZ, - PCNT, - SEXT_B, - SEXT_H, CRC32_B, CRC32_H, CRC32_W, CRC32C_B, CRC32C_H, CRC32C_W, - CLMUL, - CLMULR, - CLMULH, - MIN, - MAX, - MINU, - MAXU, SHFL, UNSHFL, - BDEP, - BEXT, - PACK, - PACKU, - BMATOR, - BMATXOR, - PACKH, - BFP, SHFLI, UNSHFLI, -`endif // BITMANIP_V0_9_2 - -`ifdef BITMANIP_V1_0_0 + BCOMPRESS, + BDECOMPRESS, + BFP, // RV64ZBA instructions ADD_UW, SH1ADD_UW, @@ -273,54 +245,32 @@ package riscv_instr_pkg; ROLW, RORW, RORIW, -`endif // BITMANIP_V1_0_0 - -`ifdef BITMANIP_V0_9_2 //RV64B instructions - ADDIWU, - SLLIU_W, - ADDWU, - SUBWU, + // Remaining bitmanip instructions of draft v.0.93 not ratified in v.1.00 (Zba, Zbb, Zbc, Zbs). + BMATOR, + BMATXOR, BMATFLIP, CRC32_D, CRC32C_D, - ADDU_W, - SUBU_W, + SHFLW, + UNSHFLW, + BCOMPRESSW, + BDECOMPRESSW, + BFPW, SLOW, SROW, - ROLW, - RORW, - SBCLRW, - SBSETW, - SBINVW, - SBEXTW, - GORCW, - GREVW, SLOIW, SROIW, - RORIW, - SBCLRIW, - SBSETIW, - SBINVIW, - GORCIW, + GREVW, GREVIW, FSLW, FSRW, FSRIW, - CLZW, - CTZW, - PCNTW, - CLMULW, - CLMULRW, - CLMULHW, - SHFLW, - UNSHFLW, - BDEPW, - BEXTW, + GORCW, + GORCIW, PACKW, PACKUW, - BFPW, -`endif // BITMANIP_V0_9_2 + XPERM_W, // RV32M instructions MUL, MULH, @@ -1244,7 +1194,7 @@ package riscv_instr_pkg; parameter int DATA_WIDTH = 32; // Parameters for output assembly program formatting - parameter int MAX_INSTR_STR_LEN = 11; + parameter int MAX_INSTR_STR_LEN = 13; parameter int LABEL_STR_LEN = 18; // Parameter for program generation @@ -1438,28 +1388,19 @@ package riscv_instr_pkg; `include "riscv_vector_cfg.sv" `include "riscv_pmp_cfg.sv" typedef class riscv_instr; - `ifdef BITMANIP_V0_9_2 - typedef class riscv_b_instr; - `endif - - `ifdef BITMANIP_V1_0_0 typedef class riscv_zba_instr; typedef class riscv_zbb_instr; typedef class riscv_zbc_instr; typedef class riscv_zbs_instr; - `endif + typedef class riscv_b_instr; `include "riscv_instr_gen_config.sv" `include "isa/riscv_instr.sv" `include "isa/riscv_amo_instr.sv" - `ifdef BITMANIP_V0_9_2 - `include "isa/riscv_b_instr.sv" - `endif - `ifdef BITMANIP_V1_0_0 `include "isa/riscv_zba_instr.sv" `include "isa/riscv_zbb_instr.sv" `include "isa/riscv_zbc_instr.sv" `include "isa/riscv_zbs_instr.sv" - `endif + `include "isa/riscv_b_instr.sv" `include "isa/riscv_floating_point_instr.sv" `include "isa/riscv_vector_instr.sv" `include "isa/riscv_compressed_instr.sv"