1,008 legit_start/verilog/Example_4_Video_In.map.rpt
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8 legit_start/verilog/Example_4_Video_In.map.smsg
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@@ -27,3 +27,11 @@ Warning (10037): Verilog HDL or VHDL warning at video_system_clock_2.v(254): con
Warning (10037): Verilog HDL or VHDL warning at video_system_clock_2.v(263): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at video_system_clock_2.v(272): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at video_system_clock_2.v(281): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at video_system_clock_3.v(98): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at video_system_clock_3.v(107): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at video_system_clock_3.v(116): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at video_system_clock_3.v(245): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at video_system_clock_3.v(254): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at video_system_clock_3.v(263): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at video_system_clock_3.v(272): conditional expression evaluates to a constant
Warning (10037): Verilog HDL or VHDL warning at video_system_clock_3.v(281): conditional expression evaluates to a constant
10 legit_start/verilog/Example_4_Video_In.map.summary
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@@ -1,12 +1,12 @@
Analysis & Synthesis Status : Successful - Wed Feb 25 12:04:05 2015
Analysis & Synthesis Status : Successful - Thu Feb 26 18:58:47 2015
Quartus II 64-Bit Version : 11.0 Build 157 04/27/2011 SJ Full Version
Revision Name : Example_4_Video_In
Top-level Entity Name : Example_4_Video_In
Family : Cyclone IV E
Total logic elements : 2,989
Total combinational functions : 2,620
Dedicated logic registers : 1,592
Total registers : 1592
Total logic elements : 3,074
Total combinational functions : 2,663
Dedicated logic registers : 1,662
Total registers : 1662
Total pins : 85
Total virtual pins : 0
Total memory bits : 3,220,736
BIN +0 Bytes (100%) legit_start/verilog/Example_4_Video_In.pof
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BIN +0 Bytes (100%) legit_start/verilog/Example_4_Video_In.sof
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2,954 legit_start/verilog/Example_4_Video_In.sta.rpt
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26 legit_start/verilog/Example_4_Video_In.sta.summary
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@@ -3,63 +3,63 @@ TimeQuest Timing Analyzer Summary
------------------------------------------------------------

Type : Slow 1200mV 85C Model Setup 'altera_reserved_tck'
Slack : 46.334
Slack : 44.976
TNS : 0.000

Type : Slow 1200mV 85C Model Hold 'altera_reserved_tck'
Slack : 0.444
Slack : 0.445
TNS : 0.000

Type : Slow 1200mV 85C Model Recovery 'altera_reserved_tck'
Slack : 47.035
Slack : 47.873
TNS : 0.000

Type : Slow 1200mV 85C Model Removal 'altera_reserved_tck'
Slack : 1.120
Slack : 1.124
TNS : 0.000

Type : Slow 1200mV 85C Model Minimum Pulse Width 'altera_reserved_tck'
Slack : 49.506
Slack : 49.507
TNS : 0.000

Type : Slow 1200mV 0C Model Setup 'altera_reserved_tck'
Slack : 46.808
Slack : 45.522
TNS : 0.000

Type : Slow 1200mV 0C Model Hold 'altera_reserved_tck'
Slack : 0.393
TNS : 0.000

Type : Slow 1200mV 0C Model Recovery 'altera_reserved_tck'
Slack : 47.366
Slack : 48.164
TNS : 0.000

Type : Slow 1200mV 0C Model Removal 'altera_reserved_tck'
Slack : 1.022
Slack : 1.027
TNS : 0.000

Type : Slow 1200mV 0C Model Minimum Pulse Width 'altera_reserved_tck'
Slack : 49.380
TNS : 0.000

Type : Fast 1200mV 0C Model Setup 'altera_reserved_tck'
Slack : 48.813
Slack : 48.246
TNS : 0.000

Type : Fast 1200mV 0C Model Hold 'altera_reserved_tck'
Slack : 0.180
Slack : 0.181
TNS : 0.000

Type : Fast 1200mV 0C Model Recovery 'altera_reserved_tck'
Slack : 48.967
Slack : 49.395
TNS : 0.000

Type : Fast 1200mV 0C Model Removal 'altera_reserved_tck'
Slack : 0.491
Slack : 0.490
TNS : 0.000

Type : Fast 1200mV 0C Model Minimum Pulse Width 'altera_reserved_tck'
Slack : 49.302
Slack : 49.301
TNS : 0.000

------------------------------------------------------------
14 legit_start/verilog/Example_4_Video_In.v
View file
@@ -43,6 +43,8 @@ module Example_4_Video_In (

);

wire [7:0] sound_out;

/*****************************************************************************
* Internal Modules *
*****************************************************************************/
@@ -67,10 +69,13 @@ Video_System Video_System_inst
.VGA_VS_from_the_VGA_Controller (VGA_VS),
.clk (CLOCK_50),
.in_port_to_the_pio_0 (KEY),
.out_port_from_the_sound (sound_out),
.reset_n (1'b1),
.sys_clk (),
.vga_clk ()
);

/* Audio hardware setup */

wire AUD_CTRL_CLK;
wire DLY_RST;
@@ -116,17 +121,20 @@ wire signed [15:0] sine_out;
assign audio_outR = (lfsr_out<<1) + sine_out;
assign audio_outL = (lfsr_out<<1) + sine_out;


/* Crashing sound generator. Hooked up to pin 0 of sound parallel IO port*/
LFSR_attack_decay crash(.clock(AUD_DACLRCK),
.reset(KEY[2]),
.reset(~sound_out[0]),
.cutoff(3'd7), // cutoff from full freq to clock/(2^7)
.gain(3'd7), // gain = 3 bit shift factor = 1 to 2^7
.attack(4'd0), // fast rise
.decay(4'd6), // fairly slow fall
.amp(16'h7FFF), // nearly full amp
.noise_out(lfsr_out));


/* Success sound generator (440hz). Hooked up to pin 0 of sound parallel IO port*/
DDS sine (.clock(AUD_DACLRCK),
.reset(KEY[3]),
.reset(~sound_out[1]),
.increment({18'd2507, 14'b0}),
.phase(8'd0),
.sine_out(sine_out));
14 legit_start/verilog/Video_System.bsf
View file
@@ -1,8 +1,8 @@
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 432 384)
(rect 0 0 432 416)
(text "Video_System" (rect 4 0 101 16)(font "Arial" (font_size 10)))
(text "inst" (rect 4 368 28 384)(font "Arial"))
(text "inst" (rect 4 400 28 416)(font "Arial"))
(port
(pt 0 32)
(input)
@@ -143,9 +143,17 @@
(text "VGA_VS_from_the_VGA_Controller " (rect 229 313 405 329)(font "Arial" (font_size 8)))
(line (pt 416 320)(pt 432 320)(line_width 1))
)
(port
(pt 432 384)
(output)
(text "out_port_from_the_sound[7..0] " (rect 0 0 146 16)(font "Arial" (font_size 8)))
(text "out_port_from_the_sound[7..0] " (rect 258 377 405 393)(font "Arial" (font_size 8)))
(line (pt 416 384)(pt 432 384)(line_width 3))
)
(drawing
(line (pt 16 64)(pt 415 64)(color 0 0 0)(dotted)(line_width 1))
(line (pt 16 192)(pt 415 192)(color 0 0 0)(dotted)(line_width 1))
(line (pt 16 336)(pt 415 336)(color 0 0 0)(dotted)(line_width 1))
(rectangle (rect 16 16 416 368)(line_width 1)))
(line (pt 16 368)(pt 415 368)(color 0 0 0)(dotted)(line_width 1))
(rectangle (rect 16 16 416 400)(line_width 1)))
)
210 legit_start/verilog/Video_System.html
View file
@@ -67,7 +67,7 @@
</table>
<table class="blueBar">
<tr>
<td class="l">2015.02.19.18:00:19</td>
<td class="l">2015.02.26.18:26:27</td>
<td class="r">Datasheet</td>
</tr>
</table>
@@ -78,7 +78,7 @@
<table class="connectionboxes">
<tr>
<td class="lefthandwire">&#160;&#160;clk&#160;</td>
<td class="main" rowspan="5">Video_System</td>
<td class="main" rowspan="6">Video_System</td>
</tr>
<tr style="height:6px">
<td></td>
@@ -94,6 +94,10 @@
<td></td>
<td class="righthandwire">&#160;in_port&#160;&#160;</td>
</tr>
<tr>
<td></td>
<td class="righthandwire">&#160;out_port&#160;&#160;</td>
</tr>
<tr style="height:6px">
<td></td>
</tr>
@@ -124,6 +128,9 @@
</a> altera_avalon_jtag_uart 11.0
<br/>&#160;&#160;
<a href="#module_pio_0"><b>pio_0</b>
</a> altera_avalon_pio 11.0
<br/>&#160;&#160;
<a href="#module_sound"><b>sound</b>
</a> altera_avalon_pio 11.0</span>
</div>
</div>
@@ -251,6 +258,21 @@
<td class="addr"><span style="color:#989898">0x</span>00301010</td>
<td class="empty"></td>
</tr>
<tr>
<td class="slavemodule">&#160;
<a href="#module_sound"><b>sound</b>
</a>
</td>
<td class="empty"></td>
<td class="empty"></td>
<td class="empty"></td>
</tr>
<tr>
<td class="slaveb">s1&#160;</td>
<td class="empty"></td>
<td class="addr"><span style="color:#989898">0x</span>00200000</td>
<td class="empty"></td>
</tr>
</table>
<a name="module_clk"> </a>
<div>
@@ -311,7 +333,7 @@ <h2>CPU</h2>altera_nios2 v11.0
<a href="#module_Clock_Signals">Clock_Signals</a>
</td>
<td class="from">sys_clk&#160;&#160;</td>
<td class="main" rowspan="25">CPU</td>
<td class="main" rowspan="28">CPU</td>
</tr>
<tr>
<td class="to">&#160;&#160;clk</td>
@@ -439,6 +461,22 @@ <h2>CPU</h2>altera_nios2 v11.0
<td></td>
<td class="to">&#160;&#160;irq</td>
</tr>
<tr style="height:6px">
<td></td>
</tr>
<tr>
<td></td>
<td></td>
<td class="from">data_master&#160;&#160;</td>
<td class="neighbor" rowspan="2">
<a href="#module_sound">sound</a>
</td>
</tr>
<tr>
<td></td>
<td></td>
<td class="to">&#160;&#160;s1</td>
</tr>
</table>
</div>
<br/>
@@ -818,7 +856,7 @@ <h2>Parameters</h2>
</tr>
<tr>
<td class="parametername">dataSlaveMapParam</td>
<td class="parametervalue">&lt;address-map&gt;&lt;slave name='Pixel_Buffer.avalon_sram_slave' start='0x0' end='0x200000' /&gt;&lt;slave name='Onchip_Memory.s1' start='0x280000' end='0x2E1A80' /&gt;&lt;slave name='CPU.jtag_debug_module' start='0x300800' end='0x301000' /&gt;&lt;slave name='Pixel_Buffer_DMA.avalon_control_slave' start='0x301000' end='0x301010' /&gt;&lt;slave name='pio_0.s1' start='0x301010' end='0x301020' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x301020' end='0x301028' /&gt;&lt;slave name='Clock_Signals.avalon_clocks_slave' start='0x301028' end='0x30102A' /&gt;&lt;/address-map&gt;</td>
<td class="parametervalue">&lt;address-map&gt;&lt;slave name='Pixel_Buffer.avalon_sram_slave' start='0x0' end='0x200000' /&gt;&lt;slave name='sound.s1' start='0x200000' end='0x200020' /&gt;&lt;slave name='Onchip_Memory.s1' start='0x280000' end='0x2E1A80' /&gt;&lt;slave name='CPU.jtag_debug_module' start='0x300800' end='0x301000' /&gt;&lt;slave name='Pixel_Buffer_DMA.avalon_control_slave' start='0x301000' end='0x301010' /&gt;&lt;slave name='pio_0.s1' start='0x301010' end='0x301020' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x301020' end='0x301028' /&gt;&lt;slave name='Clock_Signals.avalon_clocks_slave' start='0x301028' end='0x30102A' /&gt;&lt;/address-map&gt;</td>
</tr>
<tr>
<td class="parametername">dataAddrWidth</td>
@@ -2142,10 +2180,170 @@ <h2>Software Assignments</h2>
</tr>
</table>
</div>
<a name="module_sound"> </a>
<div>
<hr/>
<h2>sound</h2>altera_avalon_pio v11.0
<br/>
<div class="greydiv">
<table class="connectionboxes">
<tr>
<td class="neighbor" rowspan="2">
<a href="#module_clk">clk</a>
</td>
<td class="from">clk&#160;&#160;</td>
<td class="main" rowspan="5">sound</td>
</tr>
<tr>
<td class="to">&#160;&#160;clk</td>
</tr>
<tr style="height:6px">
<td></td>
</tr>
<tr>
<td class="neighbor" rowspan="2">
<a href="#module_CPU">CPU</a>
</td>
<td class="from">data_master&#160;&#160;</td>
</tr>
<tr>
<td class="to">&#160;&#160;s1</td>
</tr>
</table>
</div>
<br/>
<br/>
<table class="flowbox">
<tr>
<td class="parametersbox">
<h2>Parameters</h2>
<table>
<tr>
<td class="parametername">bitClearingEdgeCapReg</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">bitModifyingOutReg</td>
<td class="parametervalue">true</td>
</tr>
<tr>
<td class="parametername">captureEdge</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">clockRate</td>
<td class="parametervalue">50000000</td>
</tr>
<tr>
<td class="parametername">direction</td>
<td class="parametervalue">Output</td>
</tr>
<tr>
<td class="parametername">edgeType</td>
<td class="parametervalue">RISING</td>
</tr>
<tr>
<td class="parametername">generateIRQ</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">irqType</td>
<td class="parametervalue">LEVEL</td>
</tr>
<tr>
<td class="parametername">resetValue</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">simDoTestBenchWiring</td>
<td class="parametervalue">false</td>
</tr>
<tr>
<td class="parametername">simDrivenValue</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">width</td>
<td class="parametervalue">8</td>
</tr>
<tr>
<td class="parametername">deviceFamily</td>
<td class="parametervalue">UNKNOWN</td>
</tr>
<tr>
<td class="parametername">generateLegacySim</td>
<td class="parametervalue">false</td>
</tr>
</table>
</td>
</tr>
</table>&#160;&#160;
<table class="flowbox">
<tr>
<td class="parametersbox">
<h2>Software Assignments</h2>
<table>
<tr>
<td class="parametername">DO_TEST_BENCH_WIRING</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">DRIVEN_SIM_VALUE</td>
<td class="parametervalue">0x0</td>
</tr>
<tr>
<td class="parametername">HAS_TRI</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">HAS_OUT</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">HAS_IN</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">CAPTURE</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">BIT_CLEARING_EDGE_REGISTER</td>
<td class="parametervalue">0</td>
</tr>
<tr>
<td class="parametername">BIT_MODIFYING_OUTPUT_REGISTER</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">DATA_WIDTH</td>
<td class="parametervalue">8</td>
</tr>
<tr>
<td class="parametername">RESET_VALUE</td>
<td class="parametervalue">0x0</td>
</tr>
<tr>
<td class="parametername">EDGE_TYPE</td>
<td class="parametervalue">"NONE"</td>
</tr>
<tr>
<td class="parametername">IRQ_TYPE</td>
<td class="parametervalue">"NONE"</td>
</tr>
<tr>
<td class="parametername">FREQ</td>
<td class="parametervalue">50000000u</td>
</tr>
</table>
</td>
</tr>
</table>
</div>
<table class="blueBar">
<tr>
<td class="l">generation took 0.00 seconds</td>
<td class="r">rendering took 0.09 seconds</td>
<td class="l">generation took 0.01 seconds</td>
<td class="r">rendering took 0.15 seconds</td>
</tr>
</table>
</body>
174 legit_start/verilog/Video_System.ptf
View file
@@ -562,6 +562,12 @@ SYSTEM Video_System
span = "0x00000010";
is_bridge = "0";
}
Entry sound/s1
{
address = "0x00200000";
span = "0x00000020";
is_bridge = "0";
}
}
}
WIZARD_SCRIPT_ARGUMENTS
@@ -2965,4 +2971,172 @@ SYSTEM Video_System
Synthesis_Only_Files = "";
}
}
MODULE sound
{
SLAVE s1
{
PORT_WIRING
{
PORT clk
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT reset_n
{
type = "reset_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT address
{
type = "address";
width = "3";
direction = "input";
Is_Enabled = "1";
}
PORT write_n
{
type = "write_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT writedata
{
type = "writedata";
width = "32";
direction = "input";
Is_Enabled = "1";
}
PORT chipselect
{
type = "chipselect";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT readdata
{
type = "readdata";
width = "32";
direction = "output";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Write_Wait_States = "0cycles";
Read_Wait_States = "1cycles";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "0";
Address_Alignment = "native";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Read_Latency = "0";
Is_Memory_Device = "0";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Write_Latency = "0";
Is_Flash = "0";
Data_Width = "32";
Address_Width = "3";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
MASTERED_BY CPU/data_master
{
priority = "1";
Offset_Address = "0x00200000";
}
Base_Address = "0x00200000";
Has_IRQ = "0";
Address_Group = "0";
IRQ_MASTER CPU/data_master
{
IRQ_Number = "NC";
}
Is_Readable = "0";
Is_Writable = "1";
}
}
PORT_WIRING
{
PORT out_port
{
type = "export";
width = "8";
direction = "output";
Is_Enabled = "1";
}
PORT in_port
{
direction = "input";
Is_Enabled = "0";
width = "32";
}
PORT bidir_port
{
direction = "inout";
Is_Enabled = "0";
width = "32";
}
}
class = "altera_avalon_pio";
class_version = "7.08110";
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Wire_Test_Bench_Values = "1";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
Has_Clock = "1";
Date_Modified = "";
View
{
MESSAGES
{
}
Settings_Summary = " 32-bit PIO using <br>


output pins";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
Do_Test_Bench_Wiring = "0";
Driven_Sim_Value = "0";
has_tri = "0";
has_out = "1";
has_in = "0";
capture = "0";
Data_Width = "8";
reset_value = "0";
edge_type = "NONE";
irq_type = "NONE";
bit_clearing_edge_register = "0";
bit_modifying_output_register = "1";
}
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sound.v";
Synthesis_Only_Files = "";
}
}
}
153 legit_start/verilog/Video_System.ptf.8.0
View file
@@ -2,7 +2,7 @@ SYSTEM Video_System
{
#
# Generated by: com.altera.sopcmodel.ensemble.EnsembleGeneratePTF
# Date: 2015.02.19.18:00:24
# Date: 2015.02.26.18:26:53
#
# clock_source "clk"
# altera_nios2 "CPU"
@@ -15,8 +15,9 @@ SYSTEM Video_System
# altera_up_avalon_video_vga_controller "VGA_Controller"
# altera_avalon_jtag_uart "jtag_uart_0"
# altera_avalon_pio "pio_0"
# altera_avalon_pio "sound"
#
# Contains 26 connections.
# Contains 28 connections.
#
System_Wizard_Version = "8.0";
Builder_Application = "sopc_builder_ca";
@@ -526,6 +527,12 @@ SYSTEM Video_System
span = "0x00000010";
is_bridge = "0";
}
Entry sound/s1
{
address = "0x00200000";
span = "0x00000020";
is_bridge = "0";
}
}
}
WIZARD_SCRIPT_ARGUMENTS
@@ -958,7 +965,7 @@ SYSTEM Video_System
}
HDL_INFO
{
Simulation_HDL_Files = "C:/sean_fei/legit_start/verilog/Dual_Clock_FIFO.v";
Simulation_HDL_Files = "C:/our_shit/ECE5760Projects/legit_start/verilog/Dual_Clock_FIFO.v";
}
WIZARD_SCRIPT_ARGUMENTS
{
@@ -1062,7 +1069,7 @@ SYSTEM Video_System
}
HDL_INFO
{
Simulation_HDL_Files = "C:/sean_fei/legit_start/verilog/Clock_Signals.v";
Simulation_HDL_Files = "C:/our_shit/ECE5760Projects/legit_start/verilog/Clock_Signals.v";
}
WIZARD_SCRIPT_ARGUMENTS
{
@@ -1248,7 +1255,7 @@ SYSTEM Video_System
}
HDL_INFO
{
Simulation_HDL_Files = "C:/sean_fei/legit_start/verilog/Pixel_Buffer.v";
Simulation_HDL_Files = "C:/our_shit/ECE5760Projects/legit_start/verilog/Pixel_Buffer.v";
}
WIZARD_SCRIPT_ARGUMENTS
{
@@ -1493,7 +1500,7 @@ SYSTEM Video_System
}
HDL_INFO
{
Simulation_HDL_Files = "C:/sean_fei/legit_start/verilog/Pixel_Buffer_DMA.v";
Simulation_HDL_Files = "C:/our_shit/ECE5760Projects/legit_start/verilog/Pixel_Buffer_DMA.v";
}
WIZARD_SCRIPT_ARGUMENTS
{
@@ -1625,7 +1632,7 @@ SYSTEM Video_System
}
HDL_INFO
{
Simulation_HDL_Files = "C:/sean_fei/legit_start/verilog/Pixel_RGB_Resampler.v";
Simulation_HDL_Files = "C:/our_shit/ECE5760Projects/legit_start/verilog/Pixel_RGB_Resampler.v";
}
WIZARD_SCRIPT_ARGUMENTS
{
@@ -1771,7 +1778,7 @@ SYSTEM Video_System
}
HDL_INFO
{
Simulation_HDL_Files = "C:/sean_fei/legit_start/verilog/VGA_Controller.v";
Simulation_HDL_Files = "C:/our_shit/ECE5760Projects/legit_start/verilog/VGA_Controller.v";
}
WIZARD_SCRIPT_ARGUMENTS
{
@@ -2140,4 +2147,134 @@ SYSTEM Video_System
bit_modifying_output_register = "0";
}
}
MODULE sound
{
SLAVE s1
{
PORT_WIRING
{
PORT clk
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT reset_n
{
type = "reset_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT address
{
type = "address";
width = "3";
direction = "input";
Is_Enabled = "1";
}
PORT write_n
{
type = "write_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT writedata
{
type = "writedata";
width = "32";
direction = "input";
Is_Enabled = "1";
}
PORT chipselect
{
type = "chipselect";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT readdata
{
type = "readdata";
width = "32";
direction = "output";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Write_Wait_States = "0cycles";
Read_Wait_States = "1cycles";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "0";
Address_Alignment = "native";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Read_Latency = "0";
Is_Memory_Device = "0";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Write_Latency = "0";
Is_Flash = "0";
Data_Width = "32";
Address_Width = "3";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
MASTERED_BY CPU/data_master
{
priority = "1";
Offset_Address = "0x00200000";
}
Base_Address = "0x00200000";
}
}
PORT_WIRING
{
PORT out_port
{
type = "export";
width = "8";
direction = "output";
Is_Enabled = "1";
}
}
class = "altera_avalon_pio";
class_version = "11.0";
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Wire_Test_Bench_Values = "1";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
Has_Clock = "1";
}
WIZARD_SCRIPT_ARGUMENTS
{
Do_Test_Bench_Wiring = "0";
Driven_Sim_Value = "0";
has_tri = "0";
has_out = "1";
has_in = "0";
capture = "0";
Data_Width = "8";
reset_value = "0";
edge_type = "NONE";
irq_type = "NONE";
bit_clearing_edge_register = "0";
bit_modifying_output_register = "1";
}
}
}
194 legit_start/verilog/Video_System.ptf.bak
View file
@@ -4,7 +4,7 @@ SYSTEM Video_System
System_Wizard_Build = "157";
#
# Generated by: com.altera.sopcmodel.ensemble.EnsembleGeneratePTF
# Date: 2015.02.19.18:00:24
# Date: 2015.02.26.18:26:53
#
# clock_source "clk"
# altera_nios2 "CPU"
@@ -17,8 +17,9 @@ SYSTEM Video_System
# altera_up_avalon_video_vga_controller "VGA_Controller"
# altera_avalon_jtag_uart "jtag_uart_0"
# altera_avalon_pio "pio_0"
# altera_avalon_pio "sound"
#
# Contains 26 connections.
# Contains 28 connections.
#
Builder_Application = "sopc_builder_ca";
#. values for Builder_Application are:
@@ -86,6 +87,8 @@ SYSTEM Video_System
clock_freq = "50000000";
clock_freq = "50000000";
clock_freq = "50000000";
clock_freq = "50000000";
clock_freq = "50000000";
board_class = "";
view_master_columns = "1";
view_master_priorities = "0";
@@ -569,6 +572,12 @@ SYSTEM Video_System
span = "0x00000010";
is_bridge = "0";
}
Entry sound/s1
{
address = "0x00200000";
span = "0x00000020";
is_bridge = "0";
}
}
}
WIZARD_SCRIPT_ARGUMENTS
@@ -1445,7 +1454,7 @@ SYSTEM Video_System
}
HDL_INFO
{
Simulation_HDL_Files = "C:/sean_fei/legit_start/verilog/Dual_Clock_FIFO.v";
Simulation_HDL_Files = "C:/our_shit/ECE5760Projects/legit_start/verilog/Dual_Clock_FIFO.v";
}
WIZARD_SCRIPT_ARGUMENTS
{
@@ -1561,7 +1570,7 @@ SYSTEM Video_System
}
HDL_INFO
{
Simulation_HDL_Files = "C:/sean_fei/legit_start/verilog/Clock_Signals.v";
Simulation_HDL_Files = "C:/our_shit/ECE5760Projects/legit_start/verilog/Clock_Signals.v";
}
WIZARD_SCRIPT_ARGUMENTS
{
@@ -1758,7 +1767,7 @@ SYSTEM Video_System
}
HDL_INFO
{
Simulation_HDL_Files = "C:/sean_fei/legit_start/verilog/Pixel_Buffer.v";
Simulation_HDL_Files = "C:/our_shit/ECE5760Projects/legit_start/verilog/Pixel_Buffer.v";
}
WIZARD_SCRIPT_ARGUMENTS
{
@@ -2014,7 +2023,7 @@ SYSTEM Video_System
}
HDL_INFO
{
Simulation_HDL_Files = "C:/sean_fei/legit_start/verilog/Pixel_Buffer_DMA.v";
Simulation_HDL_Files = "C:/our_shit/ECE5760Projects/legit_start/verilog/Pixel_Buffer_DMA.v";
}
WIZARD_SCRIPT_ARGUMENTS
{
@@ -2154,7 +2163,7 @@ SYSTEM Video_System
}
HDL_INFO
{
Simulation_HDL_Files = "C:/sean_fei/legit_start/verilog/Pixel_RGB_Resampler.v";
Simulation_HDL_Files = "C:/our_shit/ECE5760Projects/legit_start/verilog/Pixel_RGB_Resampler.v";
}
WIZARD_SCRIPT_ARGUMENTS
{
@@ -2308,7 +2317,7 @@ SYSTEM Video_System
}
HDL_INFO
{
Simulation_HDL_Files = "C:/sean_fei/legit_start/verilog/VGA_Controller.v";
Simulation_HDL_Files = "C:/our_shit/ECE5760Projects/legit_start/verilog/VGA_Controller.v";
}
WIZARD_SCRIPT_ARGUMENTS
{
@@ -2729,4 +2738,173 @@ SYSTEM Video_System
# various filenames are known.
}
}
MODULE sound
{
SLAVE s1
{
PORT_WIRING
{
PORT clk
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT reset_n
{
type = "reset_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT address
{
type = "address";
width = "3";
direction = "input";
Is_Enabled = "1";
}
PORT write_n
{
type = "write_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT writedata
{
type = "writedata";
width = "32";
direction = "input";
Is_Enabled = "1";
}
PORT chipselect
{
type = "chipselect";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT readdata
{
type = "readdata";
width = "32";
direction = "output";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Write_Wait_States = "0cycles";
Read_Wait_States = "1cycles";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "0";
Address_Alignment = "native";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Read_Latency = "0";
Is_Memory_Device = "0";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Write_Latency = "0";
Is_Flash = "0";
Data_Width = "32";
Address_Width = "3";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
MASTERED_BY CPU/data_master
{
priority = "1";
Offset_Address = "0x00200000";
}
Base_Address = "0x00200000";
Has_IRQ = "0";
Address_Group = "0";
IRQ_MASTER CPU/data_master
{
IRQ_Number = "NC";
}
Is_Readable = "0";
Is_Writable = "1";
}
}
PORT_WIRING
{
PORT out_port
{
type = "export";
width = "32";
direction = "output";
Is_Enabled = "1";
}
PORT in_port
{
direction = "input";
Is_Enabled = "0";
width = "32";
}
PORT bidir_port
{
direction = "inout";
Is_Enabled = "0";
width = "32";
}
}
class = "altera_avalon_pio";
class_version = "7.08110";
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Wire_Test_Bench_Values = "1";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
Has_Clock = "1";
Date_Modified = "";
View
{
MESSAGES
{
}
Settings_Summary = " 32-bit PIO using <br>


output pins";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
Do_Test_Bench_Wiring = "0";
Driven_Sim_Value = "0";
has_tri = "0";
has_out = "1";
has_in = "0";
capture = "0";
Data_Width = "8";
reset_value = "0";
edge_type = "NONE";
irq_type = "NONE";
bit_clearing_edge_register = "0";
bit_modifying_output_register = "1";
}
HDL_INFO
{
# The list of files associated with this module (for synthesis
# and other purposes) depends on the users' wizard-choices.
# This section will be filled-in by the Generator_Program
# after the module logic has been created and the
# various filenames are known.
}
}
}
153 legit_start/verilog/Video_System.ptf.pre_generation_ptf
View file
@@ -2,7 +2,7 @@ SYSTEM Video_System
{
#
# Generated by: com.altera.sopcmodel.ensemble.EnsembleGeneratePTF
# Date: 2015.02.19.18:00:24
# Date: 2015.02.26.18:26:53
#
# clock_source "clk"
# altera_nios2 "CPU"
@@ -15,8 +15,9 @@ SYSTEM Video_System
# altera_up_avalon_video_vga_controller "VGA_Controller"
# altera_avalon_jtag_uart "jtag_uart_0"
# altera_avalon_pio "pio_0"
# altera_avalon_pio "sound"
#
# Contains 26 connections.
# Contains 28 connections.
#
System_Wizard_Version = "8.0";
Builder_Application = "sopc_builder_ca";
@@ -526,6 +527,12 @@ SYSTEM Video_System
span = "0x00000010";
is_bridge = "0";
}
Entry sound/s1
{
address = "0x00200000";
span = "0x00000020";
is_bridge = "0";
}
}
}
WIZARD_SCRIPT_ARGUMENTS
@@ -958,7 +965,7 @@ SYSTEM Video_System
}
HDL_INFO
{
Simulation_HDL_Files = "C:/sean_fei/legit_start/verilog/Dual_Clock_FIFO.v";
Simulation_HDL_Files = "C:/our_shit/ECE5760Projects/legit_start/verilog/Dual_Clock_FIFO.v";
}
WIZARD_SCRIPT_ARGUMENTS
{
@@ -1062,7 +1069,7 @@ SYSTEM Video_System
}
HDL_INFO
{
Simulation_HDL_Files = "C:/sean_fei/legit_start/verilog/Clock_Signals.v";
Simulation_HDL_Files = "C:/our_shit/ECE5760Projects/legit_start/verilog/Clock_Signals.v";
}
WIZARD_SCRIPT_ARGUMENTS
{
@@ -1248,7 +1255,7 @@ SYSTEM Video_System
}
HDL_INFO
{
Simulation_HDL_Files = "C:/sean_fei/legit_start/verilog/Pixel_Buffer.v";
Simulation_HDL_Files = "C:/our_shit/ECE5760Projects/legit_start/verilog/Pixel_Buffer.v";
}
WIZARD_SCRIPT_ARGUMENTS
{
@@ -1493,7 +1500,7 @@ SYSTEM Video_System
}
HDL_INFO
{
Simulation_HDL_Files = "C:/sean_fei/legit_start/verilog/Pixel_Buffer_DMA.v";
Simulation_HDL_Files = "C:/our_shit/ECE5760Projects/legit_start/verilog/Pixel_Buffer_DMA.v";
}
WIZARD_SCRIPT_ARGUMENTS
{
@@ -1625,7 +1632,7 @@ SYSTEM Video_System
}
HDL_INFO
{
Simulation_HDL_Files = "C:/sean_fei/legit_start/verilog/Pixel_RGB_Resampler.v";
Simulation_HDL_Files = "C:/our_shit/ECE5760Projects/legit_start/verilog/Pixel_RGB_Resampler.v";
}
WIZARD_SCRIPT_ARGUMENTS
{
@@ -1771,7 +1778,7 @@ SYSTEM Video_System
}
HDL_INFO
{
Simulation_HDL_Files = "C:/sean_fei/legit_start/verilog/VGA_Controller.v";
Simulation_HDL_Files = "C:/our_shit/ECE5760Projects/legit_start/verilog/VGA_Controller.v";
}
WIZARD_SCRIPT_ARGUMENTS
{
@@ -2140,4 +2147,134 @@ SYSTEM Video_System
bit_modifying_output_register = "0";
}
}
MODULE sound
{
SLAVE s1
{
PORT_WIRING
{
PORT clk
{
type = "clk";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT reset_n
{
type = "reset_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT address
{
type = "address";
width = "3";
direction = "input";
Is_Enabled = "1";
}
PORT write_n
{
type = "write_n";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT writedata
{
type = "writedata";
width = "32";
direction = "input";
Is_Enabled = "1";
}
PORT chipselect
{
type = "chipselect";
width = "1";
direction = "input";
Is_Enabled = "1";
}
PORT readdata
{
type = "readdata";
width = "32";
direction = "output";
Is_Enabled = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Write_Wait_States = "0cycles";
Read_Wait_States = "1cycles";
Hold_Time = "0cycles";
Setup_Time = "0cycles";
Is_Printable_Device = "0";
Address_Alignment = "native";
Well_Behaved_Waitrequest = "0";
Is_Nonvolatile_Storage = "0";
Read_Latency = "0";
Is_Memory_Device = "0";
Maximum_Pending_Read_Transactions = "0";
Minimum_Uninterrupted_Run_Length = "1";
Accepts_Internal_Connections = "1";
Write_Latency = "0";
Is_Flash = "0";
Data_Width = "32";
Address_Width = "3";
Maximum_Burst_Size = "1";
Register_Incoming_Signals = "0";
Register_Outgoing_Signals = "0";
Interleave_Bursts = "0";
Linewrap_Bursts = "0";
Burst_On_Burst_Boundaries_Only = "0";
Always_Burst_Max_Burst = "0";
Is_Big_Endian = "0";
Is_Enabled = "1";
MASTERED_BY CPU/data_master
{
priority = "1";
Offset_Address = "0x00200000";
}
Base_Address = "0x00200000";
}
}
PORT_WIRING
{
PORT out_port
{
type = "export";
width = "8";
direction = "output";
Is_Enabled = "1";
}
}
class = "altera_avalon_pio";
class_version = "11.0";
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Wire_Test_Bench_Values = "1";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
Has_Clock = "1";
}
WIZARD_SCRIPT_ARGUMENTS
{
Do_Test_Bench_Wiring = "0";
Driven_Sim_Value = "0";
has_tri = "0";
has_out = "1";
has_in = "0";
capture = "0";
Data_Width = "8";
reset_value = "0";
edge_type = "NONE";
irq_type = "NONE";
bit_clearing_edge_register = "0";
bit_modifying_output_register = "1";
}
}
}
3 legit_start/verilog/Video_System.qip
View file
@@ -25,5 +25,6 @@ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) VGA_Con
# pio_0
# null
set_global_assignment -name SDC_FILE [file join $::quartus(ip_rootpath) altera/sopc_builder_ip/altera_avalon_clock_adapter/altera_avalon_clock_adapter.sdc]
set_global_assignment -name SOPC_BUILDER_SIGNATURE_ID 00000000000000E00000014BA41205AB
# sound
set_global_assignment -name SOPC_BUILDER_SIGNATURE_ID 00000000000000E00000014BC836753F

50 legit_start/verilog/Video_System.sopc
View file
@@ -188,6 +188,19 @@
type = "int";
}
}
element pio_0.s1
{
datum _tags
{
value = "";
type = "String";
}
datum baseAddress
{
value = "3149840";
type = "long";
}
}
element Onchip_Memory.s1
{
datum baseAddress
@@ -196,14 +209,22 @@
type = "long";
}
}
element pio_0.s1
element sound.s1
{
datum baseAddress
{
value = "3149840";
value = "2097152";
type = "long";
}
}
element sound
{
datum _sortIndex
{
value = "11";
type = "int";
}
}
element Clock_Signals.sys_clk
{
datum _clockDomain
@@ -232,8 +253,8 @@
<parameter name="maxAdditionalLatency" value="0" />
<parameter name="projectName">Example_4_Video_In.qpf</parameter>
<parameter name="sopcBorderPoints" value="true" />
<parameter name="systemHash" value="41742192577" />
<parameter name="timeStamp" value="1424386795009" />
<parameter name="systemHash" value="45866325928" />
<parameter name="timeStamp" value="1424994512216" />
<module kind="clock_source" version="11.0" enabled="1" name="clk">
<parameter name="clockFrequency" value="50000000" />
<parameter name="clockFrequencyKnown" value="true" />
@@ -333,7 +354,7 @@
<parameter name="dcache_numTCDM" value="_0" />
<parameter name="dcache_lineSize" value="_32" />
<parameter name="dcache_bursts" value="false" />
<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='Pixel_Buffer.avalon_sram_slave' start='0x0' end='0x200000' /><slave name='Onchip_Memory.s1' start='0x280000' end='0x2E1A80' /><slave name='CPU.jtag_debug_module' start='0x300800' end='0x301000' /><slave name='Pixel_Buffer_DMA.avalon_control_slave' start='0x301000' end='0x301010' /><slave name='pio_0.s1' start='0x301010' end='0x301020' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x301020' end='0x301028' /><slave name='Clock_Signals.avalon_clocks_slave' start='0x301028' end='0x30102A' /></address-map>]]></parameter>
<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='Pixel_Buffer.avalon_sram_slave' start='0x0' end='0x200000' /><slave name='sound.s1' start='0x200000' end='0x200020' /><slave name='Onchip_Memory.s1' start='0x280000' end='0x2E1A80' /><slave name='CPU.jtag_debug_module' start='0x300800' end='0x301000' /><slave name='Pixel_Buffer_DMA.avalon_control_slave' start='0x301000' end='0x301010' /><slave name='pio_0.s1' start='0x301010' end='0x301020' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x301020' end='0x301028' /><slave name='Clock_Signals.avalon_clocks_slave' start='0x301028' end='0x30102A' /></address-map>]]></parameter>
<parameter name="dataAddrWidth" value="22" />
<parameter name="customInstSlavesSystemInfo" value="&lt;info/&gt;" />
<parameter name="cpuReset" value="false" />
@@ -469,6 +490,20 @@
<parameter name="simDrivenValue" value="0" />
<parameter name="width" value="4" />
</module>
<module kind="altera_avalon_pio" version="11.0" enabled="1" name="sound">
<parameter name="bitClearingEdgeCapReg" value="false" />
<parameter name="bitModifyingOutReg" value="true" />
<parameter name="captureEdge" value="false" />
<parameter name="clockRate" value="50000000" />
<parameter name="direction" value="Output" />
<parameter name="edgeType" value="RISING" />
<parameter name="generateIRQ" value="false" />
<parameter name="irqType" value="LEVEL" />
<parameter name="resetValue" value="0" />
<parameter name="simDoTestBenchWiring" value="false" />
<parameter name="simDrivenValue" value="0" />
<parameter name="width" value="8" />
</module>
<connection
kind="avalon"
version="11.0"
@@ -617,4 +652,9 @@
<connection kind="interrupt" version="11.0" start="CPU.d_irq" end="pio_0.irq">
<parameter name="irqNumber" value="1" />
</connection>
<connection kind="clock" version="11.0" start="clk.clk" end="sound.clk" />
<connection kind="avalon" version="11.0" start="CPU.data_master" end="sound.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00200000" />
</connection>
</system>
1,376 legit_start/verilog/Video_System.sopcinfo
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977 legit_start/verilog/Video_System.v
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2 legit_start/verilog/Video_System_generation_script
View file
@@ -2,4 +2,4 @@

c:/altera/11.0/quartus//bin/perl/bin/perl -I$sopc_builder/bin -I$sopc_builder/bin/perl_lib -I$sopc_builder/bin/europa $sopc_builder/bin/ptf_update.pl Video_System.ptf

c:/altera/11.0/quartus//bin/perl/bin/perl -I$sopc_builder/bin -I$sopc_builder/bin/perl_lib -I$sopc_builder/bin/europa $sopc_builder/bin/mk_systembus.pl --sopc_directory=$sopc_builder --sopc_perl=c:/altera/11.0/quartus//bin/perl --sopc_lib_path="C:/sean_fei/legit_start/verilog+C:/altera/11.0/ip/altera/sopc_builder_ip+C:/altera/11.0/ip/altera/pci_compiler/lib/sopc_builder+C:/altera/11.0/ip/altera/ip_compiler_for_pci_express/lib/sopc_builder+C:/altera/11.0/ip/altera/nios2_ip+C:/altera/11.0/ip/altera/ddr_high_perf/lib/sopc_builder+C:/altera/11.0/ip/altera/ddr2_high_perf/lib/sopc_builder+C:/altera/11.0/ip/altera/ddr3_high_perf/lib/sopc_builder+C:/altera/11.0/ip/altera/ddr_ddr2_sdram/lib/sopc_builder+C:/altera/11.0/ip/altera/triple_speed_ethernet/lib/sopc_builder+c:/altera/11.0/quartus//../ip/altera/sopc_builder_ip+c:/altera/11.0/quartus//../ip/altera/nios2_ip+c:/altera/11.0/quartus//sopc_builder/components" --target_module_name=Video_System --system_directory=C:/sean_fei/legit_start/verilog --system_name=Video_System --project_name=Example_4_Video_In.qpf --sopc_quartus_dir= $1
c:/altera/11.0/quartus//bin/perl/bin/perl -I$sopc_builder/bin -I$sopc_builder/bin/perl_lib -I$sopc_builder/bin/europa $sopc_builder/bin/mk_systembus.pl --sopc_directory=$sopc_builder --sopc_perl=c:/altera/11.0/quartus//bin/perl --sopc_lib_path="C:/our_shit/ECE5760Projects/legit_start/verilog+C:/altera/11.0/ip/altera/sopc_builder_ip+C:/altera/11.0/ip/altera/pci_compiler/lib/sopc_builder+C:/altera/11.0/ip/altera/ip_compiler_for_pci_express/lib/sopc_builder+C:/altera/11.0/ip/altera/nios2_ip+C:/altera/11.0/ip/altera/ddr_high_perf/lib/sopc_builder+C:/altera/11.0/ip/altera/ddr2_high_perf/lib/sopc_builder+C:/altera/11.0/ip/altera/ddr3_high_perf/lib/sopc_builder+C:/altera/11.0/ip/altera/ddr_ddr2_sdram/lib/sopc_builder+C:/altera/11.0/ip/altera/triple_speed_ethernet/lib/sopc_builder+c:/altera/11.0/quartus//../ip/altera/sopc_builder_ip+c:/altera/11.0/quartus//../ip/altera/nios2_ip+c:/altera/11.0/quartus//sopc_builder/components" --target_module_name=Video_System --system_directory=C:/our_shit/ECE5760Projects/legit_start/verilog --system_name=Video_System --project_name=Example_4_Video_In.qpf --sopc_quartus_dir= $1
1 legit_start/verilog/Video_System_inst.v
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@@ -18,6 +18,7 @@
.VGA_VS_from_the_VGA_Controller (VGA_VS_from_the_VGA_Controller),
.clk (clk),
.in_port_to_the_pio_0 (in_port_to_the_pio_0),
.out_port_from_the_sound (out_port_from_the_sound),
.reset_n (reset_n),
.sys_clk (sys_clk),
.vga_clk (vga_clk)
93 legit_start/verilog/Video_System_log.txt
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@@ -3,77 +3,82 @@ Copyright (c) 1999-2009 Altera Corporation. All rights reserved.


No .sopc_builder configuration file(!)
# 2015.02.19 18:00:39 (*) mk_custom_sdk starting
# 2015.02.19 18:00:39 (*) Reading project C:/sean_fei/legit_start/verilog/Video_System.ptf.
# 2015.02.26 18:27:16 (*) mk_custom_sdk starting
# 2015.02.26 18:27:16 (*) Reading project C:/our_shit/ECE5760Projects/legit_start/verilog/Video_System.ptf.

# 2015.02.19 18:00:39 (*) Finding all CPUs
# 2015.02.19 18:00:39 (*) Finding all available components
# 2015.02.19 18:00:39 (*) Reading C:/sean_fei/legit_start/verilog/.sopc_builder/install.ptf
# 2015.02.26 18:27:16 (*) Finding all CPUs
# 2015.02.26 18:27:16 (*) Finding all available components
# 2015.02.26 18:27:16 (*) Reading C:/our_shit/ECE5760Projects/legit_start/verilog/.sopc_builder/install.ptf

# 2015.02.19 18:00:39 (*) Found 63 components
# 2015.02.26 18:27:16 (*) Found 63 components

# 2015.02.19 18:00:40 (*) Finding all peripherals
# 2015.02.26 18:27:17 (*) Finding all peripherals

# 2015.02.19 18:00:40 (*) Finding software components
# 2015.02.26 18:27:17 (*) Finding software components

# 2015.02.19 18:00:40 (*) (Legacy SDK Generation Skipped)
# 2015.02.19 18:00:40 (*) (All TCL Script Generation Skipped)
# 2015.02.19 18:00:40 (*) (No Libraries Built)
# 2015.02.19 18:00:40 (*) (Contents Generation Skipped)
# 2015.02.19 18:00:40 (*) mk_custom_sdk finishing
# 2015.02.19 18:00:40 (*) Starting generation for system: Video_System.
# 2015.02.26 18:27:17 (*) (Legacy SDK Generation Skipped)
# 2015.02.26 18:27:17 (*) (All TCL Script Generation Skipped)
# 2015.02.26 18:27:17 (*) (No Libraries Built)
# 2015.02.26 18:27:17 (*) (Contents Generation Skipped)
# 2015.02.26 18:27:17 (*) mk_custom_sdk finishing
# 2015.02.26 18:27:17 (*) Starting generation for system: Video_System.

.
.
.
..
.
.
....

# 2015.02.26 18:27:18 (*) Running Generator Program for CPU

# 2015.02.26 18:27:20 (*) Starting Nios II generation
# 2015.02.26 18:27:20 (*) Checking for plaintext license.
# 2015.02.26 18:27:20 (*) Plaintext license not found.
# 2015.02.26 18:27:20 (*) No license required to generate encrypted Nios II/e.
# 2015.02.26 18:27:20 (*) Getting CPU configuration settings
# 2015.02.26 18:27:20 (*) Elaborating CPU configuration settings
# 2015.02.26 18:27:20 (*) Creating all objects for CPU
# 2015.02.26 18:27:22 (*) Generating HDL from CPU objects
# 2015.02.26 18:27:22 (*) Creating plain-text HDL

# 2015.02.26 18:27:24 (*) Done Nios II generation

# 2015.02.26 18:27:24 (*) Running Generator Program for Onchip_Memory

# 2015.02.19 18:00:41 (*) Running Generator Program for CPU
# 2015.02.26 18:27:26 (*) Running Generator Program for jtag_uart_0

# 2015.02.19 18:00:42 (*) Starting Nios II generation
# 2015.02.19 18:00:42 (*) Checking for plaintext license.
# 2015.02.19 18:00:42 (*) Plaintext license not found.
# 2015.02.19 18:00:42 (*) No license required to generate encrypted Nios II/e.
# 2015.02.19 18:00:42 (*) Getting CPU configuration settings
# 2015.02.19 18:00:42 (*) Elaborating CPU configuration settings
# 2015.02.19 18:00:43 (*) Creating all objects for CPU
# 2015.02.19 18:00:44 (*) Generating HDL from CPU objects
# 2015.02.19 18:00:44 (*) Creating plain-text HDL
# 2015.02.26 18:27:27 (*) Running Generator Program for pio_0

# 2015.02.19 18:00:46 (*) Done Nios II generation
# 2015.02.26 18:27:28 (*) Running Generator Program for sound

# 2015.02.19 18:00:46 (*) Running Generator Program for Onchip_Memory
# 2015.02.26 18:27:29 (*) Running Generator Program for Video_System_clock_0

# 2015.02.19 18:00:48 (*) Running Generator Program for jtag_uart_0
# 2015.02.26 18:27:30 (*) Running Generator Program for Video_System_clock_1

# 2015.02.19 18:00:49 (*) Running Generator Program for pio_0
# 2015.02.26 18:27:31 (*) Running Generator Program for Video_System_clock_2

# 2015.02.19 18:00:50 (*) Running Generator Program for Video_System_clock_0
# 2015.02.26 18:27:32 (*) Running Generator Program for Video_System_clock_3

# 2015.02.19 18:00:51 (*) Running Generator Program for Video_System_clock_1

# 2015.02.19 18:00:52 (*) Running Generator Program for Video_System_clock_2
# 2015.02.26 18:27:33 (*) Making arbitration and system (top) modules.

# 2015.02.26 18:27:38 (*) Generating Quartus symbol for top level: Video_System

# 2015.02.19 18:00:53 (*) Making arbitration and system (top) modules.
# 2015.02.26 18:27:38 (*) Generating Symbol C:/our_shit/ECE5760Projects/legit_start/verilog/Video_System.bsf

# 2015.02.19 18:00:57 (*) Generating Quartus symbol for top level: Video_System
# 2015.02.26 18:27:38 (*) Creating command-line system-generation script: C:/our_shit/ECE5760Projects/legit_start/verilog/Video_System_generation_script

# 2015.02.19 18:00:57 (*) Symbol C:/sean_fei/legit_start/verilog/Video_System.bsf already exists, no need to regenerate
# 2015.02.19 18:00:57 (*) Creating command-line system-generation script: C:/sean_fei/legit_start/verilog/Video_System_generation_script
# 2015.02.26 18:27:38 (*) Running setup for HDL simulator: modelsim

# 2015.02.19 18:00:58 (*) Running setup for HDL simulator: modelsim

# 2015.02.26 18:27:39 (*) Completed generation for system: Video_System.
# 2015.02.26 18:27:39 (*) THE FOLLOWING SYSTEM ITEMS HAVE BEEN GENERATED:

# 2015.02.19 18:00:58 (*) Completed generation for system: Video_System.
# 2015.02.19 18:00:58 (*) THE FOLLOWING SYSTEM ITEMS HAVE BEEN GENERATED:
SOPC Builder database : C:/sean_fei/legit_start/verilog/Video_System.ptf
System HDL Model : C:/sean_fei/legit_start/verilog/Video_System.v
System Generation Script : C:/sean_fei/legit_start/verilog/Video_System_generation_script
SOPC Builder database : C:/our_shit/ECE5760Projects/legit_start/verilog/Video_System.ptf
System HDL Model : C:/our_shit/ECE5760Projects/legit_start/verilog/Video_System.v
System Generation Script : C:/our_shit/ECE5760Projects/legit_start/verilog/Video_System_generation_script

# 2015.02.19 18:00:58 (*) SUCCESS: SYSTEM GENERATION COMPLETED.
# 2015.02.26 18:27:39 (*) SUCCESS: SYSTEM GENERATION COMPLETED.


Press 'Exit' to exit.
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4 legit_start/verilog/db/Example_4_Video_In.asm.qmsg
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@@ -1,6 +1,6 @@
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Info: Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 11.0 Build 157 04/27/2011 SJ Full Version " "Info: Version 11.0 Build 157 04/27/2011 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Wed Feb 25 12:04:52 2015 " "Info: Processing started: Wed Feb 25 12:04:52 2015" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Info: Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 11.0 Build 157 04/27/2011 SJ Full Version " "Info: Version 11.0 Build 157 04/27/2011 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 26 18:59:36 2015 " "Info: Processing started: Thu Feb 26 18:59:36 2015" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off Example_4_Video_In -c Example_4_Video_In " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off Example_4_Video_In -c Example_4_Video_In" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "615 " "Info: Peak virtual memory: 615 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Feb 25 12:05:02 2015 " "Info: Processing ended: Wed Feb 25 12:05:02 2015" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Info: Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:10 " "Info: Total CPU time (on all processors): 00:00:10" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "619 " "Info: Peak virtual memory: 619 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 26 18:59:47 2015 " "Info: Processing ended: Thu Feb 26 18:59:47 2015" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Info: Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Info: Total CPU time (on all processors): 00:00:09" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
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BIN -4.27 KB (98%) legit_start/verilog/db/Example_4_Video_In.asm_labs.ddb
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2 legit_start/verilog/db/Example_4_Video_In.cmp.logdb
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@@ -120,9 +120,9 @@ IO_RULES_MATRIX,SRAM_DQ[14],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;I
IO_RULES_MATRIX,SRAM_DQ[15],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,CLOCK_50,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,KEY[0],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,KEY[1],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,KEY[3],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,KEY[2],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,KEY[1],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,altera_reserved_tms,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,altera_reserved_tck,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
IO_RULES_MATRIX,altera_reserved_tdi,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
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52 legit_start/verilog/db/Example_4_Video_In.fit.qmsg
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198 legit_start/verilog/db/Example_4_Video_In.lpc.html
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@@ -208,6 +208,38 @@
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Video_System_inst|the_sound</TD>
<TD ALIGN="LEFT">39</TD>
<TD ALIGN="LEFT">24</TD>
<TD ALIGN="LEFT">24</TD>
<TD ALIGN="LEFT">24</TD>
<TD ALIGN="LEFT">40</TD>
<TD ALIGN="LEFT">24</TD>
<TD ALIGN="LEFT">24</TD>
<TD ALIGN="LEFT">24</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Video_System_inst|the_sound_s1</TD>
<TD ALIGN="LEFT">76</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">5</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">75</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Video_System_inst|the_pio_0</TD>
<TD ALIGN="LEFT">42</TD>
<TD ALIGN="LEFT">0</TD>
@@ -560,6 +592,166 @@
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Video_System_inst|the_Video_System_clock_3|endofpacket_bit_pipe</TD>
<TD ALIGN="LEFT">5</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Video_System_inst|the_Video_System_clock_3|master_FSM</TD>
<TD ALIGN="LEFT">5</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">4</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Video_System_inst|the_Video_System_clock_3|write_request_edge_to_pulse</TD>
<TD ALIGN="LEFT">3</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Video_System_inst|the_Video_System_clock_3|read_request_edge_to_pulse</TD>
<TD ALIGN="LEFT">3</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Video_System_inst|the_Video_System_clock_3|slave_FSM</TD>
<TD ALIGN="LEFT">6</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">3</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Video_System_inst|the_Video_System_clock_3|write_done_edge_to_pulse</TD>
<TD ALIGN="LEFT">3</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Video_System_inst|the_Video_System_clock_3|read_done_edge_to_pulse</TD>
<TD ALIGN="LEFT">3</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Video_System_inst|the_Video_System_clock_3</TD>
<TD ALIGN="LEFT">84</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">80</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Video_System_inst|the_Video_System_clock_3_out</TD>
<TD ALIGN="LEFT">82</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">40</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">39</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Video_System_inst|the_Video_System_clock_3_in</TD>
<TD ALIGN="LEFT">97</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">2</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">86</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Video_System_inst|the_Video_System_clock_2|endofpacket_bit_pipe</TD>
<TD ALIGN="LEFT">5</TD>
<TD ALIGN="LEFT">0</TD>
@@ -2497,9 +2689,9 @@
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Video_System_inst|the_CPU_data_master</TD>
<TD ALIGN="LEFT">290</TD>
<TD ALIGN="LEFT">328</TD>
<TD ALIGN="LEFT">30</TD>
<TD ALIGN="LEFT">17</TD>
<TD ALIGN="LEFT">20</TD>
<TD ALIGN="LEFT">30</TD>
<TD ALIGN="LEFT">114</TD>
<TD ALIGN="LEFT">30</TD>
@@ -2533,7 +2725,7 @@
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">54</TD>
<TD ALIGN="LEFT">62</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">1</TD>
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16 legit_start/verilog/db/Example_4_Video_In.lpc.txt
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@@ -15,6 +15,8 @@
; Video_System_inst|Video_System_reset_vga_clk_domain_synch ; 3 ; 1 ; 0 ; 1 ; 1 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; Video_System_inst|Video_System_reset_clk_domain_synch ; 3 ; 1 ; 0 ; 1 ; 1 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; Video_System_inst|Video_System_reset_sys_clk_domain_synch ; 3 ; 1 ; 0 ; 1 ; 1 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; Video_System_inst|the_sound ; 39 ; 24 ; 24 ; 24 ; 40 ; 24 ; 24 ; 24 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; Video_System_inst|the_sound_s1 ; 76 ; 1 ; 5 ; 1 ; 75 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; Video_System_inst|the_pio_0 ; 42 ; 0 ; 28 ; 0 ; 33 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; Video_System_inst|the_pio_0_s1 ; 75 ; 1 ; 4 ; 1 ; 75 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; Video_System_inst|the_jtag_uart_0|the_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|wr_ptr ; 4 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
@@ -37,6 +39,16 @@
; Video_System_inst|the_jtag_uart_0|the_jtag_uart_0_scfifo_w ; 12 ; 0 ; 0 ; 0 ; 16 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; Video_System_inst|the_jtag_uart_0 ; 38 ; 10 ; 23 ; 10 ; 36 ; 10 ; 10 ; 10 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; Video_System_inst|the_jtag_uart_0_avalon_jtag_slave ; 76 ; 1 ; 3 ; 1 ; 78 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; Video_System_inst|the_Video_System_clock_3|endofpacket_bit_pipe ; 5 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; Video_System_inst|the_Video_System_clock_3|master_FSM ; 5 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; Video_System_inst|the_Video_System_clock_3|write_request_edge_to_pulse ; 3 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; Video_System_inst|the_Video_System_clock_3|read_request_edge_to_pulse ; 3 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; Video_System_inst|the_Video_System_clock_3|slave_FSM ; 6 ; 0 ; 0 ; 0 ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; Video_System_inst|the_Video_System_clock_3|write_done_edge_to_pulse ; 3 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; Video_System_inst|the_Video_System_clock_3|read_done_edge_to_pulse ; 3 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; Video_System_inst|the_Video_System_clock_3 ; 84 ; 1 ; 0 ; 1 ; 80 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; Video_System_inst|the_Video_System_clock_3_out ; 82 ; 0 ; 40 ; 0 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; Video_System_inst|the_Video_System_clock_3_in ; 97 ; 1 ; 2 ; 1 ; 86 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; Video_System_inst|the_Video_System_clock_2|endofpacket_bit_pipe ; 5 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; Video_System_inst|the_Video_System_clock_2|master_FSM ; 5 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; Video_System_inst|the_Video_System_clock_2|write_request_edge_to_pulse ; 3 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
@@ -158,7 +170,7 @@
; Video_System_inst|the_CPU_instruction_master ; 99 ; 1 ; 5 ; 1 ; 55 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; Video_System_inst|the_CPU_data_master|pio_0_s1_irq_from_sa_clock_crossing_CPU_data_master ; 3 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; Video_System_inst|the_CPU_data_master|jtag_uart_0_avalon_jtag_slave_irq_from_sa_clock_crossing_CPU_data_master ; 3 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; Video_System_inst|the_CPU_data_master ; 290 ; 30 ; 17 ; 30 ; 114 ; 30 ; 30 ; 30 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; Video_System_inst|the_CPU_data_master ; 328 ; 30 ; 20 ; 30 ; 114 ; 30 ; 30 ; 30 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; Video_System_inst|the_CPU_jtag_debug_module ; 120 ; 2 ; 4 ; 2 ; 92 ; 2 ; 2 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; Video_System_inst ; 6 ; 1 ; 0 ; 1 ; 54 ; 1 ; 1 ; 1 ; 16 ; 0 ; 0 ; 0 ; 0 ;
; Video_System_inst ; 6 ; 1 ; 0 ; 1 ; 62 ; 1 ; 1 ; 1 ; 16 ; 0 ; 0 ; 0 ; 0 ;
+----------------------------------------------------------------------------------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
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12 legit_start/verilog/db/Example_4_Video_In.smp_dump.txt
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@@ -5,6 +5,18 @@ mSetup_ST.0000 0 0 0
mSetup_ST.0001 1 0 1
mSetup_ST.0010 1 1 0

State Machine - |Example_4_Video_In|Video_System:Video_System_inst|Video_System_clock_3:the_Video_System_clock_3|Video_System_clock_3_master_FSM:master_FSM|master_state
Name master_state.100 master_state.010 master_state.001
master_state.001 0 0 0
master_state.010 0 1 1
master_state.100 1 0 1

State Machine - |Example_4_Video_In|Video_System:Video_System_inst|Video_System_clock_3:the_Video_System_clock_3|Video_System_clock_3_slave_FSM:slave_FSM|slave_state
Name slave_state.100 slave_state.010 slave_state.001
slave_state.001 0 0 0
slave_state.010 0 1 1
slave_state.100 1 0 1

State Machine - |Example_4_Video_In|Video_System:Video_System_inst|Video_System_clock_2:the_Video_System_clock_2|Video_System_clock_2_master_FSM:master_FSM|master_state
Name master_state.100 master_state.010 master_state.001
master_state.001 0 0 0
36 legit_start/verilog/db/Example_4_Video_In.sta.qmsg
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285 legit_start/verilog/db/prev_cmp_Example_4_Video_In.qmsg
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496 legit_start/verilog/db/sopcb_tb2_Video_System.xml
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BIN +6.42 KB (100%) ...tart/verilog/incremental_db/compiled_partitions/Example_4_Video_In.root_partition.cmp.cdb
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688 legit_start/verilog/software/.metadata/.log
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1 legit_start/verilog/software/.metadata/.plugins/org.eclipse.cdt.core/.log
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@@ -1 +1,2 @@
*** SESSION Feb 25, 2015 11:53:55.97 -------------------------------------------
*** SESSION Feb 26, 2015 18:20:24.68 -------------------------------------------
BIN +20 KB (100%) ...art/verilog/software/.metadata/.plugins/org.eclipse.cdt.core/legit_BSP.1424883320800.pdom
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23 legit_start/verilog/software/.metadata/.plugins/org.eclipse.cdt.make.core/legit_app.sc
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@@ -4,6 +4,15 @@
<scannerInfo id="org.eclipse.cdt.make.core.discoveredScannerInfo">
<instance id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1624212479;preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1624212479.;cdt.managedbuild.tool.gnu.cpp.compiler.cygwin.base.1147992395;cdt.managedbuild.tool.gnu.cpp.compiler.input.cygwin.139992917">
<collector id="org.eclipse.cdt.make.core.PerProjectSICollector">
<includePath path="C:/our_shit/ECE5760Projects/legit_start/verilog/software/legit_BSP/HAL/inc"/>
<includePath path="C:/our_shit/ECE5760Projects/legit_start/verilog/software/legit_BSP/"/>
<includePath path="C:/our_shit/ECE5760Projects/legit_start/verilog/software/legit_BSP/drivers/inc"/>
<includePath path="c:\altera\11.0\quartus\bin\cygwin\lib\gcc\i686-pc-cygwin\3.4.4\include\c++"/>
<includePath path="c:\altera\11.0\quartus\bin\cygwin\lib\gcc\i686-pc-cygwin\3.4.4\include\c++\i686-pc-cygwin"/>
<includePath path="c:\altera\11.0\quartus\bin\cygwin\lib\gcc\i686-pc-cygwin\3.4.4\include\c++\backward"/>
<includePath path="c:\altera\11.0\quartus\bin\cygwin\lib\gcc\i686-pc-cygwin\3.4.4\include"/>
<includePath path="c:\altera\11.0\quartus\bin\cygwin\usr\include"/>
<includePath path="c:\altera\11.0\quartus\bin\cygwin\usr\include\w32api"/>
<includePath path="C:\altera\11.0\quartus\bin\cygwin\lib\gcc\i686-pc-cygwin\3.4.4\include\c++"/>
<includePath path="C:\altera\11.0\quartus\bin\cygwin\lib\gcc\i686-pc-cygwin\3.4.4\include\c++\i686-pc-cygwin"/>
<includePath path="C:\altera\11.0\quartus\bin\cygwin\lib\gcc\i686-pc-cygwin\3.4.4\include\c++\backward"/>
@@ -95,10 +104,20 @@
<definedSymbol symbol="unix=1"/>
<definedSymbol symbol="__unix__=1"/>
<definedSymbol symbol="__unix=1"/>
<definedSymbol symbol="SYSTEM_BUS_WIDTH=32"/>
<definedSymbol symbol="__hal__=1"/>
<definedSymbol symbol="ALT_NO_INSTRUCTION_EMULATION=1"/>
<definedSymbol symbol="ALT_SINGLE_THREADED=1"/>
</collector>
</instance>
<instance id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1624212479;preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1624212479.;cdt.managedbuild.tool.gnu.c.compiler.cygwin.base.1416994968;cdt.managedbuild.tool.gnu.c.compiler.input.cygwin.1042756107">
<collector id="org.eclipse.cdt.make.core.PerProjectSICollector">
<includePath path="C:/our_shit/ECE5760Projects/legit_start/verilog/software/legit_BSP/HAL/inc"/>
<includePath path="C:/our_shit/ECE5760Projects/legit_start/verilog/software/legit_BSP/"/>
<includePath path="C:/our_shit/ECE5760Projects/legit_start/verilog/software/legit_BSP/drivers/inc"/>
<includePath path="c:\altera\11.0\quartus\bin\cygwin\lib\gcc\i686-pc-cygwin\3.4.4\include"/>
<includePath path="c:\altera\11.0\quartus\bin\cygwin\usr\include"/>
<includePath path="c:\altera\11.0\quartus\bin\cygwin\usr\include\w32api"/>
<includePath path="C:\altera\11.0\quartus\bin\cygwin\lib\gcc\i686-pc-cygwin\3.4.4\include"/>
<includePath path="C:\altera\11.0\quartus\bin\cygwin\usr\include"/>
<includePath path="C:\altera\11.0\quartus\bin\cygwin\usr\include\w32api"/>
@@ -181,6 +200,10 @@
<definedSymbol symbol="unix=1"/>
<definedSymbol symbol="__unix__=1"/>
<definedSymbol symbol="__unix=1"/>
<definedSymbol symbol="SYSTEM_BUS_WIDTH=32"/>
<definedSymbol symbol="__hal__=1"/>
<definedSymbol symbol="ALT_NO_INSTRUCTION_EMULATION=1"/>
<definedSymbol symbol="ALT_SINGLE_THREADED=1"/>
</collector>
</instance>
</scannerInfo>
18 legit_start/verilog/software/.metadata/.plugins/org.eclipse.cdt.ui/legit_app.build.log
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@@ -5,4 +5,22 @@ make all
Info: Building ../legit_BSP/
make --no-print-directory -C ../legit_BSP/
[BSP build complete]
Info: Compiling drawing.c to obj/drawing.o
nios2-elf-gcc -xc -MP -MMD -c -I../legit_BSP//HAL/inc -I../legit_BSP/ -I../legit_BSP//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -EL -mno-hw-div -mno-hw-mul -mno-hw-mulx -o obj/drawing.o drawing.c
drawing.c:34: warning: built-in function 'y1' declared as non-function
drawing.c:60: warning: conflicting types for built-in function 'cos'
drawing.c:90: warning: conflicting types for built-in function 'sin'
drawing.c: In function 'crash':
drawing.c:208: warning: implicit declaration of function 'usleep'
Info: Compiling main.c to obj/main.o
nios2-elf-gcc -xc -MP -MMD -c -I../legit_BSP//HAL/inc -I../legit_BSP/ -I../legit_BSP//drivers/inc -DSYSTEM_BUS_WIDTH=32 -pipe -D__hal__ -DALT_NO_INSTRUCTION_EMULATION -DALT_SINGLE_THREADED -O0 -g -Wall -EL -mno-hw-div -mno-hw-mul -mno-hw-mulx -o obj/main.o main.c
main.c: In function 'main':
main.c:22: warning: implicit declaration of function 'draw_lander'
Info: Linking legit_app.elf
nios2-elf-g++ -T'../legit_BSP//linker.x' -msys-crt0='../legit_BSP//obj/HAL/src/crt0.o' -msys-lib=hal_bsp -L../legit_BSP/ -Wl,-Map=legit_app.map -O0 -g -Wall -EL -mno-hw-div -mno-hw-mul -mno-hw-mulx -o legit_app.elf obj/drawing.o obj/interrupts.o obj/main.o -lm
nios2-elf-insert legit_app.elf --thread_model hal --cpu_name CPU --simulation_enabled false --stderr_dev jtag_uart_0 --stdin_dev jtag_uart_0 --stdout_dev jtag_uart_0 --sopc_system_name Video_System --jdi C:/our_shit/ECE5760Projects/legit_start/verilog/software/legit_BSP/../../Example_4_Video_In.jdi
Info: (legit_app.elf) 65 KBytes program size (code + initialized data).
Info: 318 KBytes free for stack + heap.
Info: Creating legit_app.objdump
nios2-elf-objdump --disassemble --syms --all-header legit_app.elf >legit_app.objdump
[legit_app build complete]
BIN +233 Bytes (260%) ...etadata/.plugins/org.eclipse.core.resources/.projects/legit_BSP/.indexes/properties.index
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BIN -18.5 KB legit_start/verilog/software/.metadata/.plugins/org.eclipse.core.resources/.root/1.tree
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5 ...ata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.managedbuilder.core.prefs
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@@ -1,3 +1,4 @@
#Wed Feb 25 12:06:24 EST 2015
#Thu Feb 26 20:48:33 EST 2015
properties/legit_BSP.null.1837984912/preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1802798897=\#\r\n\#Thu Feb 26 20\:35\:23 EST 2015\r\naltera.nios2.mingw.gcc4.1515632751\=\\\#\\r\\n\\\#Thu Feb 26 20\\\:35\\\:23 EST 2015\\r\\nrebuildState\\\=false\\r\\n\r\ncdt.managedbuild.tool.gnu.assembler.cygwin.base.1725173184\=\\\#\\r\\n\\\#Thu Feb 26 20\\\:35\\\:23 EST 2015\\r\\nrebuildState\\\=false\\r\\n\r\ncdt.managedbuild.tool.gnu.c.linker.cygwin.base.330344452\=\\\#\\r\\n\\\#Thu Feb 26 20\\\:35\\\:23 EST 2015\\r\\nrebuildState\\\=false\\r\\n\r\npreference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1802798897\=\\\#\\r\\n\\\#Thu Feb 26 20\\\:35\\\:23 EST 2015\\r\\nrcState\\\=0\\r\\nrebuildState\\\=false\\r\\n\r\ncdt.managedbuild.tool.gnu.cpp.compiler.cygwin.base.925092005\=\\\#\\r\\n\\\#Thu Feb 26 20\\\:35\\\:23 EST 2015\\r\\nrebuildState\\\=false\\r\\n\r\ncdt.managedbuild.tool.gnu.c.compiler.cygwin.base.1478134130\=\\\#\\r\\n\\\#Thu Feb 26 20\\\:35\\\:23 EST 2015\\r\\nrebuildState\\\=false\\r\\n\r\ncdt.managedbuild.tool.gnu.cpp.linker.cygwin.base.720858314\=\\\#\\r\\n\\\#Thu Feb 26 20\\\:35\\\:23 EST 2015\\r\\nrebuildState\\\=false\\r\\n\r\ncdt.managedbuild.tool.gnu.archiver.cygwin.base.1666610805\=\\\#\\r\\n\\\#Thu Feb 26 20\\\:35\\\:23 EST 2015\\r\\nrebuildState\\\=false\\r\\n\r\n
eclipse.preferences.version=1
properties/legit_app.null.989035460/preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1624212479=\#\r\n\#Wed Feb 25 12\:06\:24 EST 2015\r\naltera.nios2.mingw.gcc4.260122017\=\\\#\\r\\n\\\#Wed Feb 25 12\\\:06\\\:24 EST 2015\\r\\nrebuildState\\\=false\\r\\n\r\ncdt.managedbuild.tool.gnu.cpp.compiler.cygwin.base.1147992395\=\\\#\\r\\n\\\#Wed Feb 25 12\\\:06\\\:24 EST 2015\\r\\nrebuildState\\\=false\\r\\n\r\ncdt.managedbuild.tool.gnu.assembler.cygwin.base.1227490617\=\\\#\\r\\n\\\#Wed Feb 25 12\\\:06\\\:24 EST 2015\\r\\nrebuildState\\\=false\\r\\n\r\npreference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1624212479\=\\\#\\r\\n\\\#Wed Feb 25 12\\\:06\\\:24 EST 2015\\r\\nrcState\\\=0\\r\\nrebuildState\\\=false\\r\\n\r\ncdt.managedbuild.tool.gnu.c.linker.cygwin.base.599782071\=\\\#\\r\\n\\\#Wed Feb 25 12\\\:06\\\:24 EST 2015\\r\\nrebuildState\\\=false\\r\\n\r\ncdt.managedbuild.tool.gnu.cpp.linker.cygwin.base.480856787\=\\\#\\r\\n\\\#Wed Feb 25 12\\\:06\\\:24 EST 2015\\r\\nrebuildState\\\=false\\r\\n\r\ncdt.managedbuild.tool.gnu.archiver.cygwin.base.130987963\=\\\#\\r\\n\\\#Wed Feb 25 12\\\:06\\\:24 EST 2015\\r\\nrebuildState\\\=false\\r\\n\r\ncdt.managedbuild.tool.gnu.c.compiler.cygwin.base.1416994968\=\\\#\\r\\n\\\#Wed Feb 25 12\\\:06\\\:24 EST 2015\\r\\nrebuildState\\\=false\\r\\n\r\n
properties/legit_app.null.989035460/preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1624212479=\#\r\n\#Thu Feb 26 20\:48\:33 EST 2015\r\naltera.nios2.mingw.gcc4.260122017\=\\\#\\r\\n\\\#Thu Feb 26 20\\\:48\\\:33 EST 2015\\r\\nrebuildState\\\=false\\r\\n\r\ncdt.managedbuild.tool.gnu.cpp.compiler.cygwin.base.1147992395\=\\\#\\r\\n\\\#Thu Feb 26 20\\\:48\\\:33 EST 2015\\r\\nrebuildState\\\=false\\r\\n\r\ncdt.managedbuild.tool.gnu.assembler.cygwin.base.1227490617\=\\\#\\r\\n\\\#Thu Feb 26 20\\\:48\\\:33 EST 2015\\r\\nrebuildState\\\=false\\r\\n\r\npreference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1624212479\=\\\#\\r\\n\\\#Thu Feb 26 20\\\:35\\\:01 EST 2015\\r\\nrcState\\\=0\\r\\nrebuildState\\\=false\\r\\n\r\ncdt.managedbuild.tool.gnu.c.linker.cygwin.base.599782071\=\\\#\\r\\n\\\#Thu Feb 26 20\\\:48\\\:33 EST 2015\\r\\nrebuildState\\\=false\\r\\n\r\ncdt.managedbuild.tool.gnu.cpp.linker.cygwin.base.480856787\=\\\#\\r\\n\\\#Thu Feb 26 20\\\:48\\\:33 EST 2015\\r\\nrebuildState\\\=false\\r\\n\r\ncdt.managedbuild.tool.gnu.archiver.cygwin.base.130987963\=\\\#\\r\\n\\\#Thu Feb 26 20\\\:48\\\:33 EST 2015\\r\\nrebuildState\\\=false\\r\\n\r\ncdt.managedbuild.tool.gnu.c.compiler.cygwin.base.1416994968\=\\\#\\r\\n\\\#Thu Feb 26 20\\\:48\\\:33 EST 2015\\r\\nrebuildState\\\=false\\r\\n\r\n
4 ...g/software/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.ide.prefs
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@@ -1,6 +1,6 @@
#Wed Feb 25 12:07:25 EST 2015
#Thu Feb 26 20:34:20 EST 2015
eclipse.preferences.version=1
tipsAndTricks=true
platformState=1424883200366
platformState=1424992769509
quickStart=false
PROBLEMS_FILTERS_MIGRATE=true
8 legit_start/verilog/software/.metadata/.plugins/org.eclipse.debug.ui/dialog_settings.xml
View file
@@ -1,5 +1,13 @@
<?xml version="1.0" encoding="UTF-8"?>
<section name="Workbench">
<section name="org.eclipse.debug.ui.LAUNCH_CONFIGURATIONS_DIALOG_SECTION">
<item value="800" key="DIALOG_WIDTH"/>
<item value=", com.altera.sbtgui.launch.hardware.Nios2HardwareLaunchConfiguration, " key="org.eclipse.debug.ui.EXPANDED_NODES"/>
<item value="640" key="DIALOG_HEIGHT"/>
<item value="237" key="org.eclipse.debug.ui.DIALOG_SASH_WEIGHTS_1"/>
<item value="1|Segoe UI|9.0|0|WINDOWS|1|-12|0|0|0|400|0|0|0|1|0|0|0|0|Segoe UI" key="DIALOG_FONT_NAME"/>
<item value="762" key="org.eclipse.debug.ui.DIALOG_SASH_WEIGHTS_2"/>
</section>
<section name="org.eclipse.debug.ui.SELECT_LAUNCH_SHORTCUT_DIALOG">
<item value="270" key="DIALOG_WIDTH"/>
<item value="435" key="DIALOG_HEIGHT"/>