From 0852138341c9bb1b40df6cb064606604254c412d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= <joachim@secworks.se>
Date: Fri, 9 Feb 2018 19:54:36 +0100
Subject: [PATCH] Removed timescale directives. Fixed nits in the makefile.

---
 src/tb/tb_siphash.v      |  5 -----
 src/tb/tb_siphash_core.v |  5 -----
 toolruns/Makefile        | 29 ++++++++++++++++++++---------
 3 files changed, 20 insertions(+), 19 deletions(-)

diff --git a/src/tb/tb_siphash.v b/src/tb/tb_siphash.v
index bec4239..5592442 100644
--- a/src/tb/tb_siphash.v
+++ b/src/tb/tb_siphash.v
@@ -35,11 +35,6 @@
 //
 //======================================================================
 
-//------------------------------------------------------------------
-// Compiler directives.
-//------------------------------------------------------------------
-`timescale 1ns/10ps
-
 module tb_siphash();
 
   //----------------------------------------------------------------
diff --git a/src/tb/tb_siphash_core.v b/src/tb/tb_siphash_core.v
index 4eba43d..5e5e325 100644
--- a/src/tb/tb_siphash_core.v
+++ b/src/tb/tb_siphash_core.v
@@ -35,11 +35,6 @@
 //
 //======================================================================
 
-//------------------------------------------------------------------
-// Compiler directives.
-//------------------------------------------------------------------
-`timescale 1ns/100ps
-
 module tb_siphash_core();
 
   //----------------------------------------------------------------
diff --git a/toolruns/Makefile b/toolruns/Makefile
index 2d81497..40513a6 100644
--- a/toolruns/Makefile
+++ b/toolruns/Makefile
@@ -36,28 +36,39 @@
 #=======================================================================
 
 CORE_SRC = ../src/rtl/siphash_core.v
-TOP_SRC = ../src/rtl/siphash.v $(CORE_SRC)
+CORE_TB = ../src/tb/tb_siphash_core.v
 
+TOP_SRC = ../src/rtl/siphash.v $(CORE_SRC)
 TOP_TB = ../src/tb/tb_siphash.v
-CORE_TB = ../src/tb/tb_siphash_core.v
 
 CC = iverilog
+CC_FLAGS= -Wall
+
 LINT=verilator
+LINT_FLAGS = +1364-2001ext+ --lint-only -Wall -Wno-fatal -Wno-DECLFILENAME
+
+
+all: top.sim core.sim
+
+
+top.sim: $(TOP_TB_SRC) $(TOP_SRC)
+	$(CC) $(CC_FLAGS) -o top.sim $(TOP_TB_SRC) $(TOP_SRC)
 
 
-all:    top core
+core.sim: $(CORE_TB_SRC) $(CORE_SRC)
+	$(CC) $(CC_FLAGS) -o core.sim $(CORE_SRC) $(CORE_TB_SRC)
 
 
-top:	$(TOP_TB) $(TOP_SRC)
-	iverilog -Wall -o top.sim $(TOP_TB) $(TOP_SRC)
+sim-top: top.sim
+	./top.sim
 
 
-core:	$(CORE_TB) $(CORE_SRC)
-	iverilog -Wall -o core.sim $(CORE_TB) $(CORE_SRC)
+sim-core: core.sim
+	./core.sim
 
 
-lint:
-	verilator --lint-only -Wall $(TOP_SRC)
+lint: $(TOP_SRC)
+	$(LINT) $(LINT_FLAGS) $(TOP_SRC)
 
 
 clean: