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fiber-optic-uart
graphics-footprints Design first draft Oct 10, 2019
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README.md
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README.md

Fiber Optic UART

Have you ever thought, "you know, this basic serial link really needs to be more complicated?" Do you lie awake at night wondering whether you could communicate better if blinky lights were involved? Are you unsatisfied with the metallic aftertaste or disappointing mouthfeel from your cabling?

Well, my friend, look no further! This project contains the schematics for a simple and inexpensive fiber-optic transceiver usable for any serial communication link up to 50 megabaud! It is fairly robust to both data and power glitches and uses inexpensive POF (Plastic Optical Fiber) fiber-optic cables.

Front Back

Power and signaling

A variety of power supply and signal level options are available. These can be configured by the solder jumpers on the board.

3.3V signal level

As configured, the transceiver works with 3.3V signals. For this application, power can be provided from either a regulated 3.3V or unregulated 3.6–5.5V supply.

  • Regulated 3.3V input: Jumper Power to U and Unreg to 3. This disconnects the onboard regulator and powers the board off the +3.3V pin.
  • Unregulated 3.6V–5.5V input: Jumper Power to R. This powers the board off the onboard regulator, which is supplied from the +5V pin. The Unreg jumper is not used in this configuration.

Signal inversion

To increase the longevity of the transciever LEDs, they should be enabled as little as possible. Thus, the TX and RX signals can be individually inverted, allowing the transceivers to also act as inverters as needed.

  • For NRZ-type signaling, no inversion is needed: Jumper TX to N and RX to N.
  • For UART signals, the default bus state is a logic 1, so it is preferable to invert the waveform on the fiber: Jumper TX to I and RX to I.
  • To invert the received signal, jumper one of TX or RX to I and the other to N. Choose where to perform the inversion based on the desired fiber-optic waveform.

5V signal level

The chosen transcievers can support 5V logic signals as well. However, the specified TVS diodes will hold the data pins at or below 3.5V; for 5V signals, the diodes must either be removed or replaced with an appropriate alternative.

Power must be supplied from a regulated 5V power supply: Jumper Power to U and Unreg to 5. This disconnects the onboard regulator and powers the board from the +5V pin.

Keep in mind that 5V power will shorten the lifespan of the transciever LEDs as well.

Extra: 3.3V out

To tap the onboard regulated 3.3V power supply, jumper Power to both U and R and Unreg to 3. Do not use Unreg jumpered to 5. This will provide 3.3V on the +3.3V pin. The regulator should be able to supply about 50 mA to +3.3V in this configuration.

Please monitor the temperature of the regulator IC in this configuration.

Component notes

Transciever

The transciever is capable of transmitting digital signals from DC to 50 Mbaud. This is more that sufficient for 115200 bits/sec UART signaling. It should also be usable for low-speed digital control signals such as relay switching signals.

The transceivers use standard 2.2 mm POF fiber. They directly grab the fiber, so crimped-on terminals are not necessary. All that is necessary for terminating the fiber is basic polishing.

Power

The onboard regulator is an LDO selected for its high power supply rejection ratio (PSRR). This improves the transciever's resilience in harsh environemnts where clean power may not be assured. Generous filter capacitors are also used.

Revisions

Rev. 0

  • Initial revision
  • No revision mark; PCB lot no. 2782500A-Y1-15

Rev. 1

  • Improve silkscreen text legibility
  • Include CERN OHL license notice
  • Add test points for Vin and Vo
  • Uses same solder stencil as Rev. 0

Credits

This project developed by the SeNDeComp research group. Thanks to Ford Motor Company, Missouri S&T, and the US Department of Education for funding the research that motivated this project.

Trans-istor logo provided by C. Sparks.

License

Copyright Natasha Jarus 2019.

This documentation describes Open Hardware and is licensed under the CERN OHL v.1.2.

You may redistribute and modify this documentation under the terms of the CERN OHL v.1.2. This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN OHL v.1.2 for applicable conditions.

If you use this project and have any questions, comments, or modifications, let me know!

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