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Ethernet Initialization

Serge Vakulenko edited this page Apr 3, 2015 · 9 revisions

Ethernet Initialization Sequence

(From Microchip PIC32 Family Reference Manual, Section 35: Ethernet Controller)

To initialize the Ethernet Controller to receive and transmit Ethernet messages, perform these steps:

1. Ethernet Controller Initialization

a) Disable Ethernet interrupts in the EVIC register by clearing the Ethernet Controller IE bit, ETHIE (IEC1<28>).

b) Turn the Ethernet Controller off, and then clear the ON bit (ETHCON1<15>), the RXEN bit (ETHCON1<8>), and the TXRTS bit (ETHCON1<9>).

c) Abort the Wait activity by polling the ETHBUSY bit (ETHSTAT<7>).

d) Clear the Ethernet Interrupt Flag bit (ETHIF) in the Interrupts module (IFS1<28>).

e) Disable any Ethernet Controller interrupt generation by clearing the ETHIRQIE register.

f) Clear the TX and RX start addresses from the ETHTXST and ETHRXST registers.

2. MAC Initialization

a) Reset the MAC using the SOFTRESET bit (EMAC1CFG1<15>), or individually reset the modules by setting the Reset MCS/RX bit, RESETRMCS (EMAC1CFG1<11), the Reset RX Function bit, RESETRFUN (EMAC1CFG1<10>), the Reset MCS/TX bit, RESETTMCS (EMAC1CFG1<9>), and the Reset TX Function bit, RESETTFUN (EMAC1CFG1<8>).

b) Use the Configuration bit setting, FETHIO (DEVCFG3<25>), to detect the alternate or default I/O configuration. Refer to Section 32. “Configuration” (DS60001124) for more information.

c) Use the Configuration bit setting, FMIIEN (DEVCFG3<24>), to detect MII/RMII operation mode.

d) Initialize as digital, all of the pins used by the MAC PHY interface (generally, only those pins that have shared analog functionality need to be configured).

e) Initialize the MIIM interface:

  • If the RMII operation is selected, Reset the RMII module by using the RESETRMII bit (EMAC1SUPP<11>) and set proper speed in the SPEEDRMII bit (EMAC1SUPP<8>).

  • Issue an MIIM block reset, by setting and then clearing the Test Reset MII Management bit, RESETMGMT (EMAC1MCFG<15>).

  • Select a proper divider in the CLKSEL<3:0> bits (EMAC1MCFG<5:2>) for the MIIM PHY communication based on the system running clock frequency and the external PHY supported clock.

3. PHY Initialization

This depends on the actual external PHY used. All PHYs should implement the basic register set as specified in Table 22-6 of the “MII Management Register Set” in Clause 22 of the IEEE 802.3 Specification.

In addition to the basic register set, PHYs may provide an extended set of nine registers and capabilities that may be accessed and controlled through the MIIM interface. They provide a PHY specific identifier, control and monitoring for the auto-negotiation process, and so on. The IEEE 802.3 Specification provides room for 16 extended registers which implement vendor-specific capabilities.

Following are the common steps for PHY initialization. Adjust these steps according to the vendor specific PHY data sheet:

a) Reset the PHY (use Control Register 0).

b) Set the MII/RMII operation mode. This requires access to a vendor-specific control register.

c) Set the normal, swapped, or automatic (preferred) MDIX. This requires access to a vendor-specific control register.

d) Check the PHY capabilities by investigating the Status Register 1.

e) The automatic negotiation should be enabled (preferably), if the PHY supports it. Advertise the supported capabilities using the PHY Register 4 “Auto-negotiation Advertisement Register”. Start the negotiation (Control Register 0) and wait for the negotiation to complete. Once the negotiation is complete, get the link partner capabilities from the PHY Register 5 “Auto-negotiation Link Partner Ability Register” and negotiation result from the vendor-specific register.

f) If automatic negotiation is not supported or selected, update the PHY Duplex and Speed settings directly (use Control Register 0 and possibly some vendor-specific registers).

4. MAC Configuration

When the Duplex and Speed settings are available, configure the MAC using these steps:

a) Enable the MAC Receive Enable bit, RXENABLE (EMAC1CFG1<0>), selecting both the MAC TX Flow Control bit, TXPAUSE (EMAC1CFG1<3>), and the MAC RX Flow Control bit, RXPAUSE (EMAC1CFG1<2>) (the PIC32 MAC supports both).

b) Select the desired automatic padding and CRC capabilities, enabling of the Huge frames, and the Duplex type in the EMAC1CFG2 register.

c) Program the EMAC1IPGT register with the back-to-back inter-packet gap.

d) Use the Ethernet Controller EMAC1IPGR register, for setting the non-back-to-back inter-packet gap.

e) Set the collision window and the maximum number of retransmissions in the EMAC1CLRT register.

f) Set the maximum frame length in the EMAC1MAXF register.

g) Optionally, set the station MAC address in the EMAC1SA0, EMAC1SA1, and EMAC1SA2 registers (these registers are loaded at Reset from the factory preprogrammed station address).

5. Continue the Ethernet Controller initialization

a) If you want to turn on the Flow Control, update the value of the PTV<15:0> bits (ETHCON1<31:16>).

b) If you want to use automatic Flow Control, set the full and empty watermarks: RXFWM<7:0> bits (ETHRXWM<23:16>) and the RXEWM<7:0> bits (ETHRXWM<7:0>).

c) If needed, enable the automatic Flow Control by setting the AUTOFC bit (ETHCON1<7>).

d) Set the RXFs by updating the ETHHT0, ETHHT1, ETHPMM0, ETHPMM1, ETHPMCS, and ETHRXFC registers.

e) Set the size of the RX buffers in the RXBUFSZ<6:0> bits (ETHCON2<10:4>) (all receive descriptors use the same buffer size). Note that using packets that are too small will lead to packet fragmentation, and has a noticeable impact on the performance.

f) Prepare a list/ring of TX descriptors for messages to be transmitted. Update all of the fields in the TX descriptor (NPV, EOWN = 1, NEXT_ED) (see Table 35-7). If using a list, end it with a software own descriptor (EOWN = 0). The SOP, EOP, DATA_BUFFER_ADDRESS and BYTE_COUNT will be updated when a specific message has to be transmitted. The DATA_BUFFER_ADDRESS will contain the physical address of the message, and the BYTE_COUNT contains the message size. SOP and EOP are set depending on how many packets are needed to transmit the message.

g) Prepare a list of the RX descriptors populated with valid buffers for messages to be received. Update the NEXT ED Pointer Valid (NPV) Enable bit, EOWN = 1 and DATA_BUFFER_ADDRESS fields in the RX descriptors (see Table 35-8). The DATA_BUFFER_ADDRESS should contain the physical address of the corresponding RX buffer.

h) The actual number of RX/TX descriptors and the previously allocated RX buffers depends on the available system memory, and the anticipated Ethernet traffic.

i) Update the ETHTXST register with the physical address of the Head of the TX descriptors list.

j) Update the ETHRXST register with the physical address of the Head of the RX descriptors list.

k) Enable the Ethernet Controller by setting the ON bit (ETHCON1<15>).

l) Enable the receiving of messages by setting the RXEN bit (ETHCON1<8>).

m) Check the list of RX descriptors to determine whether the EOWN bit is clear. If the EOWN bit is clear, this descriptor is under software control and an Ethernet message is received. Use SOP and EOP to extract the Ethernet message, and use the BYTE_COUNT, RXF_RSV, RSV and PKT_CHECKSUM to get the Ethernet message characteristics.

n) To transmit an Ethernet message:

  • Ensure that the message has the proper format according the Ethernet Frame specifications.

  • Update the necessary number of TX descriptors, starting with the Head of the list, by setting the DATA_BUFFER_ADDRESS as the physical address of the corresponding buffer in the message to be transmitted.

  • Note that large packet fragmentation has an impact on the performance.

  • Update the BYTE_COUNT value for each descriptor with the number of bytes contained in each buffer.

  • Set EOWN = 1 for each descriptor that belongs to the packet.

  • Use SOP and EOP to specify that the message uses one or more TX descriptors.

o) To enable the transmission of the message, set the TXRTS bit (ETHCON1<9>).

p) Inspect the list of TX descriptors to check if the EOWN bit is cleared. If it is cleared, this descriptor is under software control and the message is transmitted. Use TSV to check the transmission result.