{"payload":{"header_redesign_enabled":false,"results":[{"id":"213605319","archived":false,"color":"#adb2cb","followers":12,"has_funding_file":false,"hl_name":"shinde-shantanu/FPGA_TDC","hl_trunc_description":"Time to Digital Converter on an FPGA","language":"VHDL","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":213605319,"name":"FPGA_TDC","owner_id":48611375,"owner_login":"shinde-shantanu","updated_at":"2020-10-08T10:59:52.836Z","has_issues":true}},"sponsorable":false,"topics":["fpga","verilog","xilinx-vivado","nexys4ddr"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":60,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Ashinde-shantanu%252FFPGA_TDC%2B%2Blanguage%253AVHDL","metadata":null,"csrf_tokens":{"/shinde-shantanu/FPGA_TDC/star":{"post":"EyKmIUJPfXB9T-dIYFGI9PJHZwv1k_NVgj4HVb1t3wWyLVGC0XNlmwePUITFxlgTUNmudd19g_c2K8Y1bBSA1w"},"/shinde-shantanu/FPGA_TDC/unstar":{"post":"eIZvZeF2p-1cSs6JADF53J5mVS6cIVGzPCWZO46Bn92XzZEkhZWko0Y0Fzo13Vj916wBVDOtF5RNerTZuFY2_A"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"UoXANLSlTdg_MAP_HcyA74l5Ywrle0c8gMNZlsp6qUsmbpS-eM1ljpqzhq3sa1NHw2dmXn2RbicNtf5aWxE4dw"}}},"title":"Repository search results"}