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Implement 24bit load/store

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shinh committed Mar 14, 2016
1 parent 097c691 commit edbf034d7989b7602151a795d72a33f66eede4ec
Showing with 35 additions and 1 deletion.
  1. +34 −0 bfcore.rb
  2. +1 −1 common.rb
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@@ -41,6 +41,15 @@ def gen_mem_load
g.move_ptr(MEM)
g.set_ptr(0)
if $bfs24
g.decloop(MEM_A-1) {
g.move_word(MEM_A, MEM_A + MEM_BLK_LEN*256)
g.move_ptr(MEM_A + MEM_BLK_LEN*256)
g.set_ptr(MEM_A)
g.add(MEM_USE+1, 1)
}
end
g.decloop(MEM_A) {
g.move_word(MEM_A, MEM_A + MEM_BLK_LEN)
g.move_ptr(MEM_A + MEM_BLK_LEN)
@@ -56,12 +65,21 @@ def gen_mem_load
g.add(MEM_A + 1, -1)
}
g.clear(MEM_A + 1)
g.decloop(MEM_USE) {
g.move_word(MEM_V, MEM_V - MEM_BLK_LEN)
g.move_ptr(MEM_V - MEM_BLK_LEN)
g.set_ptr(MEM_V)
}
if $bfs24
g.decloop(MEM_USE+1) {
g.move_word(MEM_V, MEM_V - MEM_BLK_LEN*256)
g.move_ptr(MEM_V - MEM_BLK_LEN*256)
g.set_ptr(MEM_V)
}
end
g.move_ptr(0)
g.set_ptr(MEM)
g.clear_word(A)
@@ -77,6 +95,16 @@ def gen_mem_store
g.move_ptr(MEM)
g.set_ptr(0)
if $bfs24
g.decloop(MEM_A-1) {
g.move_word(MEM_V, MEM_V + MEM_BLK_LEN*256)
g.move_word(MEM_A, MEM_A + MEM_BLK_LEN*256)
g.move_ptr(MEM_A + MEM_BLK_LEN*256)
g.set_ptr(MEM_A)
g.add(MEM_USE+1, 1)
}
end
g.decloop(MEM_A) {
g.move_word(MEM_V, MEM_V + MEM_BLK_LEN)
g.move_word(MEM_A, MEM_A + MEM_BLK_LEN)
@@ -95,9 +123,15 @@ def gen_mem_store
g.add(MEM_A + 1, -1)
}
g.clear(MEM_A + 1)
g.move_ptr(MEM_USE)
g.emit '[-' + '<' * MEM_BLK_LEN + ']'
if $bfs24
g.move_ptr(MEM_USE+1)
g.emit '[-' + '<' * (MEM_BLK_LEN*256) + ']'
end
g.move_ptr(0)
g.set_ptr(MEM)
}
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@@ -44,7 +44,7 @@
MEM_A = 3
MEM_WRK = 6
MEM_USE = 12
MEM_CTL_LEN = 13
MEM_CTL_LEN = 15
MEM_BLK_LEN = (256*3) + MEM_CTL_LEN
else
MEM_A = 2

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