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Shinpei Kato authored
1 /*
2 * Copyright 2011 Shinpei Kato
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #ifndef __GDEV_NVIDIA_DEF_H__
26 #define __GDEV_NVIDIA_DEF_H__
27
28 #ifdef __KERNEL__
29 #include <linux/types.h>
30 #else
31 #include <stdint.h>
32 #endif
33
34 /**
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35 * static numbers for nvidia GPUs.
36 */
37 #define GDEV_NVIDIA_CONST_SEGMENT_MAX_COUNT 16 /* by definition? */
38
39 /**
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40 * query values for the device-specific information
41 */
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42 #define GDEV_NVIDIA_QUERY_MP_COUNT 100
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43
44 /**
45 * GPGPU kernel object struct:
46 * we use the same kernel struct between user-space and kernel-space.
47 *
48 * if you want to know how NVIDIA GPGPU kernels work, please reference
49 * the NVIDIA docs and/or the PSCNV wiki available at:
50 * https://github.com/pathscale/pscnv/wiki/Nvidia_Compute
51 */
52 struct gdev_kernel {
53 uint64_t code_addr; /* code address in VAS */
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54 uint32_t code_size; /* code size */
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55 uint32_t code_pc; /* initial program counter */
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56 struct gdev_cmem {
57 uint64_t addr; /* constant memory address in VAS */
58 uint32_t size; /* constant memory size */
59 uint32_t offset; /* offset in constant memory */
60 uint32_t *buf; /* data buffer */
61 } cmem[GDEV_NVIDIA_CONST_SEGMENT_MAX_COUNT];
62 uint32_t cmem_param_segment; /* constant memory segment for parameters */
63 uint32_t cmem_count; /* constant memory count */
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64 uint64_t lmem_addr; /* local memory address in VAS */
65 uint64_t lmem_size_total; /* local memory size for all threads */
66 uint32_t lmem_size; /* local memory size per thread (l[positive]) */
67 uint32_t lmem_size_neg; /* local memory size per thread (l[negaive]) */
68 uint32_t lmem_base; /* $lbase */
69 uint32_t smem_size; /* shared memory size */
70 uint32_t smem_base; /* $sbase */
71 uint32_t stack_level; /* stack level */
72 uint32_t warp_size; /* warp size */
73 uint32_t reg_count; /* register count */
74 uint32_t bar_count; /* barrier count */
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75 uint32_t call_limit; /* call limit log */
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76 uint32_t grid_id; /* grid ID */
77 uint32_t grid_x; /* grid dimension X */
78 uint32_t grid_y; /* grid dimension Y */
79 uint32_t grid_z; /* grid dimension Z */
80 uint32_t block_x; /* block dimension X */
81 uint32_t block_y; /* block dimension Y */
82 uint32_t block_z; /* block dimension Z */
83 };
84
85 #endif
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