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shivampotdar/README.md

Hi there πŸ‘‹

I am Shivam Potdar!

and I have a website πŸ˜„

Pinned

  1. stevehoover/warp-v stevehoover/warp-v Public

    WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.

    TL-Verilog 225 56

  2. PrincetonUniversity/openpiton PrincetonUniversity/openpiton Public

    The OpenPiton Platform

    Assembly 600 212

  3. warp-v warp-v Public

    Forked from stevehoover/warp-v

    WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.

    Verilog

  4. eyantra/gas-sensor-interfacing eyantra/gas-sensor-interfacing Public

    Interface gas sensor module with the Firebird robot

    C 1 1

  5. eyantra/bluetooth-interfacing eyantra/bluetooth-interfacing Public

    Interfacing Bluetooth module HC-05 with Firebird Robot

    Makefile 1

  6. tlv_flow_lib tlv_flow_lib Public

    Forked from TL-X-org/tlv_flow_lib

    Generic transaction flow components (like FIFOs, arbitors, and stall pipelines) for Transaction-Level Verilog

    M4