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I am Shivam Potdar!
and I have a website 😄
WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
The OpenPiton Platform
Forked from stevehoover/warp-v
Interface gas sensor module with the Firebird robot
Interfacing Bluetooth module HC-05 with Firebird Robot
Forked from stevehoover/tlv_flow_lib
Generic transaction flow components (like FIFOs, arbitors, and stall pipelines) for Transaction-Level Verilog
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