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shivampotdar/README.md

Hi there 👋

I am Shivam Potdar!

and I have a website 😄

Pinned

  1. WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.

    JavaScript 123 29

  2. The OpenPiton Platform

    Assembly 300 104

  3. Forked from stevehoover/warp-v

    WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.

    Verilog

  4. Interface gas sensor module with the Firebird robot

    C 1 2

  5. Interfacing Bluetooth module HC-05 with Firebird Robot

    Makefile 1

  6. Forked from stevehoover/tlv_flow_lib

    Generic transaction flow components (like FIFOs, arbitors, and stall pipelines) for Transaction-Level Verilog

    M4

593 contributions in the last year

May Jun Jul Aug Sep Oct Nov Dec Jan Feb Mar Apr Mon Wed Fri

Contribution activity

May 2021

shivampotdar has no activity yet for this period.

April 2021

Created 1 commit in 1 repository
21 contributions in private repositories Apr 3 – Apr 8

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