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shivampotdar/README.md

Hi there 👋

I am Shivam Potdar!

and I have a website 😄

Pinned

  1. WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.

    JavaScript 164 37

  2. The OpenPiton Platform

    Assembly 319 114

  3. Forked from stevehoover/warp-v

    WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.

    Verilog

  4. Interface gas sensor module with the Firebird robot

    C 1 2

  5. Interfacing Bluetooth module HC-05 with Firebird Robot

    Makefile 1

  6. Forked from stevehoover/tlv_flow_lib

    Generic transaction flow components (like FIFOs, arbitors, and stall pipelines) for Transaction-Level Verilog

    M4

344 contributions in the last year

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Contribution activity

August 2021

shivampotdar has no activity yet for this period.

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