*  Generated for: PrimeSim
*  Design library name: sidhant_lib
*  Design cell name: Top_Module
*  Design view name: schematic


*Custom Compiler Version S-2021.09
*Thu Feb 24 08:08:17 2022


********************************************************************************
* Library          : sidhant_lib
* Cell             : D_ff
* View             : schematic
* View Search List : hspice hspiceD schematic spice veriloga
* View Stop List   : hspice hspiceD
********************************************************************************
.subckt d_ff din q qn clk resetn vdd vss
xm33 d net131 vdd vdd p105 w=0.1u l=0.03u nf=1 m=1
xm29 net131 resetn vdd vdd p105 w=0.1u l=0.03u nf=1 m=1
xm28 net131 din vdd vdd p105 w=0.1u l=0.03u nf=1 m=1
xm21 dn d vdd vdd p105 w=0.1u l=0.03u nf=1 m=1
xm7 qn q vdd vdd p105 w=0.1u l=0.03u nf=1 m=1
xm6 qn in2 vdd vdd p105 w=0.1u l=0.03u nf=1 m=1
xm5 in2 clk vdd vdd p105 w=0.1u l=0.03u nf=1 m=1
xm20 in2 dn vdd vdd p105 w=0.1u l=0.03u nf=1 m=1
xm3 q qn vdd vdd p105 w=0.1u l=0.03u nf=1 m=1
xm2 q in1 vdd vdd p105 w=0.1u l=0.03u nf=1 m=1
xm1 in1 clk vdd vdd p105 w=0.1u l=0.03u nf=1 m=1
xm0 in1 d net2 net2 p105 w=0.1u l=0.03u nf=1 m=1
xm32 d net131 vss vss n105 w=0.1u l=0.03u nf=1 m=1
xm31 net119 resetn vss vss n105 w=0.1u l=0.03u nf=1 m=1
xm30 net131 din net119 vss n105 w=0.1u l=0.03u nf=1 m=1
xm22 dn d vss vss n105 w=0.1u l=0.03u nf=1 m=1
xm16 net63 q vss vss n105 w=0.1u l=0.03u nf=1 m=1
xm15 qn in2 net63 net63 n105 w=0.1u l=0.03u nf=1 m=1
xm14 net55 clk vss vss n105 w=0.1u l=0.03u nf=1 m=1
xm13 in2 dn net55 net55 n105 w=0.1u l=0.03u nf=1 m=1
xm12 net47 qn vss vss n105 w=0.1u l=0.03u nf=1 m=1
xm11 q in1 net47 net47 n105 w=0.1u l=0.03u nf=1 m=1
xm10 net35 clk vss vss n105 w=0.1u l=0.03u nf=1 m=1
xm8 in1 d net35 net35 n105 w=0.1u l=0.03u nf=1 m=1
c27 qn vss c=10f
c26 q vss c=10f
c25 in2 vss c=10f
c24 in1 vss c=10f
c23 dn vss c=10f
.ends d_ff

********************************************************************************
* Library          : sidhant_lib
* Cell             : xnor_gate
* View             : schematic
* View Search List : hspice hspiceD schematic spice veriloga
* View Stop List   : hspice hspiceD
********************************************************************************
.subckt xnor_gate a b out vdd vss
xm6 bbar b vdd vdd p105 w=0.1u l=0.03u nf=1 m=1
xm5 abar a vdd vdd p105 w=0.1u l=0.03u nf=1 m=1
xm4 out net56 vdd vdd p105 w=0.1u l=0.03u nf=1 m=1
xm3 net56 abar net61 vdd p105 w=0.1u l=0.03u nf=1 m=1
xm2 net56 bbar net61 vdd p105 w=0.1u l=0.03u nf=1 m=1
xm1 net61 a vdd vdd p105 w=0.1u l=0.03u nf=1 m=1
xm0 net61 b vdd vdd p105 w=0.1u l=0.03u nf=1 m=1
xm13 out net56 vss vss n105 w=0.1u l=0.03u nf=1 m=1
xm12 net49 bbar vss vss n105 w=0.1u l=0.03u nf=1 m=1
xm11 net62 b net46 net46 n105 w=0.1u l=0.03u nf=1 m=1
xm10 net56 abar net49 vss n105 w=0.1u l=0.03u nf=1 m=1
xm9 net56 a net62 net46 n105 w=0.1u l=0.03u nf=1 m=1
xm8 bbar b vss vss n105 w=0.1u l=0.03u nf=1 m=1
xm7 abar a vss vss n105 w=0.1u l=0.03u nf=1 m=1
c17 abar vss c=10f
c16 bbar vss c=10f
c15 out vss c=10f
c14 net56 vss c=10f
.ends xnor_gate

********************************************************************************
* Library          : sidhant_lib
* Cell             : inverter
* View             : schematic
* View Search List : hspice hspiceD schematic spice veriloga
* View Stop List   : hspice hspiceD
********************************************************************************
.subckt inverter in op vdd vss
xm0 op in vdd vdd p105 w=0.1u l=0.03u nf=1 m=1
xm1 op in vss vss n105 w=0.1u l=0.03u nf=1 m=1
.ends inverter

********************************************************************************
* Library          : sidhant_lib
* Cell             : Top_Module
* View             : schematic
* View Search List : hspice hspiceD schematic spice veriloga
* View Stop List   : hspice hspiceD
********************************************************************************
xi1 rand0 rand1 randn1 clk1 resetn vdd vss d_ff
xi0 ddin rand0 randn0 clk resetn vdd vss d_ff
xi5 randn0 randn1 out1 vdd vss xnor_gate
xi4 out1 net42 dencryp vdd vss xnor_gate
xi3 clk datain net42 vdd vss xnor_gate
xi2 rand0 rand1 outin vss vdd xnor_gate
xi7 outin ddin vss vdd inverter









.option primesim_remove_probe_prefix = 0
.probe v(*) i(*) level=1

.temp 25



.option primesim_output=wdf


.option parhier = LOCAL






.end