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arm64: iommu: smmu-v3: Add data structure initialization and stage 2 …

…for SMMUv3

A System Memory Management Unit(SMMU) performs a task analogous to a
CPU's MMU, translating addresses for device requests from system I/O
devices before the requests are passed into the system interconnect.

Implement a driver for SMMU v3 that maps and unmaps memory for specified
stream ids.

The guest cells are assigned stream IDs in their configs and only those
assigned stream IDs can be used by the cells. There is no checking in
place to make sure two cells do not use the same stream IDs. This must
be taken care of when creating the cell configs.

This driver is implemented based on the following assumptions:
- Running on a Little endian 64 bit core compatible with ARM v8
- SMMU supporting only AARCH64 mode.
- SMMU AARCH 64 stage 2 translation configurations are compatible with
  ARMv8 VMSA. So re-using the translation tables of CPU for SMMU.

This driver is loosely based on the Linux kernel SMMU v3 driver.

Signed-off-by: Pratyush Yadav <>
Signed-off-by: Lokesh Vutla <>
[Jan: dropped comments about SMMU emulation - not present here,
      added iommu_count_units() check to arm_smmuv3_cell_exit]
Signed-off-by: Jan Kiszka <>
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Pratyush Yadav authored and jan-kiszka committed Aug 7, 2019
1 parent e194da3 commit 458f7d0a6bdf3fc66e94fe09ff5fb2ab3e2c6c5f
Showing with 1,129 additions and 1 deletion.
  1. +1 −1 hypervisor/arch/arm64/Kbuild
  2. +1,128 −0 hypervisor/arch/arm64/smmu-v3.c
@@ -20,4 +20,4 @@ always := lib.a
# irqchip (common-objs-y), <generic units>

lib-y := $(common-objs-y)
lib-y += entry.o setup.o control.o mmio.o paging.o caches.o traps.o
lib-y += entry.o setup.o control.o mmio.o paging.o caches.o traps.o smmu-v3.o

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