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Commits on Jan 26, 2016
  1. @jan-kiszka

    x86: Make debug UART port configurable via system config

    jan-kiszka committed
    We already allow to enable a VGA console via the system config, so let's
    make the UART port configurable this way as well: phys_start will hold
    the port, and flags must not have JAILHOUSE_MEM_IO set, in order to
    differentiate us from the memory-mapped VGA console. And by leaving
    phys_start at 0, we can even turn off the console now.
    
    Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
  2. @jan-kiszka

    core: Initialize system_config earlier

    jan-kiszka committed
    On x86, we want to make the debug UART configurable via the system
    config. That means we will need this pointer in arch_dbg_write_init
    already.
    
    Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
  3. @jan-kiszka

    config: Set .debug_console for x86 targets

    jan-kiszka committed
    We will make the debug console UART port configurable via the system
    config. Set the corresponding values, they will be ignored so far.
    
    Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
  4. @jan-kiszka

    x86: Pull usage check out of vga_write

    jan-kiszka committed
    This makes the code more regular.
    
    Account for the additional contributor at this chance.
    
    Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
  5. @jan-kiszka

    x86: Remove redundant typecast

    jan-kiszka committed
    debug_console_base is a void pointer.
    
    Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
  6. @jan-kiszka

    arm: Only filter out complete string from KBUILD_AFLAGS

    jan-kiszka committed
    Otherwise we remove those words separately, destroying any
    "-include header.h" addition made elsewhere.
    
    Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Commits on Jan 25, 2016
  1. @jan-kiszka

    core, driver: Pass rounded-up core size in hypervisor header

    jan-kiszka committed
    Hypervisor and root kernel may have different ideas about PAGE_SIZE.
    This will cause wrong hypervisor core size calculations as seen on arm64
    with 64K Linux PAGE_SIZE.
    
    Avoid this trap by moving the round-up into the hypervisor code, passing
    a ready-to-be-used size value in the header.
    
    Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Commits on Jan 23, 2016
  1. @jan-kiszka

    ci: Switch to Wily for packages too old in Trusty

    jan-kiszka committed
    Vivid is EOL soon, so move on now.
    
    Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Commits on Jan 22, 2016
  1. @jan-kiszka

    ci: Work around Travis Trusty issue #5326

    jan-kiszka committed
    Current Trusty beta leaves non-system installations of python in the
    PATH. Therefore, we fail to find the Mako package during build.
    
    Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Commits on Jan 21, 2016
  1. @jan-kiszka

    ci: Break the build properly if anything goes wrong

    jan-kiszka committed
    If the make failed, we didn't bail out properly so far, leaving false
    negatives of test builds behind.
    
    Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
  2. @jan-kiszka

    ci: Update build environment to kernel 4.4

    jan-kiszka committed
    The renovation will be needed when adding arm64 to CI.
    
    Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
  3. @jan-kiszka

    ci: Drop COVERITY_SCAN_TOKEN from Travis configuration

    jan-kiszka committed
    This is better managed via the Travis CI project settings.
    
    Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
  4. @jan-kiszka

    vga: Add support for VGA text buffer output on x86

    Daniel Sangorrin committed with jan-kiszka
    Hypervisor messages are useful for debugging and are
    typically handed out to the serial port. Unfortunately, x86
    computers often lack of a serial port. This patch allows
    hypervisor messages to be redirected to a screen by leveraging
    the traditional VGA text buffer mode.
    
    Signed-off-by: Daniel Sangorrin <daniel.sangorrin@toshiba.co.jp>
    [Jan: avoid row_line writeback in panic case, remove redundant braces]
    Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
  5. @jan-kiszka

    console: rename uart to console

    Daniel Sangorrin committed with jan-kiszka
    Jailhouse may support different console devices other than
    the UART. For that reason, we adopt a more generic name.
    
    Signed-off-by: Daniel Sangorrin <daniel.sangorrin@toshiba.co.jp>
    Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Commits on Jan 15, 2016
  1. @jan-kiszka

    configs: Update Banana Pi configs to make use of unaligned MMIO regions

    jan-kiszka committed
    Split up the MMIO page 0x1c20000 on the Alwinner A20 into CCU,
    interrupts controller, GPIOs and the timer. GPIOs are further broken up
    to allow assigning port H to the gic-demo cell, along with the CCU (to
    control the UART timing).
    
    Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
  2. @jan-kiszka

    core: Add support for sub-page MMIO regions

    jan-kiszka committed
    This allows to specify memory regions for MMIO accesses that do not
    start or end on page boundaries. Instead of mapping full pages into the
    cell, sub-page MMIO requires to intercept the page accesses, validate
    all parameters against the target memory region and then perform the
    access in hypervisor context, provided the validation was successful.
    
    As the access can now fail in hypervisor context, we need to be more
    picky: besides read/write permissions, alignment and access widths can
    be checked additionally. These attributes are specified via the
    JAILHOUSE_MEM_IO_* flags.
    
    Sub-page MMIO is surely not a fast path. It not only requires world
    switches between cell and hypervisor, the current implementation also
    uses dynamic mappings. This is easier to implement than a static mapping
    scheme, but surely not faster. We may revisit this design later on,
    ideally towards a 1:1 mapping scheme.
    
    Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
  3. @jan-kiszka

    core: Remove memory regions check

    jan-kiszka committed
    Most of the checks will be removed when adding sub-page memory region
    support. We rather need some offline validation outside the hypervisor
    eventually.
    
    Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
  4. @jan-kiszka

    core: Introduce and use mmio_perform_access

    jan-kiszka committed
    Generalize arm_mmio_perform_access to mmio_perform_access which can also
    be used on other architectures, including those with 64-bit MMIO
    support.
    
    Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
  5. @jan-kiszka

    arm: Remove useless warning from arm_mmio_perform_access

    jan-kiszka committed
    This functions is only called with size 1, 2 or 4. This is ensured by
    arch_handle_dabt, the only (indirect) caller, which generates the size
    accordingly (1 << sas) and filters out sizes > 4.
    
    Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
  6. @jan-kiszka

    core: Introduce and use for_each_mem_region

    jan-kiszka committed
    This iterator simplifies walking over memory regions in cell and system
    configs.
    
    Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
  7. @jan-kiszka

    x86: Add support for 32-bit displacement in mod 0

    jan-kiszka committed
    Easy enough to add: a 32-bit address displacement follows the ModR/M
    byte, and nothing else.
    
    Turned out to be useful while testing with a sub-page HPET memory
    region.
    
    Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Commits on Jan 12, 2016
  1. @jan-kiszka

    TODO: Update CAT-related item

    jan-kiszka committed
    CAT support is now available, but we should add CDP later on (no
    hardware available so far to test it).
    
    Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
  2. @jan-kiszka

    configs: Add cache region to x86 demo cells

    jan-kiszka committed
    Assuming we have more than 4 units of L3 cache on systems that support
    L3 partitioning, assign the first 2 units (e.g. 2 MB on a Xeon D 1540)
    to apic-demo, the 3rd to tiny-demo. Also the non-root Linux config gets
    the first 2 units (it cannot run in parallel to the other demos). All
    this is for testing the management logic and will later be used to
    benchmark the partitioning.
    
    Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
  3. @jan-kiszka

    x86: Introduce Cache Allocation Technology support for Intel CPUs

    jan-kiszka committed
    CAT is a CPU feature first added to Xeon D and certain Xeon E5 v3
    processors. It so far allows to specify access restrictions to the L3
    cache, including complete isolation between different entities.
    
    This adds CAT control to Jailhouse on a per-cell level. The user is free
    to specify a contiguous access mask for each cell, use that mask
    exclusively (typical case), share any overlaps with the root cell
    (JAILHOUSE_CACHE_ROOTSHARED), or simply use the root cell mask. If
    nothing else is specified, the root cell uses the full cache (until
    non-root cells shrink it).
    
    Due to the hardware-induced requirement to have a contiguous bitmask,
    shrinking the root mask on cell creation and extending it again on
    destruction is not trivial. Not at all.
    
    When creating a new cell, we may punch a hole into the root mask. In
    that case, we also remove the lower half from the roor mask and
    accumulate those bits in a "freed mask" for reuse once the hole closes
    again. And if we are unlucky, adding a cell empties the current root
    mask. Then we have to look into the freed mask and switch to it if it's
    non-empty.
    
    When restoring the root mask on cell destruction, we choose a simple
    algorithm that first collects all released bits in the freed mask, then
    try to merge that mask bit-wise with the current root cell mask. On
    success we restart the freed mask walk to ensure that all contiguous
    bits are merged.
    
    One may wonder why not reallocating masks completely dynamically and
    automatically on each reconfiguration, instead of requiring that
    explicit allocation via the config? The reason is that we do not want to
    invalidate cache allocations of those cells that are not involved in a
    reconfiguration.
    
    A lot of complication with this mechanism which looked so simple on
    first sight. Let's just hope that there is a noteworthy benefit in
    restricting CAT bitmasks in hardware this way.
    
    Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Commits on Jan 10, 2016
  1. @jan-kiszka

    core, tools: Introduce cache regions to the cell configuration

    jan-kiszka committed
    Allow to specify regions of caches so that the hypervisor can partition
    their usage accordingly whenever the hardware supports this.
    
    The specification of their start location and sizes depend on the
    architecture specific partitioning support. So far, only L3 cache types
    are definable, either as unified cached or further partitioned into code
    and data (to cater Intel's CAT and CDP). As with memory regions, caches
    are usually taken from the root cell on non-root cell creation, but they
    can also be declared as shared with the root cell.
    
    Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
  2. @jan-kiszka

    x86: vmx: Block write access to CAT MSRs

    jan-kiszka committed
    Make sure the cells cannot mess around with them, modifying the
    configuration the hypervisor chose.
    
    Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
  3. @jan-kiszka

    x86: Add sub-leaf selection parameter to cpuid_*

    jan-kiszka committed
    This allows to call cpuid also on specific sub-leaves. Will be used
    first for CAT.
    
    Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
  4. @jan-kiszka

    inmates: arm: Make LED blinking in gic-demo optional

    jan-kiszka committed
    This is both a test/demo case for command line parsing on ARM and a
    feature to control the LED signal in the gic-demo on Banana Pi. The
    green LED will now only blink if "blinking_led" is specified as inmate
    command line option.
    
    Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Commits on Jan 9, 2016
  1. @jan-kiszka

    inmates: x86: Add optional cache pollution to apic-demo

    jan-kiszka committed
    When "pollute_cache" is specified as command line parameter of the
    apic-demo, the demo will fill each cache line with a pattern in each
    measurement loop. Up to 512 KB of cache can be polluted this way.
    
    This allows to test L3 cache partitioning features of recent Intel CPUs:
    The cache pollution will dirty the L1 and L2 data caches so that the
    next loop iteration will access L3. If that cache is shared, latencies
    will rise as other cells use the cache as well.
    
    Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
  2. @jan-kiszka

    inmates: x86: Allow to bypass TSC and APIC timer calibration

    jan-kiszka committed
    Make use of the command line feature and introduce the "tsc_freq" and
    "apic_freq" parameters. When provided, these values are used directly
    instead of running calibrations against the PM timer.
    
    This is particularly useful when running micro-benchmarks that are
    sensitive to the inherent small variations of the calibrations.
    
    Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
  3. @jan-kiszka

    tools: jailhouse: Add support for string loading

    jan-kiszka committed
    Extend the "cell load" command by a variant where a string provided
    along with the command is loaded into the cell memory. This can be used
    together with the new command line feature to pass parameters to inmates
    that support this.
    
    Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Commits on Jan 8, 2016
  1. @jan-kiszka

    tools: Rewrap jailhouse help output

    jan-kiszka committed
    Avoid that we exceed 80 characters.
    
    Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
  2. @jan-kiszka

    inmates: Add support for command line parameters

    jan-kiszka committed
    This provides support for parsing string, integer (long long type) and
    boolean command line parameters. The former two need to be in the form
    of "name=value" so that cmdline_parse_str/int will return the extracted
    value. Boolean parameters are just of the form "name", and
    cmdline_parse_bool will return true if this pattern is found. Parameters
    need to be separated by blanks.
    
    The parameters can be passed to the inmate by loading the string at an
    architecture-specific location. That is 0xf0000 on x86 and 0x100 on ARM
    so far. Note that the inmate has to reserve an appropriately sized
    buffer via the CMDLINE_BUFFER macro.
    
    Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
  3. @jan-kiszka

    inmates: Add strlen and strncmp to library

    jan-kiszka committed
    Add simplistic but generic implementations of strlen and strncmp to the
    inmate library. Both will be used for the command line parser.
    
    Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
  4. @jan-kiszka

    inmates: Avoid jailhouse/types.h

    jan-kiszka committed
    Add missing bool to inmate_common.h and use inmate.h instead of pulling
    the hypervisor types header.
    
    Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
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