From 351a6de31945c6f6c6c1bccce84ccfddb00f8699 Mon Sep 17 00:00:00 2001 From: Benshan Mei Date: Mon, 1 Feb 2021 18:16:57 +0800 Subject: [PATCH 01/26] add support for vc709 in fpga-shells --- .../xilinxvc709mig/XilinxVC709MIG.scala | 176 ++++++ .../XilinxVC709MIGPeriphery.scala | 35 + .../xilinxvc709pciex1/XilinxVC709PCIeX1.scala | 76 +++ .../XilinxVC709PCIeX1Periphery.scala | 32 + .../vc709axi_to_pcie_x1.scala | 439 +++++++++++++ .../scala/ip/xilinx/vc709mig/vc709-ddr.pin | 36 ++ .../scala/ip/xilinx/vc709mig/vc709mig.scala | 330 ++++++++++ .../scala/ip/xilinx/vc709mig/vc709mig8g.scala | 598 ++++++++++++++++++ .../scala/shell/xilinx/VC709NewShell.scala | 359 +++++++++++ xilinx/vc709/constraints/vc709-master.xdc | 10 + xilinx/vc709/constraints/vc709mig4gb.ucf | 116 ++++ xilinx/vc709/constraints/vc709mig8gb-C0.ucf | 116 ++++ xilinx/vc709/constraints/vc709mig8gb-C1.ucf | 116 ++++ xilinx/vc709/constraints/vc709mig8gb.ucf | 116 ++++ xilinx/vc709/tcl/board.tcl | 4 + xilinx/vc709/tcl/clocks.tcl | 50 ++ xilinx/vc709/tcl/ios.tcl | 76 +++ xilinx/vc709/vsrc/vc709reset.v | 78 +++ 18 files changed, 2763 insertions(+) create mode 100644 src/main/scala/devices/xilinx/xilinxvc709mig/XilinxVC709MIG.scala create mode 100644 src/main/scala/devices/xilinx/xilinxvc709mig/XilinxVC709MIGPeriphery.scala create mode 100644 src/main/scala/devices/xilinx/xilinxvc709pciex1/XilinxVC709PCIeX1.scala create mode 100644 src/main/scala/devices/xilinx/xilinxvc709pciex1/XilinxVC709PCIeX1Periphery.scala create mode 100644 src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala create mode 100644 src/main/scala/ip/xilinx/vc709mig/vc709-ddr.pin create mode 100644 src/main/scala/ip/xilinx/vc709mig/vc709mig.scala create mode 100644 src/main/scala/ip/xilinx/vc709mig/vc709mig8g.scala create mode 100644 src/main/scala/shell/xilinx/VC709NewShell.scala create mode 100644 xilinx/vc709/constraints/vc709-master.xdc create mode 100644 xilinx/vc709/constraints/vc709mig4gb.ucf create mode 100644 xilinx/vc709/constraints/vc709mig8gb-C0.ucf create mode 100644 xilinx/vc709/constraints/vc709mig8gb-C1.ucf create mode 100644 xilinx/vc709/constraints/vc709mig8gb.ucf create mode 100644 xilinx/vc709/tcl/board.tcl create mode 100644 xilinx/vc709/tcl/clocks.tcl create mode 100644 xilinx/vc709/tcl/ios.tcl create mode 100644 xilinx/vc709/vsrc/vc709reset.v diff --git a/src/main/scala/devices/xilinx/xilinxvc709mig/XilinxVC709MIG.scala b/src/main/scala/devices/xilinx/xilinxvc709mig/XilinxVC709MIG.scala new file mode 100644 index 00000000..c6ac2166 --- /dev/null +++ b/src/main/scala/devices/xilinx/xilinxvc709mig/XilinxVC709MIG.scala @@ -0,0 +1,176 @@ +// See LICENSE for license details. +package sifive.fpgashells.devices.xilinx.xilinxvc709mig + +import Chisel._ +import chisel3.experimental.{Analog,attach} +import freechips.rocketchip.amba.axi4._ +import freechips.rocketchip.config.Parameters +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.interrupts._ +import sifive.fpgashells.ip.xilinx.vc709mig.{VC709MIGIOClocksReset, VC709MIGIODDR, vc709mig} + +case class XilinxVC709MIGParams( + address : Seq[AddressSet] +) + +class XilinxVC709MIGPads(depth : BigInt) extends VC709MIGIODDR(depth) { + def this(c : XilinxVC709MIGParams) { + this(AddressRange.fromSets(c.address).head.size) + } +} + +class XilinxVC709MIGIO(depth : BigInt) extends VC709MIGIODDR(depth) with VC709MIGIOClocksReset + +class XilinxVC709MIGIsland(c : XilinxVC709MIGParams, val crossing: ClockCrossingType = AsynchronousCrossing(8))(implicit p: Parameters) extends LazyModule with CrossesToOnlyOneClockDomain { + val ranges = AddressRange.fromSets(c.address) + require (ranges.size == 1, "DDR range must be contiguous") + val offset = ranges.head.base + val depth = ranges.head.size + require((depth<=0x200000000L),"vc709mig supports upto 8GB depth configuraton") + + val device = new MemoryDevice + val node = AXI4SlaveNode(Seq(AXI4SlavePortParameters( + slaves = Seq(AXI4SlaveParameters( + address = c.address, + resources = device.reg, + regionType = RegionType.UNCACHED, + executable = true, + supportsWrite = TransferSizes(1, 128), + supportsRead = TransferSizes(1, 128))), + beatBytes = 8))) + + lazy val module = new LazyRawModuleImp(this) { + val io = IO(new Bundle { + val port = new XilinxVC709MIGIO(depth) + }) + + childClock := io.port.ui_clk + childReset := io.port.ui_clk_sync_rst + + //MIG black box instantiation + val blackbox = Module(new vc709mig(depth)) + val (axi_async, _) = node.in(0) + + //pins to top level + + //inouts + //#[DDR3 SODIMM 0] + attach(io.port.ddr3_dq,blackbox.io.ddr3_dq) + attach(io.port.ddr3_dqs_n,blackbox.io.ddr3_dqs_n) + attach(io.port.ddr3_dqs_p,blackbox.io.ddr3_dqs_p) + + //outputs + //#[DDR3 SODIMM 0] + io.port.ddr3_addr := blackbox.io.ddr3_addr + io.port.ddr3_ba := blackbox.io.ddr3_ba + io.port.ddr3_ras_n := blackbox.io.ddr3_ras_n + io.port.ddr3_cas_n := blackbox.io.ddr3_cas_n + io.port.ddr3_we_n := blackbox.io.ddr3_we_n + io.port.ddr3_reset_n := blackbox.io.ddr3_reset_n + io.port.ddr3_ck_p := blackbox.io.ddr3_ck_p + io.port.ddr3_ck_n := blackbox.io.ddr3_ck_n + io.port.ddr3_cke := blackbox.io.ddr3_cke + io.port.ddr3_cs_n := blackbox.io.ddr3_cs_n + io.port.ddr3_dm := blackbox.io.ddr3_dm + io.port.ddr3_odt := blackbox.io.ddr3_odt + + //inputs + //NO_BUFFER clock + blackbox.io.sys_clk_i := io.port.sys_clk_i + + //#[DDR3 SODIMM 0] + io.port.ui_clk := blackbox.io.ui_clk + io.port.ui_clk_sync_rst := blackbox.io.ui_clk_sync_rst + io.port.mmcm_locked := blackbox.io.mmcm_locked + blackbox.io.aresetn := io.port.aresetn + blackbox.io.app_sr_req := Bool(false) + blackbox.io.app_ref_req := Bool(false) + blackbox.io.app_zq_req := Bool(false) + //app_sr_active := unconnected + //app_ref_ack := unconnected + //app_zq_ack := unconnected + + val awaddr = axi_async.aw.bits.addr - UInt(offset) + val araddr = axi_async.ar.bits.addr - UInt(offset) + + // [DDR3 SODIMM 0] + //slave AXI interface write address ports + blackbox.io.s_axi_awid := axi_async.aw.bits.id + blackbox.io.s_axi_awaddr := awaddr //truncated + blackbox.io.s_axi_awlen := axi_async.aw.bits.len + blackbox.io.s_axi_awsize := axi_async.aw.bits.size + blackbox.io.s_axi_awburst := axi_async.aw.bits.burst + blackbox.io.s_axi_awlock := axi_async.aw.bits.lock + blackbox.io.s_axi_awcache := UInt("b0011") + blackbox.io.s_axi_awprot := axi_async.aw.bits.prot + blackbox.io.s_axi_awqos := axi_async.aw.bits.qos + blackbox.io.s_axi_awvalid := axi_async.aw.valid + axi_async.aw.ready := blackbox.io.s_axi_awready + + //slave interface write data ports + blackbox.io.s_axi_wdata := axi_async.w.bits.data + blackbox.io.s_axi_wstrb := axi_async.w.bits.strb + blackbox.io.s_axi_wlast := axi_async.w.bits.last + blackbox.io.s_axi_wvalid := axi_async.w.valid + axi_async.w.ready := blackbox.io.s_axi_wready + + //slave interface write response + blackbox.io.s_axi_bready := axi_async.b.ready + axi_async.b.bits.id := blackbox.io.s_axi_bid + axi_async.b.bits.resp := blackbox.io.s_axi_bresp + axi_async.b.valid := blackbox.io.s_axi_bvalid + + //slave AXI interface read address ports + blackbox.io.s_axi_arid := axi_async.ar.bits.id + blackbox.io.s_axi_araddr := araddr // truncated + blackbox.io.s_axi_arlen := axi_async.ar.bits.len + blackbox.io.s_axi_arsize := axi_async.ar.bits.size + blackbox.io.s_axi_arburst := axi_async.ar.bits.burst + blackbox.io.s_axi_arlock := axi_async.ar.bits.lock + blackbox.io.s_axi_arcache := UInt("b0011") + blackbox.io.s_axi_arprot := axi_async.ar.bits.prot + blackbox.io.s_axi_arqos := axi_async.ar.bits.qos + blackbox.io.s_axi_arvalid := axi_async.ar.valid + + axi_async.ar.ready := blackbox.io.s_axi_arready + + //slace AXI interface read data ports + blackbox.io.s_axi_rready := axi_async.r.ready + axi_async.r.bits.id := blackbox.io.s_axi_rid + axi_async.r.bits.data := blackbox.io.s_axi_rdata + axi_async.r.bits.resp := blackbox.io.s_axi_rresp + axi_async.r.bits.last := blackbox.io.s_axi_rlast + axi_async.r.valid := blackbox.io.s_axi_rvalid + + //misc + io.port.init_calib_complete := blackbox.io.init_calib_complete + + blackbox.io.sys_rst :=io.port.sys_rst + //mig.device_temp :- unconnceted + } +} + +class XilinxVC709MIG(c : XilinxVC709MIGParams, crossing: ClockCrossingType = AsynchronousCrossing(8))(implicit p: Parameters) extends LazyModule { + val ranges = AddressRange.fromSets(c.address) + val depth = ranges.head.size + + val buffer = LazyModule(new TLBuffer) + val toaxi4 = LazyModule(new TLToAXI4(adapterName = Some("mem"), stripBits = 1)) + val indexer = LazyModule(new AXI4IdIndexer(idBits = 4)) + val deint = LazyModule(new AXI4Deinterleaver(p(CacheBlockBytes))) + val yank = LazyModule(new AXI4UserYanker) + val island = LazyModule(new XilinxVC709MIGIsland(c, crossing)) + + val node: TLInwardNode = + island.crossAXI4In(island.node) := yank.node := deint.node := indexer.node := toaxi4.node := buffer.node + + lazy val module = new LazyModuleImp(this) { + val io = IO(new Bundle { + val port = new XilinxVC709MIGIO(depth) + }) + + io.port <> island.module.io.port + } +} diff --git a/src/main/scala/devices/xilinx/xilinxvc709mig/XilinxVC709MIGPeriphery.scala b/src/main/scala/devices/xilinx/xilinxvc709mig/XilinxVC709MIGPeriphery.scala new file mode 100644 index 00000000..93f23ccd --- /dev/null +++ b/src/main/scala/devices/xilinx/xilinxvc709mig/XilinxVC709MIGPeriphery.scala @@ -0,0 +1,35 @@ +// See LICENSE for license details. +package sifive.fpgashells.devices.xilinx.xilinxvc709mig + +import Chisel._ +import freechips.rocketchip.config._ +import freechips.rocketchip.subsystem.BaseSubsystem +import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, AddressRange} + +case object MemoryXilinxDDRKey extends Field[XilinxVC709MIGParams] + +trait HasMemoryXilinxVC709MIG { this: BaseSubsystem => + val module: HasMemoryXilinxVC709MIGModuleImp + + val xilinxvc709mig = LazyModule(new XilinxVC709MIG(p(MemoryXilinxDDRKey))) + + xilinxvc709mig.node := mbus.toDRAMController(Some("xilinxvc709mig"))() +} + +trait HasMemoryXilinxVC709MIGBundle { + val xilinxvc709mig: XilinxVC709MIGIO + def connectXilinxVC709MIGToPads(pads: XilinxVC709MIGPads) { + pads <> xilinxvc709mig + } +} + +trait HasMemoryXilinxVC709MIGModuleImp extends LazyModuleImp + with HasMemoryXilinxVC709MIGBundle { + val outer: HasMemoryXilinxVC709MIG + val ranges = AddressRange.fromSets(p(MemoryXilinxDDRKey).address) + require (ranges.size == 1, "DDR range must be contiguous") + val depth = ranges.head.size + val xilinxvc709mig = IO(new XilinxVC709MIGIO(depth)) + + xilinxvc709mig <> outer.xilinxvc709mig.module.io.port +} diff --git a/src/main/scala/devices/xilinx/xilinxvc709pciex1/XilinxVC709PCIeX1.scala b/src/main/scala/devices/xilinx/xilinxvc709pciex1/XilinxVC709PCIeX1.scala new file mode 100644 index 00000000..1b45db02 --- /dev/null +++ b/src/main/scala/devices/xilinx/xilinxvc709pciex1/XilinxVC709PCIeX1.scala @@ -0,0 +1,76 @@ +// See LICENSE for license details. +package sifive.fpgashells.devices.xilinx.xilinxvc709pciex1 + +import Chisel._ +import freechips.rocketchip.amba.axi4._ +import freechips.rocketchip.config.Parameters +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.interrupts._ +import freechips.rocketchip.subsystem.{CrossesToOnlyOneClockDomain, CacheBlockBytes} +import sifive.fpgashells.ip.xilinx.vc709axi_to_pcie_x1.{VC709AXIToPCIeX1, VC709AXIToPCIeX1IOClocksReset, VC709AXIToPCIeX1IOSerial} +import sifive.fpgashells.ip.xilinx.ibufds_gte2.IBUFDS_GTE2 + +trait VC709AXIToPCIeRefClk extends Bundle{ + val REFCLK_rxp = Bool(INPUT) + val REFCLK_rxn = Bool(INPUT) +} + +class XilinxVC709PCIeX1Pads extends Bundle + with VC709AXIToPCIeX1IOSerial + with VC709AXIToPCIeRefClk + +class XilinxVC709PCIeX1IO extends Bundle + with VC709AXIToPCIeRefClk + with VC709AXIToPCIeX1IOSerial + with VC709AXIToPCIeX1IOClocksReset { + val axi_ctl_aresetn = Bool(INPUT) +} + +class XilinxVC709PCIeX1(implicit p: Parameters, val crossing: ClockCrossingType = AsynchronousCrossing(8)) + extends LazyModule with CrossesToOnlyOneClockDomain +{ + val axi_to_pcie_x1 = LazyModule(new VC709AXIToPCIeX1) + + val slave: TLInwardNode = + (axi_to_pcie_x1.slave + := AXI4Buffer() + := AXI4UserYanker() + := AXI4Deinterleaver(p(CacheBlockBytes)) + := AXI4IdIndexer(idBits=4) + := TLToAXI4(adapterName = Some("pcie-slave"))) + + val control: TLInwardNode = + (axi_to_pcie_x1.control + := AXI4Buffer() + := AXI4UserYanker(capMaxFlight = Some(2)) + := TLToAXI4() + := TLFragmenter(4, p(CacheBlockBytes), holdFirstDeny = true)) + + val master: TLOutwardNode = + (TLWidthWidget(8) + := AXI4ToTL() + := AXI4UserYanker(capMaxFlight=Some(8)) + := AXI4Fragmenter() + := axi_to_pcie_x1.master) + + val intnode: IntOutwardNode = axi_to_pcie_x1.intnode + + lazy val module = new LazyRawModuleImp(this) { + val io = IO(new Bundle { + val port = new XilinxVC709PCIeX1IO + }) + + childClock := io.port.axi_aclk // axi_aclk_out is changed to axi_aclk + childReset := ~io.port.axi_aresetn // + + io.port <> axi_to_pcie_x1.module.io.port + + //PCIe Reference Clock + val ibufds_gte2 = Module(new IBUFDS_GTE2) + axi_to_pcie_x1.module.io.refclk := ibufds_gte2.io.O // REFCLK is changed to refclk + ibufds_gte2.io.CEB := UInt(0) + ibufds_gte2.io.I := io.port.REFCLK_rxp + ibufds_gte2.io.IB := io.port.REFCLK_rxn + } +} diff --git a/src/main/scala/devices/xilinx/xilinxvc709pciex1/XilinxVC709PCIeX1Periphery.scala b/src/main/scala/devices/xilinx/xilinxvc709pciex1/XilinxVC709PCIeX1Periphery.scala new file mode 100644 index 00000000..85964770 --- /dev/null +++ b/src/main/scala/devices/xilinx/xilinxvc709pciex1/XilinxVC709PCIeX1Periphery.scala @@ -0,0 +1,32 @@ +// See LICENSE for license details. +package sifive.fpgashells.devices.xilinx.xilinxvc709pciex1 + +import Chisel._ +import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BufferParams} +import freechips.rocketchip.subsystem.BaseSubsystem +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.interrupts.IntSyncCrossingSink + +trait HasSystemXilinxVC709PCIeX1 { this: BaseSubsystem => + val xilinxvc709pcie = LazyModule(new XilinxVC709PCIeX1) + private val cname = "xilinxvc709pcie" + sbus.coupleFrom(s"master_named_$cname") { _ :=* TLFIFOFixer(TLFIFOFixer.all) :=* xilinxvc709pcie.crossTLOut(xilinxvc709pcie.master) } + sbus.coupleTo(s"slave_named_$cname") { xilinxvc709pcie.crossTLIn(xilinxvc709pcie.slave) :*= TLWidthWidget(sbus.beatBytes) :*= _ } + sbus.coupleTo(s"controller_named_$cname") { xilinxvc709pcie.crossTLIn(xilinxvc709pcie.control) :*= TLWidthWidget(sbus.beatBytes) :*= _ } + ibus.fromSync := xilinxvc709pcie.crossIntOut(xilinxvc709pcie.intnode) +} + +trait HasSystemXilinxVC709PCIeX1Bundle { + val xilinxvc709pcie: XilinxVC709PCIeX1IO + def connectXilinxVC709PCIeX1ToPads(pads: XilinxVC709PCIeX1Pads) { + pads <> xilinxvc709pcie + } +} + +trait HasSystemXilinxVC709PCIeX1ModuleImp extends LazyModuleImp + with HasSystemXilinxVC709PCIeX1Bundle { + val outer: HasSystemXilinxVC709PCIeX1 + val xilinxvc709pcie = IO(new XilinxVC709PCIeX1IO) + + xilinxvc709pcie <> outer.xilinxvc709pcie.module.io.port +} diff --git a/src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala b/src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala new file mode 100644 index 00000000..9839c344 --- /dev/null +++ b/src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala @@ -0,0 +1,439 @@ +// See LICENSE for license details. +package sifive.fpgashells.ip.xilinx.vc709axi_to_pcie_x1 + +import Chisel._ +import freechips.rocketchip.config._ +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.amba.axi4._ +import freechips.rocketchip.interrupts._ +import freechips.rocketchip.util.{ElaborationArtefacts} + +// IP VLNV: xilinx.com:customize_ip:vc709pcietoaxi:3.0 +// Black Box +// Signals named _exactly_ as per Vivado generated verilog +// s : -{lock, cache, prot, qos} + +trait VC709AXIToPCIeX1IOSerial extends Bundle { + //serial external pins + val pci_exp_txp = Bits(OUTPUT, 8) + val pci_exp_txn = Bits(OUTPUT, 8) + val pci_exp_rxp = Bits(INPUT, 8) + val pci_exp_rxn = Bits(INPUT, 8) +} + +trait VC709AXIToPCIeX1IOClocksReset extends Bundle { + //clock, reset, control + val axi_aresetn = Bool(INPUT) + val axi_aclk = Clock(OUTPUT) // axi_aclk_out is changed to axi_aclk in 3.0 +} + +//scalastyle:off +//turn off linter: blackbox name must match verilog module +class vc709axi_to_pcie_x1() extends BlackBox +{ + val io = new Bundle with VC709AXIToPCIeX1IOSerial + with VC709AXIToPCIeX1IOClocksReset { + //refclk + val refclk = Bool(INPUT) // REFCLK is changed in 3.0 + + //clock, reset, control + val intx_msi_request = Bool(INPUT) // INTX_MSI_Request is changed in 3.0 + val intx_msi_grant = Bool(OUTPUT) // INTX_MSI_Grant is changed in 3.0 + + val msi_enable = Bool(OUTPUT) // MSI_enable is changed in 3.0 + val msi_vector_num = Bits(INPUT, 5) // MSI_Vector_Num is changed in 3.0 + val msi_vector_width = Bits(OUTPUT,3) // MSI_Vector_Width is changed in 3.0 + + //interrupt + val interrupt_out = Bool(OUTPUT) + + //axi slave + //-{lock, cache, prot, qos} + //slave interface write address + val s_axi_awid = Bits(INPUT,4) + val s_axi_awaddr = Bits(INPUT,32) + val s_axi_awregion = Bits(INPUT,4) + val s_axi_awlen = Bits(INPUT,8) + val s_axi_awsize = Bits(INPUT,3) + val s_axi_awburst = Bits(INPUT,2) + //val s_axi_awlock = Bool(INPUT) + //val s_axi_awcache = Bits(INPUT,4) + //val s_axi_awprot = Bits(INPUT,3) + //val s_axi_awqos = Bits(INPUT,4) + val s_axi_awvalid = Bool(INPUT) + val s_axi_awready = Bool(OUTPUT) + //slave interface write data + val s_axi_wdata = Bits(INPUT,128) // 64 + val s_axi_wstrb = Bits(INPUT,16) // 8 + val s_axi_wlast = Bool(INPUT) + val s_axi_wvalid = Bool(INPUT) + val s_axi_wready = Bool(OUTPUT) + //slave interface write response + val s_axi_bready = Bool(INPUT) + val s_axi_bid = Bits(OUTPUT,4) + val s_axi_bresp = Bits(OUTPUT,2) + val s_axi_bvalid = Bool(OUTPUT) + //slave interface read address + val s_axi_arid = Bits(INPUT,4) + val s_axi_araddr = Bits(INPUT,32) + val s_axi_arregion = Bits(INPUT,4) + val s_axi_arlen = Bits(INPUT,8) + val s_axi_arsize = Bits(INPUT,3) + val s_axi_arburst = Bits(INPUT,2) + //val s_axi_arlock = Bits(INPUT,1) + //val s_axi_arcache = Bits(INPUT,4) + //val s_axi_arprot = Bits(INPUT,3) + //val s_axi_arqos = Bits(INPUT,4) + val s_axi_arvalid = Bool(INPUT) + val s_axi_arready = Bool(OUTPUT) + //slave interface read data + val s_axi_rready = Bool(INPUT) + val s_axi_rid = Bits(OUTPUT,4) + val s_axi_rdata = Bits(OUTPUT,128) // 64 + val s_axi_rresp = Bits(OUTPUT,2) + val s_axi_rlast = Bool(OUTPUT) + val s_axi_rvalid = Bool(OUTPUT) + + //axi master + //-{id,region,qos} + //slave interface write address ports + //val m_axi_awid = Bits(OUTPUT,4) + val m_axi_awaddr = Bits(OUTPUT,32) + //val m_axi_awregion = Bits(OUTPUT,4) + val m_axi_awlen = Bits(OUTPUT,8) + val m_axi_awsize = Bits(OUTPUT,3) + val m_axi_awburst = Bits(OUTPUT,2) + val m_axi_awlock = Bool(OUTPUT) + val m_axi_awcache = Bits(OUTPUT,4) + val m_axi_awprot = Bits(OUTPUT,3) + //val m_axi_awqos = Bits(OUTPUT,4) + val m_axi_awvalid = Bool(OUTPUT) + val m_axi_awready = Bool(INPUT) + //slave interface write data ports + val m_axi_wdata = Bits(OUTPUT,128) // 64 + val m_axi_wstrb = Bits(OUTPUT,16) // 8 + val m_axi_wlast = Bool(OUTPUT) + val m_axi_wvalid = Bool(OUTPUT) + val m_axi_wready = Bool(INPUT) + //slave interface write response ports + val m_axi_bready = Bool(OUTPUT) + //val m_axi_bid = Bits(INPUT,3) // 4 + val m_axi_bresp = Bits(INPUT,2) + val m_axi_bvalid = Bool(INPUT) + //slave interface read address ports + //val m_axi_arid = Bits(OUTPUT,4) + val m_axi_araddr = Bits(OUTPUT,32) + //val m_axi_arregion = Bits(OUTPUT,4) + val m_axi_arlen = Bits(OUTPUT,8) + val m_axi_arsize = Bits(OUTPUT,3) + val m_axi_arburst = Bits(OUTPUT,2) + val m_axi_arlock = Bits(OUTPUT,1) + val m_axi_arcache = Bits(OUTPUT,4) + val m_axi_arprot = Bits(OUTPUT,3) + //val m_axi_arqos = Bits(OUTPUT,4) + val m_axi_arvalid = Bool(OUTPUT) + val m_axi_arready = Bool(INPUT) + //slave interface read data ports + val m_axi_rready = Bool(OUTPUT) + //val m_axi_rid = Bits(INPUT,4) + val m_axi_rdata = Bits(INPUT,128) // 64 + val m_axi_rresp = Bits(INPUT,2) + val m_axi_rlast = Bool(INPUT) + val m_axi_rvalid = Bool(INPUT) + + //axi lite slave for control + val s_axi_ctl_awaddr = Bits(INPUT,28) // 32 + val s_axi_ctl_awvalid = Bool(INPUT) + val s_axi_ctl_awready = Bool(OUTPUT) + val s_axi_ctl_wdata = Bits(INPUT,32) + val s_axi_ctl_wstrb = Bits(INPUT,4) + val s_axi_ctl_wvalid = Bool(INPUT) + val s_axi_ctl_wready = Bool(OUTPUT) + val s_axi_ctl_bresp = Bits(OUTPUT,2) + val s_axi_ctl_bvalid = Bool(OUTPUT) + val s_axi_ctl_bready = Bool(INPUT) + val s_axi_ctl_araddr = Bits(INPUT,28) // 32 + val s_axi_ctl_arvalid = Bool(INPUT) + val s_axi_ctl_arready = Bool(OUTPUT) + val s_axi_ctl_rdata = Bits(OUTPUT,32) + val s_axi_ctl_rresp = Bits(OUTPUT,2) + val s_axi_ctl_rvalid = Bool(OUTPUT) + val s_axi_ctl_rready = Bool(INPUT) + } +} +//scalastyle:off + +//wrap vc709_axi_to_pcie_x1 black box in Nasti Bundles + +class VC709AXIToPCIeX1(implicit p:Parameters) extends LazyModule +{ + // device-tree node + val device = new SimpleDevice("pci", Seq("xlnx,axi-pcie-host-1.00.a")) { + override def describe(resources: ResourceBindings): Description = { + val Description(name, mapping) = super.describe(resources) + val intc = "pcie_intc" + def ofInt(x: Int) = Seq(ResourceInt(BigInt(x))) + def ofMap(x: Int) = Seq(0, 0, 0, x).flatMap(ofInt) ++ Seq(ResourceReference(intc)) ++ ofInt(x) + val extra = Map( + "#address-cells" -> ofInt(3), + "#size-cells" -> ofInt(2), + "#interrupt-cells" -> ofInt(1), + "device_type" -> Seq(ResourceString("pci")), + "ranges" -> resources("ranges").map(x => + (x: @unchecked) match { case Binding(_, ResourceAddress(address, perms)) => + ResourceMapping(address, BigInt(0x02000000) << 64, perms) }), + "interrupt-map-mask" -> Seq(0, 0, 0, 7).flatMap(ofInt), + "interrupt-map" -> Seq(1, 2, 3, 4).flatMap(ofMap), + "interrupt-controller" -> Seq(ResourceMap(labels = Seq(intc), value = Map( + "interrupt-controller" -> Nil, + "#address-cells" -> ofInt(0), + "#interrupt-cells" -> ofInt(1))))) + Description(name, mapping ++ extra) + } + } + + val slave = AXI4SlaveNode(Seq(AXI4SlavePortParameters( + slaves = Seq(AXI4SlaveParameters( + address = List(AddressSet(0x40000000L, 0x1fffffffL)), + resources = Seq(Resource(device, "ranges")), + executable = true, + supportsWrite = TransferSizes(1, 128), + supportsRead = TransferSizes(1, 128))), + beatBytes = 8))) + + val control = AXI4SlaveNode(Seq(AXI4SlavePortParameters( + slaves = Seq(AXI4SlaveParameters( + address = List(AddressSet(0x2000000000L, 0x3ffffffL)), // when truncated to 32-bits, is 0 + resources = device.reg("control"), + supportsWrite = TransferSizes(1, 4), + supportsRead = TransferSizes(1, 4), + interleavedId = Some(0))), // AXI4-Lite never interleaves responses + beatBytes = 4))) + + val master = AXI4MasterNode(Seq(AXI4MasterPortParameters( + masters = Seq(AXI4MasterParameters( + name = "VC709 PCIe", + id = IdRange(0, 1), + aligned = false))))) + + val intnode = IntSourceNode(IntSourcePortSimple(resources = device.int)) + + lazy val module = new LazyModuleImp(this) { + // The master on the control port must be AXI-lite + require (control.edges.in(0).master.endId == 1) + // Must have exactly the right number of idBits + require (slave.edges.in(0).bundle.idBits == 4) + + class VC709AXIToPCIeX1IOBundle extends Bundle with VC709AXIToPCIeX1IOSerial + with VC709AXIToPCIeX1IOClocksReset; + + val io = IO(new Bundle { + val port = new VC709AXIToPCIeX1IOBundle + val refclk = Bool(INPUT) // REFCLK is changed to refclk in 3.0 + }) + + val blackbox = Module(new vc709axi_to_pcie_x1) + + val (s, _) = slave.in(0) + val (c, _) = control.in(0) + val (m, _) = master.out(0) + val (i, _) = intnode.out(0) + + //to top level + blackbox.io.axi_aresetn := io.port.axi_aresetn + io.port.axi_aclk := blackbox.io.axi_aclk // axi_aclk_out is changed to axi_aclk in 3.0 + // io.port.axi_ctl_aclk_out := blackbox.io.axi_ctl_aclk_out + // io.port.mmcm_lock := blackbox.io.mmcm_lock + io.port.pci_exp_txp := blackbox.io.pci_exp_txp + io.port.pci_exp_txn := blackbox.io.pci_exp_txn + blackbox.io.pci_exp_rxp := io.port.pci_exp_rxp + blackbox.io.pci_exp_rxn := io.port.pci_exp_rxn + i(0) := blackbox.io.interrupt_out + blackbox.io.refclk := io.refclk // REFCLK is changed in to refclk 3.0 + + //s + //AXI4 signals ordered as per AXI4 Specification (Release D) Section A.2 + //-{lock, cache, prot, qos} + //-{aclk, aresetn, awuser, wid, wuser, buser, ruser} + //global signals + //aclk := + //aresetn := + //slave interface write address + blackbox.io.s_axi_awid := s.aw.bits.id + blackbox.io.s_axi_awaddr := s.aw.bits.addr + blackbox.io.s_axi_awlen := s.aw.bits.len + blackbox.io.s_axi_awsize := s.aw.bits.size + blackbox.io.s_axi_awburst := s.aw.bits.burst + //blackbox.io.s_axi_awlock := s.aw.bits.lock + //blackbox.io.s_axi_awcache := s.aw.bits.cache + //blackbox.io.s_axi_awprot := s.aw.bits.prot + //blackbox.io.s_axi_awqos := s.aw.bits.qos + blackbox.io.s_axi_awregion := UInt(0) + //blackbox.io.awuser := s.aw.bits.user + blackbox.io.s_axi_awvalid := s.aw.valid + s.aw.ready := blackbox.io.s_axi_awready + //slave interface write data ports + //blackbox.io.s_axi_wid := s.w.bits.id + blackbox.io.s_axi_wdata := s.w.bits.data + blackbox.io.s_axi_wstrb := s.w.bits.strb + blackbox.io.s_axi_wlast := s.w.bits.last + //blackbox.io.s_axi_wuser := s.w.bits.user + blackbox.io.s_axi_wvalid := s.w.valid + s.w.ready := blackbox.io.s_axi_wready + //slave interface write response + s.b.bits.id := blackbox.io.s_axi_bid + s.b.bits.resp := blackbox.io.s_axi_bresp + //s.b.bits.user := blackbox.io.s_axi_buser + s.b.valid := blackbox.io.s_axi_bvalid + blackbox.io.s_axi_bready := s.b.ready + //slave AXI interface read address ports + blackbox.io.s_axi_arid := s.ar.bits.id + blackbox.io.s_axi_araddr := s.ar.bits.addr + blackbox.io.s_axi_arlen := s.ar.bits.len + blackbox.io.s_axi_arsize := s.ar.bits.size + blackbox.io.s_axi_arburst := s.ar.bits.burst + //blackbox.io.s_axi_arlock := s.ar.bits.lock + //blackbox.io.s_axi_arcache := s.ar.bits.cache + //blackbox.io.s_axi_arprot := s.ar.bits.prot + //blackbox.io.s_axi_arqos := s.ar.bits.qos + blackbox.io.s_axi_arregion := UInt(0) + //blackbox.io.s_axi_aruser := s.ar.bits.user + blackbox.io.s_axi_arvalid := s.ar.valid + s.ar.ready := blackbox.io.s_axi_arready + //slave AXI interface read data ports + s.r.bits.id := blackbox.io.s_axi_rid + s.r.bits.data := blackbox.io.s_axi_rdata + s.r.bits.resp := blackbox.io.s_axi_rresp + s.r.bits.last := blackbox.io.s_axi_rlast + //s.r.bits.ruser := blackbox.io.s_axi_ruser + s.r.valid := blackbox.io.s_axi_rvalid + blackbox.io.s_axi_rready := s.r.ready + + //ctl + //axi-lite slave interface write address + blackbox.io.s_axi_ctl_awaddr := c.aw.bits.addr + blackbox.io.s_axi_ctl_awvalid := c.aw.valid + c.aw.ready := blackbox.io.s_axi_ctl_awready + //axi-lite slave interface write data ports + blackbox.io.s_axi_ctl_wdata := c.w.bits.data + blackbox.io.s_axi_ctl_wstrb := c.w.bits.strb + blackbox.io.s_axi_ctl_wvalid := c.w.valid + c.w.ready := blackbox.io.s_axi_ctl_wready + //axi-lite slave interface write response + blackbox.io.s_axi_ctl_bready := c.b.ready + c.b.bits.id := UInt(0) + c.b.bits.resp := blackbox.io.s_axi_ctl_bresp + c.b.valid := blackbox.io.s_axi_ctl_bvalid + //axi-lite slave AXI interface read address ports + blackbox.io.s_axi_ctl_araddr := c.ar.bits.addr + blackbox.io.s_axi_ctl_arvalid := c.ar.valid + c.ar.ready := blackbox.io.s_axi_ctl_arready + //slave AXI interface read data ports + blackbox.io.s_axi_ctl_rready := c.r.ready + c.r.bits.id := UInt(0) + c.r.bits.data := blackbox.io.s_axi_ctl_rdata + c.r.bits.resp := blackbox.io.s_axi_ctl_rresp + c.r.bits.last := Bool(true) + c.r.valid := blackbox.io.s_axi_ctl_rvalid + + //m + //AXI4 signals ordered per AXI4 Specification (Release D) Section A.2 + //-{id,region,qos} + //-{aclk, aresetn, awuser, wid, wuser, buser, ruser} + //global signals + //aclk := + //aresetn := + //master interface write address + m.aw.bits.id := UInt(0) + m.aw.bits.addr := blackbox.io.m_axi_awaddr + m.aw.bits.len := blackbox.io.m_axi_awlen + m.aw.bits.size := blackbox.io.m_axi_awsize + m.aw.bits.burst := blackbox.io.m_axi_awburst + m.aw.bits.lock := blackbox.io.m_axi_awlock + m.aw.bits.cache := blackbox.io.m_axi_awcache + m.aw.bits.prot := blackbox.io.m_axi_awprot + m.aw.bits.qos := UInt(0) + //m.aw.bits.region := blackbox.io.m_axi_awregion + //m.aw.bits.user := blackbox.io.m_axi_awuser + m.aw.valid := blackbox.io.m_axi_awvalid + blackbox.io.m_axi_awready := m.aw.ready + + //master interface write data ports + m.w.bits.data := blackbox.io.m_axi_wdata + m.w.bits.strb := blackbox.io.m_axi_wstrb + m.w.bits.last := blackbox.io.m_axi_wlast + //m.w.bits.user := blackbox.io.m_axi_wuser + m.w.valid := blackbox.io.m_axi_wvalid + blackbox.io.m_axi_wready := m.w.ready + + //master interface write response + //blackbox.io.m_axi_bid := m.b.bits.id + blackbox.io.m_axi_bresp := m.b.bits.resp + //blackbox.io.m_axi_buser := m.b.bits.user + blackbox.io.m_axi_bvalid := m.b.valid + m.b.ready := blackbox.io.m_axi_bready + + //master AXI interface read address ports + m.ar.bits.id := UInt(0) + m.ar.bits.addr := blackbox.io.m_axi_araddr + m.ar.bits.len := blackbox.io.m_axi_arlen + m.ar.bits.size := blackbox.io.m_axi_arsize + m.ar.bits.burst := blackbox.io.m_axi_arburst + m.ar.bits.lock := blackbox.io.m_axi_arlock + m.ar.bits.cache := blackbox.io.m_axi_arcache + m.ar.bits.prot := blackbox.io.m_axi_arprot + m.ar.bits.qos := UInt(0) + //m.ar.bits.region := blackbox.io.m_axi_arregion + //m.ar.bits.user := blackbox.io.s_axi_aruser + m.ar.valid := blackbox.io.m_axi_arvalid + blackbox.io.m_axi_arready := m.ar.ready + + //master AXI interface read data ports + //blackbox.io.m_axi_rid := m.r.bits.id + blackbox.io.m_axi_rdata := m.r.bits.data + blackbox.io.m_axi_rresp := m.r.bits.resp + blackbox.io.m_axi_rlast := m.r.bits.last + //blackbox.io.s_axi_ruser := s.bits.ruser + blackbox.io.m_axi_rvalid := m.r.valid + m.r.ready := blackbox.io.m_axi_rready + } + + ElaborationArtefacts.add( + "vc709axi_to_pcie_x1.vivado.tcl", + """ + create_ip -vendor xilinx.com -library ip -version 3.0 -name axi_pcie3 -module_name vc709axi_to_pcie_x1 -dir $ipdir -force + set_property -dict [list \ + CONFIG.AXIBAR2PCIEBAR_0 {0x40000000} \ + CONFIG.AXIBAR_0 {0x40000000} \ + CONFIG.AXIBAR_HIGHADDR_0 {0x5FFFFFFF} \ + CONFIG.AXIBAR_NUM {1} \ + CONFIG.BASEADDR {0x00000000} \ + CONFIG.HIGHADDR {0x03FFFFFF} \ + CONFIG.COMP_TIMEOUT {50ms} \ + CONFIG.DEVICE_PORT_TYPE {Root_Port_of_PCI_Express_Root_Complex}\ + CONFIG.INCLUDE_BAROFFSET_REG {true} \ + CONFIG.PCIEBAR2AXIBAR_0 {0x00000000} \ + CONFIG.PCIE_BLK_LOCN {X0Y0} \ + CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \ + CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {2.5_GT/s} \ + CONFIG.PF0_DEVICE_ID {8018} \ + CONFIG.PF0_REVISION_ID {0} \ + CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10EE} \ + CONFIG.PF0_SUBSYSTEM_ID {7} \ + CONFIG.PF0_BAR0_64BIT {true} \ + CONFIG.PF0_BAR0_ENABLED {true} \ + CONFIG.PF0_BAR0_PREFETCHABLE {false} \ + CONFIG.PF0_BAR0_SCALE {Gigabytes} \ + CONFIG.PF0_BAR0_SIZE {4} \ + CONFIG.PF0_BAR0_TYPE {Memory} \ + CONFIG.PF0_SUB_CLASS_interface_menu {Host_bridge} \ + CONFIG.REF_CLK_FREQ {100_MHz} \ + CONFIG.AXI_ADDR_WIDTH {32} \ + CONFIG.AXI_DATA_WIDTH {128_bit} \ + CONFIG.VENDOR_ID {10EE} \ + CONFIG.XLNX_REF_BOARD {VC709} \ + CONFIG.axi_aclk_loopback {false} \ + CONFIG.en_ext_ch_gt_drp {false} \ + CONFIG.en_transceiver_status_ports {false} ] [get_ips vc709axi_to_pcie_x1]""" + ) +} diff --git a/src/main/scala/ip/xilinx/vc709mig/vc709-ddr.pin b/src/main/scala/ip/xilinx/vc709mig/vc709-ddr.pin new file mode 100644 index 00000000..3fb3e2ff --- /dev/null +++ b/src/main/scala/ip/xilinx/vc709mig/vc709-ddr.pin @@ -0,0 +1,36 @@ +// addr +"A20", "B19", "C20", "A19", "A17", "A16", "D20", "C18", "D17", "C19", "B21", "B17", "A15", "A21", "F17", "E17", +// ba +"D21", "C21", "D18", +// ctrl: ras_n, cas_n, we_n, reset_n, ck_p, ck_n, cke, cs_n, odt +"E20", "K17", "F20", "P18", "E19", "E18", "K19", "J17", "H20", +// dm +"M13", "K15", "F12", "A14", "C23", "D25", "C31", "F31", +// dq +"N14", "N13", "L14", "M14", "M12", "N15", "M11", "L12", "K14", "K13", "H13", "J13", "L16", "L15", "H14", "J15", +"E15", "E13", "F15", "E14", "G13", "G12", "F14", "G14", "B14", "C13", "B16", "D15", "D13", "E12", "C16", "D16", +"A24", "B23", "B27", "B26", "A22", "B22", "A25", "C24", "E24", "D23", "D26", "C25", "E23", "D22", "F22", "E22", +"A30", "D27", "A29", "C28", "D28", "B31", "A31", "A32", "E30", "F29", "F30", "F27", "C30", "E29", "F26", "D30", +// ddr3_dqs_n +"M16", "J12", "G16", "C14", "A27", "E25", "B29", "E28", +// ddr3_dqs_p +"N16", "K12", "H16", "C15", "A26", "F25", "B28", "E27", + + +// addr +"AN19", "AR19", "AP20", "AP17", "AP18", "AJ18", "AN16", "AM16", "AK18", "AK19", "AM17", "AM18", "AL17", "AK17", "AM19", "AL19", +// ba +"AR17", "AR18", "AN18", +// ctrl: ras_n, cas_n, we_n, reset_n, ck_p, ck_n, cke, cs_n, odt +"AV19", "AT20", "AU19", "BB19", "AT17", "AU17", "AW17", "AV16", "AT16", +// dm +"AT22", "AL22", "AU24", "BB23", "BB12", "AV15", "AK12", "AP13", +// dq +"AN24", "AM24", "AR22", "AR23", "AN23", "AM23", "AN21", "AP21", "AK23", "AJ23", "AL21", "AM21", "AJ21", "AJ20", "AK20", "AL20", +"AW22", "AW23", "AW21", "AV21", "AU23", "AV23", "AR24", "AT24", "BB24", "BA24", "AY23", "AY24", "AY25", "BA25", "BB21", "BA21", +"AY14", "AW15", "BB14", "BB13", "AW12", "AY13", "AY12", "BA12", "AU12", "AU13", "AT12", "AU14", "AV13", "AW13", "AT15", "AR15", +"AL15", "AJ15", "AK14", "AJ12", "AJ16", "AL16", "AJ13", "AK13", "AR14", "AT14", "AM12", "AP11", "AM13", "AN13", "AM11", "AN11", +// ddr3_dqs_n +"AP22", "AK22", "AU21", "BB22", "BA14", "AR12", "AL14", "AN14", +// ddr3_dqs_p +"AP23", "AJ22", "AT21", "BA22", "BA15", "AP12", "AK15", "AN15", \ No newline at end of file diff --git a/src/main/scala/ip/xilinx/vc709mig/vc709mig.scala b/src/main/scala/ip/xilinx/vc709mig/vc709mig.scala new file mode 100644 index 00000000..85dbf642 --- /dev/null +++ b/src/main/scala/ip/xilinx/vc709mig/vc709mig.scala @@ -0,0 +1,330 @@ +// See LICENSE for license details. +package sifive.fpgashells.ip.xilinx.vc709mig + +import Chisel._ +import chisel3.experimental.{Analog,attach} +import freechips.rocketchip.util.{ElaborationArtefacts} +import freechips.rocketchip.util.GenericParameterizedBundle +import freechips.rocketchip.config._ + +// IP VLNV: xilinx.com:customize_ip:vc709mig:4.1 +// Black Box + +class VC709MIGIODDR(depth : BigInt) extends GenericParameterizedBundle(depth) { + require((depth<=0x100000000L),"VC709MIGIODDR supports upto 4GB depth configuraton") + val ddr3_addr = Bits(OUTPUT,16) + val ddr3_ba = Bits(OUTPUT,3) + val ddr3_ras_n = Bool(OUTPUT) + val ddr3_cas_n = Bool(OUTPUT) + val ddr3_we_n = Bool(OUTPUT) + val ddr3_reset_n = Bool(OUTPUT) + val ddr3_ck_p = Bits(OUTPUT,1) + val ddr3_ck_n = Bits(OUTPUT,1) + val ddr3_cke = Bits(OUTPUT,1) + val ddr3_cs_n = Bits(OUTPUT,1) + val ddr3_odt = Bits(OUTPUT,1) + val ddr3_dm = Bits(OUTPUT,8) + + val ddr3_dq = Analog(64.W) + val ddr3_dqs_n = Analog(8.W) + val ddr3_dqs_p = Analog(8.W) +} + +//reused directly in io bundle for sifive.blocks.devices.xilinxvc709mig +trait VC709MIGIOClocksReset extends Bundle { + //inputs + //"NO_BUFFER" clock source (must be connected to IBUF outside of IP) + val sys_clk_i = Bool(INPUT) + //user interface signals + val ui_clk = Clock(OUTPUT) + val ui_clk_sync_rst = Bool(OUTPUT) + val mmcm_locked = Bool(OUTPUT) + val aresetn = Bool(INPUT) + //misc + val init_calib_complete = Bool(OUTPUT) + val sys_rst = Bool(INPUT) +} + +//scalastyle:off +//turn off linter: blackbox name must match verilog module +class vc709mig(depth : BigInt)(implicit val p:Parameters) extends BlackBox +{ + require((depth<=0x100000000L),"vc709mig supports upto 4GB depth configuraton") + override def desiredName = "vc709mig4gb" + + val io = new VC709MIGIODDR(depth) with VC709MIGIOClocksReset { + // User interface signals + val app_sr_req = Bool(INPUT) + val app_ref_req = Bool(INPUT) + val app_zq_req = Bool(INPUT) + val app_sr_active = Bool(OUTPUT) + val app_ref_ack = Bool(OUTPUT) + val app_zq_ack = Bool(OUTPUT) + //axi_s + //slave interface write address ports + val s_axi_awid = Bits(INPUT,4) + val s_axi_awaddr = Bits(INPUT,32) + val s_axi_awlen = Bits(INPUT,8) + val s_axi_awsize = Bits(INPUT,3) + val s_axi_awburst = Bits(INPUT,2) + val s_axi_awlock = Bits(INPUT,1) + val s_axi_awcache = Bits(INPUT,4) + val s_axi_awprot = Bits(INPUT,3) + val s_axi_awqos = Bits(INPUT,4) + val s_axi_awvalid = Bool(INPUT) + val s_axi_awready = Bool(OUTPUT) + //slave interface write data ports + val s_axi_wdata = Bits(INPUT,64) + val s_axi_wstrb = Bits(INPUT,8) + val s_axi_wlast = Bool(INPUT) + val s_axi_wvalid = Bool(INPUT) + val s_axi_wready = Bool(OUTPUT) + //slave interface write response ports + val s_axi_bready = Bool(INPUT) + val s_axi_bid = Bits(OUTPUT,4) + val s_axi_bresp = Bits(OUTPUT,2) + val s_axi_bvalid = Bool(OUTPUT) + //slave interface read address ports + val s_axi_arid = Bits(INPUT,4) + val s_axi_araddr = Bits(INPUT,32) + val s_axi_arlen = Bits(INPUT,8) + val s_axi_arsize = Bits(INPUT,3) + val s_axi_arburst = Bits(INPUT,2) + val s_axi_arlock = Bits(INPUT,1) + val s_axi_arcache = Bits(INPUT,4) + val s_axi_arprot = Bits(INPUT,3) + val s_axi_arqos = Bits(INPUT,4) + val s_axi_arvalid = Bool(INPUT) + val s_axi_arready = Bool(OUTPUT) + //slave interface read data ports + val s_axi_rready = Bool(INPUT) + val s_axi_rid = Bits(OUTPUT,4) + val s_axi_rdata = Bits(OUTPUT,64) + val s_axi_rresp = Bits(OUTPUT,2) + val s_axi_rlast = Bool(OUTPUT) + val s_axi_rvalid = Bool(OUTPUT) + //misc + val device_temp = Bits(OUTPUT,12) + } + + val vc709mig4gbprj = """ { + + + vc709mig4gb + 1 + 1 + OFF + 1024 + ON + Enabled + xc7vx690t-ffg1761/-2 + 4.1 + No Buffer + Use System Clock + ACTIVE HIGH + FALSE + 0 + 50 Ohms + 0 + + DDR3_SDRAM/SODIMMs/MT8KTF51264HZ-1G9 + 1250 + 2.0V + 4:1 + 200 + 0 + 800 + 1.000 + 1 + 1 + 1 + 1 + 64 + 1 + 1 + Disabled + Normal + 4 + FALSE + + 16 + 10 + 3 + 1.5V + BANK_ROW_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 11 + Normal + No + Slow Exit + Enable + RZQ/7 + Disable + Enable + RZQ/6 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 8 + Enabled + Normal + Dynamic ODT off + AXI + + RD_PRI_REG + 32 + 64 + 4 + 0 + + + + +}""" + + val migprj = vc709mig4gbprj + val migprjname = """{/vc709mig4gb.prj}""" + val modulename = """vc709mig4gb""" + + ElaborationArtefacts.add( + modulename++".vivado.tcl", + """set migprj """++migprj++""" + set migprjfile """++migprjname++""" + set migprjfilepath $ipdir$migprjfile + set fp [open $migprjfilepath w+] + puts $fp $migprj + close $fp + create_ip -vendor xilinx.com -library ip -name mig_7series -module_name """ ++ modulename ++ """ -dir $ipdir -force + set_property CONFIG.XML_INPUT_FILE $migprjfilepath [get_ips """ ++ modulename ++ """] """ + ) +} +//scalastyle:on diff --git a/src/main/scala/ip/xilinx/vc709mig/vc709mig8g.scala b/src/main/scala/ip/xilinx/vc709mig/vc709mig8g.scala new file mode 100644 index 00000000..404ac56d --- /dev/null +++ b/src/main/scala/ip/xilinx/vc709mig/vc709mig8g.scala @@ -0,0 +1,598 @@ +// See LICENSE for license details. +package sifive.fpgashells.ip.xilinx.vc709mig8g + +import Chisel._ +import chisel3.experimental.{Analog,attach} +import freechips.rocketchip.util.{ElaborationArtefacts} +import freechips.rocketchip.util.GenericParameterizedBundle +import freechips.rocketchip.config._ + +// IP VLNV: xilinx.com:customize_ip:vc709mig:1.0 +// Black Box + +class VC709MIGIODDR(depth : BigInt) extends GenericParameterizedBundle(depth) { + require((depth<=0x200000000L),"VC709MIGIODDR supports upto 8GB depth configuraton") + // DDR3 SODIMM 0 + val c0_ddr3_addr = Bits(OUTPUT,16) + val c0_ddr3_ba = Bits(OUTPUT,3) + val c0_ddr3_ras_n = Bool(OUTPUT) + val c0_ddr3_cas_n = Bool(OUTPUT) + val c0_ddr3_we_n = Bool(OUTPUT) + val c0_ddr3_reset_n = Bool(OUTPUT) + val c0_ddr3_ck_p = Bits(OUTPUT,1) + val c0_ddr3_ck_n = Bits(OUTPUT,1) + val c0_ddr3_cke = Bits(OUTPUT,1) + val c0_ddr3_cs_n = Bits(OUTPUT,1) + val c0_ddr3_dm = Bits(OUTPUT,8) + val c0_ddr3_odt = Bits(OUTPUT,1) + + val c0_ddr3_dq = Analog(64.W) + val c0_ddr3_dqs_n = Analog(8.W) + val c0_ddr3_dqs_p = Analog(8.W) + + // DDR3 SODIMM 1 + val c1_ddr3_addr = Bits(OUTPUT,16) + val c1_ddr3_ba = Bits(OUTPUT,3) + val c1_ddr3_ras_n = Bool(OUTPUT) + val c1_ddr3_cas_n = Bool(OUTPUT) + val c1_ddr3_we_n = Bool(OUTPUT) + val c1_ddr3_reset_n = Bool(OUTPUT) + val c1_ddr3_ck_p = Bits(OUTPUT,1) + val c1_ddr3_ck_n = Bits(OUTPUT,1) + val c1_ddr3_cke = Bits(OUTPUT,1) + val c1_ddr3_cs_n = Bits(OUTPUT,1) + val c1_ddr3_dm = Bits(OUTPUT,8) + val c1_ddr3_odt = Bits(OUTPUT,1) + + val c1_ddr3_dq = Analog(64.W) + val c1_ddr3_dqs_n = Analog(8.W) + val c1_ddr3_dqs_p = Analog(8.W) +} + +//reused directly in io bundle for sifive.blocks.devices.xilinxvc709mig +trait VC709MIGIOClocksReset extends Bundle { + // DDR3 SODIMM 0 + //inputs + //"NO_BUFFER" clock source (must be connected to IBUF outside of IP) + val c0_sys_clk_i = Bool(INPUT) + //user interface signals + val c0_ui_clk = Clock(OUTPUT) + val c0_ui_clk_sync_rst = Bool(OUTPUT) + val c0_mmcm_locked = Bool(OUTPUT) + val c0_aresetn = Bool(INPUT) + //misc + val c0_init_calib_complete = Bool(OUTPUT) + + // DDR3 SODIMM 1 + //inputs + //"NO_BUFFER" clock source (must be connected to IBUF outside of IP) + val c1_sys_clk_i = Bool(INPUT) + //user interface signals + val c1_ui_clk = Clock(OUTPUT) + val c1_ui_clk_sync_rst = Bool(OUTPUT) + val c1_mmcm_locked = Bool(OUTPUT) + val c1_aresetn = Bool(INPUT) + //misc + val c1_init_calib_complete = Bool(OUTPUT) + + // common part + val sys_rst = Bool(INPUT) +} + +//scalastyle:off +//turn off linter: blackbox name must match verilog module +class vc709mig(depth : BigInt)(implicit val p:Parameters) extends BlackBox +{ + require((depth<=0x200000000L),"vc709mig supports upto 8GB depth configuraton") + override def desiredName = "vc709mig8gb" + + val io = new VC709MIGIODDR(depth) with VC709MIGIOClocksReset { + + //axi_s [DDR3 SODIMM 0] + // User interface signals (DDR3 SODIMM 0) + val c0_app_sr_req = Bool(INPUT) + val c0_app_ref_req = Bool(INPUT) + val c0_app_zq_req = Bool(INPUT) + val c0_app_sr_active = Bool(OUTPUT) + val c0_app_ref_ack = Bool(OUTPUT) + val c0_app_zq_ack = Bool(OUTPUT) + + //slave interface write address ports + val c0_s_axi_awid = Bits(INPUT,4) + val c0_s_axi_awaddr = Bits(INPUT,32) + val c0_s_axi_awlen = Bits(INPUT,8) + val c0_s_axi_awsize = Bits(INPUT,3) + val c0_s_axi_awburst = Bits(INPUT,2) + val c0_s_axi_awlock = Bits(INPUT,1) + val c0_s_axi_awcache = Bits(INPUT,4) + val c0_s_axi_awprot = Bits(INPUT,3) + val c0_s_axi_awqos = Bits(INPUT,4) + val c0_s_axi_awvalid = Bool(INPUT) + val c0_s_axi_awready = Bool(OUTPUT) + //slave interface write data ports + val c0_s_axi_wdata = Bits(INPUT,64) + val c0_s_axi_wstrb = Bits(INPUT,8) + val c0_s_axi_wlast = Bool(INPUT) + val c0_s_axi_wvalid = Bool(INPUT) + val c0_s_axi_wready = Bool(OUTPUT) + //slave interface write response ports + val c0_s_axi_bready = Bool(INPUT) + val c0_s_axi_bid = Bits(OUTPUT,4) + val c0_s_axi_bresp = Bits(OUTPUT,2) + val c0_s_axi_bvalid = Bool(OUTPUT) + //slave interface read address ports + val c0_s_axi_arid = Bits(INPUT,4) + val c0_s_axi_araddr = Bits(INPUT,32) + val c0_s_axi_arlen = Bits(INPUT,8) + val c0_s_axi_arsize = Bits(INPUT,3) + val c0_s_axi_arburst = Bits(INPUT,2) + val c0_s_axi_arlock = Bits(INPUT,1) + val c0_s_axi_arcache = Bits(INPUT,4) + val c0_s_axi_arprot = Bits(INPUT,3) + val c0_s_axi_arqos = Bits(INPUT,4) + val c0_s_axi_arvalid = Bool(INPUT) + val c0_s_axi_arready = Bool(OUTPUT) + //slave interface read data ports + val c0_s_axi_rready = Bool(INPUT) + val c0_s_axi_rid = Bits(OUTPUT,4) + val c0_s_axi_rdata = Bits(OUTPUT,64) + val c0_s_axi_rresp = Bits(OUTPUT,2) + val c0_s_axi_rlast = Bool(OUTPUT) + val c0_s_axi_rvalid = Bool(OUTPUT) + //misc + val c0_device_temp = Bits(OUTPUT,12) + + //axi_s [DDR3 SODIMM 1] + // User interface signals + val c1_app_sr_req = Bool(INPUT) + val c1_app_ref_req = Bool(INPUT) + val c1_app_zq_req = Bool(INPUT) + val c1_app_sr_active = Bool(OUTPUT) + val c1_app_ref_ack = Bool(OUTPUT) + val c1_app_zq_ack = Bool(OUTPUT) + + //slave interface write address ports + val c1_s_axi_awid = Bits(INPUT,4) + val c1_s_axi_awaddr = Bits(INPUT,32) + val c1_s_axi_awlen = Bits(INPUT,8) + val c1_s_axi_awsize = Bits(INPUT,3) + val c1_s_axi_awburst = Bits(INPUT,2) + val c1_s_axi_awlock = Bits(INPUT,1) + val c1_s_axi_awcache = Bits(INPUT,4) + val c1_s_axi_awprot = Bits(INPUT,3) + val c1_s_axi_awqos = Bits(INPUT,4) + val c1_s_axi_awvalid = Bool(INPUT) + val c1_s_axi_awready = Bool(OUTPUT) + //slave interface write data ports + val c1_s_axi_wdata = Bits(INPUT,64) + val c1_s_axi_wstrb = Bits(INPUT,8) + val c1_s_axi_wlast = Bool(INPUT) + val c1_s_axi_wvalid = Bool(INPUT) + val c1_s_axi_wready = Bool(OUTPUT) + //slave interface write response ports + val c1_s_axi_bready = Bool(INPUT) + val c1_s_axi_bid = Bits(OUTPUT,4) + val c1_s_axi_bresp = Bits(OUTPUT,2) + val c1_s_axi_bvalid = Bool(OUTPUT) + //slave interface read address ports + val c1_s_axi_arid = Bits(INPUT,4) + val c1_s_axi_araddr = Bits(INPUT,32) + val c1_s_axi_arlen = Bits(INPUT,8) + val c1_s_axi_arsize = Bits(INPUT,3) + val c1_s_axi_arburst = Bits(INPUT,2) + val c1_s_axi_arlock = Bits(INPUT,1) + val c1_s_axi_arcache = Bits(INPUT,4) + val c1_s_axi_arprot = Bits(INPUT,3) + val c1_s_axi_arqos = Bits(INPUT,4) + val c1_s_axi_arvalid = Bool(INPUT) + val c1_s_axi_arready = Bool(OUTPUT) + //slave interface read data ports + val c1_s_axi_rready = Bool(INPUT) + val c1_s_axi_rid = Bits(OUTPUT,4) + val c1_s_axi_rdata = Bits(OUTPUT,64) + val c1_s_axi_rresp = Bits(OUTPUT,2) + val c1_s_axi_rlast = Bool(OUTPUT) + val c1_s_axi_rvalid = Bool(OUTPUT) + //misc + val c1_device_temp = Bits(OUTPUT,12) + } + + var vc709mig8gbprj = """ { + + + vc709mig8gb + 1 + 1 + Disable + 1024 + ON + Enabled + xc7vx690t-ffg1761/-2 + 4.1 + No Buffer + Use System Clock + ACTIVE HIGH + FALSE + 0 + 50 Ohms + 0 + + DDR3_SDRAM/SODIMMs/MT8KTF51264HZ-1G9 + 1250 + 2.0V + 4:1 + 200 + 0 + 800 + 1.000 + 1 + 1 + 1 + 1 + 64 + 1 + 1 + Disabled + Normal + 4 + FALSE + + 16 + 10 + 3 + 1.5V + BANK_ROW_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 11 + Normal + No + Slow Exit + Enable + RZQ/7 + Disable + Enable + RZQ/6 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 8 + Enabled + Normal + Dynamic ODT off + AXI + + RD_PRI_REG + 32 + 64 + 4 + 0 + + + + + + DDR3_SDRAM/SODIMMs/MT8KTF51264HZ-1G9 + 1250 + 2.0V + 4:1 + 200 + 0 + 800 + 1.000 + 1 + 1 + 1 + 1 + 64 + 1 + 1 + Disabled + Normal + 4 + FALSE + + 16 + 10 + 3 + 1.5V + BANK_ROW_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 11 + Normal + No + Slow Exit + Enable + RZQ/7 + Disable + Enable + RZQ/6 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 8 + Enabled + Normal + Dynamic ODT off + AXI + + RD_PRI_REG + 32 + 64 + 4 + 0 + + + + +}""" + + val migprj = vc709mig8gbprj + val migprjname = """{/vc709mig8gb.prj}""" + val modulename = """vc709mig8gb""" + + ElaborationArtefacts.add( + modulename++".vivado.tcl", + """set migprj """++migprj++""" + set migprjfile """++migprjname++""" + set migprjfilepath $ipdir$migprjfile + set fp [open $migprjfilepath w+] + puts $fp $migprj + close $fp + create_ip -vendor xilinx.com -library ip -name mig_7series -module_name """ ++ modulename ++ """ -dir $ipdir -force + set_property CONFIG.XML_INPUT_FILE $migprjfilepath [get_ips """ ++ modulename ++ """] """ + ) +} +//scalastyle:on diff --git a/src/main/scala/shell/xilinx/VC709NewShell.scala b/src/main/scala/shell/xilinx/VC709NewShell.scala new file mode 100644 index 00000000..9d3a4185 --- /dev/null +++ b/src/main/scala/shell/xilinx/VC709NewShell.scala @@ -0,0 +1,359 @@ +// See LICENSE for license details. +package sifive.fpgashells.shell.xilinx + +import chisel3._ +import chisel3.experimental.{attach, IO, withClockAndReset} +import freechips.rocketchip.config._ +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.util.SyncResetSynchronizerShiftReg +import sifive.fpgashells.clocks._ +import sifive.fpgashells.shell._ +import sifive.fpgashells.ip.xilinx._ +import sifive.blocks.devices.chiplink._ +import sifive.fpgashells.devices.xilinx.xilinxvc709mig._ +import sifive.fpgashells.devices.xilinx.xilinxvc709pciex1._ + +class SysClockVC709PlacedOverlay(val shell: VC709Shell, name: String, val designInput: ClockInputDesignInput, val shellInput: ClockInputShellInput) + extends LVDSClockInputXilinxPlacedOverlay(name, designInput, shellInput) +{ + val node = shell { ClockSourceNode(freqMHz = 200, jitterPS = 50)(ValName(name)) } + + shell { InModuleBody { + shell.xdc.addBoardPin(io.p, "clk_p") + shell.xdc.addBoardPin(io.n, "clk_n") + // shell.xdc.addPackagePin(io.p, "H19") + // shell.xdc.addPackagePin(io.n, "G18") + // shell.xdc.addIOStandard(io.p, "DIFF_SSTL15") + // shell.xdc.addIOStandard(io.n, "DIFF_SSTL15") + } } +} + +class SysClockVC709ShellPlacer(shell: VC709Shell, val shellInput: ClockInputShellInput)(implicit val valName: ValName) + extends ClockInputShellPlacer[VC709Shell] +{ + def place(designInput: ClockInputDesignInput) = new SysClockVC709PlacedOverlay(shell, valName.name, designInput, shellInput) +} + +class UARTVC709PlacedOverlay(val shell: VC709Shell, name: String, val designInput: UARTDesignInput, val shellInput: UARTShellInput) + extends UARTXilinxPlacedOverlay(name, designInput, shellInput, true) +{ + shell { InModuleBody { + val packagePinsWithPackageIOs = Seq(("AR34", IOPin(io.rtsn.get)), + ("AT32", IOPin(io.ctsn.get)), + ("AU36", IOPin(io.txd)), + ("AU33", IOPin(io.rxd))) + + packagePinsWithPackageIOs foreach { case (pin, io) => { + shell.xdc.addPackagePin(io, pin) + shell.xdc.addIOStandard(io, "LVCMOS18") + shell.xdc.addIOB(io) + } } + } } +} +class UARTVC709ShellPlacer(val shell: VC709Shell, val shellInput: UARTShellInput)(implicit val valName: ValName) + extends UARTShellPlacer[VC709Shell] { + def place(designInput: UARTDesignInput) = new UARTVC709PlacedOverlay(shell, valName.name, designInput, shellInput) +} + +class LEDVC709PlacedOverlay(val shell: VC709Shell, name: String, val designInput: LEDDesignInput, val shellInput: LEDShellInput) + extends LEDXilinxPlacedOverlay(name, designInput, shellInput, boardPin = Some(s"leds_8bits_tri_o_${shellInput.number}")) +class LEDVC709ShellPlacer(val shell: VC709Shell, val shellInput: LEDShellInput)(implicit val valName: ValName) + extends LEDShellPlacer[VC709Shell] { + def place(designInput: LEDDesignInput) = new LEDVC709PlacedOverlay(shell, valName.name, designInput, shellInput) +} + +class SwitchVC709PlacedOverlay(val shell: VC709Shell, name: String, val designInput: SwitchDesignInput, val shellInput: SwitchShellInput) + extends SwitchXilinxPlacedOverlay(name, designInput, shellInput, boardPin = Some(s"dip_switches_tri_i_${shellInput.number}")) +class SwitchVC709ShellPlacer(val shell: VC709Shell, val shellInput: SwitchShellInput)(implicit val valName: ValName) + extends SwitchShellPlacer[VC709Shell] { + def place(designInput: SwitchDesignInput) = new SwitchVC709PlacedOverlay(shell, valName.name, designInput, shellInput) +} + +class ButtonVC709PlacedOverlay(val shell: VC709Shell, name: String, val designInput: ButtonDesignInput, val shellInput: ButtonShellInput) + extends ButtonXilinxPlacedOverlay(name, designInput, shellInput, boardPin = Some(s"push_buttons_5bits_tri_i_${shellInput.number}")) +class ButtonVC709ShellPlacer(val shell: VC709Shell, val shellInput: ButtonShellInput)(implicit val valName: ValName) + extends ButtonShellPlacer[VC709Shell] { + def place(designInput: ButtonDesignInput) = new ButtonVC709PlacedOverlay(shell, valName.name, designInput, shellInput) +} + +class ChipLinkVC709PlacedOverlay(val shell: VC709Shell, name: String, val designInput: ChipLinkDesignInput, val shellInput: ChipLinkShellInput) + extends ChipLinkXilinxPlacedOverlay(name, designInput, shellInput, rxPhase=280, txPhase=220, rxMargin=0.3, txMargin=0.3) +{ + val ereset_n = shell { InModuleBody { + val ereset_n = IO(Input(Bool())) + ereset_n.suggestName("ereset_n") + shell.xdc.addPackagePin(ereset_n, "AF40") + shell.xdc.addIOStandard(ereset_n, "LVCMOS18") + shell.xdc.addTermination(ereset_n, "NONE") + ereset_n + } } + + shell { InModuleBody { + val dir1 = Seq("AF39", "AJ41", "AJ40", /* clk, rst, send */ + "AD40", "AD41", "AF41", "AG41", "AK39", "AL39", "AJ42", "AK42", + "AL41", "AL42", "AF42", "AG42", "AD38", "AE38", "AC40", "AC41", + "AD42", "AE42", "AJ38", "AK38", "AB41", "AB42", "Y42", "AA42", + "Y39", "AA39", "W40", "Y40", "AB38", "AB39", "AC38", "AC39") + val dir2 = Seq("U39", "R37", "T36", /* clk, rst, send */ + "U37", "U38", "U36", "T37", "U32", "U33", "V33", "V34", + "P35", "P36", "W32", "W33", "R38", "R39", "U34", "T35", + "R33", "R34", "N33", "N34", "P32", "P33", "V35", "V36", + "W36", "W37", "T32", "R32", "V39", "V40", "P37", "P38") + (IOPin.of(io.b2c) zip dir1) foreach { case (io, pin) => shell.xdc.addPackagePin(io, pin) } + (IOPin.of(io.c2b) zip dir2) foreach { case (io, pin) => shell.xdc.addPackagePin(io, pin) } + } } +} +class ChipLinkVC709ShellPlacer(val shell: VC709Shell, val shellInput: ChipLinkShellInput)(implicit val valName: ValName) + extends ChipLinkShellPlacer[VC709Shell] { + def place(designInput: ChipLinkDesignInput) = new ChipLinkVC709PlacedOverlay(shell, valName.name, designInput, shellInput) +} + +// TODO: JTAG is untested +class JTAGDebugVC709PlacedOverlay(val shell: VC709Shell, name: String, val designInput: JTAGDebugDesignInput, val shellInput: JTAGDebugShellInput) + extends JTAGDebugXilinxPlacedOverlay(name, designInput, shellInput) +{ + shell { InModuleBody { + shell.sdc.addClock("JTCK", IOPin(io.jtag_TCK), 10) + shell.sdc.addGroup(clocks = Seq("JTCK")) + shell.xdc.clockDedicatedRouteFalse(IOPin(io.jtag_TCK)) +/* if old method + val packagePinsWithPackageIOs = Seq(("R32", IOPin(io.jtag_TCK)), + ("W36", IOPin(io.jtag_TMS)), + ("W37", IOPin(io.jtag_TDI)), + ("V40", IOPin(io.jtag_TDO))) +*/ + /* + #Olimex Pin Olimex Function LCD Pin LCD Function FPGA Pin + #1 VREF 14 5V + #3 TTRST_N 1 LCD_DB7 AN40 + #5 TTDI 2 LCD_DB6 AR39 + #7 TTMS 3 LCD_DB5 AR38 + #9 TTCK 4 LCD_DB4 AT42 + #11 TRTCK NC NC NC + #13 TTDO 9 LCD_E AT40 + #15 TSRST_N 10 LCD_RW AR42 + #2 VREF 14 5V + #18 GND 13 GND + */ + val packagePinsWithPackageIOs = Seq(("AT42", IOPin(io.jtag_TCK)), + ("AR38", IOPin(io.jtag_TMS)), + ("AR39", IOPin(io.jtag_TDI)), + ("AR42", IOPin(io.srst_n)), + ("AT40", IOPin(io.jtag_TDO))) + packagePinsWithPackageIOs foreach { case (pin, io) => { + shell.xdc.addPackagePin(io, pin) + shell.xdc.addIOStandard(io, "LVCMOS18") + shell.xdc.addPullup(io) + } } + } } +} +class JTAGDebugVC709ShellPlacer(val shell: VC709Shell, val shellInput: JTAGDebugShellInput)(implicit val valName: ValName) + extends JTAGDebugShellPlacer[VC709Shell] { + def place(designInput: JTAGDebugDesignInput) = new JTAGDebugVC709PlacedOverlay(shell, valName.name, designInput, shellInput) +} + +case object VC709DDR3Size extends Field[BigInt](0x100000000L) // 4GB +class DDR3VC709PlacedOverlay(val shell: VC709Shell, name: String, val designInput: DDRDesignInput, val shellInput: DDRShellInput) + extends DDRPlacedOverlay[XilinxVC709MIGPads](name, designInput, shellInput) +{ + val size = p(VC709DDR3Size) + + val migParams = XilinxVC709MIGParams(address = AddressSet.misaligned(di.baseAddress, size)) + val mig = LazyModule(new XilinxVC709MIG(migParams)) + val ioNode = BundleBridgeSource(() => mig.module.io.cloneType) + val topIONode = shell { ioNode.makeSink() } + val ddrUI = shell { ClockSourceNode(freqMHz = 200) } + val areset = shell { ClockSinkNode(Seq(ClockSinkParameters())) } + areset := designInput.wrangler := ddrUI + + // since this uses a separate clk/rst need to put an async crossing + val asyncSink = LazyModule(new TLAsyncCrossingSink()) + val migClkRstNode = BundleBridgeSource(() => new Bundle { + val clock = Output(Clock()) + val reset = Output(Bool()) + }) + val topMigClkRstIONode = shell { migClkRstNode.makeSink() } + + def overlayOutput = DDROverlayOutput(ddr = mig.node) + def ioFactory = new XilinxVC709MIGPads(size) + + InModuleBody { + ioNode.bundle <> mig.module.io + + // setup async crossing + asyncSink.module.clock := migClkRstNode.bundle.clock + asyncSink.module.reset := migClkRstNode.bundle.reset + } + + shell { InModuleBody { + require (shell.sys_clock.get.isDefined, "Use of DDRVC709Overlay depends on SysClockVC709PlacedOverlay") + val (sys, _) = shell.sys_clock.get.get.overlayOutput.node.out(0) + val (ui, _) = ddrUI.out(0) + val (ar, _) = areset.in(0) + + // connect the async fifo sync to sys_clock + topMigClkRstIONode.bundle.clock := sys.clock + topMigClkRstIONode.bundle.reset := sys.reset + + val port = topIONode.bundle.port + io <> port + // This is modified for vc709 + ui.clock := port.ui_clk + ui.reset := !port.mmcm_locked || port.ui_clk_sync_rst + port.sys_clk_i := sys.clock.asUInt + port.sys_rst := sys.reset // pllReset + port.aresetn := !ar.reset + + // The pins for DDR3 on vc709 board are emitted in the following order: + // addr[0->15], ba[0-2], ras_n, cas_n, we_n, reset_n, ck_p, ck_n, cke, cs_n, odt, dm[0->7], dq[0->63], dqs_n[0->7], dqs_p[0->7] + val allddrpins = Seq( + "A20", "B19", "C20", "A19", "A17", "A16", "D20", "C18", "D17", "C19", "B21", "B17", "A15", "A21", "F17", "E17", // addr[0->15] + "D21", "C21", "D18", // ba[0->2] + "E20", "K17", "F20", "P18", "E19", "E18", "K19", "J17", "H20", // ras_n, cas_n, we_n, reset_n, ck_p, ck_n, cke, cs_n, odt + "M13", "K15", "F12", "A14", "C23", "D25", "C31", "F31", // dm [0->7] + "N14", "N13", "L14", "M14", "M12", "N15", "M11", "L12", "K14", "K13", "H13", "J13", "L16", "L15", "H14", "J15", // dq[0->15] + "E15", "E13", "F15", "E14", "G13", "G12", "F14", "G14", "B14", "C13", "B16", "D15", "D13", "E12", "C16", "D16", // dq[16->31] + "A24", "B23", "B27", "B26", "A22", "B22", "A25", "C24", "E24", "D23", "D26", "C25", "E23", "D22", "F22", "E22", // dq[32->47] + "A30", "D27", "A29", "C28", "D28", "B31", "A31", "A32", "E30", "F29", "F30", "F27", "C30", "E29", "F26", "D30", // dq[48->63] + "M16", "J12", "G16", "C14", "A27", "E25", "B29", "E28", // dqs_n[0->7] + "N16", "K12", "H16", "C15", "A26", "F25", "B28", "E27") // dqs_p[0->7] + + (IOPin.of(io) zip allddrpins) foreach { case (io, pin) => shell.xdc.addPackagePin(io, pin) } + } } + + shell.sdc.addGroup(pins = Seq(mig.island.module.blackbox.io.ui_clk)) +} +class DDR3VC709ShellPlacer(shell: VC709Shell, val shellInput: DDRShellInput)(implicit val valName: ValName) + extends DDRShellPlacer[VC709Shell] { + def place(designInput: DDRDesignInput) = new DDR3VC709PlacedOverlay(shell, valName.name, designInput, shellInput) +} + +class PCIeVC709PlacedOverlay(val shell: VC709Shell, name: String, val designInput: PCIeDesignInput, val shellInput: PCIeShellInput) + extends PCIePlacedOverlay[XilinxVC709PCIeX1Pads](name, designInput, shellInput) +{ + val pcie = LazyModule(new XilinxVC709PCIeX1) + val ioNode = BundleBridgeSource(() => pcie.module.io.cloneType) + val topIONode = shell { ioNode.makeSink() } + val axiClk = shell { ClockSourceNode(freqMHz = 125) } + val areset = shell { ClockSinkNode(Seq(ClockSinkParameters())) } + areset := designInput.wrangler := axiClk + + val slaveSide = TLIdentityNode() + pcie.crossTLIn(pcie.slave) := slaveSide + pcie.crossTLIn(pcie.control) := slaveSide + val node = NodeHandle(slaveSide, pcie.crossTLOut(pcie.master)) + val intnode = pcie.crossIntOut(pcie.intnode) + + def overlayOutput = PCIeOverlayOutput(node, intnode) + def ioFactory = new XilinxVC709PCIeX1Pads + + InModuleBody { ioNode.bundle <> pcie.module.io } + + shell { InModuleBody { + val (axi, _) = axiClk.out(0) + val (ar, _) = areset.in(0) + val port = topIONode.bundle.port + io <> port + axi.clock := port.axi_aclk // port.axi_aclk_out is changed to port.axi_aclk in 3.0 + // axi.reset := !port.mmcm_lock // mmcm_lock is removed in 3.0 + port.axi_aresetn := !ar.reset + port.axi_ctl_aresetn := !ar.reset + + shell.xdc.addPackagePin(io.REFCLK_rxp, "AB8") + shell.xdc.addPackagePin(io.REFCLK_rxn, "AB7") + + val txn = Seq("W1", "AA1", "AC1", "AE1", "AG1", "AH3", "AJ1", "AK3") /* [0-7] */ + val txp = Seq("W2", "AA2", "AC2", "AE2", "AG2", "AH4", "AJ2", "AK4") /* [0-7] */ + val rxn = Seq("Y3", "AA5", "AB3", "AC5", "AD3", "AE5", "AF3", "AG5") /* [0-7] */ + val rxp = Seq("Y4", "AA6", "AB4", "AC6", "AD4", "AE6", "AF4", "AG6") /* [0-7] */ + + def bind(io: Seq[IOPin], pad: Seq[String]) { + (io zip pad) foreach { case (io, pad) => shell.xdc.addPackagePin(io, pad) } + } + + bind(IOPin.of(io.pci_exp_rxp), rxp) + bind(IOPin.of(io.pci_exp_rxn), rxn) + bind(IOPin.of(io.pci_exp_txp), txp) + bind(IOPin.of(io.pci_exp_txn), txn) + + shell.sdc.addClock(s"${name}_ref_clk", io.REFCLK_rxp, 100) + } } + + shell.sdc.addGroup(clocks = Seq("txoutclk", "userclk1")) +} +class PCIeVC709ShellPlacer(val shell: VC709Shell, val shellInput: PCIeShellInput)(implicit val valName: ValName) + extends PCIeShellPlacer[VC709Shell] { + def place(designInput: PCIeDesignInput) = new PCIeVC709PlacedOverlay(shell, valName.name, designInput, shellInput) +} + +abstract class VC709Shell()(implicit p: Parameters) extends Series7Shell +{ + // PLL reset causes + val pllReset = InModuleBody { Wire(Bool()) } + + // Order matters; ddr depends on sys_clock + val sys_clock = Overlay(ClockInputOverlayKey, new SysClockVC709ShellPlacer(this, ClockInputShellInput())) + val led = Seq.tabulate(8)(i => Overlay(LEDOverlayKey, new LEDVC709ShellPlacer(this, LEDShellInput(color = "red", number = i))(valName = ValName(s"led_$i")))) + val switch = Seq.tabulate(8)(i => Overlay(SwitchOverlayKey, new SwitchVC709ShellPlacer(this, SwitchShellInput(number = i))(valName = ValName(s"switch_$i")))) + val button = Seq.tabulate(5)(i => Overlay(ButtonOverlayKey, new ButtonVC709ShellPlacer(this, ButtonShellInput(number = i))(valName = ValName(s"button_$i")))) + val chiplink = Overlay(ChipLinkOverlayKey, new ChipLinkVC709ShellPlacer(this, ChipLinkShellInput())) + val ddr0 = Overlay(DDROverlayKey, new DDR3VC709ShellPlacer(this, DDRShellInput())) +} + +class VC709BaseShell()(implicit p: Parameters) extends VC709Shell +{ + val topDesign = LazyModule(p(DesignKey)(designParameters)) + + // Place the sys_clock at the Shell if the user didn't ask for it + p(ClockInputOverlayKey).foreach(_.place(ClockInputDesignInput())) + + override lazy val module = new LazyRawModuleImp(this) { + val reset = IO(Input(Bool())) + xdc.addBoardPin(reset, "reset") + + val reset_ibuf = Module(new IBUF) + reset_ibuf.io.I := reset + + val sysclk: Clock = sys_clock.get() match { + case Some(x: SysClockVC709PlacedOverlay) => x.clock + } + val powerOnReset = PowerOnResetFPGAOnly(sysclk) + sdc.addAsyncPath(Seq(powerOnReset)) + + val ereset: Bool = chiplink.get() match { + case Some(x: ChipLinkVC709PlacedOverlay) => !x.ereset_n + case _ => false.B + } + pllReset := + reset_ibuf.io.O || powerOnReset || false.B + } +} + +class VC709PCIeShell()(implicit p: Parameters) extends VC709Shell +{ + val pcie = Overlay(PCIeOverlayKey, new PCIeVC709ShellPlacer(this, PCIeShellInput())) + val topDesign = LazyModule(p(DesignKey)(designParameters)) + + // Place the sys_clock at the Shell if the user didn't ask for it + p(ClockInputOverlayKey).foreach(_.place(ClockInputDesignInput())) + + override lazy val module = new LazyRawModuleImp(this) { + val reset = IO(Input(Bool())) + xdc.addBoardPin(reset, "reset") + + val reset_ibuf = Module(new IBUF) + reset_ibuf.io.I := reset + val sysclk: Clock = sys_clock.get() match { + case Some(x: SysClockVC709PlacedOverlay) => x.clock + } + val powerOnReset = PowerOnResetFPGAOnly(sysclk) + sdc.addAsyncPath(Seq(powerOnReset)) + val ereset: Bool = chiplink.get() match { + case Some(x: ChipLinkVCU118PlacedOverlay) => !x.ereset_n + case _ => false.B + } + pllReset := + reset_ibuf.io.O || powerOnReset || false.B + } +} diff --git a/xilinx/vc709/constraints/vc709-master.xdc b/xilinx/vc709/constraints/vc709-master.xdc new file mode 100644 index 00000000..cdbe7437 --- /dev/null +++ b/xilinx/vc709/constraints/vc709-master.xdc @@ -0,0 +1,10 @@ +#-------------- MCS Generation ---------------------- +set_property CFGBVS GND [current_design] +set_property CONFIG_VOLTAGE 1.8 [current_design] + +set_property EXTRACT_ENABLE YES [get_cells dut_/spi_0_1/mac/phy/txd_reg*] +set_property EXTRACT_ENABLE YES [get_cells dut_/spi_0_1/mac/phy/sck_reg] + + + + diff --git a/xilinx/vc709/constraints/vc709mig4gb.ucf b/xilinx/vc709/constraints/vc709mig4gb.ucf new file mode 100644 index 00000000..c3dbb407 --- /dev/null +++ b/xilinx/vc709/constraints/vc709mig4gb.ucf @@ -0,0 +1,116 @@ +NET "ddr3_dq[0]" LOC = "N14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[1]" LOC = "N13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[2]" LOC = "L14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[3]" LOC = "M14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[4]" LOC = "M12" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[5]" LOC = "N15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[6]" LOC = "M11" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[7]" LOC = "L12" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[8]" LOC = "K14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[9]" LOC = "K13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[10]" LOC = "H13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[11]" LOC = "J13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[12]" LOC = "L16" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[13]" LOC = "L15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[14]" LOC = "H14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[15]" LOC = "J15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[16]" LOC = "E15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[17]" LOC = "E13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[18]" LOC = "F15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[19]" LOC = "E14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[20]" LOC = "G13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[21]" LOC = "G12" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[22]" LOC = "F14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[23]" LOC = "G14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[24]" LOC = "B14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[25]" LOC = "C13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[26]" LOC = "B16" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[27]" LOC = "D15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[28]" LOC = "D13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[29]" LOC = "E12" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[30]" LOC = "C16" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[31]" LOC = "D16" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[32]" LOC = "A24" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[33]" LOC = "B23" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[34]" LOC = "B27" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[35]" LOC = "B26" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[36]" LOC = "A22" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[37]" LOC = "B22" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[38]" LOC = "A25" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[39]" LOC = "C24" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[40]" LOC = "E24" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[41]" LOC = "D23" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[42]" LOC = "D26" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[43]" LOC = "C25" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[44]" LOC = "E23" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[45]" LOC = "D22" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[46]" LOC = "F22" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[47]" LOC = "E22" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[48]" LOC = "A30" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[49]" LOC = "D27" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[50]" LOC = "A29" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[51]" LOC = "C28" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[52]" LOC = "D28" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[53]" LOC = "B31" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[54]" LOC = "A31" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[55]" LOC = "A32" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[56]" LOC = "E30" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[57]" LOC = "F29" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[58]" LOC = "F30" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[59]" LOC = "F27" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[60]" LOC = "C30" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[61]" LOC = "E29" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[62]" LOC = "F26" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[63]" LOC = "D30" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dm[0]" LOC = "M13" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_dm[1]" LOC = "K15" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_dm[2]" LOC = "F12" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_dm[3]" LOC = "A14" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_dm[4]" LOC = "C23" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_dm[5]" LOC = "D25" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_dm[6]" LOC = "C31" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_dm[7]" LOC = "F31" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_p[0]" LOC = "N16" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_n[0]" LOC = "M16" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_p[1]" LOC = "K12" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_n[1]" LOC = "J12" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_p[2]" LOC = "H16" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_n[2]" LOC = "G16" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_p[3]" LOC = "C15" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_n[3]" LOC = "C14" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_p[4]" LOC = "A26" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_n[4]" LOC = "A27" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_p[5]" LOC = "F25" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_n[5]" LOC = "E25" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_p[6]" LOC = "B28" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_n[6]" LOC = "B29" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_p[7]" LOC = "E27" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_n[7]" LOC = "E28" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_addr[15]" LOC = "E17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[14]" LOC = "F17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[13]" LOC = "A21" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[12]" LOC = "A15" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[11]" LOC = "B17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[10]" LOC = "B21" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[9]" LOC = "C19" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[8]" LOC = "D17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[7]" LOC = "C18" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[6]" LOC = "D20" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[5]" LOC = "A16" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[4]" LOC = "A17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[3]" LOC = "A19" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[2]" LOC = "C20" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[1]" LOC = "B19" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[0]" LOC = "A20" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_ba[2]" LOC = "D18" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_ba[1]" LOC = "C21" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_ba[0]" LOC = "D21" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_ck_p[0]" LOC = "E19" | IOSTANDARD = DIFF_SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_ck_n[0]" LOC = "E18" | IOSTANDARD = DIFF_SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_ras_n" LOC = "E20" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_cas_n" LOC = "K17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_we_n" LOC = "F20" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_reset_n" LOC = "P18" | IOSTANDARD = LVCMOS15 | VCCAUX_IO = HIGH ; +NET "ddr3_cke[0]" LOC = "K19" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_odt[0]" LOC = "H20" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_cs_n[0]" LOC = "J17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; diff --git a/xilinx/vc709/constraints/vc709mig8gb-C0.ucf b/xilinx/vc709/constraints/vc709mig8gb-C0.ucf new file mode 100644 index 00000000..c3dbb407 --- /dev/null +++ b/xilinx/vc709/constraints/vc709mig8gb-C0.ucf @@ -0,0 +1,116 @@ +NET "ddr3_dq[0]" LOC = "N14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[1]" LOC = "N13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[2]" LOC = "L14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[3]" LOC = "M14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[4]" LOC = "M12" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[5]" LOC = "N15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[6]" LOC = "M11" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[7]" LOC = "L12" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[8]" LOC = "K14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[9]" LOC = "K13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[10]" LOC = "H13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[11]" LOC = "J13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[12]" LOC = "L16" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[13]" LOC = "L15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[14]" LOC = "H14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[15]" LOC = "J15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[16]" LOC = "E15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[17]" LOC = "E13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[18]" LOC = "F15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[19]" LOC = "E14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[20]" LOC = "G13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[21]" LOC = "G12" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[22]" LOC = "F14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[23]" LOC = "G14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[24]" LOC = "B14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[25]" LOC = "C13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[26]" LOC = "B16" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[27]" LOC = "D15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[28]" LOC = "D13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[29]" LOC = "E12" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[30]" LOC = "C16" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[31]" LOC = "D16" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[32]" LOC = "A24" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[33]" LOC = "B23" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[34]" LOC = "B27" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[35]" LOC = "B26" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[36]" LOC = "A22" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[37]" LOC = "B22" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[38]" LOC = "A25" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[39]" LOC = "C24" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[40]" LOC = "E24" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[41]" LOC = "D23" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[42]" LOC = "D26" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[43]" LOC = "C25" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[44]" LOC = "E23" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[45]" LOC = "D22" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[46]" LOC = "F22" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[47]" LOC = "E22" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[48]" LOC = "A30" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[49]" LOC = "D27" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[50]" LOC = "A29" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[51]" LOC = "C28" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[52]" LOC = "D28" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[53]" LOC = "B31" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[54]" LOC = "A31" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[55]" LOC = "A32" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[56]" LOC = "E30" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[57]" LOC = "F29" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[58]" LOC = "F30" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[59]" LOC = "F27" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[60]" LOC = "C30" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[61]" LOC = "E29" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[62]" LOC = "F26" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[63]" LOC = "D30" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dm[0]" LOC = "M13" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_dm[1]" LOC = "K15" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_dm[2]" LOC = "F12" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_dm[3]" LOC = "A14" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_dm[4]" LOC = "C23" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_dm[5]" LOC = "D25" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_dm[6]" LOC = "C31" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_dm[7]" LOC = "F31" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_p[0]" LOC = "N16" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_n[0]" LOC = "M16" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_p[1]" LOC = "K12" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_n[1]" LOC = "J12" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_p[2]" LOC = "H16" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_n[2]" LOC = "G16" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_p[3]" LOC = "C15" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_n[3]" LOC = "C14" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_p[4]" LOC = "A26" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_n[4]" LOC = "A27" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_p[5]" LOC = "F25" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_n[5]" LOC = "E25" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_p[6]" LOC = "B28" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_n[6]" LOC = "B29" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_p[7]" LOC = "E27" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_n[7]" LOC = "E28" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_addr[15]" LOC = "E17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[14]" LOC = "F17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[13]" LOC = "A21" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[12]" LOC = "A15" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[11]" LOC = "B17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[10]" LOC = "B21" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[9]" LOC = "C19" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[8]" LOC = "D17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[7]" LOC = "C18" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[6]" LOC = "D20" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[5]" LOC = "A16" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[4]" LOC = "A17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[3]" LOC = "A19" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[2]" LOC = "C20" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[1]" LOC = "B19" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[0]" LOC = "A20" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_ba[2]" LOC = "D18" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_ba[1]" LOC = "C21" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_ba[0]" LOC = "D21" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_ck_p[0]" LOC = "E19" | IOSTANDARD = DIFF_SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_ck_n[0]" LOC = "E18" | IOSTANDARD = DIFF_SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_ras_n" LOC = "E20" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_cas_n" LOC = "K17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_we_n" LOC = "F20" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_reset_n" LOC = "P18" | IOSTANDARD = LVCMOS15 | VCCAUX_IO = HIGH ; +NET "ddr3_cke[0]" LOC = "K19" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_odt[0]" LOC = "H20" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_cs_n[0]" LOC = "J17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; diff --git a/xilinx/vc709/constraints/vc709mig8gb-C1.ucf b/xilinx/vc709/constraints/vc709mig8gb-C1.ucf new file mode 100644 index 00000000..bf01ab95 --- /dev/null +++ b/xilinx/vc709/constraints/vc709mig8gb-C1.ucf @@ -0,0 +1,116 @@ +NET "ddr3_dq[0]" LOC = "AN24" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[1]" LOC = "AM24" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[2]" LOC = "AR22" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[3]" LOC = "AR23" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[4]" LOC = "AN23" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[5]" LOC = "AM23" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[6]" LOC = "AN21" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[7]" LOC = "AP21" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[8]" LOC = "AK23" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[9]" LOC = "AJ23" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[10]" LOC = "AL21" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[11]" LOC = "AM21" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[12]" LOC = "AJ21" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[13]" LOC = "AJ20" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[14]" LOC = "AK20" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[15]" LOC = "AL20" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[16]" LOC = "AW22" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[17]" LOC = "AW23" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[18]" LOC = "AW21" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[19]" LOC = "AV21" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[20]" LOC = "AU23" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[21]" LOC = "AV23" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[22]" LOC = "AR24" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[23]" LOC = "AT24" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[24]" LOC = "BB24" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[25]" LOC = "BA24" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[26]" LOC = "AY23" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[27]" LOC = "AY24" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[28]" LOC = "AY25" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[29]" LOC = "BA25" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[30]" LOC = "BB21" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[31]" LOC = "BA21" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[32]" LOC = "AY14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[33]" LOC = "AW15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[34]" LOC = "BB14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[35]" LOC = "BB13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[36]" LOC = "AW12" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[37]" LOC = "AY13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[38]" LOC = "AY12" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[39]" LOC = "BA12" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[40]" LOC = "AU12" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[41]" LOC = "AU13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[42]" LOC = "AT12" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[43]" LOC = "AU14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[44]" LOC = "AV13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[45]" LOC = "AW13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[46]" LOC = "AT15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[47]" LOC = "AR15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[48]" LOC = "AL15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[49]" LOC = "AJ15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[50]" LOC = "AK14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[51]" LOC = "AJ12" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[52]" LOC = "AJ16" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[53]" LOC = "AL16" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[54]" LOC = "AJ13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[55]" LOC = "AK13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[56]" LOC = "AR14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[57]" LOC = "AT14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[58]" LOC = "AM12" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[59]" LOC = "AP11" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[60]" LOC = "AM13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[61]" LOC = "AN13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[62]" LOC = "AM11" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[63]" LOC = "AN11" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dm[0]" LOC = "AT22" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_dm[1]" LOC = "AL22" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_dm[2]" LOC = "AU24" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_dm[3]" LOC = "BB23" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_dm[4]" LOC = "BB12" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_dm[5]" LOC = "AV15" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_dm[6]" LOC = "AK12" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_dm[7]" LOC = "AP13" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_p[0]" LOC = "AP23" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_n[0]" LOC = "AP22" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_p[1]" LOC = "AJ22" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_n[1]" LOC = "AK22" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_p[2]" LOC = "AT21" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_n[2]" LOC = "AU21" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_p[3]" LOC = "BA22" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_n[3]" LOC = "BB22" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_p[4]" LOC = "BA15" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_n[4]" LOC = "BA14" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_p[5]" LOC = "AP12" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_n[5]" LOC = "AR12" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_p[6]" LOC = "AK15" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_n[6]" LOC = "AL14" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_p[7]" LOC = "AN15" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_n[7]" LOC = "AN14" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_addr[15]" LOC = "AL19" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[14]" LOC = "AM19" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[13]" LOC = "AK17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[12]" LOC = "AL17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[11]" LOC = "AM18" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[10]" LOC = "AM17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[9]" LOC = "AK19" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[8]" LOC = "AK18" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[7]" LOC = "AM16" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[6]" LOC = "AN16" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[5]" LOC = "AJ18" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[4]" LOC = "AP18" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[3]" LOC = "AP17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[2]" LOC = "AP20" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[1]" LOC = "AR19" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[0]" LOC = "AN19" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_ba[2]" LOC = "AN18" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_ba[1]" LOC = "AR18" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_ba[0]" LOC = "AR17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_ck_p[0]" LOC = "AT17" | IOSTANDARD = DIFF_SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_ck_n[0]" LOC = "AU17" | IOSTANDARD = DIFF_SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_ras_n" LOC = "AV19" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_cas_n" LOC = "AT20" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_we_n" LOC = "AU19" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_reset_n" LOC = "BB19" | IOSTANDARD = LVCMOS15 | VCCAUX_IO = HIGH ; +NET "ddr3_cke[0]" LOC = "AW17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_odt[0]" LOC = "AT16" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_cs_n[0]" LOC = "AV16" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; diff --git a/xilinx/vc709/constraints/vc709mig8gb.ucf b/xilinx/vc709/constraints/vc709mig8gb.ucf new file mode 100644 index 00000000..bf01ab95 --- /dev/null +++ b/xilinx/vc709/constraints/vc709mig8gb.ucf @@ -0,0 +1,116 @@ +NET "ddr3_dq[0]" LOC = "AN24" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[1]" LOC = "AM24" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[2]" LOC = "AR22" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[3]" LOC = "AR23" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[4]" LOC = "AN23" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[5]" LOC = "AM23" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[6]" LOC = "AN21" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[7]" LOC = "AP21" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[8]" LOC = "AK23" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[9]" LOC = "AJ23" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[10]" LOC = "AL21" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[11]" LOC = "AM21" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[12]" LOC = "AJ21" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[13]" LOC = "AJ20" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[14]" LOC = "AK20" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[15]" LOC = "AL20" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[16]" LOC = "AW22" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[17]" LOC = "AW23" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[18]" LOC = "AW21" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[19]" LOC = "AV21" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[20]" LOC = "AU23" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[21]" LOC = "AV23" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[22]" LOC = "AR24" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[23]" LOC = "AT24" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[24]" LOC = "BB24" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[25]" LOC = "BA24" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[26]" LOC = "AY23" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[27]" LOC = "AY24" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[28]" LOC = "AY25" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[29]" LOC = "BA25" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[30]" LOC = "BB21" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[31]" LOC = "BA21" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[32]" LOC = "AY14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[33]" LOC = "AW15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[34]" LOC = "BB14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[35]" LOC = "BB13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[36]" LOC = "AW12" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[37]" LOC = "AY13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[38]" LOC = "AY12" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[39]" LOC = "BA12" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[40]" LOC = "AU12" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[41]" LOC = "AU13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[42]" LOC = "AT12" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[43]" LOC = "AU14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[44]" LOC = "AV13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[45]" LOC = "AW13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[46]" LOC = "AT15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[47]" LOC = "AR15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[48]" LOC = "AL15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[49]" LOC = "AJ15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[50]" LOC = "AK14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[51]" LOC = "AJ12" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[52]" LOC = "AJ16" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[53]" LOC = "AL16" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[54]" LOC = "AJ13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[55]" LOC = "AK13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[56]" LOC = "AR14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[57]" LOC = "AT14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[58]" LOC = "AM12" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[59]" LOC = "AP11" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[60]" LOC = "AM13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[61]" LOC = "AN13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[62]" LOC = "AM11" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dq[63]" LOC = "AN11" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dm[0]" LOC = "AT22" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_dm[1]" LOC = "AL22" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_dm[2]" LOC = "AU24" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_dm[3]" LOC = "BB23" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_dm[4]" LOC = "BB12" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_dm[5]" LOC = "AV15" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_dm[6]" LOC = "AK12" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_dm[7]" LOC = "AP13" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_p[0]" LOC = "AP23" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_n[0]" LOC = "AP22" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_p[1]" LOC = "AJ22" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_n[1]" LOC = "AK22" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_p[2]" LOC = "AT21" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_n[2]" LOC = "AU21" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_p[3]" LOC = "BA22" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_n[3]" LOC = "BB22" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_p[4]" LOC = "BA15" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_n[4]" LOC = "BA14" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_p[5]" LOC = "AP12" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_n[5]" LOC = "AR12" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_p[6]" LOC = "AK15" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_n[6]" LOC = "AL14" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_p[7]" LOC = "AN15" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_dqs_n[7]" LOC = "AN14" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; +NET "ddr3_addr[15]" LOC = "AL19" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[14]" LOC = "AM19" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[13]" LOC = "AK17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[12]" LOC = "AL17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[11]" LOC = "AM18" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[10]" LOC = "AM17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[9]" LOC = "AK19" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[8]" LOC = "AK18" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[7]" LOC = "AM16" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[6]" LOC = "AN16" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[5]" LOC = "AJ18" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[4]" LOC = "AP18" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[3]" LOC = "AP17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[2]" LOC = "AP20" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[1]" LOC = "AR19" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_addr[0]" LOC = "AN19" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_ba[2]" LOC = "AN18" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_ba[1]" LOC = "AR18" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_ba[0]" LOC = "AR17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_ck_p[0]" LOC = "AT17" | IOSTANDARD = DIFF_SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_ck_n[0]" LOC = "AU17" | IOSTANDARD = DIFF_SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_ras_n" LOC = "AV19" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_cas_n" LOC = "AT20" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_we_n" LOC = "AU19" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_reset_n" LOC = "BB19" | IOSTANDARD = LVCMOS15 | VCCAUX_IO = HIGH ; +NET "ddr3_cke[0]" LOC = "AW17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_odt[0]" LOC = "AT16" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; +NET "ddr3_cs_n[0]" LOC = "AV16" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; diff --git a/xilinx/vc709/tcl/board.tcl b/xilinx/vc709/tcl/board.tcl new file mode 100644 index 00000000..8637a367 --- /dev/null +++ b/xilinx/vc709/tcl/board.tcl @@ -0,0 +1,4 @@ +# See LICENSE for license details. +set name {vc709} +set part_fpga {xc7vx690tffg1761-2} +set part_board {xilinx.com:vc709:part0:1.8} diff --git a/xilinx/vc709/tcl/clocks.tcl b/xilinx/vc709/tcl/clocks.tcl new file mode 100644 index 00000000..69014fcf --- /dev/null +++ b/xilinx/vc709/tcl/clocks.tcl @@ -0,0 +1,50 @@ +if { [llength [get_ports -quiet chiplink_b2c_clk]] > 0 } { + create_clock -name chiplink_b2c_clock -period 10 [get_ports chiplink_b2c_clk] + create_generated_clock -name {chiplink_c2b_clock} \ + -divide_by 1 \ + -source [ get_pins { vc709_sys_clock_mmcm0/inst/mmcm_adv_inst/CLKOUT6 } ] \ + [ get_ports { chiplink_c2b_clk } ] + + # RX side: want to latch almost anywhere except on the rising edge of the clock + # The data signals coming from Aloe have: clock - 1.2 <= transition <= clock + 0.8 + # Let's add 0.6ns of safety for trace jitter+skew on both sides: + # min = hold = - 1.2 - 0.6 + # max = period - setup = 0.8 + 0.6 + set_input_delay -min -1.8 -clock {chiplink_b2c_clock} [ get_ports { chiplink_b2c_data* chiplink_b2c_rst chiplink_b2c_send } ] + set_input_delay -max 1.4 -clock {chiplink_b2c_clock} [ get_ports { chiplink_b2c_data* chiplink_b2c_rst chiplink_b2c_send } ] + + # TX side: want to transition almost anywhere except on the rising edge of the clock + # The data signals going to Aloe must have: clock - 1.85 <= NO transition <= clock + 0.65 + # Let's add 1ns of safey for trace jitter+skew on both sides: + # min = -hold = -0.65 - 0.6 + # max = setup = 1.85 + 0.6 + set_output_delay -min -1.25 -clock {chiplink_c2b_clock} [ get_ports { chiplink_c2b_data* chiplink_c2b_rst chiplink_c2b_send } ] + set_output_delay -max 2.45 -clock {chiplink_c2b_clock} [ get_ports { chiplink_c2b_data* chiplink_c2b_rst chiplink_c2b_send } ] +} + +set group_mem [get_clocks -quiet {clk_pll_i}] +set group_sys [get_clocks -quiet {sys_diff_clk \ + clk_out*_vc709_sys_clock_mmcm1 \ + clk_out*_vc709_sys_clock_mmcm2 \ + chiplink_c2b_clock}] +set group_cl [get_clocks -quiet {chiplink_b2c_clock \ + clk_out*_vc709_sys_clock_mmcm3}] +set group_pci [get_clocks -quiet {userclk1 txoutclk}] + +set group_jtag [get_clocks -quiet {JTCK}] + +puts "group_mem: $group_mem" +puts "group_sys: $group_sys" +puts "group_pci: $group_pci" +puts "group_cl: $group_cl" +puts "group_jtag: $group_jtag" + +set groups [list] +if { [llength $group_mem] > 0 } { lappend groups -group $group_mem } +if { [llength $group_sys] > 0 } { lappend groups -group $group_sys } +if { [llength $group_pci] > 0 } { lappend groups -group $group_pci } +if { [llength $group_cl] > 0 } { lappend groups -group $group_cl } +if { [llength $group_jtag] > 0 } { lappend groups -group $group_jtag } + +puts "set_clock_groups -asynchronous $groups" +set_clock_groups -asynchronous {*}$groups diff --git a/xilinx/vc709/tcl/ios.tcl b/xilinx/vc709/tcl/ios.tcl new file mode 100644 index 00000000..c3b959b6 --- /dev/null +++ b/xilinx/vc709/tcl/ios.tcl @@ -0,0 +1,76 @@ +#---------------Physical Constraints----------------- + +#get_port_part_pins +#clk_n clk_p dip_switches_tri_i_0 dip_switches_tri_i_1 dip_switches_tri_i_2 dip_switches_tri_i_3 dip_switches_tri_i_4 dip_switches_tri_i_5 dip_switches_tri_i_6 dip_switches_tri_i_7 iic_main_scl_i iic_main_sda_i lcd_7bits_tri_o_0 lcd_7bits_tri_o_1 lcd_7bits_tri_o_2 lcd_7bits_tri_o_3 lcd_7bits_tri_o_4 lcd_7bits_tri_o_5 lcd_7bits_tri_o_6 leds_8bits_tri_o_0 leds_8bits_tri_o_1 leds_8bits_tri_o_2 leds_8bits_tri_o_3 leds_8bits_tri_o_4 leds_8bits_tri_o_5 leds_8bits_tri_o_6 leds_8bits_tri_o_7 linear_flash_addr_1 linear_flash_addr_10 linear_flash_addr_11 linear_flash_addr_12 linear_flash_addr_13 linear_flash_addr_14 linear_flash_addr_15 linear_flash_addr_16 linear_flash_addr_17 linear_flash_addr_18 linear_flash_addr_19 linear_flash_addr_2 linear_flash_addr_20 linear_flash_addr_21 linear_flash_addr_22 linear_flash_addr_23 linear_flash_addr_24 linear_flash_addr_25 linear_flash_addr_26 linear_flash_addr_3 linear_flash_addr_4 linear_flash_addr_5 linear_flash_addr_6 linear_flash_addr_7 linear_flash_addr_8 linear_flash_addr_9 linear_flash_adv_ldn linear_flash_ce_n linear_flash_dq_i_0 linear_flash_dq_i_1 linear_flash_dq_i_10 linear_flash_dq_i_11 linear_flash_dq_i_12 linear_flash_dq_i_13 linear_flash_dq_i_14 linear_flash_dq_i_15 linear_flash_dq_i_2 linear_flash_dq_i_3 linear_flash_dq_i_4 linear_flash_dq_i_5 linear_flash_dq_i_6 linear_flash_dq_i_7 linear_flash_dq_i_8 linear_flash_dq_i_9 linear_flash_oen linear_flash_wen mdc mdio_i phy_rst_out push_buttons_5bits_tri_i_0 push_buttons_5bits_tri_i_1 push_buttons_5bits_tri_i_2 push_buttons_5bits_tri_i_3 push_buttons_5bits_tri_i_4 reset rotary_inca_push_incb_tri_i_0 rotary_inca_push_incb_tri_i_1 rotary_inca_push_incb_tri_i_2 rs232_uart_rxd rs232_uart_txd sfp_rxn sfp_rxp sfp_sgmii_txn sfp_sgmii_txp sgmii_mgt_clkn sgmii_mgt_clkp sgmii_rxn sgmii_rxp sgmii_txn sgmii_txp sma_lvds_rxn sma_lvds_rxp sma_lvds_txn sma_lvds_txp sma_mgt_clkn sma_mgt_clkp sma_sfp_rxn sma_sfp_rxp sma_sfp_txn sma_sfp_txp + +set_property BOARD_PIN {clk_p} [get_ports sys_diff_clock_clk_p] +set_property BOARD_PIN {clk_n} [get_ports sys_diff_clock_clk_n] +set_property BOARD_PIN {reset} [get_ports reset] + +create_clock -name sys_diff_clk -period 5.0 [get_ports sys_diff_clock_clk_p] +set_input_jitter [get_clocks -of_objects [get_ports sys_diff_clock_clk_p]] 0.5 + +## LED +set_property BOARD_PIN {leds_8bits_tri_o_0} [get_ports led_0] +set_property BOARD_PIN {leds_8bits_tri_o_1} [get_ports led_1] +set_property BOARD_PIN {leds_8bits_tri_o_2} [get_ports led_2] +set_property BOARD_PIN {leds_8bits_tri_o_3} [get_ports led_3] +set_property BOARD_PIN {leds_8bits_tri_o_4} [get_ports led_4] +set_property BOARD_PIN {leds_8bits_tri_o_5} [get_ports led_5] +set_property BOARD_PIN {leds_8bits_tri_o_6} [get_ports led_6] +set_property BOARD_PIN {leds_8bits_tri_o_7} [get_ports led_7] + +## BUTTON +set_property BOARD_PIN {push_buttons_5bits_tri_i_0} [get_ports btn_0] +set_property BOARD_PIN {push_buttons_5bits_tri_i_1} [get_ports btn_1] +set_property BOARD_PIN {push_buttons_5bits_tri_i_2} [get_ports btn_2] +set_property BOARD_PIN {push_buttons_5bits_tri_i_3} [get_ports btn_3] + +## SWITCH +set_property BOARD_PIN {dip_switches_tri_i_0} [get_ports sw_0] +set_property BOARD_PIN {dip_switches_tri_i_1} [get_ports sw_1] +set_property BOARD_PIN {dip_switches_tri_i_2} [get_ports sw_2] +set_property BOARD_PIN {dip_switches_tri_i_3} [get_ports sw_3] +set_property BOARD_PIN {dip_switches_tri_i_4} [get_ports sw_4] +set_property BOARD_PIN {dip_switches_tri_i_5} [get_ports sw_5] +set_property BOARD_PIN {dip_switches_tri_i_6} [get_ports sw_6] +set_property BOARD_PIN {dip_switches_tri_i_7} [get_ports sw_7] + +## UART +# RX +set_property PACKAGE_PIN AU33 [get_ports uart_rx] +set_property IOSTANDARD LVCMOS18 [get_ports uart_rx] +set_property IOB TRUE [get_cells -of_objects [all_fanout -flat -endpoints_only [get_ports uart_rx]]] +# CTSN +set_property PACKAGE_PIN AT32 [get_ports uart_ctsn] +set_property IOSTANDARD LVCMOS18 [get_ports uart_ctsn] +set_property IOB TRUE [get_ports uart_ctsn] +# TX +set_property PACKAGE_PIN AU36 [get_ports uart_tx] +set_property IOSTANDARD LVCMOS18 [get_ports uart_tx] +set_property IOB TRUE [get_cells -of_objects [all_fanin -flat -startpoints_only [get_ports uart_tx]]] +# RTSN +set_property PACKAGE_PIN AR34 [get_ports uart_rtsn] +set_property IOSTANDARD LVCMOS18 [get_ports uart_rtsn] +set_property IOB TRUE [get_ports uart_rtsn] + +## PCI Express +#FMC 1 refclk +set_property PACKAGE_PIN A10 [get_ports {pcie_REFCLK_rxp}] +set_property PACKAGE_PIN A9 [get_ports {pcie_REFCLK_rxn}] +create_clock -name pcie_ref_clk -period 10 [get_ports pcie_REFCLK_rxp] +set_input_jitter [get_clocks -of_objects [get_ports pcie_REFCLK_rxp]] 0.5 +#TX +set_property PACKAGE_PIN H4 [get_ports {pcie_pci_exp_txp}] +set_property PACKAGE_PIN H3 [get_ports {pcie_pci_exp_txn}] +#RX +set_property PACKAGE_PIN G6 [get_ports {pcie_pci_exp_rxp}] +set_property PACKAGE_PIN G5 [get_ports {pcie_pci_exp_rxn}] + +## SDIO +# set_property -dict { PACKAGE_PIN AN30 IOSTANDARD LVCMOS18 IOB TRUE } [get_ports {sdio_clk}] +# set_property -dict { PACKAGE_PIN AP30 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_cmd}] +# set_property -dict { PACKAGE_PIN AR30 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_dat[0]}] +# set_property -dict { PACKAGE_PIN AU31 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_dat[1]}] +# set_property -dict { PACKAGE_PIN AV31 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_dat[2]}] +# set_property -dict { PACKAGE_PIN AT30 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_dat[3]}] diff --git a/xilinx/vc709/vsrc/vc709reset.v b/xilinx/vc709/vsrc/vc709reset.v new file mode 100644 index 00000000..4e2cc021 --- /dev/null +++ b/xilinx/vc709/vsrc/vc709reset.v @@ -0,0 +1,78 @@ +// See LICENSE for license details. +`timescale 1ns/1ps +`default_nettype none +`define RESET_SYNC 4 +`define DEBOUNCE_BITS 8 + +module vc709reset( + // Asynchronous reset input, should be held high until + // all clocks are locked and power is stable. + input wire areset, + // Clock domains are brought up in increasing order + // All clocks are reset for at least 2^DEBOUNCE_BITS * period(clock1) + input wire clock1, + output wire reset1, + input wire clock2, + output wire reset2, + input wire clock3, + output wire reset3, + input wire clock4, + output wire reset4 +); + sifive_reset_hold hold_clock0(areset, clock1, reset1); + sifive_reset_sync sync_clock2(reset1, clock2, reset2); + sifive_reset_sync sync_clock3(reset2, clock3, reset3); + sifive_reset_sync sync_clock4(reset3, clock4, reset4); +endmodule + +// Assumes that areset is held for more than one clock +// Allows areset to be deasserted asynchronously +module sifive_reset_sync( + input wire areset, + input wire clock, + output wire reset +); + reg [`RESET_SYNC-1:0] gen_reset = {`RESET_SYNC{1'b1}}; + always @(posedge clock, posedge areset) begin + if (areset) begin + gen_reset <= {`RESET_SYNC{1'b1}}; + end else begin + gen_reset <= {1'b0,gen_reset[`RESET_SYNC-1:1]}; + end + end + assign reset = gen_reset[0]; +endmodule + +module sifive_reset_hold( + input wire areset, + input wire clock, + output wire reset +); + wire raw_reset; + reg [`RESET_SYNC-1:0] sync_reset = {`RESET_SYNC{1'b1}}; + reg [`DEBOUNCE_BITS:0] debounce_reset = {`DEBOUNCE_BITS{1'b1}}; + wire out_reset; + + // Captures reset even if clock is not running + sifive_reset_sync capture(areset, clock, raw_reset); + + // Remove any glitches due to runt areset + always @(posedge clock) begin + sync_reset <= {raw_reset,sync_reset[`RESET_SYNC-1:1]}; + end + + // Debounce the reset + assign out_reset = debounce_reset[`DEBOUNCE_BITS]; + always @(posedge clock) begin + if (sync_reset[0]) begin + debounce_reset <= {(`DEBOUNCE_BITS+1){1'b1}}; + end else begin + debounce_reset <= debounce_reset - out_reset; + end + end + + assign reset = out_reset; + +endmodule + +`default_nettype wire From 4c26de254dd6f6f06c8dfd845e273a060e5fc785 Mon Sep 17 00:00:00 2001 From: Benshan Mei Date: Tue, 2 Feb 2021 15:54:27 +0800 Subject: [PATCH 02/26] add support for vc709 --- src/main/scala/shell/xilinx/VC709NewShell.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/main/scala/shell/xilinx/VC709NewShell.scala b/src/main/scala/shell/xilinx/VC709NewShell.scala index 9d3a4185..287c4dfe 100644 --- a/src/main/scala/shell/xilinx/VC709NewShell.scala +++ b/src/main/scala/shell/xilinx/VC709NewShell.scala @@ -298,7 +298,7 @@ abstract class VC709Shell()(implicit p: Parameters) extends Series7Shell val switch = Seq.tabulate(8)(i => Overlay(SwitchOverlayKey, new SwitchVC709ShellPlacer(this, SwitchShellInput(number = i))(valName = ValName(s"switch_$i")))) val button = Seq.tabulate(5)(i => Overlay(ButtonOverlayKey, new ButtonVC709ShellPlacer(this, ButtonShellInput(number = i))(valName = ValName(s"button_$i")))) val chiplink = Overlay(ChipLinkOverlayKey, new ChipLinkVC709ShellPlacer(this, ChipLinkShellInput())) - val ddr0 = Overlay(DDROverlayKey, new DDR3VC709ShellPlacer(this, DDRShellInput())) + val ddr0 = Overlay(DDROverlayKey, new DDR3VC709ShellPlacer(this, DDRShellInput())) } class VC709BaseShell()(implicit p: Parameters) extends VC709Shell @@ -326,7 +326,7 @@ class VC709BaseShell()(implicit p: Parameters) extends VC709Shell case _ => false.B } pllReset := - reset_ibuf.io.O || powerOnReset || false.B + reset_ibuf.io.O || powerOnReset || ereset } } @@ -354,6 +354,6 @@ class VC709PCIeShell()(implicit p: Parameters) extends VC709Shell case _ => false.B } pllReset := - reset_ibuf.io.O || powerOnReset || false.B + reset_ibuf.io.O || powerOnReset || ereset } } From 9f2252dddfbed26c8672dc87d3e0acc9496bf529 Mon Sep 17 00:00:00 2001 From: Benshan Mei Date: Sat, 6 Feb 2021 12:32:00 +0800 Subject: [PATCH 03/26] support for two memory controllers modified: vc709mig.scala modified: vc709mig8g.scala modified: ../../../devices/xilinx/xilinxvc709mig/XilinxVC709MIG.scala modified: ../vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala modified: ../../../shell/DDROverlay.scala modified: ../../../shell/PCIeOverlay.scala modified: ../../../shell/xilinx/VC707NewShell.scala modified: ../../../shell/xilinx/VC709NewShell.scala modified: ../../../shell/xilinx/XilinxShell.scala modified: ../../../../../../xilinx/common/tcl/boards.tcl modified: ../../../../../../xilinx/common/tcl/vivado.tcl --- .../scala/ip/xilinx/vc709mig/vc709mig.scala | 242 +++++++++++++++++- .../scala/ip/xilinx/vc709mig/vc709mig8g.scala | 29 +-- 2 files changed, 244 insertions(+), 27 deletions(-) diff --git a/src/main/scala/ip/xilinx/vc709mig/vc709mig.scala b/src/main/scala/ip/xilinx/vc709mig/vc709mig.scala index 85dbf642..fe4f60d8 100644 --- a/src/main/scala/ip/xilinx/vc709mig/vc709mig.scala +++ b/src/main/scala/ip/xilinx/vc709mig/vc709mig.scala @@ -45,12 +45,27 @@ trait VC709MIGIOClocksReset extends Bundle { val sys_rst = Bool(INPUT) } +object vc709mig +{ + var vc709migNo = 0 + def alloc = { + vc709migNo += 1 + vc709migNo + } + def last = { + vc709mig.vc709migNo - 1 + } +} + //scalastyle:off //turn off linter: blackbox name must match verilog module class vc709mig(depth : BigInt)(implicit val p:Parameters) extends BlackBox { - require((depth<=0x100000000L),"vc709mig supports upto 4GB depth configuraton") - override def desiredName = "vc709mig4gb" + require((depth<=0x100000000L), "vc709mig supports upto 4GB depth configuraton") + require((vc709mig.alloc <= 2), "vc709mig supports upto two memory controllers") + + val index = vc709mig.last + override def desiredName = Seq("vc709mig_a", "vc709mig_b")(index) val io = new VC709MIGIODDR(depth) with VC709MIGIOClocksReset { // User interface signals @@ -104,19 +119,20 @@ class vc709mig(depth : BigInt)(implicit val p:Parameters) extends BlackBox val s_axi_rlast = Bool(OUTPUT) val s_axi_rvalid = Bool(OUTPUT) //misc - val device_temp = Bits(OUTPUT,12) + val device_temp_i = Bits(INPUT,12) + // val device_temp = Bits(OUTPUT,12) } - val vc709mig4gbprj = """ { + val vc709mig_a = """ { - vc709mig4gb + vc709mig_a 1 1 OFF 1024 ON - Enabled + Disabled xc7vx690t-ffg1761/-2 4.1 No Buffer @@ -311,14 +327,218 @@ class vc709mig(depth : BigInt)(implicit val p:Parameters) extends BlackBox }""" - val migprj = vc709mig4gbprj - val migprjname = """{/vc709mig4gb.prj}""" - val modulename = """vc709mig4gb""" + val vc709mig_b = """ { + + + vc709mig_b + 1 + 1 + OFF + 1024 + ON + Disabled + xc7vx690t-ffg1761/-2 + 4.1 + No Buffer + Use System Clock + ACTIVE HIGH + FALSE + 0 + 50 Ohms + 0 + + DDR3_SDRAM/SODIMMs/MT8KTF51264HZ-1G9 + 1250 + 2.0V + 4:1 + 200 + 0 + 800 + 1.000 + 1 + 1 + 1 + 1 + 64 + 1 + 1 + Disabled + Normal + 4 + FALSE + + 16 + 10 + 3 + 1.5V + BANK_ROW_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 11 + Normal + No + Slow Exit + Enable + RZQ/7 + Disable + Enable + RZQ/6 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 8 + Enabled + Normal + Dynamic ODT off + AXI + + RD_PRI_REG + 32 + 64 + 4 + 0 + + + + +}""" + + val migprj = Seq(vc709mig_a, vc709mig_b)(index) + val migprjname = Seq("{/vc709mig_a.prj}", "{/vc709mig_b.prj}")(index) + val modulename = Seq("vc709mig_a", "vc709mig_b")(index) ElaborationArtefacts.add( modulename++".vivado.tcl", - """set migprj """++migprj++""" - set migprjfile """++migprjname++""" + """set migprj """ ++ migprj ++ """ + set migprjfile """ ++ migprjname ++ """ set migprjfilepath $ipdir$migprjfile set fp [open $migprjfilepath w+] puts $fp $migprj diff --git a/src/main/scala/ip/xilinx/vc709mig/vc709mig8g.scala b/src/main/scala/ip/xilinx/vc709mig/vc709mig8g.scala index 404ac56d..306a74ac 100644 --- a/src/main/scala/ip/xilinx/vc709mig/vc709mig8g.scala +++ b/src/main/scala/ip/xilinx/vc709mig/vc709mig8g.scala @@ -11,7 +11,7 @@ import freechips.rocketchip.config._ // Black Box class VC709MIGIODDR(depth : BigInt) extends GenericParameterizedBundle(depth) { - require((depth<=0x200000000L),"VC709MIGIODDR supports upto 8GB depth configuraton") + require((depth==0x200000000L),"VC709MIGIODDR supports upto 8GB depth configuraton") // DDR3 SODIMM 0 val c0_ddr3_addr = Bits(OUTPUT,16) val c0_ddr3_ba = Bits(OUTPUT,3) @@ -29,7 +29,6 @@ class VC709MIGIODDR(depth : BigInt) extends GenericParameterizedBundle(depth) { val c0_ddr3_dq = Analog(64.W) val c0_ddr3_dqs_n = Analog(8.W) val c0_ddr3_dqs_p = Analog(8.W) - // DDR3 SODIMM 1 val c1_ddr3_addr = Bits(OUTPUT,16) val c1_ddr3_ba = Bits(OUTPUT,3) @@ -62,7 +61,6 @@ trait VC709MIGIOClocksReset extends Bundle { val c0_aresetn = Bool(INPUT) //misc val c0_init_calib_complete = Bool(OUTPUT) - // DDR3 SODIMM 1 //inputs //"NO_BUFFER" clock source (must be connected to IBUF outside of IP) @@ -142,15 +140,16 @@ class vc709mig(depth : BigInt)(implicit val p:Parameters) extends BlackBox //misc val c0_device_temp = Bits(OUTPUT,12) + //axi_s [DDR3 SODIMM 1] - // User interface signals + // User interface signals (DDR3 SODIMM 0) val c1_app_sr_req = Bool(INPUT) val c1_app_ref_req = Bool(INPUT) val c1_app_zq_req = Bool(INPUT) val c1_app_sr_active = Bool(OUTPUT) val c1_app_ref_ack = Bool(OUTPUT) val c1_app_zq_ack = Bool(OUTPUT) - + //slave interface write address ports val c1_s_axi_awid = Bits(INPUT,4) val c1_s_axi_awaddr = Bits(INPUT,32) @@ -390,11 +389,11 @@ class vc709mig(depth : BigInt)(implicit val p:Parameters) extends BlackBox Dynamic ODT off AXI - RD_PRI_REG - 32 - 64 - 4 - 0 + RD_PRI_REG + 32 + 64 + 4 + 0 @@ -580,19 +579,17 @@ class vc709mig(depth : BigInt)(implicit val p:Parameters) extends BlackBox }""" val migprj = vc709mig8gbprj - val migprjname = """{/vc709mig8gb.prj}""" - val modulename = """vc709mig8gb""" ElaborationArtefacts.add( - modulename++".vivado.tcl", + "vc709mig8gb.vivado.tcl", """set migprj """++migprj++""" - set migprjfile """++migprjname++""" + set migprjfile {/vc709mig8gb.prj} set migprjfilepath $ipdir$migprjfile set fp [open $migprjfilepath w+] puts $fp $migprj close $fp - create_ip -vendor xilinx.com -library ip -name mig_7series -module_name """ ++ modulename ++ """ -dir $ipdir -force - set_property CONFIG.XML_INPUT_FILE $migprjfilepath [get_ips """ ++ modulename ++ """] """ + create_ip -vendor xilinx.com -library ip -name mig_7series -module_name vc709mig8gb -dir $ipdir -force + set_property CONFIG.XML_INPUT_FILE $migprjfilepath [get_ips vc709mig8gb] """ ) } //scalastyle:on From f58eef33af63d30379768c2c031a62d37eb01a2d Mon Sep 17 00:00:00 2001 From: Benshan Mei Date: Sat, 6 Feb 2021 12:36:50 +0800 Subject: [PATCH 04/26] add support for PCIe and DDR3 in Xilinx vc709 --- .../xilinxvc709mig/XilinxVC709MIG.scala | 5 +- .../vc709axi_to_pcie_x1.scala | 4 +- src/main/scala/shell/DDROverlay.scala | 2 +- src/main/scala/shell/PCIeOverlay.scala | 5 +- .../scala/shell/xilinx/VC707NewShell.scala | 6 +- .../scala/shell/xilinx/VC709NewShell.scala | 196 ++++++------------ src/main/scala/shell/xilinx/XilinxShell.scala | 2 +- xilinx/common/tcl/boards.tcl | 1 + xilinx/common/tcl/vivado.tcl | 1 + 9 files changed, 81 insertions(+), 141 deletions(-) diff --git a/src/main/scala/devices/xilinx/xilinxvc709mig/XilinxVC709MIG.scala b/src/main/scala/devices/xilinx/xilinxvc709mig/XilinxVC709MIG.scala index c6ac2166..20a48f7d 100644 --- a/src/main/scala/devices/xilinx/xilinxvc709mig/XilinxVC709MIG.scala +++ b/src/main/scala/devices/xilinx/xilinxvc709mig/XilinxVC709MIG.scala @@ -28,7 +28,7 @@ class XilinxVC709MIGIsland(c : XilinxVC709MIGParams, val crossing: ClockCrossing require (ranges.size == 1, "DDR range must be contiguous") val offset = ranges.head.base val depth = ranges.head.size - require((depth<=0x200000000L),"vc709mig supports upto 8GB depth configuraton") + require((depth<=0x100000000L),"vc709mig supports upto 4GB depth configuraton") val device = new MemoryDevice val node = AXI4SlaveNode(Seq(AXI4SlavePortParameters( @@ -148,6 +148,7 @@ class XilinxVC709MIGIsland(c : XilinxVC709MIGParams, val crossing: ClockCrossing io.port.init_calib_complete := blackbox.io.init_calib_complete blackbox.io.sys_rst :=io.port.sys_rst + //mig.device_temp_i :- unconnected //mig.device_temp :- unconnceted } } @@ -157,7 +158,7 @@ class XilinxVC709MIG(c : XilinxVC709MIGParams, crossing: ClockCrossingType = Asy val depth = ranges.head.size val buffer = LazyModule(new TLBuffer) - val toaxi4 = LazyModule(new TLToAXI4(adapterName = Some("mem"), stripBits = 1)) + val toaxi4 = LazyModule(new TLToAXI4(adapterName = Some("mem"))) val indexer = LazyModule(new AXI4IdIndexer(idBits = 4)) val deint = LazyModule(new AXI4Deinterleaver(p(CacheBlockBytes))) val yank = LazyModule(new AXI4UserYanker) diff --git a/src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala b/src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala index 9839c344..8ed8393e 100644 --- a/src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala +++ b/src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala @@ -179,11 +179,11 @@ class VC709AXIToPCIeX1(implicit p:Parameters) extends LazyModule "#size-cells" -> ofInt(2), "#interrupt-cells" -> ofInt(1), "device_type" -> Seq(ResourceString("pci")), + "interrupt-map-mask" -> Seq(0, 0, 0, 7).flatMap(ofInt), + "interrupt-map" -> Seq(1, 2, 3, 4).flatMap(ofMap), "ranges" -> resources("ranges").map(x => (x: @unchecked) match { case Binding(_, ResourceAddress(address, perms)) => ResourceMapping(address, BigInt(0x02000000) << 64, perms) }), - "interrupt-map-mask" -> Seq(0, 0, 0, 7).flatMap(ofInt), - "interrupt-map" -> Seq(1, 2, 3, 4).flatMap(ofMap), "interrupt-controller" -> Seq(ResourceMap(labels = Seq(intc), value = Map( "interrupt-controller" -> Nil, "#address-cells" -> ofInt(0), diff --git a/src/main/scala/shell/DDROverlay.scala b/src/main/scala/shell/DDROverlay.scala index be0ed9e0..45019bbd 100644 --- a/src/main/scala/shell/DDROverlay.scala +++ b/src/main/scala/shell/DDROverlay.scala @@ -24,4 +24,4 @@ abstract class DDRPlacedOverlay[IO <: Data](val name: String, val di: DDRDesignI extends IOPlacedOverlay[IO, DDRDesignInput, DDRShellInput, DDROverlayOutput] { implicit val p = di.p -} +} \ No newline at end of file diff --git a/src/main/scala/shell/PCIeOverlay.scala b/src/main/scala/shell/PCIeOverlay.scala index 072104dd..37ea0356 100644 --- a/src/main/scala/shell/PCIeOverlay.scala +++ b/src/main/scala/shell/PCIeOverlay.scala @@ -8,6 +8,9 @@ import freechips.rocketchip.tilelink._ import freechips.rocketchip.interrupts._ import sifive.fpgashells.clocks._ +import sifive.fpgashells.devices.xilinx.xilinxvc709pciex1.{XilinxVC709PCIeX1Pads, XilinxVC709PCIeX1} +import sifive.fpgashells.shell.xilinx.{Series7Shell} + case class PCIeShellInput() case class PCIeDesignInput( wrangler: ClockAdapterNode, @@ -29,4 +32,4 @@ abstract class PCIePlacedOverlay[IO <: Data]( extends IOPlacedOverlay[IO, PCIeDesignInput, PCIeShellInput, PCIeOverlayOutput] { implicit val p = di.p -} +} \ No newline at end of file diff --git a/src/main/scala/shell/xilinx/VC707NewShell.scala b/src/main/scala/shell/xilinx/VC707NewShell.scala index dbe811af..64ef8310 100644 --- a/src/main/scala/shell/xilinx/VC707NewShell.scala +++ b/src/main/scala/shell/xilinx/VC707NewShell.scala @@ -217,15 +217,15 @@ class DDRVC707ShellPlacer(val shell: VC707Shell, val shellInput: DDRShellInput)( class PCIeVC707PlacedOverlay(val shell: VC707Shell, name: String, val designInput: PCIeDesignInput, val shellInput: PCIeShellInput) extends PCIePlacedOverlay[XilinxVC707PCIeX1Pads](name, designInput, shellInput) { - val pcie = LazyModule(new XilinxVC707PCIeX1) - val ioNode = BundleBridgeSource(() => pcie.module.io.cloneType) + val pcie = LazyModule(new XilinxVC707PCIeX1) + val ioNode = BundleBridgeSource(() => pcie.module.io.cloneType) val topIONode = shell { ioNode.makeSink() } val axiClk = shell { ClockSourceNode(freqMHz = 125) } val areset = shell { ClockSinkNode(Seq(ClockSinkParameters())) } areset := designInput.wrangler := axiClk val slaveSide = TLIdentityNode() - pcie.crossTLIn(pcie.slave) := slaveSide + pcie.crossTLIn(pcie.slave) := slaveSide pcie.crossTLIn(pcie.control) := slaveSide val node = NodeHandle(slaveSide, pcie.crossTLOut(pcie.master)) val intnode = pcie.crossIntOut(pcie.intnode) diff --git a/src/main/scala/shell/xilinx/VC709NewShell.scala b/src/main/scala/shell/xilinx/VC709NewShell.scala index 287c4dfe..96e870b7 100644 --- a/src/main/scala/shell/xilinx/VC709NewShell.scala +++ b/src/main/scala/shell/xilinx/VC709NewShell.scala @@ -14,28 +14,34 @@ import sifive.blocks.devices.chiplink._ import sifive.fpgashells.devices.xilinx.xilinxvc709mig._ import sifive.fpgashells.devices.xilinx.xilinxvc709pciex1._ -class SysClockVC709PlacedOverlay(val shell: VC709Shell, name: String, val designInput: ClockInputDesignInput, val shellInput: ClockInputShellInput) +class SysClockVC709PlacedOverlay(val shell: VC709ShellBasicOverlays, name: String, val designInput: ClockInputDesignInput, val shellInput: ClockInputShellInput) extends LVDSClockInputXilinxPlacedOverlay(name, designInput, shellInput) { val node = shell { ClockSourceNode(freqMHz = 200, jitterPS = 50)(ValName(name)) } shell { InModuleBody { + // sysclk_p, sysclk_n +// val packagePinsWithPackageIOs = Seq(("H19", IOPin(io.p)), +// ("G18", IOPin(io.n))) + +// packagePinsWithPackageIOs foreach { case (pin, io) => { +// shell.xdc.addPackagePin(io, pin) +// shell.xdc.addIOStandard(io, "DIFF_SSTL15") +// shell.xdc.addIOB(io) +// } } + shell.xdc.addBoardPin(io.p, "clk_p") shell.xdc.addBoardPin(io.n, "clk_n") - // shell.xdc.addPackagePin(io.p, "H19") - // shell.xdc.addPackagePin(io.n, "G18") - // shell.xdc.addIOStandard(io.p, "DIFF_SSTL15") - // shell.xdc.addIOStandard(io.n, "DIFF_SSTL15") } } } -class SysClockVC709ShellPlacer(shell: VC709Shell, val shellInput: ClockInputShellInput)(implicit val valName: ValName) - extends ClockInputShellPlacer[VC709Shell] +class SysClockVC709ShellPlacer(shell: VC709ShellBasicOverlays, val shellInput: ClockInputShellInput)(implicit val valName: ValName) + extends ClockInputShellPlacer[VC709ShellBasicOverlays] { def place(designInput: ClockInputDesignInput) = new SysClockVC709PlacedOverlay(shell, valName.name, designInput, shellInput) } -class UARTVC709PlacedOverlay(val shell: VC709Shell, name: String, val designInput: UARTDesignInput, val shellInput: UARTShellInput) +class UARTVC709PlacedOverlay(val shell: VC709ShellBasicOverlays, name: String, val designInput: UARTDesignInput, val shellInput: UARTShellInput) extends UARTXilinxPlacedOverlay(name, designInput, shellInput, true) { shell { InModuleBody { @@ -51,33 +57,33 @@ class UARTVC709PlacedOverlay(val shell: VC709Shell, name: String, val designInpu } } } } } -class UARTVC709ShellPlacer(val shell: VC709Shell, val shellInput: UARTShellInput)(implicit val valName: ValName) - extends UARTShellPlacer[VC709Shell] { +class UARTVC709ShellPlacer(val shell: VC709ShellBasicOverlays, val shellInput: UARTShellInput)(implicit val valName: ValName) + extends UARTShellPlacer[VC709ShellBasicOverlays] { def place(designInput: UARTDesignInput) = new UARTVC709PlacedOverlay(shell, valName.name, designInput, shellInput) } -class LEDVC709PlacedOverlay(val shell: VC709Shell, name: String, val designInput: LEDDesignInput, val shellInput: LEDShellInput) +class LEDVC709PlacedOverlay(val shell: VC709ShellBasicOverlays, name: String, val designInput: LEDDesignInput, val shellInput: LEDShellInput) extends LEDXilinxPlacedOverlay(name, designInput, shellInput, boardPin = Some(s"leds_8bits_tri_o_${shellInput.number}")) -class LEDVC709ShellPlacer(val shell: VC709Shell, val shellInput: LEDShellInput)(implicit val valName: ValName) - extends LEDShellPlacer[VC709Shell] { +class LEDVC709ShellPlacer(val shell: VC709ShellBasicOverlays, val shellInput: LEDShellInput)(implicit val valName: ValName) + extends LEDShellPlacer[VC709ShellBasicOverlays] { def place(designInput: LEDDesignInput) = new LEDVC709PlacedOverlay(shell, valName.name, designInput, shellInput) } -class SwitchVC709PlacedOverlay(val shell: VC709Shell, name: String, val designInput: SwitchDesignInput, val shellInput: SwitchShellInput) +class SwitchVC709PlacedOverlay(val shell: VC709ShellBasicOverlays, name: String, val designInput: SwitchDesignInput, val shellInput: SwitchShellInput) extends SwitchXilinxPlacedOverlay(name, designInput, shellInput, boardPin = Some(s"dip_switches_tri_i_${shellInput.number}")) -class SwitchVC709ShellPlacer(val shell: VC709Shell, val shellInput: SwitchShellInput)(implicit val valName: ValName) - extends SwitchShellPlacer[VC709Shell] { +class SwitchVC709ShellPlacer(val shell: VC709ShellBasicOverlays, val shellInput: SwitchShellInput)(implicit val valName: ValName) + extends SwitchShellPlacer[VC709ShellBasicOverlays] { def place(designInput: SwitchDesignInput) = new SwitchVC709PlacedOverlay(shell, valName.name, designInput, shellInput) } -class ButtonVC709PlacedOverlay(val shell: VC709Shell, name: String, val designInput: ButtonDesignInput, val shellInput: ButtonShellInput) +class ButtonVC709PlacedOverlay(val shell: VC709ShellBasicOverlays, name: String, val designInput: ButtonDesignInput, val shellInput: ButtonShellInput) extends ButtonXilinxPlacedOverlay(name, designInput, shellInput, boardPin = Some(s"push_buttons_5bits_tri_i_${shellInput.number}")) -class ButtonVC709ShellPlacer(val shell: VC709Shell, val shellInput: ButtonShellInput)(implicit val valName: ValName) - extends ButtonShellPlacer[VC709Shell] { +class ButtonVC709ShellPlacer(val shell: VC709ShellBasicOverlays, val shellInput: ButtonShellInput)(implicit val valName: ValName) + extends ButtonShellPlacer[VC709ShellBasicOverlays] { def place(designInput: ButtonDesignInput) = new ButtonVC709PlacedOverlay(shell, valName.name, designInput, shellInput) } -class ChipLinkVC709PlacedOverlay(val shell: VC709Shell, name: String, val designInput: ChipLinkDesignInput, val shellInput: ChipLinkShellInput) +class ChipLinkVC709PlacedOverlay(val shell: VC709ShellBasicOverlays, name: String, val designInput: ChipLinkDesignInput, val shellInput: ChipLinkShellInput) extends ChipLinkXilinxPlacedOverlay(name, designInput, shellInput, rxPhase=280, txPhase=220, rxMargin=0.3, txMargin=0.3) { val ereset_n = shell { InModuleBody { @@ -104,13 +110,13 @@ class ChipLinkVC709PlacedOverlay(val shell: VC709Shell, name: String, val design (IOPin.of(io.c2b) zip dir2) foreach { case (io, pin) => shell.xdc.addPackagePin(io, pin) } } } } -class ChipLinkVC709ShellPlacer(val shell: VC709Shell, val shellInput: ChipLinkShellInput)(implicit val valName: ValName) - extends ChipLinkShellPlacer[VC709Shell] { +class ChipLinkVC709ShellPlacer(val shell: VC709ShellBasicOverlays, val shellInput: ChipLinkShellInput)(implicit val valName: ValName) + extends ChipLinkShellPlacer[VC709ShellBasicOverlays] { def place(designInput: ChipLinkDesignInput) = new ChipLinkVC709PlacedOverlay(shell, valName.name, designInput, shellInput) } // TODO: JTAG is untested -class JTAGDebugVC709PlacedOverlay(val shell: VC709Shell, name: String, val designInput: JTAGDebugDesignInput, val shellInput: JTAGDebugShellInput) +class JTAGDebugVC709PlacedOverlay(val shell: VC709ShellBasicOverlays, name: String, val designInput: JTAGDebugDesignInput, val shellInput: JTAGDebugShellInput) extends JTAGDebugXilinxPlacedOverlay(name, designInput, shellInput) { shell { InModuleBody { @@ -148,63 +154,15 @@ class JTAGDebugVC709PlacedOverlay(val shell: VC709Shell, name: String, val desig } } } } } -class JTAGDebugVC709ShellPlacer(val shell: VC709Shell, val shellInput: JTAGDebugShellInput)(implicit val valName: ValName) - extends JTAGDebugShellPlacer[VC709Shell] { +class JTAGDebugVC709ShellPlacer(val shell: VC709ShellBasicOverlays, val shellInput: JTAGDebugShellInput)(implicit val valName: ValName) + extends JTAGDebugShellPlacer[VC709ShellBasicOverlays] { def place(designInput: JTAGDebugDesignInput) = new JTAGDebugVC709PlacedOverlay(shell, valName.name, designInput, shellInput) } -case object VC709DDR3Size extends Field[BigInt](0x100000000L) // 4GB -class DDR3VC709PlacedOverlay(val shell: VC709Shell, name: String, val designInput: DDRDesignInput, val shellInput: DDRShellInput) - extends DDRPlacedOverlay[XilinxVC709MIGPads](name, designInput, shellInput) +class DDR3VC709PlacedOverlay(val shell: VC709ShellBasicOverlays, name: String, val designInput: DDRDesignInput, val shellInput: DDRShellInput) + extends DDR3XilinxPlacedOverlay(shell, name, designInput, shellInput) { - val size = p(VC709DDR3Size) - - val migParams = XilinxVC709MIGParams(address = AddressSet.misaligned(di.baseAddress, size)) - val mig = LazyModule(new XilinxVC709MIG(migParams)) - val ioNode = BundleBridgeSource(() => mig.module.io.cloneType) - val topIONode = shell { ioNode.makeSink() } - val ddrUI = shell { ClockSourceNode(freqMHz = 200) } - val areset = shell { ClockSinkNode(Seq(ClockSinkParameters())) } - areset := designInput.wrangler := ddrUI - - // since this uses a separate clk/rst need to put an async crossing - val asyncSink = LazyModule(new TLAsyncCrossingSink()) - val migClkRstNode = BundleBridgeSource(() => new Bundle { - val clock = Output(Clock()) - val reset = Output(Bool()) - }) - val topMigClkRstIONode = shell { migClkRstNode.makeSink() } - - def overlayOutput = DDROverlayOutput(ddr = mig.node) - def ioFactory = new XilinxVC709MIGPads(size) - - InModuleBody { - ioNode.bundle <> mig.module.io - - // setup async crossing - asyncSink.module.clock := migClkRstNode.bundle.clock - asyncSink.module.reset := migClkRstNode.bundle.reset - } - shell { InModuleBody { - require (shell.sys_clock.get.isDefined, "Use of DDRVC709Overlay depends on SysClockVC709PlacedOverlay") - val (sys, _) = shell.sys_clock.get.get.overlayOutput.node.out(0) - val (ui, _) = ddrUI.out(0) - val (ar, _) = areset.in(0) - - // connect the async fifo sync to sys_clock - topMigClkRstIONode.bundle.clock := sys.clock - topMigClkRstIONode.bundle.reset := sys.reset - - val port = topIONode.bundle.port - io <> port - // This is modified for vc709 - ui.clock := port.ui_clk - ui.reset := !port.mmcm_locked || port.ui_clk_sync_rst - port.sys_clk_i := sys.clock.asUInt - port.sys_rst := sys.reset // pllReset - port.aresetn := !ar.reset - // The pins for DDR3 on vc709 board are emitted in the following order: // addr[0->15], ba[0-2], ras_n, cas_n, we_n, reset_n, ck_p, ck_n, cke, cs_n, odt, dm[0->7], dq[0->63], dqs_n[0->7], dqs_p[0->7] val allddrpins = Seq( @@ -219,59 +177,60 @@ class DDR3VC709PlacedOverlay(val shell: VC709Shell, name: String, val designInpu "M16", "J12", "G16", "C14", "A27", "E25", "B29", "E28", // dqs_n[0->7] "N16", "K12", "H16", "C15", "A26", "F25", "B28", "E27") // dqs_p[0->7] + IOPin.of(io).foreach { shell.xdc.addPackagePin(_, "") } (IOPin.of(io) zip allddrpins) foreach { case (io, pin) => shell.xdc.addPackagePin(io, pin) } } } - shell.sdc.addGroup(pins = Seq(mig.island.module.blackbox.io.ui_clk)) + shell.sdc.addGroup(clocks = Seq("ui_clk0"), pins = Seq(mig.island.module.blackbox.io.ui_clk)) } -class DDR3VC709ShellPlacer(shell: VC709Shell, val shellInput: DDRShellInput)(implicit val valName: ValName) - extends DDRShellPlacer[VC709Shell] { +class DDR3VC709ShellPlacer(shell: VC709ShellBasicOverlays, val shellInput: DDRShellInput)(implicit val valName: ValName) + extends DDRShellPlacer[VC709ShellBasicOverlays] { def place(designInput: DDRDesignInput) = new DDR3VC709PlacedOverlay(shell, valName.name, designInput, shellInput) } -class PCIeVC709PlacedOverlay(val shell: VC709Shell, name: String, val designInput: PCIeDesignInput, val shellInput: PCIeShellInput) +class PCIeVC709PlacedOverlay(val shell: VC709ShellBasicOverlays, name: String, val designInput: PCIeDesignInput, val shellInput: PCIeShellInput) extends PCIePlacedOverlay[XilinxVC709PCIeX1Pads](name, designInput, shellInput) { - val pcie = LazyModule(new XilinxVC709PCIeX1) - val ioNode = BundleBridgeSource(() => pcie.module.io.cloneType) - val topIONode = shell { ioNode.makeSink() } + val pcie = LazyModule(new XilinxVC709PCIeX1) + val bridge = BundleBridgeSource(() => pcie.module.io.cloneType) + val topBridge = shell { bridge.makeSink() } val axiClk = shell { ClockSourceNode(freqMHz = 125) } val areset = shell { ClockSinkNode(Seq(ClockSinkParameters())) } areset := designInput.wrangler := axiClk val slaveSide = TLIdentityNode() - pcie.crossTLIn(pcie.slave) := slaveSide + pcie.crossTLIn(pcie.slave) := slaveSide pcie.crossTLIn(pcie.control) := slaveSide val node = NodeHandle(slaveSide, pcie.crossTLOut(pcie.master)) - val intnode = pcie.crossIntOut(pcie.intnode) + val intNode = pcie.crossIntOut(pcie.intnode) - def overlayOutput = PCIeOverlayOutput(node, intnode) + def overlayOutput = PCIeOverlayOutput(node, intNode) def ioFactory = new XilinxVC709PCIeX1Pads - InModuleBody { ioNode.bundle <> pcie.module.io } + InModuleBody { bridge.bundle <> pcie.module.io } shell { InModuleBody { val (axi, _) = axiClk.out(0) val (ar, _) = areset.in(0) - val port = topIONode.bundle.port + val port = topBridge.bundle.port io <> port - axi.clock := port.axi_aclk // port.axi_aclk_out is changed to port.axi_aclk in 3.0 - // axi.reset := !port.mmcm_lock // mmcm_lock is removed in 3.0 + axi.clock := port.axi_aclk // port.axi_aclk_out is changed to port.axi_aclk in 3.0 + // axi.reset := !port.mmcm_lock // mmcm_lock is removed in 3.0 port.axi_aresetn := !ar.reset port.axi_ctl_aresetn := !ar.reset - shell.xdc.addPackagePin(io.REFCLK_rxp, "AB8") - shell.xdc.addPackagePin(io.REFCLK_rxn, "AB7") + def bind(io: Seq[IOPin], pad: Seq[String]) { + (io zip pad) foreach { case (io, pad) => shell.xdc.addPackagePin(io, pad) } + } val txn = Seq("W1", "AA1", "AC1", "AE1", "AG1", "AH3", "AJ1", "AK3") /* [0-7] */ val txp = Seq("W2", "AA2", "AC2", "AE2", "AG2", "AH4", "AJ2", "AK4") /* [0-7] */ val rxn = Seq("Y3", "AA5", "AB3", "AC5", "AD3", "AE5", "AF3", "AG5") /* [0-7] */ val rxp = Seq("Y4", "AA6", "AB4", "AC6", "AD4", "AE6", "AF4", "AG6") /* [0-7] */ - - def bind(io: Seq[IOPin], pad: Seq[String]) { - (io zip pad) foreach { case (io, pad) => shell.xdc.addPackagePin(io, pad) } - } - + + IOPin.of(io).foreach { shell.xdc.addPackagePin(_, "") } + bind(IOPin.of(io.REFCLK_rxp), Seq("AB8")) + bind(IOPin.of(io.REFCLK_rxn), Seq("AB7")) bind(IOPin.of(io.pci_exp_rxp), rxp) bind(IOPin.of(io.pci_exp_rxn), rxn) bind(IOPin.of(io.pci_exp_txp), txp) @@ -282,26 +241,29 @@ class PCIeVC709PlacedOverlay(val shell: VC709Shell, name: String, val designInpu shell.sdc.addGroup(clocks = Seq("txoutclk", "userclk1")) } -class PCIeVC709ShellPlacer(val shell: VC709Shell, val shellInput: PCIeShellInput)(implicit val valName: ValName) - extends PCIeShellPlacer[VC709Shell] { +class PCIeVC709ShellPlacer(val shell: VC709ShellBasicOverlays, val shellInput: PCIeShellInput)(implicit val valName: ValName) + extends PCIeShellPlacer[VC709ShellBasicOverlays] { def place(designInput: PCIeDesignInput) = new PCIeVC709PlacedOverlay(shell, valName.name, designInput, shellInput) } -abstract class VC709Shell()(implicit p: Parameters) extends Series7Shell +abstract class VC709ShellBasicOverlays()(implicit p: Parameters) extends Series7Shell { // PLL reset causes val pllReset = InModuleBody { Wire(Bool()) } // Order matters; ddr depends on sys_clock val sys_clock = Overlay(ClockInputOverlayKey, new SysClockVC709ShellPlacer(this, ClockInputShellInput())) - val led = Seq.tabulate(8)(i => Overlay(LEDOverlayKey, new LEDVC709ShellPlacer(this, LEDShellInput(color = "red", number = i))(valName = ValName(s"led_$i")))) - val switch = Seq.tabulate(8)(i => Overlay(SwitchOverlayKey, new SwitchVC709ShellPlacer(this, SwitchShellInput(number = i))(valName = ValName(s"switch_$i")))) - val button = Seq.tabulate(5)(i => Overlay(ButtonOverlayKey, new ButtonVC709ShellPlacer(this, ButtonShellInput(number = i))(valName = ValName(s"button_$i")))) + // val led = Seq.tabulate(8)(i => Overlay(LEDOverlayKey, new LEDVC709ShellPlacer(this, LEDShellInput(color = "red", number = i))(valName = ValName(s"led_$i")))) + // val switch = Seq.tabulate(8)(i => Overlay(SwitchOverlayKey, new SwitchVC709ShellPlacer(this, SwitchShellInput(number = i))(valName = ValName(s"switch_$i")))) + // val button = Seq.tabulate(5)(i => Overlay(ButtonOverlayKey, new ButtonVC709ShellPlacer(this, ButtonShellInput(number = i))(valName = ValName(s"button_$i")))) + val uart = Seq.tabulate(1)(i => Overlay(UARTOverlayKey, new UARTVC709ShellPlacer(this, UARTShellInput(index = 0)))) + val jtag = Overlay(JTAGDebugOverlayKey, new JTAGDebugVC709ShellPlacer(this, JTAGDebugShellInput())) val chiplink = Overlay(ChipLinkOverlayKey, new ChipLinkVC709ShellPlacer(this, ChipLinkShellInput())) val ddr0 = Overlay(DDROverlayKey, new DDR3VC709ShellPlacer(this, DDRShellInput())) + val pcie = Overlay(PCIeOverlayKey, new PCIeVC709ShellPlacer(this, PCIeShellInput())) } -class VC709BaseShell()(implicit p: Parameters) extends VC709Shell +class VC709BaseShell()(implicit p: Parameters) extends VC709ShellBasicOverlays { val topDesign = LazyModule(p(DesignKey)(designParameters)) @@ -329,31 +291,3 @@ class VC709BaseShell()(implicit p: Parameters) extends VC709Shell reset_ibuf.io.O || powerOnReset || ereset } } - -class VC709PCIeShell()(implicit p: Parameters) extends VC709Shell -{ - val pcie = Overlay(PCIeOverlayKey, new PCIeVC709ShellPlacer(this, PCIeShellInput())) - val topDesign = LazyModule(p(DesignKey)(designParameters)) - - // Place the sys_clock at the Shell if the user didn't ask for it - p(ClockInputOverlayKey).foreach(_.place(ClockInputDesignInput())) - - override lazy val module = new LazyRawModuleImp(this) { - val reset = IO(Input(Bool())) - xdc.addBoardPin(reset, "reset") - - val reset_ibuf = Module(new IBUF) - reset_ibuf.io.I := reset - val sysclk: Clock = sys_clock.get() match { - case Some(x: SysClockVC709PlacedOverlay) => x.clock - } - val powerOnReset = PowerOnResetFPGAOnly(sysclk) - sdc.addAsyncPath(Seq(powerOnReset)) - val ereset: Bool = chiplink.get() match { - case Some(x: ChipLinkVCU118PlacedOverlay) => !x.ereset_n - case _ => false.B - } - pllReset := - reset_ibuf.io.O || powerOnReset || ereset - } -} diff --git a/src/main/scala/shell/xilinx/XilinxShell.scala b/src/main/scala/shell/xilinx/XilinxShell.scala index 72ed6476..5a62c8e2 100644 --- a/src/main/scala/shell/xilinx/XilinxShell.scala +++ b/src/main/scala/shell/xilinx/XilinxShell.scala @@ -86,4 +86,4 @@ abstract class UltraScaleShell()(implicit p: Parameters) extends XilinxShell override def designParameters = super.designParameters.alterPartial { case PLLFactoryKey => pllFactory } -} +} \ No newline at end of file diff --git a/xilinx/common/tcl/boards.tcl b/xilinx/common/tcl/boards.tcl index af1c686b..fd73fb83 100644 --- a/xilinx/common/tcl/boards.tcl +++ b/xilinx/common/tcl/boards.tcl @@ -6,4 +6,5 @@ set ::program::boards::spec [dict create \ arty [dict create iface spix4 size 16 bitaddr 0x0 memdev {n25q128-3.3v-spi-x1_x2_x4}] \ arty_a7_100 [dict create iface spix4 size 16 bitaddr 0x0 memdev {s25fl128sxxxxxx0-spi-x1_x2_x4}] \ vc707 [dict create iface bpix16 size 128 bitaddr 0x3000000 ] \ + vc709 [dict create iface bpix16 size 128 bitaddr 0x3000000 memdev {mt28gu01gaax1e-bpi-x16}] \ vcu118 [dict create iface spix8 size 256 bitaddr 0x0 memdev {mt25qu01g-spi-x1_x2_x4_x8}]] diff --git a/xilinx/common/tcl/vivado.tcl b/xilinx/common/tcl/vivado.tcl index 46f26145..5ebdc709 100644 --- a/xilinx/common/tcl/vivado.tcl +++ b/xilinx/common/tcl/vivado.tcl @@ -1,4 +1,5 @@ # See LICENSE for license details. +set_param general.maxThreads 8 # Set the variable for the directory that includes all scripts set scriptdir [file dirname [info script]] From e6f890dcd061328802dfc811b2aa376e155d2861 Mon Sep 17 00:00:00 2001 From: Benshan Mei Date: Sat, 6 Feb 2021 12:39:15 +0800 Subject: [PATCH 05/26] add support for dual memory channels --- src/main/scala/shell/xilinx/DDR3Overlay.scala | 69 +++++++++++++++++++ 1 file changed, 69 insertions(+) create mode 100644 src/main/scala/shell/xilinx/DDR3Overlay.scala diff --git a/src/main/scala/shell/xilinx/DDR3Overlay.scala b/src/main/scala/shell/xilinx/DDR3Overlay.scala new file mode 100644 index 00000000..83c906c9 --- /dev/null +++ b/src/main/scala/shell/xilinx/DDR3Overlay.scala @@ -0,0 +1,69 @@ +package sifive.fpgashells.shell.xilinx + +import chisel3._ +import chisel3.experimental.{attach, IO, withClockAndReset} +import freechips.rocketchip.config._ +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.util.SyncResetSynchronizerShiftReg +import sifive.fpgashells.clocks._ +import sifive.fpgashells.shell._ +import sifive.fpgashells.ip.xilinx._ +import sifive.blocks.devices.chiplink._ +import sifive.fpgashells.devices.xilinx.xilinxvc709mig._ + +case object VC709DDR3Size extends Field[BigInt](0x100000000L) // 4GB + +abstract class DDR3XilinxPlacedOverlay(shell: VC709ShellBasicOverlays, name: String, designInput: DDRDesignInput, shellInput: DDRShellInput) + extends DDRPlacedOverlay[XilinxVC709MIGPads](name, designInput, shellInput) +{ + val size = p(VC709DDR3Size) + + val migParams = XilinxVC709MIGParams(address = AddressSet.misaligned(di.baseAddress, size)) + val mig = LazyModule(new XilinxVC709MIG(migParams)) + val ioNode = BundleBridgeSource(() => mig.module.io.cloneType) + val topIONode = shell { ioNode.makeSink() } + val ddrUI = shell { ClockSourceNode(freqMHz = 200) } + val areset = shell { ClockSinkNode(Seq(ClockSinkParameters())) } + areset := designInput.wrangler := ddrUI + + // since this uses a separate clk/rst need to put an async crossing + val asyncSink = LazyModule(new TLAsyncCrossingSink()) + val migClkRstNode = BundleBridgeSource(() => new Bundle { + val clock = Output(Clock()) + val reset = Output(Bool()) + }) + val topMigClkRstIONode = shell { migClkRstNode.makeSink() } + + def overlayOutput = DDROverlayOutput(ddr = mig.node) + def ioFactory = new XilinxVC709MIGPads(size) + + InModuleBody { + ioNode.bundle <> mig.module.io + + // setup async crossing + asyncSink.module.clock := migClkRstNode.bundle.clock + asyncSink.module.reset := migClkRstNode.bundle.reset + } + + shell { InModuleBody { + require (shell.sys_clock.get.isDefined, "Use of DDR3XilinxPlacedOverlay depends on SysClockVC709PlacedOverlay") + + val (sys, _) = shell.sys_clock.get.get.overlayOutput.node.out(0) + val (ui, _) = ddrUI.out(0) + val (ar, _) = areset.in(0) + + // connect the async fifo sync to sys_clock + topMigClkRstIONode.bundle.clock := sys.clock + topMigClkRstIONode.bundle.reset := sys.reset + + val port = topIONode.bundle.port + io <> port + // This is modified for vc709 + ui.clock := port.ui_clk + ui.reset := !port.mmcm_locked || port.ui_clk_sync_rst + port.sys_clk_i := sys.clock.asUInt + port.sys_rst := sys.reset // pllReset + port.aresetn := !ar.reset + } } +} \ No newline at end of file From 8ef984cd04ee4661f7559f4613db38b222dec979 Mon Sep 17 00:00:00 2001 From: Benshan Mei Date: Sat, 6 Feb 2021 21:52:03 +0800 Subject: [PATCH 06/26] support two memory channels --- .../xilinxvc709mig/XilinxVC709MIG.scala | 1 + .../XilinxVC709PCIeX1Periphery.scala | 2 +- .../scala/ip/xilinx/vc709mig/vc709mig.tcl | 34 ++++++++++++++++ src/main/scala/shell/xilinx/DDR3Overlay.scala | 21 ---------- .../scala/shell/xilinx/VC709NewShell.scala | 40 ++++++++++--------- 5 files changed, 57 insertions(+), 41 deletions(-) create mode 100644 src/main/scala/ip/xilinx/vc709mig/vc709mig.tcl diff --git a/src/main/scala/devices/xilinx/xilinxvc709mig/XilinxVC709MIG.scala b/src/main/scala/devices/xilinx/xilinxvc709mig/XilinxVC709MIG.scala index 20a48f7d..35e6cdf1 100644 --- a/src/main/scala/devices/xilinx/xilinxvc709mig/XilinxVC709MIG.scala +++ b/src/main/scala/devices/xilinx/xilinxvc709mig/XilinxVC709MIG.scala @@ -157,6 +157,7 @@ class XilinxVC709MIG(c : XilinxVC709MIGParams, crossing: ClockCrossingType = Asy val ranges = AddressRange.fromSets(c.address) val depth = ranges.head.size + // The data follows from top to down val buffer = LazyModule(new TLBuffer) val toaxi4 = LazyModule(new TLToAXI4(adapterName = Some("mem"))) val indexer = LazyModule(new AXI4IdIndexer(idBits = 4)) diff --git a/src/main/scala/devices/xilinx/xilinxvc709pciex1/XilinxVC709PCIeX1Periphery.scala b/src/main/scala/devices/xilinx/xilinxvc709pciex1/XilinxVC709PCIeX1Periphery.scala index 85964770..15017561 100644 --- a/src/main/scala/devices/xilinx/xilinxvc709pciex1/XilinxVC709PCIeX1Periphery.scala +++ b/src/main/scala/devices/xilinx/xilinxvc709pciex1/XilinxVC709PCIeX1Periphery.scala @@ -29,4 +29,4 @@ trait HasSystemXilinxVC709PCIeX1ModuleImp extends LazyModuleImp val xilinxvc709pcie = IO(new XilinxVC709PCIeX1IO) xilinxvc709pcie <> outer.xilinxvc709pcie.module.io.port -} +} \ No newline at end of file diff --git a/src/main/scala/ip/xilinx/vc709mig/vc709mig.tcl b/src/main/scala/ip/xilinx/vc709mig/vc709mig.tcl new file mode 100644 index 00000000..079c22ec --- /dev/null +++ b/src/main/scala/ip/xilinx/vc709mig/vc709mig.tcl @@ -0,0 +1,34 @@ + # // ElaborationArtefacts.add( + # // "vc709mig4gb.vivado.tcl", + # // """ + # // create_bd_cell -type ip -vlvn xilinx.com:ip:mig_7series:3.0 vc709mig4gb -dir $ipdir -force + # // set_property -dict [list \ + # // CONFIG.AXI4_INTERFACE {true} \ + # // CONFIG.TARGET_FPGA {xc7vx690t-ffg1761/-2} \ + # // CONFIG.C0.ControllerType {DDR3_SDRAM} \ + # // CONFIG.C0.DDR3_TimePeriod {1250} \ + # // CONFIG.C0.DDR3_MemoryType {SODIMMs} \ + # // CONFIG.C0.DDR3_MemoryPart {MT8KTF51264HZ-1G9} \ + # // CONFIG.C0.DDR3_MemoryVoltage {1.5V} \ + # // CONFIG.C0.DDR3_BankMachineCnt {4} \ + # // CONFIG.C0.DDR3_Ordering {Normal} \ + # // CONFIG.C0_S_AXI_DATA_WIDTH {64} \ + # // CONFIG.C0_C_RD_WR_ARB_ALGORITHM {RD_PRI_REG} \ + # // CONFIG.C0_S_AXI_SUPPORTS_NARROW_BURST {0} \ + # // CONFIG.C0_S_AXI_ID_WIDTH {4} \ + # // CONFIG.InputClkFreq {200} \ + # // CONFIG.C0.DDR3_BurstType {Sequential} \ + # // CONFIG.C0.DDR3_OutputDriverImpedenceControl {RZQ/7} \ + # // CONFIG.C0.DDR3_ControllerChipSelectPin {enable} + # // CONFIG.C0.DDR3_OnDieTermination {RZQ/6} \ + # // CONFIG.UserMemoryAddressMap {BANK_ROW_COLUMN} \ + # // CONFIG.System_Clock {No_Buffer} \ + # // CONFIG.Reference_Clock {Use System Clock} \ + # // CONFIG.System_Reset_Polarity {ACTIVE HIGH} + # // CONFIG.Debug_Signal {Disable} \ + # // CONFIG.IOPowerReduction {ON} \ + # // CONFIG.DCI_Cascade {false} \ + # // CONFIG.BankSelectionFlag {false} \ + # // CONFIG.RESET_BOARD_INTERFACE {Custom} \ + # // ] [get_ips vc709mig4gb]""" + # // ) \ No newline at end of file diff --git a/src/main/scala/shell/xilinx/DDR3Overlay.scala b/src/main/scala/shell/xilinx/DDR3Overlay.scala index 83c906c9..9fdf8b85 100644 --- a/src/main/scala/shell/xilinx/DDR3Overlay.scala +++ b/src/main/scala/shell/xilinx/DDR3Overlay.scala @@ -45,25 +45,4 @@ abstract class DDR3XilinxPlacedOverlay(shell: VC709ShellBasicOverlays, name: Str asyncSink.module.clock := migClkRstNode.bundle.clock asyncSink.module.reset := migClkRstNode.bundle.reset } - - shell { InModuleBody { - require (shell.sys_clock.get.isDefined, "Use of DDR3XilinxPlacedOverlay depends on SysClockVC709PlacedOverlay") - - val (sys, _) = shell.sys_clock.get.get.overlayOutput.node.out(0) - val (ui, _) = ddrUI.out(0) - val (ar, _) = areset.in(0) - - // connect the async fifo sync to sys_clock - topMigClkRstIONode.bundle.clock := sys.clock - topMigClkRstIONode.bundle.reset := sys.reset - - val port = topIONode.bundle.port - io <> port - // This is modified for vc709 - ui.clock := port.ui_clk - ui.reset := !port.mmcm_locked || port.ui_clk_sync_rst - port.sys_clk_i := sys.clock.asUInt - port.sys_rst := sys.reset // pllReset - port.aresetn := !ar.reset - } } } \ No newline at end of file diff --git a/src/main/scala/shell/xilinx/VC709NewShell.scala b/src/main/scala/shell/xilinx/VC709NewShell.scala index 96e870b7..0e217205 100644 --- a/src/main/scala/shell/xilinx/VC709NewShell.scala +++ b/src/main/scala/shell/xilinx/VC709NewShell.scala @@ -163,25 +163,27 @@ class DDR3VC709PlacedOverlay(val shell: VC709ShellBasicOverlays, name: String, v extends DDR3XilinxPlacedOverlay(shell, name, designInput, shellInput) { shell { InModuleBody { - // The pins for DDR3 on vc709 board are emitted in the following order: - // addr[0->15], ba[0-2], ras_n, cas_n, we_n, reset_n, ck_p, ck_n, cke, cs_n, odt, dm[0->7], dq[0->63], dqs_n[0->7], dqs_p[0->7] - val allddrpins = Seq( - "A20", "B19", "C20", "A19", "A17", "A16", "D20", "C18", "D17", "C19", "B21", "B17", "A15", "A21", "F17", "E17", // addr[0->15] - "D21", "C21", "D18", // ba[0->2] - "E20", "K17", "F20", "P18", "E19", "E18", "K19", "J17", "H20", // ras_n, cas_n, we_n, reset_n, ck_p, ck_n, cke, cs_n, odt - "M13", "K15", "F12", "A14", "C23", "D25", "C31", "F31", // dm [0->7] - "N14", "N13", "L14", "M14", "M12", "N15", "M11", "L12", "K14", "K13", "H13", "J13", "L16", "L15", "H14", "J15", // dq[0->15] - "E15", "E13", "F15", "E14", "G13", "G12", "F14", "G14", "B14", "C13", "B16", "D15", "D13", "E12", "C16", "D16", // dq[16->31] - "A24", "B23", "B27", "B26", "A22", "B22", "A25", "C24", "E24", "D23", "D26", "C25", "E23", "D22", "F22", "E22", // dq[32->47] - "A30", "D27", "A29", "C28", "D28", "B31", "A31", "A32", "E30", "F29", "F30", "F27", "C30", "E29", "F26", "D30", // dq[48->63] - "M16", "J12", "G16", "C14", "A27", "E25", "B29", "E28", // dqs_n[0->7] - "N16", "K12", "H16", "C15", "A26", "F25", "B28", "E27") // dqs_p[0->7] + require (shell.sys_clock.get.isDefined, "Use of DDR3VC709PlacedOverlay depends on SysClockVC709PlacedOverlay") - IOPin.of(io).foreach { shell.xdc.addPackagePin(_, "") } - (IOPin.of(io) zip allddrpins) foreach { case (io, pin) => shell.xdc.addPackagePin(io, pin) } + val (sys, _) = shell.sys_clock.get.get.overlayOutput.node.out(0) + val (ui, _) = ddrUI.out(0) + val (ar, _) = areset.in(0) + + // connect the async fifo sync to sys_clock + topMigClkRstIONode.bundle.clock := sys.clock + topMigClkRstIONode.bundle.reset := sys.reset + + val port = topIONode.bundle.port + io <> port + // This is modified for vc709 + ui.clock := port.ui_clk + ui.reset := !port.mmcm_locked || port.ui_clk_sync_rst + port.sys_clk_i := sys.clock.asUInt + port.sys_rst := sys.reset // pllReset + port.aresetn := !ar.reset } } - shell.sdc.addGroup(clocks = Seq("ui_clk0"), pins = Seq(mig.island.module.blackbox.io.ui_clk)) + shell.sdc.addGroup(pins = Seq(mig.island.module.blackbox.io.ui_clk)) } class DDR3VC709ShellPlacer(shell: VC709ShellBasicOverlays, val shellInput: DDRShellInput)(implicit val valName: ValName) extends DDRShellPlacer[VC709ShellBasicOverlays] { @@ -253,9 +255,9 @@ abstract class VC709ShellBasicOverlays()(implicit p: Parameters) extends Series7 // Order matters; ddr depends on sys_clock val sys_clock = Overlay(ClockInputOverlayKey, new SysClockVC709ShellPlacer(this, ClockInputShellInput())) - // val led = Seq.tabulate(8)(i => Overlay(LEDOverlayKey, new LEDVC709ShellPlacer(this, LEDShellInput(color = "red", number = i))(valName = ValName(s"led_$i")))) - // val switch = Seq.tabulate(8)(i => Overlay(SwitchOverlayKey, new SwitchVC709ShellPlacer(this, SwitchShellInput(number = i))(valName = ValName(s"switch_$i")))) - // val button = Seq.tabulate(5)(i => Overlay(ButtonOverlayKey, new ButtonVC709ShellPlacer(this, ButtonShellInput(number = i))(valName = ValName(s"button_$i")))) + val led = Seq.tabulate(8)(i => Overlay(LEDOverlayKey, new LEDVC709ShellPlacer(this, LEDShellInput(color = "red", number = i))(valName = ValName(s"led_$i")))) + val switch = Seq.tabulate(8)(i => Overlay(SwitchOverlayKey, new SwitchVC709ShellPlacer(this, SwitchShellInput(number = i))(valName = ValName(s"switch_$i")))) + val button = Seq.tabulate(5)(i => Overlay(ButtonOverlayKey, new ButtonVC709ShellPlacer(this, ButtonShellInput(number = i))(valName = ValName(s"button_$i")))) val uart = Seq.tabulate(1)(i => Overlay(UARTOverlayKey, new UARTVC709ShellPlacer(this, UARTShellInput(index = 0)))) val jtag = Overlay(JTAGDebugOverlayKey, new JTAGDebugVC709ShellPlacer(this, JTAGDebugShellInput())) val chiplink = Overlay(ChipLinkOverlayKey, new ChipLinkVC709ShellPlacer(this, ChipLinkShellInput())) From cd7e3ca12b375ffed102732e2dae5f357d081776 Mon Sep 17 00:00:00 2001 From: Benshan Mei Date: Tue, 2 Mar 2021 11:16:13 +0800 Subject: [PATCH 07/26] support pcie for vc709 board --- .../vc709axi_to_pcie_x1.scala | 2 +- .../scala/shell/xilinx/VC709NewShell.scala | 21 +++++++++---------- 2 files changed, 11 insertions(+), 12 deletions(-) diff --git a/src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala b/src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala index 8ed8393e..9437a8d0 100644 --- a/src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala +++ b/src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala @@ -164,7 +164,7 @@ class vc709axi_to_pcie_x1() extends BlackBox //scalastyle:off //wrap vc709_axi_to_pcie_x1 black box in Nasti Bundles - +// see Chipyard doc: 9.1.2 Manager Node class VC709AXIToPCIeX1(implicit p:Parameters) extends LazyModule { // device-tree node diff --git a/src/main/scala/shell/xilinx/VC709NewShell.scala b/src/main/scala/shell/xilinx/VC709NewShell.scala index 0e217205..8f8836ce 100644 --- a/src/main/scala/shell/xilinx/VC709NewShell.scala +++ b/src/main/scala/shell/xilinx/VC709NewShell.scala @@ -20,7 +20,8 @@ class SysClockVC709PlacedOverlay(val shell: VC709ShellBasicOverlays, name: Strin val node = shell { ClockSourceNode(freqMHz = 200, jitterPS = 50)(ValName(name)) } shell { InModuleBody { - // sysclk_p, sysclk_n + shell.xdc.addBoardPin(io.p, "clk_p") + shell.xdc.addBoardPin(io.n, "clk_n") // val packagePinsWithPackageIOs = Seq(("H19", IOPin(io.p)), // ("G18", IOPin(io.n))) @@ -29,9 +30,6 @@ class SysClockVC709PlacedOverlay(val shell: VC709ShellBasicOverlays, name: Strin // shell.xdc.addIOStandard(io, "DIFF_SSTL15") // shell.xdc.addIOB(io) // } } - - shell.xdc.addBoardPin(io.p, "clk_p") - shell.xdc.addBoardPin(io.n, "clk_n") } } } @@ -200,13 +198,14 @@ class PCIeVC709PlacedOverlay(val shell: VC709ShellBasicOverlays, name: String, v val areset = shell { ClockSinkNode(Seq(ClockSinkParameters())) } areset := designInput.wrangler := axiClk + // 9.1.4 Indentity Node val slaveSide = TLIdentityNode() pcie.crossTLIn(pcie.slave) := slaveSide pcie.crossTLIn(pcie.control) := slaveSide - val node = NodeHandle(slaveSide, pcie.crossTLOut(pcie.master)) - val intNode = pcie.crossIntOut(pcie.intnode) - - def overlayOutput = PCIeOverlayOutput(node, intNode) + val masterSide = pcie.crossTLOut(pcie.master) + // NodeHandle(inward, outward) defined in: rocketchip/diplomacy/Nodes.scala + def overlayOutput = PCIeOverlayOutput(pcieNode=NodeHandle(slaveSide, masterSide), intNode=pcie.crossIntOut(pcie.intnode)) + def ioFactory = new XilinxVC709PCIeX1Pads InModuleBody { bridge.bundle <> pcie.module.io } @@ -255,9 +254,9 @@ abstract class VC709ShellBasicOverlays()(implicit p: Parameters) extends Series7 // Order matters; ddr depends on sys_clock val sys_clock = Overlay(ClockInputOverlayKey, new SysClockVC709ShellPlacer(this, ClockInputShellInput())) - val led = Seq.tabulate(8)(i => Overlay(LEDOverlayKey, new LEDVC709ShellPlacer(this, LEDShellInput(color = "red", number = i))(valName = ValName(s"led_$i")))) - val switch = Seq.tabulate(8)(i => Overlay(SwitchOverlayKey, new SwitchVC709ShellPlacer(this, SwitchShellInput(number = i))(valName = ValName(s"switch_$i")))) - val button = Seq.tabulate(5)(i => Overlay(ButtonOverlayKey, new ButtonVC709ShellPlacer(this, ButtonShellInput(number = i))(valName = ValName(s"button_$i")))) + // val led = Seq.tabulate(8)(i => Overlay(LEDOverlayKey, new LEDVC709ShellPlacer(this, LEDShellInput(color = "red", number = i))(valName = ValName(s"led_$i")))) + // val switch = Seq.tabulate(8)(i => Overlay(SwitchOverlayKey, new SwitchVC709ShellPlacer(this, SwitchShellInput(number = i))(valName = ValName(s"switch_$i")))) + // val button = Seq.tabulate(5)(i => Overlay(ButtonOverlayKey, new ButtonVC709ShellPlacer(this, ButtonShellInput(number = i))(valName = ValName(s"button_$i")))) val uart = Seq.tabulate(1)(i => Overlay(UARTOverlayKey, new UARTVC709ShellPlacer(this, UARTShellInput(index = 0)))) val jtag = Overlay(JTAGDebugOverlayKey, new JTAGDebugVC709ShellPlacer(this, JTAGDebugShellInput())) val chiplink = Overlay(ChipLinkOverlayKey, new ChipLinkVC709ShellPlacer(this, ChipLinkShellInput())) From 423d0f70666f7ab862b563b7de6ce71d4e2c6c34 Mon Sep 17 00:00:00 2001 From: Benshan Mei Date: Thu, 4 Mar 2021 15:43:00 +0800 Subject: [PATCH 08/26] update DDR3Overlay --- .../vc709axi_to_pcie_x1.scala | 4 ++-- src/main/scala/shell/xilinx/DDR3Overlay.scala | 16 +--------------- src/main/scala/shell/xilinx/VC709NewShell.scala | 9 +++------ 3 files changed, 6 insertions(+), 23 deletions(-) diff --git a/src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala b/src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala index 9437a8d0..165878c0 100644 --- a/src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala +++ b/src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala @@ -63,7 +63,7 @@ class vc709axi_to_pcie_x1() extends BlackBox val s_axi_awvalid = Bool(INPUT) val s_axi_awready = Bool(OUTPUT) //slave interface write data - val s_axi_wdata = Bits(INPUT,128) // 64 + val s_axi_wdata = Bits(INPUT,128) // 64 val s_axi_wstrb = Bits(INPUT,16) // 8 val s_axi_wlast = Bool(INPUT) val s_axi_wvalid = Bool(INPUT) @@ -110,7 +110,7 @@ class vc709axi_to_pcie_x1() extends BlackBox val m_axi_awvalid = Bool(OUTPUT) val m_axi_awready = Bool(INPUT) //slave interface write data ports - val m_axi_wdata = Bits(OUTPUT,128) // 64 + val m_axi_wdata = Bits(OUTPUT,128) // 64 val m_axi_wstrb = Bits(OUTPUT,16) // 8 val m_axi_wlast = Bool(OUTPUT) val m_axi_wvalid = Bool(OUTPUT) diff --git a/src/main/scala/shell/xilinx/DDR3Overlay.scala b/src/main/scala/shell/xilinx/DDR3Overlay.scala index 9fdf8b85..8e832a9a 100644 --- a/src/main/scala/shell/xilinx/DDR3Overlay.scala +++ b/src/main/scala/shell/xilinx/DDR3Overlay.scala @@ -13,7 +13,6 @@ import sifive.blocks.devices.chiplink._ import sifive.fpgashells.devices.xilinx.xilinxvc709mig._ case object VC709DDR3Size extends Field[BigInt](0x100000000L) // 4GB - abstract class DDR3XilinxPlacedOverlay(shell: VC709ShellBasicOverlays, name: String, designInput: DDRDesignInput, shellInput: DDRShellInput) extends DDRPlacedOverlay[XilinxVC709MIGPads](name, designInput, shellInput) { @@ -27,22 +26,9 @@ abstract class DDR3XilinxPlacedOverlay(shell: VC709ShellBasicOverlays, name: Str val areset = shell { ClockSinkNode(Seq(ClockSinkParameters())) } areset := designInput.wrangler := ddrUI - // since this uses a separate clk/rst need to put an async crossing - val asyncSink = LazyModule(new TLAsyncCrossingSink()) - val migClkRstNode = BundleBridgeSource(() => new Bundle { - val clock = Output(Clock()) - val reset = Output(Bool()) - }) - val topMigClkRstIONode = shell { migClkRstNode.makeSink() } def overlayOutput = DDROverlayOutput(ddr = mig.node) def ioFactory = new XilinxVC709MIGPads(size) - InModuleBody { - ioNode.bundle <> mig.module.io - - // setup async crossing - asyncSink.module.clock := migClkRstNode.bundle.clock - asyncSink.module.reset := migClkRstNode.bundle.reset - } + InModuleBody { ioNode.bundle <> mig.module.io } } \ No newline at end of file diff --git a/src/main/scala/shell/xilinx/VC709NewShell.scala b/src/main/scala/shell/xilinx/VC709NewShell.scala index 8f8836ce..3ce47c14 100644 --- a/src/main/scala/shell/xilinx/VC709NewShell.scala +++ b/src/main/scala/shell/xilinx/VC709NewShell.scala @@ -162,17 +162,13 @@ class DDR3VC709PlacedOverlay(val shell: VC709ShellBasicOverlays, name: String, v { shell { InModuleBody { require (shell.sys_clock.get.isDefined, "Use of DDR3VC709PlacedOverlay depends on SysClockVC709PlacedOverlay") - val (sys, _) = shell.sys_clock.get.get.overlayOutput.node.out(0) val (ui, _) = ddrUI.out(0) val (ar, _) = areset.in(0) - - // connect the async fifo sync to sys_clock - topMigClkRstIONode.bundle.clock := sys.clock - topMigClkRstIONode.bundle.reset := sys.reset - val port = topIONode.bundle.port + io <> port + // This is modified for vc709 ui.clock := port.ui_clk ui.reset := !port.mmcm_locked || port.ui_clk_sync_rst @@ -181,6 +177,7 @@ class DDR3VC709PlacedOverlay(val shell: VC709ShellBasicOverlays, name: String, v port.aresetn := !ar.reset } } + // shell.sdc.addGroup(clocks = Seq("clk_pll_i")) shell.sdc.addGroup(pins = Seq(mig.island.module.blackbox.io.ui_clk)) } class DDR3VC709ShellPlacer(shell: VC709ShellBasicOverlays, val shellInput: DDRShellInput)(implicit val valName: ValName) From ce62c047963436c483ea185d07e31edb84adb30c Mon Sep 17 00:00:00 2001 From: Benshan Mei Date: Mon, 8 Mar 2021 16:14:13 +0800 Subject: [PATCH 09/26] support PCIeX8 for vc709 --- .../ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala | 6 +++--- src/main/scala/shell/xilinx/DDR3Overlay.scala | 1 - src/main/scala/shell/xilinx/VC709NewShell.scala | 3 ++- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala b/src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala index 165878c0..c7ba2f09 100644 --- a/src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala +++ b/src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala @@ -419,12 +419,12 @@ class VC709AXIToPCIeX1(implicit p:Parameters) extends LazyModule CONFIG.PF0_DEVICE_ID {8018} \ CONFIG.PF0_REVISION_ID {0} \ CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10EE} \ - CONFIG.PF0_SUBSYSTEM_ID {7} \ + CONFIG.PF0_SUBSYSTEM_ID {0007} \ CONFIG.PF0_BAR0_64BIT {true} \ CONFIG.PF0_BAR0_ENABLED {true} \ CONFIG.PF0_BAR0_PREFETCHABLE {false} \ - CONFIG.PF0_BAR0_SCALE {Gigabytes} \ - CONFIG.PF0_BAR0_SIZE {4} \ + CONFIG.PF0_BAR0_SCALE {Megabytes} \ + CONFIG.PF0_BAR0_SIZE {1} \ CONFIG.PF0_BAR0_TYPE {Memory} \ CONFIG.PF0_SUB_CLASS_interface_menu {Host_bridge} \ CONFIG.REF_CLK_FREQ {100_MHz} \ diff --git a/src/main/scala/shell/xilinx/DDR3Overlay.scala b/src/main/scala/shell/xilinx/DDR3Overlay.scala index 8e832a9a..1e4e9cd5 100644 --- a/src/main/scala/shell/xilinx/DDR3Overlay.scala +++ b/src/main/scala/shell/xilinx/DDR3Overlay.scala @@ -26,7 +26,6 @@ abstract class DDR3XilinxPlacedOverlay(shell: VC709ShellBasicOverlays, name: Str val areset = shell { ClockSinkNode(Seq(ClockSinkParameters())) } areset := designInput.wrangler := ddrUI - def overlayOutput = DDROverlayOutput(ddr = mig.node) def ioFactory = new XilinxVC709MIGPads(size) diff --git a/src/main/scala/shell/xilinx/VC709NewShell.scala b/src/main/scala/shell/xilinx/VC709NewShell.scala index 3ce47c14..3876878a 100644 --- a/src/main/scala/shell/xilinx/VC709NewShell.scala +++ b/src/main/scala/shell/xilinx/VC709NewShell.scala @@ -212,7 +212,7 @@ class PCIeVC709PlacedOverlay(val shell: VC709ShellBasicOverlays, name: String, v val (ar, _) = areset.in(0) val port = topBridge.bundle.port io <> port - axi.clock := port.axi_aclk // port.axi_aclk_out is changed to port.axi_aclk in 3.0 + axi.clock := port.axi_aclk // axi.reset := !port.mmcm_lock // mmcm_lock is removed in 3.0 port.axi_aresetn := !ar.reset port.axi_ctl_aresetn := !ar.reset @@ -263,6 +263,7 @@ abstract class VC709ShellBasicOverlays()(implicit p: Parameters) extends Series7 class VC709BaseShell()(implicit p: Parameters) extends VC709ShellBasicOverlays { + // val topDesign = LazyModule(p(BuildTop)(dp)).suggestName("chiptop") val topDesign = LazyModule(p(DesignKey)(designParameters)) // Place the sys_clock at the Shell if the user didn't ask for it From ab19d860ed730c0019888ce13f979e9f0ce6cc74 Mon Sep 17 00:00:00 2001 From: mbs0221 Date: Sat, 13 Mar 2021 16:41:44 +0800 Subject: [PATCH 10/26] update support for vc709 board --- .../xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala | 4 ++-- src/main/scala/shell/xilinx/VC707NewShell.scala | 8 ++++---- src/main/scala/shell/xilinx/VC709NewShell.scala | 8 +++----- 3 files changed, 9 insertions(+), 11 deletions(-) diff --git a/src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala b/src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala index c7ba2f09..409ab066 100644 --- a/src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala +++ b/src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala @@ -423,8 +423,8 @@ class VC709AXIToPCIeX1(implicit p:Parameters) extends LazyModule CONFIG.PF0_BAR0_64BIT {true} \ CONFIG.PF0_BAR0_ENABLED {true} \ CONFIG.PF0_BAR0_PREFETCHABLE {false} \ - CONFIG.PF0_BAR0_SCALE {Megabytes} \ - CONFIG.PF0_BAR0_SIZE {1} \ + CONFIG.PF0_BAR0_SCALE {Gigabytes} \ + CONFIG.PF0_BAR0_SIZE {4} \ CONFIG.PF0_BAR0_TYPE {Memory} \ CONFIG.PF0_SUB_CLASS_interface_menu {Host_bridge} \ CONFIG.REF_CLK_FREQ {100_MHz} \ diff --git a/src/main/scala/shell/xilinx/VC707NewShell.scala b/src/main/scala/shell/xilinx/VC707NewShell.scala index 64ef8310..9e471c5d 100644 --- a/src/main/scala/shell/xilinx/VC707NewShell.scala +++ b/src/main/scala/shell/xilinx/VC707NewShell.scala @@ -156,11 +156,11 @@ class JTAGDebugVC707PlacedOverlay(val shell: VC707Shell, name: String, val desig #2 VREF 14 5V #18 GND 13 GND */ - val packagePinsWithPackageIOs = Seq(("AT42", IOPin(io.jtag_TCK)), - ("AR38", IOPin(io.jtag_TMS)), - ("AR39", IOPin(io.jtag_TDI)), + val packagePinsWithPackageIOs = Seq(("R32", IOPin(io.jtag_TCK)), + ("W36", IOPin(io.jtag_TMS)), + ("W37", IOPin(io.jtag_TDI)), ("AR42", IOPin(io.srst_n)), - ("AT40", IOPin(io.jtag_TDO))) + ("V40", IOPin(io.jtag_TDO))) packagePinsWithPackageIOs foreach { case (pin, io) => { shell.xdc.addPackagePin(io, pin) shell.xdc.addIOStandard(io, "LVCMOS18") diff --git a/src/main/scala/shell/xilinx/VC709NewShell.scala b/src/main/scala/shell/xilinx/VC709NewShell.scala index 3876878a..0a4f39b5 100644 --- a/src/main/scala/shell/xilinx/VC709NewShell.scala +++ b/src/main/scala/shell/xilinx/VC709NewShell.scala @@ -177,8 +177,8 @@ class DDR3VC709PlacedOverlay(val shell: VC709ShellBasicOverlays, name: String, v port.aresetn := !ar.reset } } - // shell.sdc.addGroup(clocks = Seq("clk_pll_i")) - shell.sdc.addGroup(pins = Seq(mig.island.module.blackbox.io.ui_clk)) + shell.sdc.addGroup(clocks = Seq("clk_pll_i")) + // shell.sdc.addGroup(pins = Seq(mig.island.module.blackbox.io.ui_clk)) } class DDR3VC709ShellPlacer(shell: VC709ShellBasicOverlays, val shellInput: DDRShellInput)(implicit val valName: ValName) extends DDRShellPlacer[VC709ShellBasicOverlays] { @@ -195,14 +195,12 @@ class PCIeVC709PlacedOverlay(val shell: VC709ShellBasicOverlays, name: String, v val areset = shell { ClockSinkNode(Seq(ClockSinkParameters())) } areset := designInput.wrangler := axiClk - // 9.1.4 Indentity Node val slaveSide = TLIdentityNode() pcie.crossTLIn(pcie.slave) := slaveSide pcie.crossTLIn(pcie.control) := slaveSide val masterSide = pcie.crossTLOut(pcie.master) - // NodeHandle(inward, outward) defined in: rocketchip/diplomacy/Nodes.scala + def overlayOutput = PCIeOverlayOutput(pcieNode=NodeHandle(slaveSide, masterSide), intNode=pcie.crossIntOut(pcie.intnode)) - def ioFactory = new XilinxVC709PCIeX1Pads InModuleBody { bridge.bundle <> pcie.module.io } From ca1182aaef00e148138eb2e81951348a18e2b9f0 Mon Sep 17 00:00:00 2001 From: mbs0221 Date: Wed, 17 Mar 2021 10:36:41 +0800 Subject: [PATCH 11/26] update support for PCIe Endpoint Device ip --- .../vc709axi_to_pcie_x1.scala | 166 ++++++------------ 1 file changed, 50 insertions(+), 116 deletions(-) diff --git a/src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala b/src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala index 409ab066..3b7d8e8a 100644 --- a/src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala +++ b/src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala @@ -8,13 +8,12 @@ import freechips.rocketchip.amba.axi4._ import freechips.rocketchip.interrupts._ import freechips.rocketchip.util.{ElaborationArtefacts} +// AXI Bridge for PCI Express Gen3 Subsystem v3.0 +// Product Guide Vivado Design Suite PG194 (v3.0) July 22, 2020 // IP VLNV: xilinx.com:customize_ip:vc709pcietoaxi:3.0 -// Black Box -// Signals named _exactly_ as per Vivado generated verilog -// s : -{lock, cache, prot, qos} - +// Black Box Signals named _exactly_ as per Vivado generated verilog trait VC709AXIToPCIeX1IOSerial extends Bundle { - //serial external pins + // PCIe Interface val pci_exp_txp = Bits(OUTPUT, 8) val pci_exp_txn = Bits(OUTPUT, 8) val pci_exp_rxp = Bits(INPUT, 8) @@ -22,9 +21,9 @@ trait VC709AXIToPCIeX1IOSerial extends Bundle { } trait VC709AXIToPCIeX1IOClocksReset extends Bundle { - //clock, reset, control + // Global Signals val axi_aresetn = Bool(INPUT) - val axi_aclk = Clock(OUTPUT) // axi_aclk_out is changed to axi_aclk in 3.0 + val axi_aclk = Clock(OUTPUT) } //scalastyle:off @@ -33,57 +32,45 @@ class vc709axi_to_pcie_x1() extends BlackBox { val io = new Bundle with VC709AXIToPCIeX1IOSerial with VC709AXIToPCIeX1IOClocksReset { - //refclk - val refclk = Bool(INPUT) // REFCLK is changed in 3.0 - - //clock, reset, control - val intx_msi_request = Bool(INPUT) // INTX_MSI_Request is changed in 3.0 - val intx_msi_grant = Bool(OUTPUT) // INTX_MSI_Grant is changed in 3.0 - - val msi_enable = Bool(OUTPUT) // MSI_enable is changed in 3.0 - val msi_vector_num = Bits(INPUT, 5) // MSI_Vector_Num is changed in 3.0 - val msi_vector_width = Bits(OUTPUT,3) // MSI_Vector_Width is changed in 3.0 - - //interrupt + // Global Signals + val refclk = Bool(INPUT) val interrupt_out = Bool(OUTPUT) - //axi slave - //-{lock, cache, prot, qos} - //slave interface write address + // AXI Bridge for PCIe Gen3 MSI Signals + val intx_msi_request = Bool(INPUT) + val intx_msi_grant = Bool(OUTPUT) + val msi_enable = Bool(OUTPUT) + val msi_vector_num = Bits(INPUT, 5) + val msi_vector_width = Bits(OUTPUT,3) + + // AXI Slave Interface + // write address val s_axi_awid = Bits(INPUT,4) val s_axi_awaddr = Bits(INPUT,32) val s_axi_awregion = Bits(INPUT,4) val s_axi_awlen = Bits(INPUT,8) val s_axi_awsize = Bits(INPUT,3) val s_axi_awburst = Bits(INPUT,2) - //val s_axi_awlock = Bool(INPUT) - //val s_axi_awcache = Bits(INPUT,4) - //val s_axi_awprot = Bits(INPUT,3) - //val s_axi_awqos = Bits(INPUT,4) val s_axi_awvalid = Bool(INPUT) val s_axi_awready = Bool(OUTPUT) - //slave interface write data + // write data val s_axi_wdata = Bits(INPUT,128) // 64 val s_axi_wstrb = Bits(INPUT,16) // 8 val s_axi_wlast = Bool(INPUT) val s_axi_wvalid = Bool(INPUT) val s_axi_wready = Bool(OUTPUT) - //slave interface write response + // write response val s_axi_bready = Bool(INPUT) val s_axi_bid = Bits(OUTPUT,4) val s_axi_bresp = Bits(OUTPUT,2) val s_axi_bvalid = Bool(OUTPUT) - //slave interface read address + // read address val s_axi_arid = Bits(INPUT,4) val s_axi_araddr = Bits(INPUT,32) val s_axi_arregion = Bits(INPUT,4) val s_axi_arlen = Bits(INPUT,8) val s_axi_arsize = Bits(INPUT,3) val s_axi_arburst = Bits(INPUT,2) - //val s_axi_arlock = Bits(INPUT,1) - //val s_axi_arcache = Bits(INPUT,4) - //val s_axi_arprot = Bits(INPUT,3) - //val s_axi_arqos = Bits(INPUT,4) val s_axi_arvalid = Bool(INPUT) val s_axi_arready = Bool(OUTPUT) //slave interface read data @@ -94,54 +81,41 @@ class vc709axi_to_pcie_x1() extends BlackBox val s_axi_rlast = Bool(OUTPUT) val s_axi_rvalid = Bool(OUTPUT) - //axi master - //-{id,region,qos} - //slave interface write address ports - //val m_axi_awid = Bits(OUTPUT,4) + // AXI Master Interface + // write address val m_axi_awaddr = Bits(OUTPUT,32) - //val m_axi_awregion = Bits(OUTPUT,4) val m_axi_awlen = Bits(OUTPUT,8) val m_axi_awsize = Bits(OUTPUT,3) val m_axi_awburst = Bits(OUTPUT,2) - val m_axi_awlock = Bool(OUTPUT) - val m_axi_awcache = Bits(OUTPUT,4) val m_axi_awprot = Bits(OUTPUT,3) - //val m_axi_awqos = Bits(OUTPUT,4) val m_axi_awvalid = Bool(OUTPUT) val m_axi_awready = Bool(INPUT) - //slave interface write data ports + // write data val m_axi_wdata = Bits(OUTPUT,128) // 64 val m_axi_wstrb = Bits(OUTPUT,16) // 8 val m_axi_wlast = Bool(OUTPUT) val m_axi_wvalid = Bool(OUTPUT) val m_axi_wready = Bool(INPUT) - //slave interface write response ports + // write response val m_axi_bready = Bool(OUTPUT) - //val m_axi_bid = Bits(INPUT,3) // 4 val m_axi_bresp = Bits(INPUT,2) val m_axi_bvalid = Bool(INPUT) - //slave interface read address ports - //val m_axi_arid = Bits(OUTPUT,4) + // read address val m_axi_araddr = Bits(OUTPUT,32) - //val m_axi_arregion = Bits(OUTPUT,4) val m_axi_arlen = Bits(OUTPUT,8) val m_axi_arsize = Bits(OUTPUT,3) val m_axi_arburst = Bits(OUTPUT,2) - val m_axi_arlock = Bits(OUTPUT,1) - val m_axi_arcache = Bits(OUTPUT,4) val m_axi_arprot = Bits(OUTPUT,3) - //val m_axi_arqos = Bits(OUTPUT,4) val m_axi_arvalid = Bool(OUTPUT) val m_axi_arready = Bool(INPUT) - //slave interface read data ports + // read data val m_axi_rready = Bool(OUTPUT) - //val m_axi_rid = Bits(INPUT,4) val m_axi_rdata = Bits(INPUT,128) // 64 val m_axi_rresp = Bits(INPUT,2) val m_axi_rlast = Bool(INPUT) val m_axi_rvalid = Bool(INPUT) - //axi lite slave for control + // AXI4-Lite Control Interface val s_axi_ctl_awaddr = Bits(INPUT,28) // 32 val s_axi_ctl_awvalid = Bool(INPUT) val s_axi_ctl_awready = Bool(OUTPUT) @@ -241,94 +215,72 @@ class VC709AXIToPCIeX1(implicit p:Parameters) extends LazyModule //to top level blackbox.io.axi_aresetn := io.port.axi_aresetn - io.port.axi_aclk := blackbox.io.axi_aclk // axi_aclk_out is changed to axi_aclk in 3.0 - // io.port.axi_ctl_aclk_out := blackbox.io.axi_ctl_aclk_out - // io.port.mmcm_lock := blackbox.io.mmcm_lock + io.port.axi_aclk := blackbox.io.axi_aclk io.port.pci_exp_txp := blackbox.io.pci_exp_txp io.port.pci_exp_txn := blackbox.io.pci_exp_txn blackbox.io.pci_exp_rxp := io.port.pci_exp_rxp blackbox.io.pci_exp_rxn := io.port.pci_exp_rxn i(0) := blackbox.io.interrupt_out - blackbox.io.refclk := io.refclk // REFCLK is changed in to refclk 3.0 + blackbox.io.refclk := io.refclk - //s - //AXI4 signals ordered as per AXI4 Specification (Release D) Section A.2 - //-{lock, cache, prot, qos} - //-{aclk, aresetn, awuser, wid, wuser, buser, ruser} - //global signals - //aclk := - //aresetn := - //slave interface write address + // AXI Slave Interface + // write address blackbox.io.s_axi_awid := s.aw.bits.id blackbox.io.s_axi_awaddr := s.aw.bits.addr blackbox.io.s_axi_awlen := s.aw.bits.len blackbox.io.s_axi_awsize := s.aw.bits.size blackbox.io.s_axi_awburst := s.aw.bits.burst - //blackbox.io.s_axi_awlock := s.aw.bits.lock - //blackbox.io.s_axi_awcache := s.aw.bits.cache - //blackbox.io.s_axi_awprot := s.aw.bits.prot - //blackbox.io.s_axi_awqos := s.aw.bits.qos blackbox.io.s_axi_awregion := UInt(0) - //blackbox.io.awuser := s.aw.bits.user blackbox.io.s_axi_awvalid := s.aw.valid s.aw.ready := blackbox.io.s_axi_awready - //slave interface write data ports - //blackbox.io.s_axi_wid := s.w.bits.id + // write data blackbox.io.s_axi_wdata := s.w.bits.data blackbox.io.s_axi_wstrb := s.w.bits.strb blackbox.io.s_axi_wlast := s.w.bits.last - //blackbox.io.s_axi_wuser := s.w.bits.user blackbox.io.s_axi_wvalid := s.w.valid s.w.ready := blackbox.io.s_axi_wready - //slave interface write response + // write response s.b.bits.id := blackbox.io.s_axi_bid s.b.bits.resp := blackbox.io.s_axi_bresp - //s.b.bits.user := blackbox.io.s_axi_buser s.b.valid := blackbox.io.s_axi_bvalid blackbox.io.s_axi_bready := s.b.ready - //slave AXI interface read address ports + // read address blackbox.io.s_axi_arid := s.ar.bits.id blackbox.io.s_axi_araddr := s.ar.bits.addr blackbox.io.s_axi_arlen := s.ar.bits.len blackbox.io.s_axi_arsize := s.ar.bits.size blackbox.io.s_axi_arburst := s.ar.bits.burst - //blackbox.io.s_axi_arlock := s.ar.bits.lock - //blackbox.io.s_axi_arcache := s.ar.bits.cache - //blackbox.io.s_axi_arprot := s.ar.bits.prot - //blackbox.io.s_axi_arqos := s.ar.bits.qos blackbox.io.s_axi_arregion := UInt(0) - //blackbox.io.s_axi_aruser := s.ar.bits.user blackbox.io.s_axi_arvalid := s.ar.valid s.ar.ready := blackbox.io.s_axi_arready - //slave AXI interface read data ports + // read data s.r.bits.id := blackbox.io.s_axi_rid s.r.bits.data := blackbox.io.s_axi_rdata s.r.bits.resp := blackbox.io.s_axi_rresp s.r.bits.last := blackbox.io.s_axi_rlast - //s.r.bits.ruser := blackbox.io.s_axi_ruser s.r.valid := blackbox.io.s_axi_rvalid blackbox.io.s_axi_rready := s.r.ready - //ctl - //axi-lite slave interface write address + // AXI4-Lite Control Interface + // write address blackbox.io.s_axi_ctl_awaddr := c.aw.bits.addr blackbox.io.s_axi_ctl_awvalid := c.aw.valid c.aw.ready := blackbox.io.s_axi_ctl_awready - //axi-lite slave interface write data ports + // write data blackbox.io.s_axi_ctl_wdata := c.w.bits.data blackbox.io.s_axi_ctl_wstrb := c.w.bits.strb blackbox.io.s_axi_ctl_wvalid := c.w.valid c.w.ready := blackbox.io.s_axi_ctl_wready - //axi-lite slave interface write response + // write response blackbox.io.s_axi_ctl_bready := c.b.ready c.b.bits.id := UInt(0) c.b.bits.resp := blackbox.io.s_axi_ctl_bresp c.b.valid := blackbox.io.s_axi_ctl_bvalid - //axi-lite slave AXI interface read address ports + // read address blackbox.io.s_axi_ctl_araddr := c.ar.bits.addr blackbox.io.s_axi_ctl_arvalid := c.ar.valid c.ar.ready := blackbox.io.s_axi_ctl_arready - //slave AXI interface read data ports + // read data blackbox.io.s_axi_ctl_rready := c.r.ready c.r.bits.id := UInt(0) c.r.bits.data := blackbox.io.s_axi_ctl_rdata @@ -336,14 +288,8 @@ class VC709AXIToPCIeX1(implicit p:Parameters) extends LazyModule c.r.bits.last := Bool(true) c.r.valid := blackbox.io.s_axi_ctl_rvalid - //m - //AXI4 signals ordered per AXI4 Specification (Release D) Section A.2 - //-{id,region,qos} - //-{aclk, aresetn, awuser, wid, wuser, buser, ruser} - //global signals - //aclk := - //aresetn := - //master interface write address + // AXI Master Interface + // write address m.aw.bits.id := UInt(0) m.aw.bits.addr := blackbox.io.m_axi_awaddr m.aw.bits.len := blackbox.io.m_axi_awlen @@ -353,27 +299,19 @@ class VC709AXIToPCIeX1(implicit p:Parameters) extends LazyModule m.aw.bits.cache := blackbox.io.m_axi_awcache m.aw.bits.prot := blackbox.io.m_axi_awprot m.aw.bits.qos := UInt(0) - //m.aw.bits.region := blackbox.io.m_axi_awregion - //m.aw.bits.user := blackbox.io.m_axi_awuser m.aw.valid := blackbox.io.m_axi_awvalid blackbox.io.m_axi_awready := m.aw.ready - - //master interface write data ports + // write data m.w.bits.data := blackbox.io.m_axi_wdata m.w.bits.strb := blackbox.io.m_axi_wstrb m.w.bits.last := blackbox.io.m_axi_wlast - //m.w.bits.user := blackbox.io.m_axi_wuser m.w.valid := blackbox.io.m_axi_wvalid blackbox.io.m_axi_wready := m.w.ready - - //master interface write response - //blackbox.io.m_axi_bid := m.b.bits.id + // write response blackbox.io.m_axi_bresp := m.b.bits.resp - //blackbox.io.m_axi_buser := m.b.bits.user blackbox.io.m_axi_bvalid := m.b.valid m.b.ready := blackbox.io.m_axi_bready - - //master AXI interface read address ports + // read address m.ar.bits.id := UInt(0) m.ar.bits.addr := blackbox.io.m_axi_araddr m.ar.bits.len := blackbox.io.m_axi_arlen @@ -383,17 +321,12 @@ class VC709AXIToPCIeX1(implicit p:Parameters) extends LazyModule m.ar.bits.cache := blackbox.io.m_axi_arcache m.ar.bits.prot := blackbox.io.m_axi_arprot m.ar.bits.qos := UInt(0) - //m.ar.bits.region := blackbox.io.m_axi_arregion - //m.ar.bits.user := blackbox.io.s_axi_aruser m.ar.valid := blackbox.io.m_axi_arvalid blackbox.io.m_axi_arready := m.ar.ready - - //master AXI interface read data ports - //blackbox.io.m_axi_rid := m.r.bits.id + // read data blackbox.io.m_axi_rdata := m.r.bits.data blackbox.io.m_axi_rresp := m.r.bits.resp blackbox.io.m_axi_rlast := m.r.bits.last - //blackbox.io.s_axi_ruser := s.bits.ruser blackbox.io.m_axi_rvalid := m.r.valid m.r.ready := blackbox.io.m_axi_rready } @@ -410,7 +343,7 @@ class VC709AXIToPCIeX1(implicit p:Parameters) extends LazyModule CONFIG.BASEADDR {0x00000000} \ CONFIG.HIGHADDR {0x03FFFFFF} \ CONFIG.COMP_TIMEOUT {50ms} \ - CONFIG.DEVICE_PORT_TYPE {Root_Port_of_PCI_Express_Root_Complex}\ + CONFIG.DEVICE_PORT_TYPE {PCI_Express_Endpoint_Device} \ CONFIG.INCLUDE_BAROFFSET_REG {true} \ CONFIG.PCIEBAR2AXIBAR_0 {0x00000000} \ CONFIG.PCIE_BLK_LOCN {X0Y0} \ @@ -426,8 +359,9 @@ class VC709AXIToPCIeX1(implicit p:Parameters) extends LazyModule CONFIG.PF0_BAR0_SCALE {Gigabytes} \ CONFIG.PF0_BAR0_SIZE {4} \ CONFIG.PF0_BAR0_TYPE {Memory} \ - CONFIG.PF0_SUB_CLASS_interface_menu {Host_bridge} \ + CONFIG.PF0_SUB_CLASS_interface_menu {Other_memory_controller} \ CONFIG.REF_CLK_FREQ {100_MHz} \ + CONFIG.CORECLK_FREQ {500} \ CONFIG.AXI_ADDR_WIDTH {32} \ CONFIG.AXI_DATA_WIDTH {128_bit} \ CONFIG.VENDOR_ID {10EE} \ From 891b7aba90ffc8848a58842c9c5ae035a692aea5 Mon Sep 17 00:00:00 2001 From: mbs0221 Date: Wed, 17 Mar 2021 11:08:53 +0800 Subject: [PATCH 12/26] update support for PCIe Endpoint Device --- .../vc709axi_to_pcie_x1.scala | 41 +++++++++---------- 1 file changed, 19 insertions(+), 22 deletions(-) diff --git a/src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala b/src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala index 3b7d8e8a..e5db5eb9 100644 --- a/src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala +++ b/src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala @@ -30,6 +30,8 @@ trait VC709AXIToPCIeX1IOClocksReset extends Bundle { //turn off linter: blackbox name must match verilog module class vc709axi_to_pcie_x1() extends BlackBox { + def AXI_ADDR_WIDTH = 64 + def AXI_DATA_WIDTH = 256 val io = new Bundle with VC709AXIToPCIeX1IOSerial with VC709AXIToPCIeX1IOClocksReset { // Global Signals @@ -46,7 +48,7 @@ class vc709axi_to_pcie_x1() extends BlackBox // AXI Slave Interface // write address val s_axi_awid = Bits(INPUT,4) - val s_axi_awaddr = Bits(INPUT,32) + val s_axi_awaddr = Bits(INPUT,AXI_ADDR_WIDTH) val s_axi_awregion = Bits(INPUT,4) val s_axi_awlen = Bits(INPUT,8) val s_axi_awsize = Bits(INPUT,3) @@ -54,8 +56,8 @@ class vc709axi_to_pcie_x1() extends BlackBox val s_axi_awvalid = Bool(INPUT) val s_axi_awready = Bool(OUTPUT) // write data - val s_axi_wdata = Bits(INPUT,128) // 64 - val s_axi_wstrb = Bits(INPUT,16) // 8 + val s_axi_wdata = Bits(INPUT,AXI_DATA_WIDTH) + val s_axi_wstrb = Bits(INPUT,16) val s_axi_wlast = Bool(INPUT) val s_axi_wvalid = Bool(INPUT) val s_axi_wready = Bool(OUTPUT) @@ -66,7 +68,7 @@ class vc709axi_to_pcie_x1() extends BlackBox val s_axi_bvalid = Bool(OUTPUT) // read address val s_axi_arid = Bits(INPUT,4) - val s_axi_araddr = Bits(INPUT,32) + val s_axi_araddr = Bits(INPUT,AXI_ADDR_WIDTH) val s_axi_arregion = Bits(INPUT,4) val s_axi_arlen = Bits(INPUT,8) val s_axi_arsize = Bits(INPUT,3) @@ -76,14 +78,14 @@ class vc709axi_to_pcie_x1() extends BlackBox //slave interface read data val s_axi_rready = Bool(INPUT) val s_axi_rid = Bits(OUTPUT,4) - val s_axi_rdata = Bits(OUTPUT,128) // 64 + val s_axi_rdata = Bits(OUTPUT,AXI_DATA_WIDTH) val s_axi_rresp = Bits(OUTPUT,2) val s_axi_rlast = Bool(OUTPUT) val s_axi_rvalid = Bool(OUTPUT) // AXI Master Interface // write address - val m_axi_awaddr = Bits(OUTPUT,32) + val m_axi_awaddr = Bits(OUTPUT,AXI_ADDR_WIDTH) val m_axi_awlen = Bits(OUTPUT,8) val m_axi_awsize = Bits(OUTPUT,3) val m_axi_awburst = Bits(OUTPUT,2) @@ -91,8 +93,8 @@ class vc709axi_to_pcie_x1() extends BlackBox val m_axi_awvalid = Bool(OUTPUT) val m_axi_awready = Bool(INPUT) // write data - val m_axi_wdata = Bits(OUTPUT,128) // 64 - val m_axi_wstrb = Bits(OUTPUT,16) // 8 + val m_axi_wdata = Bits(OUTPUT,AXI_DATA_WIDTH) + val m_axi_wstrb = Bits(OUTPUT,16) val m_axi_wlast = Bool(OUTPUT) val m_axi_wvalid = Bool(OUTPUT) val m_axi_wready = Bool(INPUT) @@ -101,7 +103,7 @@ class vc709axi_to_pcie_x1() extends BlackBox val m_axi_bresp = Bits(INPUT,2) val m_axi_bvalid = Bool(INPUT) // read address - val m_axi_araddr = Bits(OUTPUT,32) + val m_axi_araddr = Bits(OUTPUT,AXI_ADDR_WIDTH) val m_axi_arlen = Bits(OUTPUT,8) val m_axi_arsize = Bits(OUTPUT,3) val m_axi_arburst = Bits(OUTPUT,2) @@ -110,13 +112,13 @@ class vc709axi_to_pcie_x1() extends BlackBox val m_axi_arready = Bool(INPUT) // read data val m_axi_rready = Bool(OUTPUT) - val m_axi_rdata = Bits(INPUT,128) // 64 + val m_axi_rdata = Bits(INPUT,AXI_DATA_WIDTH) val m_axi_rresp = Bits(INPUT,2) val m_axi_rlast = Bool(INPUT) val m_axi_rvalid = Bool(INPUT) // AXI4-Lite Control Interface - val s_axi_ctl_awaddr = Bits(INPUT,28) // 32 + val s_axi_ctl_awaddr = Bits(INPUT,28) val s_axi_ctl_awvalid = Bool(INPUT) val s_axi_ctl_awready = Bool(OUTPUT) val s_axi_ctl_wdata = Bits(INPUT,32) @@ -126,7 +128,7 @@ class vc709axi_to_pcie_x1() extends BlackBox val s_axi_ctl_bresp = Bits(OUTPUT,2) val s_axi_ctl_bvalid = Bool(OUTPUT) val s_axi_ctl_bready = Bool(INPUT) - val s_axi_ctl_araddr = Bits(INPUT,28) // 32 + val s_axi_ctl_araddr = Bits(INPUT,28) val s_axi_ctl_arvalid = Bool(INPUT) val s_axi_ctl_arready = Bool(OUTPUT) val s_axi_ctl_rdata = Bits(OUTPUT,32) @@ -171,8 +173,8 @@ class VC709AXIToPCIeX1(implicit p:Parameters) extends LazyModule address = List(AddressSet(0x40000000L, 0x1fffffffL)), resources = Seq(Resource(device, "ranges")), executable = true, - supportsWrite = TransferSizes(1, 128), - supportsRead = TransferSizes(1, 128))), + supportsWrite = TransferSizes(1, 256), + supportsRead = TransferSizes(1, 256))), beatBytes = 8))) val control = AXI4SlaveNode(Seq(AXI4SlavePortParameters( @@ -295,8 +297,6 @@ class VC709AXIToPCIeX1(implicit p:Parameters) extends LazyModule m.aw.bits.len := blackbox.io.m_axi_awlen m.aw.bits.size := blackbox.io.m_axi_awsize m.aw.bits.burst := blackbox.io.m_axi_awburst - m.aw.bits.lock := blackbox.io.m_axi_awlock - m.aw.bits.cache := blackbox.io.m_axi_awcache m.aw.bits.prot := blackbox.io.m_axi_awprot m.aw.bits.qos := UInt(0) m.aw.valid := blackbox.io.m_axi_awvalid @@ -317,8 +317,6 @@ class VC709AXIToPCIeX1(implicit p:Parameters) extends LazyModule m.ar.bits.len := blackbox.io.m_axi_arlen m.ar.bits.size := blackbox.io.m_axi_arsize m.ar.bits.burst := blackbox.io.m_axi_arburst - m.ar.bits.lock := blackbox.io.m_axi_arlock - m.ar.bits.cache := blackbox.io.m_axi_arcache m.ar.bits.prot := blackbox.io.m_axi_arprot m.ar.bits.qos := UInt(0) m.ar.valid := blackbox.io.m_axi_arvalid @@ -348,7 +346,7 @@ class VC709AXIToPCIeX1(implicit p:Parameters) extends LazyModule CONFIG.PCIEBAR2AXIBAR_0 {0x00000000} \ CONFIG.PCIE_BLK_LOCN {X0Y0} \ CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \ - CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {2.5_GT/s} \ + CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \ CONFIG.PF0_DEVICE_ID {8018} \ CONFIG.PF0_REVISION_ID {0} \ CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10EE} \ @@ -361,9 +359,8 @@ class VC709AXIToPCIeX1(implicit p:Parameters) extends LazyModule CONFIG.PF0_BAR0_TYPE {Memory} \ CONFIG.PF0_SUB_CLASS_interface_menu {Other_memory_controller} \ CONFIG.REF_CLK_FREQ {100_MHz} \ - CONFIG.CORECLK_FREQ {500} \ - CONFIG.AXI_ADDR_WIDTH {32} \ - CONFIG.AXI_DATA_WIDTH {128_bit} \ + CONFIG.AXI_ADDR_WIDTH {64} \ + CONFIG.AXI_DATA_WIDTH {256_bit} \ CONFIG.VENDOR_ID {10EE} \ CONFIG.XLNX_REF_BOARD {VC709} \ CONFIG.axi_aclk_loopback {false} \ From 77cf5e0fe279fcdfba947bc9ff07f817aa0f1482 Mon Sep 17 00:00:00 2001 From: mbs0221 Date: Thu, 18 Mar 2021 10:06:15 +0800 Subject: [PATCH 13/26] support I2C for vc709 --- .../vc709axi_to_pcie_x1.scala | 29 +++++++++-------- .../scala/shell/xilinx/VC709NewShell.scala | 31 +++++++++++++------ 2 files changed, 35 insertions(+), 25 deletions(-) diff --git a/src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala b/src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala index e5db5eb9..f3b15227 100644 --- a/src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala +++ b/src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala @@ -13,11 +13,12 @@ import freechips.rocketchip.util.{ElaborationArtefacts} // IP VLNV: xilinx.com:customize_ip:vc709pcietoaxi:3.0 // Black Box Signals named _exactly_ as per Vivado generated verilog trait VC709AXIToPCIeX1IOSerial extends Bundle { + def NUM_LANES = 8 // PCIe Interface - val pci_exp_txp = Bits(OUTPUT, 8) - val pci_exp_txn = Bits(OUTPUT, 8) - val pci_exp_rxp = Bits(INPUT, 8) - val pci_exp_rxn = Bits(INPUT, 8) + val pci_exp_txp = Bits(OUTPUT,NUM_LANES) + val pci_exp_txn = Bits(OUTPUT,NUM_LANES) + val pci_exp_rxp = Bits(INPUT,NUM_LANES) + val pci_exp_rxn = Bits(INPUT,NUM_LANES) } trait VC709AXIToPCIeX1IOClocksReset extends Bundle { @@ -31,7 +32,7 @@ trait VC709AXIToPCIeX1IOClocksReset extends Bundle { class vc709axi_to_pcie_x1() extends BlackBox { def AXI_ADDR_WIDTH = 64 - def AXI_DATA_WIDTH = 256 + def AXI_DATA_WIDTH = 128 val io = new Bundle with VC709AXIToPCIeX1IOSerial with VC709AXIToPCIeX1IOClocksReset { // Global Signals @@ -42,8 +43,8 @@ class vc709axi_to_pcie_x1() extends BlackBox val intx_msi_request = Bool(INPUT) val intx_msi_grant = Bool(OUTPUT) val msi_enable = Bool(OUTPUT) - val msi_vector_num = Bits(INPUT, 5) val msi_vector_width = Bits(OUTPUT,3) + val msi_vector_num = Bits(INPUT,5) // AXI Slave Interface // write address @@ -173,8 +174,8 @@ class VC709AXIToPCIeX1(implicit p:Parameters) extends LazyModule address = List(AddressSet(0x40000000L, 0x1fffffffL)), resources = Seq(Resource(device, "ranges")), executable = true, - supportsWrite = TransferSizes(1, 256), - supportsRead = TransferSizes(1, 256))), + supportsWrite = TransferSizes(1, 128), + supportsRead = TransferSizes(1, 128))), beatBytes = 8))) val control = AXI4SlaveNode(Seq(AXI4SlavePortParameters( @@ -205,7 +206,7 @@ class VC709AXIToPCIeX1(implicit p:Parameters) extends LazyModule val io = IO(new Bundle { val port = new VC709AXIToPCIeX1IOBundle - val refclk = Bool(INPUT) // REFCLK is changed to refclk in 3.0 + val refclk = Bool(INPUT) }) val blackbox = Module(new vc709axi_to_pcie_x1) @@ -346,7 +347,7 @@ class VC709AXIToPCIeX1(implicit p:Parameters) extends LazyModule CONFIG.PCIEBAR2AXIBAR_0 {0x00000000} \ CONFIG.PCIE_BLK_LOCN {X0Y0} \ CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \ - CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \ + CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {2.5_GT/s} \ CONFIG.PF0_DEVICE_ID {8018} \ CONFIG.PF0_REVISION_ID {0} \ CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10EE} \ @@ -357,14 +358,12 @@ class VC709AXIToPCIeX1(implicit p:Parameters) extends LazyModule CONFIG.PF0_BAR0_SCALE {Gigabytes} \ CONFIG.PF0_BAR0_SIZE {4} \ CONFIG.PF0_BAR0_TYPE {Memory} \ + CONFIG.PF0_BASE_CLASS_MENU {Memory Controller} \ CONFIG.PF0_SUB_CLASS_interface_menu {Other_memory_controller} \ CONFIG.REF_CLK_FREQ {100_MHz} \ CONFIG.AXI_ADDR_WIDTH {64} \ - CONFIG.AXI_DATA_WIDTH {256_bit} \ + CONFIG.AXI_DATA_WIDTH {128_bit} \ CONFIG.VENDOR_ID {10EE} \ - CONFIG.XLNX_REF_BOARD {VC709} \ - CONFIG.axi_aclk_loopback {false} \ - CONFIG.en_ext_ch_gt_drp {false} \ - CONFIG.en_transceiver_status_ports {false} ] [get_ips vc709axi_to_pcie_x1]""" + CONFIG.XLNX_REF_BOARD {VC709}] [get_ips vc709axi_to_pcie_x1]""" ) } diff --git a/src/main/scala/shell/xilinx/VC709NewShell.scala b/src/main/scala/shell/xilinx/VC709NewShell.scala index 0a4f39b5..8be32a81 100644 --- a/src/main/scala/shell/xilinx/VC709NewShell.scala +++ b/src/main/scala/shell/xilinx/VC709NewShell.scala @@ -22,14 +22,6 @@ class SysClockVC709PlacedOverlay(val shell: VC709ShellBasicOverlays, name: Strin shell { InModuleBody { shell.xdc.addBoardPin(io.p, "clk_p") shell.xdc.addBoardPin(io.n, "clk_n") -// val packagePinsWithPackageIOs = Seq(("H19", IOPin(io.p)), -// ("G18", IOPin(io.n))) - -// packagePinsWithPackageIOs foreach { case (pin, io) => { -// shell.xdc.addPackagePin(io, pin) -// shell.xdc.addIOStandard(io, "DIFF_SSTL15") -// shell.xdc.addIOB(io) -// } } } } } @@ -39,6 +31,25 @@ class SysClockVC709ShellPlacer(shell: VC709ShellBasicOverlays, val shellInput: C def place(designInput: ClockInputDesignInput) = new SysClockVC709PlacedOverlay(shell, valName.name, designInput, shellInput) } +class I2CVC709PlacedOverlay(val shell: VC709ShellBasicOverlays, name: String, val designInput: I2CDesignInput, val shellInput: I2CShellInput) + extends I2CXilinxPlacedOverlay(name, designInput, shellInput) +{ + shell { InModuleBody { + val packagePinsWithPackageIOs = Seq(("AU32", IOPin(io.sda)), + ("AT35", IOPin(io.scl))) + + packagePinsWithPackageIOs foreach { case (pin, io) => { + shell.xdc.addPackagePin(io, pin) + shell.xdc.addIOStandard(io, "LVCMOS18") + shell.xdc.addIOB(io) + } } + } } +} +class I2CVC709ShellPlacer(val shell: VC709ShellBasicOverlays, val shellInput: I2CShellInput)(implicit val valName: ValName) + extends I2CShellPlacer[VC709ShellBasicOverlays] { + def place(designInput: I2CDesignInput) = new I2CVC709PlacedOverlay(shell, valName.name, designInput, shellInput) +} + class UARTVC709PlacedOverlay(val shell: VC709ShellBasicOverlays, name: String, val designInput: UARTDesignInput, val shellInput: UARTShellInput) extends UARTXilinxPlacedOverlay(name, designInput, shellInput, true) { @@ -178,7 +189,6 @@ class DDR3VC709PlacedOverlay(val shell: VC709ShellBasicOverlays, name: String, v } } shell.sdc.addGroup(clocks = Seq("clk_pll_i")) - // shell.sdc.addGroup(pins = Seq(mig.island.module.blackbox.io.ui_clk)) } class DDR3VC709ShellPlacer(shell: VC709ShellBasicOverlays, val shellInput: DDRShellInput)(implicit val valName: ValName) extends DDRShellPlacer[VC709ShellBasicOverlays] { @@ -252,7 +262,8 @@ abstract class VC709ShellBasicOverlays()(implicit p: Parameters) extends Series7 // val led = Seq.tabulate(8)(i => Overlay(LEDOverlayKey, new LEDVC709ShellPlacer(this, LEDShellInput(color = "red", number = i))(valName = ValName(s"led_$i")))) // val switch = Seq.tabulate(8)(i => Overlay(SwitchOverlayKey, new SwitchVC709ShellPlacer(this, SwitchShellInput(number = i))(valName = ValName(s"switch_$i")))) // val button = Seq.tabulate(5)(i => Overlay(ButtonOverlayKey, new ButtonVC709ShellPlacer(this, ButtonShellInput(number = i))(valName = ValName(s"button_$i")))) - val uart = Seq.tabulate(1)(i => Overlay(UARTOverlayKey, new UARTVC709ShellPlacer(this, UARTShellInput(index = 0)))) + val i2c = Seq.tabulate(1)(i => Overlay(I2COverlayKey, new I2CVC709ShellPlacer(this, I2CShellInput(index = i)))) + val uart = Seq.tabulate(1)(i => Overlay(UARTOverlayKey, new UARTVC709ShellPlacer(this, UARTShellInput(index = i)))) val jtag = Overlay(JTAGDebugOverlayKey, new JTAGDebugVC709ShellPlacer(this, JTAGDebugShellInput())) val chiplink = Overlay(ChipLinkOverlayKey, new ChipLinkVC709ShellPlacer(this, ChipLinkShellInput())) val ddr0 = Overlay(DDROverlayKey, new DDR3VC709ShellPlacer(this, DDRShellInput())) From 7bde86f07c38a88b215a9144044d80d0d0e0d80f Mon Sep 17 00:00:00 2001 From: mbs0221 Date: Sat, 20 Mar 2021 16:04:28 +0800 Subject: [PATCH 14/26] updata support PCIe in vc709 --- .../vc709axi_to_pcie_x1.scala | 25 ++++++++++++------ .../scala/shell/xilinx/VC709NewShell.scala | 20 +++++++------- xilinx/vc709/tcl/ios.tcl | 26 +++++-------------- 3 files changed, 35 insertions(+), 36 deletions(-) diff --git a/src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala b/src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala index f3b15227..8f8a9c89 100644 --- a/src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala +++ b/src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala @@ -92,6 +92,8 @@ class vc709axi_to_pcie_x1() extends BlackBox val m_axi_awburst = Bits(OUTPUT,2) val m_axi_awprot = Bits(OUTPUT,3) val m_axi_awvalid = Bool(OUTPUT) + val m_axi_awlock = Bits(OUTPUT,1) + val m_axi_awcache = Bits(OUTPUT,4) val m_axi_awready = Bool(INPUT) // write data val m_axi_wdata = Bits(OUTPUT,AXI_DATA_WIDTH) @@ -110,6 +112,8 @@ class vc709axi_to_pcie_x1() extends BlackBox val m_axi_arburst = Bits(OUTPUT,2) val m_axi_arprot = Bits(OUTPUT,3) val m_axi_arvalid = Bool(OUTPUT) + val m_axi_arlock = Bits(OUTPUT,1) + val m_axi_arcache = Bits(OUTPUT,4) val m_axi_arready = Bool(INPUT) // read data val m_axi_rready = Bool(OUTPUT) @@ -206,7 +210,7 @@ class VC709AXIToPCIeX1(implicit p:Parameters) extends LazyModule val io = IO(new Bundle { val port = new VC709AXIToPCIeX1IOBundle - val refclk = Bool(INPUT) + val refclk = Bool(INPUT) // REFCLK is changed to refclk in 3.0 }) val blackbox = Module(new vc709axi_to_pcie_x1) @@ -299,6 +303,8 @@ class VC709AXIToPCIeX1(implicit p:Parameters) extends LazyModule m.aw.bits.size := blackbox.io.m_axi_awsize m.aw.bits.burst := blackbox.io.m_axi_awburst m.aw.bits.prot := blackbox.io.m_axi_awprot + m.aw.bits.lock := blackbox.io.m_axi_awlock + m.aw.bits.cache := blackbox.io.m_axi_awcache m.aw.bits.qos := UInt(0) m.aw.valid := blackbox.io.m_axi_awvalid blackbox.io.m_axi_awready := m.aw.ready @@ -318,6 +324,8 @@ class VC709AXIToPCIeX1(implicit p:Parameters) extends LazyModule m.ar.bits.len := blackbox.io.m_axi_arlen m.ar.bits.size := blackbox.io.m_axi_arsize m.ar.bits.burst := blackbox.io.m_axi_arburst + m.ar.bits.lock := blackbox.io.m_axi_arlock + m.ar.bits.cache := blackbox.io.m_axi_arcache m.ar.bits.prot := blackbox.io.m_axi_arprot m.ar.bits.qos := UInt(0) m.ar.valid := blackbox.io.m_axi_arvalid @@ -341,14 +349,13 @@ class VC709AXIToPCIeX1(implicit p:Parameters) extends LazyModule CONFIG.AXIBAR_NUM {1} \ CONFIG.BASEADDR {0x00000000} \ CONFIG.HIGHADDR {0x03FFFFFF} \ - CONFIG.COMP_TIMEOUT {50ms} \ - CONFIG.DEVICE_PORT_TYPE {PCI_Express_Endpoint_Device} \ + CONFIG.DEVICE_PORT_TYPE {Root_Port_of_PCI_Express_Root_Complex} \ CONFIG.INCLUDE_BAROFFSET_REG {true} \ CONFIG.PCIEBAR2AXIBAR_0 {0x00000000} \ CONFIG.PCIE_BLK_LOCN {X0Y0} \ CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \ CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {2.5_GT/s} \ - CONFIG.PF0_DEVICE_ID {8018} \ + CONFIG.PF0_DEVICE_ID {7118} \ CONFIG.PF0_REVISION_ID {0} \ CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10EE} \ CONFIG.PF0_SUBSYSTEM_ID {0007} \ @@ -358,12 +365,14 @@ class VC709AXIToPCIeX1(implicit p:Parameters) extends LazyModule CONFIG.PF0_BAR0_SCALE {Gigabytes} \ CONFIG.PF0_BAR0_SIZE {4} \ CONFIG.PF0_BAR0_TYPE {Memory} \ - CONFIG.PF0_BASE_CLASS_MENU {Memory Controller} \ - CONFIG.PF0_SUB_CLASS_interface_menu {Other_memory_controller} \ + CONFIG.PF0_BASE_CLASS_MENU {Bridge_device} \ + CONFIG.PF0_SUB_CLASS_interface_menu {Host_bridge} \ + CONFIG.PF0_CLASS_CODE {0x060000} \ + CONFIG.COMP_TIMEOUT {50ms} \ CONFIG.REF_CLK_FREQ {100_MHz} \ CONFIG.AXI_ADDR_WIDTH {64} \ CONFIG.AXI_DATA_WIDTH {128_bit} \ - CONFIG.VENDOR_ID {10EE} \ - CONFIG.XLNX_REF_BOARD {VC709}] [get_ips vc709axi_to_pcie_x1]""" + CONFIG.C_S_AXI_SUPPORTS_NARROW_BURST {false} \ + CONFIG.XLNX_REF_BOARD {VC709} ] [get_ips vc709axi_to_pcie_x1]""" ) } diff --git a/src/main/scala/shell/xilinx/VC709NewShell.scala b/src/main/scala/shell/xilinx/VC709NewShell.scala index 8be32a81..c80dd77d 100644 --- a/src/main/scala/shell/xilinx/VC709NewShell.scala +++ b/src/main/scala/shell/xilinx/VC709NewShell.scala @@ -72,21 +72,21 @@ class UARTVC709ShellPlacer(val shell: VC709ShellBasicOverlays, val shellInput: U } class LEDVC709PlacedOverlay(val shell: VC709ShellBasicOverlays, name: String, val designInput: LEDDesignInput, val shellInput: LEDShellInput) - extends LEDXilinxPlacedOverlay(name, designInput, shellInput, boardPin = Some(s"leds_8bits_tri_o_${shellInput.number}")) + extends LEDXilinxPlacedOverlay(name, designInput, shellInput, boardPin = Some(s"leds_8bits_tri_o_${shellInput.number}"), ioStandard = "LVCMOS18") class LEDVC709ShellPlacer(val shell: VC709ShellBasicOverlays, val shellInput: LEDShellInput)(implicit val valName: ValName) extends LEDShellPlacer[VC709ShellBasicOverlays] { def place(designInput: LEDDesignInput) = new LEDVC709PlacedOverlay(shell, valName.name, designInput, shellInput) } class SwitchVC709PlacedOverlay(val shell: VC709ShellBasicOverlays, name: String, val designInput: SwitchDesignInput, val shellInput: SwitchShellInput) - extends SwitchXilinxPlacedOverlay(name, designInput, shellInput, boardPin = Some(s"dip_switches_tri_i_${shellInput.number}")) + extends SwitchXilinxPlacedOverlay(name, designInput, shellInput, boardPin = Some(s"dip_switches_tri_i_${shellInput.number}"), ioStandard = "LVCMOS18") class SwitchVC709ShellPlacer(val shell: VC709ShellBasicOverlays, val shellInput: SwitchShellInput)(implicit val valName: ValName) extends SwitchShellPlacer[VC709ShellBasicOverlays] { def place(designInput: SwitchDesignInput) = new SwitchVC709PlacedOverlay(shell, valName.name, designInput, shellInput) } class ButtonVC709PlacedOverlay(val shell: VC709ShellBasicOverlays, name: String, val designInput: ButtonDesignInput, val shellInput: ButtonShellInput) - extends ButtonXilinxPlacedOverlay(name, designInput, shellInput, boardPin = Some(s"push_buttons_5bits_tri_i_${shellInput.number}")) + extends ButtonXilinxPlacedOverlay(name, designInput, shellInput, boardPin = Some(s"push_buttons_5bits_tri_i_${shellInput.number}"), ioStandard = "LVCMOS18") class ButtonVC709ShellPlacer(val shell: VC709ShellBasicOverlays, val shellInput: ButtonShellInput)(implicit val valName: ValName) extends ButtonShellPlacer[VC709ShellBasicOverlays] { def place(designInput: ButtonDesignInput) = new ButtonVC709PlacedOverlay(shell, valName.name, designInput, shellInput) @@ -210,7 +210,10 @@ class PCIeVC709PlacedOverlay(val shell: VC709ShellBasicOverlays, name: String, v pcie.crossTLIn(pcie.control) := slaveSide val masterSide = pcie.crossTLOut(pcie.master) - def overlayOutput = PCIeOverlayOutput(pcieNode=NodeHandle(slaveSide, masterSide), intNode=pcie.crossIntOut(pcie.intnode)) + val pcieNode = NodeHandle(slaveSide, masterSide) + val intNode = pcie.crossIntOut(pcie.intnode) + + def overlayOutput = PCIeOverlayOutput(pcieNode, intNode) def ioFactory = new XilinxVC709PCIeX1Pads InModuleBody { bridge.bundle <> pcie.module.io } @@ -259,20 +262,19 @@ abstract class VC709ShellBasicOverlays()(implicit p: Parameters) extends Series7 // Order matters; ddr depends on sys_clock val sys_clock = Overlay(ClockInputOverlayKey, new SysClockVC709ShellPlacer(this, ClockInputShellInput())) - // val led = Seq.tabulate(8)(i => Overlay(LEDOverlayKey, new LEDVC709ShellPlacer(this, LEDShellInput(color = "red", number = i))(valName = ValName(s"led_$i")))) - // val switch = Seq.tabulate(8)(i => Overlay(SwitchOverlayKey, new SwitchVC709ShellPlacer(this, SwitchShellInput(number = i))(valName = ValName(s"switch_$i")))) - // val button = Seq.tabulate(5)(i => Overlay(ButtonOverlayKey, new ButtonVC709ShellPlacer(this, ButtonShellInput(number = i))(valName = ValName(s"button_$i")))) + val led = Seq.tabulate(8)(i => Overlay(LEDOverlayKey, new LEDVC709ShellPlacer(this, LEDShellInput(color = "red", number = i))(valName = ValName(s"led_$i")))) + val switch = Seq.tabulate(8)(i => Overlay(SwitchOverlayKey, new SwitchVC709ShellPlacer(this, SwitchShellInput(number = i))(valName = ValName(s"switch_$i")))) + val button = Seq.tabulate(5)(i => Overlay(ButtonOverlayKey, new ButtonVC709ShellPlacer(this, ButtonShellInput(number = i))(valName = ValName(s"button_$i")))) val i2c = Seq.tabulate(1)(i => Overlay(I2COverlayKey, new I2CVC709ShellPlacer(this, I2CShellInput(index = i)))) val uart = Seq.tabulate(1)(i => Overlay(UARTOverlayKey, new UARTVC709ShellPlacer(this, UARTShellInput(index = i)))) val jtag = Overlay(JTAGDebugOverlayKey, new JTAGDebugVC709ShellPlacer(this, JTAGDebugShellInput())) val chiplink = Overlay(ChipLinkOverlayKey, new ChipLinkVC709ShellPlacer(this, ChipLinkShellInput())) val ddr0 = Overlay(DDROverlayKey, new DDR3VC709ShellPlacer(this, DDRShellInput())) - val pcie = Overlay(PCIeOverlayKey, new PCIeVC709ShellPlacer(this, PCIeShellInput())) + val pcie = Overlay(PCIeOverlayKey, new PCIeVC709ShellPlacer(this, PCIeShellInput())(valName = ValName(s"pcie"))) } class VC709BaseShell()(implicit p: Parameters) extends VC709ShellBasicOverlays { - // val topDesign = LazyModule(p(BuildTop)(dp)).suggestName("chiptop") val topDesign = LazyModule(p(DesignKey)(designParameters)) // Place the sys_clock at the Shell if the user didn't ask for it diff --git a/xilinx/vc709/tcl/ios.tcl b/xilinx/vc709/tcl/ios.tcl index c3b959b6..7c08c0a9 100644 --- a/xilinx/vc709/tcl/ios.tcl +++ b/xilinx/vc709/tcl/ios.tcl @@ -54,23 +54,11 @@ set_property PACKAGE_PIN AR34 [get_ports uart_rtsn] set_property IOSTANDARD LVCMOS18 [get_ports uart_rtsn] set_property IOB TRUE [get_ports uart_rtsn] -## PCI Express -#FMC 1 refclk -set_property PACKAGE_PIN A10 [get_ports {pcie_REFCLK_rxp}] -set_property PACKAGE_PIN A9 [get_ports {pcie_REFCLK_rxn}] -create_clock -name pcie_ref_clk -period 10 [get_ports pcie_REFCLK_rxp] -set_input_jitter [get_clocks -of_objects [get_ports pcie_REFCLK_rxp]] 0.5 -#TX -set_property PACKAGE_PIN H4 [get_ports {pcie_pci_exp_txp}] -set_property PACKAGE_PIN H3 [get_ports {pcie_pci_exp_txn}] -#RX -set_property PACKAGE_PIN G6 [get_ports {pcie_pci_exp_rxp}] -set_property PACKAGE_PIN G5 [get_ports {pcie_pci_exp_rxn}] +## I2C +set_property PACKAGE_PIN AU32 [get_ports i2c_sda] +set_property IOSTANDARD LVCMOS18 [get_ports i2c_sda] +set_property IOB TRUE [get_cells -of_objects [all_fanout -flat -endpoints_only [get_ports i2c_sda]]] -## SDIO -# set_property -dict { PACKAGE_PIN AN30 IOSTANDARD LVCMOS18 IOB TRUE } [get_ports {sdio_clk}] -# set_property -dict { PACKAGE_PIN AP30 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_cmd}] -# set_property -dict { PACKAGE_PIN AR30 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_dat[0]}] -# set_property -dict { PACKAGE_PIN AU31 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_dat[1]}] -# set_property -dict { PACKAGE_PIN AV31 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_dat[2]}] -# set_property -dict { PACKAGE_PIN AT30 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_dat[3]}] +set_property PACKAGE_PIN AT35 [get_ports i2c_scl] +set_property IOSTANDARD LVCMOS18 [get_ports i2c_scl] +set_property IOB TRUE [get_cells -of_objects [all_fanout -flat -endpoints_only [get_ports i2c_scl]]] \ No newline at end of file From 03f1381f7bc02b9a94f89f0ea73a84c9b1a59288 Mon Sep 17 00:00:00 2001 From: mbs0221 Date: Thu, 25 Mar 2021 20:20:20 +0800 Subject: [PATCH 15/26] revert mofification of vc707 --- src/main/scala/shell/xilinx/VC707NewShell.scala | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/main/scala/shell/xilinx/VC707NewShell.scala b/src/main/scala/shell/xilinx/VC707NewShell.scala index 9e471c5d..64ef8310 100644 --- a/src/main/scala/shell/xilinx/VC707NewShell.scala +++ b/src/main/scala/shell/xilinx/VC707NewShell.scala @@ -156,11 +156,11 @@ class JTAGDebugVC707PlacedOverlay(val shell: VC707Shell, name: String, val desig #2 VREF 14 5V #18 GND 13 GND */ - val packagePinsWithPackageIOs = Seq(("R32", IOPin(io.jtag_TCK)), - ("W36", IOPin(io.jtag_TMS)), - ("W37", IOPin(io.jtag_TDI)), + val packagePinsWithPackageIOs = Seq(("AT42", IOPin(io.jtag_TCK)), + ("AR38", IOPin(io.jtag_TMS)), + ("AR39", IOPin(io.jtag_TDI)), ("AR42", IOPin(io.srst_n)), - ("V40", IOPin(io.jtag_TDO))) + ("AT40", IOPin(io.jtag_TDO))) packagePinsWithPackageIOs foreach { case (pin, io) => { shell.xdc.addPackagePin(io, pin) shell.xdc.addIOStandard(io, "LVCMOS18") From db60f066bed59a1945c5ceade950fd620abf7517 Mon Sep 17 00:00:00 2001 From: mbs0221 Date: Thu, 25 Mar 2021 20:25:31 +0800 Subject: [PATCH 16/26] remove irrelavent files --- .../scala/ip/xilinx/vc709mig/vc709-ddr.pin | 36 -- .../scala/ip/xilinx/vc709mig/vc709mig.tcl | 34 - .../scala/ip/xilinx/vc709mig/vc709mig8g.scala | 595 ------------------ xilinx/vc709/constraints/vc709mig4gb.ucf | 116 ---- xilinx/vc709/constraints/vc709mig8gb-C0.ucf | 116 ---- xilinx/vc709/constraints/vc709mig8gb-C1.ucf | 116 ---- xilinx/vc709/constraints/vc709mig8gb.ucf | 116 ---- 7 files changed, 1129 deletions(-) delete mode 100644 src/main/scala/ip/xilinx/vc709mig/vc709-ddr.pin delete mode 100644 src/main/scala/ip/xilinx/vc709mig/vc709mig.tcl delete mode 100644 src/main/scala/ip/xilinx/vc709mig/vc709mig8g.scala delete mode 100644 xilinx/vc709/constraints/vc709mig4gb.ucf delete mode 100644 xilinx/vc709/constraints/vc709mig8gb-C0.ucf delete mode 100644 xilinx/vc709/constraints/vc709mig8gb-C1.ucf delete mode 100644 xilinx/vc709/constraints/vc709mig8gb.ucf diff --git a/src/main/scala/ip/xilinx/vc709mig/vc709-ddr.pin b/src/main/scala/ip/xilinx/vc709mig/vc709-ddr.pin deleted file mode 100644 index 3fb3e2ff..00000000 --- a/src/main/scala/ip/xilinx/vc709mig/vc709-ddr.pin +++ /dev/null @@ -1,36 +0,0 @@ -// addr -"A20", "B19", "C20", "A19", "A17", "A16", "D20", "C18", "D17", "C19", "B21", "B17", "A15", "A21", "F17", "E17", -// ba -"D21", "C21", "D18", -// ctrl: ras_n, cas_n, we_n, reset_n, ck_p, ck_n, cke, cs_n, odt -"E20", "K17", "F20", "P18", "E19", "E18", "K19", "J17", "H20", -// dm -"M13", "K15", "F12", "A14", "C23", "D25", "C31", "F31", -// dq -"N14", "N13", "L14", "M14", "M12", "N15", "M11", "L12", "K14", "K13", "H13", "J13", "L16", "L15", "H14", "J15", -"E15", "E13", "F15", "E14", "G13", "G12", "F14", "G14", "B14", "C13", "B16", "D15", "D13", "E12", "C16", "D16", -"A24", "B23", "B27", "B26", "A22", "B22", "A25", "C24", "E24", "D23", "D26", "C25", "E23", "D22", "F22", "E22", -"A30", "D27", "A29", "C28", "D28", "B31", "A31", "A32", "E30", "F29", "F30", "F27", "C30", "E29", "F26", "D30", -// ddr3_dqs_n -"M16", "J12", "G16", "C14", "A27", "E25", "B29", "E28", -// ddr3_dqs_p -"N16", "K12", "H16", "C15", "A26", "F25", "B28", "E27", - - -// addr -"AN19", "AR19", "AP20", "AP17", "AP18", "AJ18", "AN16", "AM16", "AK18", "AK19", "AM17", "AM18", "AL17", "AK17", "AM19", "AL19", -// ba -"AR17", "AR18", "AN18", -// ctrl: ras_n, cas_n, we_n, reset_n, ck_p, ck_n, cke, cs_n, odt -"AV19", "AT20", "AU19", "BB19", "AT17", "AU17", "AW17", "AV16", "AT16", -// dm -"AT22", "AL22", "AU24", "BB23", "BB12", "AV15", "AK12", "AP13", -// dq -"AN24", "AM24", "AR22", "AR23", "AN23", "AM23", "AN21", "AP21", "AK23", "AJ23", "AL21", "AM21", "AJ21", "AJ20", "AK20", "AL20", -"AW22", "AW23", "AW21", "AV21", "AU23", "AV23", "AR24", "AT24", "BB24", "BA24", "AY23", "AY24", "AY25", "BA25", "BB21", "BA21", -"AY14", "AW15", "BB14", "BB13", "AW12", "AY13", "AY12", "BA12", "AU12", "AU13", "AT12", "AU14", "AV13", "AW13", "AT15", "AR15", -"AL15", "AJ15", "AK14", "AJ12", "AJ16", "AL16", "AJ13", "AK13", "AR14", "AT14", "AM12", "AP11", "AM13", "AN13", "AM11", "AN11", -// ddr3_dqs_n -"AP22", "AK22", "AU21", "BB22", "BA14", "AR12", "AL14", "AN14", -// ddr3_dqs_p -"AP23", "AJ22", "AT21", "BA22", "BA15", "AP12", "AK15", "AN15", \ No newline at end of file diff --git a/src/main/scala/ip/xilinx/vc709mig/vc709mig.tcl b/src/main/scala/ip/xilinx/vc709mig/vc709mig.tcl deleted file mode 100644 index 079c22ec..00000000 --- a/src/main/scala/ip/xilinx/vc709mig/vc709mig.tcl +++ /dev/null @@ -1,34 +0,0 @@ - # // ElaborationArtefacts.add( - # // "vc709mig4gb.vivado.tcl", - # // """ - # // create_bd_cell -type ip -vlvn xilinx.com:ip:mig_7series:3.0 vc709mig4gb -dir $ipdir -force - # // set_property -dict [list \ - # // CONFIG.AXI4_INTERFACE {true} \ - # // CONFIG.TARGET_FPGA {xc7vx690t-ffg1761/-2} \ - # // CONFIG.C0.ControllerType {DDR3_SDRAM} \ - # // CONFIG.C0.DDR3_TimePeriod {1250} \ - # // CONFIG.C0.DDR3_MemoryType {SODIMMs} \ - # // CONFIG.C0.DDR3_MemoryPart {MT8KTF51264HZ-1G9} \ - # // CONFIG.C0.DDR3_MemoryVoltage {1.5V} \ - # // CONFIG.C0.DDR3_BankMachineCnt {4} \ - # // CONFIG.C0.DDR3_Ordering {Normal} \ - # // CONFIG.C0_S_AXI_DATA_WIDTH {64} \ - # // CONFIG.C0_C_RD_WR_ARB_ALGORITHM {RD_PRI_REG} \ - # // CONFIG.C0_S_AXI_SUPPORTS_NARROW_BURST {0} \ - # // CONFIG.C0_S_AXI_ID_WIDTH {4} \ - # // CONFIG.InputClkFreq {200} \ - # // CONFIG.C0.DDR3_BurstType {Sequential} \ - # // CONFIG.C0.DDR3_OutputDriverImpedenceControl {RZQ/7} \ - # // CONFIG.C0.DDR3_ControllerChipSelectPin {enable} - # // CONFIG.C0.DDR3_OnDieTermination {RZQ/6} \ - # // CONFIG.UserMemoryAddressMap {BANK_ROW_COLUMN} \ - # // CONFIG.System_Clock {No_Buffer} \ - # // CONFIG.Reference_Clock {Use System Clock} \ - # // CONFIG.System_Reset_Polarity {ACTIVE HIGH} - # // CONFIG.Debug_Signal {Disable} \ - # // CONFIG.IOPowerReduction {ON} \ - # // CONFIG.DCI_Cascade {false} \ - # // CONFIG.BankSelectionFlag {false} \ - # // CONFIG.RESET_BOARD_INTERFACE {Custom} \ - # // ] [get_ips vc709mig4gb]""" - # // ) \ No newline at end of file diff --git a/src/main/scala/ip/xilinx/vc709mig/vc709mig8g.scala b/src/main/scala/ip/xilinx/vc709mig/vc709mig8g.scala deleted file mode 100644 index 306a74ac..00000000 --- a/src/main/scala/ip/xilinx/vc709mig/vc709mig8g.scala +++ /dev/null @@ -1,595 +0,0 @@ -// See LICENSE for license details. -package sifive.fpgashells.ip.xilinx.vc709mig8g - -import Chisel._ -import chisel3.experimental.{Analog,attach} -import freechips.rocketchip.util.{ElaborationArtefacts} -import freechips.rocketchip.util.GenericParameterizedBundle -import freechips.rocketchip.config._ - -// IP VLNV: xilinx.com:customize_ip:vc709mig:1.0 -// Black Box - -class VC709MIGIODDR(depth : BigInt) extends GenericParameterizedBundle(depth) { - require((depth==0x200000000L),"VC709MIGIODDR supports upto 8GB depth configuraton") - // DDR3 SODIMM 0 - val c0_ddr3_addr = Bits(OUTPUT,16) - val c0_ddr3_ba = Bits(OUTPUT,3) - val c0_ddr3_ras_n = Bool(OUTPUT) - val c0_ddr3_cas_n = Bool(OUTPUT) - val c0_ddr3_we_n = Bool(OUTPUT) - val c0_ddr3_reset_n = Bool(OUTPUT) - val c0_ddr3_ck_p = Bits(OUTPUT,1) - val c0_ddr3_ck_n = Bits(OUTPUT,1) - val c0_ddr3_cke = Bits(OUTPUT,1) - val c0_ddr3_cs_n = Bits(OUTPUT,1) - val c0_ddr3_dm = Bits(OUTPUT,8) - val c0_ddr3_odt = Bits(OUTPUT,1) - - val c0_ddr3_dq = Analog(64.W) - val c0_ddr3_dqs_n = Analog(8.W) - val c0_ddr3_dqs_p = Analog(8.W) - // DDR3 SODIMM 1 - val c1_ddr3_addr = Bits(OUTPUT,16) - val c1_ddr3_ba = Bits(OUTPUT,3) - val c1_ddr3_ras_n = Bool(OUTPUT) - val c1_ddr3_cas_n = Bool(OUTPUT) - val c1_ddr3_we_n = Bool(OUTPUT) - val c1_ddr3_reset_n = Bool(OUTPUT) - val c1_ddr3_ck_p = Bits(OUTPUT,1) - val c1_ddr3_ck_n = Bits(OUTPUT,1) - val c1_ddr3_cke = Bits(OUTPUT,1) - val c1_ddr3_cs_n = Bits(OUTPUT,1) - val c1_ddr3_dm = Bits(OUTPUT,8) - val c1_ddr3_odt = Bits(OUTPUT,1) - - val c1_ddr3_dq = Analog(64.W) - val c1_ddr3_dqs_n = Analog(8.W) - val c1_ddr3_dqs_p = Analog(8.W) -} - -//reused directly in io bundle for sifive.blocks.devices.xilinxvc709mig -trait VC709MIGIOClocksReset extends Bundle { - // DDR3 SODIMM 0 - //inputs - //"NO_BUFFER" clock source (must be connected to IBUF outside of IP) - val c0_sys_clk_i = Bool(INPUT) - //user interface signals - val c0_ui_clk = Clock(OUTPUT) - val c0_ui_clk_sync_rst = Bool(OUTPUT) - val c0_mmcm_locked = Bool(OUTPUT) - val c0_aresetn = Bool(INPUT) - //misc - val c0_init_calib_complete = Bool(OUTPUT) - // DDR3 SODIMM 1 - //inputs - //"NO_BUFFER" clock source (must be connected to IBUF outside of IP) - val c1_sys_clk_i = Bool(INPUT) - //user interface signals - val c1_ui_clk = Clock(OUTPUT) - val c1_ui_clk_sync_rst = Bool(OUTPUT) - val c1_mmcm_locked = Bool(OUTPUT) - val c1_aresetn = Bool(INPUT) - //misc - val c1_init_calib_complete = Bool(OUTPUT) - - // common part - val sys_rst = Bool(INPUT) -} - -//scalastyle:off -//turn off linter: blackbox name must match verilog module -class vc709mig(depth : BigInt)(implicit val p:Parameters) extends BlackBox -{ - require((depth<=0x200000000L),"vc709mig supports upto 8GB depth configuraton") - override def desiredName = "vc709mig8gb" - - val io = new VC709MIGIODDR(depth) with VC709MIGIOClocksReset { - - //axi_s [DDR3 SODIMM 0] - // User interface signals (DDR3 SODIMM 0) - val c0_app_sr_req = Bool(INPUT) - val c0_app_ref_req = Bool(INPUT) - val c0_app_zq_req = Bool(INPUT) - val c0_app_sr_active = Bool(OUTPUT) - val c0_app_ref_ack = Bool(OUTPUT) - val c0_app_zq_ack = Bool(OUTPUT) - - //slave interface write address ports - val c0_s_axi_awid = Bits(INPUT,4) - val c0_s_axi_awaddr = Bits(INPUT,32) - val c0_s_axi_awlen = Bits(INPUT,8) - val c0_s_axi_awsize = Bits(INPUT,3) - val c0_s_axi_awburst = Bits(INPUT,2) - val c0_s_axi_awlock = Bits(INPUT,1) - val c0_s_axi_awcache = Bits(INPUT,4) - val c0_s_axi_awprot = Bits(INPUT,3) - val c0_s_axi_awqos = Bits(INPUT,4) - val c0_s_axi_awvalid = Bool(INPUT) - val c0_s_axi_awready = Bool(OUTPUT) - //slave interface write data ports - val c0_s_axi_wdata = Bits(INPUT,64) - val c0_s_axi_wstrb = Bits(INPUT,8) - val c0_s_axi_wlast = Bool(INPUT) - val c0_s_axi_wvalid = Bool(INPUT) - val c0_s_axi_wready = Bool(OUTPUT) - //slave interface write response ports - val c0_s_axi_bready = Bool(INPUT) - val c0_s_axi_bid = Bits(OUTPUT,4) - val c0_s_axi_bresp = Bits(OUTPUT,2) - val c0_s_axi_bvalid = Bool(OUTPUT) - //slave interface read address ports - val c0_s_axi_arid = Bits(INPUT,4) - val c0_s_axi_araddr = Bits(INPUT,32) - val c0_s_axi_arlen = Bits(INPUT,8) - val c0_s_axi_arsize = Bits(INPUT,3) - val c0_s_axi_arburst = Bits(INPUT,2) - val c0_s_axi_arlock = Bits(INPUT,1) - val c0_s_axi_arcache = Bits(INPUT,4) - val c0_s_axi_arprot = Bits(INPUT,3) - val c0_s_axi_arqos = Bits(INPUT,4) - val c0_s_axi_arvalid = Bool(INPUT) - val c0_s_axi_arready = Bool(OUTPUT) - //slave interface read data ports - val c0_s_axi_rready = Bool(INPUT) - val c0_s_axi_rid = Bits(OUTPUT,4) - val c0_s_axi_rdata = Bits(OUTPUT,64) - val c0_s_axi_rresp = Bits(OUTPUT,2) - val c0_s_axi_rlast = Bool(OUTPUT) - val c0_s_axi_rvalid = Bool(OUTPUT) - //misc - val c0_device_temp = Bits(OUTPUT,12) - - - //axi_s [DDR3 SODIMM 1] - // User interface signals (DDR3 SODIMM 0) - val c1_app_sr_req = Bool(INPUT) - val c1_app_ref_req = Bool(INPUT) - val c1_app_zq_req = Bool(INPUT) - val c1_app_sr_active = Bool(OUTPUT) - val c1_app_ref_ack = Bool(OUTPUT) - val c1_app_zq_ack = Bool(OUTPUT) - - //slave interface write address ports - val c1_s_axi_awid = Bits(INPUT,4) - val c1_s_axi_awaddr = Bits(INPUT,32) - val c1_s_axi_awlen = Bits(INPUT,8) - val c1_s_axi_awsize = Bits(INPUT,3) - val c1_s_axi_awburst = Bits(INPUT,2) - val c1_s_axi_awlock = Bits(INPUT,1) - val c1_s_axi_awcache = Bits(INPUT,4) - val c1_s_axi_awprot = Bits(INPUT,3) - val c1_s_axi_awqos = Bits(INPUT,4) - val c1_s_axi_awvalid = Bool(INPUT) - val c1_s_axi_awready = Bool(OUTPUT) - //slave interface write data ports - val c1_s_axi_wdata = Bits(INPUT,64) - val c1_s_axi_wstrb = Bits(INPUT,8) - val c1_s_axi_wlast = Bool(INPUT) - val c1_s_axi_wvalid = Bool(INPUT) - val c1_s_axi_wready = Bool(OUTPUT) - //slave interface write response ports - val c1_s_axi_bready = Bool(INPUT) - val c1_s_axi_bid = Bits(OUTPUT,4) - val c1_s_axi_bresp = Bits(OUTPUT,2) - val c1_s_axi_bvalid = Bool(OUTPUT) - //slave interface read address ports - val c1_s_axi_arid = Bits(INPUT,4) - val c1_s_axi_araddr = Bits(INPUT,32) - val c1_s_axi_arlen = Bits(INPUT,8) - val c1_s_axi_arsize = Bits(INPUT,3) - val c1_s_axi_arburst = Bits(INPUT,2) - val c1_s_axi_arlock = Bits(INPUT,1) - val c1_s_axi_arcache = Bits(INPUT,4) - val c1_s_axi_arprot = Bits(INPUT,3) - val c1_s_axi_arqos = Bits(INPUT,4) - val c1_s_axi_arvalid = Bool(INPUT) - val c1_s_axi_arready = Bool(OUTPUT) - //slave interface read data ports - val c1_s_axi_rready = Bool(INPUT) - val c1_s_axi_rid = Bits(OUTPUT,4) - val c1_s_axi_rdata = Bits(OUTPUT,64) - val c1_s_axi_rresp = Bits(OUTPUT,2) - val c1_s_axi_rlast = Bool(OUTPUT) - val c1_s_axi_rvalid = Bool(OUTPUT) - //misc - val c1_device_temp = Bits(OUTPUT,12) - } - - var vc709mig8gbprj = """ { - - - vc709mig8gb - 1 - 1 - Disable - 1024 - ON - Enabled - xc7vx690t-ffg1761/-2 - 4.1 - No Buffer - Use System Clock - ACTIVE HIGH - FALSE - 0 - 50 Ohms - 0 - - DDR3_SDRAM/SODIMMs/MT8KTF51264HZ-1G9 - 1250 - 2.0V - 4:1 - 200 - 0 - 800 - 1.000 - 1 - 1 - 1 - 1 - 64 - 1 - 1 - Disabled - Normal - 4 - FALSE - - 16 - 10 - 3 - 1.5V - BANK_ROW_COLUMN - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 8 - Fixed - Sequential - 11 - Normal - No - Slow Exit - Enable - RZQ/7 - Disable - Enable - RZQ/6 - 0 - Disabled - Enabled - Output Buffer Enabled - Full Array - 8 - Enabled - Normal - Dynamic ODT off - AXI - - RD_PRI_REG - 32 - 64 - 4 - 0 - - - - - - DDR3_SDRAM/SODIMMs/MT8KTF51264HZ-1G9 - 1250 - 2.0V - 4:1 - 200 - 0 - 800 - 1.000 - 1 - 1 - 1 - 1 - 64 - 1 - 1 - Disabled - Normal - 4 - FALSE - - 16 - 10 - 3 - 1.5V - BANK_ROW_COLUMN - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 8 - Fixed - Sequential - 11 - Normal - No - Slow Exit - Enable - RZQ/7 - Disable - Enable - RZQ/6 - 0 - Disabled - Enabled - Output Buffer Enabled - Full Array - 8 - Enabled - Normal - Dynamic ODT off - AXI - - RD_PRI_REG - 32 - 64 - 4 - 0 - - - - -}""" - - val migprj = vc709mig8gbprj - - ElaborationArtefacts.add( - "vc709mig8gb.vivado.tcl", - """set migprj """++migprj++""" - set migprjfile {/vc709mig8gb.prj} - set migprjfilepath $ipdir$migprjfile - set fp [open $migprjfilepath w+] - puts $fp $migprj - close $fp - create_ip -vendor xilinx.com -library ip -name mig_7series -module_name vc709mig8gb -dir $ipdir -force - set_property CONFIG.XML_INPUT_FILE $migprjfilepath [get_ips vc709mig8gb] """ - ) -} -//scalastyle:on diff --git a/xilinx/vc709/constraints/vc709mig4gb.ucf b/xilinx/vc709/constraints/vc709mig4gb.ucf deleted file mode 100644 index c3dbb407..00000000 --- a/xilinx/vc709/constraints/vc709mig4gb.ucf +++ /dev/null @@ -1,116 +0,0 @@ -NET "ddr3_dq[0]" LOC = "N14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[1]" LOC = "N13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[2]" LOC = "L14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[3]" LOC = "M14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[4]" LOC = "M12" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[5]" LOC = "N15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[6]" LOC = "M11" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[7]" LOC = "L12" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[8]" LOC = "K14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[9]" LOC = "K13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[10]" LOC = "H13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[11]" LOC = "J13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[12]" LOC = "L16" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[13]" LOC = "L15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[14]" LOC = "H14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[15]" LOC = "J15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[16]" LOC = "E15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[17]" LOC = "E13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[18]" LOC = "F15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[19]" LOC = "E14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[20]" LOC = "G13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[21]" LOC = "G12" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[22]" LOC = "F14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[23]" LOC = "G14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[24]" LOC = "B14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[25]" LOC = "C13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[26]" LOC = "B16" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[27]" LOC = "D15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[28]" LOC = "D13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[29]" LOC = "E12" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[30]" LOC = "C16" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[31]" LOC = "D16" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[32]" LOC = "A24" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[33]" LOC = "B23" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[34]" LOC = "B27" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[35]" LOC = "B26" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[36]" LOC = "A22" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[37]" LOC = "B22" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[38]" LOC = "A25" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[39]" LOC = "C24" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[40]" LOC = "E24" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[41]" LOC = "D23" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[42]" LOC = "D26" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[43]" LOC = "C25" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[44]" LOC = "E23" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[45]" LOC = "D22" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[46]" LOC = "F22" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[47]" LOC = "E22" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[48]" LOC = "A30" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[49]" LOC = "D27" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[50]" LOC = "A29" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[51]" LOC = "C28" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[52]" LOC = "D28" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[53]" LOC = "B31" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[54]" LOC = "A31" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[55]" LOC = "A32" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[56]" LOC = "E30" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[57]" LOC = "F29" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[58]" LOC = "F30" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[59]" LOC = "F27" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[60]" LOC = "C30" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[61]" LOC = "E29" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[62]" LOC = "F26" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[63]" LOC = "D30" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dm[0]" LOC = "M13" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_dm[1]" LOC = "K15" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_dm[2]" LOC = "F12" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_dm[3]" LOC = "A14" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_dm[4]" LOC = "C23" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_dm[5]" LOC = "D25" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_dm[6]" LOC = "C31" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_dm[7]" LOC = "F31" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_p[0]" LOC = "N16" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_n[0]" LOC = "M16" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_p[1]" LOC = "K12" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_n[1]" LOC = "J12" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_p[2]" LOC = "H16" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_n[2]" LOC = "G16" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_p[3]" LOC = "C15" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_n[3]" LOC = "C14" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_p[4]" LOC = "A26" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_n[4]" LOC = "A27" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_p[5]" LOC = "F25" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_n[5]" LOC = "E25" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_p[6]" LOC = "B28" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_n[6]" LOC = "B29" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_p[7]" LOC = "E27" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_n[7]" LOC = "E28" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_addr[15]" LOC = "E17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[14]" LOC = "F17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[13]" LOC = "A21" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[12]" LOC = "A15" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[11]" LOC = "B17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[10]" LOC = "B21" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[9]" LOC = "C19" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[8]" LOC = "D17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[7]" LOC = "C18" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[6]" LOC = "D20" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[5]" LOC = "A16" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[4]" LOC = "A17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[3]" LOC = "A19" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[2]" LOC = "C20" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[1]" LOC = "B19" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[0]" LOC = "A20" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_ba[2]" LOC = "D18" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_ba[1]" LOC = "C21" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_ba[0]" LOC = "D21" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_ck_p[0]" LOC = "E19" | IOSTANDARD = DIFF_SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_ck_n[0]" LOC = "E18" | IOSTANDARD = DIFF_SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_ras_n" LOC = "E20" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_cas_n" LOC = "K17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_we_n" LOC = "F20" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_reset_n" LOC = "P18" | IOSTANDARD = LVCMOS15 | VCCAUX_IO = HIGH ; -NET "ddr3_cke[0]" LOC = "K19" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_odt[0]" LOC = "H20" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_cs_n[0]" LOC = "J17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; diff --git a/xilinx/vc709/constraints/vc709mig8gb-C0.ucf b/xilinx/vc709/constraints/vc709mig8gb-C0.ucf deleted file mode 100644 index c3dbb407..00000000 --- a/xilinx/vc709/constraints/vc709mig8gb-C0.ucf +++ /dev/null @@ -1,116 +0,0 @@ -NET "ddr3_dq[0]" LOC = "N14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[1]" LOC = "N13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[2]" LOC = "L14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[3]" LOC = "M14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[4]" LOC = "M12" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[5]" LOC = "N15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[6]" LOC = "M11" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[7]" LOC = "L12" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[8]" LOC = "K14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[9]" LOC = "K13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[10]" LOC = "H13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[11]" LOC = "J13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[12]" LOC = "L16" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[13]" LOC = "L15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[14]" LOC = "H14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[15]" LOC = "J15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[16]" LOC = "E15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[17]" LOC = "E13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[18]" LOC = "F15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[19]" LOC = "E14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[20]" LOC = "G13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[21]" LOC = "G12" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[22]" LOC = "F14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[23]" LOC = "G14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[24]" LOC = "B14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[25]" LOC = "C13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[26]" LOC = "B16" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[27]" LOC = "D15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[28]" LOC = "D13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[29]" LOC = "E12" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[30]" LOC = "C16" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[31]" LOC = "D16" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[32]" LOC = "A24" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[33]" LOC = "B23" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[34]" LOC = "B27" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[35]" LOC = "B26" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[36]" LOC = "A22" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[37]" LOC = "B22" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[38]" LOC = "A25" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[39]" LOC = "C24" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[40]" LOC = "E24" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[41]" LOC = "D23" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[42]" LOC = "D26" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[43]" LOC = "C25" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[44]" LOC = "E23" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[45]" LOC = "D22" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[46]" LOC = "F22" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[47]" LOC = "E22" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[48]" LOC = "A30" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[49]" LOC = "D27" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[50]" LOC = "A29" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[51]" LOC = "C28" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[52]" LOC = "D28" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[53]" LOC = "B31" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[54]" LOC = "A31" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[55]" LOC = "A32" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[56]" LOC = "E30" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[57]" LOC = "F29" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[58]" LOC = "F30" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[59]" LOC = "F27" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[60]" LOC = "C30" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[61]" LOC = "E29" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[62]" LOC = "F26" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[63]" LOC = "D30" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dm[0]" LOC = "M13" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_dm[1]" LOC = "K15" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_dm[2]" LOC = "F12" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_dm[3]" LOC = "A14" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_dm[4]" LOC = "C23" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_dm[5]" LOC = "D25" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_dm[6]" LOC = "C31" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_dm[7]" LOC = "F31" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_p[0]" LOC = "N16" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_n[0]" LOC = "M16" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_p[1]" LOC = "K12" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_n[1]" LOC = "J12" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_p[2]" LOC = "H16" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_n[2]" LOC = "G16" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_p[3]" LOC = "C15" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_n[3]" LOC = "C14" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_p[4]" LOC = "A26" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_n[4]" LOC = "A27" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_p[5]" LOC = "F25" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_n[5]" LOC = "E25" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_p[6]" LOC = "B28" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_n[6]" LOC = "B29" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_p[7]" LOC = "E27" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_n[7]" LOC = "E28" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_addr[15]" LOC = "E17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[14]" LOC = "F17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[13]" LOC = "A21" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[12]" LOC = "A15" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[11]" LOC = "B17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[10]" LOC = "B21" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[9]" LOC = "C19" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[8]" LOC = "D17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[7]" LOC = "C18" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[6]" LOC = "D20" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[5]" LOC = "A16" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[4]" LOC = "A17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[3]" LOC = "A19" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[2]" LOC = "C20" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[1]" LOC = "B19" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[0]" LOC = "A20" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_ba[2]" LOC = "D18" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_ba[1]" LOC = "C21" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_ba[0]" LOC = "D21" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_ck_p[0]" LOC = "E19" | IOSTANDARD = DIFF_SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_ck_n[0]" LOC = "E18" | IOSTANDARD = DIFF_SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_ras_n" LOC = "E20" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_cas_n" LOC = "K17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_we_n" LOC = "F20" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_reset_n" LOC = "P18" | IOSTANDARD = LVCMOS15 | VCCAUX_IO = HIGH ; -NET "ddr3_cke[0]" LOC = "K19" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_odt[0]" LOC = "H20" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_cs_n[0]" LOC = "J17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; diff --git a/xilinx/vc709/constraints/vc709mig8gb-C1.ucf b/xilinx/vc709/constraints/vc709mig8gb-C1.ucf deleted file mode 100644 index bf01ab95..00000000 --- a/xilinx/vc709/constraints/vc709mig8gb-C1.ucf +++ /dev/null @@ -1,116 +0,0 @@ -NET "ddr3_dq[0]" LOC = "AN24" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[1]" LOC = "AM24" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[2]" LOC = "AR22" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[3]" LOC = "AR23" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[4]" LOC = "AN23" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[5]" LOC = "AM23" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[6]" LOC = "AN21" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[7]" LOC = "AP21" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[8]" LOC = "AK23" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[9]" LOC = "AJ23" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[10]" LOC = "AL21" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[11]" LOC = "AM21" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[12]" LOC = "AJ21" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[13]" LOC = "AJ20" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[14]" LOC = "AK20" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[15]" LOC = "AL20" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[16]" LOC = "AW22" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[17]" LOC = "AW23" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[18]" LOC = "AW21" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[19]" LOC = "AV21" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[20]" LOC = "AU23" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[21]" LOC = "AV23" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[22]" LOC = "AR24" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[23]" LOC = "AT24" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[24]" LOC = "BB24" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[25]" LOC = "BA24" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[26]" LOC = "AY23" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[27]" LOC = "AY24" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[28]" LOC = "AY25" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[29]" LOC = "BA25" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[30]" LOC = "BB21" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[31]" LOC = "BA21" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[32]" LOC = "AY14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[33]" LOC = "AW15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[34]" LOC = "BB14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[35]" LOC = "BB13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[36]" LOC = "AW12" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[37]" LOC = "AY13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[38]" LOC = "AY12" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[39]" LOC = "BA12" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[40]" LOC = "AU12" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[41]" LOC = "AU13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[42]" LOC = "AT12" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[43]" LOC = "AU14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[44]" LOC = "AV13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[45]" LOC = "AW13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[46]" LOC = "AT15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[47]" LOC = "AR15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[48]" LOC = "AL15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[49]" LOC = "AJ15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[50]" LOC = "AK14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[51]" LOC = "AJ12" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[52]" LOC = "AJ16" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[53]" LOC = "AL16" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[54]" LOC = "AJ13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[55]" LOC = "AK13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[56]" LOC = "AR14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[57]" LOC = "AT14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[58]" LOC = "AM12" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[59]" LOC = "AP11" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[60]" LOC = "AM13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[61]" LOC = "AN13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[62]" LOC = "AM11" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[63]" LOC = "AN11" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dm[0]" LOC = "AT22" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_dm[1]" LOC = "AL22" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_dm[2]" LOC = "AU24" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_dm[3]" LOC = "BB23" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_dm[4]" LOC = "BB12" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_dm[5]" LOC = "AV15" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_dm[6]" LOC = "AK12" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_dm[7]" LOC = "AP13" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_p[0]" LOC = "AP23" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_n[0]" LOC = "AP22" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_p[1]" LOC = "AJ22" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_n[1]" LOC = "AK22" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_p[2]" LOC = "AT21" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_n[2]" LOC = "AU21" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_p[3]" LOC = "BA22" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_n[3]" LOC = "BB22" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_p[4]" LOC = "BA15" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_n[4]" LOC = "BA14" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_p[5]" LOC = "AP12" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_n[5]" LOC = "AR12" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_p[6]" LOC = "AK15" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_n[6]" LOC = "AL14" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_p[7]" LOC = "AN15" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_n[7]" LOC = "AN14" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_addr[15]" LOC = "AL19" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[14]" LOC = "AM19" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[13]" LOC = "AK17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[12]" LOC = "AL17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[11]" LOC = "AM18" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[10]" LOC = "AM17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[9]" LOC = "AK19" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[8]" LOC = "AK18" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[7]" LOC = "AM16" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[6]" LOC = "AN16" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[5]" LOC = "AJ18" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[4]" LOC = "AP18" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[3]" LOC = "AP17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[2]" LOC = "AP20" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[1]" LOC = "AR19" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[0]" LOC = "AN19" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_ba[2]" LOC = "AN18" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_ba[1]" LOC = "AR18" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_ba[0]" LOC = "AR17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_ck_p[0]" LOC = "AT17" | IOSTANDARD = DIFF_SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_ck_n[0]" LOC = "AU17" | IOSTANDARD = DIFF_SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_ras_n" LOC = "AV19" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_cas_n" LOC = "AT20" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_we_n" LOC = "AU19" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_reset_n" LOC = "BB19" | IOSTANDARD = LVCMOS15 | VCCAUX_IO = HIGH ; -NET "ddr3_cke[0]" LOC = "AW17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_odt[0]" LOC = "AT16" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_cs_n[0]" LOC = "AV16" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; diff --git a/xilinx/vc709/constraints/vc709mig8gb.ucf b/xilinx/vc709/constraints/vc709mig8gb.ucf deleted file mode 100644 index bf01ab95..00000000 --- a/xilinx/vc709/constraints/vc709mig8gb.ucf +++ /dev/null @@ -1,116 +0,0 @@ -NET "ddr3_dq[0]" LOC = "AN24" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[1]" LOC = "AM24" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[2]" LOC = "AR22" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[3]" LOC = "AR23" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[4]" LOC = "AN23" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[5]" LOC = "AM23" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[6]" LOC = "AN21" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[7]" LOC = "AP21" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[8]" LOC = "AK23" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[9]" LOC = "AJ23" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[10]" LOC = "AL21" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[11]" LOC = "AM21" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[12]" LOC = "AJ21" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[13]" LOC = "AJ20" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[14]" LOC = "AK20" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[15]" LOC = "AL20" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[16]" LOC = "AW22" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[17]" LOC = "AW23" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[18]" LOC = "AW21" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[19]" LOC = "AV21" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[20]" LOC = "AU23" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[21]" LOC = "AV23" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[22]" LOC = "AR24" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[23]" LOC = "AT24" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[24]" LOC = "BB24" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[25]" LOC = "BA24" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[26]" LOC = "AY23" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[27]" LOC = "AY24" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[28]" LOC = "AY25" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[29]" LOC = "BA25" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[30]" LOC = "BB21" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[31]" LOC = "BA21" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[32]" LOC = "AY14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[33]" LOC = "AW15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[34]" LOC = "BB14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[35]" LOC = "BB13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[36]" LOC = "AW12" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[37]" LOC = "AY13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[38]" LOC = "AY12" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[39]" LOC = "BA12" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[40]" LOC = "AU12" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[41]" LOC = "AU13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[42]" LOC = "AT12" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[43]" LOC = "AU14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[44]" LOC = "AV13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[45]" LOC = "AW13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[46]" LOC = "AT15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[47]" LOC = "AR15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[48]" LOC = "AL15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[49]" LOC = "AJ15" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[50]" LOC = "AK14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[51]" LOC = "AJ12" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[52]" LOC = "AJ16" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[53]" LOC = "AL16" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[54]" LOC = "AJ13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[55]" LOC = "AK13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[56]" LOC = "AR14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[57]" LOC = "AT14" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[58]" LOC = "AM12" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[59]" LOC = "AP11" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[60]" LOC = "AM13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[61]" LOC = "AN13" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[62]" LOC = "AM11" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dq[63]" LOC = "AN11" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dm[0]" LOC = "AT22" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_dm[1]" LOC = "AL22" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_dm[2]" LOC = "AU24" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_dm[3]" LOC = "BB23" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_dm[4]" LOC = "BB12" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_dm[5]" LOC = "AV15" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_dm[6]" LOC = "AK12" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_dm[7]" LOC = "AP13" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_p[0]" LOC = "AP23" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_n[0]" LOC = "AP22" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_p[1]" LOC = "AJ22" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_n[1]" LOC = "AK22" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_p[2]" LOC = "AT21" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_n[2]" LOC = "AU21" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_p[3]" LOC = "BA22" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_n[3]" LOC = "BB22" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_p[4]" LOC = "BA15" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_n[4]" LOC = "BA14" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_p[5]" LOC = "AP12" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_n[5]" LOC = "AR12" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_p[6]" LOC = "AK15" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_n[6]" LOC = "AL14" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_p[7]" LOC = "AN15" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_n[7]" LOC = "AN14" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ; -NET "ddr3_addr[15]" LOC = "AL19" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[14]" LOC = "AM19" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[13]" LOC = "AK17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[12]" LOC = "AL17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[11]" LOC = "AM18" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[10]" LOC = "AM17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[9]" LOC = "AK19" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[8]" LOC = "AK18" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[7]" LOC = "AM16" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[6]" LOC = "AN16" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[5]" LOC = "AJ18" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[4]" LOC = "AP18" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[3]" LOC = "AP17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[2]" LOC = "AP20" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[1]" LOC = "AR19" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_addr[0]" LOC = "AN19" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_ba[2]" LOC = "AN18" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_ba[1]" LOC = "AR18" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_ba[0]" LOC = "AR17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_ck_p[0]" LOC = "AT17" | IOSTANDARD = DIFF_SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_ck_n[0]" LOC = "AU17" | IOSTANDARD = DIFF_SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_ras_n" LOC = "AV19" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_cas_n" LOC = "AT20" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_we_n" LOC = "AU19" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_reset_n" LOC = "BB19" | IOSTANDARD = LVCMOS15 | VCCAUX_IO = HIGH ; -NET "ddr3_cke[0]" LOC = "AW17" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_odt[0]" LOC = "AT16" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; -NET "ddr3_cs_n[0]" LOC = "AV16" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ; From c6d0a67f95291d94e47368a24837e96aabed0c97 Mon Sep 17 00:00:00 2001 From: mbs0221 Date: Thu, 25 Mar 2021 20:26:41 +0800 Subject: [PATCH 17/26] update ios.tcl --- xilinx/vc709/tcl/ios.tcl | 1 + 1 file changed, 1 insertion(+) diff --git a/xilinx/vc709/tcl/ios.tcl b/xilinx/vc709/tcl/ios.tcl index 7c08c0a9..4a6c1df0 100644 --- a/xilinx/vc709/tcl/ios.tcl +++ b/xilinx/vc709/tcl/ios.tcl @@ -25,6 +25,7 @@ set_property BOARD_PIN {push_buttons_5bits_tri_i_0} [get_ports btn_0] set_property BOARD_PIN {push_buttons_5bits_tri_i_1} [get_ports btn_1] set_property BOARD_PIN {push_buttons_5bits_tri_i_2} [get_ports btn_2] set_property BOARD_PIN {push_buttons_5bits_tri_i_3} [get_ports btn_3] +set_property BOARD_PIN {push_buttons_5bits_tri_i_4} [get_ports btn_4] ## SWITCH set_property BOARD_PIN {dip_switches_tri_i_0} [get_ports sw_0] From 1b6f6d3bb6764b7b6d356832f16f9a24e1b2c1d7 Mon Sep 17 00:00:00 2001 From: mbs0221 Date: Sat, 27 Mar 2021 20:49:56 +0800 Subject: [PATCH 18/26] add tcl scripts for uploading and booting from mcs files --- .../xilinxvc709mig/XilinxVC709MIG.scala | 7 +-- .../scala/shell/xilinx/VC709NewShell.scala | 2 +- xilinx/common/tcl/boot.tcl | 13 +++++ xilinx/common/tcl/upload_mcs.tcl | 54 +++++++++++++++++++ 4 files changed, 72 insertions(+), 4 deletions(-) create mode 100644 xilinx/common/tcl/boot.tcl create mode 100644 xilinx/common/tcl/upload_mcs.tcl diff --git a/src/main/scala/devices/xilinx/xilinxvc709mig/XilinxVC709MIG.scala b/src/main/scala/devices/xilinx/xilinxvc709mig/XilinxVC709MIG.scala index 35e6cdf1..bac63af0 100644 --- a/src/main/scala/devices/xilinx/xilinxvc709mig/XilinxVC709MIG.scala +++ b/src/main/scala/devices/xilinx/xilinxvc709mig/XilinxVC709MIG.scala @@ -23,11 +23,12 @@ class XilinxVC709MIGPads(depth : BigInt) extends VC709MIGIODDR(depth) { class XilinxVC709MIGIO(depth : BigInt) extends VC709MIGIODDR(depth) with VC709MIGIOClocksReset -class XilinxVC709MIGIsland(c : XilinxVC709MIGParams, val crossing: ClockCrossingType = AsynchronousCrossing(8))(implicit p: Parameters) extends LazyModule with CrossesToOnlyOneClockDomain { +class XilinxVC709MIGIsland(c : XilinxVC709MIGParams)(implicit p: Parameters) extends LazyModule with CrossesToOnlyOneClockDomain { val ranges = AddressRange.fromSets(c.address) require (ranges.size == 1, "DDR range must be contiguous") val offset = ranges.head.base val depth = ranges.head.size + val crossing = AsynchronousCrossing(8) require((depth<=0x100000000L),"vc709mig supports upto 4GB depth configuraton") val device = new MemoryDevice @@ -153,7 +154,7 @@ class XilinxVC709MIGIsland(c : XilinxVC709MIGParams, val crossing: ClockCrossing } } -class XilinxVC709MIG(c : XilinxVC709MIGParams, crossing: ClockCrossingType = AsynchronousCrossing(8))(implicit p: Parameters) extends LazyModule { +class XilinxVC709MIG(c : XilinxVC709MIGParams)(implicit p: Parameters) extends LazyModule { val ranges = AddressRange.fromSets(c.address) val depth = ranges.head.size @@ -163,7 +164,7 @@ class XilinxVC709MIG(c : XilinxVC709MIGParams, crossing: ClockCrossingType = Asy val indexer = LazyModule(new AXI4IdIndexer(idBits = 4)) val deint = LazyModule(new AXI4Deinterleaver(p(CacheBlockBytes))) val yank = LazyModule(new AXI4UserYanker) - val island = LazyModule(new XilinxVC709MIGIsland(c, crossing)) + val island = LazyModule(new XilinxVC709MIGIsland(c)) val node: TLInwardNode = island.crossAXI4In(island.node) := yank.node := deint.node := indexer.node := toaxi4.node := buffer.node diff --git a/src/main/scala/shell/xilinx/VC709NewShell.scala b/src/main/scala/shell/xilinx/VC709NewShell.scala index c80dd77d..70619b0b 100644 --- a/src/main/scala/shell/xilinx/VC709NewShell.scala +++ b/src/main/scala/shell/xilinx/VC709NewShell.scala @@ -188,7 +188,7 @@ class DDR3VC709PlacedOverlay(val shell: VC709ShellBasicOverlays, name: String, v port.aresetn := !ar.reset } } - shell.sdc.addGroup(clocks = Seq("clk_pll_i")) + shell.sdc.addGroup(pins = Seq(mig.island.module.blackbox.io.ui_clk)) } class DDR3VC709ShellPlacer(shell: VC709ShellBasicOverlays, val shellInput: DDRShellInput)(implicit val valName: ValName) extends DDRShellPlacer[VC709ShellBasicOverlays] { diff --git a/xilinx/common/tcl/boot.tcl b/xilinx/common/tcl/boot.tcl new file mode 100644 index 00000000..a24e18c2 --- /dev/null +++ b/xilinx/common/tcl/boot.tcl @@ -0,0 +1,13 @@ +if {$argc < 1 || $argc > 1} { + puts $argc + puts {Error: Invalid number of arguments} + puts {Usage: boot.tcl board} + exit 1 +} +lassign $argv board + +open_hw +connect_hw_server +open_hw_target +current_hw_device [get_hw_devices $board] +boot_hw_device [lindex [get_hw_devices $board] 0] \ No newline at end of file diff --git a/xilinx/common/tcl/upload_mcs.tcl b/xilinx/common/tcl/upload_mcs.tcl new file mode 100644 index 00000000..3b2a5184 --- /dev/null +++ b/xilinx/common/tcl/upload_mcs.tcl @@ -0,0 +1,54 @@ +# Upload an MCS-format memory configuration file to the board. + +if {$argc < 3 || $argc > 3} { + puts $argc + puts {Error: Invalid number of arguments} + puts {Usage: upload_mcs.tcl board mcsfile prmfile} + exit 1 +} +lassign $argv board mcsfile prmfile + +open_hw +connect_hw_server +open_hw_target + +current_hw_device [get_hw_devices $board] +refresh_hw_device -update_hw_probes false [lindex [get_hw_devices $board] 0] +refresh_hw_device [lindex [get_hw_devices $board] 0] + +create_hw_cfgmem -hw_device [lindex [get_hw_devices $board] 0] [lindex [get_cfgmem_parts {mt28gu01gaax1e-bpi-x16}] 0] +set_property PROGRAM.BLANK_CHECK 0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices $board] 0]] +set_property PROGRAM.ERASE 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices $board] 0]] +set_property PROGRAM.CFG_PROGRAM 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices $board] 0]] +set_property PROGRAM.VERIFY 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices $board] 0]] +set_property PROGRAM.CHECKSUM 0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices $board] 0]] +refresh_hw_device [lindex [get_hw_devices $board] 0] + +set_property PROGRAM.ADDRESS_RANGE {use_file} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices $board] 0]] +set_property PROGRAM.FILES [list $mcsfile ] [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices $board] 0]] +set_property PROGRAM.BPI_RS_PINS {none} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices $board] 0]] +set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices $board] 0]] +set_property PROGRAM.BLANK_CHECK 0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices $board] 0]] +set_property PROGRAM.ERASE 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices $board] 0]] +set_property PROGRAM.CFG_PROGRAM 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices $board] 0]] +set_property PROGRAM.VERIFY 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices $board] 0]] +set_property PROGRAM.CHECKSUM 0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices $board] 0]] +set_property PROGRAM.PRM_FILES [list $prmfile ] [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices $board] 0]] +set_property PROGRAM.ADDRESS_RANGE {use_file} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices $board] 0]] +set_property PROGRAM.FILES [list $mcsfile ] [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices $board] 0]] +set_property PROGRAM.PRM_FILE { $prmfile } [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices $board] 0]] +set_property PROGRAM.BPI_RS_PINS {none} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices $board] 0]] +set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices $board] 0]] +set_property PROGRAM.BLANK_CHECK 0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices $board] 0]] +set_property PROGRAM.ERASE 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices $board] 0]] +set_property PROGRAM.CFG_PROGRAM 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices $board] 0]] +set_property PROGRAM.VERIFY 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices $board] 0]] +set_property PROGRAM.CHECKSUM 0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices $board] 0]] + +startgroup + +if {![string equal [get_property PROGRAM.HW_CFGMEM_TYPE [lindex [get_hw_devices $board] 0]] [get_property MEM_TYPE [get_property CFGMEM_PART [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices $board] 0]]]]] } { + create_hw_bitstream -hw_device [lindex [get_hw_devices $board] 0] [get_property PROGRAM.HW_CFGMEM_BITFILE [ lindex [get_hw_devices $board] 0]]; + program_hw_devices [lindex [get_hw_devices $board] 0]; +}; +program_hw_cfgmem -hw_cfgmem [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices $board] 0]] From 9f1ca654d9a7ca75b6aac20e1846d58eb58b31ce Mon Sep 17 00:00:00 2001 From: mbs0221 Date: Thu, 1 Apr 2021 09:09:19 +0800 Subject: [PATCH 19/26] update PCIe support for vc709 --- .../xilinxvc709pciex1/XilinxVC709PCIeX1.scala | 76 ---- .../XilinxVC709PCIeX1Periphery.scala | 32 -- .../vc709axi_to_pcie_x1.scala | 378 ------------------ 3 files changed, 486 deletions(-) delete mode 100644 src/main/scala/devices/xilinx/xilinxvc709pciex1/XilinxVC709PCIeX1.scala delete mode 100644 src/main/scala/devices/xilinx/xilinxvc709pciex1/XilinxVC709PCIeX1Periphery.scala delete mode 100644 src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala diff --git a/src/main/scala/devices/xilinx/xilinxvc709pciex1/XilinxVC709PCIeX1.scala b/src/main/scala/devices/xilinx/xilinxvc709pciex1/XilinxVC709PCIeX1.scala deleted file mode 100644 index 1b45db02..00000000 --- a/src/main/scala/devices/xilinx/xilinxvc709pciex1/XilinxVC709PCIeX1.scala +++ /dev/null @@ -1,76 +0,0 @@ -// See LICENSE for license details. -package sifive.fpgashells.devices.xilinx.xilinxvc709pciex1 - -import Chisel._ -import freechips.rocketchip.amba.axi4._ -import freechips.rocketchip.config.Parameters -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.interrupts._ -import freechips.rocketchip.subsystem.{CrossesToOnlyOneClockDomain, CacheBlockBytes} -import sifive.fpgashells.ip.xilinx.vc709axi_to_pcie_x1.{VC709AXIToPCIeX1, VC709AXIToPCIeX1IOClocksReset, VC709AXIToPCIeX1IOSerial} -import sifive.fpgashells.ip.xilinx.ibufds_gte2.IBUFDS_GTE2 - -trait VC709AXIToPCIeRefClk extends Bundle{ - val REFCLK_rxp = Bool(INPUT) - val REFCLK_rxn = Bool(INPUT) -} - -class XilinxVC709PCIeX1Pads extends Bundle - with VC709AXIToPCIeX1IOSerial - with VC709AXIToPCIeRefClk - -class XilinxVC709PCIeX1IO extends Bundle - with VC709AXIToPCIeRefClk - with VC709AXIToPCIeX1IOSerial - with VC709AXIToPCIeX1IOClocksReset { - val axi_ctl_aresetn = Bool(INPUT) -} - -class XilinxVC709PCIeX1(implicit p: Parameters, val crossing: ClockCrossingType = AsynchronousCrossing(8)) - extends LazyModule with CrossesToOnlyOneClockDomain -{ - val axi_to_pcie_x1 = LazyModule(new VC709AXIToPCIeX1) - - val slave: TLInwardNode = - (axi_to_pcie_x1.slave - := AXI4Buffer() - := AXI4UserYanker() - := AXI4Deinterleaver(p(CacheBlockBytes)) - := AXI4IdIndexer(idBits=4) - := TLToAXI4(adapterName = Some("pcie-slave"))) - - val control: TLInwardNode = - (axi_to_pcie_x1.control - := AXI4Buffer() - := AXI4UserYanker(capMaxFlight = Some(2)) - := TLToAXI4() - := TLFragmenter(4, p(CacheBlockBytes), holdFirstDeny = true)) - - val master: TLOutwardNode = - (TLWidthWidget(8) - := AXI4ToTL() - := AXI4UserYanker(capMaxFlight=Some(8)) - := AXI4Fragmenter() - := axi_to_pcie_x1.master) - - val intnode: IntOutwardNode = axi_to_pcie_x1.intnode - - lazy val module = new LazyRawModuleImp(this) { - val io = IO(new Bundle { - val port = new XilinxVC709PCIeX1IO - }) - - childClock := io.port.axi_aclk // axi_aclk_out is changed to axi_aclk - childReset := ~io.port.axi_aresetn // - - io.port <> axi_to_pcie_x1.module.io.port - - //PCIe Reference Clock - val ibufds_gte2 = Module(new IBUFDS_GTE2) - axi_to_pcie_x1.module.io.refclk := ibufds_gte2.io.O // REFCLK is changed to refclk - ibufds_gte2.io.CEB := UInt(0) - ibufds_gte2.io.I := io.port.REFCLK_rxp - ibufds_gte2.io.IB := io.port.REFCLK_rxn - } -} diff --git a/src/main/scala/devices/xilinx/xilinxvc709pciex1/XilinxVC709PCIeX1Periphery.scala b/src/main/scala/devices/xilinx/xilinxvc709pciex1/XilinxVC709PCIeX1Periphery.scala deleted file mode 100644 index 15017561..00000000 --- a/src/main/scala/devices/xilinx/xilinxvc709pciex1/XilinxVC709PCIeX1Periphery.scala +++ /dev/null @@ -1,32 +0,0 @@ -// See LICENSE for license details. -package sifive.fpgashells.devices.xilinx.xilinxvc709pciex1 - -import Chisel._ -import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BufferParams} -import freechips.rocketchip.subsystem.BaseSubsystem -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.interrupts.IntSyncCrossingSink - -trait HasSystemXilinxVC709PCIeX1 { this: BaseSubsystem => - val xilinxvc709pcie = LazyModule(new XilinxVC709PCIeX1) - private val cname = "xilinxvc709pcie" - sbus.coupleFrom(s"master_named_$cname") { _ :=* TLFIFOFixer(TLFIFOFixer.all) :=* xilinxvc709pcie.crossTLOut(xilinxvc709pcie.master) } - sbus.coupleTo(s"slave_named_$cname") { xilinxvc709pcie.crossTLIn(xilinxvc709pcie.slave) :*= TLWidthWidget(sbus.beatBytes) :*= _ } - sbus.coupleTo(s"controller_named_$cname") { xilinxvc709pcie.crossTLIn(xilinxvc709pcie.control) :*= TLWidthWidget(sbus.beatBytes) :*= _ } - ibus.fromSync := xilinxvc709pcie.crossIntOut(xilinxvc709pcie.intnode) -} - -trait HasSystemXilinxVC709PCIeX1Bundle { - val xilinxvc709pcie: XilinxVC709PCIeX1IO - def connectXilinxVC709PCIeX1ToPads(pads: XilinxVC709PCIeX1Pads) { - pads <> xilinxvc709pcie - } -} - -trait HasSystemXilinxVC709PCIeX1ModuleImp extends LazyModuleImp - with HasSystemXilinxVC709PCIeX1Bundle { - val outer: HasSystemXilinxVC709PCIeX1 - val xilinxvc709pcie = IO(new XilinxVC709PCIeX1IO) - - xilinxvc709pcie <> outer.xilinxvc709pcie.module.io.port -} \ No newline at end of file diff --git a/src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala b/src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala deleted file mode 100644 index 8f8a9c89..00000000 --- a/src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala +++ /dev/null @@ -1,378 +0,0 @@ -// See LICENSE for license details. -package sifive.fpgashells.ip.xilinx.vc709axi_to_pcie_x1 - -import Chisel._ -import freechips.rocketchip.config._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.amba.axi4._ -import freechips.rocketchip.interrupts._ -import freechips.rocketchip.util.{ElaborationArtefacts} - -// AXI Bridge for PCI Express Gen3 Subsystem v3.0 -// Product Guide Vivado Design Suite PG194 (v3.0) July 22, 2020 -// IP VLNV: xilinx.com:customize_ip:vc709pcietoaxi:3.0 -// Black Box Signals named _exactly_ as per Vivado generated verilog -trait VC709AXIToPCIeX1IOSerial extends Bundle { - def NUM_LANES = 8 - // PCIe Interface - val pci_exp_txp = Bits(OUTPUT,NUM_LANES) - val pci_exp_txn = Bits(OUTPUT,NUM_LANES) - val pci_exp_rxp = Bits(INPUT,NUM_LANES) - val pci_exp_rxn = Bits(INPUT,NUM_LANES) -} - -trait VC709AXIToPCIeX1IOClocksReset extends Bundle { - // Global Signals - val axi_aresetn = Bool(INPUT) - val axi_aclk = Clock(OUTPUT) -} - -//scalastyle:off -//turn off linter: blackbox name must match verilog module -class vc709axi_to_pcie_x1() extends BlackBox -{ - def AXI_ADDR_WIDTH = 64 - def AXI_DATA_WIDTH = 128 - val io = new Bundle with VC709AXIToPCIeX1IOSerial - with VC709AXIToPCIeX1IOClocksReset { - // Global Signals - val refclk = Bool(INPUT) - val interrupt_out = Bool(OUTPUT) - - // AXI Bridge for PCIe Gen3 MSI Signals - val intx_msi_request = Bool(INPUT) - val intx_msi_grant = Bool(OUTPUT) - val msi_enable = Bool(OUTPUT) - val msi_vector_width = Bits(OUTPUT,3) - val msi_vector_num = Bits(INPUT,5) - - // AXI Slave Interface - // write address - val s_axi_awid = Bits(INPUT,4) - val s_axi_awaddr = Bits(INPUT,AXI_ADDR_WIDTH) - val s_axi_awregion = Bits(INPUT,4) - val s_axi_awlen = Bits(INPUT,8) - val s_axi_awsize = Bits(INPUT,3) - val s_axi_awburst = Bits(INPUT,2) - val s_axi_awvalid = Bool(INPUT) - val s_axi_awready = Bool(OUTPUT) - // write data - val s_axi_wdata = Bits(INPUT,AXI_DATA_WIDTH) - val s_axi_wstrb = Bits(INPUT,16) - val s_axi_wlast = Bool(INPUT) - val s_axi_wvalid = Bool(INPUT) - val s_axi_wready = Bool(OUTPUT) - // write response - val s_axi_bready = Bool(INPUT) - val s_axi_bid = Bits(OUTPUT,4) - val s_axi_bresp = Bits(OUTPUT,2) - val s_axi_bvalid = Bool(OUTPUT) - // read address - val s_axi_arid = Bits(INPUT,4) - val s_axi_araddr = Bits(INPUT,AXI_ADDR_WIDTH) - val s_axi_arregion = Bits(INPUT,4) - val s_axi_arlen = Bits(INPUT,8) - val s_axi_arsize = Bits(INPUT,3) - val s_axi_arburst = Bits(INPUT,2) - val s_axi_arvalid = Bool(INPUT) - val s_axi_arready = Bool(OUTPUT) - //slave interface read data - val s_axi_rready = Bool(INPUT) - val s_axi_rid = Bits(OUTPUT,4) - val s_axi_rdata = Bits(OUTPUT,AXI_DATA_WIDTH) - val s_axi_rresp = Bits(OUTPUT,2) - val s_axi_rlast = Bool(OUTPUT) - val s_axi_rvalid = Bool(OUTPUT) - - // AXI Master Interface - // write address - val m_axi_awaddr = Bits(OUTPUT,AXI_ADDR_WIDTH) - val m_axi_awlen = Bits(OUTPUT,8) - val m_axi_awsize = Bits(OUTPUT,3) - val m_axi_awburst = Bits(OUTPUT,2) - val m_axi_awprot = Bits(OUTPUT,3) - val m_axi_awvalid = Bool(OUTPUT) - val m_axi_awlock = Bits(OUTPUT,1) - val m_axi_awcache = Bits(OUTPUT,4) - val m_axi_awready = Bool(INPUT) - // write data - val m_axi_wdata = Bits(OUTPUT,AXI_DATA_WIDTH) - val m_axi_wstrb = Bits(OUTPUT,16) - val m_axi_wlast = Bool(OUTPUT) - val m_axi_wvalid = Bool(OUTPUT) - val m_axi_wready = Bool(INPUT) - // write response - val m_axi_bready = Bool(OUTPUT) - val m_axi_bresp = Bits(INPUT,2) - val m_axi_bvalid = Bool(INPUT) - // read address - val m_axi_araddr = Bits(OUTPUT,AXI_ADDR_WIDTH) - val m_axi_arlen = Bits(OUTPUT,8) - val m_axi_arsize = Bits(OUTPUT,3) - val m_axi_arburst = Bits(OUTPUT,2) - val m_axi_arprot = Bits(OUTPUT,3) - val m_axi_arvalid = Bool(OUTPUT) - val m_axi_arlock = Bits(OUTPUT,1) - val m_axi_arcache = Bits(OUTPUT,4) - val m_axi_arready = Bool(INPUT) - // read data - val m_axi_rready = Bool(OUTPUT) - val m_axi_rdata = Bits(INPUT,AXI_DATA_WIDTH) - val m_axi_rresp = Bits(INPUT,2) - val m_axi_rlast = Bool(INPUT) - val m_axi_rvalid = Bool(INPUT) - - // AXI4-Lite Control Interface - val s_axi_ctl_awaddr = Bits(INPUT,28) - val s_axi_ctl_awvalid = Bool(INPUT) - val s_axi_ctl_awready = Bool(OUTPUT) - val s_axi_ctl_wdata = Bits(INPUT,32) - val s_axi_ctl_wstrb = Bits(INPUT,4) - val s_axi_ctl_wvalid = Bool(INPUT) - val s_axi_ctl_wready = Bool(OUTPUT) - val s_axi_ctl_bresp = Bits(OUTPUT,2) - val s_axi_ctl_bvalid = Bool(OUTPUT) - val s_axi_ctl_bready = Bool(INPUT) - val s_axi_ctl_araddr = Bits(INPUT,28) - val s_axi_ctl_arvalid = Bool(INPUT) - val s_axi_ctl_arready = Bool(OUTPUT) - val s_axi_ctl_rdata = Bits(OUTPUT,32) - val s_axi_ctl_rresp = Bits(OUTPUT,2) - val s_axi_ctl_rvalid = Bool(OUTPUT) - val s_axi_ctl_rready = Bool(INPUT) - } -} -//scalastyle:off - -//wrap vc709_axi_to_pcie_x1 black box in Nasti Bundles -// see Chipyard doc: 9.1.2 Manager Node -class VC709AXIToPCIeX1(implicit p:Parameters) extends LazyModule -{ - // device-tree node - val device = new SimpleDevice("pci", Seq("xlnx,axi-pcie-host-1.00.a")) { - override def describe(resources: ResourceBindings): Description = { - val Description(name, mapping) = super.describe(resources) - val intc = "pcie_intc" - def ofInt(x: Int) = Seq(ResourceInt(BigInt(x))) - def ofMap(x: Int) = Seq(0, 0, 0, x).flatMap(ofInt) ++ Seq(ResourceReference(intc)) ++ ofInt(x) - val extra = Map( - "#address-cells" -> ofInt(3), - "#size-cells" -> ofInt(2), - "#interrupt-cells" -> ofInt(1), - "device_type" -> Seq(ResourceString("pci")), - "interrupt-map-mask" -> Seq(0, 0, 0, 7).flatMap(ofInt), - "interrupt-map" -> Seq(1, 2, 3, 4).flatMap(ofMap), - "ranges" -> resources("ranges").map(x => - (x: @unchecked) match { case Binding(_, ResourceAddress(address, perms)) => - ResourceMapping(address, BigInt(0x02000000) << 64, perms) }), - "interrupt-controller" -> Seq(ResourceMap(labels = Seq(intc), value = Map( - "interrupt-controller" -> Nil, - "#address-cells" -> ofInt(0), - "#interrupt-cells" -> ofInt(1))))) - Description(name, mapping ++ extra) - } - } - - val slave = AXI4SlaveNode(Seq(AXI4SlavePortParameters( - slaves = Seq(AXI4SlaveParameters( - address = List(AddressSet(0x40000000L, 0x1fffffffL)), - resources = Seq(Resource(device, "ranges")), - executable = true, - supportsWrite = TransferSizes(1, 128), - supportsRead = TransferSizes(1, 128))), - beatBytes = 8))) - - val control = AXI4SlaveNode(Seq(AXI4SlavePortParameters( - slaves = Seq(AXI4SlaveParameters( - address = List(AddressSet(0x2000000000L, 0x3ffffffL)), // when truncated to 32-bits, is 0 - resources = device.reg("control"), - supportsWrite = TransferSizes(1, 4), - supportsRead = TransferSizes(1, 4), - interleavedId = Some(0))), // AXI4-Lite never interleaves responses - beatBytes = 4))) - - val master = AXI4MasterNode(Seq(AXI4MasterPortParameters( - masters = Seq(AXI4MasterParameters( - name = "VC709 PCIe", - id = IdRange(0, 1), - aligned = false))))) - - val intnode = IntSourceNode(IntSourcePortSimple(resources = device.int)) - - lazy val module = new LazyModuleImp(this) { - // The master on the control port must be AXI-lite - require (control.edges.in(0).master.endId == 1) - // Must have exactly the right number of idBits - require (slave.edges.in(0).bundle.idBits == 4) - - class VC709AXIToPCIeX1IOBundle extends Bundle with VC709AXIToPCIeX1IOSerial - with VC709AXIToPCIeX1IOClocksReset; - - val io = IO(new Bundle { - val port = new VC709AXIToPCIeX1IOBundle - val refclk = Bool(INPUT) // REFCLK is changed to refclk in 3.0 - }) - - val blackbox = Module(new vc709axi_to_pcie_x1) - - val (s, _) = slave.in(0) - val (c, _) = control.in(0) - val (m, _) = master.out(0) - val (i, _) = intnode.out(0) - - //to top level - blackbox.io.axi_aresetn := io.port.axi_aresetn - io.port.axi_aclk := blackbox.io.axi_aclk - io.port.pci_exp_txp := blackbox.io.pci_exp_txp - io.port.pci_exp_txn := blackbox.io.pci_exp_txn - blackbox.io.pci_exp_rxp := io.port.pci_exp_rxp - blackbox.io.pci_exp_rxn := io.port.pci_exp_rxn - i(0) := blackbox.io.interrupt_out - blackbox.io.refclk := io.refclk - - // AXI Slave Interface - // write address - blackbox.io.s_axi_awid := s.aw.bits.id - blackbox.io.s_axi_awaddr := s.aw.bits.addr - blackbox.io.s_axi_awlen := s.aw.bits.len - blackbox.io.s_axi_awsize := s.aw.bits.size - blackbox.io.s_axi_awburst := s.aw.bits.burst - blackbox.io.s_axi_awregion := UInt(0) - blackbox.io.s_axi_awvalid := s.aw.valid - s.aw.ready := blackbox.io.s_axi_awready - // write data - blackbox.io.s_axi_wdata := s.w.bits.data - blackbox.io.s_axi_wstrb := s.w.bits.strb - blackbox.io.s_axi_wlast := s.w.bits.last - blackbox.io.s_axi_wvalid := s.w.valid - s.w.ready := blackbox.io.s_axi_wready - // write response - s.b.bits.id := blackbox.io.s_axi_bid - s.b.bits.resp := blackbox.io.s_axi_bresp - s.b.valid := blackbox.io.s_axi_bvalid - blackbox.io.s_axi_bready := s.b.ready - // read address - blackbox.io.s_axi_arid := s.ar.bits.id - blackbox.io.s_axi_araddr := s.ar.bits.addr - blackbox.io.s_axi_arlen := s.ar.bits.len - blackbox.io.s_axi_arsize := s.ar.bits.size - blackbox.io.s_axi_arburst := s.ar.bits.burst - blackbox.io.s_axi_arregion := UInt(0) - blackbox.io.s_axi_arvalid := s.ar.valid - s.ar.ready := blackbox.io.s_axi_arready - // read data - s.r.bits.id := blackbox.io.s_axi_rid - s.r.bits.data := blackbox.io.s_axi_rdata - s.r.bits.resp := blackbox.io.s_axi_rresp - s.r.bits.last := blackbox.io.s_axi_rlast - s.r.valid := blackbox.io.s_axi_rvalid - blackbox.io.s_axi_rready := s.r.ready - - // AXI4-Lite Control Interface - // write address - blackbox.io.s_axi_ctl_awaddr := c.aw.bits.addr - blackbox.io.s_axi_ctl_awvalid := c.aw.valid - c.aw.ready := blackbox.io.s_axi_ctl_awready - // write data - blackbox.io.s_axi_ctl_wdata := c.w.bits.data - blackbox.io.s_axi_ctl_wstrb := c.w.bits.strb - blackbox.io.s_axi_ctl_wvalid := c.w.valid - c.w.ready := blackbox.io.s_axi_ctl_wready - // write response - blackbox.io.s_axi_ctl_bready := c.b.ready - c.b.bits.id := UInt(0) - c.b.bits.resp := blackbox.io.s_axi_ctl_bresp - c.b.valid := blackbox.io.s_axi_ctl_bvalid - // read address - blackbox.io.s_axi_ctl_araddr := c.ar.bits.addr - blackbox.io.s_axi_ctl_arvalid := c.ar.valid - c.ar.ready := blackbox.io.s_axi_ctl_arready - // read data - blackbox.io.s_axi_ctl_rready := c.r.ready - c.r.bits.id := UInt(0) - c.r.bits.data := blackbox.io.s_axi_ctl_rdata - c.r.bits.resp := blackbox.io.s_axi_ctl_rresp - c.r.bits.last := Bool(true) - c.r.valid := blackbox.io.s_axi_ctl_rvalid - - // AXI Master Interface - // write address - m.aw.bits.id := UInt(0) - m.aw.bits.addr := blackbox.io.m_axi_awaddr - m.aw.bits.len := blackbox.io.m_axi_awlen - m.aw.bits.size := blackbox.io.m_axi_awsize - m.aw.bits.burst := blackbox.io.m_axi_awburst - m.aw.bits.prot := blackbox.io.m_axi_awprot - m.aw.bits.lock := blackbox.io.m_axi_awlock - m.aw.bits.cache := blackbox.io.m_axi_awcache - m.aw.bits.qos := UInt(0) - m.aw.valid := blackbox.io.m_axi_awvalid - blackbox.io.m_axi_awready := m.aw.ready - // write data - m.w.bits.data := blackbox.io.m_axi_wdata - m.w.bits.strb := blackbox.io.m_axi_wstrb - m.w.bits.last := blackbox.io.m_axi_wlast - m.w.valid := blackbox.io.m_axi_wvalid - blackbox.io.m_axi_wready := m.w.ready - // write response - blackbox.io.m_axi_bresp := m.b.bits.resp - blackbox.io.m_axi_bvalid := m.b.valid - m.b.ready := blackbox.io.m_axi_bready - // read address - m.ar.bits.id := UInt(0) - m.ar.bits.addr := blackbox.io.m_axi_araddr - m.ar.bits.len := blackbox.io.m_axi_arlen - m.ar.bits.size := blackbox.io.m_axi_arsize - m.ar.bits.burst := blackbox.io.m_axi_arburst - m.ar.bits.lock := blackbox.io.m_axi_arlock - m.ar.bits.cache := blackbox.io.m_axi_arcache - m.ar.bits.prot := blackbox.io.m_axi_arprot - m.ar.bits.qos := UInt(0) - m.ar.valid := blackbox.io.m_axi_arvalid - blackbox.io.m_axi_arready := m.ar.ready - // read data - blackbox.io.m_axi_rdata := m.r.bits.data - blackbox.io.m_axi_rresp := m.r.bits.resp - blackbox.io.m_axi_rlast := m.r.bits.last - blackbox.io.m_axi_rvalid := m.r.valid - m.r.ready := blackbox.io.m_axi_rready - } - - ElaborationArtefacts.add( - "vc709axi_to_pcie_x1.vivado.tcl", - """ - create_ip -vendor xilinx.com -library ip -version 3.0 -name axi_pcie3 -module_name vc709axi_to_pcie_x1 -dir $ipdir -force - set_property -dict [list \ - CONFIG.AXIBAR2PCIEBAR_0 {0x40000000} \ - CONFIG.AXIBAR_0 {0x40000000} \ - CONFIG.AXIBAR_HIGHADDR_0 {0x5FFFFFFF} \ - CONFIG.AXIBAR_NUM {1} \ - CONFIG.BASEADDR {0x00000000} \ - CONFIG.HIGHADDR {0x03FFFFFF} \ - CONFIG.DEVICE_PORT_TYPE {Root_Port_of_PCI_Express_Root_Complex} \ - CONFIG.INCLUDE_BAROFFSET_REG {true} \ - CONFIG.PCIEBAR2AXIBAR_0 {0x00000000} \ - CONFIG.PCIE_BLK_LOCN {X0Y0} \ - CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \ - CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {2.5_GT/s} \ - CONFIG.PF0_DEVICE_ID {7118} \ - CONFIG.PF0_REVISION_ID {0} \ - CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10EE} \ - CONFIG.PF0_SUBSYSTEM_ID {0007} \ - CONFIG.PF0_BAR0_64BIT {true} \ - CONFIG.PF0_BAR0_ENABLED {true} \ - CONFIG.PF0_BAR0_PREFETCHABLE {false} \ - CONFIG.PF0_BAR0_SCALE {Gigabytes} \ - CONFIG.PF0_BAR0_SIZE {4} \ - CONFIG.PF0_BAR0_TYPE {Memory} \ - CONFIG.PF0_BASE_CLASS_MENU {Bridge_device} \ - CONFIG.PF0_SUB_CLASS_interface_menu {Host_bridge} \ - CONFIG.PF0_CLASS_CODE {0x060000} \ - CONFIG.COMP_TIMEOUT {50ms} \ - CONFIG.REF_CLK_FREQ {100_MHz} \ - CONFIG.AXI_ADDR_WIDTH {64} \ - CONFIG.AXI_DATA_WIDTH {128_bit} \ - CONFIG.C_S_AXI_SUPPORTS_NARROW_BURST {false} \ - CONFIG.XLNX_REF_BOARD {VC709} ] [get_ips vc709axi_to_pcie_x1]""" - ) -} From 7ee68ad352dbfdaa9131248ed0a64c0d6facdab9 Mon Sep 17 00:00:00 2001 From: mbs0221 Date: Thu, 1 Apr 2021 09:47:20 +0800 Subject: [PATCH 20/26] update support for pcie --- .../xilinxvc709pciex1/XilinxVC709PCIeX1.scala | 76 ++++ .../XilinxVC709PCIeX1Periphery.scala | 32 ++ .../vc709axi_to_pcie_x1.scala | 378 ++++++++++++++++++ 3 files changed, 486 insertions(+) create mode 100644 src/main/scala/devices/xilinx/xilinxvc709pciex1/XilinxVC709PCIeX1.scala create mode 100644 src/main/scala/devices/xilinx/xilinxvc709pciex1/XilinxVC709PCIeX1Periphery.scala create mode 100644 src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala diff --git a/src/main/scala/devices/xilinx/xilinxvc709pciex1/XilinxVC709PCIeX1.scala b/src/main/scala/devices/xilinx/xilinxvc709pciex1/XilinxVC709PCIeX1.scala new file mode 100644 index 00000000..1b45db02 --- /dev/null +++ b/src/main/scala/devices/xilinx/xilinxvc709pciex1/XilinxVC709PCIeX1.scala @@ -0,0 +1,76 @@ +// See LICENSE for license details. +package sifive.fpgashells.devices.xilinx.xilinxvc709pciex1 + +import Chisel._ +import freechips.rocketchip.amba.axi4._ +import freechips.rocketchip.config.Parameters +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.interrupts._ +import freechips.rocketchip.subsystem.{CrossesToOnlyOneClockDomain, CacheBlockBytes} +import sifive.fpgashells.ip.xilinx.vc709axi_to_pcie_x1.{VC709AXIToPCIeX1, VC709AXIToPCIeX1IOClocksReset, VC709AXIToPCIeX1IOSerial} +import sifive.fpgashells.ip.xilinx.ibufds_gte2.IBUFDS_GTE2 + +trait VC709AXIToPCIeRefClk extends Bundle{ + val REFCLK_rxp = Bool(INPUT) + val REFCLK_rxn = Bool(INPUT) +} + +class XilinxVC709PCIeX1Pads extends Bundle + with VC709AXIToPCIeX1IOSerial + with VC709AXIToPCIeRefClk + +class XilinxVC709PCIeX1IO extends Bundle + with VC709AXIToPCIeRefClk + with VC709AXIToPCIeX1IOSerial + with VC709AXIToPCIeX1IOClocksReset { + val axi_ctl_aresetn = Bool(INPUT) +} + +class XilinxVC709PCIeX1(implicit p: Parameters, val crossing: ClockCrossingType = AsynchronousCrossing(8)) + extends LazyModule with CrossesToOnlyOneClockDomain +{ + val axi_to_pcie_x1 = LazyModule(new VC709AXIToPCIeX1) + + val slave: TLInwardNode = + (axi_to_pcie_x1.slave + := AXI4Buffer() + := AXI4UserYanker() + := AXI4Deinterleaver(p(CacheBlockBytes)) + := AXI4IdIndexer(idBits=4) + := TLToAXI4(adapterName = Some("pcie-slave"))) + + val control: TLInwardNode = + (axi_to_pcie_x1.control + := AXI4Buffer() + := AXI4UserYanker(capMaxFlight = Some(2)) + := TLToAXI4() + := TLFragmenter(4, p(CacheBlockBytes), holdFirstDeny = true)) + + val master: TLOutwardNode = + (TLWidthWidget(8) + := AXI4ToTL() + := AXI4UserYanker(capMaxFlight=Some(8)) + := AXI4Fragmenter() + := axi_to_pcie_x1.master) + + val intnode: IntOutwardNode = axi_to_pcie_x1.intnode + + lazy val module = new LazyRawModuleImp(this) { + val io = IO(new Bundle { + val port = new XilinxVC709PCIeX1IO + }) + + childClock := io.port.axi_aclk // axi_aclk_out is changed to axi_aclk + childReset := ~io.port.axi_aresetn // + + io.port <> axi_to_pcie_x1.module.io.port + + //PCIe Reference Clock + val ibufds_gte2 = Module(new IBUFDS_GTE2) + axi_to_pcie_x1.module.io.refclk := ibufds_gte2.io.O // REFCLK is changed to refclk + ibufds_gte2.io.CEB := UInt(0) + ibufds_gte2.io.I := io.port.REFCLK_rxp + ibufds_gte2.io.IB := io.port.REFCLK_rxn + } +} diff --git a/src/main/scala/devices/xilinx/xilinxvc709pciex1/XilinxVC709PCIeX1Periphery.scala b/src/main/scala/devices/xilinx/xilinxvc709pciex1/XilinxVC709PCIeX1Periphery.scala new file mode 100644 index 00000000..15017561 --- /dev/null +++ b/src/main/scala/devices/xilinx/xilinxvc709pciex1/XilinxVC709PCIeX1Periphery.scala @@ -0,0 +1,32 @@ +// See LICENSE for license details. +package sifive.fpgashells.devices.xilinx.xilinxvc709pciex1 + +import Chisel._ +import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BufferParams} +import freechips.rocketchip.subsystem.BaseSubsystem +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.interrupts.IntSyncCrossingSink + +trait HasSystemXilinxVC709PCIeX1 { this: BaseSubsystem => + val xilinxvc709pcie = LazyModule(new XilinxVC709PCIeX1) + private val cname = "xilinxvc709pcie" + sbus.coupleFrom(s"master_named_$cname") { _ :=* TLFIFOFixer(TLFIFOFixer.all) :=* xilinxvc709pcie.crossTLOut(xilinxvc709pcie.master) } + sbus.coupleTo(s"slave_named_$cname") { xilinxvc709pcie.crossTLIn(xilinxvc709pcie.slave) :*= TLWidthWidget(sbus.beatBytes) :*= _ } + sbus.coupleTo(s"controller_named_$cname") { xilinxvc709pcie.crossTLIn(xilinxvc709pcie.control) :*= TLWidthWidget(sbus.beatBytes) :*= _ } + ibus.fromSync := xilinxvc709pcie.crossIntOut(xilinxvc709pcie.intnode) +} + +trait HasSystemXilinxVC709PCIeX1Bundle { + val xilinxvc709pcie: XilinxVC709PCIeX1IO + def connectXilinxVC709PCIeX1ToPads(pads: XilinxVC709PCIeX1Pads) { + pads <> xilinxvc709pcie + } +} + +trait HasSystemXilinxVC709PCIeX1ModuleImp extends LazyModuleImp + with HasSystemXilinxVC709PCIeX1Bundle { + val outer: HasSystemXilinxVC709PCIeX1 + val xilinxvc709pcie = IO(new XilinxVC709PCIeX1IO) + + xilinxvc709pcie <> outer.xilinxvc709pcie.module.io.port +} \ No newline at end of file diff --git a/src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala b/src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala new file mode 100644 index 00000000..8f8a9c89 --- /dev/null +++ b/src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala @@ -0,0 +1,378 @@ +// See LICENSE for license details. +package sifive.fpgashells.ip.xilinx.vc709axi_to_pcie_x1 + +import Chisel._ +import freechips.rocketchip.config._ +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.amba.axi4._ +import freechips.rocketchip.interrupts._ +import freechips.rocketchip.util.{ElaborationArtefacts} + +// AXI Bridge for PCI Express Gen3 Subsystem v3.0 +// Product Guide Vivado Design Suite PG194 (v3.0) July 22, 2020 +// IP VLNV: xilinx.com:customize_ip:vc709pcietoaxi:3.0 +// Black Box Signals named _exactly_ as per Vivado generated verilog +trait VC709AXIToPCIeX1IOSerial extends Bundle { + def NUM_LANES = 8 + // PCIe Interface + val pci_exp_txp = Bits(OUTPUT,NUM_LANES) + val pci_exp_txn = Bits(OUTPUT,NUM_LANES) + val pci_exp_rxp = Bits(INPUT,NUM_LANES) + val pci_exp_rxn = Bits(INPUT,NUM_LANES) +} + +trait VC709AXIToPCIeX1IOClocksReset extends Bundle { + // Global Signals + val axi_aresetn = Bool(INPUT) + val axi_aclk = Clock(OUTPUT) +} + +//scalastyle:off +//turn off linter: blackbox name must match verilog module +class vc709axi_to_pcie_x1() extends BlackBox +{ + def AXI_ADDR_WIDTH = 64 + def AXI_DATA_WIDTH = 128 + val io = new Bundle with VC709AXIToPCIeX1IOSerial + with VC709AXIToPCIeX1IOClocksReset { + // Global Signals + val refclk = Bool(INPUT) + val interrupt_out = Bool(OUTPUT) + + // AXI Bridge for PCIe Gen3 MSI Signals + val intx_msi_request = Bool(INPUT) + val intx_msi_grant = Bool(OUTPUT) + val msi_enable = Bool(OUTPUT) + val msi_vector_width = Bits(OUTPUT,3) + val msi_vector_num = Bits(INPUT,5) + + // AXI Slave Interface + // write address + val s_axi_awid = Bits(INPUT,4) + val s_axi_awaddr = Bits(INPUT,AXI_ADDR_WIDTH) + val s_axi_awregion = Bits(INPUT,4) + val s_axi_awlen = Bits(INPUT,8) + val s_axi_awsize = Bits(INPUT,3) + val s_axi_awburst = Bits(INPUT,2) + val s_axi_awvalid = Bool(INPUT) + val s_axi_awready = Bool(OUTPUT) + // write data + val s_axi_wdata = Bits(INPUT,AXI_DATA_WIDTH) + val s_axi_wstrb = Bits(INPUT,16) + val s_axi_wlast = Bool(INPUT) + val s_axi_wvalid = Bool(INPUT) + val s_axi_wready = Bool(OUTPUT) + // write response + val s_axi_bready = Bool(INPUT) + val s_axi_bid = Bits(OUTPUT,4) + val s_axi_bresp = Bits(OUTPUT,2) + val s_axi_bvalid = Bool(OUTPUT) + // read address + val s_axi_arid = Bits(INPUT,4) + val s_axi_araddr = Bits(INPUT,AXI_ADDR_WIDTH) + val s_axi_arregion = Bits(INPUT,4) + val s_axi_arlen = Bits(INPUT,8) + val s_axi_arsize = Bits(INPUT,3) + val s_axi_arburst = Bits(INPUT,2) + val s_axi_arvalid = Bool(INPUT) + val s_axi_arready = Bool(OUTPUT) + //slave interface read data + val s_axi_rready = Bool(INPUT) + val s_axi_rid = Bits(OUTPUT,4) + val s_axi_rdata = Bits(OUTPUT,AXI_DATA_WIDTH) + val s_axi_rresp = Bits(OUTPUT,2) + val s_axi_rlast = Bool(OUTPUT) + val s_axi_rvalid = Bool(OUTPUT) + + // AXI Master Interface + // write address + val m_axi_awaddr = Bits(OUTPUT,AXI_ADDR_WIDTH) + val m_axi_awlen = Bits(OUTPUT,8) + val m_axi_awsize = Bits(OUTPUT,3) + val m_axi_awburst = Bits(OUTPUT,2) + val m_axi_awprot = Bits(OUTPUT,3) + val m_axi_awvalid = Bool(OUTPUT) + val m_axi_awlock = Bits(OUTPUT,1) + val m_axi_awcache = Bits(OUTPUT,4) + val m_axi_awready = Bool(INPUT) + // write data + val m_axi_wdata = Bits(OUTPUT,AXI_DATA_WIDTH) + val m_axi_wstrb = Bits(OUTPUT,16) + val m_axi_wlast = Bool(OUTPUT) + val m_axi_wvalid = Bool(OUTPUT) + val m_axi_wready = Bool(INPUT) + // write response + val m_axi_bready = Bool(OUTPUT) + val m_axi_bresp = Bits(INPUT,2) + val m_axi_bvalid = Bool(INPUT) + // read address + val m_axi_araddr = Bits(OUTPUT,AXI_ADDR_WIDTH) + val m_axi_arlen = Bits(OUTPUT,8) + val m_axi_arsize = Bits(OUTPUT,3) + val m_axi_arburst = Bits(OUTPUT,2) + val m_axi_arprot = Bits(OUTPUT,3) + val m_axi_arvalid = Bool(OUTPUT) + val m_axi_arlock = Bits(OUTPUT,1) + val m_axi_arcache = Bits(OUTPUT,4) + val m_axi_arready = Bool(INPUT) + // read data + val m_axi_rready = Bool(OUTPUT) + val m_axi_rdata = Bits(INPUT,AXI_DATA_WIDTH) + val m_axi_rresp = Bits(INPUT,2) + val m_axi_rlast = Bool(INPUT) + val m_axi_rvalid = Bool(INPUT) + + // AXI4-Lite Control Interface + val s_axi_ctl_awaddr = Bits(INPUT,28) + val s_axi_ctl_awvalid = Bool(INPUT) + val s_axi_ctl_awready = Bool(OUTPUT) + val s_axi_ctl_wdata = Bits(INPUT,32) + val s_axi_ctl_wstrb = Bits(INPUT,4) + val s_axi_ctl_wvalid = Bool(INPUT) + val s_axi_ctl_wready = Bool(OUTPUT) + val s_axi_ctl_bresp = Bits(OUTPUT,2) + val s_axi_ctl_bvalid = Bool(OUTPUT) + val s_axi_ctl_bready = Bool(INPUT) + val s_axi_ctl_araddr = Bits(INPUT,28) + val s_axi_ctl_arvalid = Bool(INPUT) + val s_axi_ctl_arready = Bool(OUTPUT) + val s_axi_ctl_rdata = Bits(OUTPUT,32) + val s_axi_ctl_rresp = Bits(OUTPUT,2) + val s_axi_ctl_rvalid = Bool(OUTPUT) + val s_axi_ctl_rready = Bool(INPUT) + } +} +//scalastyle:off + +//wrap vc709_axi_to_pcie_x1 black box in Nasti Bundles +// see Chipyard doc: 9.1.2 Manager Node +class VC709AXIToPCIeX1(implicit p:Parameters) extends LazyModule +{ + // device-tree node + val device = new SimpleDevice("pci", Seq("xlnx,axi-pcie-host-1.00.a")) { + override def describe(resources: ResourceBindings): Description = { + val Description(name, mapping) = super.describe(resources) + val intc = "pcie_intc" + def ofInt(x: Int) = Seq(ResourceInt(BigInt(x))) + def ofMap(x: Int) = Seq(0, 0, 0, x).flatMap(ofInt) ++ Seq(ResourceReference(intc)) ++ ofInt(x) + val extra = Map( + "#address-cells" -> ofInt(3), + "#size-cells" -> ofInt(2), + "#interrupt-cells" -> ofInt(1), + "device_type" -> Seq(ResourceString("pci")), + "interrupt-map-mask" -> Seq(0, 0, 0, 7).flatMap(ofInt), + "interrupt-map" -> Seq(1, 2, 3, 4).flatMap(ofMap), + "ranges" -> resources("ranges").map(x => + (x: @unchecked) match { case Binding(_, ResourceAddress(address, perms)) => + ResourceMapping(address, BigInt(0x02000000) << 64, perms) }), + "interrupt-controller" -> Seq(ResourceMap(labels = Seq(intc), value = Map( + "interrupt-controller" -> Nil, + "#address-cells" -> ofInt(0), + "#interrupt-cells" -> ofInt(1))))) + Description(name, mapping ++ extra) + } + } + + val slave = AXI4SlaveNode(Seq(AXI4SlavePortParameters( + slaves = Seq(AXI4SlaveParameters( + address = List(AddressSet(0x40000000L, 0x1fffffffL)), + resources = Seq(Resource(device, "ranges")), + executable = true, + supportsWrite = TransferSizes(1, 128), + supportsRead = TransferSizes(1, 128))), + beatBytes = 8))) + + val control = AXI4SlaveNode(Seq(AXI4SlavePortParameters( + slaves = Seq(AXI4SlaveParameters( + address = List(AddressSet(0x2000000000L, 0x3ffffffL)), // when truncated to 32-bits, is 0 + resources = device.reg("control"), + supportsWrite = TransferSizes(1, 4), + supportsRead = TransferSizes(1, 4), + interleavedId = Some(0))), // AXI4-Lite never interleaves responses + beatBytes = 4))) + + val master = AXI4MasterNode(Seq(AXI4MasterPortParameters( + masters = Seq(AXI4MasterParameters( + name = "VC709 PCIe", + id = IdRange(0, 1), + aligned = false))))) + + val intnode = IntSourceNode(IntSourcePortSimple(resources = device.int)) + + lazy val module = new LazyModuleImp(this) { + // The master on the control port must be AXI-lite + require (control.edges.in(0).master.endId == 1) + // Must have exactly the right number of idBits + require (slave.edges.in(0).bundle.idBits == 4) + + class VC709AXIToPCIeX1IOBundle extends Bundle with VC709AXIToPCIeX1IOSerial + with VC709AXIToPCIeX1IOClocksReset; + + val io = IO(new Bundle { + val port = new VC709AXIToPCIeX1IOBundle + val refclk = Bool(INPUT) // REFCLK is changed to refclk in 3.0 + }) + + val blackbox = Module(new vc709axi_to_pcie_x1) + + val (s, _) = slave.in(0) + val (c, _) = control.in(0) + val (m, _) = master.out(0) + val (i, _) = intnode.out(0) + + //to top level + blackbox.io.axi_aresetn := io.port.axi_aresetn + io.port.axi_aclk := blackbox.io.axi_aclk + io.port.pci_exp_txp := blackbox.io.pci_exp_txp + io.port.pci_exp_txn := blackbox.io.pci_exp_txn + blackbox.io.pci_exp_rxp := io.port.pci_exp_rxp + blackbox.io.pci_exp_rxn := io.port.pci_exp_rxn + i(0) := blackbox.io.interrupt_out + blackbox.io.refclk := io.refclk + + // AXI Slave Interface + // write address + blackbox.io.s_axi_awid := s.aw.bits.id + blackbox.io.s_axi_awaddr := s.aw.bits.addr + blackbox.io.s_axi_awlen := s.aw.bits.len + blackbox.io.s_axi_awsize := s.aw.bits.size + blackbox.io.s_axi_awburst := s.aw.bits.burst + blackbox.io.s_axi_awregion := UInt(0) + blackbox.io.s_axi_awvalid := s.aw.valid + s.aw.ready := blackbox.io.s_axi_awready + // write data + blackbox.io.s_axi_wdata := s.w.bits.data + blackbox.io.s_axi_wstrb := s.w.bits.strb + blackbox.io.s_axi_wlast := s.w.bits.last + blackbox.io.s_axi_wvalid := s.w.valid + s.w.ready := blackbox.io.s_axi_wready + // write response + s.b.bits.id := blackbox.io.s_axi_bid + s.b.bits.resp := blackbox.io.s_axi_bresp + s.b.valid := blackbox.io.s_axi_bvalid + blackbox.io.s_axi_bready := s.b.ready + // read address + blackbox.io.s_axi_arid := s.ar.bits.id + blackbox.io.s_axi_araddr := s.ar.bits.addr + blackbox.io.s_axi_arlen := s.ar.bits.len + blackbox.io.s_axi_arsize := s.ar.bits.size + blackbox.io.s_axi_arburst := s.ar.bits.burst + blackbox.io.s_axi_arregion := UInt(0) + blackbox.io.s_axi_arvalid := s.ar.valid + s.ar.ready := blackbox.io.s_axi_arready + // read data + s.r.bits.id := blackbox.io.s_axi_rid + s.r.bits.data := blackbox.io.s_axi_rdata + s.r.bits.resp := blackbox.io.s_axi_rresp + s.r.bits.last := blackbox.io.s_axi_rlast + s.r.valid := blackbox.io.s_axi_rvalid + blackbox.io.s_axi_rready := s.r.ready + + // AXI4-Lite Control Interface + // write address + blackbox.io.s_axi_ctl_awaddr := c.aw.bits.addr + blackbox.io.s_axi_ctl_awvalid := c.aw.valid + c.aw.ready := blackbox.io.s_axi_ctl_awready + // write data + blackbox.io.s_axi_ctl_wdata := c.w.bits.data + blackbox.io.s_axi_ctl_wstrb := c.w.bits.strb + blackbox.io.s_axi_ctl_wvalid := c.w.valid + c.w.ready := blackbox.io.s_axi_ctl_wready + // write response + blackbox.io.s_axi_ctl_bready := c.b.ready + c.b.bits.id := UInt(0) + c.b.bits.resp := blackbox.io.s_axi_ctl_bresp + c.b.valid := blackbox.io.s_axi_ctl_bvalid + // read address + blackbox.io.s_axi_ctl_araddr := c.ar.bits.addr + blackbox.io.s_axi_ctl_arvalid := c.ar.valid + c.ar.ready := blackbox.io.s_axi_ctl_arready + // read data + blackbox.io.s_axi_ctl_rready := c.r.ready + c.r.bits.id := UInt(0) + c.r.bits.data := blackbox.io.s_axi_ctl_rdata + c.r.bits.resp := blackbox.io.s_axi_ctl_rresp + c.r.bits.last := Bool(true) + c.r.valid := blackbox.io.s_axi_ctl_rvalid + + // AXI Master Interface + // write address + m.aw.bits.id := UInt(0) + m.aw.bits.addr := blackbox.io.m_axi_awaddr + m.aw.bits.len := blackbox.io.m_axi_awlen + m.aw.bits.size := blackbox.io.m_axi_awsize + m.aw.bits.burst := blackbox.io.m_axi_awburst + m.aw.bits.prot := blackbox.io.m_axi_awprot + m.aw.bits.lock := blackbox.io.m_axi_awlock + m.aw.bits.cache := blackbox.io.m_axi_awcache + m.aw.bits.qos := UInt(0) + m.aw.valid := blackbox.io.m_axi_awvalid + blackbox.io.m_axi_awready := m.aw.ready + // write data + m.w.bits.data := blackbox.io.m_axi_wdata + m.w.bits.strb := blackbox.io.m_axi_wstrb + m.w.bits.last := blackbox.io.m_axi_wlast + m.w.valid := blackbox.io.m_axi_wvalid + blackbox.io.m_axi_wready := m.w.ready + // write response + blackbox.io.m_axi_bresp := m.b.bits.resp + blackbox.io.m_axi_bvalid := m.b.valid + m.b.ready := blackbox.io.m_axi_bready + // read address + m.ar.bits.id := UInt(0) + m.ar.bits.addr := blackbox.io.m_axi_araddr + m.ar.bits.len := blackbox.io.m_axi_arlen + m.ar.bits.size := blackbox.io.m_axi_arsize + m.ar.bits.burst := blackbox.io.m_axi_arburst + m.ar.bits.lock := blackbox.io.m_axi_arlock + m.ar.bits.cache := blackbox.io.m_axi_arcache + m.ar.bits.prot := blackbox.io.m_axi_arprot + m.ar.bits.qos := UInt(0) + m.ar.valid := blackbox.io.m_axi_arvalid + blackbox.io.m_axi_arready := m.ar.ready + // read data + blackbox.io.m_axi_rdata := m.r.bits.data + blackbox.io.m_axi_rresp := m.r.bits.resp + blackbox.io.m_axi_rlast := m.r.bits.last + blackbox.io.m_axi_rvalid := m.r.valid + m.r.ready := blackbox.io.m_axi_rready + } + + ElaborationArtefacts.add( + "vc709axi_to_pcie_x1.vivado.tcl", + """ + create_ip -vendor xilinx.com -library ip -version 3.0 -name axi_pcie3 -module_name vc709axi_to_pcie_x1 -dir $ipdir -force + set_property -dict [list \ + CONFIG.AXIBAR2PCIEBAR_0 {0x40000000} \ + CONFIG.AXIBAR_0 {0x40000000} \ + CONFIG.AXIBAR_HIGHADDR_0 {0x5FFFFFFF} \ + CONFIG.AXIBAR_NUM {1} \ + CONFIG.BASEADDR {0x00000000} \ + CONFIG.HIGHADDR {0x03FFFFFF} \ + CONFIG.DEVICE_PORT_TYPE {Root_Port_of_PCI_Express_Root_Complex} \ + CONFIG.INCLUDE_BAROFFSET_REG {true} \ + CONFIG.PCIEBAR2AXIBAR_0 {0x00000000} \ + CONFIG.PCIE_BLK_LOCN {X0Y0} \ + CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \ + CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {2.5_GT/s} \ + CONFIG.PF0_DEVICE_ID {7118} \ + CONFIG.PF0_REVISION_ID {0} \ + CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10EE} \ + CONFIG.PF0_SUBSYSTEM_ID {0007} \ + CONFIG.PF0_BAR0_64BIT {true} \ + CONFIG.PF0_BAR0_ENABLED {true} \ + CONFIG.PF0_BAR0_PREFETCHABLE {false} \ + CONFIG.PF0_BAR0_SCALE {Gigabytes} \ + CONFIG.PF0_BAR0_SIZE {4} \ + CONFIG.PF0_BAR0_TYPE {Memory} \ + CONFIG.PF0_BASE_CLASS_MENU {Bridge_device} \ + CONFIG.PF0_SUB_CLASS_interface_menu {Host_bridge} \ + CONFIG.PF0_CLASS_CODE {0x060000} \ + CONFIG.COMP_TIMEOUT {50ms} \ + CONFIG.REF_CLK_FREQ {100_MHz} \ + CONFIG.AXI_ADDR_WIDTH {64} \ + CONFIG.AXI_DATA_WIDTH {128_bit} \ + CONFIG.C_S_AXI_SUPPORTS_NARROW_BURST {false} \ + CONFIG.XLNX_REF_BOARD {VC709} ] [get_ips vc709axi_to_pcie_x1]""" + ) +} From 6775874dba755508231ee08069b9069573eb9fe6 Mon Sep 17 00:00:00 2001 From: mbs0221 Date: Thu, 1 Apr 2021 09:48:34 +0800 Subject: [PATCH 21/26] update support for PCIe --- .../xilinxvc709pcie/XilinxVC709PCIe.scala | 76 ++++ .../XilinxVC709PCIePeriphery.scala | 32 ++ .../vc709axi_to_pcie/vc709axi_to_pcie.scala | 378 ++++++++++++++++++ 3 files changed, 486 insertions(+) create mode 100644 src/main/scala/devices/xilinx/xilinxvc709pcie/XilinxVC709PCIe.scala create mode 100644 src/main/scala/devices/xilinx/xilinxvc709pcie/XilinxVC709PCIePeriphery.scala create mode 100644 src/main/scala/ip/xilinx/vc709axi_to_pcie/vc709axi_to_pcie.scala diff --git a/src/main/scala/devices/xilinx/xilinxvc709pcie/XilinxVC709PCIe.scala b/src/main/scala/devices/xilinx/xilinxvc709pcie/XilinxVC709PCIe.scala new file mode 100644 index 00000000..d39d350f --- /dev/null +++ b/src/main/scala/devices/xilinx/xilinxvc709pcie/XilinxVC709PCIe.scala @@ -0,0 +1,76 @@ +// See LICENSE for license details. +package sifive.fpgashells.devices.xilinx.xilinxvc709pcie + +import Chisel._ +import freechips.rocketchip.amba.axi4._ +import freechips.rocketchip.config.Parameters +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.interrupts._ +import freechips.rocketchip.subsystem.{CrossesToOnlyOneClockDomain, CacheBlockBytes} +import sifive.fpgashells.ip.xilinx.vc709axi_to_pcie.{VC709AXIToPCIe, VC709AXIToPCIeIOClocksReset, VC709AXIToPCIeIOSerial} +import sifive.fpgashells.ip.xilinx.ibufds_gte2.IBUFDS_GTE2 + +trait VC709AXIToPCIeRefClk extends Bundle{ + val REFCLK_rxp = Bool(INPUT) + val REFCLK_rxn = Bool(INPUT) +} + +class XilinxVC709PCIePads extends Bundle + with VC709AXIToPCIeIOSerial + with VC709AXIToPCIeRefClk + +class XilinxVC709PCIeIO extends Bundle + with VC709AXIToPCIeRefClk + with VC709AXIToPCIeIOSerial + with VC709AXIToPCIeIOClocksReset { + val axi_ctl_aresetn = Bool(INPUT) +} + +class XilinxVC709PCIe(implicit p: Parameters, val crossing: ClockCrossingType = AsynchronousCrossing(8)) + extends LazyModule with CrossesToOnlyOneClockDomain +{ + val axi_to_pcie = LazyModule(new VC709AXIToPCIe) + + val slave: TLInwardNode = + (axi_to_pcie.slave + := AXI4Buffer() + := AXI4UserYanker() + := AXI4Deinterleaver(p(CacheBlockBytes)) + := AXI4IdIndexer(idBits=4) + := TLToAXI4(adapterName = Some("pcie-slave"))) + + val control: TLInwardNode = + (axi_to_pcie.control + := AXI4Buffer() + := AXI4UserYanker(capMaxFlight = Some(2)) + := TLToAXI4() + := TLFragmenter(4, p(CacheBlockBytes), holdFirstDeny = true)) + + val master: TLOutwardNode = + (TLWidthWidget(8) + := AXI4ToTL() + := AXI4UserYanker(capMaxFlight=Some(8)) + := AXI4Fragmenter() + := axi_to_pcie.master) + + val intnode: IntOutwardNode = axi_to_pcie.intnode + + lazy val module = new LazyRawModuleImp(this) { + val io = IO(new Bundle { + val port = new XilinxVC709PCIeIO + }) + + childClock := io.port.axi_aclk // axi_aclk_out is changed to axi_aclk + childReset := ~io.port.axi_aresetn // + + io.port <> axi_to_pcie.module.io.port + + //PCIe Reference Clock + val ibufds_gte2 = Module(new IBUFDS_GTE2) + axi_to_pcie.module.io.refclk := ibufds_gte2.io.O // REFCLK is changed to refclk + ibufds_gte2.io.CEB := UInt(0) + ibufds_gte2.io.I := io.port.REFCLK_rxp + ibufds_gte2.io.IB := io.port.REFCLK_rxn + } +} diff --git a/src/main/scala/devices/xilinx/xilinxvc709pcie/XilinxVC709PCIePeriphery.scala b/src/main/scala/devices/xilinx/xilinxvc709pcie/XilinxVC709PCIePeriphery.scala new file mode 100644 index 00000000..a0b7aafd --- /dev/null +++ b/src/main/scala/devices/xilinx/xilinxvc709pcie/XilinxVC709PCIePeriphery.scala @@ -0,0 +1,32 @@ +// See LICENSE for license details. +package sifive.fpgashells.devices.xilinx.xilinxvc709pcie + +import Chisel._ +import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BufferParams} +import freechips.rocketchip.subsystem.BaseSubsystem +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.interrupts.IntSyncCrossingSink + +trait HasSystemXilinxVC709PCIe { this: BaseSubsystem => + val xilinxvc709pcie = LazyModule(new XilinxVC709PCIe) + private val cname = "xilinxvc709pcie" + sbus.coupleFrom(s"master_named_$cname") { _ :=* TLFIFOFixer(TLFIFOFixer.all) :=* xilinxvc709pcie.crossTLOut(xilinxvc709pcie.master) } + sbus.coupleTo(s"slave_named_$cname") { xilinxvc709pcie.crossTLIn(xilinxvc709pcie.slave) :*= TLWidthWidget(sbus.beatBytes) :*= _ } + sbus.coupleTo(s"controller_named_$cname") { xilinxvc709pcie.crossTLIn(xilinxvc709pcie.control) :*= TLWidthWidget(sbus.beatBytes) :*= _ } + ibus.fromSync := xilinxvc709pcie.crossIntOut(xilinxvc709pcie.intnode) +} + +trait HasSystemXilinxVC709PCIeBundle { + val xilinxvc709pcie: XilinxVC709PCIeIO + def connectXilinxVC709PCIeToPads(pads: XilinxVC709PCIePads) { + pads <> xilinxvc709pcie + } +} + +trait HasSystemXilinxVC709PCIeModuleImp extends LazyModuleImp + with HasSystemXilinxVC709PCIeBundle { + val outer: HasSystemXilinxVC709PCIe + val xilinxvc709pcie = IO(new XilinxVC709PCIeIO) + + xilinxvc709pcie <> outer.xilinxvc709pcie.module.io.port +} \ No newline at end of file diff --git a/src/main/scala/ip/xilinx/vc709axi_to_pcie/vc709axi_to_pcie.scala b/src/main/scala/ip/xilinx/vc709axi_to_pcie/vc709axi_to_pcie.scala new file mode 100644 index 00000000..760bbd9f --- /dev/null +++ b/src/main/scala/ip/xilinx/vc709axi_to_pcie/vc709axi_to_pcie.scala @@ -0,0 +1,378 @@ +// See LICENSE for license details. +package sifive.fpgashells.ip.xilinx.vc709axi_to_pcie + +import Chisel._ +import freechips.rocketchip.config._ +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.amba.axi4._ +import freechips.rocketchip.interrupts._ +import freechips.rocketchip.util.{ElaborationArtefacts} + +// AXI Bridge for PCI Express Gen3 Subsystem v3.0 +// Product Guide Vivado Design Suite PG194 (v3.0) July 22, 2020 +// IP VLNV: xilinx.com:customize_ip:vc709pcietoaxi:3.0 +// Black Box Signals named _exactly_ as per Vivado generated verilog +trait VC709AXIToPCIeIOSerial extends Bundle { + def NUM_LANES = 8 + // PCIe Interface + val pci_exp_txp = Bits(OUTPUT,NUM_LANES) + val pci_exp_txn = Bits(OUTPUT,NUM_LANES) + val pci_exp_rxp = Bits(INPUT,NUM_LANES) + val pci_exp_rxn = Bits(INPUT,NUM_LANES) +} + +trait VC709AXIToPCIeIOClocksReset extends Bundle { + // Global Signals + val axi_aresetn = Bool(INPUT) + val axi_aclk = Clock(OUTPUT) +} + +//scalastyle:off +//turn off linter: blackbox name must match verilog module +class vc709axi_to_pcie() extends BlackBox +{ + def AXI_ADDR_WIDTH = 32 + def AXI_DATA_WIDTH = 128 + val io = new Bundle with VC709AXIToPCIeIOSerial + with VC709AXIToPCIeIOClocksReset { + // Global Signals + val refclk = Bool(INPUT) + val interrupt_out = Bool(OUTPUT) + + // AXI Bridge for PCIe Gen3 MSI Signals + val intx_msi_request = Bool(INPUT) + val intx_msi_grant = Bool(OUTPUT) + val msi_enable = Bool(OUTPUT) + val msi_vector_width = Bits(OUTPUT,3) + val msi_vector_num = Bits(INPUT,5) + + // AXI Slave Interface + // write address + val s_axi_awid = Bits(INPUT,4) + val s_axi_awaddr = Bits(INPUT,AXI_ADDR_WIDTH) + val s_axi_awregion = Bits(INPUT,4) + val s_axi_awlen = Bits(INPUT,8) + val s_axi_awsize = Bits(INPUT,3) + val s_axi_awburst = Bits(INPUT,2) + val s_axi_awvalid = Bool(INPUT) + val s_axi_awready = Bool(OUTPUT) + // write data + val s_axi_wdata = Bits(INPUT,AXI_DATA_WIDTH) + val s_axi_wstrb = Bits(INPUT,16) + val s_axi_wlast = Bool(INPUT) + val s_axi_wvalid = Bool(INPUT) + val s_axi_wready = Bool(OUTPUT) + // write response + val s_axi_bready = Bool(INPUT) + val s_axi_bid = Bits(OUTPUT,4) + val s_axi_bresp = Bits(OUTPUT,2) + val s_axi_bvalid = Bool(OUTPUT) + // read address + val s_axi_arid = Bits(INPUT,4) + val s_axi_araddr = Bits(INPUT,AXI_ADDR_WIDTH) + val s_axi_arregion = Bits(INPUT,4) + val s_axi_arlen = Bits(INPUT,8) + val s_axi_arsize = Bits(INPUT,3) + val s_axi_arburst = Bits(INPUT,2) + val s_axi_arvalid = Bool(INPUT) + val s_axi_arready = Bool(OUTPUT) + //slave interface read data + val s_axi_rready = Bool(INPUT) + val s_axi_rid = Bits(OUTPUT,4) + val s_axi_rdata = Bits(OUTPUT,AXI_DATA_WIDTH) + val s_axi_rresp = Bits(OUTPUT,2) + val s_axi_rlast = Bool(OUTPUT) + val s_axi_rvalid = Bool(OUTPUT) + + // AXI Master Interface + // write address + val m_axi_awaddr = Bits(OUTPUT,AXI_ADDR_WIDTH) + val m_axi_awlen = Bits(OUTPUT,8) + val m_axi_awsize = Bits(OUTPUT,3) + val m_axi_awburst = Bits(OUTPUT,2) + val m_axi_awprot = Bits(OUTPUT,3) + val m_axi_awvalid = Bool(OUTPUT) + val m_axi_awlock = Bits(OUTPUT,1) + val m_axi_awcache = Bits(OUTPUT,4) + val m_axi_awready = Bool(INPUT) + // write data + val m_axi_wdata = Bits(OUTPUT,AXI_DATA_WIDTH) + val m_axi_wstrb = Bits(OUTPUT,16) + val m_axi_wlast = Bool(OUTPUT) + val m_axi_wvalid = Bool(OUTPUT) + val m_axi_wready = Bool(INPUT) + // write response + val m_axi_bready = Bool(OUTPUT) + val m_axi_bresp = Bits(INPUT,2) + val m_axi_bvalid = Bool(INPUT) + // read address + val m_axi_araddr = Bits(OUTPUT,AXI_ADDR_WIDTH) + val m_axi_arlen = Bits(OUTPUT,8) + val m_axi_arsize = Bits(OUTPUT,3) + val m_axi_arburst = Bits(OUTPUT,2) + val m_axi_arprot = Bits(OUTPUT,3) + val m_axi_arvalid = Bool(OUTPUT) + val m_axi_arlock = Bits(OUTPUT,1) + val m_axi_arcache = Bits(OUTPUT,4) + val m_axi_arready = Bool(INPUT) + // read data + val m_axi_rready = Bool(OUTPUT) + val m_axi_rdata = Bits(INPUT,AXI_DATA_WIDTH) + val m_axi_rresp = Bits(INPUT,2) + val m_axi_rlast = Bool(INPUT) + val m_axi_rvalid = Bool(INPUT) + + // AXI4-Lite Control Interface + val s_axi_ctl_awaddr = Bits(INPUT,28) + val s_axi_ctl_awvalid = Bool(INPUT) + val s_axi_ctl_awready = Bool(OUTPUT) + val s_axi_ctl_wdata = Bits(INPUT,32) + val s_axi_ctl_wstrb = Bits(INPUT,4) + val s_axi_ctl_wvalid = Bool(INPUT) + val s_axi_ctl_wready = Bool(OUTPUT) + val s_axi_ctl_bresp = Bits(OUTPUT,2) + val s_axi_ctl_bvalid = Bool(OUTPUT) + val s_axi_ctl_bready = Bool(INPUT) + val s_axi_ctl_araddr = Bits(INPUT,28) + val s_axi_ctl_arvalid = Bool(INPUT) + val s_axi_ctl_arready = Bool(OUTPUT) + val s_axi_ctl_rdata = Bits(OUTPUT,32) + val s_axi_ctl_rresp = Bits(OUTPUT,2) + val s_axi_ctl_rvalid = Bool(OUTPUT) + val s_axi_ctl_rready = Bool(INPUT) + } +} +//scalastyle:off + +//wrap vc709_axi_to_pcie black box in Nasti Bundles +// see Chipyard doc: 9.1.2 Manager Node +class VC709AXIToPCIe(implicit p:Parameters) extends LazyModule +{ + // device-tree node + val device = new SimpleDevice("pci", Seq("xlnx,axi-pcie-host-1.00.a")) { + override def describe(resources: ResourceBindings): Description = { + val Description(name, mapping) = super.describe(resources) + val intc = "pcie_intc" + def ofInt(x: Int) = Seq(ResourceInt(BigInt(x))) + def ofMap(x: Int) = Seq(0, 0, 0, x).flatMap(ofInt) ++ Seq(ResourceReference(intc)) ++ ofInt(x) + val extra = Map( + "#address-cells" -> ofInt(3), + "#size-cells" -> ofInt(2), + "#interrupt-cells" -> ofInt(1), + "device_type" -> Seq(ResourceString("pci")), + "interrupt-map-mask" -> Seq(0, 0, 0, 7).flatMap(ofInt), + "interrupt-map" -> Seq(1, 2, 3, 4).flatMap(ofMap), + "ranges" -> resources("ranges").map(x => + (x: @unchecked) match { case Binding(_, ResourceAddress(address, perms)) => + ResourceMapping(address, BigInt(0x02000000) << 64, perms) }), + "interrupt-controller" -> Seq(ResourceMap(labels = Seq(intc), value = Map( + "interrupt-controller" -> Nil, + "#address-cells" -> ofInt(0), + "#interrupt-cells" -> ofInt(1))))) + Description(name, mapping ++ extra) + } + } + + val slave = AXI4SlaveNode(Seq(AXI4SlavePortParameters( + slaves = Seq(AXI4SlaveParameters( + address = List(AddressSet(0x40000000L, 0x1fffffffL)), + resources = Seq(Resource(device, "ranges")), + executable = true, + supportsWrite = TransferSizes(1, 128), + supportsRead = TransferSizes(1, 128))), + beatBytes = 8))) + + val control = AXI4SlaveNode(Seq(AXI4SlavePortParameters( + slaves = Seq(AXI4SlaveParameters( + address = List(AddressSet(0x2000000000L, 0x3ffffffL)), // when truncated to 32-bits, is 0 + resources = device.reg("control"), + supportsWrite = TransferSizes(1, 4), + supportsRead = TransferSizes(1, 4), + interleavedId = Some(0))), // AXI4-Lite never interleaves responses + beatBytes = 4))) + + val master = AXI4MasterNode(Seq(AXI4MasterPortParameters( + masters = Seq(AXI4MasterParameters( + name = "VC709 PCIe", + id = IdRange(0, 1), + aligned = false))))) + + val intnode = IntSourceNode(IntSourcePortSimple(resources = device.int)) + + lazy val module = new LazyModuleImp(this) { + // The master on the control port must be AXI-lite + require (control.edges.in(0).master.endId == 1) + // Must have exactly the right number of idBits + require (slave.edges.in(0).bundle.idBits == 4) + + class VC709AXIToPCIeIOBundle extends Bundle with VC709AXIToPCIeIOSerial + with VC709AXIToPCIeIOClocksReset; + + val io = IO(new Bundle { + val port = new VC709AXIToPCIeIOBundle + val refclk = Bool(INPUT) // REFCLK is changed to refclk in 3.0 + }) + + val blackbox = Module(new vc709axi_to_pcie) + + val (s, _) = slave.in(0) + val (c, _) = control.in(0) + val (m, _) = master.out(0) + val (i, _) = intnode.out(0) + + //to top level + blackbox.io.axi_aresetn := io.port.axi_aresetn + io.port.axi_aclk := blackbox.io.axi_aclk + io.port.pci_exp_txp := blackbox.io.pci_exp_txp + io.port.pci_exp_txn := blackbox.io.pci_exp_txn + blackbox.io.pci_exp_rxp := io.port.pci_exp_rxp + blackbox.io.pci_exp_rxn := io.port.pci_exp_rxn + i(0) := blackbox.io.interrupt_out + blackbox.io.refclk := io.refclk + + // AXI Slave Interface + // write address + blackbox.io.s_axi_awid := s.aw.bits.id + blackbox.io.s_axi_awaddr := s.aw.bits.addr + blackbox.io.s_axi_awlen := s.aw.bits.len + blackbox.io.s_axi_awsize := s.aw.bits.size + blackbox.io.s_axi_awburst := s.aw.bits.burst + blackbox.io.s_axi_awregion := UInt(0) + blackbox.io.s_axi_awvalid := s.aw.valid + s.aw.ready := blackbox.io.s_axi_awready + // write data + blackbox.io.s_axi_wdata := s.w.bits.data + blackbox.io.s_axi_wstrb := s.w.bits.strb + blackbox.io.s_axi_wlast := s.w.bits.last + blackbox.io.s_axi_wvalid := s.w.valid + s.w.ready := blackbox.io.s_axi_wready + // write response + s.b.bits.id := blackbox.io.s_axi_bid + s.b.bits.resp := blackbox.io.s_axi_bresp + s.b.valid := blackbox.io.s_axi_bvalid + blackbox.io.s_axi_bready := s.b.ready + // read address + blackbox.io.s_axi_arid := s.ar.bits.id + blackbox.io.s_axi_araddr := s.ar.bits.addr + blackbox.io.s_axi_arlen := s.ar.bits.len + blackbox.io.s_axi_arsize := s.ar.bits.size + blackbox.io.s_axi_arburst := s.ar.bits.burst + blackbox.io.s_axi_arregion := UInt(0) + blackbox.io.s_axi_arvalid := s.ar.valid + s.ar.ready := blackbox.io.s_axi_arready + // read data + s.r.bits.id := blackbox.io.s_axi_rid + s.r.bits.data := blackbox.io.s_axi_rdata + s.r.bits.resp := blackbox.io.s_axi_rresp + s.r.bits.last := blackbox.io.s_axi_rlast + s.r.valid := blackbox.io.s_axi_rvalid + blackbox.io.s_axi_rready := s.r.ready + + // AXI4-Lite Control Interface + // write address + blackbox.io.s_axi_ctl_awaddr := c.aw.bits.addr + blackbox.io.s_axi_ctl_awvalid := c.aw.valid + c.aw.ready := blackbox.io.s_axi_ctl_awready + // write data + blackbox.io.s_axi_ctl_wdata := c.w.bits.data + blackbox.io.s_axi_ctl_wstrb := c.w.bits.strb + blackbox.io.s_axi_ctl_wvalid := c.w.valid + c.w.ready := blackbox.io.s_axi_ctl_wready + // write response + blackbox.io.s_axi_ctl_bready := c.b.ready + c.b.bits.id := UInt(0) + c.b.bits.resp := blackbox.io.s_axi_ctl_bresp + c.b.valid := blackbox.io.s_axi_ctl_bvalid + // read address + blackbox.io.s_axi_ctl_araddr := c.ar.bits.addr + blackbox.io.s_axi_ctl_arvalid := c.ar.valid + c.ar.ready := blackbox.io.s_axi_ctl_arready + // read data + blackbox.io.s_axi_ctl_rready := c.r.ready + c.r.bits.id := UInt(0) + c.r.bits.data := blackbox.io.s_axi_ctl_rdata + c.r.bits.resp := blackbox.io.s_axi_ctl_rresp + c.r.bits.last := Bool(true) + c.r.valid := blackbox.io.s_axi_ctl_rvalid + + // AXI Master Interface + // write address + m.aw.bits.id := UInt(0) + m.aw.bits.addr := blackbox.io.m_axi_awaddr + m.aw.bits.len := blackbox.io.m_axi_awlen + m.aw.bits.size := blackbox.io.m_axi_awsize + m.aw.bits.burst := blackbox.io.m_axi_awburst + m.aw.bits.prot := blackbox.io.m_axi_awprot + m.aw.bits.lock := blackbox.io.m_axi_awlock + m.aw.bits.cache := blackbox.io.m_axi_awcache + m.aw.bits.qos := UInt(0) + m.aw.valid := blackbox.io.m_axi_awvalid + blackbox.io.m_axi_awready := m.aw.ready + // write data + m.w.bits.data := blackbox.io.m_axi_wdata + m.w.bits.strb := blackbox.io.m_axi_wstrb + m.w.bits.last := blackbox.io.m_axi_wlast + m.w.valid := blackbox.io.m_axi_wvalid + blackbox.io.m_axi_wready := m.w.ready + // write response + blackbox.io.m_axi_bresp := m.b.bits.resp + blackbox.io.m_axi_bvalid := m.b.valid + m.b.ready := blackbox.io.m_axi_bready + // read address + m.ar.bits.id := UInt(0) + m.ar.bits.addr := blackbox.io.m_axi_araddr + m.ar.bits.len := blackbox.io.m_axi_arlen + m.ar.bits.size := blackbox.io.m_axi_arsize + m.ar.bits.burst := blackbox.io.m_axi_arburst + m.ar.bits.lock := blackbox.io.m_axi_arlock + m.ar.bits.cache := blackbox.io.m_axi_arcache + m.ar.bits.prot := blackbox.io.m_axi_arprot + m.ar.bits.qos := UInt(0) + m.ar.valid := blackbox.io.m_axi_arvalid + blackbox.io.m_axi_arready := m.ar.ready + // read data + blackbox.io.m_axi_rdata := m.r.bits.data + blackbox.io.m_axi_rresp := m.r.bits.resp + blackbox.io.m_axi_rlast := m.r.bits.last + blackbox.io.m_axi_rvalid := m.r.valid + m.r.ready := blackbox.io.m_axi_rready + } + + ElaborationArtefacts.add( + "vc709axi_to_pcie.vivado.tcl", + """ + create_ip -vendor xilinx.com -library ip -version 3.0 -name axi_pcie3 -module_name vc709axi_to_pcie -dir $ipdir -force + set_property -dict [list \ + CONFIG.AXIBAR2PCIEBAR_0 {0x40000000} \ + CONFIG.AXIBAR_0 {0x40000000} \ + CONFIG.AXIBAR_HIGHADDR_0 {0x5FFFFFFF} \ + CONFIG.AXIBAR_NUM {1} \ + CONFIG.BASEADDR {0x00000000} \ + CONFIG.HIGHADDR {0x03FFFFFF} \ + CONFIG.DEVICE_PORT_TYPE {Root_Port_of_PCI_Express_Root_Complex} \ + CONFIG.INCLUDE_BAROFFSET_REG {true} \ + CONFIG.PCIEBAR2AXIBAR_0 {0x00000000} \ + CONFIG.PCIE_BLK_LOCN {X0Y0} \ + CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \ + CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {2.5_GT/s} \ + CONFIG.PF0_DEVICE_ID {7118} \ + CONFIG.PF0_REVISION_ID {0} \ + CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10EE} \ + CONFIG.PF0_SUBSYSTEM_ID {0007} \ + CONFIG.PF0_BAR0_64BIT {true} \ + CONFIG.PF0_BAR0_ENABLED {true} \ + CONFIG.PF0_BAR0_PREFETCHABLE {false} \ + CONFIG.PF0_BAR0_SCALE {Gigabytes} \ + CONFIG.PF0_BAR0_SIZE {4} \ + CONFIG.PF0_BAR0_TYPE {Memory} \ + CONFIG.PF0_BASE_CLASS_MENU {Bridge_device} \ + CONFIG.PF0_SUB_CLASS_interface_menu {Host_bridge} \ + CONFIG.PF0_CLASS_CODE {0x060000} \ + CONFIG.COMP_TIMEOUT {50ms} \ + CONFIG.REF_CLK_FREQ {100_MHz} \ + CONFIG.AXI_ADDR_WIDTH {32} \ + CONFIG.AXI_DATA_WIDTH {128_bit} \ + CONFIG.C_S_AXI_SUPPORTS_NARROW_BURST {false} \ + CONFIG.XLNX_REF_BOARD {VC709} ] [get_ips vc709axi_to_pcie]""" + ) +} From 0142088e523d62d535e9e2f0ba518ad418212886 Mon Sep 17 00:00:00 2001 From: mbs0221 Date: Thu, 1 Apr 2021 09:50:02 +0800 Subject: [PATCH 22/26] update support for PCIe --- .../xilinxvc709pciex1/XilinxVC709PCIeX1.scala | 76 ---- .../XilinxVC709PCIeX1Periphery.scala | 32 -- .../vc709axi_to_pcie_x1.scala | 378 ------------------ src/main/scala/shell/PCIeOverlay.scala | 3 - .../scala/shell/xilinx/VC709NewShell.scala | 8 +- 5 files changed, 4 insertions(+), 493 deletions(-) delete mode 100644 src/main/scala/devices/xilinx/xilinxvc709pciex1/XilinxVC709PCIeX1.scala delete mode 100644 src/main/scala/devices/xilinx/xilinxvc709pciex1/XilinxVC709PCIeX1Periphery.scala delete mode 100644 src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala diff --git a/src/main/scala/devices/xilinx/xilinxvc709pciex1/XilinxVC709PCIeX1.scala b/src/main/scala/devices/xilinx/xilinxvc709pciex1/XilinxVC709PCIeX1.scala deleted file mode 100644 index 1b45db02..00000000 --- a/src/main/scala/devices/xilinx/xilinxvc709pciex1/XilinxVC709PCIeX1.scala +++ /dev/null @@ -1,76 +0,0 @@ -// See LICENSE for license details. -package sifive.fpgashells.devices.xilinx.xilinxvc709pciex1 - -import Chisel._ -import freechips.rocketchip.amba.axi4._ -import freechips.rocketchip.config.Parameters -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.interrupts._ -import freechips.rocketchip.subsystem.{CrossesToOnlyOneClockDomain, CacheBlockBytes} -import sifive.fpgashells.ip.xilinx.vc709axi_to_pcie_x1.{VC709AXIToPCIeX1, VC709AXIToPCIeX1IOClocksReset, VC709AXIToPCIeX1IOSerial} -import sifive.fpgashells.ip.xilinx.ibufds_gte2.IBUFDS_GTE2 - -trait VC709AXIToPCIeRefClk extends Bundle{ - val REFCLK_rxp = Bool(INPUT) - val REFCLK_rxn = Bool(INPUT) -} - -class XilinxVC709PCIeX1Pads extends Bundle - with VC709AXIToPCIeX1IOSerial - with VC709AXIToPCIeRefClk - -class XilinxVC709PCIeX1IO extends Bundle - with VC709AXIToPCIeRefClk - with VC709AXIToPCIeX1IOSerial - with VC709AXIToPCIeX1IOClocksReset { - val axi_ctl_aresetn = Bool(INPUT) -} - -class XilinxVC709PCIeX1(implicit p: Parameters, val crossing: ClockCrossingType = AsynchronousCrossing(8)) - extends LazyModule with CrossesToOnlyOneClockDomain -{ - val axi_to_pcie_x1 = LazyModule(new VC709AXIToPCIeX1) - - val slave: TLInwardNode = - (axi_to_pcie_x1.slave - := AXI4Buffer() - := AXI4UserYanker() - := AXI4Deinterleaver(p(CacheBlockBytes)) - := AXI4IdIndexer(idBits=4) - := TLToAXI4(adapterName = Some("pcie-slave"))) - - val control: TLInwardNode = - (axi_to_pcie_x1.control - := AXI4Buffer() - := AXI4UserYanker(capMaxFlight = Some(2)) - := TLToAXI4() - := TLFragmenter(4, p(CacheBlockBytes), holdFirstDeny = true)) - - val master: TLOutwardNode = - (TLWidthWidget(8) - := AXI4ToTL() - := AXI4UserYanker(capMaxFlight=Some(8)) - := AXI4Fragmenter() - := axi_to_pcie_x1.master) - - val intnode: IntOutwardNode = axi_to_pcie_x1.intnode - - lazy val module = new LazyRawModuleImp(this) { - val io = IO(new Bundle { - val port = new XilinxVC709PCIeX1IO - }) - - childClock := io.port.axi_aclk // axi_aclk_out is changed to axi_aclk - childReset := ~io.port.axi_aresetn // - - io.port <> axi_to_pcie_x1.module.io.port - - //PCIe Reference Clock - val ibufds_gte2 = Module(new IBUFDS_GTE2) - axi_to_pcie_x1.module.io.refclk := ibufds_gte2.io.O // REFCLK is changed to refclk - ibufds_gte2.io.CEB := UInt(0) - ibufds_gte2.io.I := io.port.REFCLK_rxp - ibufds_gte2.io.IB := io.port.REFCLK_rxn - } -} diff --git a/src/main/scala/devices/xilinx/xilinxvc709pciex1/XilinxVC709PCIeX1Periphery.scala b/src/main/scala/devices/xilinx/xilinxvc709pciex1/XilinxVC709PCIeX1Periphery.scala deleted file mode 100644 index 15017561..00000000 --- a/src/main/scala/devices/xilinx/xilinxvc709pciex1/XilinxVC709PCIeX1Periphery.scala +++ /dev/null @@ -1,32 +0,0 @@ -// See LICENSE for license details. -package sifive.fpgashells.devices.xilinx.xilinxvc709pciex1 - -import Chisel._ -import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BufferParams} -import freechips.rocketchip.subsystem.BaseSubsystem -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.interrupts.IntSyncCrossingSink - -trait HasSystemXilinxVC709PCIeX1 { this: BaseSubsystem => - val xilinxvc709pcie = LazyModule(new XilinxVC709PCIeX1) - private val cname = "xilinxvc709pcie" - sbus.coupleFrom(s"master_named_$cname") { _ :=* TLFIFOFixer(TLFIFOFixer.all) :=* xilinxvc709pcie.crossTLOut(xilinxvc709pcie.master) } - sbus.coupleTo(s"slave_named_$cname") { xilinxvc709pcie.crossTLIn(xilinxvc709pcie.slave) :*= TLWidthWidget(sbus.beatBytes) :*= _ } - sbus.coupleTo(s"controller_named_$cname") { xilinxvc709pcie.crossTLIn(xilinxvc709pcie.control) :*= TLWidthWidget(sbus.beatBytes) :*= _ } - ibus.fromSync := xilinxvc709pcie.crossIntOut(xilinxvc709pcie.intnode) -} - -trait HasSystemXilinxVC709PCIeX1Bundle { - val xilinxvc709pcie: XilinxVC709PCIeX1IO - def connectXilinxVC709PCIeX1ToPads(pads: XilinxVC709PCIeX1Pads) { - pads <> xilinxvc709pcie - } -} - -trait HasSystemXilinxVC709PCIeX1ModuleImp extends LazyModuleImp - with HasSystemXilinxVC709PCIeX1Bundle { - val outer: HasSystemXilinxVC709PCIeX1 - val xilinxvc709pcie = IO(new XilinxVC709PCIeX1IO) - - xilinxvc709pcie <> outer.xilinxvc709pcie.module.io.port -} \ No newline at end of file diff --git a/src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala b/src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala deleted file mode 100644 index 8f8a9c89..00000000 --- a/src/main/scala/ip/xilinx/vc709axi_to_pcie_x1/vc709axi_to_pcie_x1.scala +++ /dev/null @@ -1,378 +0,0 @@ -// See LICENSE for license details. -package sifive.fpgashells.ip.xilinx.vc709axi_to_pcie_x1 - -import Chisel._ -import freechips.rocketchip.config._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.amba.axi4._ -import freechips.rocketchip.interrupts._ -import freechips.rocketchip.util.{ElaborationArtefacts} - -// AXI Bridge for PCI Express Gen3 Subsystem v3.0 -// Product Guide Vivado Design Suite PG194 (v3.0) July 22, 2020 -// IP VLNV: xilinx.com:customize_ip:vc709pcietoaxi:3.0 -// Black Box Signals named _exactly_ as per Vivado generated verilog -trait VC709AXIToPCIeX1IOSerial extends Bundle { - def NUM_LANES = 8 - // PCIe Interface - val pci_exp_txp = Bits(OUTPUT,NUM_LANES) - val pci_exp_txn = Bits(OUTPUT,NUM_LANES) - val pci_exp_rxp = Bits(INPUT,NUM_LANES) - val pci_exp_rxn = Bits(INPUT,NUM_LANES) -} - -trait VC709AXIToPCIeX1IOClocksReset extends Bundle { - // Global Signals - val axi_aresetn = Bool(INPUT) - val axi_aclk = Clock(OUTPUT) -} - -//scalastyle:off -//turn off linter: blackbox name must match verilog module -class vc709axi_to_pcie_x1() extends BlackBox -{ - def AXI_ADDR_WIDTH = 64 - def AXI_DATA_WIDTH = 128 - val io = new Bundle with VC709AXIToPCIeX1IOSerial - with VC709AXIToPCIeX1IOClocksReset { - // Global Signals - val refclk = Bool(INPUT) - val interrupt_out = Bool(OUTPUT) - - // AXI Bridge for PCIe Gen3 MSI Signals - val intx_msi_request = Bool(INPUT) - val intx_msi_grant = Bool(OUTPUT) - val msi_enable = Bool(OUTPUT) - val msi_vector_width = Bits(OUTPUT,3) - val msi_vector_num = Bits(INPUT,5) - - // AXI Slave Interface - // write address - val s_axi_awid = Bits(INPUT,4) - val s_axi_awaddr = Bits(INPUT,AXI_ADDR_WIDTH) - val s_axi_awregion = Bits(INPUT,4) - val s_axi_awlen = Bits(INPUT,8) - val s_axi_awsize = Bits(INPUT,3) - val s_axi_awburst = Bits(INPUT,2) - val s_axi_awvalid = Bool(INPUT) - val s_axi_awready = Bool(OUTPUT) - // write data - val s_axi_wdata = Bits(INPUT,AXI_DATA_WIDTH) - val s_axi_wstrb = Bits(INPUT,16) - val s_axi_wlast = Bool(INPUT) - val s_axi_wvalid = Bool(INPUT) - val s_axi_wready = Bool(OUTPUT) - // write response - val s_axi_bready = Bool(INPUT) - val s_axi_bid = Bits(OUTPUT,4) - val s_axi_bresp = Bits(OUTPUT,2) - val s_axi_bvalid = Bool(OUTPUT) - // read address - val s_axi_arid = Bits(INPUT,4) - val s_axi_araddr = Bits(INPUT,AXI_ADDR_WIDTH) - val s_axi_arregion = Bits(INPUT,4) - val s_axi_arlen = Bits(INPUT,8) - val s_axi_arsize = Bits(INPUT,3) - val s_axi_arburst = Bits(INPUT,2) - val s_axi_arvalid = Bool(INPUT) - val s_axi_arready = Bool(OUTPUT) - //slave interface read data - val s_axi_rready = Bool(INPUT) - val s_axi_rid = Bits(OUTPUT,4) - val s_axi_rdata = Bits(OUTPUT,AXI_DATA_WIDTH) - val s_axi_rresp = Bits(OUTPUT,2) - val s_axi_rlast = Bool(OUTPUT) - val s_axi_rvalid = Bool(OUTPUT) - - // AXI Master Interface - // write address - val m_axi_awaddr = Bits(OUTPUT,AXI_ADDR_WIDTH) - val m_axi_awlen = Bits(OUTPUT,8) - val m_axi_awsize = Bits(OUTPUT,3) - val m_axi_awburst = Bits(OUTPUT,2) - val m_axi_awprot = Bits(OUTPUT,3) - val m_axi_awvalid = Bool(OUTPUT) - val m_axi_awlock = Bits(OUTPUT,1) - val m_axi_awcache = Bits(OUTPUT,4) - val m_axi_awready = Bool(INPUT) - // write data - val m_axi_wdata = Bits(OUTPUT,AXI_DATA_WIDTH) - val m_axi_wstrb = Bits(OUTPUT,16) - val m_axi_wlast = Bool(OUTPUT) - val m_axi_wvalid = Bool(OUTPUT) - val m_axi_wready = Bool(INPUT) - // write response - val m_axi_bready = Bool(OUTPUT) - val m_axi_bresp = Bits(INPUT,2) - val m_axi_bvalid = Bool(INPUT) - // read address - val m_axi_araddr = Bits(OUTPUT,AXI_ADDR_WIDTH) - val m_axi_arlen = Bits(OUTPUT,8) - val m_axi_arsize = Bits(OUTPUT,3) - val m_axi_arburst = Bits(OUTPUT,2) - val m_axi_arprot = Bits(OUTPUT,3) - val m_axi_arvalid = Bool(OUTPUT) - val m_axi_arlock = Bits(OUTPUT,1) - val m_axi_arcache = Bits(OUTPUT,4) - val m_axi_arready = Bool(INPUT) - // read data - val m_axi_rready = Bool(OUTPUT) - val m_axi_rdata = Bits(INPUT,AXI_DATA_WIDTH) - val m_axi_rresp = Bits(INPUT,2) - val m_axi_rlast = Bool(INPUT) - val m_axi_rvalid = Bool(INPUT) - - // AXI4-Lite Control Interface - val s_axi_ctl_awaddr = Bits(INPUT,28) - val s_axi_ctl_awvalid = Bool(INPUT) - val s_axi_ctl_awready = Bool(OUTPUT) - val s_axi_ctl_wdata = Bits(INPUT,32) - val s_axi_ctl_wstrb = Bits(INPUT,4) - val s_axi_ctl_wvalid = Bool(INPUT) - val s_axi_ctl_wready = Bool(OUTPUT) - val s_axi_ctl_bresp = Bits(OUTPUT,2) - val s_axi_ctl_bvalid = Bool(OUTPUT) - val s_axi_ctl_bready = Bool(INPUT) - val s_axi_ctl_araddr = Bits(INPUT,28) - val s_axi_ctl_arvalid = Bool(INPUT) - val s_axi_ctl_arready = Bool(OUTPUT) - val s_axi_ctl_rdata = Bits(OUTPUT,32) - val s_axi_ctl_rresp = Bits(OUTPUT,2) - val s_axi_ctl_rvalid = Bool(OUTPUT) - val s_axi_ctl_rready = Bool(INPUT) - } -} -//scalastyle:off - -//wrap vc709_axi_to_pcie_x1 black box in Nasti Bundles -// see Chipyard doc: 9.1.2 Manager Node -class VC709AXIToPCIeX1(implicit p:Parameters) extends LazyModule -{ - // device-tree node - val device = new SimpleDevice("pci", Seq("xlnx,axi-pcie-host-1.00.a")) { - override def describe(resources: ResourceBindings): Description = { - val Description(name, mapping) = super.describe(resources) - val intc = "pcie_intc" - def ofInt(x: Int) = Seq(ResourceInt(BigInt(x))) - def ofMap(x: Int) = Seq(0, 0, 0, x).flatMap(ofInt) ++ Seq(ResourceReference(intc)) ++ ofInt(x) - val extra = Map( - "#address-cells" -> ofInt(3), - "#size-cells" -> ofInt(2), - "#interrupt-cells" -> ofInt(1), - "device_type" -> Seq(ResourceString("pci")), - "interrupt-map-mask" -> Seq(0, 0, 0, 7).flatMap(ofInt), - "interrupt-map" -> Seq(1, 2, 3, 4).flatMap(ofMap), - "ranges" -> resources("ranges").map(x => - (x: @unchecked) match { case Binding(_, ResourceAddress(address, perms)) => - ResourceMapping(address, BigInt(0x02000000) << 64, perms) }), - "interrupt-controller" -> Seq(ResourceMap(labels = Seq(intc), value = Map( - "interrupt-controller" -> Nil, - "#address-cells" -> ofInt(0), - "#interrupt-cells" -> ofInt(1))))) - Description(name, mapping ++ extra) - } - } - - val slave = AXI4SlaveNode(Seq(AXI4SlavePortParameters( - slaves = Seq(AXI4SlaveParameters( - address = List(AddressSet(0x40000000L, 0x1fffffffL)), - resources = Seq(Resource(device, "ranges")), - executable = true, - supportsWrite = TransferSizes(1, 128), - supportsRead = TransferSizes(1, 128))), - beatBytes = 8))) - - val control = AXI4SlaveNode(Seq(AXI4SlavePortParameters( - slaves = Seq(AXI4SlaveParameters( - address = List(AddressSet(0x2000000000L, 0x3ffffffL)), // when truncated to 32-bits, is 0 - resources = device.reg("control"), - supportsWrite = TransferSizes(1, 4), - supportsRead = TransferSizes(1, 4), - interleavedId = Some(0))), // AXI4-Lite never interleaves responses - beatBytes = 4))) - - val master = AXI4MasterNode(Seq(AXI4MasterPortParameters( - masters = Seq(AXI4MasterParameters( - name = "VC709 PCIe", - id = IdRange(0, 1), - aligned = false))))) - - val intnode = IntSourceNode(IntSourcePortSimple(resources = device.int)) - - lazy val module = new LazyModuleImp(this) { - // The master on the control port must be AXI-lite - require (control.edges.in(0).master.endId == 1) - // Must have exactly the right number of idBits - require (slave.edges.in(0).bundle.idBits == 4) - - class VC709AXIToPCIeX1IOBundle extends Bundle with VC709AXIToPCIeX1IOSerial - with VC709AXIToPCIeX1IOClocksReset; - - val io = IO(new Bundle { - val port = new VC709AXIToPCIeX1IOBundle - val refclk = Bool(INPUT) // REFCLK is changed to refclk in 3.0 - }) - - val blackbox = Module(new vc709axi_to_pcie_x1) - - val (s, _) = slave.in(0) - val (c, _) = control.in(0) - val (m, _) = master.out(0) - val (i, _) = intnode.out(0) - - //to top level - blackbox.io.axi_aresetn := io.port.axi_aresetn - io.port.axi_aclk := blackbox.io.axi_aclk - io.port.pci_exp_txp := blackbox.io.pci_exp_txp - io.port.pci_exp_txn := blackbox.io.pci_exp_txn - blackbox.io.pci_exp_rxp := io.port.pci_exp_rxp - blackbox.io.pci_exp_rxn := io.port.pci_exp_rxn - i(0) := blackbox.io.interrupt_out - blackbox.io.refclk := io.refclk - - // AXI Slave Interface - // write address - blackbox.io.s_axi_awid := s.aw.bits.id - blackbox.io.s_axi_awaddr := s.aw.bits.addr - blackbox.io.s_axi_awlen := s.aw.bits.len - blackbox.io.s_axi_awsize := s.aw.bits.size - blackbox.io.s_axi_awburst := s.aw.bits.burst - blackbox.io.s_axi_awregion := UInt(0) - blackbox.io.s_axi_awvalid := s.aw.valid - s.aw.ready := blackbox.io.s_axi_awready - // write data - blackbox.io.s_axi_wdata := s.w.bits.data - blackbox.io.s_axi_wstrb := s.w.bits.strb - blackbox.io.s_axi_wlast := s.w.bits.last - blackbox.io.s_axi_wvalid := s.w.valid - s.w.ready := blackbox.io.s_axi_wready - // write response - s.b.bits.id := blackbox.io.s_axi_bid - s.b.bits.resp := blackbox.io.s_axi_bresp - s.b.valid := blackbox.io.s_axi_bvalid - blackbox.io.s_axi_bready := s.b.ready - // read address - blackbox.io.s_axi_arid := s.ar.bits.id - blackbox.io.s_axi_araddr := s.ar.bits.addr - blackbox.io.s_axi_arlen := s.ar.bits.len - blackbox.io.s_axi_arsize := s.ar.bits.size - blackbox.io.s_axi_arburst := s.ar.bits.burst - blackbox.io.s_axi_arregion := UInt(0) - blackbox.io.s_axi_arvalid := s.ar.valid - s.ar.ready := blackbox.io.s_axi_arready - // read data - s.r.bits.id := blackbox.io.s_axi_rid - s.r.bits.data := blackbox.io.s_axi_rdata - s.r.bits.resp := blackbox.io.s_axi_rresp - s.r.bits.last := blackbox.io.s_axi_rlast - s.r.valid := blackbox.io.s_axi_rvalid - blackbox.io.s_axi_rready := s.r.ready - - // AXI4-Lite Control Interface - // write address - blackbox.io.s_axi_ctl_awaddr := c.aw.bits.addr - blackbox.io.s_axi_ctl_awvalid := c.aw.valid - c.aw.ready := blackbox.io.s_axi_ctl_awready - // write data - blackbox.io.s_axi_ctl_wdata := c.w.bits.data - blackbox.io.s_axi_ctl_wstrb := c.w.bits.strb - blackbox.io.s_axi_ctl_wvalid := c.w.valid - c.w.ready := blackbox.io.s_axi_ctl_wready - // write response - blackbox.io.s_axi_ctl_bready := c.b.ready - c.b.bits.id := UInt(0) - c.b.bits.resp := blackbox.io.s_axi_ctl_bresp - c.b.valid := blackbox.io.s_axi_ctl_bvalid - // read address - blackbox.io.s_axi_ctl_araddr := c.ar.bits.addr - blackbox.io.s_axi_ctl_arvalid := c.ar.valid - c.ar.ready := blackbox.io.s_axi_ctl_arready - // read data - blackbox.io.s_axi_ctl_rready := c.r.ready - c.r.bits.id := UInt(0) - c.r.bits.data := blackbox.io.s_axi_ctl_rdata - c.r.bits.resp := blackbox.io.s_axi_ctl_rresp - c.r.bits.last := Bool(true) - c.r.valid := blackbox.io.s_axi_ctl_rvalid - - // AXI Master Interface - // write address - m.aw.bits.id := UInt(0) - m.aw.bits.addr := blackbox.io.m_axi_awaddr - m.aw.bits.len := blackbox.io.m_axi_awlen - m.aw.bits.size := blackbox.io.m_axi_awsize - m.aw.bits.burst := blackbox.io.m_axi_awburst - m.aw.bits.prot := blackbox.io.m_axi_awprot - m.aw.bits.lock := blackbox.io.m_axi_awlock - m.aw.bits.cache := blackbox.io.m_axi_awcache - m.aw.bits.qos := UInt(0) - m.aw.valid := blackbox.io.m_axi_awvalid - blackbox.io.m_axi_awready := m.aw.ready - // write data - m.w.bits.data := blackbox.io.m_axi_wdata - m.w.bits.strb := blackbox.io.m_axi_wstrb - m.w.bits.last := blackbox.io.m_axi_wlast - m.w.valid := blackbox.io.m_axi_wvalid - blackbox.io.m_axi_wready := m.w.ready - // write response - blackbox.io.m_axi_bresp := m.b.bits.resp - blackbox.io.m_axi_bvalid := m.b.valid - m.b.ready := blackbox.io.m_axi_bready - // read address - m.ar.bits.id := UInt(0) - m.ar.bits.addr := blackbox.io.m_axi_araddr - m.ar.bits.len := blackbox.io.m_axi_arlen - m.ar.bits.size := blackbox.io.m_axi_arsize - m.ar.bits.burst := blackbox.io.m_axi_arburst - m.ar.bits.lock := blackbox.io.m_axi_arlock - m.ar.bits.cache := blackbox.io.m_axi_arcache - m.ar.bits.prot := blackbox.io.m_axi_arprot - m.ar.bits.qos := UInt(0) - m.ar.valid := blackbox.io.m_axi_arvalid - blackbox.io.m_axi_arready := m.ar.ready - // read data - blackbox.io.m_axi_rdata := m.r.bits.data - blackbox.io.m_axi_rresp := m.r.bits.resp - blackbox.io.m_axi_rlast := m.r.bits.last - blackbox.io.m_axi_rvalid := m.r.valid - m.r.ready := blackbox.io.m_axi_rready - } - - ElaborationArtefacts.add( - "vc709axi_to_pcie_x1.vivado.tcl", - """ - create_ip -vendor xilinx.com -library ip -version 3.0 -name axi_pcie3 -module_name vc709axi_to_pcie_x1 -dir $ipdir -force - set_property -dict [list \ - CONFIG.AXIBAR2PCIEBAR_0 {0x40000000} \ - CONFIG.AXIBAR_0 {0x40000000} \ - CONFIG.AXIBAR_HIGHADDR_0 {0x5FFFFFFF} \ - CONFIG.AXIBAR_NUM {1} \ - CONFIG.BASEADDR {0x00000000} \ - CONFIG.HIGHADDR {0x03FFFFFF} \ - CONFIG.DEVICE_PORT_TYPE {Root_Port_of_PCI_Express_Root_Complex} \ - CONFIG.INCLUDE_BAROFFSET_REG {true} \ - CONFIG.PCIEBAR2AXIBAR_0 {0x00000000} \ - CONFIG.PCIE_BLK_LOCN {X0Y0} \ - CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \ - CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {2.5_GT/s} \ - CONFIG.PF0_DEVICE_ID {7118} \ - CONFIG.PF0_REVISION_ID {0} \ - CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10EE} \ - CONFIG.PF0_SUBSYSTEM_ID {0007} \ - CONFIG.PF0_BAR0_64BIT {true} \ - CONFIG.PF0_BAR0_ENABLED {true} \ - CONFIG.PF0_BAR0_PREFETCHABLE {false} \ - CONFIG.PF0_BAR0_SCALE {Gigabytes} \ - CONFIG.PF0_BAR0_SIZE {4} \ - CONFIG.PF0_BAR0_TYPE {Memory} \ - CONFIG.PF0_BASE_CLASS_MENU {Bridge_device} \ - CONFIG.PF0_SUB_CLASS_interface_menu {Host_bridge} \ - CONFIG.PF0_CLASS_CODE {0x060000} \ - CONFIG.COMP_TIMEOUT {50ms} \ - CONFIG.REF_CLK_FREQ {100_MHz} \ - CONFIG.AXI_ADDR_WIDTH {64} \ - CONFIG.AXI_DATA_WIDTH {128_bit} \ - CONFIG.C_S_AXI_SUPPORTS_NARROW_BURST {false} \ - CONFIG.XLNX_REF_BOARD {VC709} ] [get_ips vc709axi_to_pcie_x1]""" - ) -} diff --git a/src/main/scala/shell/PCIeOverlay.scala b/src/main/scala/shell/PCIeOverlay.scala index 37ea0356..d6ed571d 100644 --- a/src/main/scala/shell/PCIeOverlay.scala +++ b/src/main/scala/shell/PCIeOverlay.scala @@ -8,9 +8,6 @@ import freechips.rocketchip.tilelink._ import freechips.rocketchip.interrupts._ import sifive.fpgashells.clocks._ -import sifive.fpgashells.devices.xilinx.xilinxvc709pciex1.{XilinxVC709PCIeX1Pads, XilinxVC709PCIeX1} -import sifive.fpgashells.shell.xilinx.{Series7Shell} - case class PCIeShellInput() case class PCIeDesignInput( wrangler: ClockAdapterNode, diff --git a/src/main/scala/shell/xilinx/VC709NewShell.scala b/src/main/scala/shell/xilinx/VC709NewShell.scala index 70619b0b..03eceabf 100644 --- a/src/main/scala/shell/xilinx/VC709NewShell.scala +++ b/src/main/scala/shell/xilinx/VC709NewShell.scala @@ -12,7 +12,7 @@ import sifive.fpgashells.shell._ import sifive.fpgashells.ip.xilinx._ import sifive.blocks.devices.chiplink._ import sifive.fpgashells.devices.xilinx.xilinxvc709mig._ -import sifive.fpgashells.devices.xilinx.xilinxvc709pciex1._ +import sifive.fpgashells.devices.xilinx.xilinxvc709pcie._ class SysClockVC709PlacedOverlay(val shell: VC709ShellBasicOverlays, name: String, val designInput: ClockInputDesignInput, val shellInput: ClockInputShellInput) extends LVDSClockInputXilinxPlacedOverlay(name, designInput, shellInput) @@ -196,9 +196,9 @@ class DDR3VC709ShellPlacer(shell: VC709ShellBasicOverlays, val shellInput: DDRSh } class PCIeVC709PlacedOverlay(val shell: VC709ShellBasicOverlays, name: String, val designInput: PCIeDesignInput, val shellInput: PCIeShellInput) - extends PCIePlacedOverlay[XilinxVC709PCIeX1Pads](name, designInput, shellInput) + extends PCIePlacedOverlay[XilinxVC709PCIePads](name, designInput, shellInput) { - val pcie = LazyModule(new XilinxVC709PCIeX1) + val pcie = LazyModule(new XilinxVC709PCIe) val bridge = BundleBridgeSource(() => pcie.module.io.cloneType) val topBridge = shell { bridge.makeSink() } val axiClk = shell { ClockSourceNode(freqMHz = 125) } @@ -214,7 +214,7 @@ class PCIeVC709PlacedOverlay(val shell: VC709ShellBasicOverlays, name: String, v val intNode = pcie.crossIntOut(pcie.intnode) def overlayOutput = PCIeOverlayOutput(pcieNode, intNode) - def ioFactory = new XilinxVC709PCIeX1Pads + def ioFactory = new XilinxVC709PCIePads InModuleBody { bridge.bundle <> pcie.module.io } From 6428e4af5876e1f7f67854b202574c129f9d4004 Mon Sep 17 00:00:00 2001 From: mbs0221 Date: Sun, 1 Aug 2021 22:52:27 +0800 Subject: [PATCH 23/26] update VC709NewShell --- src/main/scala/shell/xilinx/VC709NewShell.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/shell/xilinx/VC709NewShell.scala b/src/main/scala/shell/xilinx/VC709NewShell.scala index 3876878a..d35c59d7 100644 --- a/src/main/scala/shell/xilinx/VC709NewShell.scala +++ b/src/main/scala/shell/xilinx/VC709NewShell.scala @@ -177,8 +177,8 @@ class DDR3VC709PlacedOverlay(val shell: VC709ShellBasicOverlays, name: String, v port.aresetn := !ar.reset } } - // shell.sdc.addGroup(clocks = Seq("clk_pll_i")) - shell.sdc.addGroup(pins = Seq(mig.island.module.blackbox.io.ui_clk)) + shell.sdc.addGroup(clocks = Seq("clk_pll_i")) + // shell.sdc.addGroup(pins = Seq(mig.island.module.blackbox.io.ui_clk)) } class DDR3VC709ShellPlacer(shell: VC709ShellBasicOverlays, val shellInput: DDRShellInput)(implicit val valName: ValName) extends DDRShellPlacer[VC709ShellBasicOverlays] { From f67e638a75763558f96178e475c41e7118a61f8a Mon Sep 17 00:00:00 2001 From: mbs0221 Date: Fri, 27 Aug 2021 17:04:33 +0800 Subject: [PATCH 24/26] update I2C module --- src/main/scala/shell/SPIOverlay.scala | 2 +- src/main/scala/shell/xilinx/VC709NewShell.scala | 9 ++++----- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/src/main/scala/shell/SPIOverlay.scala b/src/main/scala/shell/SPIOverlay.scala index 996d9e7b..e939cb42 100644 --- a/src/main/scala/shell/SPIOverlay.scala +++ b/src/main/scala/shell/SPIOverlay.scala @@ -11,7 +11,7 @@ import freechips.rocketchip.tilelink.TLBusWrapper import freechips.rocketchip.interrupts.IntInwardNode //This should not do the controller placement either -case class SPIShellInput() +case class SPIShellInput(index: Int = 0) case class SPIDesignInput(spiParam: SPIParams, node: BundleBridgeSource[SPIPortIO])(implicit val p: Parameters) case class SPIOverlayOutput() case object SPIOverlayKey extends Field[Seq[DesignPlacer[SPIDesignInput, SPIShellInput, SPIOverlayOutput]]](Nil) diff --git a/src/main/scala/shell/xilinx/VC709NewShell.scala b/src/main/scala/shell/xilinx/VC709NewShell.scala index 03eceabf..1e24507e 100644 --- a/src/main/scala/shell/xilinx/VC709NewShell.scala +++ b/src/main/scala/shell/xilinx/VC709NewShell.scala @@ -35,12 +35,11 @@ class I2CVC709PlacedOverlay(val shell: VC709ShellBasicOverlays, name: String, va extends I2CXilinxPlacedOverlay(name, designInput, shellInput) { shell { InModuleBody { - val packagePinsWithPackageIOs = Seq(("AU32", IOPin(io.sda)), - ("AT35", IOPin(io.scl))) + val packagePinsWithPackageIOs = Seq(("U52.3", IOPin(io.sda)), + ("U52.4", IOPin(io.scl))) packagePinsWithPackageIOs foreach { case (pin, io) => { shell.xdc.addPackagePin(io, pin) - shell.xdc.addIOStandard(io, "LVCMOS18") shell.xdc.addIOB(io) } } } } @@ -265,8 +264,8 @@ abstract class VC709ShellBasicOverlays()(implicit p: Parameters) extends Series7 val led = Seq.tabulate(8)(i => Overlay(LEDOverlayKey, new LEDVC709ShellPlacer(this, LEDShellInput(color = "red", number = i))(valName = ValName(s"led_$i")))) val switch = Seq.tabulate(8)(i => Overlay(SwitchOverlayKey, new SwitchVC709ShellPlacer(this, SwitchShellInput(number = i))(valName = ValName(s"switch_$i")))) val button = Seq.tabulate(5)(i => Overlay(ButtonOverlayKey, new ButtonVC709ShellPlacer(this, ButtonShellInput(number = i))(valName = ValName(s"button_$i")))) - val i2c = Seq.tabulate(1)(i => Overlay(I2COverlayKey, new I2CVC709ShellPlacer(this, I2CShellInput(index = i)))) - val uart = Seq.tabulate(1)(i => Overlay(UARTOverlayKey, new UARTVC709ShellPlacer(this, UARTShellInput(index = i)))) + val i2c0 = Seq.tabulate(1)(i => Overlay(I2COverlayKey, new I2CVC709ShellPlacer(this, I2CShellInput(index = i)))) + val uart0 = Seq.tabulate(1)(i => Overlay(UARTOverlayKey, new UARTVC709ShellPlacer(this, UARTShellInput(index = i)))) val jtag = Overlay(JTAGDebugOverlayKey, new JTAGDebugVC709ShellPlacer(this, JTAGDebugShellInput())) val chiplink = Overlay(ChipLinkOverlayKey, new ChipLinkVC709ShellPlacer(this, ChipLinkShellInput())) val ddr0 = Overlay(DDROverlayKey, new DDR3VC709ShellPlacer(this, DDRShellInput())) From 17bb3eec417e83e9b5b5b01205e160ce3d0232cc Mon Sep 17 00:00:00 2001 From: mbs0221 Date: Wed, 1 Sep 2021 15:59:14 +0800 Subject: [PATCH 25/26] update support for vc709mig --- .../scala/ip/xilinx/vc709mig/vc709mig.scala | 234 +++++++++--------- .../scala/shell/xilinx/VC709NewShell.scala | 73 +----- 2 files changed, 130 insertions(+), 177 deletions(-) diff --git a/src/main/scala/ip/xilinx/vc709mig/vc709mig.scala b/src/main/scala/ip/xilinx/vc709mig/vc709mig.scala index fe4f60d8..86942cc8 100644 --- a/src/main/scala/ip/xilinx/vc709mig/vc709mig.scala +++ b/src/main/scala/ip/xilinx/vc709mig/vc709mig.scala @@ -123,7 +123,7 @@ class vc709mig(depth : BigInt)(implicit val p:Parameters) extends BlackBox // val device_temp = Bits(OUTPUT,12) } - val vc709mig_a = """ { + val vc709mig_a = """ { vc709mig_a @@ -373,122 +373,122 @@ class vc709mig(depth : BigInt)(implicit val p:Parameters) extends BlackBox 1.5V BANK_ROW_COLUMN - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/src/main/scala/shell/xilinx/VC709NewShell.scala b/src/main/scala/shell/xilinx/VC709NewShell.scala index 1e24507e..e80266df 100644 --- a/src/main/scala/shell/xilinx/VC709NewShell.scala +++ b/src/main/scala/shell/xilinx/VC709NewShell.scala @@ -31,24 +31,6 @@ class SysClockVC709ShellPlacer(shell: VC709ShellBasicOverlays, val shellInput: C def place(designInput: ClockInputDesignInput) = new SysClockVC709PlacedOverlay(shell, valName.name, designInput, shellInput) } -class I2CVC709PlacedOverlay(val shell: VC709ShellBasicOverlays, name: String, val designInput: I2CDesignInput, val shellInput: I2CShellInput) - extends I2CXilinxPlacedOverlay(name, designInput, shellInput) -{ - shell { InModuleBody { - val packagePinsWithPackageIOs = Seq(("U52.3", IOPin(io.sda)), - ("U52.4", IOPin(io.scl))) - - packagePinsWithPackageIOs foreach { case (pin, io) => { - shell.xdc.addPackagePin(io, pin) - shell.xdc.addIOB(io) - } } - } } -} -class I2CVC709ShellPlacer(val shell: VC709ShellBasicOverlays, val shellInput: I2CShellInput)(implicit val valName: ValName) - extends I2CShellPlacer[VC709ShellBasicOverlays] { - def place(designInput: I2CDesignInput) = new I2CVC709PlacedOverlay(shell, valName.name, designInput, shellInput) -} - class UARTVC709PlacedOverlay(val shell: VC709ShellBasicOverlays, name: String, val designInput: UARTDesignInput, val shellInput: UARTShellInput) extends UARTXilinxPlacedOverlay(name, designInput, shellInput, true) { @@ -70,59 +52,36 @@ class UARTVC709ShellPlacer(val shell: VC709ShellBasicOverlays, val shellInput: U def place(designInput: UARTDesignInput) = new UARTVC709PlacedOverlay(shell, valName.name, designInput, shellInput) } +object LEDVC709PinConstraints { + val pins = Seq("AM39","AN39","AR37","AT37","AR35","AP41","AP42","AU39") +} class LEDVC709PlacedOverlay(val shell: VC709ShellBasicOverlays, name: String, val designInput: LEDDesignInput, val shellInput: LEDShellInput) - extends LEDXilinxPlacedOverlay(name, designInput, shellInput, boardPin = Some(s"leds_8bits_tri_o_${shellInput.number}"), ioStandard = "LVCMOS18") + extends LEDXilinxPlacedOverlay(name, designInput, shellInput, packagePin = Some(LEDVC709PinConstraints.pins(shellInput.number)), ioStandard = "LVCMOS18") class LEDVC709ShellPlacer(val shell: VC709ShellBasicOverlays, val shellInput: LEDShellInput)(implicit val valName: ValName) extends LEDShellPlacer[VC709ShellBasicOverlays] { def place(designInput: LEDDesignInput) = new LEDVC709PlacedOverlay(shell, valName.name, designInput, shellInput) } +object SwitchVC709PinConstraints { + val pins = Seq("AV30","AY33","BA31","BA32","AW30","AY30","BA30","BB31") +} class SwitchVC709PlacedOverlay(val shell: VC709ShellBasicOverlays, name: String, val designInput: SwitchDesignInput, val shellInput: SwitchShellInput) - extends SwitchXilinxPlacedOverlay(name, designInput, shellInput, boardPin = Some(s"dip_switches_tri_i_${shellInput.number}"), ioStandard = "LVCMOS18") + extends SwitchXilinxPlacedOverlay(name, designInput, shellInput, packagePin = Some(SwitchVC709PinConstraints.pins(shellInput.number)), ioStandard = "LVCMOS18") class SwitchVC709ShellPlacer(val shell: VC709ShellBasicOverlays, val shellInput: SwitchShellInput)(implicit val valName: ValName) extends SwitchShellPlacer[VC709ShellBasicOverlays] { def place(designInput: SwitchDesignInput) = new SwitchVC709PlacedOverlay(shell, valName.name, designInput, shellInput) } +object ButtonVC709PinConstraints { + val pins = Seq("AR40","AU38","AP40","AW40","AV39") +} class ButtonVC709PlacedOverlay(val shell: VC709ShellBasicOverlays, name: String, val designInput: ButtonDesignInput, val shellInput: ButtonShellInput) - extends ButtonXilinxPlacedOverlay(name, designInput, shellInput, boardPin = Some(s"push_buttons_5bits_tri_i_${shellInput.number}"), ioStandard = "LVCMOS18") + extends ButtonXilinxPlacedOverlay(name, designInput, shellInput, packagePin = Some(ButtonVC709PinConstraints.pins(shellInput.number)), ioStandard = "LVCMOS18") class ButtonVC709ShellPlacer(val shell: VC709ShellBasicOverlays, val shellInput: ButtonShellInput)(implicit val valName: ValName) extends ButtonShellPlacer[VC709ShellBasicOverlays] { def place(designInput: ButtonDesignInput) = new ButtonVC709PlacedOverlay(shell, valName.name, designInput, shellInput) } -class ChipLinkVC709PlacedOverlay(val shell: VC709ShellBasicOverlays, name: String, val designInput: ChipLinkDesignInput, val shellInput: ChipLinkShellInput) - extends ChipLinkXilinxPlacedOverlay(name, designInput, shellInput, rxPhase=280, txPhase=220, rxMargin=0.3, txMargin=0.3) -{ - val ereset_n = shell { InModuleBody { - val ereset_n = IO(Input(Bool())) - ereset_n.suggestName("ereset_n") - shell.xdc.addPackagePin(ereset_n, "AF40") - shell.xdc.addIOStandard(ereset_n, "LVCMOS18") - shell.xdc.addTermination(ereset_n, "NONE") - ereset_n - } } - - shell { InModuleBody { - val dir1 = Seq("AF39", "AJ41", "AJ40", /* clk, rst, send */ - "AD40", "AD41", "AF41", "AG41", "AK39", "AL39", "AJ42", "AK42", - "AL41", "AL42", "AF42", "AG42", "AD38", "AE38", "AC40", "AC41", - "AD42", "AE42", "AJ38", "AK38", "AB41", "AB42", "Y42", "AA42", - "Y39", "AA39", "W40", "Y40", "AB38", "AB39", "AC38", "AC39") - val dir2 = Seq("U39", "R37", "T36", /* clk, rst, send */ - "U37", "U38", "U36", "T37", "U32", "U33", "V33", "V34", - "P35", "P36", "W32", "W33", "R38", "R39", "U34", "T35", - "R33", "R34", "N33", "N34", "P32", "P33", "V35", "V36", - "W36", "W37", "T32", "R32", "V39", "V40", "P37", "P38") - (IOPin.of(io.b2c) zip dir1) foreach { case (io, pin) => shell.xdc.addPackagePin(io, pin) } - (IOPin.of(io.c2b) zip dir2) foreach { case (io, pin) => shell.xdc.addPackagePin(io, pin) } - } } -} -class ChipLinkVC709ShellPlacer(val shell: VC709ShellBasicOverlays, val shellInput: ChipLinkShellInput)(implicit val valName: ValName) - extends ChipLinkShellPlacer[VC709ShellBasicOverlays] { - def place(designInput: ChipLinkDesignInput) = new ChipLinkVC709PlacedOverlay(shell, valName.name, designInput, shellInput) -} - // TODO: JTAG is untested class JTAGDebugVC709PlacedOverlay(val shell: VC709ShellBasicOverlays, name: String, val designInput: JTAGDebugDesignInput, val shellInput: JTAGDebugShellInput) extends JTAGDebugXilinxPlacedOverlay(name, designInput, shellInput) @@ -264,10 +223,8 @@ abstract class VC709ShellBasicOverlays()(implicit p: Parameters) extends Series7 val led = Seq.tabulate(8)(i => Overlay(LEDOverlayKey, new LEDVC709ShellPlacer(this, LEDShellInput(color = "red", number = i))(valName = ValName(s"led_$i")))) val switch = Seq.tabulate(8)(i => Overlay(SwitchOverlayKey, new SwitchVC709ShellPlacer(this, SwitchShellInput(number = i))(valName = ValName(s"switch_$i")))) val button = Seq.tabulate(5)(i => Overlay(ButtonOverlayKey, new ButtonVC709ShellPlacer(this, ButtonShellInput(number = i))(valName = ValName(s"button_$i")))) - val i2c0 = Seq.tabulate(1)(i => Overlay(I2COverlayKey, new I2CVC709ShellPlacer(this, I2CShellInput(index = i)))) val uart0 = Seq.tabulate(1)(i => Overlay(UARTOverlayKey, new UARTVC709ShellPlacer(this, UARTShellInput(index = i)))) val jtag = Overlay(JTAGDebugOverlayKey, new JTAGDebugVC709ShellPlacer(this, JTAGDebugShellInput())) - val chiplink = Overlay(ChipLinkOverlayKey, new ChipLinkVC709ShellPlacer(this, ChipLinkShellInput())) val ddr0 = Overlay(DDROverlayKey, new DDR3VC709ShellPlacer(this, DDRShellInput())) val pcie = Overlay(PCIeOverlayKey, new PCIeVC709ShellPlacer(this, PCIeShellInput())(valName = ValName(s"pcie"))) } @@ -292,11 +249,7 @@ class VC709BaseShell()(implicit p: Parameters) extends VC709ShellBasicOverlays val powerOnReset = PowerOnResetFPGAOnly(sysclk) sdc.addAsyncPath(Seq(powerOnReset)) - val ereset: Bool = chiplink.get() match { - case Some(x: ChipLinkVC709PlacedOverlay) => !x.ereset_n - case _ => false.B - } pllReset := - reset_ibuf.io.O || powerOnReset || ereset + reset_ibuf.io.O || powerOnReset || false.B } } From ad40b2bad7f2d7b1ce2b46095692333a17bad7c0 Mon Sep 17 00:00:00 2001 From: mbs0221 Date: Wed, 17 Nov 2021 14:15:06 +0800 Subject: [PATCH 26/26] fix dual MIGs --- .../scala/ip/xilinx/vc709mig/vc709mig.scala | 62 ++++++++----------- src/main/scala/shell/xilinx/DDR3Overlay.scala | 1 + 2 files changed, 28 insertions(+), 35 deletions(-) diff --git a/src/main/scala/ip/xilinx/vc709mig/vc709mig.scala b/src/main/scala/ip/xilinx/vc709mig/vc709mig.scala index 86942cc8..c13fe735 100644 --- a/src/main/scala/ip/xilinx/vc709mig/vc709mig.scala +++ b/src/main/scala/ip/xilinx/vc709mig/vc709mig.scala @@ -2,6 +2,7 @@ package sifive.fpgashells.ip.xilinx.vc709mig import Chisel._ +import chisel3.util._ import chisel3.experimental.{Analog,attach} import freechips.rocketchip.util.{ElaborationArtefacts} import freechips.rocketchip.util.GenericParameterizedBundle @@ -11,7 +12,7 @@ import freechips.rocketchip.config._ // Black Box class VC709MIGIODDR(depth : BigInt) extends GenericParameterizedBundle(depth) { - require((depth<=0x100000000L),"VC709MIGIODDR supports upto 4GB depth configuraton") + require((depth<=0x200000000L),"VC709MIGIODDR supports upto 4GB depth configuraton") val ddr3_addr = Bits(OUTPUT,16) val ddr3_ba = Bits(OUTPUT,3) val ddr3_ras_n = Bool(OUTPUT) @@ -45,27 +46,16 @@ trait VC709MIGIOClocksReset extends Bundle { val sys_rst = Bool(INPUT) } -object vc709mig -{ - var vc709migNo = 0 - def alloc = { - vc709migNo += 1 - vc709migNo - } - def last = { - vc709mig.vc709migNo - 1 - } -} - //scalastyle:off //turn off linter: blackbox name must match verilog module class vc709mig(depth : BigInt)(implicit val p:Parameters) extends BlackBox { - require((depth<=0x100000000L), "vc709mig supports upto 4GB depth configuraton") - require((vc709mig.alloc <= 2), "vc709mig supports upto two memory controllers") + require((depth<=0x200000000L), "vc709mig supports upto 8GB depth configuraton") - val index = vc709mig.last - override def desiredName = Seq("vc709mig_a", "vc709mig_b")(index) + override def desiredName = "vc709mig_a" + + def DDR3_ADDR_WIDTH = 32 + def DDR3_DATA_WIDTH = 64 val io = new VC709MIGIODDR(depth) with VC709MIGIOClocksReset { // User interface signals @@ -78,7 +68,7 @@ class vc709mig(depth : BigInt)(implicit val p:Parameters) extends BlackBox //axi_s //slave interface write address ports val s_axi_awid = Bits(INPUT,4) - val s_axi_awaddr = Bits(INPUT,32) + val s_axi_awaddr = Bits(INPUT,DDR3_ADDR_WIDTH) val s_axi_awlen = Bits(INPUT,8) val s_axi_awsize = Bits(INPUT,3) val s_axi_awburst = Bits(INPUT,2) @@ -89,7 +79,7 @@ class vc709mig(depth : BigInt)(implicit val p:Parameters) extends BlackBox val s_axi_awvalid = Bool(INPUT) val s_axi_awready = Bool(OUTPUT) //slave interface write data ports - val s_axi_wdata = Bits(INPUT,64) + val s_axi_wdata = Bits(INPUT,DDR3_DATA_WIDTH) val s_axi_wstrb = Bits(INPUT,8) val s_axi_wlast = Bool(INPUT) val s_axi_wvalid = Bool(INPUT) @@ -101,7 +91,7 @@ class vc709mig(depth : BigInt)(implicit val p:Parameters) extends BlackBox val s_axi_bvalid = Bool(OUTPUT) //slave interface read address ports val s_axi_arid = Bits(INPUT,4) - val s_axi_araddr = Bits(INPUT,32) + val s_axi_araddr = Bits(INPUT,DDR3_ADDR_WIDTH) val s_axi_arlen = Bits(INPUT,8) val s_axi_arsize = Bits(INPUT,3) val s_axi_arburst = Bits(INPUT,2) @@ -114,7 +104,7 @@ class vc709mig(depth : BigInt)(implicit val p:Parameters) extends BlackBox //slave interface read data ports val s_axi_rready = Bool(INPUT) val s_axi_rid = Bits(OUTPUT,4) - val s_axi_rdata = Bits(OUTPUT,64) + val s_axi_rdata = Bits(OUTPUT,DDR3_DATA_WIDTH) val s_axi_rresp = Bits(OUTPUT,2) val s_axi_rlast = Bool(OUTPUT) val s_axi_rvalid = Bool(OUTPUT) @@ -531,20 +521,22 @@ class vc709mig(depth : BigInt)(implicit val p:Parameters) extends BlackBox }""" - val migprj = Seq(vc709mig_a, vc709mig_b)(index) - val migprjname = Seq("{/vc709mig_a.prj}", "{/vc709mig_b.prj}")(index) - val modulename = Seq("vc709mig_a", "vc709mig_b")(index) + def add_vc709mig(migprj : String, modulename : String) = + ElaborationArtefacts.add( + "%1$s.vivado.tcl".format(modulename), + """set migprj %1$s + set migprjfile {/%2$s.prj} + set migprjfilepath $ipdir$migprjfile + set fp [open $migprjfilepath w+] + puts $fp $migprj + close $fp + create_ip -vendor xilinx.com -library ip -name mig_7series -module_name %2$s -dir $ipdir -force + set_property CONFIG.XML_INPUT_FILE $migprjfilepath [get_ips %2$s] """.format(migprj, modulename) + ) + + add_vc709mig(vc709mig_a, "vc709mig_a") + add_vc709mig(vc709mig_b, "vc709mig_b") - ElaborationArtefacts.add( - modulename++".vivado.tcl", - """set migprj """ ++ migprj ++ """ - set migprjfile """ ++ migprjname ++ """ - set migprjfilepath $ipdir$migprjfile - set fp [open $migprjfilepath w+] - puts $fp $migprj - close $fp - create_ip -vendor xilinx.com -library ip -name mig_7series -module_name """ ++ modulename ++ """ -dir $ipdir -force - set_property CONFIG.XML_INPUT_FILE $migprjfilepath [get_ips """ ++ modulename ++ """] """ - ) + // addResource("/vsrc/vc709mig8gb.v") } //scalastyle:on diff --git a/src/main/scala/shell/xilinx/DDR3Overlay.scala b/src/main/scala/shell/xilinx/DDR3Overlay.scala index 1e4e9cd5..4203e52e 100644 --- a/src/main/scala/shell/xilinx/DDR3Overlay.scala +++ b/src/main/scala/shell/xilinx/DDR3Overlay.scala @@ -13,6 +13,7 @@ import sifive.blocks.devices.chiplink._ import sifive.fpgashells.devices.xilinx.xilinxvc709mig._ case object VC709DDR3Size extends Field[BigInt](0x100000000L) // 4GB +case object DualVC709DDR3Size extends Field[BigInt](0x200000000L) // 8GB abstract class DDR3XilinxPlacedOverlay(shell: VC709ShellBasicOverlays, name: String, designInput: DDRDesignInput, shellInput: DDRShellInput) extends DDRPlacedOverlay[XilinxVC709MIGPads](name, designInput, shellInput) {