Merge pull request #67 from sifive/bump-all

terpstra · web-flow · commit 397c395b8216 · 2018-06-08T17:16:18.000+02:00
Bump all sub-repositories
diff --git a/Makefile.e300artydevkit b/Makefile.e300artydevkit
@@ -12,8 +12,8 @@ export BOOTROM_DIR := $(base_dir)/bootrom/xip
 rocketchip_dir := $(base_dir)/rocket-chip
 sifiveblocks_dir := $(base_dir)/sifive-blocks
 VSRCS := \
-	$(rocketchip_dir)/vsrc/AsyncResetReg.v \
-	$(rocketchip_dir)/vsrc/plusarg_reader.v \
+	$(rocketchip_dir)/src/main/resources/vsrc/AsyncResetReg.v \
+	$(rocketchip_dir)/src/main/resources/vsrc/plusarg_reader.v \
 	$(sifiveblocks_dir)/vsrc/SRLatch.v \
 	$(FPGA_DIR)/common/vsrc/PowerOnResetFPGAOnly.v \
 	$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.v \
diff --git a/Makefile.u500polarfireevalkit b/Makefile.u500polarfireevalkit
@@ -12,8 +12,8 @@ export BOOTROM_DIR := $(base_dir)/bootrom/sdboot
 rocketchip_dir := $(base_dir)/rocket-chip
 sifiveblocks_dir := $(base_dir)/sifive-blocks
 VSRCS := \
-	$(rocketchip_dir)/vsrc/AsyncResetReg.v \
-	$(rocketchip_dir)/vsrc/plusarg_reader.v \
+	$(rocketchip_dir)/src/main/resources/vsrc/AsyncResetReg.v \
+	$(rocketchip_dir)/src/main/resources/vsrc/plusarg_reader.v \
 	$(sifiveblocks_dir)/vsrc/SRLatch.v \
 	$(FPGA_DIR)/common/vsrc/PowerOnResetFPGAOnly.v \
 	$(FPGA_DIR)/$(BOARD)/vsrc/sdio.v \
diff --git a/Makefile.u500vc707devkit b/Makefile.u500vc707devkit
@@ -12,8 +12,8 @@ export BOOTROM_DIR := $(base_dir)/bootrom/sdboot
 rocketchip_dir := $(base_dir)/rocket-chip
 sifiveblocks_dir := $(base_dir)/sifive-blocks
 VSRCS := \
-	$(rocketchip_dir)/vsrc/AsyncResetReg.v \
-	$(rocketchip_dir)/vsrc/plusarg_reader.v \
+	$(rocketchip_dir)/src/main/resources/vsrc/AsyncResetReg.v \
+	$(rocketchip_dir)/src/main/resources/vsrc/plusarg_reader.v \
 	$(sifiveblocks_dir)/vsrc/SRLatch.v \
 	$(FPGA_DIR)/common/vsrc/PowerOnResetFPGAOnly.v \
 	$(FPGA_DIR)/$(BOARD)/vsrc/sdio.v \
diff --git a/Makefile.u500vc707iofpga b/Makefile.u500vc707iofpga
@@ -11,8 +11,8 @@ export BOARD := vc707
 rocketchip_dir := $(base_dir)/rocket-chip
 sifiveblocks_dir := $(base_dir)/sifive-blocks
 VSRCS := \
-	$(rocketchip_dir)/vsrc/AsyncResetReg.v \
-	$(rocketchip_dir)/vsrc/plusarg_reader.v \
+	$(rocketchip_dir)/src/main/resources/vsrc/AsyncResetReg.v \
+	$(rocketchip_dir)/src/main/resources/vsrc/plusarg_reader.v \
 	$(sifiveblocks_dir)/vsrc/SRLatch.v \
 	$(FPGA_DIR)/common/vsrc/PowerOnResetFPGAOnly.v \
 	$(FPGA_DIR)/$(BOARD)/vsrc/sdio.v \
diff --git a/Makefile.veraiofpga b/Makefile.veraiofpga
@@ -11,8 +11,8 @@ export BOARD := vera
 rocketchip_dir := $(base_dir)/rocket-chip
 sifiveblocks_dir := $(base_dir)/sifive-blocks
 VSRCS := \
-	$(rocketchip_dir)/vsrc/AsyncResetReg.v \
-	$(rocketchip_dir)/vsrc/plusarg_reader.v \
+	$(rocketchip_dir)/src/main/resources/vsrc/AsyncResetReg.v \
+	$(rocketchip_dir)/src/main/resources/vsrc/plusarg_reader.v \
 	$(sifiveblocks_dir)/vsrc/SRLatch.v \
 	$(FPGA_DIR)/common/vsrc/PowerOnResetFPGAOnly.v \
 	$(FPGA_DIR)/$(BOARD)/vsrc/sdio.v \
diff --git a/fpga-shells b/fpga-shells
@@ -1 +1 @@
-Subproject commit bd86017f86573384603dfa8fc1572ae6303241f1
+Subproject commit fba94960ed47dfe579319c153f376f5ede268a2d
diff --git a/rocket-chip b/rocket-chip
@@ -1 +1 @@
-Subproject commit 4ba8acb4aa26901899963136704d065a22e36460
+Subproject commit 846425cc0fe8956f0b8b339320847d9cd2096b65
diff --git a/sifive-blocks b/sifive-blocks
@@ -1 +1 @@
-Subproject commit 3e1e7ac8fcbc5719562e37a2478910173fe87f7f
+Subproject commit c340d7ade16a9bea307685c54a13d830fa90bc3b
diff --git a/src/main/scala/unleashed/u500polarfireevalkit/Config.scala b/src/main/scala/unleashed/u500polarfireevalkit/Config.scala
@@ -47,7 +47,7 @@ class U500PolarFireEvalKitConfig extends Config(
     case MemoryMicrosemiDDR3Key => PolarFireEvalKitDDR3Params(address = Seq(AddressSet(0x80000000L,0x40000000L-1))) //1GB
 //    case MemoryMicrosemiDDR4Key => PolarFireEvalKitDDR4Params(address = Seq(AddressSet(0x80000000L,0x40000000L-1))) //1GB
     case DTSTimebase => BigInt(1000000)
-    case ExtMem => up(ExtMem).copy(size = 0x40000000L)
+    case ExtMem => up(ExtMem).map(_.copy(size = 0x40000000L))
     case JtagDTMKey => new JtagDTMConfig (
       idcodeVersion = 2,      // 1 was legacy (FE310-G000, Acai).
       idcodePartNum = 0x000,  // Decided to simplify.
diff --git a/src/main/scala/unleashed/u500vc707devkit/Config.scala b/src/main/scala/unleashed/u500vc707devkit/Config.scala
@@ -44,7 +44,7 @@ class U500VC707DevKitConfig extends Config(
     case PeripheryBusKey => up(PeripheryBusKey, site).copy(frequency = 50000000) // 50 MHz hperiphery
     case MemoryXilinxDDRKey => XilinxVC707MIGParams(address = Seq(AddressSet(0x80000000L,0x40000000L-1))) //1GB
     case DTSTimebase => BigInt(1000000)
-    case ExtMem => up(ExtMem).copy(size = 0x40000000L)
+    case ExtMem => up(ExtMem).map(_.copy(size = 0x40000000L))
     case JtagDTMKey => new JtagDTMConfig (
       idcodeVersion = 2,      // 1 was legacy (FE310-G000, Acai).
       idcodePartNum = 0x000,  // Decided to simplify.
diff --git a/src/main/scala/unleashed/u500vcu118devkit/Config.scala b/src/main/scala/unleashed/u500vcu118devkit/Config.scala
@@ -44,7 +44,7 @@ class U500VCU118DevKitConfig extends Config(
     case PeripheryBusKey => up(PeripheryBusKey, site).copy(frequency = 50000000) // 50 MHz hperiphery
     case MemoryXilinxDDRKey => XilinxVCU118MIGParams(address = Seq(AddressSet(0x80000000L,0x80000000L-1))) //2GB
     case DTSTimebase => BigInt(1000000)
-    case ExtMem => up(ExtMem).copy(size = 0x80000000L)
+    case ExtMem => up(ExtMem).map(_.copy(size = 0x80000000L))
     case JtagDTMKey => new JtagDTMConfig (
       idcodeVersion = 2,      // 1 was legacy (FE310-G000, Acai).
       idcodePartNum = 0x000,  // Decided to simplify.
diff --git a/src/main/scala/unleashed/u500vera/Config.scala b/src/main/scala/unleashed/u500vera/Config.scala
@@ -46,7 +46,7 @@ class U500VeraConfig extends Config(
     case MemoryMicrosemiDDR3Key => PolarFireEvalKitDDR3Params(address = Seq(AddressSet(0x80000000L,0x40000000L-1))) //1GB
 //    case MemoryMicrosemiDDR4Key => PolarFireEvalKitDDR4Params(address = Seq(AddressSet(0x80000000L,0x40000000L-1))) //1GB
     case DTSTimebase => BigInt(1000000)
-    case ExtMem => up(ExtMem).copy(size = 0x40000000L)
+    case ExtMem => up(ExtMem).map(_.copy(size = 0x40000000L))
     case JtagDTMKey => new JtagDTMConfig (
       idcodeVersion = 2,      // 1 was legacy (FE310-G000, Acai).
       idcodePartNum = 0x000,  // Decided to simplify.
