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Merge pull request #67 from sifive/bump-all

Bump all sub-repositories
  • Loading branch information...
terpstra committed Jun 8, 2018
2 parents 66c9b73 + 50d2f7d commit 397c395b8216c46c3d1b21484d85c6509c3ee7e8
@@ -12,8 +12,8 @@ export BOOTROM_DIR := $(base_dir)/bootrom/xip
rocketchip_dir := $(base_dir)/rocket-chip
sifiveblocks_dir := $(base_dir)/sifive-blocks
VSRCS := \
$(rocketchip_dir)/vsrc/AsyncResetReg.v \
$(rocketchip_dir)/vsrc/plusarg_reader.v \
$(rocketchip_dir)/src/main/resources/vsrc/AsyncResetReg.v \
$(rocketchip_dir)/src/main/resources/vsrc/plusarg_reader.v \
$(sifiveblocks_dir)/vsrc/SRLatch.v \
$(FPGA_DIR)/common/vsrc/PowerOnResetFPGAOnly.v \
$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.v \
@@ -12,8 +12,8 @@ export BOOTROM_DIR := $(base_dir)/bootrom/sdboot
rocketchip_dir := $(base_dir)/rocket-chip
sifiveblocks_dir := $(base_dir)/sifive-blocks
VSRCS := \
$(rocketchip_dir)/vsrc/AsyncResetReg.v \
$(rocketchip_dir)/vsrc/plusarg_reader.v \
$(rocketchip_dir)/src/main/resources/vsrc/AsyncResetReg.v \
$(rocketchip_dir)/src/main/resources/vsrc/plusarg_reader.v \
$(sifiveblocks_dir)/vsrc/SRLatch.v \
$(FPGA_DIR)/common/vsrc/PowerOnResetFPGAOnly.v \
$(FPGA_DIR)/$(BOARD)/vsrc/sdio.v \
@@ -12,8 +12,8 @@ export BOOTROM_DIR := $(base_dir)/bootrom/sdboot
rocketchip_dir := $(base_dir)/rocket-chip
sifiveblocks_dir := $(base_dir)/sifive-blocks
VSRCS := \
$(rocketchip_dir)/vsrc/AsyncResetReg.v \
$(rocketchip_dir)/vsrc/plusarg_reader.v \
$(rocketchip_dir)/src/main/resources/vsrc/AsyncResetReg.v \
$(rocketchip_dir)/src/main/resources/vsrc/plusarg_reader.v \
$(sifiveblocks_dir)/vsrc/SRLatch.v \
$(FPGA_DIR)/common/vsrc/PowerOnResetFPGAOnly.v \
$(FPGA_DIR)/$(BOARD)/vsrc/sdio.v \
@@ -11,8 +11,8 @@ export BOARD := vc707
rocketchip_dir := $(base_dir)/rocket-chip
sifiveblocks_dir := $(base_dir)/sifive-blocks
VSRCS := \
$(rocketchip_dir)/vsrc/AsyncResetReg.v \
$(rocketchip_dir)/vsrc/plusarg_reader.v \
$(rocketchip_dir)/src/main/resources/vsrc/AsyncResetReg.v \
$(rocketchip_dir)/src/main/resources/vsrc/plusarg_reader.v \
$(sifiveblocks_dir)/vsrc/SRLatch.v \
$(FPGA_DIR)/common/vsrc/PowerOnResetFPGAOnly.v \
$(FPGA_DIR)/$(BOARD)/vsrc/sdio.v \
@@ -11,8 +11,8 @@ export BOARD := vera
rocketchip_dir := $(base_dir)/rocket-chip
sifiveblocks_dir := $(base_dir)/sifive-blocks
VSRCS := \
$(rocketchip_dir)/vsrc/AsyncResetReg.v \
$(rocketchip_dir)/vsrc/plusarg_reader.v \
$(rocketchip_dir)/src/main/resources/vsrc/AsyncResetReg.v \
$(rocketchip_dir)/src/main/resources/vsrc/plusarg_reader.v \
$(sifiveblocks_dir)/vsrc/SRLatch.v \
$(FPGA_DIR)/common/vsrc/PowerOnResetFPGAOnly.v \
$(FPGA_DIR)/$(BOARD)/vsrc/sdio.v \
@@ -47,7 +47,7 @@ class U500PolarFireEvalKitConfig extends Config(
case MemoryMicrosemiDDR3Key => PolarFireEvalKitDDR3Params(address = Seq(AddressSet(0x80000000L,0x40000000L-1))) //1GB
// case MemoryMicrosemiDDR4Key => PolarFireEvalKitDDR4Params(address = Seq(AddressSet(0x80000000L,0x40000000L-1))) //1GB
case DTSTimebase => BigInt(1000000)
case ExtMem => up(ExtMem).copy(size = 0x40000000L)
case ExtMem => up(ExtMem).map(_.copy(size = 0x40000000L))
case JtagDTMKey => new JtagDTMConfig (
idcodeVersion = 2, // 1 was legacy (FE310-G000, Acai).
idcodePartNum = 0x000, // Decided to simplify.
@@ -44,7 +44,7 @@ class U500VC707DevKitConfig extends Config(
case PeripheryBusKey => up(PeripheryBusKey, site).copy(frequency = 50000000) // 50 MHz hperiphery
case MemoryXilinxDDRKey => XilinxVC707MIGParams(address = Seq(AddressSet(0x80000000L,0x40000000L-1))) //1GB
case DTSTimebase => BigInt(1000000)
case ExtMem => up(ExtMem).copy(size = 0x40000000L)
case ExtMem => up(ExtMem).map(_.copy(size = 0x40000000L))
case JtagDTMKey => new JtagDTMConfig (
idcodeVersion = 2, // 1 was legacy (FE310-G000, Acai).
idcodePartNum = 0x000, // Decided to simplify.
@@ -44,7 +44,7 @@ class U500VCU118DevKitConfig extends Config(
case PeripheryBusKey => up(PeripheryBusKey, site).copy(frequency = 50000000) // 50 MHz hperiphery
case MemoryXilinxDDRKey => XilinxVCU118MIGParams(address = Seq(AddressSet(0x80000000L,0x80000000L-1))) //2GB
case DTSTimebase => BigInt(1000000)
case ExtMem => up(ExtMem).copy(size = 0x80000000L)
case ExtMem => up(ExtMem).map(_.copy(size = 0x80000000L))
case JtagDTMKey => new JtagDTMConfig (
idcodeVersion = 2, // 1 was legacy (FE310-G000, Acai).
idcodePartNum = 0x000, // Decided to simplify.
@@ -46,7 +46,7 @@ class U500VeraConfig extends Config(
case MemoryMicrosemiDDR3Key => PolarFireEvalKitDDR3Params(address = Seq(AddressSet(0x80000000L,0x40000000L-1))) //1GB
// case MemoryMicrosemiDDR4Key => PolarFireEvalKitDDR4Params(address = Seq(AddressSet(0x80000000L,0x40000000L-1))) //1GB
case DTSTimebase => BigInt(1000000)
case ExtMem => up(ExtMem).copy(size = 0x40000000L)
case ExtMem => up(ExtMem).map(_.copy(size = 0x40000000L))
case JtagDTMKey => new JtagDTMConfig (
idcodeVersion = 2, // 1 was legacy (FE310-G000, Acai).
idcodePartNum = 0x000, // Decided to simplify.

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