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Last Week in RISC-V: Friday October 12, 2018

This week's entry is fairly short, but it does come with one major improvement: we now have a mailing list! I've decided to create a Google Group at SiFive, and while I understand that's not ideal it's the best I can figure out for now. The Google Groups interface is quick clunky, so if you're looking for archives it's probably still best to use GitHub. Hopefully this makes it easier for people to find the mailing list.

I've copied this message to various RISC-V mailing lists, but won't be doing so in the future.

HiFive Unleashed SD Card Bootrom Bug

Paul recently found a bug in the HiFive Unleashed's bootrom that manifests when booting directly from the SD card. The bug manifests when the Unleashed is hot reset while the SD card is in the middle of a block transaction. We'll publish a concrete fix for the issue in our open source bootloader repo, but since there's no way to fix the mask ROM in the chip it isn't that useful in the short term. The bug also manifests in the FSBL (which is usually in SPI flash) during the standard boot flow, and assuming the bug is what we think it is the FSBL fix should be the same as the ZSBL fix.

To work around the bug you simply need to do a second hot reset -- just try to time that one such that you're not in the middle of another block transaction :)

Signaling NaNs in the RISC-V glibc Port

The biggest outstanding issue in the RISC-V glibc port is our handling of signaling NaNs. Jim has been working through the implementation of -fsignaling-nans in our GCC port in order to fix these test suite failures, which should aid the RV32I port submission as well.

GCC 8.2.0 Backports

Kito from Andes has backported a handful of GCC commits to our release branch. If you're distribution RISC-V compilers then I recommend pulling these as well.

QEMU 3.1 Soft Freeze

QEMU will have their soft freeze for the 3.1 release at the end of October. Thanks to Alistair from WD for collecting a small patch set and pushing on it so we can get it upstream. There are still a lot of patches in the queue, but it's great to have someone helping out!

Events

Contributing to "Last Week in RISC-V"

Like everything else in the RISC-V ecosystem, this won't be possible as just a one-man effort. I'm hosting the sources at github.com/sifive/last-week-in-risc-v, so if you're comfortable editing them feel free to open a pull request. If you don't want to get involved in GitHub then you're also welcome to just mail me patches or blurbs for inclusion and I can merge them together.

I don't really have any specific criteria as to what will or won't be included. Part of the reason I'm doing this is that the RISC-V ecosystem has started to get big enough that there are huge sections of it that I know nothing about, so I think the starting criteria will be "anything I'm interested enough in to want to read" and we'll just go from there!