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0010-riscv-sifive-unleashed-define-opp-table-cpufreq.patch
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0010-riscv-sifive-unleashed-define-opp-table-cpufreq.patch
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From a108460d04734c9bf897cf7deb8c463b3cb62e4b Mon Sep 17 00:00:00 2001
From: David Abdurachmanov <david.abdurachmanov@sifive.com>
Date: Fri, 14 May 2021 05:27:51 -0700
Subject: [PATCH 10/10] riscv: sifive: unleashed: define opp table (cpufreq)
Source: https://github.com/sifive/riscv-linux/commits/dev/paulw/cpufreq-dt-aloe-v5.3-rc4
Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
---
arch/riscv/Kconfig | 8 +++++
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 5 ++++
.../riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 34 ++++++++++++++++++++++
3 files changed, 47 insertions(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 18ec0f9..d088e00 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -549,6 +549,14 @@ config BUILTIN_DTB
depends on OF
default y if XIP_KERNEL
+menu "CPU Power Management"
+
+source "drivers/cpuidle/Kconfig"
+
+source "drivers/cpufreq/Kconfig"
+
+endmenu
+
menu "Power management options"
source "kernel/power/Kconfig"
diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
index 7db8610..023a8fd 100644
--- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
@@ -30,6 +30,7 @@
i-cache-size = <16384>;
reg = <0>;
riscv,isa = "rv64imac";
+ clocks = <&prci PRCI_CLK_COREPLL>;
status = "disabled";
cpu0_intc: interrupt-controller {
#interrupt-cells = <1>;
@@ -54,6 +55,7 @@
reg = <1>;
riscv,isa = "rv64imafdc";
tlb-split;
+ clocks = <&prci PRCI_CLK_COREPLL>;
next-level-cache = <&l2cache>;
cpu1_intc: interrupt-controller {
#interrupt-cells = <1>;
@@ -78,6 +80,7 @@
reg = <2>;
riscv,isa = "rv64imafdc";
tlb-split;
+ clocks = <&prci PRCI_CLK_COREPLL>;
next-level-cache = <&l2cache>;
cpu2_intc: interrupt-controller {
#interrupt-cells = <1>;
@@ -102,6 +105,7 @@
reg = <3>;
riscv,isa = "rv64imafdc";
tlb-split;
+ clocks = <&prci PRCI_CLK_COREPLL>;
next-level-cache = <&l2cache>;
cpu3_intc: interrupt-controller {
#interrupt-cells = <1>;
@@ -126,6 +130,7 @@
reg = <4>;
riscv,isa = "rv64imafdc";
tlb-split;
+ clocks = <&prci PRCI_CLK_COREPLL>;
next-level-cache = <&l2cache>;
cpu4_intc: interrupt-controller {
#interrupt-cells = <1>;
diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
index a99aded..b1e7f85 100644
--- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
+++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
@@ -78,6 +78,40 @@
compatible = "gpio-restart";
gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
};
+
+ fu540_c000_opp_table: opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-350000000 {
+ opp-hz = /bits/ 64 <350000000>;
+ };
+ opp-700000000 {
+ opp-hz = /bits/ 64 <700000000>;
+ };
+ opp-999999999 {
+ opp-hz = /bits/ 64 <999999999>;
+ };
+ opp-1400000000 {
+ opp-hz = /bits/ 64 <1400000000>;
+ };
+ };
+};
+
+&cpu0 {
+ operating-points-v2 = <&fu540_c000_opp_table>;
+};
+&cpu1 {
+ operating-points-v2 = <&fu540_c000_opp_table>;
+};
+&cpu2 {
+ operating-points-v2 = <&fu540_c000_opp_table>;
+};
+&cpu3 {
+ operating-points-v2 = <&fu540_c000_opp_table>;
+};
+&cpu4 {
+ operating-points-v2 = <&fu540_c000_opp_table>;
};
&uart0 {
--
2.7.4