Join GitHub today
GitHub is home to over 36 million developers working together to host and review code, manage projects, and build software together.Sign up
uart: Add a "txdone" register, set compat to "sifive,uart1" #90
The UART is a pretty small device, so its clock tends to be coupled to
Even in the fastest modes, UART word transmission happens at about 10KHz
My fix is to plumb out the busy bit from the TX module to a register
The semantics of the bit are intended to allow software to ensure that
As usual, I've given this patch absolutely no testing: in this case I
paul-walmsley-sifive left a comment
First: great commit message.
Second: the idea behind the change looks good, and we should definitely merge this fix or one like it once the hardware folks are happy with it. But we should also pursue a fix on the SoC clock integration side. A better overall approach to solve the specific problem of rate changes on the UART source clock is simply not to change the UART source clock at all (or SPI, I2C, I2S, etc.). Otherwise the UART receive side is either non-functional or might receive garbage during the PLL change, and that's not acceptable for many customer use-cases.
There are two usual ways that other SoCs have dealt with this:
Ideally both options would be available via a clock mux.
@paul-walmsley-sifive this code already supports the ability to run the UART off a constant/more dedicated clock source. Agree that is the right way to clock the UART but I think this feature is still useful, even if you never wanted to change the clock it would be nice to know when the transmission is complete.
@mwachs5 Yep, just to clarify, I think the idea behind this patch is great, and endorse it. I personally can't comment on the specific implementation since I'm not familiar enough with Chisel yet. So yeah, I'm in favor of it, no matter what happens to the SoC integration.
Regarding the integration: initial thought here was to separate the UART TX/RX logic from the UART register target, and synchronize between the two Sounds like you were thinking of placing the CDC between the interconnect and the entire UART IP. Any opinions on pros/cons of those two approaches? Would naively assume that the former case would be more efficient from the CPU and interconnect perspective, although it seems more complex to implement in Chisel.