From 401942085875932c95d673a5ad9834738b08ef45 Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Mon, 15 Sep 2025 13:43:21 -0400 Subject: [PATCH 1/2] update names to match renaming on SC --- examples/chip/chip.py | 4 ++-- lambdalib/__init__.py | 6 +++--- lambdalib/auxlib/__init__.py | 4 ++-- lambdalib/fpgalib/__init__.py | 4 ++-- lambdalib/iolib/__init__.py | 4 ++-- lambdalib/lambdalib.py | 4 ++-- lambdalib/ramlib/__init__.py | 4 ++-- lambdalib/stdlib/__init__.py | 4 ++-- lambdalib/veclib/__init__.py | 4 ++-- 9 files changed, 19 insertions(+), 19 deletions(-) diff --git a/examples/chip/chip.py b/examples/chip/chip.py index c66d7cc9..969db9d3 100644 --- a/examples/chip/chip.py +++ b/examples/chip/chip.py @@ -1,11 +1,11 @@ import subprocess -from siliconcompiler import DesignSchema +from siliconcompiler import Design from lambdalib.padring import Padring -class Chip(DesignSchema): +class Chip(Design): def __init__(self): name = 'chip' diff --git a/lambdalib/__init__.py b/lambdalib/__init__.py index 37a719b2..77920d44 100644 --- a/lambdalib/__init__.py +++ b/lambdalib/__init__.py @@ -1,4 +1,4 @@ -from siliconcompiler import DesignSchema, ASICProject +from siliconcompiler import Design, ASICProject # individual modules from lambdalib import auxlib @@ -12,8 +12,8 @@ __version__ = "0.4.0-rc1" -class LambalibTechLibrary(DesignSchema): - """A DesignSchema class to manage a lambda library and its associated technology libraries. +class LambalibTechLibrary(Design): + """A Design class to manage a lambda library and its associated technology libraries. This class encapsulates a main lambda library cell and a list of technology libraries, providing a mechanism to alias them within an ASIC project. diff --git a/lambdalib/auxlib/__init__.py b/lambdalib/auxlib/__init__.py index 79549ece..7be62bab 100644 --- a/lambdalib/auxlib/__init__.py +++ b/lambdalib/auxlib/__init__.py @@ -1,4 +1,4 @@ -from siliconcompiler import DesignSchema +from siliconcompiler import Design from .la_drsync.la_drsync import Drsync from .la_dsync.la_dsync import Dsync @@ -47,7 +47,7 @@ 'Tbuf'] -class AUXLib(DesignSchema): +class AUXLib(Design): def __init__(self): super().__init__("la_auxlib") diff --git a/lambdalib/fpgalib/__init__.py b/lambdalib/fpgalib/__init__.py index f111a173..e929b9aa 100644 --- a/lambdalib/fpgalib/__init__.py +++ b/lambdalib/fpgalib/__init__.py @@ -1,4 +1,4 @@ -from siliconcompiler import DesignSchema +from siliconcompiler import Design from .la_lut4.la_lut4 import Lut4 from .la_ble4p0.la_ble4p0 import Ble4p0 @@ -9,7 +9,7 @@ 'Lut4'] -class FPGALib(DesignSchema): +class FPGALib(Design): def __init__(self): super().__init__("la_fpgalib") diff --git a/lambdalib/iolib/__init__.py b/lambdalib/iolib/__init__.py index 73552b69..ef6c1714 100644 --- a/lambdalib/iolib/__init__.py +++ b/lambdalib/iolib/__init__.py @@ -1,4 +1,4 @@ -from siliconcompiler import DesignSchema +from siliconcompiler import Design from .la_ioanalog.la_ioanalog import Ioanalog from .la_iobidir.la_iobidir import Iobidir @@ -35,7 +35,7 @@ 'Ioxtal'] -class IOLib(DesignSchema): +class IOLib(Design): def __init__(self): super().__init__("la_iolib") diff --git a/lambdalib/lambdalib.py b/lambdalib/lambdalib.py index 5c85e98d..6759a7f5 100644 --- a/lambdalib/lambdalib.py +++ b/lambdalib/lambdalib.py @@ -1,9 +1,9 @@ from pathlib import Path from typing import Union, List -from siliconcompiler import DesignSchema +from siliconcompiler import Design -class Lambda(DesignSchema): +class Lambda(Design): def __init__(self, name: str, path: Union[str, Path], diff --git a/lambdalib/ramlib/__init__.py b/lambdalib/ramlib/__init__.py index 8498b3a2..8e27decf 100644 --- a/lambdalib/ramlib/__init__.py +++ b/lambdalib/ramlib/__init__.py @@ -1,4 +1,4 @@ -from siliconcompiler import DesignSchema +from siliconcompiler import Design from .la_asyncfifo.la_asyncfifo import Asyncfifo from .la_syncfifo.la_syncfifo import Syncfifo @@ -11,7 +11,7 @@ 'Spram'] -class RAMLib(DesignSchema): +class RAMLib(Design): def __init__(self): super().__init__("la_ramlib") diff --git a/lambdalib/stdlib/__init__.py b/lambdalib/stdlib/__init__.py index e882a902..ddec589d 100644 --- a/lambdalib/stdlib/__init__.py +++ b/lambdalib/stdlib/__init__.py @@ -1,4 +1,4 @@ -from siliconcompiler import DesignSchema +from siliconcompiler import Design from .la_and2.la_and2 import And2 from .la_and3.la_and3 import And3 @@ -195,7 +195,7 @@ 'Xor4'] -class STDLib(DesignSchema): +class STDLib(Design): def __init__(self): super().__init__("la_stdlib") diff --git a/lambdalib/veclib/__init__.py b/lambdalib/veclib/__init__.py index 2e9ecb80..1cf129a4 100644 --- a/lambdalib/veclib/__init__.py +++ b/lambdalib/veclib/__init__.py @@ -1,4 +1,4 @@ -from siliconcompiler import DesignSchema +from siliconcompiler import Design from .la_vbuf.la_vbuf import Vbuf from .la_vinv.la_vinv import Vinv @@ -25,7 +25,7 @@ 'Vmux8'] -class STDLib(DesignSchema): +class STDLib(Design): def __init__(self): super().__init__("la_veclib") From 0382a5c965e59d12ab332ac7e7110057396ed4be Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Mon, 15 Sep 2025 13:44:18 -0400 Subject: [PATCH 2/2] update to RC2 --- lambdalib/__init__.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lambdalib/__init__.py b/lambdalib/__init__.py index 77920d44..6e0a6eda 100644 --- a/lambdalib/__init__.py +++ b/lambdalib/__init__.py @@ -9,7 +9,7 @@ from lambdalib import ramlib from lambdalib import veclib -__version__ = "0.4.0-rc1" +__version__ = "0.4.0-rc2" class LambalibTechLibrary(Design):