From 90334f4bb86695af6b6efc5f4ef114d68ede9694 Mon Sep 17 00:00:00 2001
From: Peter Gadfort <gadfort@zeroasic.com>
Date: Fri, 19 Apr 2024 14:30:08 -0400
Subject: [PATCH] update lambdalib files

---
 .../asap7/libs/fakeram7/lambda/la_asyncfifo.v | 336 +++++++++---------
 .../asap7/libs/fakeram7/lambda/la_dpram.v     |  70 ++--
 .../asap7/libs/fakeram7/lambda/la_spram.v     | 104 +++---
 .../asap7/libs/fakeram7/lambda/la_spregfile.v |  84 +++--
 .../asap7/libs/fakeram7/lambda/la_syncfifo.v  | 224 ++++++------
 .../libs/fakeram45/lambda/la_asyncfifo.v      | 336 +++++++++---------
 .../libs/fakeram45/lambda/la_dpram.v          |  70 ++--
 .../libs/fakeram45/lambda/la_spram.v          | 104 +++---
 .../libs/fakeram45/lambda/la_spregfile.v      |  84 +++--
 .../libs/fakeram45/lambda/la_syncfifo.v       | 224 ++++++------
 .../libs/gf180mcu_fd_io/lambda/la_ioclamp.v   |  26 +-
 .../libs/gf180mcu_fd_io/lambda/la_ioinput.v   |  40 +--
 .../libs/gf180mcu_fd_io/lambda/la_ioshort.v   |  30 +-
 .../libs/gf180mcu_fd_io/lambda/la_iovdda.v    |  26 +-
 .../libs/gf180mcu_fd_io/lambda/la_iovssa.v    |  26 +-
 .../libs/gf180mcu_fd_io/lambda/la_ioxtal.v    |  36 +-
 .../gf180/libs/gf180mcu_fd_io/lambda/la_pt.v  |  13 +-
 .../gf180mcu_fd_ip_sram/lambda/la_asyncfifo.v | 336 +++++++++---------
 .../gf180mcu_fd_ip_sram/lambda/la_dpram.v     |  70 ++--
 .../gf180mcu_fd_ip_sram/lambda/la_spram.v     |  88 ++---
 .../gf180mcu_fd_ip_sram/lambda/la_spregfile.v |  84 +++--
 .../gf180mcu_fd_ip_sram/lambda/la_syncfifo.v  | 224 ++++++------
 .../sky130/libs/sky130io/lambda/la_ioanalog.v |  44 ++-
 .../sky130/libs/sky130io/lambda/la_ioclamp.v  |  26 +-
 .../sky130/libs/sky130io/lambda/la_ioinput.v  |  40 +--
 .../sky130/libs/sky130io/lambda/la_ioshort.v  |  30 +-
 .../sky130/libs/sky130io/lambda/la_iovdda.v   |  26 +-
 .../sky130/libs/sky130io/lambda/la_iovssa.v   |  26 +-
 .../sky130/libs/sky130io/lambda/la_ioxtal.v   |  36 +-
 lambdapdk/sky130/libs/sky130io/lambda/la_pt.v |  13 +-
 .../libs/sky130sram/lambda/la_asyncfifo.v     | 336 +++++++++---------
 .../sky130/libs/sky130sram/lambda/la_dpram.v  |  70 ++--
 .../sky130/libs/sky130sram/lambda/la_spram.v  |  83 ++---
 .../libs/sky130sram/lambda/la_spregfile.v     |  84 +++--
 .../libs/sky130sram/lambda/la_syncfifo.v      | 224 ++++++------
 35 files changed, 1769 insertions(+), 1904 deletions(-)

diff --git a/lambdapdk/asap7/libs/fakeram7/lambda/la_asyncfifo.v b/lambdapdk/asap7/libs/fakeram7/lambda/la_asyncfifo.v
index e865f73c..3d37a974 100644
--- a/lambdapdk/asap7/libs/fakeram7/lambda/la_asyncfifo.v
+++ b/lambdapdk/asap7/libs/fakeram7/lambda/la_asyncfifo.v
@@ -1,6 +1,6 @@
 /*****************************************************************************
  * Function: Dual Clock Asynchronous FIFO
- * Copyright: Lambda Project Authors. ALl rights Reserved.
+ * Copyright: Lambda Project Authors. All rights Reserved.
  * License:  MIT (see LICENSE file in Lambda repository)
  *
  * Docs:
@@ -20,192 +20,176 @@
  *
  ****************************************************************************/
 
-module la_asyncfifo
-  #(parameter DW        = 32,       // Memory width
-    parameter DEPTH     = 4,        // FIFO depth
-    parameter NS        = 1,        // Number of power supplies
-    parameter CTRLW     = 1,        // width of asic ctrl interface
-    parameter TESTW     = 1,        // width of asic teset interface
-    parameter CHAOS     = 0,        // generates random full logic when set
-    parameter TYPE      = "DEFAULT" // Pass through variable for hard macro
-    )
-   (// write port
-    input             wr_clk,
-    input             wr_nreset,
-    input [DW-1:0]    wr_din, // data to write
-    input             wr_en, // write fifo
-    input             wr_chaosmode,// randomly assert fifo full when set
-    output reg        wr_full, // fifo full
+module la_asyncfifo #(
+    parameter DW    = 32,        // Memory width
+    parameter DEPTH = 4,         // FIFO depth
+    parameter NS    = 1,         // Number of power supplies
+    parameter CTRLW = 1,         // width of asic ctrl interface
+    parameter TESTW = 1,         // width of asic teset interface
+    parameter CHAOS = 0,         // generates random full logic when set
+    parameter TYPE  = "DEFAULT"  // Pass through variable for hard macro
+) (  // write port
+    input                  wr_clk,
+    input                  wr_nreset,
+    input      [   DW-1:0] wr_din,        // data to write
+    input                  wr_en,         // write fifo
+    input                  wr_chaosmode,  // randomly assert fifo full when set
+    output reg             wr_full,       // fifo full
     // read port
-    input             rd_clk,
-    input             rd_nreset,
-    output [DW-1:0]   rd_dout, // output data (next cycle)
-    input             rd_en, // read fifo
-    output reg        rd_empty, // fifo is empty
+    input                  rd_clk,
+    input                  rd_nreset,
+    output     [   DW-1:0] rd_dout,       // output data (next cycle)
+    input                  rd_en,         // read fifo
+    output reg             rd_empty,      // fifo is empty
     // Power signals
-    input             vss, // ground signal
-    input [NS-1:0]    vdd, // supplies
+    input                  vss,           // ground signal
+    input      [   NS-1:0] vdd,           // supplies
     // Generic interfaces
-    input [CTRLW-1:0] ctrl, // pass through ASIC control interface
-    input [TESTW-1:0] test // pass through ASIC test interface
-    );
-
-   // local params
-   // The last part is to support DEPTH of 1
-   localparam AW  = $clog2(DEPTH) + {31'h0,(DEPTH == 1)};
-
-   // local wires
-   reg [AW:0]     wr_grayptr;
-   reg [AW:0]     wr_binptr;
-   reg [AW:0]     wr_binptr_mem;
-   wire [AW:0]    wr_grayptr_nxt;
-   wire [AW:0]    wr_binptr_nxt;
-   wire [AW:0]    wr_binptr_mem_nxt;
-   wire [AW:0]    wr_grayptr_sync;
-   wire           wr_chaosfull;
-
-   reg [AW:0]     rd_grayptr;
-   reg [AW:0]     rd_binptr;
-   reg [AW:0]     rd_binptr_mem;
-   wire [AW:0]    rd_grayptr_nxt;
-   wire [AW:0]    rd_binptr_nxt;
-   wire [AW:0]    rd_binptr_mem_nxt;
-   wire [AW:0]    rd_grayptr_sync;
-
-   genvar         i;
-
-   //###########################
-   //# WRITE SIDE LOGIC
-   //###########################
-
-   always @ ( posedge wr_clk or negedge wr_nreset)
-     if(~wr_nreset)
-       begin
-          wr_binptr_mem[AW:0] <= 'b0;
-          wr_binptr[AW:0]     <= 'b0;
-          wr_grayptr[AW:0]    <= 'b0;
-       end
-     else
-       begin
-          wr_binptr_mem[AW:0] <= (wr_binptr_mem_nxt[AW:0] == DEPTH) ? 'b0 : wr_binptr_mem_nxt[AW:0];
-          wr_binptr[AW:0]     <= wr_binptr_nxt[AW:0];
-          wr_grayptr[AW:0]    <= wr_grayptr_nxt[AW:0];
-       end
-
-   // Update binary pointer on write and not full
-   assign wr_binptr_mem_nxt[AW:0] = wr_binptr_mem[AW-1:0] + {{(AW-1){1'b0}}, (wr_en && ~wr_full)};
-   assign wr_binptr_nxt[AW:0]     = wr_binptr[AW:0] + {{AW{1'b0}}, (wr_en && ~wr_full)};
-
-   // Convert binary point to gray pointer for sync
-   assign wr_grayptr_nxt[AW:0] =  wr_binptr_nxt[AW:0] ^ {1'b0, wr_binptr_nxt[AW:1]};
-
-   // Full comparison (gray pointer based)
-   // Amir - add support for fifo DEPTH that is not power of 2
-   // Note - the previous logic also had a bug that full was high one entry to soon
-
-   reg [AW:0] rd_binptr_sync;
-   wire [AW:0] fifo_used;
-   integer j;
-
-   always @(*)
-     begin
+    input      [CTRLW-1:0] ctrl,          // pass through ASIC control interface
+    input      [TESTW-1:0] test           // pass through ASIC test interface
+);
+
+    // local params
+    // The last part is to support DEPTH of 1
+    localparam AW = $clog2(DEPTH) + {31'h0, (DEPTH == 1)};
+
+    // local wires
+    reg  [AW:0] wr_grayptr;
+    reg  [AW:0] wr_binptr;
+    reg  [AW:0] wr_binptr_mem;
+    wire [AW:0] wr_grayptr_nxt;
+    wire [AW:0] wr_binptr_nxt;
+    wire [AW:0] wr_binptr_mem_nxt;
+    wire [AW:0] wr_grayptr_sync;
+    wire        wr_chaosfull;
+
+    reg  [AW:0] rd_grayptr;
+    reg  [AW:0] rd_binptr;
+    reg  [AW:0] rd_binptr_mem;
+    wire [AW:0] rd_grayptr_nxt;
+    wire [AW:0] rd_binptr_nxt;
+    wire [AW:0] rd_binptr_mem_nxt;
+    wire [AW:0] rd_grayptr_sync;
+
+    genvar i;
+
+    //###########################
+    //# WRITE SIDE LOGIC
+    //###########################
+
+    always @(posedge wr_clk or negedge wr_nreset)
+        if (~wr_nreset) begin
+            wr_binptr_mem[AW:0] <= 'b0;
+            wr_binptr[AW:0]     <= 'b0;
+            wr_grayptr[AW:0]    <= 'b0;
+        end else begin
+            wr_binptr_mem[AW:0] <= (wr_binptr_mem_nxt[AW:0] == DEPTH) ? 'b0 : wr_binptr_mem_nxt[AW:0];
+            wr_binptr[AW:0] <= wr_binptr_nxt[AW:0];
+            wr_grayptr[AW:0] <= wr_grayptr_nxt[AW:0];
+        end
+
+    // Update binary pointer on write and not full
+    assign wr_binptr_mem_nxt[AW:0] = wr_binptr_mem[AW-1:0] + {{(AW-1){1'b0}}, (wr_en && ~wr_full)};
+    assign wr_binptr_nxt[AW:0] = wr_binptr[AW:0] + {{AW{1'b0}}, (wr_en && ~wr_full)};
+
+    // Convert binary point to gray pointer for sync
+    assign wr_grayptr_nxt[AW:0] = wr_binptr_nxt[AW:0] ^ {1'b0, wr_binptr_nxt[AW:1]};
+
+    // Full comparison (gray pointer based)
+    // Amir - add support for fifo DEPTH that is not power of 2
+    // Note - the previous logic also had a bug that full was high one entry to soon
+
+    reg [AW:0] rd_binptr_sync;
+    wire [AW:0] fifo_used;
+    integer j;
+
+    always @(*) begin
         rd_binptr_sync[AW] = rd_grayptr_sync[AW];
-        for (j=AW;j>0;j=j-1)
-          rd_binptr_sync[j-1] = rd_binptr_sync[j] ^ rd_grayptr_sync[j-1];
-     end
+        for (j = AW; j > 0; j = j - 1)
+        rd_binptr_sync[j-1] = rd_binptr_sync[j] ^ rd_grayptr_sync[j-1];
+    end
 
-   assign fifo_used = wr_binptr - rd_binptr_sync;
+    assign fifo_used = wr_binptr - rd_binptr_sync;
 
-   always @ (posedge wr_clk or negedge wr_nreset)
-     if (~wr_nreset)
-       wr_full <= 1'b0;
-     else
-       wr_full <= (wr_chaosfull & wr_chaosmode) |
+    always @(posedge wr_clk or negedge wr_nreset)
+        if (~wr_nreset) wr_full <= 1'b0;
+        else
+            wr_full <= (wr_chaosfull & wr_chaosmode) |
                   (fifo_used + {{AW{1'b0}}, (wr_en && ~wr_full)}) == DEPTH;
 
-   // Write --> Read clock synchronizer
-   for (i=0;i<(AW+1);i=i+1)
-     begin
-        la_drsync wrsync(.out(wr_grayptr_sync[i]),
-                         .clk(rd_clk),
-                         .nreset(rd_nreset),
-                         .in(wr_grayptr[i]));
-     end
-
-   //###########################
-   //# READ SIDE LOGIC
-   //###########################
-
-   always @ ( posedge rd_clk or negedge rd_nreset)
-     if(~rd_nreset)
-       begin
-          rd_binptr_mem[AW:0] <= 'b0;
-          rd_binptr[AW:0]     <= 'b0;
-          rd_grayptr[AW:0]    <= 'b0;
-       end
-     else
-       begin
-          rd_binptr_mem[AW:0] <= (rd_binptr_mem_nxt[AW:0] == DEPTH) ? 'b0 : rd_binptr_mem_nxt[AW:0];
-          rd_binptr[AW:0]  <= rd_binptr_nxt[AW:0];
-          rd_grayptr[AW:0] <= rd_grayptr_nxt[AW:0];
-       end
-
-   assign rd_binptr_mem_nxt[AW:0] = rd_binptr_mem[AW-1:0] + {{(AW-1){1'b0}}, (rd_en && ~rd_empty)};
-   assign rd_binptr_nxt[AW:0]     = rd_binptr[AW:0] + {{AW{1'b0}}, (rd_en && ~rd_empty)};
-   assign rd_grayptr_nxt[AW:0]    = rd_binptr_nxt[AW:0] ^ {1'b0, rd_binptr_nxt[AW:1]};
-
-   // Full comparison (gray pointer based)
-   always @ (posedge rd_clk or negedge rd_nreset)
-     if (~rd_nreset)
-       rd_empty <= 1'b1;
-     else
-       rd_empty <= (rd_grayptr_nxt[AW:0] == wr_grayptr_sync[AW:0]);
-
-   // Read --> write clock synchronizer
-   for (i=0;i<(AW+1);i=i+1)
-     begin
-        la_drsync rdsync(.out(rd_grayptr_sync[i]),
-                         .clk(wr_clk),
-                         .nreset(wr_nreset),
-                         .in(rd_grayptr[i]));
-     end
-
-   //###########################
-   //# Dual Port Memory
-   //###########################
-
-   reg [DW-1:0]         ram[DEPTH-1:0];
-
-   // Write port (FIFO input)
-   always @(posedge wr_clk)
-     if(wr_en & ~wr_full)
-       ram[wr_binptr_mem[AW-1:0]] <= wr_din[DW-1:0];
-
-   // Read port (FIFO output)
-   assign rd_dout[DW-1:0] = ram[rd_binptr_mem[AW-1:0]];
-
-   //############################
-   // Randomly Asserts FIFO full
-   //############################
-
-   generate
-      if (CHAOS)
-        begin
-           // TODO: implement LFSR
-           reg chaosreg;
-           always @ (posedge wr_clk or negedge wr_nreset)
-             if (~wr_nreset)
-               chaosreg <= 1'b0;
-             else
-               chaosreg <= ~chaosreg;
-           assign wr_chaosfull = chaosreg;
+    // Write --> Read clock synchronizer
+    for (i = 0; i < (AW + 1); i = i + 1) begin
+        la_drsync wrsync (
+            .out(wr_grayptr_sync[i]),
+            .clk(rd_clk),
+            .nreset(rd_nreset),
+            .in(wr_grayptr[i])
+        );
+    end
+
+    //###########################
+    //# READ SIDE LOGIC
+    //###########################
+
+    always @(posedge rd_clk or negedge rd_nreset)
+        if (~rd_nreset) begin
+            rd_binptr_mem[AW:0] <= 'b0;
+            rd_binptr[AW:0]     <= 'b0;
+            rd_grayptr[AW:0]    <= 'b0;
+        end else begin
+            rd_binptr_mem[AW:0] <= (rd_binptr_mem_nxt[AW:0] == DEPTH) ? 'b0 : rd_binptr_mem_nxt[AW:0];
+            rd_binptr[AW:0] <= rd_binptr_nxt[AW:0];
+            rd_grayptr[AW:0] <= rd_grayptr_nxt[AW:0];
         end
-      else
-        begin
-           assign wr_chaosfull = 1'b0;
+
+    assign rd_binptr_mem_nxt[AW:0] = rd_binptr_mem[AW-1:0] + {{(AW-1){1'b0}}, (rd_en && ~rd_empty)};
+    assign rd_binptr_nxt[AW:0] = rd_binptr[AW:0] + {{AW{1'b0}}, (rd_en && ~rd_empty)};
+    assign rd_grayptr_nxt[AW:0] = rd_binptr_nxt[AW:0] ^ {1'b0, rd_binptr_nxt[AW:1]};
+
+    // Full comparison (gray pointer based)
+    always @(posedge rd_clk or negedge rd_nreset)
+        if (~rd_nreset) rd_empty <= 1'b1;
+        else rd_empty <= (rd_grayptr_nxt[AW:0] == wr_grayptr_sync[AW:0]);
+
+    // Read --> write clock synchronizer
+    for (i = 0; i < (AW + 1); i = i + 1) begin
+        la_drsync rdsync (
+            .out(rd_grayptr_sync[i]),
+            .clk(wr_clk),
+            .nreset(wr_nreset),
+            .in(rd_grayptr[i])
+        );
+    end
+
+    //###########################
+    //# Dual Port Memory
+    //###########################
+
+    reg [DW-1:0] ram[DEPTH-1:0];
+
+    // Write port (FIFO input)
+    always @(posedge wr_clk) if (wr_en & ~wr_full) ram[wr_binptr_mem[AW-1:0]] <= wr_din[DW-1:0];
+
+    // Read port (FIFO output)
+    assign rd_dout[DW-1:0] = ram[rd_binptr_mem[AW-1:0]];
+
+    //############################
+    // Randomly Asserts FIFO full
+    //############################
+
+    generate
+        if (CHAOS) begin
+            // TODO: implement LFSR
+            reg chaosreg;
+            always @(posedge wr_clk or negedge wr_nreset)
+                if (~wr_nreset) chaosreg <= 1'b0;
+                else chaosreg <= ~chaosreg;
+            assign wr_chaosfull = chaosreg;
+        end else begin
+            assign wr_chaosfull = 1'b0;
         end
 
-   endgenerate
+    endgenerate
 
 
 endmodule
diff --git a/lambdapdk/asap7/libs/fakeram7/lambda/la_dpram.v b/lambdapdk/asap7/libs/fakeram7/lambda/la_dpram.v
index 8e46ebb7..129ef424 100644
--- a/lambdapdk/asap7/libs/fakeram7/lambda/la_dpram.v
+++ b/lambdapdk/asap7/libs/fakeram7/lambda/la_dpram.v
@@ -1,6 +1,6 @@
 /*****************************************************************************
  * Function: Dual Port RAM (One write port + One read port)
- * Copyright: Lambda Project Authors. ALl rights Reserved.
+ * Copyright: Lambda Project Authors. All rights Reserved.
  * License:  MIT (see LICENSE file in Lambda repository)
  *
  * Docs:
@@ -20,47 +20,43 @@
  *
  ****************************************************************************/
 
-module la_dpram
-  #(parameter DW     = 32,        // Memory width
-    parameter AW     = 10,        // address width (derived)
-    parameter TYPE   = "DEFAULT", // pass through variable for hard macro
-    parameter CTRLW  = 128,       // width of asic ctrl interface
-    parameter TESTW  = 128        // width of asic test interface
-    )
-   (// Write port
-    input 		wr_clk, // write clock
-    input 		wr_ce, // write chip-enable
-    input 		wr_we, // write enable
-    input [DW-1:0] 	wr_wmask, // write mask
-    input [AW-1:0] 	wr_addr, // write address
-    input [DW-1:0] 	wr_din, //write data in
+module la_dpram #(
+    parameter DW    = 32,         // Memory width
+    parameter AW    = 10,         // address width (derived)
+    parameter TYPE  = "DEFAULT",  // pass through variable for hard macro
+    parameter CTRLW = 128,        // width of asic ctrl interface
+    parameter TESTW = 128         // width of asic test interface
+) (  // Write port
+    input wr_clk,  // write clock
+    input wr_ce,  // write chip-enable
+    input wr_we,  // write enable
+    input [DW-1:0] wr_wmask,  // write mask
+    input [AW-1:0] wr_addr,  // write address
+    input [DW-1:0] wr_din,  //write data in
     // Read port
-    input 		rd_clk, // read clock
-    input 		rd_ce, // read chip-enable
-    input [AW-1:0] 	rd_addr, // read address
-    output reg [DW-1:0] rd_dout, //read data out
+    input rd_clk,  // read clock
+    input rd_ce,  // read chip-enable
+    input [AW-1:0] rd_addr,  // read address
+    output reg [DW-1:0] rd_dout,  //read data out
     // Power signal
-    input 		vss, // ground signal
-    input 		vdd, // memory core array power
-    input 		vddio, // periphery/io power
+    input vss,  // ground signal
+    input vdd,  // memory core array power
+    input vddio,  // periphery/io power
     // Generic interfaces
-    input [CTRLW-1:0] 	ctrl, // pass through ASIC control interface
-    input [TESTW-1:0] 	test // pass through ASIC test interface
-    );
+    input [CTRLW-1:0] ctrl,  // pass through ASIC control interface
+    input [TESTW-1:0] test  // pass through ASIC test interface
+);
 
-   // Generic RTL RAM
-   reg [DW-1:0]       ram[(2**AW)-1:0];
-   integer 	      i;
+    // Generic RTL RAM
+    reg     [DW-1:0] ram[(2**AW)-1:0];
+    integer          i;
 
-   // Write port
-   always @(posedge wr_clk)
-     for (i=0;i<DW;i=i+1)
-       if (wr_ce & wr_we & wr_wmask[i])
-         ram[wr_addr[AW-1:0]][i] <= wr_din[i];
+    // Write port
+    always @(posedge wr_clk)
+        for (i = 0; i < DW; i = i + 1)
+            if (wr_ce & wr_we & wr_wmask[i]) ram[wr_addr[AW-1:0]][i] <= wr_din[i];
 
-   // Read Port
-   always @ (posedge rd_clk)
-     if(rd_ce)
-       rd_dout[DW-1:0] <= ram[rd_addr[AW-1:0]];
+    // Read Port
+    always @(posedge rd_clk) if (rd_ce) rd_dout[DW-1:0] <= ram[rd_addr[AW-1:0]];
 
 endmodule
diff --git a/lambdapdk/asap7/libs/fakeram7/lambda/la_spram.v b/lambdapdk/asap7/libs/fakeram7/lambda/la_spram.v
index a6fb5166..65d22f29 100644
--- a/lambdapdk/asap7/libs/fakeram7/lambda/la_spram.v
+++ b/lambdapdk/asap7/libs/fakeram7/lambda/la_spram.v
@@ -1,6 +1,6 @@
 /*****************************************************************************
- * Function: Single Port RAM
- * Copyright: Lambda Project Authors. ALl rights Reserved.
+ * Function: Single Port ram
+ * Copyright: Lambda Project Authors. All rights Reserved.
  * License:  MIT (see LICENSE file in Lambda repository)
  *
  * Docs:
@@ -14,7 +14,7 @@
  * supplied on a per macro basis.
  *
  * Technologoy specific implementations of "la_spram" would generally include
- * one ore more hardcoded instantiations of RAM modules with a generate
+ * one ore more hardcoded instantiations of ram modules with a generate
  * statement relying on the "TYPE" to select between the list of modules
  * at build time.
  *
@@ -28,50 +28,52 @@ module la_spram
     parameter TESTW  = 128          // Width of asic test interface
     )
    (// Memory interface
-    input 		clk, // write clock
-    input 		ce, // chip enable
-    input 		we, // write enable
-    input [DW-1:0] 	wmask, //per bit write mask
-    input [AW-1:0] 	addr,//write address
-    input [DW-1:0] 	din, //write data
-    output [DW-1:0] dout,//read output data
+    input clk, // write clock
+    input ce, // chip enable
+    input we, // write enable
+    input [DW-1:0] wmask, //per bit write mask
+    input [AW-1:0] addr, //write address
+    input [DW-1:0] din, //write data
+    output [DW-1:0] dout, //read output data
     // Power signals
-    input 		vss, // ground signal
-    input 		vdd, // memory core array power
-    input 		vddio, // periphery/io power
+    input vss, // ground signal
+    input vdd, // memory core array power
+    input vddio, // periphery/io power
     // Generic interfaces
-    input [CTRLW-1:0] 	ctrl, // pass through ASIC control interface
-    input [TESTW-1:0] 	test // pass through ASIC test interface
+    input [CTRLW-1:0] ctrl, // pass through ASIC control interface
+    input [TESTW-1:0] test // pass through ASIC test interface
     );
 
     // Determine which memory to select
-    localparam MEM_TYPE = 
+    localparam MEM_TYPE = (TYPE != "DEFAULT") ? TYPE :
       (AW >= 9) ? (DW >= 64) ? "fakeram7_512x64" : "fakeram7_512x32" :
       (AW == 8) ? (DW >= 64) ? "fakeram7_256x64" : "fakeram7_256x32" :
       (AW == 7) ? "fakeram7_128x32" :
       "fakeram7_64x32";
 
     localparam MEM_WIDTH = 
-      (MEM_TYPE == "fakeram7_512x64") ? 64 :
-      (MEM_TYPE == "fakeram7_512x32") ? 32 :
-      (MEM_TYPE == "fakeram7_256x64") ? 64 :
-      (MEM_TYPE == "fakeram7_256x32") ? 32 :
       (MEM_TYPE == "fakeram7_128x32") ? 32 :
+      (MEM_TYPE == "fakeram7_256x32") ? 32 :
+      (MEM_TYPE == "fakeram7_256x64") ? 64 :
+      (MEM_TYPE == "fakeram7_512x32") ? 32 :
+      (MEM_TYPE == "fakeram7_512x64") ? 64 :
       (MEM_TYPE == "fakeram7_64x32") ? 32 :
       0;
  
     localparam MEM_DEPTH = 
-      (MEM_TYPE == "fakeram7_512x64") ? 9 :
-      (MEM_TYPE == "fakeram7_512x32") ? 9 :
-      (MEM_TYPE == "fakeram7_256x64") ? 8 :
-      (MEM_TYPE == "fakeram7_256x32") ? 8 :
       (MEM_TYPE == "fakeram7_128x32") ? 7 :
+      (MEM_TYPE == "fakeram7_256x32") ? 8 :
+      (MEM_TYPE == "fakeram7_256x64") ? 8 :
+      (MEM_TYPE == "fakeram7_512x32") ? 9 :
+      (MEM_TYPE == "fakeram7_512x64") ? 9 :
       (MEM_TYPE == "fakeram7_64x32") ? 6 :
       0;
 
     // Create memories
     localparam MEM_ADDRS = 2**(AW - MEM_DEPTH) < 1 ? 1 : 2**(AW - MEM_DEPTH);
 
+    
+
     generate
       genvar o;
       for (o = 0; o < DW; o = o + 1) begin: OUTPUTS
@@ -115,62 +117,68 @@ module la_spram
           wire we_in;
           assign ce_in = ce && selected;
           assign we_in = we && selected;
-
-          if (MEM_TYPE == "fakeram7_512x64")
-            fakeram7_512x64 memory (
-              .clk(clk),
+          
+          if (MEM_TYPE == "fakeram7_512x32")
+            fakeram7_512x32 memory (
               .addr_in(mem_addr),
               .ce_in(ce_in),
+              .clk(clk),
               .rd_out(mem_dout),
-              .we_in(we_in),
               .w_mask_in(mem_wmask),
-              .wd_in(mem_din));
-          else if (MEM_TYPE == "fakeram7_512x32")
-            fakeram7_512x32 memory (
-              .clk(clk),
+              .wd_in(mem_din),
+              .we_in(we_in)
+            );
+          else if (MEM_TYPE == "fakeram7_512x64")
+            fakeram7_512x64 memory (
               .addr_in(mem_addr),
               .ce_in(ce_in),
+              .clk(clk),
               .rd_out(mem_dout),
-              .we_in(we_in),
               .w_mask_in(mem_wmask),
-              .wd_in(mem_din));
+              .wd_in(mem_din),
+              .we_in(we_in)
+            );
           else if (MEM_TYPE == "fakeram7_256x64")
             fakeram7_256x64 memory (
-              .clk(clk),
               .addr_in(mem_addr),
               .ce_in(ce_in),
+              .clk(clk),
               .rd_out(mem_dout),
-              .we_in(we_in),
               .w_mask_in(mem_wmask),
-              .wd_in(mem_din));
+              .wd_in(mem_din),
+              .we_in(we_in)
+            );
           else if (MEM_TYPE == "fakeram7_256x32")
             fakeram7_256x32 memory (
-              .clk(clk),
               .addr_in(mem_addr),
               .ce_in(ce_in),
+              .clk(clk),
               .rd_out(mem_dout),
-              .we_in(we_in),
               .w_mask_in(mem_wmask),
-              .wd_in(mem_din));
+              .wd_in(mem_din),
+              .we_in(we_in)
+            );
           else if (MEM_TYPE == "fakeram7_128x32")
             fakeram7_128x32 memory (
-              .clk(clk),
               .addr_in(mem_addr),
               .ce_in(ce_in),
+              .clk(clk),
               .rd_out(mem_dout),
-              .we_in(we_in),
               .w_mask_in(mem_wmask),
-              .wd_in(mem_din));
+              .wd_in(mem_din),
+              .we_in(we_in)
+            );
           else if (MEM_TYPE == "fakeram7_64x32")
             fakeram7_64x32 memory (
-              .clk(clk),
               .addr_in(mem_addr),
               .ce_in(ce_in),
+              .clk(clk),
               .rd_out(mem_dout),
-              .we_in(we_in),
               .w_mask_in(mem_wmask),
-              .wd_in(mem_din));
+              .wd_in(mem_din),
+              .we_in(we_in)
+            );
         end
       end
     endgenerate
-endmodule
+endmodule
\ No newline at end of file
diff --git a/lambdapdk/asap7/libs/fakeram7/lambda/la_spregfile.v b/lambdapdk/asap7/libs/fakeram7/lambda/la_spregfile.v
index a06a09db..d167168c 100644
--- a/lambdapdk/asap7/libs/fakeram7/lambda/la_spregfile.v
+++ b/lambdapdk/asap7/libs/fakeram7/lambda/la_spregfile.v
@@ -1,6 +1,6 @@
 /*****************************************************************************
  * Function: Single Port Register File
- * Copyright: Lambda Project Authors. ALl rights Reserved.
+ * Copyright: Lambda Project Authors. All rights Reserved.
  * License:  MIT (see LICENSE file in Lambda repository)
  *
  * Docs:
@@ -20,50 +20,48 @@
  *
  ****************************************************************************/
 
-module la_spregfile
-  #(parameter DW     = 32,          // Memory width
-    parameter AW     = 10,          // Address width (derived)
-    parameter TYPE   = "DEFAULT",   // Pass through variable for hard macro
-    parameter CTRLW  = 128,         // Width of asic ctrl interface
-    parameter TESTW  = 128          // Width of asic test interface
-    )
-   (// Memory interface
-    input 		clk, // write clock
-    input 		ce, // chip enable
-    input 		we, // write enable
-    input [DW-1:0] 	wmask, //per bit write mask
-    input [AW-1:0] 	addr,//write address
-    input [DW-1:0] 	din, //write data
-    output [DW-1:0]     dout,//read output data
+module la_spregfile #(
+    parameter DW    = 32,         // Memory width
+    parameter AW    = 10,         // Address width (derived)
+    parameter TYPE  = "DEFAULT",  // Pass through variable for hard macro
+    parameter CTRLW = 128,        // Width of asic ctrl interface
+    parameter TESTW = 128         // Width of asic test interface
+) (  // Memory interface
+    input              clk,    // write clock
+    input              ce,     // chip enable
+    input              we,     // write enable
+    input  [   DW-1:0] wmask,  //per bit write mask
+    input  [   AW-1:0] addr,   //write address
+    input  [   DW-1:0] din,    //write data
+    output [   DW-1:0] dout,   //read output data
     // Power signals
-    input 		vss, // ground signal
-    input 		vdd, // memory core array power
-    input 		vddio, // periphery/io power
+    input              vss,    // ground signal
+    input              vdd,    // memory core array power
+    input              vddio,  // periphery/io power
     // Generic interfaces
-    input [CTRLW-1:0] 	ctrl, // pass through ASIC control interface
-    input [TESTW-1:0] 	test // pass through ASIC test interface
-    );
+    input  [CTRLW-1:0] ctrl,   // pass through ASIC control interface
+    input  [TESTW-1:0] test    // pass through ASIC test interface
+);
 
-   la_spram
-   #(.DW(DW),
-     .AW(AW),
-     .TYPE(TYPE),
-     .CTRLW(CTRLW),
-     .TESTW(TESTW)
-     )
-   memory (
-     .clk(clk),
-     .ce(ce),
-     .we(we),
-     .wmask(wmask),
-     .addr(addr),
-     .din(din),
-     .dout(dout),
-     .vss(vss),
-     .vdd(vdd),
-     .vddio(vddio),
-     .ctrl(ctrl),
-     .test(test)
-   );
+    la_spram #(
+        .DW(DW),
+        .AW(AW),
+        .TYPE(TYPE),
+        .CTRLW(CTRLW),
+        .TESTW(TESTW)
+    ) memory (
+        .clk(clk),
+        .ce(ce),
+        .we(we),
+        .wmask(wmask),
+        .addr(addr),
+        .din(din),
+        .dout(dout),
+        .vss(vss),
+        .vdd(vdd),
+        .vddio(vddio),
+        .ctrl(ctrl),
+        .test(test)
+    );
 
 endmodule
diff --git a/lambdapdk/asap7/libs/fakeram7/lambda/la_syncfifo.v b/lambdapdk/asap7/libs/fakeram7/lambda/la_syncfifo.v
index bcb4ec2c..6355a26d 100644
--- a/lambdapdk/asap7/libs/fakeram7/lambda/la_syncfifo.v
+++ b/lambdapdk/asap7/libs/fakeram7/lambda/la_syncfifo.v
@@ -1,6 +1,6 @@
 /*****************************************************************************
  * Function: Synchronous FIFO
- * Copyright: Lambda Project Authors. ALl rights Reserved.
+ * Copyright: Lambda Project Authors. All rights Reserved.
  * License:  MIT (see LICENSE file in Lambda repository)
  *
  * Docs:
@@ -9,128 +9,112 @@
  *
  ****************************************************************************/
 
-module la_syncfifo
-  #(parameter DW        = 32,       // Memory width
-    parameter DEPTH     = 4,        // FIFO depth
-    parameter NS        = 1,        // Number of power supplies
-    parameter CHAOS     = 1,        // generates random full logic when set
-    parameter CTRLW     = 1,        // width of asic ctrl interface
-    parameter TESTW     = 1,        // width of asic test interface
-    parameter TYPE      = "DEFAULT" // Pass through variable for hard macro
-    )
-   (// common clock, reset, power, ctrl
-    input             clk,
-    input             nreset,
-    input             vss, // ground signal
-    input [NS-1:0]    vdd, // supplies
-    input             chaosmode,// randomly assert fifo full when set
-    input [CTRLW-1:0] ctrl, // pass through ASIC control interface
-    input [TESTW-1:0] test, // pass through ASIC test interface
+module la_syncfifo #(
+    parameter DW    = 32,        // Memory width
+    parameter DEPTH = 4,         // FIFO depth
+    parameter NS    = 1,         // Number of power supplies
+    parameter CHAOS = 1,         // generates random full logic when set
+    parameter CTRLW = 1,         // width of asic ctrl interface
+    parameter TESTW = 1,         // width of asic test interface
+    parameter TYPE  = "DEFAULT"  // Pass through variable for hard macro
+) (  // common clock, reset, power, ctrl
+    input              clk,
+    input              nreset,
+    input              vss,        // ground signal
+    input  [   NS-1:0] vdd,        // supplies
+    input              chaosmode,  // randomly assert fifo full when set
+    input  [CTRLW-1:0] ctrl,       // pass through ASIC control interface
+    input  [TESTW-1:0] test,       // pass through ASIC test interface
     // write input
-    input             wr_en, // write fifo
-    input [DW-1:0]    wr_din, // data to write
-    output            wr_full, // fifo full
+    input              wr_en,      // write fifo
+    input  [   DW-1:0] wr_din,     // data to write
+    output             wr_full,    // fifo full
     // read output
-    input             rd_en, // read fifo
-    output [DW-1:0]   rd_dout, // output data
-    output            rd_empty // fifo is empty
-    );
-
-   // local params
-   parameter AW  = $clog2(DEPTH);
-
-   // local wires
-   reg [AW:0]         wr_addr;
-   wire [AW:0]        wr_addr_nxt;
-   reg [AW:0]         rd_addr;
-   wire [AW:0]        rd_addr_nxt;
-   wire               fifo_read;
-   wire               fifo_write;
-   wire               chaosfull;
-   wire               rd_wrap_around;
-   wire               wr_wrap_around;
-
-   //############################
-   // FIFO Empty/Full
-   //############################
-
-   // support any fifo depth
-   assign wr_full     = (chaosfull & chaosmode) |
-                        {~wr_addr[AW], wr_addr[AW-1:0]} == rd_addr[AW:0];
-
-   assign rd_empty    = wr_addr[AW:0] == rd_addr[AW:0];
-
-   assign fifo_read   = rd_en & ~rd_empty;
-
-   assign fifo_write  = wr_en & ~wr_full;
-
-   //############################
-   // FIFO Pointers - wrap around DEPTH-1
-   //############################
-   assign rd_wrap_around       = rd_addr[AW-1:0] == (DEPTH[AW-1:0]-1'b1);
-   assign wr_wrap_around       = wr_addr[AW-1:0] == (DEPTH[AW-1:0]-1'b1);
-
-   assign rd_addr_nxt[AW]     = rd_wrap_around ? ~rd_addr[AW] : rd_addr[AW];
-   assign rd_addr_nxt[AW-1:0] = rd_wrap_around ? 'b0 : (rd_addr[AW-1:0] + 1);
-
-   assign wr_addr_nxt[AW]     = (wr_addr[AW-1:0] == (DEPTH[AW-1:0]-1'b1)) ? ~wr_addr[AW] : wr_addr[AW];
-   assign wr_addr_nxt[AW-1:0] = (wr_addr[AW-1:0] == (DEPTH[AW-1:0]-1'b1)) ? 'b0 : (wr_addr[AW-1:0] + 1);
-
-   always @ (posedge clk or negedge nreset)
-     if(~nreset)
-       begin
-          wr_addr[AW:0]    <= 'd0;
-          rd_addr[AW:0]    <= 'b0;
-       end
-     else if(fifo_write & fifo_read)
-       begin
-          wr_addr[AW:0] <= wr_addr_nxt[AW:0];
-          rd_addr[AW:0] <= rd_addr_nxt[AW:0];
-       end
-     else if(fifo_write)
-       begin
-          wr_addr[AW:0] <= wr_addr_nxt[AW:0];
-       end
-     else if(fifo_read)
-       begin
-          rd_addr[AW:0] <= rd_addr_nxt[AW:0];
-       end
-
-   //###########################
-   //# Dual Port Memory
-   //###########################
-
-   reg [DW-1:0]         ram[DEPTH-1:0];
-
-   // Write port (FIFO input)
-   always @(posedge clk)
-     if(wr_en & ~wr_full)
-       ram[wr_addr[AW-1:0]] <= wr_din[DW-1:0];
-
-   // Read port (FIFO output)
-   assign rd_dout[DW-1:0] = ram[rd_addr[AW-1:0]];
-
-
-   //############################
-   // Randomly Asserts FIFO full
-   //############################
-
-   generate
-      if (CHAOS)
-        begin
-           // TODO: implement LFSR
-           reg chaosreg;
-           always @ (posedge clk or negedge nreset)
-             if (~nreset)
-               chaosreg <= 1'b0;
-             else
-               chaosreg <= ~chaosreg;
-           assign chaosfull = chaosreg;
+    input              rd_en,      // read fifo
+    output [   DW-1:0] rd_dout,    // output data
+    output             rd_empty    // fifo is empty
+);
+
+    // local params
+    parameter AW = $clog2(DEPTH);
+
+    // local wires
+    reg  [AW:0] wr_addr;
+    wire [AW:0] wr_addr_nxt;
+    reg  [AW:0] rd_addr;
+    wire [AW:0] rd_addr_nxt;
+    wire        fifo_read;
+    wire        fifo_write;
+    wire        chaosfull;
+    wire        rd_wrap_around;
+    wire        wr_wrap_around;
+
+    //############################
+    // FIFO Empty/Full
+    //############################
+
+    // support any fifo depth
+    assign wr_full = (chaosfull & chaosmode) | {~wr_addr[AW], wr_addr[AW-1:0]} == rd_addr[AW:0];
+
+    assign rd_empty = wr_addr[AW:0] == rd_addr[AW:0];
+
+    assign fifo_read = rd_en & ~rd_empty;
+
+    assign fifo_write = wr_en & ~wr_full;
+
+    //############################
+    // FIFO Pointers - wrap around DEPTH-1
+    //############################
+    assign rd_wrap_around = rd_addr[AW-1:0] == (DEPTH[AW-1:0] - 1'b1);
+    assign wr_wrap_around = wr_addr[AW-1:0] == (DEPTH[AW-1:0] - 1'b1);
+
+    assign rd_addr_nxt[AW] = rd_wrap_around ? ~rd_addr[AW] : rd_addr[AW];
+    assign rd_addr_nxt[AW-1:0] = rd_wrap_around ? 'b0 : (rd_addr[AW-1:0] + 1);
+
+    assign wr_addr_nxt[AW]     = (wr_addr[AW-1:0] == (DEPTH[AW-1:0]-1'b1)) ? ~wr_addr[AW] : wr_addr[AW];
+    assign wr_addr_nxt[AW-1:0] = (wr_addr[AW-1:0] == (DEPTH[AW-1:0]-1'b1)) ? 'b0 : (wr_addr[AW-1:0] + 1);
+
+    always @(posedge clk or negedge nreset)
+        if (~nreset) begin
+            wr_addr[AW:0] <= 'd0;
+            rd_addr[AW:0] <= 'b0;
+        end else if (fifo_write & fifo_read) begin
+            wr_addr[AW:0] <= wr_addr_nxt[AW:0];
+            rd_addr[AW:0] <= rd_addr_nxt[AW:0];
+        end else if (fifo_write) begin
+            wr_addr[AW:0] <= wr_addr_nxt[AW:0];
+        end else if (fifo_read) begin
+            rd_addr[AW:0] <= rd_addr_nxt[AW:0];
         end
-      else
-        begin
-           assign chaosfull = 1'b0;
+
+    //###########################
+    //# Dual Port Memory
+    //###########################
+
+    reg [DW-1:0] ram[DEPTH-1:0];
+
+    // Write port (FIFO input)
+    always @(posedge clk) if (wr_en & ~wr_full) ram[wr_addr[AW-1:0]] <= wr_din[DW-1:0];
+
+    // Read port (FIFO output)
+    assign rd_dout[DW-1:0] = ram[rd_addr[AW-1:0]];
+
+
+    //############################
+    // Randomly Asserts FIFO full
+    //############################
+
+    generate
+        if (CHAOS) begin
+            // TODO: implement LFSR
+            reg chaosreg;
+            always @(posedge clk or negedge nreset)
+                if (~nreset) chaosreg <= 1'b0;
+                else chaosreg <= ~chaosreg;
+            assign chaosfull = chaosreg;
+        end else begin
+            assign chaosfull = 1'b0;
         end
-   endgenerate
+    endgenerate
 
 endmodule
diff --git a/lambdapdk/freepdk45/libs/fakeram45/lambda/la_asyncfifo.v b/lambdapdk/freepdk45/libs/fakeram45/lambda/la_asyncfifo.v
index e865f73c..3d37a974 100644
--- a/lambdapdk/freepdk45/libs/fakeram45/lambda/la_asyncfifo.v
+++ b/lambdapdk/freepdk45/libs/fakeram45/lambda/la_asyncfifo.v
@@ -1,6 +1,6 @@
 /*****************************************************************************
  * Function: Dual Clock Asynchronous FIFO
- * Copyright: Lambda Project Authors. ALl rights Reserved.
+ * Copyright: Lambda Project Authors. All rights Reserved.
  * License:  MIT (see LICENSE file in Lambda repository)
  *
  * Docs:
@@ -20,192 +20,176 @@
  *
  ****************************************************************************/
 
-module la_asyncfifo
-  #(parameter DW        = 32,       // Memory width
-    parameter DEPTH     = 4,        // FIFO depth
-    parameter NS        = 1,        // Number of power supplies
-    parameter CTRLW     = 1,        // width of asic ctrl interface
-    parameter TESTW     = 1,        // width of asic teset interface
-    parameter CHAOS     = 0,        // generates random full logic when set
-    parameter TYPE      = "DEFAULT" // Pass through variable for hard macro
-    )
-   (// write port
-    input             wr_clk,
-    input             wr_nreset,
-    input [DW-1:0]    wr_din, // data to write
-    input             wr_en, // write fifo
-    input             wr_chaosmode,// randomly assert fifo full when set
-    output reg        wr_full, // fifo full
+module la_asyncfifo #(
+    parameter DW    = 32,        // Memory width
+    parameter DEPTH = 4,         // FIFO depth
+    parameter NS    = 1,         // Number of power supplies
+    parameter CTRLW = 1,         // width of asic ctrl interface
+    parameter TESTW = 1,         // width of asic teset interface
+    parameter CHAOS = 0,         // generates random full logic when set
+    parameter TYPE  = "DEFAULT"  // Pass through variable for hard macro
+) (  // write port
+    input                  wr_clk,
+    input                  wr_nreset,
+    input      [   DW-1:0] wr_din,        // data to write
+    input                  wr_en,         // write fifo
+    input                  wr_chaosmode,  // randomly assert fifo full when set
+    output reg             wr_full,       // fifo full
     // read port
-    input             rd_clk,
-    input             rd_nreset,
-    output [DW-1:0]   rd_dout, // output data (next cycle)
-    input             rd_en, // read fifo
-    output reg        rd_empty, // fifo is empty
+    input                  rd_clk,
+    input                  rd_nreset,
+    output     [   DW-1:0] rd_dout,       // output data (next cycle)
+    input                  rd_en,         // read fifo
+    output reg             rd_empty,      // fifo is empty
     // Power signals
-    input             vss, // ground signal
-    input [NS-1:0]    vdd, // supplies
+    input                  vss,           // ground signal
+    input      [   NS-1:0] vdd,           // supplies
     // Generic interfaces
-    input [CTRLW-1:0] ctrl, // pass through ASIC control interface
-    input [TESTW-1:0] test // pass through ASIC test interface
-    );
-
-   // local params
-   // The last part is to support DEPTH of 1
-   localparam AW  = $clog2(DEPTH) + {31'h0,(DEPTH == 1)};
-
-   // local wires
-   reg [AW:0]     wr_grayptr;
-   reg [AW:0]     wr_binptr;
-   reg [AW:0]     wr_binptr_mem;
-   wire [AW:0]    wr_grayptr_nxt;
-   wire [AW:0]    wr_binptr_nxt;
-   wire [AW:0]    wr_binptr_mem_nxt;
-   wire [AW:0]    wr_grayptr_sync;
-   wire           wr_chaosfull;
-
-   reg [AW:0]     rd_grayptr;
-   reg [AW:0]     rd_binptr;
-   reg [AW:0]     rd_binptr_mem;
-   wire [AW:0]    rd_grayptr_nxt;
-   wire [AW:0]    rd_binptr_nxt;
-   wire [AW:0]    rd_binptr_mem_nxt;
-   wire [AW:0]    rd_grayptr_sync;
-
-   genvar         i;
-
-   //###########################
-   //# WRITE SIDE LOGIC
-   //###########################
-
-   always @ ( posedge wr_clk or negedge wr_nreset)
-     if(~wr_nreset)
-       begin
-          wr_binptr_mem[AW:0] <= 'b0;
-          wr_binptr[AW:0]     <= 'b0;
-          wr_grayptr[AW:0]    <= 'b0;
-       end
-     else
-       begin
-          wr_binptr_mem[AW:0] <= (wr_binptr_mem_nxt[AW:0] == DEPTH) ? 'b0 : wr_binptr_mem_nxt[AW:0];
-          wr_binptr[AW:0]     <= wr_binptr_nxt[AW:0];
-          wr_grayptr[AW:0]    <= wr_grayptr_nxt[AW:0];
-       end
-
-   // Update binary pointer on write and not full
-   assign wr_binptr_mem_nxt[AW:0] = wr_binptr_mem[AW-1:0] + {{(AW-1){1'b0}}, (wr_en && ~wr_full)};
-   assign wr_binptr_nxt[AW:0]     = wr_binptr[AW:0] + {{AW{1'b0}}, (wr_en && ~wr_full)};
-
-   // Convert binary point to gray pointer for sync
-   assign wr_grayptr_nxt[AW:0] =  wr_binptr_nxt[AW:0] ^ {1'b0, wr_binptr_nxt[AW:1]};
-
-   // Full comparison (gray pointer based)
-   // Amir - add support for fifo DEPTH that is not power of 2
-   // Note - the previous logic also had a bug that full was high one entry to soon
-
-   reg [AW:0] rd_binptr_sync;
-   wire [AW:0] fifo_used;
-   integer j;
-
-   always @(*)
-     begin
+    input      [CTRLW-1:0] ctrl,          // pass through ASIC control interface
+    input      [TESTW-1:0] test           // pass through ASIC test interface
+);
+
+    // local params
+    // The last part is to support DEPTH of 1
+    localparam AW = $clog2(DEPTH) + {31'h0, (DEPTH == 1)};
+
+    // local wires
+    reg  [AW:0] wr_grayptr;
+    reg  [AW:0] wr_binptr;
+    reg  [AW:0] wr_binptr_mem;
+    wire [AW:0] wr_grayptr_nxt;
+    wire [AW:0] wr_binptr_nxt;
+    wire [AW:0] wr_binptr_mem_nxt;
+    wire [AW:0] wr_grayptr_sync;
+    wire        wr_chaosfull;
+
+    reg  [AW:0] rd_grayptr;
+    reg  [AW:0] rd_binptr;
+    reg  [AW:0] rd_binptr_mem;
+    wire [AW:0] rd_grayptr_nxt;
+    wire [AW:0] rd_binptr_nxt;
+    wire [AW:0] rd_binptr_mem_nxt;
+    wire [AW:0] rd_grayptr_sync;
+
+    genvar i;
+
+    //###########################
+    //# WRITE SIDE LOGIC
+    //###########################
+
+    always @(posedge wr_clk or negedge wr_nreset)
+        if (~wr_nreset) begin
+            wr_binptr_mem[AW:0] <= 'b0;
+            wr_binptr[AW:0]     <= 'b0;
+            wr_grayptr[AW:0]    <= 'b0;
+        end else begin
+            wr_binptr_mem[AW:0] <= (wr_binptr_mem_nxt[AW:0] == DEPTH) ? 'b0 : wr_binptr_mem_nxt[AW:0];
+            wr_binptr[AW:0] <= wr_binptr_nxt[AW:0];
+            wr_grayptr[AW:0] <= wr_grayptr_nxt[AW:0];
+        end
+
+    // Update binary pointer on write and not full
+    assign wr_binptr_mem_nxt[AW:0] = wr_binptr_mem[AW-1:0] + {{(AW-1){1'b0}}, (wr_en && ~wr_full)};
+    assign wr_binptr_nxt[AW:0] = wr_binptr[AW:0] + {{AW{1'b0}}, (wr_en && ~wr_full)};
+
+    // Convert binary point to gray pointer for sync
+    assign wr_grayptr_nxt[AW:0] = wr_binptr_nxt[AW:0] ^ {1'b0, wr_binptr_nxt[AW:1]};
+
+    // Full comparison (gray pointer based)
+    // Amir - add support for fifo DEPTH that is not power of 2
+    // Note - the previous logic also had a bug that full was high one entry to soon
+
+    reg [AW:0] rd_binptr_sync;
+    wire [AW:0] fifo_used;
+    integer j;
+
+    always @(*) begin
         rd_binptr_sync[AW] = rd_grayptr_sync[AW];
-        for (j=AW;j>0;j=j-1)
-          rd_binptr_sync[j-1] = rd_binptr_sync[j] ^ rd_grayptr_sync[j-1];
-     end
+        for (j = AW; j > 0; j = j - 1)
+        rd_binptr_sync[j-1] = rd_binptr_sync[j] ^ rd_grayptr_sync[j-1];
+    end
 
-   assign fifo_used = wr_binptr - rd_binptr_sync;
+    assign fifo_used = wr_binptr - rd_binptr_sync;
 
-   always @ (posedge wr_clk or negedge wr_nreset)
-     if (~wr_nreset)
-       wr_full <= 1'b0;
-     else
-       wr_full <= (wr_chaosfull & wr_chaosmode) |
+    always @(posedge wr_clk or negedge wr_nreset)
+        if (~wr_nreset) wr_full <= 1'b0;
+        else
+            wr_full <= (wr_chaosfull & wr_chaosmode) |
                   (fifo_used + {{AW{1'b0}}, (wr_en && ~wr_full)}) == DEPTH;
 
-   // Write --> Read clock synchronizer
-   for (i=0;i<(AW+1);i=i+1)
-     begin
-        la_drsync wrsync(.out(wr_grayptr_sync[i]),
-                         .clk(rd_clk),
-                         .nreset(rd_nreset),
-                         .in(wr_grayptr[i]));
-     end
-
-   //###########################
-   //# READ SIDE LOGIC
-   //###########################
-
-   always @ ( posedge rd_clk or negedge rd_nreset)
-     if(~rd_nreset)
-       begin
-          rd_binptr_mem[AW:0] <= 'b0;
-          rd_binptr[AW:0]     <= 'b0;
-          rd_grayptr[AW:0]    <= 'b0;
-       end
-     else
-       begin
-          rd_binptr_mem[AW:0] <= (rd_binptr_mem_nxt[AW:0] == DEPTH) ? 'b0 : rd_binptr_mem_nxt[AW:0];
-          rd_binptr[AW:0]  <= rd_binptr_nxt[AW:0];
-          rd_grayptr[AW:0] <= rd_grayptr_nxt[AW:0];
-       end
-
-   assign rd_binptr_mem_nxt[AW:0] = rd_binptr_mem[AW-1:0] + {{(AW-1){1'b0}}, (rd_en && ~rd_empty)};
-   assign rd_binptr_nxt[AW:0]     = rd_binptr[AW:0] + {{AW{1'b0}}, (rd_en && ~rd_empty)};
-   assign rd_grayptr_nxt[AW:0]    = rd_binptr_nxt[AW:0] ^ {1'b0, rd_binptr_nxt[AW:1]};
-
-   // Full comparison (gray pointer based)
-   always @ (posedge rd_clk or negedge rd_nreset)
-     if (~rd_nreset)
-       rd_empty <= 1'b1;
-     else
-       rd_empty <= (rd_grayptr_nxt[AW:0] == wr_grayptr_sync[AW:0]);
-
-   // Read --> write clock synchronizer
-   for (i=0;i<(AW+1);i=i+1)
-     begin
-        la_drsync rdsync(.out(rd_grayptr_sync[i]),
-                         .clk(wr_clk),
-                         .nreset(wr_nreset),
-                         .in(rd_grayptr[i]));
-     end
-
-   //###########################
-   //# Dual Port Memory
-   //###########################
-
-   reg [DW-1:0]         ram[DEPTH-1:0];
-
-   // Write port (FIFO input)
-   always @(posedge wr_clk)
-     if(wr_en & ~wr_full)
-       ram[wr_binptr_mem[AW-1:0]] <= wr_din[DW-1:0];
-
-   // Read port (FIFO output)
-   assign rd_dout[DW-1:0] = ram[rd_binptr_mem[AW-1:0]];
-
-   //############################
-   // Randomly Asserts FIFO full
-   //############################
-
-   generate
-      if (CHAOS)
-        begin
-           // TODO: implement LFSR
-           reg chaosreg;
-           always @ (posedge wr_clk or negedge wr_nreset)
-             if (~wr_nreset)
-               chaosreg <= 1'b0;
-             else
-               chaosreg <= ~chaosreg;
-           assign wr_chaosfull = chaosreg;
+    // Write --> Read clock synchronizer
+    for (i = 0; i < (AW + 1); i = i + 1) begin
+        la_drsync wrsync (
+            .out(wr_grayptr_sync[i]),
+            .clk(rd_clk),
+            .nreset(rd_nreset),
+            .in(wr_grayptr[i])
+        );
+    end
+
+    //###########################
+    //# READ SIDE LOGIC
+    //###########################
+
+    always @(posedge rd_clk or negedge rd_nreset)
+        if (~rd_nreset) begin
+            rd_binptr_mem[AW:0] <= 'b0;
+            rd_binptr[AW:0]     <= 'b0;
+            rd_grayptr[AW:0]    <= 'b0;
+        end else begin
+            rd_binptr_mem[AW:0] <= (rd_binptr_mem_nxt[AW:0] == DEPTH) ? 'b0 : rd_binptr_mem_nxt[AW:0];
+            rd_binptr[AW:0] <= rd_binptr_nxt[AW:0];
+            rd_grayptr[AW:0] <= rd_grayptr_nxt[AW:0];
         end
-      else
-        begin
-           assign wr_chaosfull = 1'b0;
+
+    assign rd_binptr_mem_nxt[AW:0] = rd_binptr_mem[AW-1:0] + {{(AW-1){1'b0}}, (rd_en && ~rd_empty)};
+    assign rd_binptr_nxt[AW:0] = rd_binptr[AW:0] + {{AW{1'b0}}, (rd_en && ~rd_empty)};
+    assign rd_grayptr_nxt[AW:0] = rd_binptr_nxt[AW:0] ^ {1'b0, rd_binptr_nxt[AW:1]};
+
+    // Full comparison (gray pointer based)
+    always @(posedge rd_clk or negedge rd_nreset)
+        if (~rd_nreset) rd_empty <= 1'b1;
+        else rd_empty <= (rd_grayptr_nxt[AW:0] == wr_grayptr_sync[AW:0]);
+
+    // Read --> write clock synchronizer
+    for (i = 0; i < (AW + 1); i = i + 1) begin
+        la_drsync rdsync (
+            .out(rd_grayptr_sync[i]),
+            .clk(wr_clk),
+            .nreset(wr_nreset),
+            .in(rd_grayptr[i])
+        );
+    end
+
+    //###########################
+    //# Dual Port Memory
+    //###########################
+
+    reg [DW-1:0] ram[DEPTH-1:0];
+
+    // Write port (FIFO input)
+    always @(posedge wr_clk) if (wr_en & ~wr_full) ram[wr_binptr_mem[AW-1:0]] <= wr_din[DW-1:0];
+
+    // Read port (FIFO output)
+    assign rd_dout[DW-1:0] = ram[rd_binptr_mem[AW-1:0]];
+
+    //############################
+    // Randomly Asserts FIFO full
+    //############################
+
+    generate
+        if (CHAOS) begin
+            // TODO: implement LFSR
+            reg chaosreg;
+            always @(posedge wr_clk or negedge wr_nreset)
+                if (~wr_nreset) chaosreg <= 1'b0;
+                else chaosreg <= ~chaosreg;
+            assign wr_chaosfull = chaosreg;
+        end else begin
+            assign wr_chaosfull = 1'b0;
         end
 
-   endgenerate
+    endgenerate
 
 
 endmodule
diff --git a/lambdapdk/freepdk45/libs/fakeram45/lambda/la_dpram.v b/lambdapdk/freepdk45/libs/fakeram45/lambda/la_dpram.v
index 8e46ebb7..129ef424 100644
--- a/lambdapdk/freepdk45/libs/fakeram45/lambda/la_dpram.v
+++ b/lambdapdk/freepdk45/libs/fakeram45/lambda/la_dpram.v
@@ -1,6 +1,6 @@
 /*****************************************************************************
  * Function: Dual Port RAM (One write port + One read port)
- * Copyright: Lambda Project Authors. ALl rights Reserved.
+ * Copyright: Lambda Project Authors. All rights Reserved.
  * License:  MIT (see LICENSE file in Lambda repository)
  *
  * Docs:
@@ -20,47 +20,43 @@
  *
  ****************************************************************************/
 
-module la_dpram
-  #(parameter DW     = 32,        // Memory width
-    parameter AW     = 10,        // address width (derived)
-    parameter TYPE   = "DEFAULT", // pass through variable for hard macro
-    parameter CTRLW  = 128,       // width of asic ctrl interface
-    parameter TESTW  = 128        // width of asic test interface
-    )
-   (// Write port
-    input 		wr_clk, // write clock
-    input 		wr_ce, // write chip-enable
-    input 		wr_we, // write enable
-    input [DW-1:0] 	wr_wmask, // write mask
-    input [AW-1:0] 	wr_addr, // write address
-    input [DW-1:0] 	wr_din, //write data in
+module la_dpram #(
+    parameter DW    = 32,         // Memory width
+    parameter AW    = 10,         // address width (derived)
+    parameter TYPE  = "DEFAULT",  // pass through variable for hard macro
+    parameter CTRLW = 128,        // width of asic ctrl interface
+    parameter TESTW = 128         // width of asic test interface
+) (  // Write port
+    input wr_clk,  // write clock
+    input wr_ce,  // write chip-enable
+    input wr_we,  // write enable
+    input [DW-1:0] wr_wmask,  // write mask
+    input [AW-1:0] wr_addr,  // write address
+    input [DW-1:0] wr_din,  //write data in
     // Read port
-    input 		rd_clk, // read clock
-    input 		rd_ce, // read chip-enable
-    input [AW-1:0] 	rd_addr, // read address
-    output reg [DW-1:0] rd_dout, //read data out
+    input rd_clk,  // read clock
+    input rd_ce,  // read chip-enable
+    input [AW-1:0] rd_addr,  // read address
+    output reg [DW-1:0] rd_dout,  //read data out
     // Power signal
-    input 		vss, // ground signal
-    input 		vdd, // memory core array power
-    input 		vddio, // periphery/io power
+    input vss,  // ground signal
+    input vdd,  // memory core array power
+    input vddio,  // periphery/io power
     // Generic interfaces
-    input [CTRLW-1:0] 	ctrl, // pass through ASIC control interface
-    input [TESTW-1:0] 	test // pass through ASIC test interface
-    );
+    input [CTRLW-1:0] ctrl,  // pass through ASIC control interface
+    input [TESTW-1:0] test  // pass through ASIC test interface
+);
 
-   // Generic RTL RAM
-   reg [DW-1:0]       ram[(2**AW)-1:0];
-   integer 	      i;
+    // Generic RTL RAM
+    reg     [DW-1:0] ram[(2**AW)-1:0];
+    integer          i;
 
-   // Write port
-   always @(posedge wr_clk)
-     for (i=0;i<DW;i=i+1)
-       if (wr_ce & wr_we & wr_wmask[i])
-         ram[wr_addr[AW-1:0]][i] <= wr_din[i];
+    // Write port
+    always @(posedge wr_clk)
+        for (i = 0; i < DW; i = i + 1)
+            if (wr_ce & wr_we & wr_wmask[i]) ram[wr_addr[AW-1:0]][i] <= wr_din[i];
 
-   // Read Port
-   always @ (posedge rd_clk)
-     if(rd_ce)
-       rd_dout[DW-1:0] <= ram[rd_addr[AW-1:0]];
+    // Read Port
+    always @(posedge rd_clk) if (rd_ce) rd_dout[DW-1:0] <= ram[rd_addr[AW-1:0]];
 
 endmodule
diff --git a/lambdapdk/freepdk45/libs/fakeram45/lambda/la_spram.v b/lambdapdk/freepdk45/libs/fakeram45/lambda/la_spram.v
index b970f705..7bc2143c 100644
--- a/lambdapdk/freepdk45/libs/fakeram45/lambda/la_spram.v
+++ b/lambdapdk/freepdk45/libs/fakeram45/lambda/la_spram.v
@@ -1,6 +1,6 @@
 /*****************************************************************************
- * Function: Single Port RAM
- * Copyright: Lambda Project Authors. ALl rights Reserved.
+ * Function: Single Port ram
+ * Copyright: Lambda Project Authors. All rights Reserved.
  * License:  MIT (see LICENSE file in Lambda repository)
  *
  * Docs:
@@ -14,7 +14,7 @@
  * supplied on a per macro basis.
  *
  * Technologoy specific implementations of "la_spram" would generally include
- * one ore more hardcoded instantiations of RAM modules with a generate
+ * one ore more hardcoded instantiations of ram modules with a generate
  * statement relying on the "TYPE" to select between the list of modules
  * at build time.
  *
@@ -28,50 +28,52 @@ module la_spram
     parameter TESTW  = 128          // Width of asic test interface
     )
    (// Memory interface
-    input 		clk, // write clock
-    input 		ce, // chip enable
-    input 		we, // write enable
-    input [DW-1:0] 	wmask, //per bit write mask
-    input [AW-1:0] 	addr,//write address
-    input [DW-1:0] 	din, //write data
-    output [DW-1:0] dout,//read output data
+    input clk, // write clock
+    input ce, // chip enable
+    input we, // write enable
+    input [DW-1:0] wmask, //per bit write mask
+    input [AW-1:0] addr, //write address
+    input [DW-1:0] din, //write data
+    output [DW-1:0] dout, //read output data
     // Power signals
-    input 		vss, // ground signal
-    input 		vdd, // memory core array power
-    input 		vddio, // periphery/io power
+    input vss, // ground signal
+    input vdd, // memory core array power
+    input vddio, // periphery/io power
     // Generic interfaces
-    input [CTRLW-1:0] 	ctrl, // pass through ASIC control interface
-    input [TESTW-1:0] 	test // pass through ASIC test interface
+    input [CTRLW-1:0] ctrl, // pass through ASIC control interface
+    input [TESTW-1:0] test // pass through ASIC test interface
     );
 
     // Determine which memory to select
-    localparam MEM_TYPE = 
+    localparam MEM_TYPE = (TYPE != "DEFAULT") ? TYPE :
       (AW >= 9) ? (DW >= 64) ? "fakeram45_512x64" : "fakeram45_512x32" :
       (AW == 8) ? (DW >= 64) ? "fakeram45_256x64" : "fakeram45_256x32" :
       (AW == 7) ? "fakeram45_128x32" :
       "fakeram45_64x32";
 
     localparam MEM_WIDTH = 
-      (MEM_TYPE == "fakeram45_512x64") ? 64 :
-      (MEM_TYPE == "fakeram45_512x32") ? 32 :
-      (MEM_TYPE == "fakeram45_256x64") ? 64 :
-      (MEM_TYPE == "fakeram45_256x32") ? 32 :
       (MEM_TYPE == "fakeram45_128x32") ? 32 :
+      (MEM_TYPE == "fakeram45_256x32") ? 32 :
+      (MEM_TYPE == "fakeram45_256x64") ? 64 :
+      (MEM_TYPE == "fakeram45_512x32") ? 32 :
+      (MEM_TYPE == "fakeram45_512x64") ? 64 :
       (MEM_TYPE == "fakeram45_64x32") ? 32 :
       0;
  
     localparam MEM_DEPTH = 
-      (MEM_TYPE == "fakeram45_512x64") ? 9 :
-      (MEM_TYPE == "fakeram45_512x32") ? 9 :
-      (MEM_TYPE == "fakeram45_256x64") ? 8 :
-      (MEM_TYPE == "fakeram45_256x32") ? 8 :
       (MEM_TYPE == "fakeram45_128x32") ? 7 :
+      (MEM_TYPE == "fakeram45_256x32") ? 8 :
+      (MEM_TYPE == "fakeram45_256x64") ? 8 :
+      (MEM_TYPE == "fakeram45_512x32") ? 9 :
+      (MEM_TYPE == "fakeram45_512x64") ? 9 :
       (MEM_TYPE == "fakeram45_64x32") ? 6 :
       0;
 
     // Create memories
     localparam MEM_ADDRS = 2**(AW - MEM_DEPTH) < 1 ? 1 : 2**(AW - MEM_DEPTH);
 
+    
+
     generate
       genvar o;
       for (o = 0; o < DW; o = o + 1) begin: OUTPUTS
@@ -115,62 +117,68 @@ module la_spram
           wire we_in;
           assign ce_in = ce && selected;
           assign we_in = we && selected;
-
-          if (MEM_TYPE == "fakeram45_512x64")
-            fakeram45_512x64 memory (
-              .clk(clk),
+          
+          if (MEM_TYPE == "fakeram45_512x32")
+            fakeram45_512x32 memory (
               .addr_in(mem_addr),
               .ce_in(ce_in),
+              .clk(clk),
               .rd_out(mem_dout),
-              .we_in(we_in),
               .w_mask_in(mem_wmask),
-              .wd_in(mem_din));
-          else if (MEM_TYPE == "fakeram45_512x32")
-            fakeram45_512x32 memory (
-              .clk(clk),
+              .wd_in(mem_din),
+              .we_in(we_in)
+            );
+          else if (MEM_TYPE == "fakeram45_512x64")
+            fakeram45_512x64 memory (
               .addr_in(mem_addr),
               .ce_in(ce_in),
+              .clk(clk),
               .rd_out(mem_dout),
-              .we_in(we_in),
               .w_mask_in(mem_wmask),
-              .wd_in(mem_din));
+              .wd_in(mem_din),
+              .we_in(we_in)
+            );
           else if (MEM_TYPE == "fakeram45_256x64")
             fakeram45_256x64 memory (
-              .clk(clk),
               .addr_in(mem_addr),
               .ce_in(ce_in),
+              .clk(clk),
               .rd_out(mem_dout),
-              .we_in(we_in),
               .w_mask_in(mem_wmask),
-              .wd_in(mem_din));
+              .wd_in(mem_din),
+              .we_in(we_in)
+            );
           else if (MEM_TYPE == "fakeram45_256x32")
             fakeram45_256x32 memory (
-              .clk(clk),
               .addr_in(mem_addr),
               .ce_in(ce_in),
+              .clk(clk),
               .rd_out(mem_dout),
-              .we_in(we_in),
               .w_mask_in(mem_wmask),
-              .wd_in(mem_din));
+              .wd_in(mem_din),
+              .we_in(we_in)
+            );
           else if (MEM_TYPE == "fakeram45_128x32")
             fakeram45_128x32 memory (
-              .clk(clk),
               .addr_in(mem_addr),
               .ce_in(ce_in),
+              .clk(clk),
               .rd_out(mem_dout),
-              .we_in(we_in),
               .w_mask_in(mem_wmask),
-              .wd_in(mem_din));
+              .wd_in(mem_din),
+              .we_in(we_in)
+            );
           else if (MEM_TYPE == "fakeram45_64x32")
             fakeram45_64x32 memory (
-              .clk(clk),
               .addr_in(mem_addr),
               .ce_in(ce_in),
+              .clk(clk),
               .rd_out(mem_dout),
-              .we_in(we_in),
               .w_mask_in(mem_wmask),
-              .wd_in(mem_din));
+              .wd_in(mem_din),
+              .we_in(we_in)
+            );
         end
       end
     endgenerate
-endmodule
+endmodule
\ No newline at end of file
diff --git a/lambdapdk/freepdk45/libs/fakeram45/lambda/la_spregfile.v b/lambdapdk/freepdk45/libs/fakeram45/lambda/la_spregfile.v
index a06a09db..d167168c 100644
--- a/lambdapdk/freepdk45/libs/fakeram45/lambda/la_spregfile.v
+++ b/lambdapdk/freepdk45/libs/fakeram45/lambda/la_spregfile.v
@@ -1,6 +1,6 @@
 /*****************************************************************************
  * Function: Single Port Register File
- * Copyright: Lambda Project Authors. ALl rights Reserved.
+ * Copyright: Lambda Project Authors. All rights Reserved.
  * License:  MIT (see LICENSE file in Lambda repository)
  *
  * Docs:
@@ -20,50 +20,48 @@
  *
  ****************************************************************************/
 
-module la_spregfile
-  #(parameter DW     = 32,          // Memory width
-    parameter AW     = 10,          // Address width (derived)
-    parameter TYPE   = "DEFAULT",   // Pass through variable for hard macro
-    parameter CTRLW  = 128,         // Width of asic ctrl interface
-    parameter TESTW  = 128          // Width of asic test interface
-    )
-   (// Memory interface
-    input 		clk, // write clock
-    input 		ce, // chip enable
-    input 		we, // write enable
-    input [DW-1:0] 	wmask, //per bit write mask
-    input [AW-1:0] 	addr,//write address
-    input [DW-1:0] 	din, //write data
-    output [DW-1:0]     dout,//read output data
+module la_spregfile #(
+    parameter DW    = 32,         // Memory width
+    parameter AW    = 10,         // Address width (derived)
+    parameter TYPE  = "DEFAULT",  // Pass through variable for hard macro
+    parameter CTRLW = 128,        // Width of asic ctrl interface
+    parameter TESTW = 128         // Width of asic test interface
+) (  // Memory interface
+    input              clk,    // write clock
+    input              ce,     // chip enable
+    input              we,     // write enable
+    input  [   DW-1:0] wmask,  //per bit write mask
+    input  [   AW-1:0] addr,   //write address
+    input  [   DW-1:0] din,    //write data
+    output [   DW-1:0] dout,   //read output data
     // Power signals
-    input 		vss, // ground signal
-    input 		vdd, // memory core array power
-    input 		vddio, // periphery/io power
+    input              vss,    // ground signal
+    input              vdd,    // memory core array power
+    input              vddio,  // periphery/io power
     // Generic interfaces
-    input [CTRLW-1:0] 	ctrl, // pass through ASIC control interface
-    input [TESTW-1:0] 	test // pass through ASIC test interface
-    );
+    input  [CTRLW-1:0] ctrl,   // pass through ASIC control interface
+    input  [TESTW-1:0] test    // pass through ASIC test interface
+);
 
-   la_spram
-   #(.DW(DW),
-     .AW(AW),
-     .TYPE(TYPE),
-     .CTRLW(CTRLW),
-     .TESTW(TESTW)
-     )
-   memory (
-     .clk(clk),
-     .ce(ce),
-     .we(we),
-     .wmask(wmask),
-     .addr(addr),
-     .din(din),
-     .dout(dout),
-     .vss(vss),
-     .vdd(vdd),
-     .vddio(vddio),
-     .ctrl(ctrl),
-     .test(test)
-   );
+    la_spram #(
+        .DW(DW),
+        .AW(AW),
+        .TYPE(TYPE),
+        .CTRLW(CTRLW),
+        .TESTW(TESTW)
+    ) memory (
+        .clk(clk),
+        .ce(ce),
+        .we(we),
+        .wmask(wmask),
+        .addr(addr),
+        .din(din),
+        .dout(dout),
+        .vss(vss),
+        .vdd(vdd),
+        .vddio(vddio),
+        .ctrl(ctrl),
+        .test(test)
+    );
 
 endmodule
diff --git a/lambdapdk/freepdk45/libs/fakeram45/lambda/la_syncfifo.v b/lambdapdk/freepdk45/libs/fakeram45/lambda/la_syncfifo.v
index bcb4ec2c..6355a26d 100644
--- a/lambdapdk/freepdk45/libs/fakeram45/lambda/la_syncfifo.v
+++ b/lambdapdk/freepdk45/libs/fakeram45/lambda/la_syncfifo.v
@@ -1,6 +1,6 @@
 /*****************************************************************************
  * Function: Synchronous FIFO
- * Copyright: Lambda Project Authors. ALl rights Reserved.
+ * Copyright: Lambda Project Authors. All rights Reserved.
  * License:  MIT (see LICENSE file in Lambda repository)
  *
  * Docs:
@@ -9,128 +9,112 @@
  *
  ****************************************************************************/
 
-module la_syncfifo
-  #(parameter DW        = 32,       // Memory width
-    parameter DEPTH     = 4,        // FIFO depth
-    parameter NS        = 1,        // Number of power supplies
-    parameter CHAOS     = 1,        // generates random full logic when set
-    parameter CTRLW     = 1,        // width of asic ctrl interface
-    parameter TESTW     = 1,        // width of asic test interface
-    parameter TYPE      = "DEFAULT" // Pass through variable for hard macro
-    )
-   (// common clock, reset, power, ctrl
-    input             clk,
-    input             nreset,
-    input             vss, // ground signal
-    input [NS-1:0]    vdd, // supplies
-    input             chaosmode,// randomly assert fifo full when set
-    input [CTRLW-1:0] ctrl, // pass through ASIC control interface
-    input [TESTW-1:0] test, // pass through ASIC test interface
+module la_syncfifo #(
+    parameter DW    = 32,        // Memory width
+    parameter DEPTH = 4,         // FIFO depth
+    parameter NS    = 1,         // Number of power supplies
+    parameter CHAOS = 1,         // generates random full logic when set
+    parameter CTRLW = 1,         // width of asic ctrl interface
+    parameter TESTW = 1,         // width of asic test interface
+    parameter TYPE  = "DEFAULT"  // Pass through variable for hard macro
+) (  // common clock, reset, power, ctrl
+    input              clk,
+    input              nreset,
+    input              vss,        // ground signal
+    input  [   NS-1:0] vdd,        // supplies
+    input              chaosmode,  // randomly assert fifo full when set
+    input  [CTRLW-1:0] ctrl,       // pass through ASIC control interface
+    input  [TESTW-1:0] test,       // pass through ASIC test interface
     // write input
-    input             wr_en, // write fifo
-    input [DW-1:0]    wr_din, // data to write
-    output            wr_full, // fifo full
+    input              wr_en,      // write fifo
+    input  [   DW-1:0] wr_din,     // data to write
+    output             wr_full,    // fifo full
     // read output
-    input             rd_en, // read fifo
-    output [DW-1:0]   rd_dout, // output data
-    output            rd_empty // fifo is empty
-    );
-
-   // local params
-   parameter AW  = $clog2(DEPTH);
-
-   // local wires
-   reg [AW:0]         wr_addr;
-   wire [AW:0]        wr_addr_nxt;
-   reg [AW:0]         rd_addr;
-   wire [AW:0]        rd_addr_nxt;
-   wire               fifo_read;
-   wire               fifo_write;
-   wire               chaosfull;
-   wire               rd_wrap_around;
-   wire               wr_wrap_around;
-
-   //############################
-   // FIFO Empty/Full
-   //############################
-
-   // support any fifo depth
-   assign wr_full     = (chaosfull & chaosmode) |
-                        {~wr_addr[AW], wr_addr[AW-1:0]} == rd_addr[AW:0];
-
-   assign rd_empty    = wr_addr[AW:0] == rd_addr[AW:0];
-
-   assign fifo_read   = rd_en & ~rd_empty;
-
-   assign fifo_write  = wr_en & ~wr_full;
-
-   //############################
-   // FIFO Pointers - wrap around DEPTH-1
-   //############################
-   assign rd_wrap_around       = rd_addr[AW-1:0] == (DEPTH[AW-1:0]-1'b1);
-   assign wr_wrap_around       = wr_addr[AW-1:0] == (DEPTH[AW-1:0]-1'b1);
-
-   assign rd_addr_nxt[AW]     = rd_wrap_around ? ~rd_addr[AW] : rd_addr[AW];
-   assign rd_addr_nxt[AW-1:0] = rd_wrap_around ? 'b0 : (rd_addr[AW-1:0] + 1);
-
-   assign wr_addr_nxt[AW]     = (wr_addr[AW-1:0] == (DEPTH[AW-1:0]-1'b1)) ? ~wr_addr[AW] : wr_addr[AW];
-   assign wr_addr_nxt[AW-1:0] = (wr_addr[AW-1:0] == (DEPTH[AW-1:0]-1'b1)) ? 'b0 : (wr_addr[AW-1:0] + 1);
-
-   always @ (posedge clk or negedge nreset)
-     if(~nreset)
-       begin
-          wr_addr[AW:0]    <= 'd0;
-          rd_addr[AW:0]    <= 'b0;
-       end
-     else if(fifo_write & fifo_read)
-       begin
-          wr_addr[AW:0] <= wr_addr_nxt[AW:0];
-          rd_addr[AW:0] <= rd_addr_nxt[AW:0];
-       end
-     else if(fifo_write)
-       begin
-          wr_addr[AW:0] <= wr_addr_nxt[AW:0];
-       end
-     else if(fifo_read)
-       begin
-          rd_addr[AW:0] <= rd_addr_nxt[AW:0];
-       end
-
-   //###########################
-   //# Dual Port Memory
-   //###########################
-
-   reg [DW-1:0]         ram[DEPTH-1:0];
-
-   // Write port (FIFO input)
-   always @(posedge clk)
-     if(wr_en & ~wr_full)
-       ram[wr_addr[AW-1:0]] <= wr_din[DW-1:0];
-
-   // Read port (FIFO output)
-   assign rd_dout[DW-1:0] = ram[rd_addr[AW-1:0]];
-
-
-   //############################
-   // Randomly Asserts FIFO full
-   //############################
-
-   generate
-      if (CHAOS)
-        begin
-           // TODO: implement LFSR
-           reg chaosreg;
-           always @ (posedge clk or negedge nreset)
-             if (~nreset)
-               chaosreg <= 1'b0;
-             else
-               chaosreg <= ~chaosreg;
-           assign chaosfull = chaosreg;
+    input              rd_en,      // read fifo
+    output [   DW-1:0] rd_dout,    // output data
+    output             rd_empty    // fifo is empty
+);
+
+    // local params
+    parameter AW = $clog2(DEPTH);
+
+    // local wires
+    reg  [AW:0] wr_addr;
+    wire [AW:0] wr_addr_nxt;
+    reg  [AW:0] rd_addr;
+    wire [AW:0] rd_addr_nxt;
+    wire        fifo_read;
+    wire        fifo_write;
+    wire        chaosfull;
+    wire        rd_wrap_around;
+    wire        wr_wrap_around;
+
+    //############################
+    // FIFO Empty/Full
+    //############################
+
+    // support any fifo depth
+    assign wr_full = (chaosfull & chaosmode) | {~wr_addr[AW], wr_addr[AW-1:0]} == rd_addr[AW:0];
+
+    assign rd_empty = wr_addr[AW:0] == rd_addr[AW:0];
+
+    assign fifo_read = rd_en & ~rd_empty;
+
+    assign fifo_write = wr_en & ~wr_full;
+
+    //############################
+    // FIFO Pointers - wrap around DEPTH-1
+    //############################
+    assign rd_wrap_around = rd_addr[AW-1:0] == (DEPTH[AW-1:0] - 1'b1);
+    assign wr_wrap_around = wr_addr[AW-1:0] == (DEPTH[AW-1:0] - 1'b1);
+
+    assign rd_addr_nxt[AW] = rd_wrap_around ? ~rd_addr[AW] : rd_addr[AW];
+    assign rd_addr_nxt[AW-1:0] = rd_wrap_around ? 'b0 : (rd_addr[AW-1:0] + 1);
+
+    assign wr_addr_nxt[AW]     = (wr_addr[AW-1:0] == (DEPTH[AW-1:0]-1'b1)) ? ~wr_addr[AW] : wr_addr[AW];
+    assign wr_addr_nxt[AW-1:0] = (wr_addr[AW-1:0] == (DEPTH[AW-1:0]-1'b1)) ? 'b0 : (wr_addr[AW-1:0] + 1);
+
+    always @(posedge clk or negedge nreset)
+        if (~nreset) begin
+            wr_addr[AW:0] <= 'd0;
+            rd_addr[AW:0] <= 'b0;
+        end else if (fifo_write & fifo_read) begin
+            wr_addr[AW:0] <= wr_addr_nxt[AW:0];
+            rd_addr[AW:0] <= rd_addr_nxt[AW:0];
+        end else if (fifo_write) begin
+            wr_addr[AW:0] <= wr_addr_nxt[AW:0];
+        end else if (fifo_read) begin
+            rd_addr[AW:0] <= rd_addr_nxt[AW:0];
         end
-      else
-        begin
-           assign chaosfull = 1'b0;
+
+    //###########################
+    //# Dual Port Memory
+    //###########################
+
+    reg [DW-1:0] ram[DEPTH-1:0];
+
+    // Write port (FIFO input)
+    always @(posedge clk) if (wr_en & ~wr_full) ram[wr_addr[AW-1:0]] <= wr_din[DW-1:0];
+
+    // Read port (FIFO output)
+    assign rd_dout[DW-1:0] = ram[rd_addr[AW-1:0]];
+
+
+    //############################
+    // Randomly Asserts FIFO full
+    //############################
+
+    generate
+        if (CHAOS) begin
+            // TODO: implement LFSR
+            reg chaosreg;
+            always @(posedge clk or negedge nreset)
+                if (~nreset) chaosreg <= 1'b0;
+                else chaosreg <= ~chaosreg;
+            assign chaosfull = chaosreg;
+        end else begin
+            assign chaosfull = 1'b0;
         end
-   endgenerate
+    endgenerate
 
 endmodule
diff --git a/lambdapdk/gf180/libs/gf180mcu_fd_io/lambda/la_ioclamp.v b/lambdapdk/gf180/libs/gf180mcu_fd_io/lambda/la_ioclamp.v
index f488febc..6adbf9b1 100644
--- a/lambdapdk/gf180/libs/gf180mcu_fd_io/lambda/la_ioclamp.v
+++ b/lambdapdk/gf180/libs/gf180mcu_fd_io/lambda/la_ioclamp.v
@@ -1,23 +1,21 @@
 /*****************************************************************************
  * Function: IO ESD clamp cell
- * Copyright: Lambda Project Authors. ALl rights Reserved.
+ * Copyright: Lambda Project Authors. All rights Reserved.
  * License:  MIT (see LICENSE file in Lambda repository)
  *
  * Docs:
  *
  ****************************************************************************/
-module la_ioclamp
-  #(
-    parameter TYPE  = "DEFAULT", // cell type
-    parameter SIDE  = "NO",      // "NO", "SO", "EA", "WE"
-    parameter RINGW =  8         // width of io ring
-    )
-   (// io pad signals
-    inout 	      vdd, // core supply
-    inout 	      vss, // core ground
-    inout 	      vddio, // io supply
-    inout 	      vssio, // io ground
-    inout [RINGW-1:0] ioring // generic io-ring interface
-    );
+module la_ioclamp #(
+    parameter TYPE  = "DEFAULT",  // cell type
+    parameter SIDE  = "NO",       // "NO", "SO", "EA", "WE"
+    parameter RINGW = 8           // width of io ring
+) (  // io pad signals
+    inout             vdd,    // core supply
+    inout             vss,    // core ground
+    inout             vddio,  // io supply
+    inout             vssio,  // io ground
+    inout [RINGW-1:0] ioring  // generic io-ring interface
+);
 
 endmodule
diff --git a/lambdapdk/gf180/libs/gf180mcu_fd_io/lambda/la_ioinput.v b/lambdapdk/gf180/libs/gf180mcu_fd_io/lambda/la_ioinput.v
index ed0aea68..05425b9b 100644
--- a/lambdapdk/gf180/libs/gf180mcu_fd_io/lambda/la_ioinput.v
+++ b/lambdapdk/gf180/libs/gf180mcu_fd_io/lambda/la_ioinput.v
@@ -1,6 +1,6 @@
 /*****************************************************************************
  * Function: IO bi-directional buffer
- * Copyright: Lambda Project Authors. ALl rights Reserved.
+ * Copyright: Lambda Project Authors. All rights Reserved.
  * License:  MIT (see LICENSE file in Lambda repository)
  *
  * Docs:
@@ -14,27 +14,25 @@
  * different IP cells for the placing cells vvertically or horizontally.
  *
  ****************************************************************************/
-module la_ioinput
-  #(
-    parameter TYPE  = "DEFAULT", // cell type
-    parameter SIDE  = "NO",      // "NO", "SO", "EA", "WE"
-    parameter CFGW  =  16,       // width of core config bus
-    parameter RINGW =  8         // width of io ring
-    )
-   (// io pad signals
-    inout 	      pad, // bidirectional pad signal
-    inout 	      vdd, // core supply
-    inout 	      vss, // core ground
-    inout 	      vddio, // io supply
-    inout 	      vssio, // io ground
+module la_ioinput #(
+    parameter TYPE  = "DEFAULT",  // cell type
+    parameter SIDE  = "NO",       // "NO", "SO", "EA", "WE"
+    parameter CFGW  = 16,         // width of core config bus
+    parameter RINGW = 8           // width of io ring
+) (  // io pad signals
+    inout              pad,     // bidirectional pad signal
+    inout              vdd,     // core supply
+    inout              vss,     // core ground
+    inout              vddio,   // io supply
+    inout              vssio,   // io ground
     // core facing signals
-    output 	      z, // output to core
-    input 	      ie, // input enable, 1 = active
-    inout [RINGW-1:0] ioring, // generic io-ring interface
-    input [CFGW-1:0]  cfg // generic config interface
-    );
+    output             z,       // output to core
+    input              ie,      // input enable, 1 = active
+    inout  [RINGW-1:0] ioring,  // generic io-ring interface
+    input  [ CFGW-1:0] cfg      // generic config interface
+);
 
-   // to core
-   assign z   = ie ? pad : 1'b0;
+    // to core
+    assign z = ie ? pad : 1'b0;
 
 endmodule
diff --git a/lambdapdk/gf180/libs/gf180mcu_fd_io/lambda/la_ioshort.v b/lambdapdk/gf180/libs/gf180mcu_fd_io/lambda/la_ioshort.v
index 94b228a2..6341cf87 100644
--- a/lambdapdk/gf180/libs/gf180mcu_fd_io/lambda/la_ioshort.v
+++ b/lambdapdk/gf180/libs/gf180mcu_fd_io/lambda/la_ioshort.v
@@ -1,6 +1,6 @@
 /*****************************************************************************
  * Function: Shorting two wires together
- * Copyright: Lambda Project Authors. ALl rights Reserved.
+ * Copyright: Lambda Project Authors. All rights Reserved.
  * License:  MIT (see LICENSE file in Lambda repository)
  *
  * Docs:
@@ -11,20 +11,24 @@
  * connection in RTL.
  *
  ****************************************************************************/
-module la_ioshort
-  (
-   inout a,
-   inout b,
-   input a2b
-   );
+module la_ioshort (
+    inout a,
+    inout b,
+    input a2b
+);
 
 `ifdef VERILATOR
-   // Using direction to break the loop
-   assign a = ~a2b ? b : 1'bz;
-   assign b = a2b  ? a : 1'bz;
+    // Using direction to break the loop
+    assign a = ~a2b ? b : 1'bz;
+    assign b = a2b ? a : 1'bz;
 `else
-   // single port pass through short/hack
-   la_pt la_pt(a,b);
+    // single port pass through short/hack
+    // verilog_lint: waive-start module-port
+    la_pt la_pt (
+        a,
+        b
+    );
+    // verilog_lint: waive-end module-port
 `endif
 
-endmodule // la_ioshort
+endmodule  // la_ioshort
diff --git a/lambdapdk/gf180/libs/gf180mcu_fd_io/lambda/la_iovdda.v b/lambdapdk/gf180/libs/gf180mcu_fd_io/lambda/la_iovdda.v
index 4a04f423..8b433c27 100644
--- a/lambdapdk/gf180/libs/gf180mcu_fd_io/lambda/la_iovdda.v
+++ b/lambdapdk/gf180/libs/gf180mcu_fd_io/lambda/la_iovdda.v
@@ -1,24 +1,22 @@
 /*****************************************************************************
  * Function: IO supply cell (vdda)
- * Copyright: Lambda Project Authors. ALl rights Reserved.
+ * Copyright: Lambda Project Authors. All rights Reserved.
  * License:  MIT (see LICENSE file in Lambda repository)
  *
  * Docs:
  *
  *
  ****************************************************************************/
-module la_iovdda
-  #(
-    parameter TYPE  = "DEFAULT", // cell type
-    parameter SIDE  = "NO",      // "NO", "SO", "EA", "WE"
-    parameter RINGW =  8         // width of io ring
-    )
-   (
-    inout 	      vdd, // core supply
-    inout 	      vss, // core ground
-    inout 	      vddio, // io supply
-    inout 	      vssio, // io ground
-    inout [RINGW-1:0] ioring // generic io-ring interface
-    );
+module la_iovdda #(
+    parameter TYPE  = "DEFAULT",  // cell type
+    parameter SIDE  = "NO",       // "NO", "SO", "EA", "WE"
+    parameter RINGW = 8           // width of io ring
+) (
+    inout             vdd,    // core supply
+    inout             vss,    // core ground
+    inout             vddio,  // io supply
+    inout             vssio,  // io ground
+    inout [RINGW-1:0] ioring  // generic io-ring interface
+);
 
 endmodule
diff --git a/lambdapdk/gf180/libs/gf180mcu_fd_io/lambda/la_iovssa.v b/lambdapdk/gf180/libs/gf180mcu_fd_io/lambda/la_iovssa.v
index 9904bb09..bf43c55b 100644
--- a/lambdapdk/gf180/libs/gf180mcu_fd_io/lambda/la_iovssa.v
+++ b/lambdapdk/gf180/libs/gf180mcu_fd_io/lambda/la_iovssa.v
@@ -1,24 +1,22 @@
 /*****************************************************************************
  * Function: IO supply cell (vssa)
- * Copyright: Lambda Project Authors. ALl rights Reserved.
+ * Copyright: Lambda Project Authors. All rights Reserved.
  * License:  MIT (see LICENSE file in Lambda repository)
  *
  * Docs:
  *
  *
  ****************************************************************************/
-module la_iovssa
-  #(
-    parameter TYPE  = "DEFAULT", // cell type
-    parameter SIDE  = "NO",      // "NO", "SO", "EA", "WE"
-    parameter RINGW =  8         // width of io ring
-    )
-   (
-    inout 	      vdd, // core supply
-    inout 	      vss, // core ground
-    inout 	      vddio, // io supply
-    inout 	      vssio, // io ground
-    inout [RINGW-1:0] ioring // generic io-ring interface
-    );
+module la_iovssa #(
+    parameter TYPE  = "DEFAULT",  // cell type
+    parameter SIDE  = "NO",       // "NO", "SO", "EA", "WE"
+    parameter RINGW = 8           // width of io ring
+) (
+    inout             vdd,    // core supply
+    inout             vss,    // core ground
+    inout             vddio,  // io supply
+    inout             vssio,  // io ground
+    inout [RINGW-1:0] ioring  // generic io-ring interface
+);
 
 endmodule
diff --git a/lambdapdk/gf180/libs/gf180mcu_fd_io/lambda/la_ioxtal.v b/lambdapdk/gf180/libs/gf180mcu_fd_io/lambda/la_ioxtal.v
index 71bece5e..91c7b9e2 100644
--- a/lambdapdk/gf180/libs/gf180mcu_fd_io/lambda/la_ioxtal.v
+++ b/lambdapdk/gf180/libs/gf180mcu_fd_io/lambda/la_ioxtal.v
@@ -1,29 +1,27 @@
 /*****************************************************************************
  * Function: IO xtal oscillator cell
- * Copyright: Lambda Project Authors. ALl rights Reserved.
+ * Copyright: Lambda Project Authors. All rights Reserved.
  * License:  MIT (see LICENSE file in Lambda repository)
  *
  * Docs:
  *
  ****************************************************************************/
-module la_ioxtal
-  #(
-    parameter TYPE = "DEFAULT", // cell type
-    parameter SIDE  = "NO",     // "NO", "SO", "EA", "WE"
-    parameter CFGW  =  16,       // width of core config bus
-    parameter RINGW =  8        // width of io ring
-    )
-   (// io pad signals
-    inout 	      padi, // xtal input pad
-    inout 	      pado, // xtal output pad
-    inout 	      vdd, // core supply
-    inout 	      vss, // core ground
-    inout 	      vddio, // io supply
-    inout 	      vssio, // io ground
-    inout [RINGW-1:0] ioring, // generic io-ring interface
-    input [CFGW-1:0]  cfg, // generic config interface
+module la_ioxtal #(
+    parameter TYPE  = "DEFAULT",  // cell type
+    parameter SIDE  = "NO",       // "NO", "SO", "EA", "WE"
+    parameter CFGW  = 16,         // width of core config bus
+    parameter RINGW = 8           // width of io ring
+) (  // io pad signals
+    inout              padi,    // xtal input pad
+    inout              pado,    // xtal output pad
+    inout              vdd,     // core supply
+    inout              vss,     // core ground
+    inout              vddio,   // io supply
+    inout              vssio,   // io ground
+    inout  [RINGW-1:0] ioring,  // generic io-ring interface
+    input  [ CFGW-1:0] cfg,     // generic config interface
     // core interface
-    output 	      z // clock output to core
-    );
+    output             z        // clock output to core
+);
 
 endmodule
diff --git a/lambdapdk/gf180/libs/gf180mcu_fd_io/lambda/la_pt.v b/lambdapdk/gf180/libs/gf180mcu_fd_io/lambda/la_pt.v
index f14916af..7e3b432c 100644
--- a/lambdapdk/gf180/libs/gf180mcu_fd_io/lambda/la_pt.v
+++ b/lambdapdk/gf180/libs/gf180mcu_fd_io/lambda/la_pt.v
@@ -1,8 +1,11 @@
 
 //Solution to the short was found at the end of a conversation thread at this
-//link: 
+//link:
 //https://groups.google.com/g/comp.lang.verilog/c/b3-6XMA8KA4
-//-PG 10/31/2022
-module la_pt(.io1(a),.io2(a));
-   inout wire a;
-endmodule // la_pt
+
+module la_pt (
+    .io1(a),
+    .io2(a)
+);
+    inout wire a;
+endmodule  // la_pt
diff --git a/lambdapdk/gf180/libs/gf180mcu_fd_ip_sram/lambda/la_asyncfifo.v b/lambdapdk/gf180/libs/gf180mcu_fd_ip_sram/lambda/la_asyncfifo.v
index e865f73c..3d37a974 100644
--- a/lambdapdk/gf180/libs/gf180mcu_fd_ip_sram/lambda/la_asyncfifo.v
+++ b/lambdapdk/gf180/libs/gf180mcu_fd_ip_sram/lambda/la_asyncfifo.v
@@ -1,6 +1,6 @@
 /*****************************************************************************
  * Function: Dual Clock Asynchronous FIFO
- * Copyright: Lambda Project Authors. ALl rights Reserved.
+ * Copyright: Lambda Project Authors. All rights Reserved.
  * License:  MIT (see LICENSE file in Lambda repository)
  *
  * Docs:
@@ -20,192 +20,176 @@
  *
  ****************************************************************************/
 
-module la_asyncfifo
-  #(parameter DW        = 32,       // Memory width
-    parameter DEPTH     = 4,        // FIFO depth
-    parameter NS        = 1,        // Number of power supplies
-    parameter CTRLW     = 1,        // width of asic ctrl interface
-    parameter TESTW     = 1,        // width of asic teset interface
-    parameter CHAOS     = 0,        // generates random full logic when set
-    parameter TYPE      = "DEFAULT" // Pass through variable for hard macro
-    )
-   (// write port
-    input             wr_clk,
-    input             wr_nreset,
-    input [DW-1:0]    wr_din, // data to write
-    input             wr_en, // write fifo
-    input             wr_chaosmode,// randomly assert fifo full when set
-    output reg        wr_full, // fifo full
+module la_asyncfifo #(
+    parameter DW    = 32,        // Memory width
+    parameter DEPTH = 4,         // FIFO depth
+    parameter NS    = 1,         // Number of power supplies
+    parameter CTRLW = 1,         // width of asic ctrl interface
+    parameter TESTW = 1,         // width of asic teset interface
+    parameter CHAOS = 0,         // generates random full logic when set
+    parameter TYPE  = "DEFAULT"  // Pass through variable for hard macro
+) (  // write port
+    input                  wr_clk,
+    input                  wr_nreset,
+    input      [   DW-1:0] wr_din,        // data to write
+    input                  wr_en,         // write fifo
+    input                  wr_chaosmode,  // randomly assert fifo full when set
+    output reg             wr_full,       // fifo full
     // read port
-    input             rd_clk,
-    input             rd_nreset,
-    output [DW-1:0]   rd_dout, // output data (next cycle)
-    input             rd_en, // read fifo
-    output reg        rd_empty, // fifo is empty
+    input                  rd_clk,
+    input                  rd_nreset,
+    output     [   DW-1:0] rd_dout,       // output data (next cycle)
+    input                  rd_en,         // read fifo
+    output reg             rd_empty,      // fifo is empty
     // Power signals
-    input             vss, // ground signal
-    input [NS-1:0]    vdd, // supplies
+    input                  vss,           // ground signal
+    input      [   NS-1:0] vdd,           // supplies
     // Generic interfaces
-    input [CTRLW-1:0] ctrl, // pass through ASIC control interface
-    input [TESTW-1:0] test // pass through ASIC test interface
-    );
-
-   // local params
-   // The last part is to support DEPTH of 1
-   localparam AW  = $clog2(DEPTH) + {31'h0,(DEPTH == 1)};
-
-   // local wires
-   reg [AW:0]     wr_grayptr;
-   reg [AW:0]     wr_binptr;
-   reg [AW:0]     wr_binptr_mem;
-   wire [AW:0]    wr_grayptr_nxt;
-   wire [AW:0]    wr_binptr_nxt;
-   wire [AW:0]    wr_binptr_mem_nxt;
-   wire [AW:0]    wr_grayptr_sync;
-   wire           wr_chaosfull;
-
-   reg [AW:0]     rd_grayptr;
-   reg [AW:0]     rd_binptr;
-   reg [AW:0]     rd_binptr_mem;
-   wire [AW:0]    rd_grayptr_nxt;
-   wire [AW:0]    rd_binptr_nxt;
-   wire [AW:0]    rd_binptr_mem_nxt;
-   wire [AW:0]    rd_grayptr_sync;
-
-   genvar         i;
-
-   //###########################
-   //# WRITE SIDE LOGIC
-   //###########################
-
-   always @ ( posedge wr_clk or negedge wr_nreset)
-     if(~wr_nreset)
-       begin
-          wr_binptr_mem[AW:0] <= 'b0;
-          wr_binptr[AW:0]     <= 'b0;
-          wr_grayptr[AW:0]    <= 'b0;
-       end
-     else
-       begin
-          wr_binptr_mem[AW:0] <= (wr_binptr_mem_nxt[AW:0] == DEPTH) ? 'b0 : wr_binptr_mem_nxt[AW:0];
-          wr_binptr[AW:0]     <= wr_binptr_nxt[AW:0];
-          wr_grayptr[AW:0]    <= wr_grayptr_nxt[AW:0];
-       end
-
-   // Update binary pointer on write and not full
-   assign wr_binptr_mem_nxt[AW:0] = wr_binptr_mem[AW-1:0] + {{(AW-1){1'b0}}, (wr_en && ~wr_full)};
-   assign wr_binptr_nxt[AW:0]     = wr_binptr[AW:0] + {{AW{1'b0}}, (wr_en && ~wr_full)};
-
-   // Convert binary point to gray pointer for sync
-   assign wr_grayptr_nxt[AW:0] =  wr_binptr_nxt[AW:0] ^ {1'b0, wr_binptr_nxt[AW:1]};
-
-   // Full comparison (gray pointer based)
-   // Amir - add support for fifo DEPTH that is not power of 2
-   // Note - the previous logic also had a bug that full was high one entry to soon
-
-   reg [AW:0] rd_binptr_sync;
-   wire [AW:0] fifo_used;
-   integer j;
-
-   always @(*)
-     begin
+    input      [CTRLW-1:0] ctrl,          // pass through ASIC control interface
+    input      [TESTW-1:0] test           // pass through ASIC test interface
+);
+
+    // local params
+    // The last part is to support DEPTH of 1
+    localparam AW = $clog2(DEPTH) + {31'h0, (DEPTH == 1)};
+
+    // local wires
+    reg  [AW:0] wr_grayptr;
+    reg  [AW:0] wr_binptr;
+    reg  [AW:0] wr_binptr_mem;
+    wire [AW:0] wr_grayptr_nxt;
+    wire [AW:0] wr_binptr_nxt;
+    wire [AW:0] wr_binptr_mem_nxt;
+    wire [AW:0] wr_grayptr_sync;
+    wire        wr_chaosfull;
+
+    reg  [AW:0] rd_grayptr;
+    reg  [AW:0] rd_binptr;
+    reg  [AW:0] rd_binptr_mem;
+    wire [AW:0] rd_grayptr_nxt;
+    wire [AW:0] rd_binptr_nxt;
+    wire [AW:0] rd_binptr_mem_nxt;
+    wire [AW:0] rd_grayptr_sync;
+
+    genvar i;
+
+    //###########################
+    //# WRITE SIDE LOGIC
+    //###########################
+
+    always @(posedge wr_clk or negedge wr_nreset)
+        if (~wr_nreset) begin
+            wr_binptr_mem[AW:0] <= 'b0;
+            wr_binptr[AW:0]     <= 'b0;
+            wr_grayptr[AW:0]    <= 'b0;
+        end else begin
+            wr_binptr_mem[AW:0] <= (wr_binptr_mem_nxt[AW:0] == DEPTH) ? 'b0 : wr_binptr_mem_nxt[AW:0];
+            wr_binptr[AW:0] <= wr_binptr_nxt[AW:0];
+            wr_grayptr[AW:0] <= wr_grayptr_nxt[AW:0];
+        end
+
+    // Update binary pointer on write and not full
+    assign wr_binptr_mem_nxt[AW:0] = wr_binptr_mem[AW-1:0] + {{(AW-1){1'b0}}, (wr_en && ~wr_full)};
+    assign wr_binptr_nxt[AW:0] = wr_binptr[AW:0] + {{AW{1'b0}}, (wr_en && ~wr_full)};
+
+    // Convert binary point to gray pointer for sync
+    assign wr_grayptr_nxt[AW:0] = wr_binptr_nxt[AW:0] ^ {1'b0, wr_binptr_nxt[AW:1]};
+
+    // Full comparison (gray pointer based)
+    // Amir - add support for fifo DEPTH that is not power of 2
+    // Note - the previous logic also had a bug that full was high one entry to soon
+
+    reg [AW:0] rd_binptr_sync;
+    wire [AW:0] fifo_used;
+    integer j;
+
+    always @(*) begin
         rd_binptr_sync[AW] = rd_grayptr_sync[AW];
-        for (j=AW;j>0;j=j-1)
-          rd_binptr_sync[j-1] = rd_binptr_sync[j] ^ rd_grayptr_sync[j-1];
-     end
+        for (j = AW; j > 0; j = j - 1)
+        rd_binptr_sync[j-1] = rd_binptr_sync[j] ^ rd_grayptr_sync[j-1];
+    end
 
-   assign fifo_used = wr_binptr - rd_binptr_sync;
+    assign fifo_used = wr_binptr - rd_binptr_sync;
 
-   always @ (posedge wr_clk or negedge wr_nreset)
-     if (~wr_nreset)
-       wr_full <= 1'b0;
-     else
-       wr_full <= (wr_chaosfull & wr_chaosmode) |
+    always @(posedge wr_clk or negedge wr_nreset)
+        if (~wr_nreset) wr_full <= 1'b0;
+        else
+            wr_full <= (wr_chaosfull & wr_chaosmode) |
                   (fifo_used + {{AW{1'b0}}, (wr_en && ~wr_full)}) == DEPTH;
 
-   // Write --> Read clock synchronizer
-   for (i=0;i<(AW+1);i=i+1)
-     begin
-        la_drsync wrsync(.out(wr_grayptr_sync[i]),
-                         .clk(rd_clk),
-                         .nreset(rd_nreset),
-                         .in(wr_grayptr[i]));
-     end
-
-   //###########################
-   //# READ SIDE LOGIC
-   //###########################
-
-   always @ ( posedge rd_clk or negedge rd_nreset)
-     if(~rd_nreset)
-       begin
-          rd_binptr_mem[AW:0] <= 'b0;
-          rd_binptr[AW:0]     <= 'b0;
-          rd_grayptr[AW:0]    <= 'b0;
-       end
-     else
-       begin
-          rd_binptr_mem[AW:0] <= (rd_binptr_mem_nxt[AW:0] == DEPTH) ? 'b0 : rd_binptr_mem_nxt[AW:0];
-          rd_binptr[AW:0]  <= rd_binptr_nxt[AW:0];
-          rd_grayptr[AW:0] <= rd_grayptr_nxt[AW:0];
-       end
-
-   assign rd_binptr_mem_nxt[AW:0] = rd_binptr_mem[AW-1:0] + {{(AW-1){1'b0}}, (rd_en && ~rd_empty)};
-   assign rd_binptr_nxt[AW:0]     = rd_binptr[AW:0] + {{AW{1'b0}}, (rd_en && ~rd_empty)};
-   assign rd_grayptr_nxt[AW:0]    = rd_binptr_nxt[AW:0] ^ {1'b0, rd_binptr_nxt[AW:1]};
-
-   // Full comparison (gray pointer based)
-   always @ (posedge rd_clk or negedge rd_nreset)
-     if (~rd_nreset)
-       rd_empty <= 1'b1;
-     else
-       rd_empty <= (rd_grayptr_nxt[AW:0] == wr_grayptr_sync[AW:0]);
-
-   // Read --> write clock synchronizer
-   for (i=0;i<(AW+1);i=i+1)
-     begin
-        la_drsync rdsync(.out(rd_grayptr_sync[i]),
-                         .clk(wr_clk),
-                         .nreset(wr_nreset),
-                         .in(rd_grayptr[i]));
-     end
-
-   //###########################
-   //# Dual Port Memory
-   //###########################
-
-   reg [DW-1:0]         ram[DEPTH-1:0];
-
-   // Write port (FIFO input)
-   always @(posedge wr_clk)
-     if(wr_en & ~wr_full)
-       ram[wr_binptr_mem[AW-1:0]] <= wr_din[DW-1:0];
-
-   // Read port (FIFO output)
-   assign rd_dout[DW-1:0] = ram[rd_binptr_mem[AW-1:0]];
-
-   //############################
-   // Randomly Asserts FIFO full
-   //############################
-
-   generate
-      if (CHAOS)
-        begin
-           // TODO: implement LFSR
-           reg chaosreg;
-           always @ (posedge wr_clk or negedge wr_nreset)
-             if (~wr_nreset)
-               chaosreg <= 1'b0;
-             else
-               chaosreg <= ~chaosreg;
-           assign wr_chaosfull = chaosreg;
+    // Write --> Read clock synchronizer
+    for (i = 0; i < (AW + 1); i = i + 1) begin
+        la_drsync wrsync (
+            .out(wr_grayptr_sync[i]),
+            .clk(rd_clk),
+            .nreset(rd_nreset),
+            .in(wr_grayptr[i])
+        );
+    end
+
+    //###########################
+    //# READ SIDE LOGIC
+    //###########################
+
+    always @(posedge rd_clk or negedge rd_nreset)
+        if (~rd_nreset) begin
+            rd_binptr_mem[AW:0] <= 'b0;
+            rd_binptr[AW:0]     <= 'b0;
+            rd_grayptr[AW:0]    <= 'b0;
+        end else begin
+            rd_binptr_mem[AW:0] <= (rd_binptr_mem_nxt[AW:0] == DEPTH) ? 'b0 : rd_binptr_mem_nxt[AW:0];
+            rd_binptr[AW:0] <= rd_binptr_nxt[AW:0];
+            rd_grayptr[AW:0] <= rd_grayptr_nxt[AW:0];
         end
-      else
-        begin
-           assign wr_chaosfull = 1'b0;
+
+    assign rd_binptr_mem_nxt[AW:0] = rd_binptr_mem[AW-1:0] + {{(AW-1){1'b0}}, (rd_en && ~rd_empty)};
+    assign rd_binptr_nxt[AW:0] = rd_binptr[AW:0] + {{AW{1'b0}}, (rd_en && ~rd_empty)};
+    assign rd_grayptr_nxt[AW:0] = rd_binptr_nxt[AW:0] ^ {1'b0, rd_binptr_nxt[AW:1]};
+
+    // Full comparison (gray pointer based)
+    always @(posedge rd_clk or negedge rd_nreset)
+        if (~rd_nreset) rd_empty <= 1'b1;
+        else rd_empty <= (rd_grayptr_nxt[AW:0] == wr_grayptr_sync[AW:0]);
+
+    // Read --> write clock synchronizer
+    for (i = 0; i < (AW + 1); i = i + 1) begin
+        la_drsync rdsync (
+            .out(rd_grayptr_sync[i]),
+            .clk(wr_clk),
+            .nreset(wr_nreset),
+            .in(rd_grayptr[i])
+        );
+    end
+
+    //###########################
+    //# Dual Port Memory
+    //###########################
+
+    reg [DW-1:0] ram[DEPTH-1:0];
+
+    // Write port (FIFO input)
+    always @(posedge wr_clk) if (wr_en & ~wr_full) ram[wr_binptr_mem[AW-1:0]] <= wr_din[DW-1:0];
+
+    // Read port (FIFO output)
+    assign rd_dout[DW-1:0] = ram[rd_binptr_mem[AW-1:0]];
+
+    //############################
+    // Randomly Asserts FIFO full
+    //############################
+
+    generate
+        if (CHAOS) begin
+            // TODO: implement LFSR
+            reg chaosreg;
+            always @(posedge wr_clk or negedge wr_nreset)
+                if (~wr_nreset) chaosreg <= 1'b0;
+                else chaosreg <= ~chaosreg;
+            assign wr_chaosfull = chaosreg;
+        end else begin
+            assign wr_chaosfull = 1'b0;
         end
 
-   endgenerate
+    endgenerate
 
 
 endmodule
diff --git a/lambdapdk/gf180/libs/gf180mcu_fd_ip_sram/lambda/la_dpram.v b/lambdapdk/gf180/libs/gf180mcu_fd_ip_sram/lambda/la_dpram.v
index 8e46ebb7..129ef424 100644
--- a/lambdapdk/gf180/libs/gf180mcu_fd_ip_sram/lambda/la_dpram.v
+++ b/lambdapdk/gf180/libs/gf180mcu_fd_ip_sram/lambda/la_dpram.v
@@ -1,6 +1,6 @@
 /*****************************************************************************
  * Function: Dual Port RAM (One write port + One read port)
- * Copyright: Lambda Project Authors. ALl rights Reserved.
+ * Copyright: Lambda Project Authors. All rights Reserved.
  * License:  MIT (see LICENSE file in Lambda repository)
  *
  * Docs:
@@ -20,47 +20,43 @@
  *
  ****************************************************************************/
 
-module la_dpram
-  #(parameter DW     = 32,        // Memory width
-    parameter AW     = 10,        // address width (derived)
-    parameter TYPE   = "DEFAULT", // pass through variable for hard macro
-    parameter CTRLW  = 128,       // width of asic ctrl interface
-    parameter TESTW  = 128        // width of asic test interface
-    )
-   (// Write port
-    input 		wr_clk, // write clock
-    input 		wr_ce, // write chip-enable
-    input 		wr_we, // write enable
-    input [DW-1:0] 	wr_wmask, // write mask
-    input [AW-1:0] 	wr_addr, // write address
-    input [DW-1:0] 	wr_din, //write data in
+module la_dpram #(
+    parameter DW    = 32,         // Memory width
+    parameter AW    = 10,         // address width (derived)
+    parameter TYPE  = "DEFAULT",  // pass through variable for hard macro
+    parameter CTRLW = 128,        // width of asic ctrl interface
+    parameter TESTW = 128         // width of asic test interface
+) (  // Write port
+    input wr_clk,  // write clock
+    input wr_ce,  // write chip-enable
+    input wr_we,  // write enable
+    input [DW-1:0] wr_wmask,  // write mask
+    input [AW-1:0] wr_addr,  // write address
+    input [DW-1:0] wr_din,  //write data in
     // Read port
-    input 		rd_clk, // read clock
-    input 		rd_ce, // read chip-enable
-    input [AW-1:0] 	rd_addr, // read address
-    output reg [DW-1:0] rd_dout, //read data out
+    input rd_clk,  // read clock
+    input rd_ce,  // read chip-enable
+    input [AW-1:0] rd_addr,  // read address
+    output reg [DW-1:0] rd_dout,  //read data out
     // Power signal
-    input 		vss, // ground signal
-    input 		vdd, // memory core array power
-    input 		vddio, // periphery/io power
+    input vss,  // ground signal
+    input vdd,  // memory core array power
+    input vddio,  // periphery/io power
     // Generic interfaces
-    input [CTRLW-1:0] 	ctrl, // pass through ASIC control interface
-    input [TESTW-1:0] 	test // pass through ASIC test interface
-    );
+    input [CTRLW-1:0] ctrl,  // pass through ASIC control interface
+    input [TESTW-1:0] test  // pass through ASIC test interface
+);
 
-   // Generic RTL RAM
-   reg [DW-1:0]       ram[(2**AW)-1:0];
-   integer 	      i;
+    // Generic RTL RAM
+    reg     [DW-1:0] ram[(2**AW)-1:0];
+    integer          i;
 
-   // Write port
-   always @(posedge wr_clk)
-     for (i=0;i<DW;i=i+1)
-       if (wr_ce & wr_we & wr_wmask[i])
-         ram[wr_addr[AW-1:0]][i] <= wr_din[i];
+    // Write port
+    always @(posedge wr_clk)
+        for (i = 0; i < DW; i = i + 1)
+            if (wr_ce & wr_we & wr_wmask[i]) ram[wr_addr[AW-1:0]][i] <= wr_din[i];
 
-   // Read Port
-   always @ (posedge rd_clk)
-     if(rd_ce)
-       rd_dout[DW-1:0] <= ram[rd_addr[AW-1:0]];
+    // Read Port
+    always @(posedge rd_clk) if (rd_ce) rd_dout[DW-1:0] <= ram[rd_addr[AW-1:0]];
 
 endmodule
diff --git a/lambdapdk/gf180/libs/gf180mcu_fd_ip_sram/lambda/la_spram.v b/lambdapdk/gf180/libs/gf180mcu_fd_ip_sram/lambda/la_spram.v
index da9ebe07..22584403 100644
--- a/lambdapdk/gf180/libs/gf180mcu_fd_ip_sram/lambda/la_spram.v
+++ b/lambdapdk/gf180/libs/gf180mcu_fd_ip_sram/lambda/la_spram.v
@@ -1,6 +1,6 @@
 /*****************************************************************************
- * Function: Single Port RAM
- * Copyright: Lambda Project Authors. ALl rights Reserved.
+ * Function: Single Port ram
+ * Copyright: Lambda Project Authors. All rights Reserved.
  * License:  MIT (see LICENSE file in Lambda repository)
  *
  * Docs:
@@ -14,7 +14,7 @@
  * supplied on a per macro basis.
  *
  * Technologoy specific implementations of "la_spram" would generally include
- * one ore more hardcoded instantiations of RAM modules with a generate
+ * one ore more hardcoded instantiations of ram modules with a generate
  * statement relying on the "TYPE" to select between the list of modules
  * at build time.
  *
@@ -28,46 +28,48 @@ module la_spram
     parameter TESTW  = 128          // Width of asic test interface
     )
    (// Memory interface
-    input 		clk, // write clock
-    input 		ce, // chip enable
-    input 		we, // write enable
-    input [DW-1:0] 	wmask, //per bit write mask
-    input [AW-1:0] 	addr,//write address
-    input [DW-1:0] 	din, //write data
-    output [DW-1:0] dout,//read output data
+    input clk, // write clock
+    input ce, // chip enable
+    input we, // write enable
+    input [DW-1:0] wmask, //per bit write mask
+    input [AW-1:0] addr, //write address
+    input [DW-1:0] din, //write data
+    output [DW-1:0] dout, //read output data
     // Power signals
-    input 		vss, // ground signal
-    input 		vdd, // memory core array power
-    input 		vddio, // periphery/io power
+    input vss, // ground signal
+    input vdd, // memory core array power
+    input vddio, // periphery/io power
     // Generic interfaces
-    input [CTRLW-1:0] 	ctrl, // pass through ASIC control interface
-    input [TESTW-1:0] 	test // pass through ASIC test interface
+    input [CTRLW-1:0] ctrl, // pass through ASIC control interface
+    input [TESTW-1:0] test // pass through ASIC test interface
     );
 
     // Determine which memory to select
-    localparam MEM_TYPE = 
+    localparam MEM_TYPE = (TYPE != "DEFAULT") ? TYPE :
       (AW >= 9) ? "gf180mcu_fd_ip_sram__sram512x8m8wm1" :
       (AW == 8) ? "gf180mcu_fd_ip_sram__sram256x8m8wm1" :
       (AW == 7) ? "gf180mcu_fd_ip_sram__sram128x8m8wm1" :
       "gf180mcu_fd_ip_sram__sram64x8m8wm1";
 
     localparam MEM_WIDTH = 
-      (MEM_TYPE == "gf180mcu_fd_ip_sram__sram512x8m8wm1") ? 8 :
-      (MEM_TYPE == "gf180mcu_fd_ip_sram__sram256x8m8wm1") ? 8 :
       (MEM_TYPE == "gf180mcu_fd_ip_sram__sram128x8m8wm1") ? 8 :
+      (MEM_TYPE == "gf180mcu_fd_ip_sram__sram256x8m8wm1") ? 8 :
+      (MEM_TYPE == "gf180mcu_fd_ip_sram__sram512x8m8wm1") ? 8 :
       (MEM_TYPE == "gf180mcu_fd_ip_sram__sram64x8m8wm1") ? 8 :
       0;
  
     localparam MEM_DEPTH = 
-      (MEM_TYPE == "gf180mcu_fd_ip_sram__sram512x8m8wm1") ? 9 :
-      (MEM_TYPE == "gf180mcu_fd_ip_sram__sram256x8m8wm1") ? 8 :
       (MEM_TYPE == "gf180mcu_fd_ip_sram__sram128x8m8wm1") ? 7 :
+      (MEM_TYPE == "gf180mcu_fd_ip_sram__sram256x8m8wm1") ? 8 :
+      (MEM_TYPE == "gf180mcu_fd_ip_sram__sram512x8m8wm1") ? 9 :
       (MEM_TYPE == "gf180mcu_fd_ip_sram__sram64x8m8wm1") ? 6 :
       0;
 
     // Create memories
     localparam MEM_ADDRS = 2**(AW - MEM_DEPTH) < 1 ? 1 : 2**(AW - MEM_DEPTH);
 
+    
+
     generate
       genvar o;
       for (o = 0; o < DW; o = o + 1) begin: OUTPUTS
@@ -111,43 +113,47 @@ module la_spram
           wire we_in;
           assign ce_in = ce && selected;
           assign we_in = we && selected;
-
+          
           if (MEM_TYPE == "gf180mcu_fd_ip_sram__sram512x8m8wm1")
             gf180mcu_fd_ip_sram__sram512x8m8wm1 memory (
-              .CLK(clk),
-              .CEN(~ce_in),
-              .GWEN(~we_in),
-              .WEN(~mem_wmask),
               .A(mem_addr),
+              .CEN(~ce_in),
+              .CLK(clk),
               .D(mem_din),
-              .Q(mem_dout));
+              .GWEN(~we_in),
+              .Q(mem_dout),
+              .WEN(~mem_wmask)
+            );
           else if (MEM_TYPE == "gf180mcu_fd_ip_sram__sram256x8m8wm1")
             gf180mcu_fd_ip_sram__sram256x8m8wm1 memory (
-              .CLK(clk),
-              .CEN(~ce_in),
-              .GWEN(~we_in),
-              .WEN(~mem_wmask),
               .A(mem_addr),
+              .CEN(~ce_in),
+              .CLK(clk),
               .D(mem_din),
-              .Q(mem_dout));
+              .GWEN(~we_in),
+              .Q(mem_dout),
+              .WEN(~mem_wmask)
+            );
           else if (MEM_TYPE == "gf180mcu_fd_ip_sram__sram128x8m8wm1")
             gf180mcu_fd_ip_sram__sram128x8m8wm1 memory (
-              .CLK(clk),
-              .CEN(~ce_in),
-              .GWEN(~we_in),
-              .WEN(~mem_wmask),
               .A(mem_addr),
+              .CEN(~ce_in),
+              .CLK(clk),
               .D(mem_din),
-              .Q(mem_dout));
+              .GWEN(~we_in),
+              .Q(mem_dout),
+              .WEN(~mem_wmask)
+            );
           else if (MEM_TYPE == "gf180mcu_fd_ip_sram__sram64x8m8wm1")
             gf180mcu_fd_ip_sram__sram64x8m8wm1 memory (
-              .CLK(clk),
-              .CEN(~ce_in),
-              .GWEN(~we_in),
-              .WEN(~mem_wmask),
               .A(mem_addr),
+              .CEN(~ce_in),
+              .CLK(clk),
               .D(mem_din),
-              .Q(mem_dout));
+              .GWEN(~we_in),
+              .Q(mem_dout),
+              .WEN(~mem_wmask)
+            );
         end
       end
     endgenerate
diff --git a/lambdapdk/gf180/libs/gf180mcu_fd_ip_sram/lambda/la_spregfile.v b/lambdapdk/gf180/libs/gf180mcu_fd_ip_sram/lambda/la_spregfile.v
index a06a09db..d167168c 100644
--- a/lambdapdk/gf180/libs/gf180mcu_fd_ip_sram/lambda/la_spregfile.v
+++ b/lambdapdk/gf180/libs/gf180mcu_fd_ip_sram/lambda/la_spregfile.v
@@ -1,6 +1,6 @@
 /*****************************************************************************
  * Function: Single Port Register File
- * Copyright: Lambda Project Authors. ALl rights Reserved.
+ * Copyright: Lambda Project Authors. All rights Reserved.
  * License:  MIT (see LICENSE file in Lambda repository)
  *
  * Docs:
@@ -20,50 +20,48 @@
  *
  ****************************************************************************/
 
-module la_spregfile
-  #(parameter DW     = 32,          // Memory width
-    parameter AW     = 10,          // Address width (derived)
-    parameter TYPE   = "DEFAULT",   // Pass through variable for hard macro
-    parameter CTRLW  = 128,         // Width of asic ctrl interface
-    parameter TESTW  = 128          // Width of asic test interface
-    )
-   (// Memory interface
-    input 		clk, // write clock
-    input 		ce, // chip enable
-    input 		we, // write enable
-    input [DW-1:0] 	wmask, //per bit write mask
-    input [AW-1:0] 	addr,//write address
-    input [DW-1:0] 	din, //write data
-    output [DW-1:0]     dout,//read output data
+module la_spregfile #(
+    parameter DW    = 32,         // Memory width
+    parameter AW    = 10,         // Address width (derived)
+    parameter TYPE  = "DEFAULT",  // Pass through variable for hard macro
+    parameter CTRLW = 128,        // Width of asic ctrl interface
+    parameter TESTW = 128         // Width of asic test interface
+) (  // Memory interface
+    input              clk,    // write clock
+    input              ce,     // chip enable
+    input              we,     // write enable
+    input  [   DW-1:0] wmask,  //per bit write mask
+    input  [   AW-1:0] addr,   //write address
+    input  [   DW-1:0] din,    //write data
+    output [   DW-1:0] dout,   //read output data
     // Power signals
-    input 		vss, // ground signal
-    input 		vdd, // memory core array power
-    input 		vddio, // periphery/io power
+    input              vss,    // ground signal
+    input              vdd,    // memory core array power
+    input              vddio,  // periphery/io power
     // Generic interfaces
-    input [CTRLW-1:0] 	ctrl, // pass through ASIC control interface
-    input [TESTW-1:0] 	test // pass through ASIC test interface
-    );
+    input  [CTRLW-1:0] ctrl,   // pass through ASIC control interface
+    input  [TESTW-1:0] test    // pass through ASIC test interface
+);
 
-   la_spram
-   #(.DW(DW),
-     .AW(AW),
-     .TYPE(TYPE),
-     .CTRLW(CTRLW),
-     .TESTW(TESTW)
-     )
-   memory (
-     .clk(clk),
-     .ce(ce),
-     .we(we),
-     .wmask(wmask),
-     .addr(addr),
-     .din(din),
-     .dout(dout),
-     .vss(vss),
-     .vdd(vdd),
-     .vddio(vddio),
-     .ctrl(ctrl),
-     .test(test)
-   );
+    la_spram #(
+        .DW(DW),
+        .AW(AW),
+        .TYPE(TYPE),
+        .CTRLW(CTRLW),
+        .TESTW(TESTW)
+    ) memory (
+        .clk(clk),
+        .ce(ce),
+        .we(we),
+        .wmask(wmask),
+        .addr(addr),
+        .din(din),
+        .dout(dout),
+        .vss(vss),
+        .vdd(vdd),
+        .vddio(vddio),
+        .ctrl(ctrl),
+        .test(test)
+    );
 
 endmodule
diff --git a/lambdapdk/gf180/libs/gf180mcu_fd_ip_sram/lambda/la_syncfifo.v b/lambdapdk/gf180/libs/gf180mcu_fd_ip_sram/lambda/la_syncfifo.v
index bcb4ec2c..6355a26d 100644
--- a/lambdapdk/gf180/libs/gf180mcu_fd_ip_sram/lambda/la_syncfifo.v
+++ b/lambdapdk/gf180/libs/gf180mcu_fd_ip_sram/lambda/la_syncfifo.v
@@ -1,6 +1,6 @@
 /*****************************************************************************
  * Function: Synchronous FIFO
- * Copyright: Lambda Project Authors. ALl rights Reserved.
+ * Copyright: Lambda Project Authors. All rights Reserved.
  * License:  MIT (see LICENSE file in Lambda repository)
  *
  * Docs:
@@ -9,128 +9,112 @@
  *
  ****************************************************************************/
 
-module la_syncfifo
-  #(parameter DW        = 32,       // Memory width
-    parameter DEPTH     = 4,        // FIFO depth
-    parameter NS        = 1,        // Number of power supplies
-    parameter CHAOS     = 1,        // generates random full logic when set
-    parameter CTRLW     = 1,        // width of asic ctrl interface
-    parameter TESTW     = 1,        // width of asic test interface
-    parameter TYPE      = "DEFAULT" // Pass through variable for hard macro
-    )
-   (// common clock, reset, power, ctrl
-    input             clk,
-    input             nreset,
-    input             vss, // ground signal
-    input [NS-1:0]    vdd, // supplies
-    input             chaosmode,// randomly assert fifo full when set
-    input [CTRLW-1:0] ctrl, // pass through ASIC control interface
-    input [TESTW-1:0] test, // pass through ASIC test interface
+module la_syncfifo #(
+    parameter DW    = 32,        // Memory width
+    parameter DEPTH = 4,         // FIFO depth
+    parameter NS    = 1,         // Number of power supplies
+    parameter CHAOS = 1,         // generates random full logic when set
+    parameter CTRLW = 1,         // width of asic ctrl interface
+    parameter TESTW = 1,         // width of asic test interface
+    parameter TYPE  = "DEFAULT"  // Pass through variable for hard macro
+) (  // common clock, reset, power, ctrl
+    input              clk,
+    input              nreset,
+    input              vss,        // ground signal
+    input  [   NS-1:0] vdd,        // supplies
+    input              chaosmode,  // randomly assert fifo full when set
+    input  [CTRLW-1:0] ctrl,       // pass through ASIC control interface
+    input  [TESTW-1:0] test,       // pass through ASIC test interface
     // write input
-    input             wr_en, // write fifo
-    input [DW-1:0]    wr_din, // data to write
-    output            wr_full, // fifo full
+    input              wr_en,      // write fifo
+    input  [   DW-1:0] wr_din,     // data to write
+    output             wr_full,    // fifo full
     // read output
-    input             rd_en, // read fifo
-    output [DW-1:0]   rd_dout, // output data
-    output            rd_empty // fifo is empty
-    );
-
-   // local params
-   parameter AW  = $clog2(DEPTH);
-
-   // local wires
-   reg [AW:0]         wr_addr;
-   wire [AW:0]        wr_addr_nxt;
-   reg [AW:0]         rd_addr;
-   wire [AW:0]        rd_addr_nxt;
-   wire               fifo_read;
-   wire               fifo_write;
-   wire               chaosfull;
-   wire               rd_wrap_around;
-   wire               wr_wrap_around;
-
-   //############################
-   // FIFO Empty/Full
-   //############################
-
-   // support any fifo depth
-   assign wr_full     = (chaosfull & chaosmode) |
-                        {~wr_addr[AW], wr_addr[AW-1:0]} == rd_addr[AW:0];
-
-   assign rd_empty    = wr_addr[AW:0] == rd_addr[AW:0];
-
-   assign fifo_read   = rd_en & ~rd_empty;
-
-   assign fifo_write  = wr_en & ~wr_full;
-
-   //############################
-   // FIFO Pointers - wrap around DEPTH-1
-   //############################
-   assign rd_wrap_around       = rd_addr[AW-1:0] == (DEPTH[AW-1:0]-1'b1);
-   assign wr_wrap_around       = wr_addr[AW-1:0] == (DEPTH[AW-1:0]-1'b1);
-
-   assign rd_addr_nxt[AW]     = rd_wrap_around ? ~rd_addr[AW] : rd_addr[AW];
-   assign rd_addr_nxt[AW-1:0] = rd_wrap_around ? 'b0 : (rd_addr[AW-1:0] + 1);
-
-   assign wr_addr_nxt[AW]     = (wr_addr[AW-1:0] == (DEPTH[AW-1:0]-1'b1)) ? ~wr_addr[AW] : wr_addr[AW];
-   assign wr_addr_nxt[AW-1:0] = (wr_addr[AW-1:0] == (DEPTH[AW-1:0]-1'b1)) ? 'b0 : (wr_addr[AW-1:0] + 1);
-
-   always @ (posedge clk or negedge nreset)
-     if(~nreset)
-       begin
-          wr_addr[AW:0]    <= 'd0;
-          rd_addr[AW:0]    <= 'b0;
-       end
-     else if(fifo_write & fifo_read)
-       begin
-          wr_addr[AW:0] <= wr_addr_nxt[AW:0];
-          rd_addr[AW:0] <= rd_addr_nxt[AW:0];
-       end
-     else if(fifo_write)
-       begin
-          wr_addr[AW:0] <= wr_addr_nxt[AW:0];
-       end
-     else if(fifo_read)
-       begin
-          rd_addr[AW:0] <= rd_addr_nxt[AW:0];
-       end
-
-   //###########################
-   //# Dual Port Memory
-   //###########################
-
-   reg [DW-1:0]         ram[DEPTH-1:0];
-
-   // Write port (FIFO input)
-   always @(posedge clk)
-     if(wr_en & ~wr_full)
-       ram[wr_addr[AW-1:0]] <= wr_din[DW-1:0];
-
-   // Read port (FIFO output)
-   assign rd_dout[DW-1:0] = ram[rd_addr[AW-1:0]];
-
-
-   //############################
-   // Randomly Asserts FIFO full
-   //############################
-
-   generate
-      if (CHAOS)
-        begin
-           // TODO: implement LFSR
-           reg chaosreg;
-           always @ (posedge clk or negedge nreset)
-             if (~nreset)
-               chaosreg <= 1'b0;
-             else
-               chaosreg <= ~chaosreg;
-           assign chaosfull = chaosreg;
+    input              rd_en,      // read fifo
+    output [   DW-1:0] rd_dout,    // output data
+    output             rd_empty    // fifo is empty
+);
+
+    // local params
+    parameter AW = $clog2(DEPTH);
+
+    // local wires
+    reg  [AW:0] wr_addr;
+    wire [AW:0] wr_addr_nxt;
+    reg  [AW:0] rd_addr;
+    wire [AW:0] rd_addr_nxt;
+    wire        fifo_read;
+    wire        fifo_write;
+    wire        chaosfull;
+    wire        rd_wrap_around;
+    wire        wr_wrap_around;
+
+    //############################
+    // FIFO Empty/Full
+    //############################
+
+    // support any fifo depth
+    assign wr_full = (chaosfull & chaosmode) | {~wr_addr[AW], wr_addr[AW-1:0]} == rd_addr[AW:0];
+
+    assign rd_empty = wr_addr[AW:0] == rd_addr[AW:0];
+
+    assign fifo_read = rd_en & ~rd_empty;
+
+    assign fifo_write = wr_en & ~wr_full;
+
+    //############################
+    // FIFO Pointers - wrap around DEPTH-1
+    //############################
+    assign rd_wrap_around = rd_addr[AW-1:0] == (DEPTH[AW-1:0] - 1'b1);
+    assign wr_wrap_around = wr_addr[AW-1:0] == (DEPTH[AW-1:0] - 1'b1);
+
+    assign rd_addr_nxt[AW] = rd_wrap_around ? ~rd_addr[AW] : rd_addr[AW];
+    assign rd_addr_nxt[AW-1:0] = rd_wrap_around ? 'b0 : (rd_addr[AW-1:0] + 1);
+
+    assign wr_addr_nxt[AW]     = (wr_addr[AW-1:0] == (DEPTH[AW-1:0]-1'b1)) ? ~wr_addr[AW] : wr_addr[AW];
+    assign wr_addr_nxt[AW-1:0] = (wr_addr[AW-1:0] == (DEPTH[AW-1:0]-1'b1)) ? 'b0 : (wr_addr[AW-1:0] + 1);
+
+    always @(posedge clk or negedge nreset)
+        if (~nreset) begin
+            wr_addr[AW:0] <= 'd0;
+            rd_addr[AW:0] <= 'b0;
+        end else if (fifo_write & fifo_read) begin
+            wr_addr[AW:0] <= wr_addr_nxt[AW:0];
+            rd_addr[AW:0] <= rd_addr_nxt[AW:0];
+        end else if (fifo_write) begin
+            wr_addr[AW:0] <= wr_addr_nxt[AW:0];
+        end else if (fifo_read) begin
+            rd_addr[AW:0] <= rd_addr_nxt[AW:0];
         end
-      else
-        begin
-           assign chaosfull = 1'b0;
+
+    //###########################
+    //# Dual Port Memory
+    //###########################
+
+    reg [DW-1:0] ram[DEPTH-1:0];
+
+    // Write port (FIFO input)
+    always @(posedge clk) if (wr_en & ~wr_full) ram[wr_addr[AW-1:0]] <= wr_din[DW-1:0];
+
+    // Read port (FIFO output)
+    assign rd_dout[DW-1:0] = ram[rd_addr[AW-1:0]];
+
+
+    //############################
+    // Randomly Asserts FIFO full
+    //############################
+
+    generate
+        if (CHAOS) begin
+            // TODO: implement LFSR
+            reg chaosreg;
+            always @(posedge clk or negedge nreset)
+                if (~nreset) chaosreg <= 1'b0;
+                else chaosreg <= ~chaosreg;
+            assign chaosfull = chaosreg;
+        end else begin
+            assign chaosfull = 1'b0;
         end
-   endgenerate
+    endgenerate
 
 endmodule
diff --git a/lambdapdk/sky130/libs/sky130io/lambda/la_ioanalog.v b/lambdapdk/sky130/libs/sky130io/lambda/la_ioanalog.v
index 909d44bb..2eede91b 100644
--- a/lambdapdk/sky130/libs/sky130io/lambda/la_ioanalog.v
+++ b/lambdapdk/sky130/libs/sky130io/lambda/la_ioanalog.v
@@ -1,6 +1,6 @@
 /*****************************************************************************
  * Function: IO analog pass-through cell
- * Copyright: Lambda Project Authors. ALl rights Reserved.
+ * Copyright: Lambda Project Authors. All rights Reserved.
  * License:  MIT (see LICENSE file in Lambda repository)
  *
  * Docs:
@@ -10,34 +10,32 @@
  * aio[2] = big series resistance
  *
  ****************************************************************************/
-module la_ioanalog
-  #(
-    parameter TYPE = "DEFAULT", // cell type
-    parameter SIDE  = "NO",     // "NO", "SO", "EA", "WE"
-    parameter RINGW =  8        // width of io ring
-    )
-   (// io pad signals
-    inout 	      pad, // bidirectional pad signal
-    inout 	      vdd, // core supply
-    inout 	      vss, // core ground
-    inout 	      vddio, // io supply
-    inout 	      vssio, // io ground
-    inout [RINGW-1:0] ioring, // generic io-ring interface
+module la_ioanalog #(
+    parameter TYPE  = "DEFAULT",  // cell type
+    parameter SIDE  = "NO",       // "NO", "SO", "EA", "WE"
+    parameter RINGW = 8           // width of io ring
+) (  // io pad signals
+    inout             pad,     // bidirectional pad signal
+    inout             vdd,     // core supply
+    inout             vss,     // core ground
+    inout             vddio,   // io supply
+    inout             vssio,   // io ground
+    inout [RINGW-1:0] ioring,  // generic io-ring interface
     // core interface
-    inout [2:0]       aio // analog core signal
-    );
+    inout [      2:0] aio      // analog core signal
+);
 
 
 `ifdef VERILATOR
-   // TODO!: input only for verilator bases simulation
-   assign aio[0] = pad;
-   assign aio[1] = pad;
-   assign aio[2] = pad;
+    // TODO!: input only for verilator bases simulation
+    assign aio[0] = pad;
+    assign aio[1] = pad;
+    assign aio[2] = pad;
 
 `else
-   tran t0(pad, aio[0]);
-   tran t1(pad, aio[1]);
-   tran t2(pad, aio[2]);
+    tran t0 (pad, aio[0]);
+    tran t1 (pad, aio[1]);
+    tran t2 (pad, aio[2]);
 `endif
 
 endmodule
diff --git a/lambdapdk/sky130/libs/sky130io/lambda/la_ioclamp.v b/lambdapdk/sky130/libs/sky130io/lambda/la_ioclamp.v
index f488febc..6adbf9b1 100644
--- a/lambdapdk/sky130/libs/sky130io/lambda/la_ioclamp.v
+++ b/lambdapdk/sky130/libs/sky130io/lambda/la_ioclamp.v
@@ -1,23 +1,21 @@
 /*****************************************************************************
  * Function: IO ESD clamp cell
- * Copyright: Lambda Project Authors. ALl rights Reserved.
+ * Copyright: Lambda Project Authors. All rights Reserved.
  * License:  MIT (see LICENSE file in Lambda repository)
  *
  * Docs:
  *
  ****************************************************************************/
-module la_ioclamp
-  #(
-    parameter TYPE  = "DEFAULT", // cell type
-    parameter SIDE  = "NO",      // "NO", "SO", "EA", "WE"
-    parameter RINGW =  8         // width of io ring
-    )
-   (// io pad signals
-    inout 	      vdd, // core supply
-    inout 	      vss, // core ground
-    inout 	      vddio, // io supply
-    inout 	      vssio, // io ground
-    inout [RINGW-1:0] ioring // generic io-ring interface
-    );
+module la_ioclamp #(
+    parameter TYPE  = "DEFAULT",  // cell type
+    parameter SIDE  = "NO",       // "NO", "SO", "EA", "WE"
+    parameter RINGW = 8           // width of io ring
+) (  // io pad signals
+    inout             vdd,    // core supply
+    inout             vss,    // core ground
+    inout             vddio,  // io supply
+    inout             vssio,  // io ground
+    inout [RINGW-1:0] ioring  // generic io-ring interface
+);
 
 endmodule
diff --git a/lambdapdk/sky130/libs/sky130io/lambda/la_ioinput.v b/lambdapdk/sky130/libs/sky130io/lambda/la_ioinput.v
index ed0aea68..05425b9b 100644
--- a/lambdapdk/sky130/libs/sky130io/lambda/la_ioinput.v
+++ b/lambdapdk/sky130/libs/sky130io/lambda/la_ioinput.v
@@ -1,6 +1,6 @@
 /*****************************************************************************
  * Function: IO bi-directional buffer
- * Copyright: Lambda Project Authors. ALl rights Reserved.
+ * Copyright: Lambda Project Authors. All rights Reserved.
  * License:  MIT (see LICENSE file in Lambda repository)
  *
  * Docs:
@@ -14,27 +14,25 @@
  * different IP cells for the placing cells vvertically or horizontally.
  *
  ****************************************************************************/
-module la_ioinput
-  #(
-    parameter TYPE  = "DEFAULT", // cell type
-    parameter SIDE  = "NO",      // "NO", "SO", "EA", "WE"
-    parameter CFGW  =  16,       // width of core config bus
-    parameter RINGW =  8         // width of io ring
-    )
-   (// io pad signals
-    inout 	      pad, // bidirectional pad signal
-    inout 	      vdd, // core supply
-    inout 	      vss, // core ground
-    inout 	      vddio, // io supply
-    inout 	      vssio, // io ground
+module la_ioinput #(
+    parameter TYPE  = "DEFAULT",  // cell type
+    parameter SIDE  = "NO",       // "NO", "SO", "EA", "WE"
+    parameter CFGW  = 16,         // width of core config bus
+    parameter RINGW = 8           // width of io ring
+) (  // io pad signals
+    inout              pad,     // bidirectional pad signal
+    inout              vdd,     // core supply
+    inout              vss,     // core ground
+    inout              vddio,   // io supply
+    inout              vssio,   // io ground
     // core facing signals
-    output 	      z, // output to core
-    input 	      ie, // input enable, 1 = active
-    inout [RINGW-1:0] ioring, // generic io-ring interface
-    input [CFGW-1:0]  cfg // generic config interface
-    );
+    output             z,       // output to core
+    input              ie,      // input enable, 1 = active
+    inout  [RINGW-1:0] ioring,  // generic io-ring interface
+    input  [ CFGW-1:0] cfg      // generic config interface
+);
 
-   // to core
-   assign z   = ie ? pad : 1'b0;
+    // to core
+    assign z = ie ? pad : 1'b0;
 
 endmodule
diff --git a/lambdapdk/sky130/libs/sky130io/lambda/la_ioshort.v b/lambdapdk/sky130/libs/sky130io/lambda/la_ioshort.v
index 94b228a2..6341cf87 100644
--- a/lambdapdk/sky130/libs/sky130io/lambda/la_ioshort.v
+++ b/lambdapdk/sky130/libs/sky130io/lambda/la_ioshort.v
@@ -1,6 +1,6 @@
 /*****************************************************************************
  * Function: Shorting two wires together
- * Copyright: Lambda Project Authors. ALl rights Reserved.
+ * Copyright: Lambda Project Authors. All rights Reserved.
  * License:  MIT (see LICENSE file in Lambda repository)
  *
  * Docs:
@@ -11,20 +11,24 @@
  * connection in RTL.
  *
  ****************************************************************************/
-module la_ioshort
-  (
-   inout a,
-   inout b,
-   input a2b
-   );
+module la_ioshort (
+    inout a,
+    inout b,
+    input a2b
+);
 
 `ifdef VERILATOR
-   // Using direction to break the loop
-   assign a = ~a2b ? b : 1'bz;
-   assign b = a2b  ? a : 1'bz;
+    // Using direction to break the loop
+    assign a = ~a2b ? b : 1'bz;
+    assign b = a2b ? a : 1'bz;
 `else
-   // single port pass through short/hack
-   la_pt la_pt(a,b);
+    // single port pass through short/hack
+    // verilog_lint: waive-start module-port
+    la_pt la_pt (
+        a,
+        b
+    );
+    // verilog_lint: waive-end module-port
 `endif
 
-endmodule // la_ioshort
+endmodule  // la_ioshort
diff --git a/lambdapdk/sky130/libs/sky130io/lambda/la_iovdda.v b/lambdapdk/sky130/libs/sky130io/lambda/la_iovdda.v
index 4a04f423..8b433c27 100644
--- a/lambdapdk/sky130/libs/sky130io/lambda/la_iovdda.v
+++ b/lambdapdk/sky130/libs/sky130io/lambda/la_iovdda.v
@@ -1,24 +1,22 @@
 /*****************************************************************************
  * Function: IO supply cell (vdda)
- * Copyright: Lambda Project Authors. ALl rights Reserved.
+ * Copyright: Lambda Project Authors. All rights Reserved.
  * License:  MIT (see LICENSE file in Lambda repository)
  *
  * Docs:
  *
  *
  ****************************************************************************/
-module la_iovdda
-  #(
-    parameter TYPE  = "DEFAULT", // cell type
-    parameter SIDE  = "NO",      // "NO", "SO", "EA", "WE"
-    parameter RINGW =  8         // width of io ring
-    )
-   (
-    inout 	      vdd, // core supply
-    inout 	      vss, // core ground
-    inout 	      vddio, // io supply
-    inout 	      vssio, // io ground
-    inout [RINGW-1:0] ioring // generic io-ring interface
-    );
+module la_iovdda #(
+    parameter TYPE  = "DEFAULT",  // cell type
+    parameter SIDE  = "NO",       // "NO", "SO", "EA", "WE"
+    parameter RINGW = 8           // width of io ring
+) (
+    inout             vdd,    // core supply
+    inout             vss,    // core ground
+    inout             vddio,  // io supply
+    inout             vssio,  // io ground
+    inout [RINGW-1:0] ioring  // generic io-ring interface
+);
 
 endmodule
diff --git a/lambdapdk/sky130/libs/sky130io/lambda/la_iovssa.v b/lambdapdk/sky130/libs/sky130io/lambda/la_iovssa.v
index 9904bb09..bf43c55b 100644
--- a/lambdapdk/sky130/libs/sky130io/lambda/la_iovssa.v
+++ b/lambdapdk/sky130/libs/sky130io/lambda/la_iovssa.v
@@ -1,24 +1,22 @@
 /*****************************************************************************
  * Function: IO supply cell (vssa)
- * Copyright: Lambda Project Authors. ALl rights Reserved.
+ * Copyright: Lambda Project Authors. All rights Reserved.
  * License:  MIT (see LICENSE file in Lambda repository)
  *
  * Docs:
  *
  *
  ****************************************************************************/
-module la_iovssa
-  #(
-    parameter TYPE  = "DEFAULT", // cell type
-    parameter SIDE  = "NO",      // "NO", "SO", "EA", "WE"
-    parameter RINGW =  8         // width of io ring
-    )
-   (
-    inout 	      vdd, // core supply
-    inout 	      vss, // core ground
-    inout 	      vddio, // io supply
-    inout 	      vssio, // io ground
-    inout [RINGW-1:0] ioring // generic io-ring interface
-    );
+module la_iovssa #(
+    parameter TYPE  = "DEFAULT",  // cell type
+    parameter SIDE  = "NO",       // "NO", "SO", "EA", "WE"
+    parameter RINGW = 8           // width of io ring
+) (
+    inout             vdd,    // core supply
+    inout             vss,    // core ground
+    inout             vddio,  // io supply
+    inout             vssio,  // io ground
+    inout [RINGW-1:0] ioring  // generic io-ring interface
+);
 
 endmodule
diff --git a/lambdapdk/sky130/libs/sky130io/lambda/la_ioxtal.v b/lambdapdk/sky130/libs/sky130io/lambda/la_ioxtal.v
index 71bece5e..91c7b9e2 100644
--- a/lambdapdk/sky130/libs/sky130io/lambda/la_ioxtal.v
+++ b/lambdapdk/sky130/libs/sky130io/lambda/la_ioxtal.v
@@ -1,29 +1,27 @@
 /*****************************************************************************
  * Function: IO xtal oscillator cell
- * Copyright: Lambda Project Authors. ALl rights Reserved.
+ * Copyright: Lambda Project Authors. All rights Reserved.
  * License:  MIT (see LICENSE file in Lambda repository)
  *
  * Docs:
  *
  ****************************************************************************/
-module la_ioxtal
-  #(
-    parameter TYPE = "DEFAULT", // cell type
-    parameter SIDE  = "NO",     // "NO", "SO", "EA", "WE"
-    parameter CFGW  =  16,       // width of core config bus
-    parameter RINGW =  8        // width of io ring
-    )
-   (// io pad signals
-    inout 	      padi, // xtal input pad
-    inout 	      pado, // xtal output pad
-    inout 	      vdd, // core supply
-    inout 	      vss, // core ground
-    inout 	      vddio, // io supply
-    inout 	      vssio, // io ground
-    inout [RINGW-1:0] ioring, // generic io-ring interface
-    input [CFGW-1:0]  cfg, // generic config interface
+module la_ioxtal #(
+    parameter TYPE  = "DEFAULT",  // cell type
+    parameter SIDE  = "NO",       // "NO", "SO", "EA", "WE"
+    parameter CFGW  = 16,         // width of core config bus
+    parameter RINGW = 8           // width of io ring
+) (  // io pad signals
+    inout              padi,    // xtal input pad
+    inout              pado,    // xtal output pad
+    inout              vdd,     // core supply
+    inout              vss,     // core ground
+    inout              vddio,   // io supply
+    inout              vssio,   // io ground
+    inout  [RINGW-1:0] ioring,  // generic io-ring interface
+    input  [ CFGW-1:0] cfg,     // generic config interface
     // core interface
-    output 	      z // clock output to core
-    );
+    output             z        // clock output to core
+);
 
 endmodule
diff --git a/lambdapdk/sky130/libs/sky130io/lambda/la_pt.v b/lambdapdk/sky130/libs/sky130io/lambda/la_pt.v
index f14916af..7e3b432c 100644
--- a/lambdapdk/sky130/libs/sky130io/lambda/la_pt.v
+++ b/lambdapdk/sky130/libs/sky130io/lambda/la_pt.v
@@ -1,8 +1,11 @@
 
 //Solution to the short was found at the end of a conversation thread at this
-//link: 
+//link:
 //https://groups.google.com/g/comp.lang.verilog/c/b3-6XMA8KA4
-//-PG 10/31/2022
-module la_pt(.io1(a),.io2(a));
-   inout wire a;
-endmodule // la_pt
+
+module la_pt (
+    .io1(a),
+    .io2(a)
+);
+    inout wire a;
+endmodule  // la_pt
diff --git a/lambdapdk/sky130/libs/sky130sram/lambda/la_asyncfifo.v b/lambdapdk/sky130/libs/sky130sram/lambda/la_asyncfifo.v
index e865f73c..3d37a974 100644
--- a/lambdapdk/sky130/libs/sky130sram/lambda/la_asyncfifo.v
+++ b/lambdapdk/sky130/libs/sky130sram/lambda/la_asyncfifo.v
@@ -1,6 +1,6 @@
 /*****************************************************************************
  * Function: Dual Clock Asynchronous FIFO
- * Copyright: Lambda Project Authors. ALl rights Reserved.
+ * Copyright: Lambda Project Authors. All rights Reserved.
  * License:  MIT (see LICENSE file in Lambda repository)
  *
  * Docs:
@@ -20,192 +20,176 @@
  *
  ****************************************************************************/
 
-module la_asyncfifo
-  #(parameter DW        = 32,       // Memory width
-    parameter DEPTH     = 4,        // FIFO depth
-    parameter NS        = 1,        // Number of power supplies
-    parameter CTRLW     = 1,        // width of asic ctrl interface
-    parameter TESTW     = 1,        // width of asic teset interface
-    parameter CHAOS     = 0,        // generates random full logic when set
-    parameter TYPE      = "DEFAULT" // Pass through variable for hard macro
-    )
-   (// write port
-    input             wr_clk,
-    input             wr_nreset,
-    input [DW-1:0]    wr_din, // data to write
-    input             wr_en, // write fifo
-    input             wr_chaosmode,// randomly assert fifo full when set
-    output reg        wr_full, // fifo full
+module la_asyncfifo #(
+    parameter DW    = 32,        // Memory width
+    parameter DEPTH = 4,         // FIFO depth
+    parameter NS    = 1,         // Number of power supplies
+    parameter CTRLW = 1,         // width of asic ctrl interface
+    parameter TESTW = 1,         // width of asic teset interface
+    parameter CHAOS = 0,         // generates random full logic when set
+    parameter TYPE  = "DEFAULT"  // Pass through variable for hard macro
+) (  // write port
+    input                  wr_clk,
+    input                  wr_nreset,
+    input      [   DW-1:0] wr_din,        // data to write
+    input                  wr_en,         // write fifo
+    input                  wr_chaosmode,  // randomly assert fifo full when set
+    output reg             wr_full,       // fifo full
     // read port
-    input             rd_clk,
-    input             rd_nreset,
-    output [DW-1:0]   rd_dout, // output data (next cycle)
-    input             rd_en, // read fifo
-    output reg        rd_empty, // fifo is empty
+    input                  rd_clk,
+    input                  rd_nreset,
+    output     [   DW-1:0] rd_dout,       // output data (next cycle)
+    input                  rd_en,         // read fifo
+    output reg             rd_empty,      // fifo is empty
     // Power signals
-    input             vss, // ground signal
-    input [NS-1:0]    vdd, // supplies
+    input                  vss,           // ground signal
+    input      [   NS-1:0] vdd,           // supplies
     // Generic interfaces
-    input [CTRLW-1:0] ctrl, // pass through ASIC control interface
-    input [TESTW-1:0] test // pass through ASIC test interface
-    );
-
-   // local params
-   // The last part is to support DEPTH of 1
-   localparam AW  = $clog2(DEPTH) + {31'h0,(DEPTH == 1)};
-
-   // local wires
-   reg [AW:0]     wr_grayptr;
-   reg [AW:0]     wr_binptr;
-   reg [AW:0]     wr_binptr_mem;
-   wire [AW:0]    wr_grayptr_nxt;
-   wire [AW:0]    wr_binptr_nxt;
-   wire [AW:0]    wr_binptr_mem_nxt;
-   wire [AW:0]    wr_grayptr_sync;
-   wire           wr_chaosfull;
-
-   reg [AW:0]     rd_grayptr;
-   reg [AW:0]     rd_binptr;
-   reg [AW:0]     rd_binptr_mem;
-   wire [AW:0]    rd_grayptr_nxt;
-   wire [AW:0]    rd_binptr_nxt;
-   wire [AW:0]    rd_binptr_mem_nxt;
-   wire [AW:0]    rd_grayptr_sync;
-
-   genvar         i;
-
-   //###########################
-   //# WRITE SIDE LOGIC
-   //###########################
-
-   always @ ( posedge wr_clk or negedge wr_nreset)
-     if(~wr_nreset)
-       begin
-          wr_binptr_mem[AW:0] <= 'b0;
-          wr_binptr[AW:0]     <= 'b0;
-          wr_grayptr[AW:0]    <= 'b0;
-       end
-     else
-       begin
-          wr_binptr_mem[AW:0] <= (wr_binptr_mem_nxt[AW:0] == DEPTH) ? 'b0 : wr_binptr_mem_nxt[AW:0];
-          wr_binptr[AW:0]     <= wr_binptr_nxt[AW:0];
-          wr_grayptr[AW:0]    <= wr_grayptr_nxt[AW:0];
-       end
-
-   // Update binary pointer on write and not full
-   assign wr_binptr_mem_nxt[AW:0] = wr_binptr_mem[AW-1:0] + {{(AW-1){1'b0}}, (wr_en && ~wr_full)};
-   assign wr_binptr_nxt[AW:0]     = wr_binptr[AW:0] + {{AW{1'b0}}, (wr_en && ~wr_full)};
-
-   // Convert binary point to gray pointer for sync
-   assign wr_grayptr_nxt[AW:0] =  wr_binptr_nxt[AW:0] ^ {1'b0, wr_binptr_nxt[AW:1]};
-
-   // Full comparison (gray pointer based)
-   // Amir - add support for fifo DEPTH that is not power of 2
-   // Note - the previous logic also had a bug that full was high one entry to soon
-
-   reg [AW:0] rd_binptr_sync;
-   wire [AW:0] fifo_used;
-   integer j;
-
-   always @(*)
-     begin
+    input      [CTRLW-1:0] ctrl,          // pass through ASIC control interface
+    input      [TESTW-1:0] test           // pass through ASIC test interface
+);
+
+    // local params
+    // The last part is to support DEPTH of 1
+    localparam AW = $clog2(DEPTH) + {31'h0, (DEPTH == 1)};
+
+    // local wires
+    reg  [AW:0] wr_grayptr;
+    reg  [AW:0] wr_binptr;
+    reg  [AW:0] wr_binptr_mem;
+    wire [AW:0] wr_grayptr_nxt;
+    wire [AW:0] wr_binptr_nxt;
+    wire [AW:0] wr_binptr_mem_nxt;
+    wire [AW:0] wr_grayptr_sync;
+    wire        wr_chaosfull;
+
+    reg  [AW:0] rd_grayptr;
+    reg  [AW:0] rd_binptr;
+    reg  [AW:0] rd_binptr_mem;
+    wire [AW:0] rd_grayptr_nxt;
+    wire [AW:0] rd_binptr_nxt;
+    wire [AW:0] rd_binptr_mem_nxt;
+    wire [AW:0] rd_grayptr_sync;
+
+    genvar i;
+
+    //###########################
+    //# WRITE SIDE LOGIC
+    //###########################
+
+    always @(posedge wr_clk or negedge wr_nreset)
+        if (~wr_nreset) begin
+            wr_binptr_mem[AW:0] <= 'b0;
+            wr_binptr[AW:0]     <= 'b0;
+            wr_grayptr[AW:0]    <= 'b0;
+        end else begin
+            wr_binptr_mem[AW:0] <= (wr_binptr_mem_nxt[AW:0] == DEPTH) ? 'b0 : wr_binptr_mem_nxt[AW:0];
+            wr_binptr[AW:0] <= wr_binptr_nxt[AW:0];
+            wr_grayptr[AW:0] <= wr_grayptr_nxt[AW:0];
+        end
+
+    // Update binary pointer on write and not full
+    assign wr_binptr_mem_nxt[AW:0] = wr_binptr_mem[AW-1:0] + {{(AW-1){1'b0}}, (wr_en && ~wr_full)};
+    assign wr_binptr_nxt[AW:0] = wr_binptr[AW:0] + {{AW{1'b0}}, (wr_en && ~wr_full)};
+
+    // Convert binary point to gray pointer for sync
+    assign wr_grayptr_nxt[AW:0] = wr_binptr_nxt[AW:0] ^ {1'b0, wr_binptr_nxt[AW:1]};
+
+    // Full comparison (gray pointer based)
+    // Amir - add support for fifo DEPTH that is not power of 2
+    // Note - the previous logic also had a bug that full was high one entry to soon
+
+    reg [AW:0] rd_binptr_sync;
+    wire [AW:0] fifo_used;
+    integer j;
+
+    always @(*) begin
         rd_binptr_sync[AW] = rd_grayptr_sync[AW];
-        for (j=AW;j>0;j=j-1)
-          rd_binptr_sync[j-1] = rd_binptr_sync[j] ^ rd_grayptr_sync[j-1];
-     end
+        for (j = AW; j > 0; j = j - 1)
+        rd_binptr_sync[j-1] = rd_binptr_sync[j] ^ rd_grayptr_sync[j-1];
+    end
 
-   assign fifo_used = wr_binptr - rd_binptr_sync;
+    assign fifo_used = wr_binptr - rd_binptr_sync;
 
-   always @ (posedge wr_clk or negedge wr_nreset)
-     if (~wr_nreset)
-       wr_full <= 1'b0;
-     else
-       wr_full <= (wr_chaosfull & wr_chaosmode) |
+    always @(posedge wr_clk or negedge wr_nreset)
+        if (~wr_nreset) wr_full <= 1'b0;
+        else
+            wr_full <= (wr_chaosfull & wr_chaosmode) |
                   (fifo_used + {{AW{1'b0}}, (wr_en && ~wr_full)}) == DEPTH;
 
-   // Write --> Read clock synchronizer
-   for (i=0;i<(AW+1);i=i+1)
-     begin
-        la_drsync wrsync(.out(wr_grayptr_sync[i]),
-                         .clk(rd_clk),
-                         .nreset(rd_nreset),
-                         .in(wr_grayptr[i]));
-     end
-
-   //###########################
-   //# READ SIDE LOGIC
-   //###########################
-
-   always @ ( posedge rd_clk or negedge rd_nreset)
-     if(~rd_nreset)
-       begin
-          rd_binptr_mem[AW:0] <= 'b0;
-          rd_binptr[AW:0]     <= 'b0;
-          rd_grayptr[AW:0]    <= 'b0;
-       end
-     else
-       begin
-          rd_binptr_mem[AW:0] <= (rd_binptr_mem_nxt[AW:0] == DEPTH) ? 'b0 : rd_binptr_mem_nxt[AW:0];
-          rd_binptr[AW:0]  <= rd_binptr_nxt[AW:0];
-          rd_grayptr[AW:0] <= rd_grayptr_nxt[AW:0];
-       end
-
-   assign rd_binptr_mem_nxt[AW:0] = rd_binptr_mem[AW-1:0] + {{(AW-1){1'b0}}, (rd_en && ~rd_empty)};
-   assign rd_binptr_nxt[AW:0]     = rd_binptr[AW:0] + {{AW{1'b0}}, (rd_en && ~rd_empty)};
-   assign rd_grayptr_nxt[AW:0]    = rd_binptr_nxt[AW:0] ^ {1'b0, rd_binptr_nxt[AW:1]};
-
-   // Full comparison (gray pointer based)
-   always @ (posedge rd_clk or negedge rd_nreset)
-     if (~rd_nreset)
-       rd_empty <= 1'b1;
-     else
-       rd_empty <= (rd_grayptr_nxt[AW:0] == wr_grayptr_sync[AW:0]);
-
-   // Read --> write clock synchronizer
-   for (i=0;i<(AW+1);i=i+1)
-     begin
-        la_drsync rdsync(.out(rd_grayptr_sync[i]),
-                         .clk(wr_clk),
-                         .nreset(wr_nreset),
-                         .in(rd_grayptr[i]));
-     end
-
-   //###########################
-   //# Dual Port Memory
-   //###########################
-
-   reg [DW-1:0]         ram[DEPTH-1:0];
-
-   // Write port (FIFO input)
-   always @(posedge wr_clk)
-     if(wr_en & ~wr_full)
-       ram[wr_binptr_mem[AW-1:0]] <= wr_din[DW-1:0];
-
-   // Read port (FIFO output)
-   assign rd_dout[DW-1:0] = ram[rd_binptr_mem[AW-1:0]];
-
-   //############################
-   // Randomly Asserts FIFO full
-   //############################
-
-   generate
-      if (CHAOS)
-        begin
-           // TODO: implement LFSR
-           reg chaosreg;
-           always @ (posedge wr_clk or negedge wr_nreset)
-             if (~wr_nreset)
-               chaosreg <= 1'b0;
-             else
-               chaosreg <= ~chaosreg;
-           assign wr_chaosfull = chaosreg;
+    // Write --> Read clock synchronizer
+    for (i = 0; i < (AW + 1); i = i + 1) begin
+        la_drsync wrsync (
+            .out(wr_grayptr_sync[i]),
+            .clk(rd_clk),
+            .nreset(rd_nreset),
+            .in(wr_grayptr[i])
+        );
+    end
+
+    //###########################
+    //# READ SIDE LOGIC
+    //###########################
+
+    always @(posedge rd_clk or negedge rd_nreset)
+        if (~rd_nreset) begin
+            rd_binptr_mem[AW:0] <= 'b0;
+            rd_binptr[AW:0]     <= 'b0;
+            rd_grayptr[AW:0]    <= 'b0;
+        end else begin
+            rd_binptr_mem[AW:0] <= (rd_binptr_mem_nxt[AW:0] == DEPTH) ? 'b0 : rd_binptr_mem_nxt[AW:0];
+            rd_binptr[AW:0] <= rd_binptr_nxt[AW:0];
+            rd_grayptr[AW:0] <= rd_grayptr_nxt[AW:0];
         end
-      else
-        begin
-           assign wr_chaosfull = 1'b0;
+
+    assign rd_binptr_mem_nxt[AW:0] = rd_binptr_mem[AW-1:0] + {{(AW-1){1'b0}}, (rd_en && ~rd_empty)};
+    assign rd_binptr_nxt[AW:0] = rd_binptr[AW:0] + {{AW{1'b0}}, (rd_en && ~rd_empty)};
+    assign rd_grayptr_nxt[AW:0] = rd_binptr_nxt[AW:0] ^ {1'b0, rd_binptr_nxt[AW:1]};
+
+    // Full comparison (gray pointer based)
+    always @(posedge rd_clk or negedge rd_nreset)
+        if (~rd_nreset) rd_empty <= 1'b1;
+        else rd_empty <= (rd_grayptr_nxt[AW:0] == wr_grayptr_sync[AW:0]);
+
+    // Read --> write clock synchronizer
+    for (i = 0; i < (AW + 1); i = i + 1) begin
+        la_drsync rdsync (
+            .out(rd_grayptr_sync[i]),
+            .clk(wr_clk),
+            .nreset(wr_nreset),
+            .in(rd_grayptr[i])
+        );
+    end
+
+    //###########################
+    //# Dual Port Memory
+    //###########################
+
+    reg [DW-1:0] ram[DEPTH-1:0];
+
+    // Write port (FIFO input)
+    always @(posedge wr_clk) if (wr_en & ~wr_full) ram[wr_binptr_mem[AW-1:0]] <= wr_din[DW-1:0];
+
+    // Read port (FIFO output)
+    assign rd_dout[DW-1:0] = ram[rd_binptr_mem[AW-1:0]];
+
+    //############################
+    // Randomly Asserts FIFO full
+    //############################
+
+    generate
+        if (CHAOS) begin
+            // TODO: implement LFSR
+            reg chaosreg;
+            always @(posedge wr_clk or negedge wr_nreset)
+                if (~wr_nreset) chaosreg <= 1'b0;
+                else chaosreg <= ~chaosreg;
+            assign wr_chaosfull = chaosreg;
+        end else begin
+            assign wr_chaosfull = 1'b0;
         end
 
-   endgenerate
+    endgenerate
 
 
 endmodule
diff --git a/lambdapdk/sky130/libs/sky130sram/lambda/la_dpram.v b/lambdapdk/sky130/libs/sky130sram/lambda/la_dpram.v
index 8e46ebb7..129ef424 100644
--- a/lambdapdk/sky130/libs/sky130sram/lambda/la_dpram.v
+++ b/lambdapdk/sky130/libs/sky130sram/lambda/la_dpram.v
@@ -1,6 +1,6 @@
 /*****************************************************************************
  * Function: Dual Port RAM (One write port + One read port)
- * Copyright: Lambda Project Authors. ALl rights Reserved.
+ * Copyright: Lambda Project Authors. All rights Reserved.
  * License:  MIT (see LICENSE file in Lambda repository)
  *
  * Docs:
@@ -20,47 +20,43 @@
  *
  ****************************************************************************/
 
-module la_dpram
-  #(parameter DW     = 32,        // Memory width
-    parameter AW     = 10,        // address width (derived)
-    parameter TYPE   = "DEFAULT", // pass through variable for hard macro
-    parameter CTRLW  = 128,       // width of asic ctrl interface
-    parameter TESTW  = 128        // width of asic test interface
-    )
-   (// Write port
-    input 		wr_clk, // write clock
-    input 		wr_ce, // write chip-enable
-    input 		wr_we, // write enable
-    input [DW-1:0] 	wr_wmask, // write mask
-    input [AW-1:0] 	wr_addr, // write address
-    input [DW-1:0] 	wr_din, //write data in
+module la_dpram #(
+    parameter DW    = 32,         // Memory width
+    parameter AW    = 10,         // address width (derived)
+    parameter TYPE  = "DEFAULT",  // pass through variable for hard macro
+    parameter CTRLW = 128,        // width of asic ctrl interface
+    parameter TESTW = 128         // width of asic test interface
+) (  // Write port
+    input wr_clk,  // write clock
+    input wr_ce,  // write chip-enable
+    input wr_we,  // write enable
+    input [DW-1:0] wr_wmask,  // write mask
+    input [AW-1:0] wr_addr,  // write address
+    input [DW-1:0] wr_din,  //write data in
     // Read port
-    input 		rd_clk, // read clock
-    input 		rd_ce, // read chip-enable
-    input [AW-1:0] 	rd_addr, // read address
-    output reg [DW-1:0] rd_dout, //read data out
+    input rd_clk,  // read clock
+    input rd_ce,  // read chip-enable
+    input [AW-1:0] rd_addr,  // read address
+    output reg [DW-1:0] rd_dout,  //read data out
     // Power signal
-    input 		vss, // ground signal
-    input 		vdd, // memory core array power
-    input 		vddio, // periphery/io power
+    input vss,  // ground signal
+    input vdd,  // memory core array power
+    input vddio,  // periphery/io power
     // Generic interfaces
-    input [CTRLW-1:0] 	ctrl, // pass through ASIC control interface
-    input [TESTW-1:0] 	test // pass through ASIC test interface
-    );
+    input [CTRLW-1:0] ctrl,  // pass through ASIC control interface
+    input [TESTW-1:0] test  // pass through ASIC test interface
+);
 
-   // Generic RTL RAM
-   reg [DW-1:0]       ram[(2**AW)-1:0];
-   integer 	      i;
+    // Generic RTL RAM
+    reg     [DW-1:0] ram[(2**AW)-1:0];
+    integer          i;
 
-   // Write port
-   always @(posedge wr_clk)
-     for (i=0;i<DW;i=i+1)
-       if (wr_ce & wr_we & wr_wmask[i])
-         ram[wr_addr[AW-1:0]][i] <= wr_din[i];
+    // Write port
+    always @(posedge wr_clk)
+        for (i = 0; i < DW; i = i + 1)
+            if (wr_ce & wr_we & wr_wmask[i]) ram[wr_addr[AW-1:0]][i] <= wr_din[i];
 
-   // Read Port
-   always @ (posedge rd_clk)
-     if(rd_ce)
-       rd_dout[DW-1:0] <= ram[rd_addr[AW-1:0]];
+    // Read Port
+    always @(posedge rd_clk) if (rd_ce) rd_dout[DW-1:0] <= ram[rd_addr[AW-1:0]];
 
 endmodule
diff --git a/lambdapdk/sky130/libs/sky130sram/lambda/la_spram.v b/lambdapdk/sky130/libs/sky130sram/lambda/la_spram.v
index c8c9a29d..7018a7e2 100644
--- a/lambdapdk/sky130/libs/sky130sram/lambda/la_spram.v
+++ b/lambdapdk/sky130/libs/sky130sram/lambda/la_spram.v
@@ -1,6 +1,6 @@
 /*****************************************************************************
- * Function: Single Port RAM
- * Copyright: Lambda Project Authors. ALl rights Reserved.
+ * Function: Single Port ram
+ * Copyright: Lambda Project Authors. All rights Reserved.
  * License:  MIT (see LICENSE file in Lambda repository)
  *
  * Docs:
@@ -14,7 +14,7 @@
  * supplied on a per macro basis.
  *
  * Technologoy specific implementations of "la_spram" would generally include
- * one ore more hardcoded instantiations of RAM modules with a generate
+ * one ore more hardcoded instantiations of ram modules with a generate
  * statement relying on the "TYPE" to select between the list of modules
  * at build time.
  *
@@ -28,32 +28,39 @@ module la_spram
     parameter TESTW  = 128          // Width of asic test interface
     )
    (// Memory interface
-    input 		clk, // write clock
-    input 		ce, // chip enable
-    input 		we, // write enable
-    input [DW-1:0] 	wmask, //per bit write mask
-    input [AW-1:0] 	addr,//write address
-    input [DW-1:0] 	din, //write data
-    output [DW-1:0] dout,//read output data
+    input clk, // write clock
+    input ce, // chip enable
+    input we, // write enable
+    input [DW-1:0] wmask, //per bit write mask
+    input [AW-1:0] addr, //write address
+    input [DW-1:0] din, //write data
+    output [DW-1:0] dout, //read output data
     // Power signals
-    input 		vss, // ground signal
-    input 		vdd, // memory core array power
-    input 		vddio, // periphery/io power
+    input vss, // ground signal
+    input vdd, // memory core array power
+    input vddio, // periphery/io power
     // Generic interfaces
-    input [CTRLW-1:0] 	ctrl, // pass through ASIC control interface
-    input [TESTW-1:0] 	test // pass through ASIC test interface
+    input [CTRLW-1:0] ctrl, // pass through ASIC control interface
+    input [TESTW-1:0] test // pass through ASIC test interface
     );
 
     // Determine which memory to select
-    localparam MEM_TYPE = "sky130_sram_1rw1r_64x256_8";
+    localparam MEM_TYPE = (TYPE != "DEFAULT") ? TYPE :
+      "sky130_sram_1rw1r_64x256_8";
 
-    localparam MEM_WIDTH = 64;
+    localparam MEM_WIDTH = 
+      (MEM_TYPE == "sky130_sram_1rw1r_64x256_8") ? 64 :
+      0;
  
-    localparam MEM_DEPTH = 8;
+    localparam MEM_DEPTH = 
+      (MEM_TYPE == "sky130_sram_1rw1r_64x256_8") ? 8 :
+      0;
 
     // Create memories
     localparam MEM_ADDRS = 2**(AW - MEM_DEPTH) < 1 ? 1 : 2**(AW - MEM_DEPTH);
 
+    
+
     generate
       genvar o;
       for (o = 0; o < DW; o = o + 1) begin: OUTPUTS
@@ -93,30 +100,26 @@ module la_spram
             end
           end
 
-          wire write_enable;
-          assign write_enable = ce && we && selected;
-          wire read_enable;
-          assign read_enable = ce && ~we && selected;
-
+          wire ce_in;
+          wire we_in;
+          assign ce_in = ce && selected;
+          assign we_in = we && selected;
+          
           if (MEM_TYPE == "sky130_sram_1rw1r_64x256_8")
             sky130_sram_1rw1r_64x256_8 memory (
-              // write port
-                .clk0(clk),
-                .csb0(write_enable),
-                .web0(write_enable),
-                .wmask0({mem_wmask[24],
-                         mem_wmask[16],
-                         mem_wmask[8],
-                         mem_wmask[0]}),
-                .addr0(mem_addr),
-                .din0(mem_din),
-                .dout0(),
-                // read port
-                .clk1(clk),
-                .csb1(read_enable),
-                .addr1(mem_addr),
-                .dout1(mem_dout));
+              .addr0(mem_addr),
+              .addr1(mem_addr),
+              .clk0(clk),
+              .clk1(clk),
+              .csb0(ce_in && we_in),
+              .csb1(ce_in && ~we_in),
+              .din0(mem_din),
+              .dout0(),
+              .dout1(mem_dout),
+              .web0(ce_in && we_in),
+              .wmask0({mem_wmask[24], mem_wmask[16], mem_wmask[8], mem_wmask[0]})
+            );
         end
       end
     endgenerate
-endmodule
+endmodule
\ No newline at end of file
diff --git a/lambdapdk/sky130/libs/sky130sram/lambda/la_spregfile.v b/lambdapdk/sky130/libs/sky130sram/lambda/la_spregfile.v
index a06a09db..d167168c 100644
--- a/lambdapdk/sky130/libs/sky130sram/lambda/la_spregfile.v
+++ b/lambdapdk/sky130/libs/sky130sram/lambda/la_spregfile.v
@@ -1,6 +1,6 @@
 /*****************************************************************************
  * Function: Single Port Register File
- * Copyright: Lambda Project Authors. ALl rights Reserved.
+ * Copyright: Lambda Project Authors. All rights Reserved.
  * License:  MIT (see LICENSE file in Lambda repository)
  *
  * Docs:
@@ -20,50 +20,48 @@
  *
  ****************************************************************************/
 
-module la_spregfile
-  #(parameter DW     = 32,          // Memory width
-    parameter AW     = 10,          // Address width (derived)
-    parameter TYPE   = "DEFAULT",   // Pass through variable for hard macro
-    parameter CTRLW  = 128,         // Width of asic ctrl interface
-    parameter TESTW  = 128          // Width of asic test interface
-    )
-   (// Memory interface
-    input 		clk, // write clock
-    input 		ce, // chip enable
-    input 		we, // write enable
-    input [DW-1:0] 	wmask, //per bit write mask
-    input [AW-1:0] 	addr,//write address
-    input [DW-1:0] 	din, //write data
-    output [DW-1:0]     dout,//read output data
+module la_spregfile #(
+    parameter DW    = 32,         // Memory width
+    parameter AW    = 10,         // Address width (derived)
+    parameter TYPE  = "DEFAULT",  // Pass through variable for hard macro
+    parameter CTRLW = 128,        // Width of asic ctrl interface
+    parameter TESTW = 128         // Width of asic test interface
+) (  // Memory interface
+    input              clk,    // write clock
+    input              ce,     // chip enable
+    input              we,     // write enable
+    input  [   DW-1:0] wmask,  //per bit write mask
+    input  [   AW-1:0] addr,   //write address
+    input  [   DW-1:0] din,    //write data
+    output [   DW-1:0] dout,   //read output data
     // Power signals
-    input 		vss, // ground signal
-    input 		vdd, // memory core array power
-    input 		vddio, // periphery/io power
+    input              vss,    // ground signal
+    input              vdd,    // memory core array power
+    input              vddio,  // periphery/io power
     // Generic interfaces
-    input [CTRLW-1:0] 	ctrl, // pass through ASIC control interface
-    input [TESTW-1:0] 	test // pass through ASIC test interface
-    );
+    input  [CTRLW-1:0] ctrl,   // pass through ASIC control interface
+    input  [TESTW-1:0] test    // pass through ASIC test interface
+);
 
-   la_spram
-   #(.DW(DW),
-     .AW(AW),
-     .TYPE(TYPE),
-     .CTRLW(CTRLW),
-     .TESTW(TESTW)
-     )
-   memory (
-     .clk(clk),
-     .ce(ce),
-     .we(we),
-     .wmask(wmask),
-     .addr(addr),
-     .din(din),
-     .dout(dout),
-     .vss(vss),
-     .vdd(vdd),
-     .vddio(vddio),
-     .ctrl(ctrl),
-     .test(test)
-   );
+    la_spram #(
+        .DW(DW),
+        .AW(AW),
+        .TYPE(TYPE),
+        .CTRLW(CTRLW),
+        .TESTW(TESTW)
+    ) memory (
+        .clk(clk),
+        .ce(ce),
+        .we(we),
+        .wmask(wmask),
+        .addr(addr),
+        .din(din),
+        .dout(dout),
+        .vss(vss),
+        .vdd(vdd),
+        .vddio(vddio),
+        .ctrl(ctrl),
+        .test(test)
+    );
 
 endmodule
diff --git a/lambdapdk/sky130/libs/sky130sram/lambda/la_syncfifo.v b/lambdapdk/sky130/libs/sky130sram/lambda/la_syncfifo.v
index bcb4ec2c..6355a26d 100644
--- a/lambdapdk/sky130/libs/sky130sram/lambda/la_syncfifo.v
+++ b/lambdapdk/sky130/libs/sky130sram/lambda/la_syncfifo.v
@@ -1,6 +1,6 @@
 /*****************************************************************************
  * Function: Synchronous FIFO
- * Copyright: Lambda Project Authors. ALl rights Reserved.
+ * Copyright: Lambda Project Authors. All rights Reserved.
  * License:  MIT (see LICENSE file in Lambda repository)
  *
  * Docs:
@@ -9,128 +9,112 @@
  *
  ****************************************************************************/
 
-module la_syncfifo
-  #(parameter DW        = 32,       // Memory width
-    parameter DEPTH     = 4,        // FIFO depth
-    parameter NS        = 1,        // Number of power supplies
-    parameter CHAOS     = 1,        // generates random full logic when set
-    parameter CTRLW     = 1,        // width of asic ctrl interface
-    parameter TESTW     = 1,        // width of asic test interface
-    parameter TYPE      = "DEFAULT" // Pass through variable for hard macro
-    )
-   (// common clock, reset, power, ctrl
-    input             clk,
-    input             nreset,
-    input             vss, // ground signal
-    input [NS-1:0]    vdd, // supplies
-    input             chaosmode,// randomly assert fifo full when set
-    input [CTRLW-1:0] ctrl, // pass through ASIC control interface
-    input [TESTW-1:0] test, // pass through ASIC test interface
+module la_syncfifo #(
+    parameter DW    = 32,        // Memory width
+    parameter DEPTH = 4,         // FIFO depth
+    parameter NS    = 1,         // Number of power supplies
+    parameter CHAOS = 1,         // generates random full logic when set
+    parameter CTRLW = 1,         // width of asic ctrl interface
+    parameter TESTW = 1,         // width of asic test interface
+    parameter TYPE  = "DEFAULT"  // Pass through variable for hard macro
+) (  // common clock, reset, power, ctrl
+    input              clk,
+    input              nreset,
+    input              vss,        // ground signal
+    input  [   NS-1:0] vdd,        // supplies
+    input              chaosmode,  // randomly assert fifo full when set
+    input  [CTRLW-1:0] ctrl,       // pass through ASIC control interface
+    input  [TESTW-1:0] test,       // pass through ASIC test interface
     // write input
-    input             wr_en, // write fifo
-    input [DW-1:0]    wr_din, // data to write
-    output            wr_full, // fifo full
+    input              wr_en,      // write fifo
+    input  [   DW-1:0] wr_din,     // data to write
+    output             wr_full,    // fifo full
     // read output
-    input             rd_en, // read fifo
-    output [DW-1:0]   rd_dout, // output data
-    output            rd_empty // fifo is empty
-    );
-
-   // local params
-   parameter AW  = $clog2(DEPTH);
-
-   // local wires
-   reg [AW:0]         wr_addr;
-   wire [AW:0]        wr_addr_nxt;
-   reg [AW:0]         rd_addr;
-   wire [AW:0]        rd_addr_nxt;
-   wire               fifo_read;
-   wire               fifo_write;
-   wire               chaosfull;
-   wire               rd_wrap_around;
-   wire               wr_wrap_around;
-
-   //############################
-   // FIFO Empty/Full
-   //############################
-
-   // support any fifo depth
-   assign wr_full     = (chaosfull & chaosmode) |
-                        {~wr_addr[AW], wr_addr[AW-1:0]} == rd_addr[AW:0];
-
-   assign rd_empty    = wr_addr[AW:0] == rd_addr[AW:0];
-
-   assign fifo_read   = rd_en & ~rd_empty;
-
-   assign fifo_write  = wr_en & ~wr_full;
-
-   //############################
-   // FIFO Pointers - wrap around DEPTH-1
-   //############################
-   assign rd_wrap_around       = rd_addr[AW-1:0] == (DEPTH[AW-1:0]-1'b1);
-   assign wr_wrap_around       = wr_addr[AW-1:0] == (DEPTH[AW-1:0]-1'b1);
-
-   assign rd_addr_nxt[AW]     = rd_wrap_around ? ~rd_addr[AW] : rd_addr[AW];
-   assign rd_addr_nxt[AW-1:0] = rd_wrap_around ? 'b0 : (rd_addr[AW-1:0] + 1);
-
-   assign wr_addr_nxt[AW]     = (wr_addr[AW-1:0] == (DEPTH[AW-1:0]-1'b1)) ? ~wr_addr[AW] : wr_addr[AW];
-   assign wr_addr_nxt[AW-1:0] = (wr_addr[AW-1:0] == (DEPTH[AW-1:0]-1'b1)) ? 'b0 : (wr_addr[AW-1:0] + 1);
-
-   always @ (posedge clk or negedge nreset)
-     if(~nreset)
-       begin
-          wr_addr[AW:0]    <= 'd0;
-          rd_addr[AW:0]    <= 'b0;
-       end
-     else if(fifo_write & fifo_read)
-       begin
-          wr_addr[AW:0] <= wr_addr_nxt[AW:0];
-          rd_addr[AW:0] <= rd_addr_nxt[AW:0];
-       end
-     else if(fifo_write)
-       begin
-          wr_addr[AW:0] <= wr_addr_nxt[AW:0];
-       end
-     else if(fifo_read)
-       begin
-          rd_addr[AW:0] <= rd_addr_nxt[AW:0];
-       end
-
-   //###########################
-   //# Dual Port Memory
-   //###########################
-
-   reg [DW-1:0]         ram[DEPTH-1:0];
-
-   // Write port (FIFO input)
-   always @(posedge clk)
-     if(wr_en & ~wr_full)
-       ram[wr_addr[AW-1:0]] <= wr_din[DW-1:0];
-
-   // Read port (FIFO output)
-   assign rd_dout[DW-1:0] = ram[rd_addr[AW-1:0]];
-
-
-   //############################
-   // Randomly Asserts FIFO full
-   //############################
-
-   generate
-      if (CHAOS)
-        begin
-           // TODO: implement LFSR
-           reg chaosreg;
-           always @ (posedge clk or negedge nreset)
-             if (~nreset)
-               chaosreg <= 1'b0;
-             else
-               chaosreg <= ~chaosreg;
-           assign chaosfull = chaosreg;
+    input              rd_en,      // read fifo
+    output [   DW-1:0] rd_dout,    // output data
+    output             rd_empty    // fifo is empty
+);
+
+    // local params
+    parameter AW = $clog2(DEPTH);
+
+    // local wires
+    reg  [AW:0] wr_addr;
+    wire [AW:0] wr_addr_nxt;
+    reg  [AW:0] rd_addr;
+    wire [AW:0] rd_addr_nxt;
+    wire        fifo_read;
+    wire        fifo_write;
+    wire        chaosfull;
+    wire        rd_wrap_around;
+    wire        wr_wrap_around;
+
+    //############################
+    // FIFO Empty/Full
+    //############################
+
+    // support any fifo depth
+    assign wr_full = (chaosfull & chaosmode) | {~wr_addr[AW], wr_addr[AW-1:0]} == rd_addr[AW:0];
+
+    assign rd_empty = wr_addr[AW:0] == rd_addr[AW:0];
+
+    assign fifo_read = rd_en & ~rd_empty;
+
+    assign fifo_write = wr_en & ~wr_full;
+
+    //############################
+    // FIFO Pointers - wrap around DEPTH-1
+    //############################
+    assign rd_wrap_around = rd_addr[AW-1:0] == (DEPTH[AW-1:0] - 1'b1);
+    assign wr_wrap_around = wr_addr[AW-1:0] == (DEPTH[AW-1:0] - 1'b1);
+
+    assign rd_addr_nxt[AW] = rd_wrap_around ? ~rd_addr[AW] : rd_addr[AW];
+    assign rd_addr_nxt[AW-1:0] = rd_wrap_around ? 'b0 : (rd_addr[AW-1:0] + 1);
+
+    assign wr_addr_nxt[AW]     = (wr_addr[AW-1:0] == (DEPTH[AW-1:0]-1'b1)) ? ~wr_addr[AW] : wr_addr[AW];
+    assign wr_addr_nxt[AW-1:0] = (wr_addr[AW-1:0] == (DEPTH[AW-1:0]-1'b1)) ? 'b0 : (wr_addr[AW-1:0] + 1);
+
+    always @(posedge clk or negedge nreset)
+        if (~nreset) begin
+            wr_addr[AW:0] <= 'd0;
+            rd_addr[AW:0] <= 'b0;
+        end else if (fifo_write & fifo_read) begin
+            wr_addr[AW:0] <= wr_addr_nxt[AW:0];
+            rd_addr[AW:0] <= rd_addr_nxt[AW:0];
+        end else if (fifo_write) begin
+            wr_addr[AW:0] <= wr_addr_nxt[AW:0];
+        end else if (fifo_read) begin
+            rd_addr[AW:0] <= rd_addr_nxt[AW:0];
         end
-      else
-        begin
-           assign chaosfull = 1'b0;
+
+    //###########################
+    //# Dual Port Memory
+    //###########################
+
+    reg [DW-1:0] ram[DEPTH-1:0];
+
+    // Write port (FIFO input)
+    always @(posedge clk) if (wr_en & ~wr_full) ram[wr_addr[AW-1:0]] <= wr_din[DW-1:0];
+
+    // Read port (FIFO output)
+    assign rd_dout[DW-1:0] = ram[rd_addr[AW-1:0]];
+
+
+    //############################
+    // Randomly Asserts FIFO full
+    //############################
+
+    generate
+        if (CHAOS) begin
+            // TODO: implement LFSR
+            reg chaosreg;
+            always @(posedge clk or negedge nreset)
+                if (~nreset) chaosreg <= 1'b0;
+                else chaosreg <= ~chaosreg;
+            assign chaosfull = chaosreg;
+        end else begin
+            assign chaosfull = 1'b0;
         end
-   endgenerate
+    endgenerate
 
 endmodule