From 004d868be2a9f6e20fc35d6dc52d2d6c5bd07254 Mon Sep 17 00:00:00 2001 From: SiliconCompiler Bot Date: Wed, 13 Mar 2024 10:33:17 +0000 Subject: [PATCH 1/3] Updating yosys from yosys-0.38 to yosys-0.39 Check https://github.com/YosysHQ/yosys/compare/yosys-0.38...yosys-0.39 for changes --- setup/_tools.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/setup/_tools.json b/setup/_tools.json index c4f425604..dc964f3af 100644 --- a/setup/_tools.json +++ b/setup/_tools.json @@ -85,7 +85,7 @@ }, "yosys": { "git-url": "https://github.com/YosysHQ/yosys.git", - "git-commit": "yosys-0.38", + "git-commit": "yosys-0.39", "version-prefix": "yosys-", "auto-update": true }, From 25de17d40bc95ab3498631aabe0dfafab0532653 Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Wed, 13 Mar 2024 18:14:03 -0400 Subject: [PATCH 2/3] remove yosys dont_use preprocess --- siliconcompiler/tools/yosys/prepareLib.py | 25 +---------------------- siliconcompiler/tools/yosys/syn_asic.py | 12 ----------- siliconcompiler/tools/yosys/syn_asic.tcl | 9 +++++++- siliconcompiler/tools/yosys/yosys.py | 2 +- 4 files changed, 10 insertions(+), 38 deletions(-) diff --git a/siliconcompiler/tools/yosys/prepareLib.py b/siliconcompiler/tools/yosys/prepareLib.py index 7969fed0e..6af37a74e 100644 --- a/siliconcompiler/tools/yosys/prepareLib.py +++ b/siliconcompiler/tools/yosys/prepareLib.py @@ -4,10 +4,9 @@ import re import gzip import argparse # argument parsing -import fnmatch -def processLibertyFile(input_file, dont_use=None, logger=None): +def processLibertyFile(input_file, logger=None): # Read input file if logger: logger.info(f"Opening file for replace: {input_file}") @@ -18,28 +17,6 @@ def processLibertyFile(input_file, dont_use=None, logger=None): content = f.read().encode("ascii", "ignore").decode("ascii") f.close() - if dont_use: - # Pattern to match a cell header - patternList = [re.compile(fnmatch.translate(du)) for du in dont_use] - - content_dont_use = "" - re_cell_line = re.compile(r"^\s*cell\s*\(\s*[\"]?(\w+)[\"]?\)\s*\{") - count = 0 - for line in content.splitlines(): - content_dont_use += line + "\n" - cell_match = re_cell_line.match(line) - if cell_match: - for du in patternList: - if du.match(cell_match.group(1)): - if logger: - logger.info(f' Marking {cell_match.group(1)} as dont_use') - content_dont_use += " dont_use : true;\n" - count += 1 - break - content = content_dont_use - if logger: - logger.info(f"Marked {count} cells as dont_use") - # Yosys-abc throws an error if original_pin is found within the liberty file. # removing pattern = r"(.*original_pin.*)" diff --git a/siliconcompiler/tools/yosys/syn_asic.py b/siliconcompiler/tools/yosys/syn_asic.py index 15337cf36..df070def7 100644 --- a/siliconcompiler/tools/yosys/syn_asic.py +++ b/siliconcompiler/tools/yosys/syn_asic.py @@ -186,23 +186,11 @@ def prepare_synthesis_libraries(chip): # mark dff libery file with dont use dff_liberty_file = chip.find_files('tool', tool, 'task', task, 'file', 'dff_liberty', step=step, index=index)[0] - dff_dont_use = [] - for lib in chip.get('asic', 'logiclib', step=step, index=index): - dontuse = chip.get('library', lib, 'asic', 'cells', 'dontuse', step=step, index=index) - if dff_liberty_file in chip.find_files(*_get_synthesis_library_key(chip, lib, corners), - step=step, index=index): - # if we have the exact library, use those dontuses, - # otherwise continue to build full list - dff_dont_use = dontuse - break - - dff_dont_use.extend(dontuse) with open(chip.get('tool', tool, 'task', task, 'file', 'dff_liberty_file', step=step, index=index)[0], 'w') as f: f.write(prepareLib.processLibertyFile( dff_liberty_file, - dont_use=dff_dont_use, logger=None if chip.get('option', 'quiet', step=step, index=index) else chip.logger )) diff --git a/siliconcompiler/tools/yosys/syn_asic.tcl b/siliconcompiler/tools/yosys/syn_asic.tcl index 50f6e7854..55786afdf 100644 --- a/siliconcompiler/tools/yosys/syn_asic.tcl +++ b/siliconcompiler/tools/yosys/syn_asic.tcl @@ -236,7 +236,14 @@ if {[dict get $sc_cfg tool $sc_tool task $sc_task var autoname] == "true"} { yosys autoname } -yosys dfflibmap -liberty $sc_dff_library +set dfflibmap_dont_use [] +foreach lib "$sc_logiclibs $sc_macrolibs" { + foreach cell [dict get $sc_cfg library $lib asic cells dontuse] { + lappend dfflibmap_dont_use -dont_use $cell + } +} + +yosys dfflibmap {*}$dfflibmap_dont_use -liberty $sc_dff_library # perform final techmap and opt in case previous techmaps introduced constructs that need # techmapping diff --git a/siliconcompiler/tools/yosys/yosys.py b/siliconcompiler/tools/yosys/yosys.py index 0d64f30a5..6ee68521d 100644 --- a/siliconcompiler/tools/yosys/yosys.py +++ b/siliconcompiler/tools/yosys/yosys.py @@ -41,7 +41,7 @@ def setup(chip): # Standard Setup chip.set('tool', tool, 'exe', 'yosys') chip.set('tool', tool, 'vswitch', '--version') - chip.set('tool', tool, 'version', '>=0.33+21', clobber=False) + chip.set('tool', tool, 'version', '>=0.38+92', clobber=False) chip.set('tool', tool, 'format', 'tcl', clobber=False) # Task Setup From f6ceebb08426dae2372d6521cbe26a23078c8ab8 Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Wed, 13 Mar 2024 18:29:41 -0400 Subject: [PATCH 3/3] fix daily_ci --- .github/workflows/daily_ci.yml | 3 --- 1 file changed, 3 deletions(-) diff --git a/.github/workflows/daily_ci.yml b/.github/workflows/daily_ci.yml index 8df99b6c3..399ea7d43 100644 --- a/.github/workflows/daily_ci.yml +++ b/.github/workflows/daily_ci.yml @@ -87,15 +87,12 @@ jobs: steps: - name: Checkout SiliconCompiler uses: actions/checkout@v4 - with: - submodules: true - name: Checkout ZeroSOC uses: actions/checkout@v4 with: repository: siliconcompiler/zerosoc path: zerosoc - submodules: true - name: Run flat if: matrix.config == 'flat'