Commits on Mar 27, 2018
  1. Fixed 40GbE Core Rx Dropped Packets

    AdamI75 committed Mar 27, 2018
    The PHY control signals to read out the FIFO have been properly gated now, so when the last word in the FIFO is the start byte there will no longer be a start packet followed by idle packets, which causes the frame to be thrown away. I have also routed the application bad frame signal, so that if the frame is bad it will be reported on the application layer.
Commits on Mar 14, 2018
  1. Updated and refined handling of GPIO yellow block instantiations. Now…

    amishpatel-dbe committed Mar 14, 2018
    … handling any combination of SKARAB lED control.
Commits on Mar 9, 2018
  1. Merged reduced_clk changes from devel into led_manager. Updated count…

    amishpatel-dbe committed Mar 9, 2018
    …ers and ELF-file - now running uBlaze v3.8.1
Commits on Mar 7, 2018
  1. Last commit on led_manager before merging devel updates.

    amishpatel-dbe committed Mar 7, 2018
    Updated method of handling gpio yellow-block handling multiple LEDs. Now also raising error if attempting to control non-consecutive LEDs.
Commits on Feb 27, 2018
  1. Toolflow reduced BSP Clock

    AdamI75 committed Feb 27, 2018
    The BSP clock has been reduced from 156.25MHz to 39.0625MHz to aid with timing closure for the big CBF designs. This has been tested with a 3 x HMC design. The I2C, 1-wire, HMC, 1GbE, 40GbE and wishbone accesses are all working.
Commits on Feb 23, 2018
  1. Finalised implementation of handling GPIO Yellow Block controlling mo…

    amishpatel-dbe committed Feb 23, 2018
    …re than one LED. Requires more testing before incorporating into devel.
  2. fixing a few signal width warnings in vivado

    wnew committed Feb 23, 2018
    Some of these signals were not connected up correctly or inferred 1 bit wide
    signals, these have been cleaned up.
    Also cleaned up white spaces and tabs in a couple of the files.
Commits on Feb 22, 2018
  1. Changes to the clock architecture

    wnew committed Feb 22, 2018
    This change adds an MMCM to create a cascaded MMCM architecture which allows
    us to generate the system, wishbone and user clocks, rather than just using
    the input clock, pre-MMCM as the system clock.
    There have been many constraint changes to aid designs in meeting timing, this
    included changes to the HMC clock constraints.
    Hopefully these changes ease timing closure.
  2. Added led_manager entity into forty_gbe, and connected accordingly. L…

    amishpatel-dbe committed Feb 22, 2018
    …EDs controlled by inherent DSP design are passed to the entity as eight individual signals (with view to changes in logic). A MUX has been implemented in the led_manager entity to select who/what controls the output values of the Front Panel LEDs. The MUX select signal (dsp_override) has been implemented as a register accessible via the wishbone interface at address 0x34 - integer address 13.
    Still need to implement logic behind selecting control over n-many LEDs from a GPIO yellow block, and how that is synthesized/generated.
Commits on Feb 19, 2018
Commits on Feb 16, 2018
  1. Added dest IP option to 40gbe RX snapshots

    Paul Prozesky
    Paul Prozesky committed Feb 16, 2018
Commits on Feb 5, 2018
  1. Added HMC Init reconfig architecture

    AdamI75 committed Feb 5, 2018
    The uBlaze waits 10s and checks to see if the HMC mezzanine cards have initialised and posted okay. If they have then nothing is done, but if they haven't then the FPGA is reconfigured. A new register has been added to check the status of the Mezzanine Cards.
  2. jasper_frontend: check HMC blks don't share sites

    Paul Prozesky
    Paul Prozesky committed Feb 5, 2018
Commits on Jan 24, 2018
  1. Skarab reset infrastructure changes

    wnew committed Jan 24, 2018
    We now create async resets for all clock domains. Each reset goes through
    syncronising logic on its clock domain and is then routed out to the rest
    of the design.
Commits on Jan 23, 2018
  1. Added warning to GPIO yellow block

    AdamI75 committed Jan 23, 2018
    I have added a warning that states that the I/O used in the gpio yellow block is unconstrained - set to false path for FPGA compile.
Commits on Jan 22, 2018
  1. Fixed 40GbE Rx Reset

    AdamI75 committed Jan 22, 2018
    The 40GbE Rx Reset was causing the data to stop flowing. There were a few application layer parameters that were not being reset when the 40GbE yellow block reset was asserted. This has been tested using casperfpga and the 40GbE tutorial.
Commits on Jan 19, 2018
  1. Updated Microblaze to ver 3.6.1

    AdamI75 committed Jan 19, 2018
    The following changes have been made since the previous release: The only change is the correction to LLDP represention of the skarab hostnames - now a base 16 representation instead of base 10. This has been tested using casperfpga.
  2. Updated Microblaze to version 3.6.0

    AdamI75 committed Jan 19, 2018
    The following changes have been made since previous version: Changes made to match Microblaze BRAM memory expansion to 256K, Write to the Microblaze "keepalive" register in LED manager in firmware, Automatically detect program memory range for memory test, Added 100ms delay before reboot to allow serial port comms to complete and Added optional time profiling code to debug programming latency.
  3. Added constraints to GPIO yellow block

    AdamI75 committed Jan 19, 2018
    I have added timing closure constraints to GPIO yellow block. It is assumed that these are non-timing critical signals and hence, they have been made set_false_path. Any timing critical signals should be in a yellow block driver of its own. This has been tested using casperfpga.
Commits on Jan 18, 2018
  1. Updated GPIO yellow block for SKARAB

    AdamI75 committed Jan 18, 2018
    I have updated the GPIO yellow block, so that it now includes the SKARAB gpio, led, sync_in, sync_out and aux_clk_diff. No I/O timing contsraints added for now.
Commits on Jan 17, 2018
  1. Fixed 40GbE tx almost full flag assertion

    AdamI75 committed Jan 17, 2018
    The tx almost full flag will no longer be asserted when yellow block user reset is asserted. Minor bug has been fixed and tested.
  2. Updated Reset counter process

    AdamI75 committed Jan 17, 2018
    added dcm_locked to sensitivity list
  3. Fixed Reset bug with counter

    AdamI75 committed Jan 17, 2018
    The counter reset that occurs on reconfiguration of the FPGA was not working over all compiles. There were times when the fpga_reset signal remains high after reconfiguration. This causes the image to be configured, but the FPGA firmware remains in reset causing the QSFP+ Mezzanine Card and microblaze to be in reset. This is what is referred to as the dud image. To fix this the reset counter process is now reset when dcm_locked = '0'. This ensures the process is always reset and fpga_reset will operate correctly.
Commits on Jan 15, 2018
  1. Updated Microblaze SoC

    AdamI75 committed Jan 15, 2018
    The microblaze SOC has been updated. Exception handling has been added, the program memory has been increased from 128K to 256K, dcm_locked bit has been routed from the reset block and the current MMCM lock bit is routed to the dcm_locked bit of the microblaze. This does not include the new reset architecture yet. This is still coming. The elf file is still not fully optimised. This is to be added soon.
Commits on Jan 8, 2018
Commits on Dec 22, 2017
  1. Fix for consecutive wishbone reads and writes

    AdamI75 committed Dec 22, 2017
    There was an issue with wishbone consecutive reads and writes. The wishbone state machine will now write to the FIFO and then wait immediately for the next strobe to occur instead of waiting for the strobe signal to complete before checking for the next strobe.
Commits on Dec 21, 2017
  1. Wishbone single write and read

    AdamI75 committed Dec 21, 2017
    The wishbone was writing twice and reading twice, because the wishbone write FIFO state machine was being executed twice. I now check for when the write strobe is deasserted before looking for strobe again. This has been tested using casperfpga.
  2. Made wishbone arbiter function sequential

    AdamI75 committed Dec 21, 2017
    The arbiter encoder function has been removed and replaced with a sequential process. This has been tested using casperfpga and works.
Commits on Dec 18, 2017
  1. set default ratio to zero for compatibility

    Jason Manley
    Jason Manley committed Dec 18, 2017
    bus_dual_port_bram default a to b ratio to 2^0 for backwards compatibility.
  2. Fix to bus library

    Jason Manley
    Jason Manley committed Dec 18, 2017
    updated bus_dual_port_ram_init with default a_to_b ratio of 1.
Commits on Dec 17, 2017
  1. comment edit

    amartens committed Dec 17, 2017
Commits on Dec 15, 2017
  1. bus_dual_port_ram mods

    amartens committed Dec 15, 2017
    library block and fix to we proms
  2. very large bram support

    amartens committed Dec 15, 2017
    bus_dual_port_ram will generate very large BRAMs as well as different
    port widths. This commit does not include the library block mod
    but only the init script.
Commits on Dec 8, 2017