Skip to content

HTTPS clone URL

Subversion checkout URL

You can clone with HTTPS or Subversion.

Download ZIP
Browse files

Initial pass at removal of non-KMS support.

It's likely there's a lot more that can be cleaned up/removed as a result
of this, we can handle that as we come across it.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Acked-by: Maarten Maathuis <madman2003@gmail.com>
  • Loading branch information...
commit 17485c234ff191cee3dd19e3dd693a80b024e189 1 parent 061cb28
Ben Skeggs authored
Showing with 176 additions and 14,684 deletions.
  1. +4 −23 configure.ac
  2. +0 −25 src/Makefile.am
  3. +47 −10 src/drmmode_display.c
  4. +0 −224 src/nouveau_bios.h
  5. +0 −617 src/nouveau_calc.c
  6. +0 −65 src/nouveau_connector.h
  7. +0 −91 src/nouveau_crtc.h
  8. +0 −6 src/nouveau_exa.c
  9. +0 −1,031 src/nouveau_hw.c
  10. +0 −352 src/nouveau_hw.h
  11. +0 −31 src/nouveau_modeset.h
  12. +0 −159 src/nouveau_ms.h
  13. +0 −69 src/nouveau_output.h
  14. +16 −23 src/nouveau_xv.c
  15. +5 −3 src/nv04_xv_blit.c
  16. +5 −1 src/nv04_xv_ovl.c
  17. +6 −6 src/nv10_exa.c
  18. +10 −2 src/nv10_xv_ovl.c
  19. +1 −1  src/nv30_exa.c
  20. +2 −3 src/nv30_xv_tex.c
  21. +1 −2  src/nv40_exa.c
  22. +2 −3 src/nv40_xv_tex.c
  23. +0 −123 src/nv50_connector.c
  24. +0 −535 src/nv50_crtc.c
  25. +0 −77 src/nv50_cursor.c
  26. +0 −225 src/nv50_dac.c
  27. +0 −150 src/nv50_display.c
  28. +0 −236 src/nv50_output.c
  29. +0 −899 src/nv50_randr.c
  30. +0 −41 src/nv50_randr.h
  31. +0 −216 src/nv50_sor.c
  32. +0 −449 src/nv50reg.h
  33. +2 −2 src/nv_accel_common.c
  34. +0 −4,810 src/nv_bios.c
  35. +0 −8 src/nv_const.h
  36. +0 −1,095 src/nv_crtc.c
  37. +0 −216 src/nv_cursor.c
  38. +0 −1  src/nv_dma.c
  39. +37 −502 src/nv_driver.c
  40. +0 −158 src/nv_i2c.c
  41. +0 −3  src/nv_include.h
  42. +0 −1,293 src/nv_output.c
  43. +0 −102 src/nv_proto.h
  44. +0 −207 src/nv_setup.c
  45. +38 −86 src/nv_type.h
  46. +0 −503 src/nvreg.h
View
27 configure.ac
@@ -22,18 +22,18 @@
AC_PREREQ(2.57)
AC_INIT([xf86-video-nouveau],
- 0.0.10,
+ 0.0.15,
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
xf86-video-nouveau)
AC_DEFINE_UNQUOTED([NV_MAJOR_VERSION],
- [$(echo $PACKAGE_VERSION | sed -e 's/^\([[0-9]]\)\.[[0-9]]\.[[0-9]]/\1/')],
+ [$(echo $PACKAGE_VERSION | sed -e 's/^\([[0-9]]*\)\.[[0-9]]*\.[[0-9]]*/\1/')],
[Major version])
AC_DEFINE_UNQUOTED([NV_MINOR_VERSION],
- [$(echo $PACKAGE_VERSION | sed -e 's/^[[0-9]]\.\([[0-9]]\)\.[[0-9]]/\1/')],
+ [$(echo $PACKAGE_VERSION | sed -e 's/^[[0-9]]*\.\([[0-9]]*\)\.[[0-9]]*/\1/')],
[Minor version])
AC_DEFINE_UNQUOTED([NV_PATCHLEVEL],
- [$(echo $PACKAGE_VERSION | sed -e 's/^[[0-9]]\.[[0-9]]\.\([[0-9]]\)/\1/')],
+ [$(echo $PACKAGE_VERSION | sed -e 's/^[[0-9]]*\.[[0-9]]*\.\([[0-9]]*\)/\1/')],
[Patch version])
AC_DEFINE_UNQUOTED([NV_DRIVER_DATE],
[$(echo -n \";git log |head -3|tail -1|tr -d '\n';echo -n \")],
@@ -96,25 +96,6 @@ AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[ #include <stdio.h> ]], [[ ]])],
# needed for the next test
CFLAGS="$CFLAGS $XORG_CFLAGS"
-AC_MSG_CHECKING(for DRM modesetting)
-AC_ARG_WITH(
- kms,
- [ --with-kms=yes,no compile with drm modesetting support (default: auto)],
- kms="$withval",
- kms="yes")
-AC_MSG_RESULT($kms)
-
-if test "x$kms" = xyes; then
- AC_CHECK_HEADER([xf86drmMode.h],[kms=yes],[kms=no],
- [#include <stdint.h>
- #include <stdlib.h> ]
- )
-fi
-
-if test "x$kms" = xyes; then
- AC_DEFINE(XF86DRM_MODE,1,[DRM kernel modesetting])
-fi
-
AC_SUBST([CFLAGS])
AC_SUBST([moduledir])
View
25 src/Makefile.am
@@ -29,17 +29,11 @@ nouveau_drv_la_LDFLAGS = -module -avoid-version @LIBDRM_NOUVEAU_LIBS@
nouveau_drv_ladir = @moduledir@/drivers
nouveau_drv_la_SOURCES = \
- nouveau_bios.h \
- nouveau_calc.c \
- nouveau_hw.c nouveau_hw.h \
nouveau_local.h \
- nouveau_ms.h \
nouveau_exa.c nouveau_xv.c nouveau_dri2.c \
nouveau_wfb.c \
nv_accel_common.c \
- nv_bios.c \
nv_const.h \
- nv_cursor.c \
nv_dma.c \
nv_dma.h \
nv_dri.c \
@@ -49,13 +43,8 @@ nouveau_drv_la_SOURCES = \
nv_dripriv.h \
nv_local.h \
nv_proto.h \
- nvreg.h \
- nv_setup.c \
nv_shadow.c \
nv_type.h \
- nv_crtc.c \
- nv_output.c \
- nv_i2c.c \
nv04_exa.c \
nv04_xv_ovl.c \
nv04_xv_blit.c \
@@ -68,23 +57,9 @@ nouveau_drv_la_SOURCES = \
nv40_exa.c \
nv40_xv_tex.c \
nv50_accel.c nv50_accel.h \
- nv50_cursor.c \
- nv50_crtc.c \
- nv50_dac.c \
- nv50_display.c \
nv50_exa.c \
- nv50_output.c \
- nv50_sor.c \
- nv50_randr.c \
- nv50_randr.h \
- nv50_connector.c \
nv50_xv.c \
nv50_texture.h \
- nv50reg.h \
- nouveau_crtc.h \
- nouveau_output.h \
- nouveau_connector.h \
- nouveau_modeset.h \
drmmode_display.c \
vl_hwmc.c \
vl_hwmc.h
View
57 src/drmmode_display.c
@@ -33,7 +33,6 @@
#include "xorgVersion.h"
-#ifdef XF86DRM_MODE
#include "nv_include.h"
#include "xf86drmMode.h"
#include "X11/Xatom.h"
@@ -368,6 +367,52 @@ drmmode_set_mode_major(xf86CrtcPtr crtc, DisplayModePtr mode,
return ret;
}
+#define SOURCE_MASK_INTERLEAVE 32
+#define TRANSPARENT_PIXEL 0
+
+/*
+ * Convert a source/mask bitmap cursor to an ARGB cursor, clipping or
+ * padding as necessary. source/mask are assumed to be alternated each
+ * SOURCE_MASK_INTERLEAVE bits.
+ */
+void
+nv_cursor_convert_cursor(uint32_t *src, void *dst, int src_stride, int dst_stride,
+ int bpp, uint32_t fg, uint32_t bg)
+{
+ int width = min(src_stride, dst_stride);
+ uint32_t b, m, pxval;
+ int i, j, k;
+
+ for (i = 0; i < width; i++) {
+ for (j = 0; j < width / SOURCE_MASK_INTERLEAVE; j++) {
+ int src_off = i*src_stride/SOURCE_MASK_INTERLEAVE + j;
+ int dst_off = i*dst_stride + j*SOURCE_MASK_INTERLEAVE;
+
+ b = src[2*src_off];
+ m = src[2*src_off + 1];
+
+ for (k = 0; k < SOURCE_MASK_INTERLEAVE; k++) {
+ pxval = TRANSPARENT_PIXEL;
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ if (m & 0x80000000)
+ pxval = (b & 0x80000000) ? fg : bg;
+ b <<= 1;
+ m <<= 1;
+#else
+ if (m & 1)
+ pxval = (b & 1) ? fg : bg;
+ b >>= 1;
+ m >>= 1;
+#endif
+ if (bpp == 32)
+ ((uint32_t *)dst)[dst_off + k] = pxval;
+ else
+ ((uint16_t *)dst)[dst_off + k] = pxval;
+ }
+ }
+ }
+}
+
static void
drmmode_reload_cursor_image(xf86CrtcPtr crtc)
{
@@ -430,7 +475,6 @@ drmmode_load_cursor_argb (xf86CrtcPtr crtc, CARD32 *image)
}
}
-
static void
drmmode_hide_cursor (xf86CrtcPtr crtc)
{
@@ -1196,9 +1240,6 @@ drmmode_is_rotate_pixmap(PixmapPtr ppix, struct nouveau_bo **bo)
xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR (pScrn);
int i;
- if (!NVPTR(pScrn)->kms_enable)
- return FALSE;
-
for (i = 0; i < config->num_crtc; i++) {
xf86CrtcPtr crtc = config->crtc[i];
drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
@@ -1237,9 +1278,6 @@ drmmode_remove_fb(ScrnInfoPtr pScrn)
drmmode_crtc_private_ptr drmmode_crtc;
drmmode_ptr drmmode;
- if (!NVPTR(pScrn)->kms_enable)
- return;
-
if (config)
crtc = config->crtc[0];
if (!crtc)
@@ -1260,10 +1298,9 @@ drmmode_cursor_init(ScreenPtr pScreen)
int size = nv_cursor_width(pNv);
int flags = HARDWARE_CURSOR_TRUECOLOR_AT_8BPP |
HARDWARE_CURSOR_SOURCE_MASK_INTERLEAVE_32 |
- (pNv->alphaCursor ? HARDWARE_CURSOR_ARGB : 0) |
+ (pNv->NVArch >= 0x11 ? HARDWARE_CURSOR_ARGB : 0) |
HARDWARE_CURSOR_UPDATE_UNHIDDEN;
return xf86_cursors_init(pScreen, size, size, flags);
}
-#endif
View
224 src/nouveau_bios.h
@@ -1,224 +0,0 @@
-/*
- * Copyright 2007-2008 Nouveau Project
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef __NOUVEAU_BIOS_H__
-#define __NOUVEAU_BIOS_H__
-
-#include "nvreg.h"
-
-#define DCB_MAX_NUM_ENTRIES 16
-#define DCB_MAX_NUM_I2C_ENTRIES 16
-
-#define DCB_LOC_ON_CHIP 0
-
-struct dcb_entry {
- int index; /* may not be raw dcb index if merging has happened */
- uint8_t type;
- uint8_t i2c_index;
- uint8_t heads;
- uint8_t bus;
- uint8_t location;
- uint8_t or;
- bool duallink_possible;
- union {
- struct {
- int maxfreq;
- } crtconf;
- struct {
- bool use_straps_for_mode;
- bool use_power_scripts;
- } lvdsconf;
- };
- bool i2c_upper_default;
-};
-
-struct dcb_i2c_entry {
- uint8_t port_type;
- uint8_t read, write;
- I2CBusPtr chan;
-};
-
-struct parsed_dcb {
- int entries;
- struct dcb_entry entry[DCB_MAX_NUM_ENTRIES];
- struct dcb_i2c_entry i2c[DCB_MAX_NUM_I2C_ENTRIES];
-};
-
-struct bios_parsed_dcb {
- uint8_t version;
-
- struct parsed_dcb dcb;
-
- uint16_t init8e_table_ptr;
- uint8_t *i2c_table;
- uint8_t i2c_default_indices;
-};
-
-enum nouveau_encoder_type
-{
- /* 0-3 match DCB types */
- OUTPUT_NONE = 4,
- OUTPUT_ANALOG = 0,
- OUTPUT_TMDS = 2,
- OUTPUT_LVDS = 3,
- OUTPUT_TV = 1,
- OUTPUT_ANY = 5,
-};
-
-#define IS_DFP(t) (t == OUTPUT_LVDS || t == OUTPUT_TMDS)
-
-enum nouveau_or {
- OUTPUT_A = (1 << 0),
- OUTPUT_B = (1 << 1),
- OUTPUT_C = (1 << 2)
-};
-
-enum LVDS_script {
- /* Order *does* matter here */
- LVDS_INIT = 1,
- LVDS_RESET,
- LVDS_BACKLIGHT_ON,
- LVDS_BACKLIGHT_OFF,
- LVDS_PANEL_ON,
- LVDS_PANEL_OFF
-};
-
-/* changing these requires matching changes to reg tables in nv_get_clock */
-#define MAX_PLL_TYPES 4
-enum pll_types {
- NVPLL,
- MPLL,
- VPLL1,
- VPLL2
-};
-
-struct pll_lims {
- struct {
- int minfreq;
- int maxfreq;
- int min_inputfreq;
- int max_inputfreq;
-
- uint8_t min_m;
- uint8_t max_m;
- uint8_t min_n;
- uint8_t max_n;
- } vco1, vco2;
-
- uint8_t max_log2p;
- /*
- * for most pre nv50 cards setting a log2P of 7 (the common max_log2p
- * value) is no different to 6 (at least for vplls) so allowing the MNP
- * calc to use 7 causes the generated clock to be out by a factor of 2.
- * however, max_log2p cannot be fixed-up during parsing as the
- * unmodified max_log2p value is still needed for setting mplls, hence
- * an additional max_usable_log2p member
- */
- uint8_t max_usable_log2p;
- uint8_t log2p_bias;
- int refclk;
-};
-
-struct nouveau_bios_info {
- struct parsed_dcb *dcb;
-
- uint8_t chip_version;
-
- uint32_t dactestval;
- uint8_t digital_min_front_porch;
- bool fp_no_ddc;
-};
-
-struct nvbios {
- struct nouveau_bios_info pub;
-
- uint8_t data[NV_PROM_SIZE];
- unsigned int length;
- bool execute;
-
- uint8_t major_version;
- uint8_t feature_byte;
- bool is_mobile;
-
- uint32_t fmaxvco, fminvco;
-
- bool old_style_init;
- uint16_t init_script_tbls_ptr;
- uint16_t extra_init_script_tbl_ptr;
- uint16_t macro_index_tbl_ptr;
- uint16_t macro_tbl_ptr;
- uint16_t condition_tbl_ptr;
- uint16_t io_condition_tbl_ptr;
- uint16_t io_flag_condition_tbl_ptr;
- uint16_t init_function_tbl_ptr;
-
- uint16_t pll_limit_tbl_ptr;
- uint16_t ram_restrict_tbl_ptr;
-
- struct bios_parsed_dcb bdcb;
-
- struct {
- int head;
- uint16_t script_table_ptr;
- } display;
-
- struct {
- uint16_t fptablepointer; /* also used by tmds */
- uint16_t fpxlatetableptr;
- int xlatwidth;
- uint16_t lvdsmanufacturerpointer;
- uint16_t fpxlatemanufacturertableptr;
- uint16_t mode_ptr;
- uint16_t xlated_entry;
- bool power_off_for_reset;
- bool reset_after_pclk_change;
- bool dual_link;
- bool link_c_increment;
- bool BITbit1;
- int duallink_transition_clk;
- uint8_t *edid;
-
- /* will need resetting after suspend */
- int last_script_invoc;
- bool lvds_init_run;
- } fp;
-
- struct {
- uint16_t output0_script_ptr;
- uint16_t output1_script_ptr;
- } tmds;
-
- struct {
- uint16_t mem_init_tbl_ptr;
- uint16_t sdr_seq_tbl_ptr;
- uint16_t ddr_seq_tbl_ptr;
-
- struct {
- uint8_t crt, tv, panel;
- } i2c_indices;
-
- uint16_t lvds_single_a_script_ptr;
- } legacy;
-};
-
-#endif
View
617 src/nouveau_calc.c
@@ -1,617 +0,0 @@
-/*
- * Copyright 1993-2003 NVIDIA, Corporation
- * Copyright 2007-2009 Stuart Bennett
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
- * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- */
-
-#include "nv_include.h"
-
-/****************************************************************************\
-* *
-* The video arbitration routines calculate some "magic" numbers. Fixes *
-* the snow seen when accessing the framebuffer without it. *
-* It just works (I hope). *
-* *
-\****************************************************************************/
-
-struct nv_fifo_info {
- int graphics_lwm;
- int video_lwm;
- int graphics_burst_size;
- int video_burst_size;
- bool valid;
-};
-
-struct nv_sim_state {
- int pclk_khz;
- int mclk_khz;
- int nvclk_khz;
- int pix_bpp;
- bool enable_mp;
- bool enable_video;
- int mem_page_miss;
- int mem_latency;
- int memory_type;
- int memory_width;
-};
-
-static void nv4CalcArbitration(struct nv_fifo_info *fifo, struct nv_sim_state *arb)
-{
- int pagemiss, cas, width, video_enable, bpp;
- int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs;
- int found, mclk_extra, mclk_loop, cbs, m1, p1;
- int mclk_freq, pclk_freq, nvclk_freq, mp_enable;
- int us_m, us_n, us_p, video_drain_rate, crtc_drain_rate;
- int vpm_us, us_video, vlwm, video_fill_us, cpm_us, us_crt, clwm;
-
- pclk_freq = arb->pclk_khz;
- mclk_freq = arb->mclk_khz;
- nvclk_freq = arb->nvclk_khz;
- pagemiss = arb->mem_page_miss;
- cas = arb->mem_latency;
- width = arb->memory_width >> 6;
- video_enable = arb->enable_video;
- bpp = arb->pix_bpp;
- mp_enable = arb->enable_mp;
- clwm = 0;
- vlwm = 0;
- cbs = 128;
- pclks = 2;
- nvclks = 2;
- nvclks += 2;
- nvclks += 1;
- mclks = 5;
- mclks += 3;
- mclks += 1;
- mclks += cas;
- mclks += 1;
- mclks += 1;
- mclks += 1;
- mclks += 1;
- mclk_extra = 3;
- nvclks += 2;
- nvclks += 1;
- nvclks += 1;
- nvclks += 1;
- if (mp_enable)
- mclks += 4;
- nvclks += 0;
- pclks += 0;
- found = 0;
- vbs = 0;
- while (found != 1) {
- fifo->valid = true;
- found = 1;
- mclk_loop = mclks + mclk_extra;
- us_m = mclk_loop * 1000 * 1000 / mclk_freq;
- us_n = nvclks * 1000 * 1000 / nvclk_freq;
- us_p = nvclks * 1000 * 1000 / pclk_freq;
- if (video_enable) {
- video_drain_rate = pclk_freq * 2;
- crtc_drain_rate = pclk_freq * bpp / 8;
- vpagemiss = 2;
- vpagemiss += 1;
- crtpagemiss = 2;
- vpm_us = vpagemiss * pagemiss * 1000 * 1000 / mclk_freq;
- if (nvclk_freq * 2 > mclk_freq * width)
- video_fill_us = cbs * 1000 * 1000 / 16 / nvclk_freq;
- else
- video_fill_us = cbs * 1000 * 1000 / (8 * width) / mclk_freq;
- us_video = vpm_us + us_m + us_n + us_p + video_fill_us;
- vlwm = us_video * video_drain_rate / (1000 * 1000);
- vlwm++;
- vbs = 128;
- if (vlwm > 128)
- vbs = 64;
- if (vlwm > (256 - 64))
- vbs = 32;
- if (nvclk_freq * 2 > mclk_freq * width)
- video_fill_us = vbs * 1000 * 1000 / 16 / nvclk_freq;
- else
- video_fill_us = vbs * 1000 * 1000 / (8 * width) / mclk_freq;
- cpm_us = crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq;
- us_crt = us_video + video_fill_us + cpm_us + us_m + us_n + us_p;
- clwm = us_crt * crtc_drain_rate / (1000 * 1000);
- clwm++;
- } else {
- crtc_drain_rate = pclk_freq * bpp / 8;
- crtpagemiss = 2;
- crtpagemiss += 1;
- cpm_us = crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq;
- us_crt = cpm_us + us_m + us_n + us_p;
- clwm = us_crt * crtc_drain_rate / (1000 * 1000);
- clwm++;
- }
- m1 = clwm + cbs - 512;
- p1 = m1 * pclk_freq / mclk_freq;
- p1 = p1 * bpp / 8;
- if ((p1 < m1 && m1 > 0) ||
- (video_enable && (clwm > 511 || vlwm > 255)) ||
- (!video_enable && clwm > 519)) {
- fifo->valid = false;
- found = !mclk_extra;
- mclk_extra--;
- }
- if (clwm < 384)
- clwm = 384;
- if (vlwm < 128)
- vlwm = 128;
- fifo->graphics_lwm = clwm;
- fifo->graphics_burst_size = 128;
- fifo->video_lwm = vlwm + 15;
- fifo->video_burst_size = vbs;
- }
-}
-
-static void nv10CalcArbitration(struct nv_fifo_info *fifo, struct nv_sim_state *arb)
-{
- int pagemiss, width, video_enable, bpp;
- int nvclks, mclks, pclks, vpagemiss, crtpagemiss;
- int nvclk_fill;
- int found, mclk_extra, mclk_loop, cbs, m1;
- int mclk_freq, pclk_freq, nvclk_freq, mp_enable;
- int us_m, us_m_min, us_n, us_p, crtc_drain_rate;
- int vus_m;
- int vpm_us, us_video, cpm_us, us_crt, clwm;
- int clwm_rnd_down;
- int m2us, us_pipe_min, p1clk, p2;
- int min_mclk_extra;
- int us_min_mclk_extra;
-
- pclk_freq = arb->pclk_khz; /* freq in KHz */
- mclk_freq = arb->mclk_khz;
- nvclk_freq = arb->nvclk_khz;
- pagemiss = arb->mem_page_miss;
- width = arb->memory_width / 64;
- video_enable = arb->enable_video;
- bpp = arb->pix_bpp;
- mp_enable = arb->enable_mp;
- clwm = 0;
- cbs = 512;
- pclks = 4; /* lwm detect. */
- nvclks = 3; /* lwm -> sync. */
- nvclks += 2; /* fbi bus cycles (1 req + 1 busy) */
- mclks = 1; /* 2 edge sync. may be very close to edge so just put one. */
- mclks += 1; /* arb_hp_req */
- mclks += 5; /* ap_hp_req tiling pipeline */
- mclks += 2; /* tc_req latency fifo */
- mclks += 2; /* fb_cas_n_ memory request to fbio block */
- mclks += 7; /* sm_d_rdv data returned from fbio block */
-
- /* fb.rd.d.Put_gc need to accumulate 256 bits for read */
- if (arb->memory_type == 0) {
- if (arb->memory_width == 64) /* 64 bit bus */
- mclks += 4;
- else
- mclks += 2;
- } else if (arb->memory_width == 64) /* 64 bit bus */
- mclks += 2;
- else
- mclks += 1;
-
- if (!video_enable && arb->memory_width == 128) {
- mclk_extra = (bpp == 32) ? 31 : 42; /* Margin of error */
- min_mclk_extra = 17;
- } else {
- mclk_extra = (bpp == 32) ? 8 : 4; /* Margin of error */
- /* mclk_extra = 4; *//* Margin of error */
- min_mclk_extra = 18;
- }
-
- nvclks += 1; /* 2 edge sync. may be very close to edge so just put one. */
- nvclks += 1; /* fbi_d_rdv_n */
- nvclks += 1; /* Fbi_d_rdata */
- nvclks += 1; /* crtfifo load */
-
- if (mp_enable)
- mclks += 4; /* Mp can get in with a burst of 8. */
- /* Extra clocks determined by heuristics */
-
- nvclks += 0;
- pclks += 0;
- found = 0;
- while (found != 1) {
- fifo->valid = true;
- found = 1;
- mclk_loop = mclks + mclk_extra;
- us_m = mclk_loop * 1000 * 1000 / mclk_freq; /* Mclk latency in us */
- us_m_min = mclks * 1000 * 1000 / mclk_freq; /* Minimum Mclk latency in us */
- us_min_mclk_extra = min_mclk_extra * 1000 * 1000 / mclk_freq;
- us_n = nvclks * 1000 * 1000 / nvclk_freq; /* nvclk latency in us */
- us_p = pclks * 1000 * 1000 / pclk_freq; /* nvclk latency in us */
- us_pipe_min = us_m_min + us_n + us_p;
-
- vus_m = mclk_loop * 1000 * 1000 / mclk_freq; /* Mclk latency in us */
-
- if (video_enable) {
- crtc_drain_rate = pclk_freq * bpp / 8; /* MB/s */
-
- vpagemiss = 1; /* self generating page miss */
- vpagemiss += 1; /* One higher priority before */
-
- crtpagemiss = 2; /* self generating page miss */
- if (mp_enable)
- crtpagemiss += 1; /* if MA0 conflict */
-
- vpm_us = vpagemiss * pagemiss * 1000 * 1000 / mclk_freq;
-
- us_video = vpm_us + vus_m; /* Video has separate read return path */
-
- cpm_us = crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq;
- us_crt = us_video /* Wait for video */
- + cpm_us /* CRT Page miss */
- + us_m + us_n + us_p; /* other latency */
-
- clwm = us_crt * crtc_drain_rate / (1000 * 1000);
- clwm++; /* fixed point <= float_point - 1. Fixes that */
- } else {
- crtc_drain_rate = pclk_freq * bpp / 8; /* bpp * pclk/8 */
-
- crtpagemiss = 1; /* self generating page miss */
- crtpagemiss += 1; /* MA0 page miss */
- if (mp_enable)
- crtpagemiss += 1; /* if MA0 conflict */
- cpm_us = crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq;
- us_crt = cpm_us + us_m + us_n + us_p;
- clwm = us_crt * crtc_drain_rate / (1000 * 1000);
- clwm++; /* fixed point <= float_point - 1. Fixes that */
-
- /* Finally, a heuristic check when width == 64 bits */
- if (width == 1) {
- nvclk_fill = nvclk_freq * 8;
- if (crtc_drain_rate * 100 >= nvclk_fill * 102)
- clwm = 0xfff; /* Large number to fail */
- else if (crtc_drain_rate * 100 >= nvclk_fill * 98) {
- clwm = 1024;
- cbs = 512;
- }
- }
- }
-
- /*
- * Overfill check:
- */
-
- clwm_rnd_down = (clwm / 8) * 8;
- if (clwm_rnd_down < clwm)
- clwm += 8;
-
- m1 = clwm + cbs - 1024; /* Amount of overfill */
- m2us = us_pipe_min + us_min_mclk_extra;
-
- /* pclk cycles to drain */
- p1clk = m2us * pclk_freq / (1000 * 1000);
- p2 = p1clk * bpp / 8; /* bytes drained. */
-
- if (p2 < m1 && m1 > 0) {
- fifo->valid = false;
- found = 0;
- if (min_mclk_extra == 0) {
- if (cbs <= 32)
- found = 1; /* Can't adjust anymore! */
- else
- cbs = cbs / 2; /* reduce the burst size */
- } else
- min_mclk_extra--;
- } else if (clwm > 1023) { /* Have some margin */
- fifo->valid = false;
- found = 0;
- if (min_mclk_extra == 0)
- found = 1; /* Can't adjust anymore! */
- else
- min_mclk_extra--;
- }
-
- if (clwm < (1024 - cbs + 8))
- clwm = 1024 - cbs + 8;
- /* printf("CRT LWM: prog: 0x%x, bs: 256\n", clwm); */
- fifo->graphics_lwm = clwm;
- fifo->graphics_burst_size = cbs;
-
- fifo->video_lwm = 1024;
- fifo->video_burst_size = 512;
- }
-}
-
-void nv4_10UpdateArbitrationSettings(ScrnInfoPtr pScrn, int VClk, int bpp, int *burst, int *lwm)
-{
- NVPtr pNv = NVPTR(pScrn);
- struct nv_fifo_info fifo_data;
- struct nv_sim_state sim_data;
- int MClk = nouveau_hw_get_clock(pScrn, MPLL);
- int NVClk = nouveau_hw_get_clock(pScrn, NVPLL);
- uint32_t cfg1 = nvReadFB(pNv, NV_PFB_CFG1);
-
- sim_data.pclk_khz = VClk;
- sim_data.mclk_khz = MClk;
- sim_data.nvclk_khz = NVClk;
- sim_data.pix_bpp = bpp;
- sim_data.enable_mp = false;
- if ((pNv->Chipset & 0xffff) == CHIPSET_NFORCE ||
- (pNv->Chipset & 0xffff) == CHIPSET_NFORCE2) {
- struct pci_device *dev = pci_device_find_by_slot(0, 0, 0, 1);
- uint32_t data;
-
- pci_device_cfg_read_u32(dev, &data, 0x7c);
-
- sim_data.enable_video = false;
- sim_data.memory_type = (data >> 12) & 1;
- sim_data.memory_width = 64;
- sim_data.mem_latency = 3;
- sim_data.mem_page_miss = 10;
- } else {
- sim_data.enable_video = (pNv->Architecture != NV_ARCH_04);
- sim_data.memory_type = nvReadFB(pNv, NV_PFB_CFG0) & 0x1;
- sim_data.memory_width = (nvReadEXTDEV(pNv, NV_PEXTDEV_BOOT_0) & 0x10) ? 128 : 64;
- sim_data.mem_latency = cfg1 & 0xf;
- sim_data.mem_page_miss = ((cfg1 >> 4) & 0xf) + ((cfg1 >> 31) & 0x1);
- }
-
- if (pNv->Architecture == NV_ARCH_04)
- nv4CalcArbitration(&fifo_data, &sim_data);
- else
- nv10CalcArbitration(&fifo_data, &sim_data);
-
- if (fifo_data.valid) {
- int b = fifo_data.graphics_burst_size >> 4;
- *burst = 0;
- while (b >>= 1)
- (*burst)++;
- *lwm = fifo_data.graphics_lwm >> 3;
- }
-}
-
-void nv30UpdateArbitrationSettings(int *burst, int *lwm)
-{
- unsigned int fifo_size, burst_size, graphics_lwm;
-
- fifo_size = 2048;
- burst_size = 512;
- graphics_lwm = fifo_size - burst_size;
-
- *burst = 0;
- burst_size >>= 5;
- while (burst_size >>= 1)
- (*burst)++;
- *lwm = graphics_lwm >> 3;
-}
-
-void
-nouveau_calc_arb(ScrnInfoPtr pScrn, int vclk, int bpp, int *burst, int *lwm)
-{
- NVPtr pNv = NVPTR(pScrn);
-
- if (pNv->Architecture < NV_ARCH_30)
- nv4_10UpdateArbitrationSettings(pScrn, vclk, bpp, burst, lwm);
- else if ((pNv->Chipset & 0xfff0) == CHIPSET_C51 ||
- (pNv->Chipset & 0xfff0) == CHIPSET_C512) {
- *burst = 128;
- *lwm = 0x0480;
- } else
- nv30UpdateArbitrationSettings(burst, lwm);
-}
-
-static int getMNP_single(ScrnInfoPtr pScrn, struct pll_lims *pll_lim, int clk,
- struct nouveau_pll_vals *bestpv)
-{
- /* Find M, N and P for a single stage PLL
- *
- * Note that some bioses (NV3x) have lookup tables of precomputed MNP
- * values, but we're too lazy to use those atm
- *
- * "clk" parameter in kHz
- * returns calculated clock
- */
-
- int cv = NVPTR(pScrn)->vbios->chip_version;
- int minvco = pll_lim->vco1.minfreq, maxvco = pll_lim->vco1.maxfreq;
- int minM = pll_lim->vco1.min_m, maxM = pll_lim->vco1.max_m;
- int minN = pll_lim->vco1.min_n, maxN = pll_lim->vco1.max_n;
- int minU = pll_lim->vco1.min_inputfreq, maxU = pll_lim->vco1.max_inputfreq;
- int maxlog2P = pll_lim->max_usable_log2p;
- int crystal = pll_lim->refclk;
- int M, N, log2P, P;
- int clkP, calcclk;
- int delta, bestdelta = INT_MAX;
- int bestclk = 0;
-
- /* this division verified for nv20, nv18, nv28 (Haiku), and nv34 */
- /* possibly correlated with introduction of 27MHz crystal */
- if (cv < 0x17 || cv == 0x1a || cv == 0x20) {
- if (clk > 250000)
- maxM = 6;
- if (clk > 340000)
- maxM = 2;
- } else if (cv < 0x40) {
- if (clk > 150000)
- maxM = 6;
- if (clk > 200000)
- maxM = 4;
- if (clk > 340000)
- maxM = 2;
- }
-
- if ((clk << maxlog2P) < minvco) {
- minvco = clk << maxlog2P;
- maxvco = minvco * 2;
- }
- if (clk + clk/200 > maxvco) /* +0.5% */
- maxvco = clk + clk/200;
-
- /* NV34 goes maxlog2P->0, NV20 goes 0->maxlog2P */
- for (log2P = 0; log2P <= maxlog2P; log2P++) {
- P = 1 << log2P;
- clkP = clk * P;
-
- if (clkP < minvco)
- continue;
- if (clkP > maxvco)
- return bestclk;
-
- for (M = minM; M <= maxM; M++) {
- if (crystal/M < minU)
- return bestclk;
- if (crystal/M > maxU)
- continue;
-
- /* add crystal/2 to round better */
- N = (clkP * M + crystal/2) / crystal;
-
- if (N < minN)
- continue;
- if (N > maxN)
- break;
-
- /* more rounding additions */
- calcclk = ((N * crystal + P/2) / P + M/2) / M;
- delta = abs(calcclk - clk);
- /* we do an exhaustive search rather than terminating
- * on an optimality condition...
- */
- if (delta < bestdelta) {
- bestdelta = delta;
- bestclk = calcclk;
- bestpv->N1 = N;
- bestpv->M1 = M;
- bestpv->log2P = log2P;
- if (delta == 0) /* except this one */
- return bestclk;
- }
- }
- }
-
- return bestclk;
-}
-
-static int getMNP_double(ScrnInfoPtr pScrn, struct pll_lims *pll_lim, int clk,
- struct nouveau_pll_vals *bestpv)
-{
- /* Find M, N and P for a two stage PLL
- *
- * Note that some bioses (NV30+) have lookup tables of precomputed MNP
- * values, but we're too lazy to use those atm
- *
- * "clk" parameter in kHz
- * returns calculated clock
- */
-
- int chip_version = NVPTR(pScrn)->vbios->chip_version;
- int minvco1 = pll_lim->vco1.minfreq, maxvco1 = pll_lim->vco1.maxfreq;
- int minvco2 = pll_lim->vco2.minfreq, maxvco2 = pll_lim->vco2.maxfreq;
- int minU1 = pll_lim->vco1.min_inputfreq, minU2 = pll_lim->vco2.min_inputfreq;
- int maxU1 = pll_lim->vco1.max_inputfreq, maxU2 = pll_lim->vco2.max_inputfreq;
- int minM1 = pll_lim->vco1.min_m, maxM1 = pll_lim->vco1.max_m;
- int minN1 = pll_lim->vco1.min_n, maxN1 = pll_lim->vco1.max_n;
- int minM2 = pll_lim->vco2.min_m, maxM2 = pll_lim->vco2.max_m;
- int minN2 = pll_lim->vco2.min_n, maxN2 = pll_lim->vco2.max_n;
- int maxlog2P = pll_lim->max_usable_log2p;
- int crystal = pll_lim->refclk;
- bool fixedgain2 = (minM2 == maxM2 && minN2 == maxN2);
- int M1, N1, M2, N2, log2P;
- int clkP, calcclk1, calcclk2, calcclkout;
- int delta, bestdelta = INT_MAX;
- int bestclk = 0;
-
- int vco2 = (maxvco2 - maxvco2/200) / 2;
- for (log2P = 0; clk && log2P < maxlog2P && clk <= (vco2 >> log2P); log2P++)
- ;
- clkP = clk << log2P;
-
- if (maxvco2 < clk + clk/200) /* +0.5% */
- maxvco2 = clk + clk/200;
-
- for (M1 = minM1; M1 <= maxM1; M1++) {
- if (crystal/M1 < minU1)
- return bestclk;
- if (crystal/M1 > maxU1)
- continue;
-
- for (N1 = minN1; N1 <= maxN1; N1++) {
- calcclk1 = crystal * N1 / M1;
- if (calcclk1 < minvco1)
- continue;
- if (calcclk1 > maxvco1)
- break;
-
- for (M2 = minM2; M2 <= maxM2; M2++) {
- if (calcclk1/M2 < minU2)
- break;
- if (calcclk1/M2 > maxU2)
- continue;
-
- /* add calcclk1/2 to round better */
- N2 = (clkP * M2 + calcclk1/2) / calcclk1;
- if (N2 < minN2)
- continue;
- if (N2 > maxN2)
- break;
-
- if (!fixedgain2) {
- if (chip_version < 0x60)
- if (N2/M2 < 4 || N2/M2 > 10)
- continue;
-
- calcclk2 = calcclk1 * N2 / M2;
- if (calcclk2 < minvco2)
- break;
- if (calcclk2 > maxvco2)
- continue;
- } else
- calcclk2 = calcclk1;
-
- calcclkout = calcclk2 >> log2P;
- delta = abs(calcclkout - clk);
- /* we do an exhaustive search rather than terminating
- * on an optimality condition...
- */
- if (delta < bestdelta) {
- bestdelta = delta;
- bestclk = calcclkout;
- bestpv->N1 = N1;
- bestpv->M1 = M1;
- bestpv->N2 = N2;
- bestpv->M2 = M2;
- bestpv->log2P = log2P;
- if (delta == 0) /* except this one */
- return bestclk;
- }
- }
- }
- }
-
- return bestclk;
-}
-
-int nouveau_calc_pll_mnp(ScrnInfoPtr pScrn, struct pll_lims *pll_lim, int clk,
- struct nouveau_pll_vals *pv)
-{
- int outclk;
-
- if (!pll_lim->vco2.maxfreq)
- outclk = getMNP_single(pScrn, pll_lim, clk, pv);
- else
- outclk = getMNP_double(pScrn, pll_lim, clk, pv);
-
- if (!outclk)
- NV_ERROR(pScrn,
- "Could not find a compatible set of PLL values\n");
-
- return outclk;
-}
View
65 src/nouveau_connector.h
@@ -1,65 +0,0 @@
-/*
- * Copyright 2008 Maarten Maathuis
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
- * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- */
-
-#ifndef __NOUVEAU_CONNECTOR_H_
-#define __NOUVEAU_CONNECTOR_H_
-
-#include "nv_include.h"
-#include "nouveau_modeset.h"
-#include "nouveau_crtc.h"
-#include "nouveau_output.h"
-
-/* I have yet to find specific information on connectors, so it's all derived from outputs. */
-typedef enum {
- CONNECTOR_NONE = 4,
- CONNECTOR_VGA = 0,
- CONNECTOR_DVI = 1,
- CONNECTOR_TV = 2,
- CONNECTOR_PANEL = 3
-} NVConnectorType;
-
-#define MAX_OUTPUTS_PER_CONNECTOR 2
-
-typedef struct nouveauConnector {
- ScrnInfoPtr scrn;
- int index;
-
- char *name;
- Bool active;
-
- NVConnectorType type;
-
- I2CBusPtr pDDCBus;
- int i2c_index;
-
- /* For load detect amongst other things. */
- nouveauOutputPtr outputs[MAX_OUTPUTS_PER_CONNECTOR];
- int connected_output;
-
- Bool hotplug_detected; /* better name? */
- /* Function pointers. */
- Bool (*HotplugDetect) (nouveauConnectorPtr connector);
- xf86MonPtr (*DDCDetect) (nouveauConnectorPtr connector);
- DisplayModePtr (*GetDDCModes) (nouveauConnectorPtr connector);
-} nouveauConnectorRec;
-
-#endif /* __NOUVEAU_CONNECTOR_H_ */
View
91 src/nouveau_crtc.h
@@ -1,91 +0,0 @@
-/*
- * Copyright 2008 Maarten Maathuis
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
- * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- */
-
-#ifndef __NOUVEAU_CRTC_H_
-#define __NOUVEAU_CRTC_H_
-
-#include "nv_include.h"
-#include "nouveau_modeset.h"
-
-typedef struct nouveauCrtc {
- ScrnInfoPtr scrn;
-
- char *name;
- uint8_t index;
- Bool active;
- Bool blanked;
-
- /* Scanout area. */
- struct nouveau_bo * front_buffer;
- uint32_t fb_pitch;
- uint32_t x; /* relative to the frontbuffer */
- uint32_t y;
-
- /* Gamma */
- struct nouveau_bo *lut;
- struct {
- uint16_t red;
- uint16_t green;
- uint16_t blue;
- uint16_t unused;
- } lut_values[256];
- bool lut_values_valid;
-
- /* Options and some state. */
- Bool modeset_lock;
- Bool dithering;
- Bool cursor_visible;
- Bool use_native_mode;
- int scale_mode;
- int pixel_clock;
-
- /* Mode info. */
- DisplayModePtr cur_mode;
- DisplayModePtr native_mode;
- DisplayModePtr mode_list;
-
- /* Function pointers. */
- Bool (*ModeValid) (nouveauCrtcPtr crtc, DisplayModePtr mode);
- void (*ModeSet) (nouveauCrtcPtr crtc, DisplayModePtr mode);
- void (*SetPixelClock) (nouveauCrtcPtr crtc, int clock);
- void (*SetClockMode) (nouveauCrtcPtr crtc, int clock); /* maybe another name? */
-
- void (*SetFB) (nouveauCrtcPtr crtc, struct nouveau_bo * buffer);
- void (*SetFBOffset) (nouveauCrtcPtr crtc, uint32_t x, uint32_t y);
-
- void (*Blank) (nouveauCrtcPtr crtc, Bool blanked);
- void (*SetDither) (nouveauCrtcPtr crtc);
-
- void (*SetScaleMode) (nouveauCrtcPtr crtc, int scale);
-
- void (*ShowCursor) (nouveauCrtcPtr crtc, Bool forced_lock);
- void (*HideCursor) (nouveauCrtcPtr crtc, Bool forced_lock);
- void (*SetCursorPosition) (nouveauCrtcPtr crtc, int x, int y);
- void (*LoadCursor) (nouveauCrtcPtr crtc, Bool argb, uint32_t *src);
-
- void (*GammaSet) (nouveauCrtcPtr crtc, uint16_t *red, uint16_t *green, uint16_t *blue, int size);
-
- void (*Save) (nouveauCrtcPtr crtc);
- void (*Load) (nouveauCrtcPtr crtc);
-} nouveauCrtcRec;
-
-#endif /* __NOUVEAU_CRTC_H_ */
View
6 src/nouveau_exa.c
@@ -724,12 +724,6 @@ nouveau_exa_init(ScreenPtr pScreen)
if (!exaDriverInit(pScreen, exa))
return FALSE;
- else
- /* EXA init catches this, but only for xserver >= 1.4 */
- if (pNv->VRAMPhysicalSize / 2 < NOUVEAU_ALIGN(pScrn->virtualX, 64) * NOUVEAU_ALIGN(pScrn->virtualY, 64) * (pScrn->bitsPerPixel >> 3)) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "The virtual screen size's resolution is too big for the video RAM framebuffer at this colour depth.\n");
- return FALSE;
- }
pNv->EXADriverPtr = exa;
return TRUE;
View
1,031 src/nouveau_hw.c
@@ -1,1031 +0,0 @@
-/*
- * Copyright 2006 Dave Airlie
- * Copyright 2007 Maarten Maathuis
- * Copyright 2007-2009 Stuart Bennett
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
- * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- */
-
-#include "nv_include.h"
-
-/*
- * misc hw access wrappers/control functions
- */
-
-void NVWriteVgaSeq(NVPtr pNv, int head, uint8_t index, uint8_t value)
-{
- NVWritePRMVIO(pNv, head, NV_PRMVIO_SRX, index);
- NVWritePRMVIO(pNv, head, NV_PRMVIO_SR, value);
-}
-
-uint8_t NVReadVgaSeq(NVPtr pNv, int head, uint8_t index)
-{
- NVWritePRMVIO(pNv, head, NV_PRMVIO_SRX, index);
- return NVReadPRMVIO(pNv, head, NV_PRMVIO_SR);
-}
-
-void NVWriteVgaGr(NVPtr pNv, int head, uint8_t index, uint8_t value)
-{
- NVWritePRMVIO(pNv, head, NV_PRMVIO_GRX, index);
- NVWritePRMVIO(pNv, head, NV_PRMVIO_GX, value);
-}
-
-uint8_t NVReadVgaGr(NVPtr pNv, int head, uint8_t index)
-{
- NVWritePRMVIO(pNv, head, NV_PRMVIO_GRX, index);
- return NVReadPRMVIO(pNv, head, NV_PRMVIO_GX);
-}
-
-/* CR44 takes values 0 (head A), 3 (head B) and 4 (heads tied)
- * it affects only the 8 bit vga io regs, which we access using mmio at
- * 0xc{0,2}3c*, 0x60{1,3}3*, and 0x68{1,3}3d*
- * in general, the set value of cr44 does not matter: reg access works as
- * expected and values can be set for the appropriate head by using a 0x2000
- * offset as required
- * however:
- * a) pre nv40, the head B range of PRMVIO regs at 0xc23c* was not exposed and
- * cr44 must be set to 0 or 3 for accessing values on the correct head
- * through the common 0xc03c* addresses
- * b) in tied mode (4) head B is programmed to the values set on head A, and
- * access using the head B addresses can have strange results, ergo we leave
- * tied mode in init once we know to what cr44 should be restored on exit
- *
- * the owner parameter is slightly abused:
- * 0 and 1 are treated as head values and so the set value is (owner * 3)
- * other values are treated as literal values to set
- */
-void NVSetOwner(NVPtr pNv, int owner)
-{
- if (owner == 1)
- owner *= 3;
- /* CR44 is always changed on CRTC0 */
- NVWriteVgaCrtc(pNv, 0, NV_CIO_CRE_44, owner);
- if (pNv->NVArch == 0x11) { /* set me harder */
- NVWriteVgaCrtc(pNv, 0, NV_CIO_CRE_2E, owner);
- NVWriteVgaCrtc(pNv, 0, NV_CIO_CRE_2E, owner);
- }
-}
-
-/*
- * on nv11 this may not be reliable
- * returned value is suitable for directly programming back into cr44
- */
-int nouveau_hw_get_current_head(ScrnInfoPtr pScrn)
-{
- NVPtr pNv = NVPTR(pScrn);
- int cr44;
-
- if (pNv->NVArch != 0x11)
- return NVReadVgaCrtc(pNv, 0, NV_CIO_CRE_44);
-
- /* reading CR44 is broken on nv11, so we attempt to infer it */
- if (nvReadMC(pNv, NV_PBUS_DEBUG_1) & (1 << 28)) /* heads tied, restore both */
- cr44 = 0x4;
- else {
- bool slaved_on_A, tvA = false;
- bool slaved_on_B, tvB = false;
- bool waslocked;
-
- waslocked = NVLockVgaCrtcs(pNv, false);
-
- slaved_on_A = NVReadVgaCrtc(pNv, 0, NV_CIO_CRE_PIXEL_INDEX) & 0x80;
- if (slaved_on_A)
- tvA = !(NVReadVgaCrtc(pNv, 0, NV_CIO_CRE_LCD__INDEX) & MASK(NV_CIO_CRE_LCD_LCD_SELECT));
-
- slaved_on_B = NVReadVgaCrtc(pNv, 1, NV_CIO_CRE_PIXEL_INDEX) & 0x80;
- if (slaved_on_B)
- tvB = !(NVReadVgaCrtc(pNv, 1, NV_CIO_CRE_LCD__INDEX) & MASK(NV_CIO_CRE_LCD_LCD_SELECT));
-
- if (waslocked)
- NVLockVgaCrtcs(pNv, true);
-
- if (slaved_on_A && !tvA)
- cr44 = 0x0;
- else if (slaved_on_B && !tvB)
- cr44 = 0x3;
- else if (slaved_on_A)
- cr44 = 0x0;
- else if (slaved_on_B)
- cr44 = 0x3;
- else
- cr44 = 0x0;
- }
-
- return cr44;
-}
-
-void NVBlankScreen(NVPtr pNv, int head, bool blank)
-{
- unsigned char seq1;
-
- if (pNv->twoHeads)
- NVSetOwner(pNv, head);
-
- seq1 = NVReadVgaSeq(pNv, head, NV_VIO_SR_CLOCK_INDEX);
-
- NVVgaSeqReset(pNv, head, true);
- if (blank)
- NVWriteVgaSeq(pNv, head, NV_VIO_SR_CLOCK_INDEX, seq1 | 0x20);
- else
- NVWriteVgaSeq(pNv, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20);
- NVVgaSeqReset(pNv, head, false);
-}
-
-/*
- * PLL setting
- */
-
-static int powerctrl_1_shift(int chip_version, int reg)
-{
- int shift = -4;
-
- if (chip_version < 0x17 || chip_version == 0x1a || chip_version == 0x20)
- return shift;
-
- switch (reg) {
- case NV_RAMDAC_VPLL2:
- shift += 4;
- case NV_PRAMDAC_VPLL_COEFF:
- shift += 4;
- case NV_PRAMDAC_MPLL_COEFF:
- shift += 4;
- case NV_PRAMDAC_NVPLL_COEFF:
- shift += 4;
- }
-
- /*
- * the shift for vpll regs is only used for nv3x chips with a single
- * stage pll
- */
- if (shift > 4 && (chip_version < 0x32 || chip_version == 0x35 ||
- chip_version == 0x36 || chip_version >= 0x40))
- shift = -4;
-
- return shift;
-}
-
-static void setPLL_single(ScrnInfoPtr pScrn, uint32_t reg,
- struct nouveau_pll_vals *pv)
-{
- NVPtr pNv = NVPTR(pScrn);
- int chip_version = pNv->vbios->chip_version;
- uint32_t oldpll = NVReadRAMDAC(pNv, 0, reg);
- int oldN = (oldpll >> 8) & 0xff, oldM = oldpll & 0xff;
- uint32_t pll = (oldpll & 0xfff80000) | pv->log2P << 16 | pv->NM1;
- uint32_t saved_powerctrl_1 = 0;
- int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg);
-
- if (oldpll == pll)
- return; /* already set */
-
- if (shift_powerctrl_1 >= 0) {
- saved_powerctrl_1 = nvReadMC(pNv, NV_PBUS_POWERCTRL_1);
- nvWriteMC(pNv, NV_PBUS_POWERCTRL_1,
- (saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) |
- 1 << shift_powerctrl_1);
- }
-
- if (oldM && pv->M1 && (oldN / oldM < pv->N1 / pv->M1))
- /* upclock -- write new post divider first */
- NVWriteRAMDAC(pNv, 0, reg, pv->log2P << 16 | (oldpll & 0xffff));
- else
- /* downclock -- write new NM first */
- NVWriteRAMDAC(pNv, 0, reg, (oldpll & 0xffff0000) | pv->NM1);
-
- if (chip_version < 0x17 && chip_version != 0x11)
- /* wait a bit on older chips */
- usleep(64000);
- NVReadRAMDAC(pNv, 0, reg);
-
- /* then write the other half as well */
- NVWriteRAMDAC(pNv, 0, reg, pll);
-
- if (shift_powerctrl_1 >= 0)
- nvWriteMC(pNv, NV_PBUS_POWERCTRL_1, saved_powerctrl_1);
-}
-
-static uint32_t new_ramdac580(uint32_t reg1, bool ss, uint32_t ramdac580)
-{
- bool head_a = (reg1 == NV_PRAMDAC_VPLL_COEFF);
-
- if (ss) /* single stage pll mode */
- ramdac580 |= head_a ? NV_RAMDAC_580_VPLL1_ACTIVE :
- NV_RAMDAC_580_VPLL2_ACTIVE;
- else
- ramdac580 &= head_a ? ~NV_RAMDAC_580_VPLL1_ACTIVE :
- ~NV_RAMDAC_580_VPLL2_ACTIVE;
-
- return ramdac580;
-}
-
-static void setPLL_double_highregs(ScrnInfoPtr pScrn, uint32_t reg1,
- struct nouveau_pll_vals *pv)
-{
- NVPtr pNv = NVPTR(pScrn);
- int chip_version = pNv->vbios->chip_version;
- bool nv3035 = chip_version == 0x30 || chip_version == 0x35;
- uint32_t reg2 = reg1 + ((reg1 == NV_RAMDAC_VPLL2) ? 0x5c : 0x70);
- uint32_t oldpll1 = NVReadRAMDAC(pNv, 0, reg1);
- uint32_t oldpll2 = !nv3035 ? NVReadRAMDAC(pNv, 0, reg2) : 0;
- uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1;
- uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | pv->NM2;
- uint32_t oldramdac580 = 0, ramdac580 = 0;
- bool single_stage = !pv->NM2 || pv->N2 == pv->M2; /* nv41+ only */
- uint32_t saved_powerctrl_1 = 0, savedc040 = 0;
- int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg1);
-
- /* model specific additions to generic pll1 and pll2 set up above */
- if (nv3035) {
- pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 |
- (pv->N2 & 0x7) << 19 | 8 << 4 | (pv->M2 & 7) << 4;
- pll2 = 0;
- }
- if (chip_version > 0x40 && reg1 >= NV_PRAMDAC_VPLL_COEFF) { /* !nv40 */
- oldramdac580 = NVReadRAMDAC(pNv, 0, NV_PRAMDAC_580);
- ramdac580 = new_ramdac580(reg1, single_stage, oldramdac580);
- if (oldramdac580 != ramdac580)
- oldpll1 = ~0; /* force mismatch */
- if (single_stage)
- /* magic value used by nvidia in single stage mode */
- pll2 |= 0x011f;
- }
- if (chip_version > 0x70)
- /* magic bits set by the blob (but not the bios) on g71-73 */
- pll1 = (pll1 & 0x7fffffff) | (single_stage ? 0x4 : 0xc) << 28;
-
- if (oldpll1 == pll1 && oldpll2 == pll2)
- return; /* already set */
-
- if (shift_powerctrl_1 >= 0) {
- saved_powerctrl_1 = nvReadMC(pNv, NV_PBUS_POWERCTRL_1);
- nvWriteMC(pNv, NV_PBUS_POWERCTRL_1,
- (saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) |
- 1 << shift_powerctrl_1);
- }
-
- if (chip_version >= 0x40) {
- int shift_c040 = 14;
-
- switch (reg1) {
- case NV_PRAMDAC_MPLL_COEFF:
- shift_c040 += 2;
- case NV_PRAMDAC_NVPLL_COEFF:
- shift_c040 += 2;
- case NV_RAMDAC_VPLL2:
- shift_c040 += 2;
- case NV_PRAMDAC_VPLL_COEFF:
- shift_c040 += 2;
- }
-
- savedc040 = nvReadMC(pNv, 0xc040);
- if (shift_c040 != 14)
- nvWriteMC(pNv, 0xc040, savedc040 & ~(3 << shift_c040));
- }
-
- if (oldramdac580 != ramdac580)
- NVWriteRAMDAC(pNv, 0, NV_PRAMDAC_580, ramdac580);
-
- if (!nv3035)
- NVWriteRAMDAC(pNv, 0, reg2, pll2);
- NVWriteRAMDAC(pNv, 0, reg1, pll1);
-
- if (shift_powerctrl_1 >= 0)
- nvWriteMC(pNv, NV_PBUS_POWERCTRL_1, saved_powerctrl_1);
- if (chip_version >= 0x40)
- nvWriteMC(pNv, 0xc040, savedc040);
-}
-
-static void setPLL_double_lowregs(ScrnInfoPtr pScrn, uint32_t NMNMreg,
- struct nouveau_pll_vals *pv)
-{
- /* When setting PLLs, there is a merry game of disabling and enabling
- * various bits of hardware during the process. This function is a
- * synthesis of six nv4x traces, nearly each card doing a subtly
- * different thing. With luck all the necessary bits for each card are
- * combined herein. Without luck it deviates from each card's formula
- * so as to not work on any :)
- */
-
- NVPtr pNv = NVPTR(pScrn);
- uint32_t Preg = NMNMreg - 4;
- bool mpll = Preg == 0x4020;
- uint32_t oldPval = nvReadMC(pNv, Preg);
- uint32_t NMNM = pv->NM2 << 16 | pv->NM1;
- uint32_t Pval = (oldPval & (mpll ? ~(0x11 << 16) : ~(1 << 16))) |
- 0xc << 28 | pv->log2P << 16;
- uint32_t saved4600 = 0;
- /* some cards have different maskc040s */
- uint32_t maskc040 = ~(3 << 14), savedc040;
- bool single_stage = !pv->NM2 || pv->N2 == pv->M2;
-
- if (nvReadMC(pNv, NMNMreg) == NMNM && (oldPval & 0xc0070000) == Pval)
- return;
-
- if (Preg == 0x4000)
- maskc040 = ~0x333;
- if (Preg == 0x4058)
- maskc040 = ~(0xc << 24);
-
- if (mpll) {
- struct pll_lims pll_lim;
- uint8_t Pval2;
-
- if (get_pll_limits(pScrn, Preg, &pll_lim))
- return;
-
- Pval2 = pv->log2P + pll_lim.log2p_bias;
- if (Pval2 > pll_lim.max_log2p)
- Pval2 = pll_lim.max_log2p;
- Pval |= 1 << 28 | Pval2 << 20;
-
- saved4600 = nvReadMC(pNv, 0x4600);
- nvWriteMC(pNv, 0x4600, saved4600 | 8 << 28);
- }
- if (single_stage)
- Pval |= mpll ? 1 << 12 : 1 << 8;
-
- nvWriteMC(pNv, Preg, oldPval | 1 << 28);
- nvWriteMC(pNv, Preg, Pval & ~(4 << 28));
- if (mpll) {
- Pval |= 8 << 20;
- nvWriteMC(pNv, 0x4020, Pval & ~(0xc << 28));
- nvWriteMC(pNv, 0x4038, Pval & ~(0xc << 28));
- }
-
- savedc040 = nvReadMC(pNv, 0xc040);
- nvWriteMC(pNv, 0xc040, savedc040 & maskc040);
-
- nvWriteMC(pNv, NMNMreg, NMNM);
- if (NMNMreg == 0x4024)
- nvWriteMC(pNv, 0x403c, NMNM);
-
- nvWriteMC(pNv, Preg, Pval);
- if (mpll) {
- Pval &= ~(8 << 20);
- nvWriteMC(pNv, 0x4020, Pval);
- nvWriteMC(pNv, 0x4038, Pval);
- nvWriteMC(pNv, 0x4600, saved4600);
- }
-
- nvWriteMC(pNv, 0xc040, savedc040);
-
- if (mpll) {
- nvWriteMC(pNv, 0x4020, Pval & ~(1 << 28));
- nvWriteMC(pNv, 0x4038, Pval & ~(1 << 28));
- }
-}
-
-void nouveau_hw_setpll(ScrnInfoPtr pScrn, uint32_t reg1,
- struct nouveau_pll_vals *pv)
-{
- int cv = NVPTR(pScrn)->vbios->chip_version;
-
- if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 ||
- cv >= 0x40) {
- if (reg1 > 0x405c)
- setPLL_double_highregs(pScrn, reg1, pv);
- else
- setPLL_double_lowregs(pScrn, reg1, pv);
- } else
- setPLL_single(pScrn, reg1, pv);
-}
-
-/*
- * PLL getting
- */
-
-static void nouveau_hw_decode_pll(NVPtr pNv, uint32_t reg1,
- uint32_t pll1, uint32_t pll2,
- struct nouveau_pll_vals *pllvals)
-{
- /* to force parsing as single stage (i.e. nv40 vplls) pass pll2 as 0 */
-
- /* log2P is & 0x7 as never more than 7, and nv30/35 only uses 3 bits */
- pllvals->log2P = (pll1 >> 16) & 0x7;
- pllvals->N2 = pllvals->M2 = 1;
-
- if (reg1 <= 0x405c) {
- pllvals->NM1 = pll2 & 0xffff;
- /* single stage NVPLL and VPLLs use 1 << 8, MPLL uses 1 << 12 */
- if (!(pll1 & 0x1100))
- pllvals->NM2 = pll2 >> 16;
- } else {
- pllvals->NM1 = pll1 & 0xffff;
- if (pNv->two_reg_pll && pll2 & NV31_RAMDAC_ENABLE_VCO2)
- pllvals->NM2 = pll2 & 0xffff;
- else if (pNv->NVArch == 0x30 || pNv->NVArch == 0x35) {
- pllvals->M1 &= 0xf; /* only 4 bits */
- if (pll1 & NV30_RAMDAC_ENABLE_VCO2) {
- pllvals->M2 = (pll1 >> 4) & 0x7;
- pllvals->N2 = ((pll1 >> 21) & 0x18) |
- ((pll1 >> 19) & 0x7);
- }
- }
- }
-}
-
-int nouveau_hw_get_pllvals(ScrnInfoPtr pScrn, enum pll_types plltype,
- struct nouveau_pll_vals *pllvals)
-{
- NVPtr pNv = NVPTR(pScrn);
- const uint32_t nv04_regs[MAX_PLL_TYPES] = { NV_PRAMDAC_NVPLL_COEFF,
- NV_PRAMDAC_MPLL_COEFF,
- NV_PRAMDAC_VPLL_COEFF,
- NV_RAMDAC_VPLL2 };
- const uint32_t nv40_regs[MAX_PLL_TYPES] = { 0x4000,
- 0x4020,
- NV_PRAMDAC_VPLL_COEFF,
- NV_RAMDAC_VPLL2 };
- uint32_t reg1, pll1, pll2 = 0;
- struct pll_lims pll_lim;
- int ret;
-
- if (pNv->Architecture < NV_ARCH_40)
- reg1 = nv04_regs[plltype];
- else
- reg1 = nv40_regs[plltype];
-
- pll1 = nvReadMC(pNv, reg1);
-
- if (reg1 <= 0x405c)
- pll2 = nvReadMC(pNv, reg1 + 4);
- else if (pNv->two_reg_pll) {
- uint32_t reg2 = reg1 + (reg1 == NV_RAMDAC_VPLL2 ? 0x5c : 0x70);
-
- pll2 = nvReadMC(pNv, reg2);
- }
-
- if (pNv->Architecture == 0x40 && reg1 >= NV_PRAMDAC_VPLL_COEFF) {
- uint32_t ramdac580 = NVReadRAMDAC(pNv, 0, NV_PRAMDAC_580);
-
- /* check whether vpll has been forced into single stage mode */
- if (reg1 == NV_PRAMDAC_VPLL_COEFF) {
- if (ramdac580 & NV_RAMDAC_580_VPLL1_ACTIVE)
- pll2 = 0;
- } else
- if (ramdac580 & NV_RAMDAC_580_VPLL2_ACTIVE)
- pll2 = 0;
- }
-
- nouveau_hw_decode_pll(pNv, reg1, pll1, pll2, pllvals);
-
- if ((ret = get_pll_limits(pScrn, plltype, &pll_lim)))
- return ret;
-
- pllvals->refclk = pll_lim.refclk;
-
- return 0;
-}
-
-int nouveau_hw_pllvals_to_clk(struct nouveau_pll_vals *pv)
-{
- /* Avoid divide by zero if called at an inappropriate time */
- if (!pv->M1 || !pv->M2)
- return 0;
-
- return (pv->N1 * pv->N2 * pv->refclk / (pv->M1 * pv->M2) >> pv->log2P);
-}
-
-int nouveau_hw_get_clock(ScrnInfoPtr pScrn, enum pll_types plltype)
-{
- NVPtr pNv = NVPTR(pScrn);
- struct nouveau_pll_vals pllvals;
-
- if (plltype == MPLL && (pNv->Chipset & 0x0ff0) == CHIPSET_NFORCE) {
- struct pci_device *dev = pci_device_find_by_slot(0, 0, 0, 3);
- uint32_t mpllP;
-
- pci_device_cfg_read_u32(dev, &mpllP, 0x6c);
- mpllP = (mpllP >> 8) & 0xf;
-
- if (!mpllP)
- mpllP = 4;
- return 400000 / mpllP;
- } else
- if (plltype == MPLL && (pNv->Chipset & 0xff0) == CHIPSET_NFORCE2) {
- struct pci_device *dev = pci_device_find_by_slot(0, 0, 0, 5);
- uint32_t data;
-
- pci_device_cfg_read_u32(dev, &data, 0x4c);
-
- return data / 1000;
- }
-
- nouveau_hw_get_pllvals(pScrn, plltype, &pllvals);
-
- return nouveau_hw_pllvals_to_clk(&pllvals);
-}
-
-static void nouveau_hw_fix_bad_vpll(ScrnInfoPtr pScrn, int head)
-{
- /* the vpll on an unused head can come up with a random value, way
- * beyond the pll limits. for some reason this causes the chip to
- * lock up when reading the dac palette regs, so set a valid pll here
- * when such a condition detected. only seen on nv11 to date
- */
-
- struct pll_lims pll_lim;
- struct nouveau_pll_vals pv;
- uint32_t pllreg = head ? NV_RAMDAC_VPLL2 : NV_PRAMDAC_VPLL_COEFF;
-
- if (get_pll_limits(pScrn, head ? VPLL2 : VPLL1, &pll_lim))
- return;
- nouveau_hw_get_pllvals(pScrn, head ? VPLL2 : VPLL1, &pv);
-
- if (pv.M1 >= pll_lim.vco1.min_m && pv.M1 <= pll_lim.vco1.max_m &&
- pv.N1 >= pll_lim.vco1.min_n && pv.N1 <= pll_lim.vco1.max_n &&
- pv.log2P <= pll_lim.max_log2p)
- return;
-
- NV_WARN(pScrn, "VPLL %d outwith limits, attempting to fix\n", head + 1);
-
- /* set lowest clock within static limits */
- pv.M1 = pll_lim.vco1.max_m;
- pv.N1 = pll_lim.vco1.min_n;
- pv.log2P = pll_lim.max_usable_log2p;
- nouveau_hw_setpll(pScrn, pllreg, &pv);
-}
-
-/*
- * vga font save/restore
- */
-
-void nouveau_hw_save_vga_fonts(ScrnInfoPtr pScrn, bool save)
-{
- NVPtr pNv = NVPTR(pScrn);
- bool graphicsmode;
- uint8_t misc, gr4, gr5, gr6, seq2, seq4;
- int i;
-
- if (pNv->twoHeads)
- NVSetOwner(pNv, 0);
-
- NVSetEnablePalette(pNv, 0, true);
- graphicsmode = NVReadVgaAttr(pNv, 0, NV_CIO_AR_MODE_INDEX) & 1;
- NVSetEnablePalette(pNv, 0, false);
-
- if (graphicsmode) /* graphics mode => framebuffer => no need to save */
- return;
-
- NV_TRACE(pScrn, "%sing VGA fonts\n", save ? "Sav" : "Restor");
- if (pNv->twoHeads)
- NVBlankScreen(pNv, 1, true);
- NVBlankScreen(pNv, 0, true);
-
- /* save control regs */
- misc = NVReadPRMVIO(pNv, 0, NV_PRMVIO_MISC__READ);
- seq2 = NVReadVgaSeq(pNv, 0, NV_VIO_SR_PLANE_MASK_INDEX);
- seq4 = NVReadVgaSeq(pNv, 0, NV_VIO_SR_MEM_MODE_INDEX);
- gr4 = NVReadVgaGr(pNv, 0, NV_VIO_GX_READ_MAP_INDEX);
- gr5 = NVReadVgaGr(pNv, 0, NV_VIO_GX_MODE_INDEX);
- gr6 = NVReadVgaGr(pNv, 0, NV_VIO_GX_MISC_INDEX);
-
- NVWritePRMVIO(pNv, 0, NV_PRMVIO_MISC__WRITE, 0x67);
- NVWriteVgaSeq(pNv, 0, NV_VIO_SR_MEM_MODE_INDEX, 0x6);
- NVWriteVgaGr(pNv, 0, NV_VIO_GX_MODE_INDEX, 0x0);
- NVWriteVgaGr(pNv, 0, NV_VIO_GX_MISC_INDEX, 0x5);
-
- /* store font in plane 0 */
- NVWriteVgaSeq(pNv, 0, NV_VIO_SR_PLANE_MASK_INDEX, 0x1);
- NVWriteVgaGr(pNv, 0, NV_VIO_GX_READ_MAP_INDEX, 0x0);
- for (i = 0; i < 16384; i++)
- if (save)
- pNv->saved_vga_font[0][i] = MMIO_IN32(pNv->FB_BAR, i * 4);
- else
- MMIO_OUT32(pNv->FB_BAR, i * 4, pNv->saved_vga_font[0][i]);
-
- /* store font in plane 1 */
- NVWriteVgaSeq(pNv, 0, NV_VIO_SR_PLANE_MASK_INDEX, 0x2);
- NVWriteVgaGr(pNv, 0, NV_VIO_GX_READ_MAP_INDEX, 0x1);
- for (i = 0; i < 16384; i++)
- if (save)
- pNv->saved_vga_font[1][i] = MMIO_IN32(pNv->FB_BAR, i * 4);
- else
- MMIO_OUT32(pNv->FB_BAR, i * 4, pNv->saved_vga_font[1][i]);
-
- /* store font in plane 2 */
- NVWriteVgaSeq(pNv, 0, NV_VIO_SR_PLANE_MASK_INDEX, 0x4);
- NVWriteVgaGr(pNv, 0, NV_VIO_GX_READ_MAP_INDEX, 0x2);
- for (i = 0; i < 16384; i++)
- if (save)
- pNv->saved_vga_font[2][i] = MMIO_IN32(pNv->FB_BAR, i * 4);
- else
- MMIO_OUT32(pNv->FB_BAR, i * 4, pNv->saved_vga_font[2][i]);
-
- /* store font in plane 3 */
- NVWriteVgaSeq(pNv, 0, NV_VIO_SR_PLANE_MASK_INDEX, 0x8);
- NVWriteVgaGr(pNv, 0, NV_VIO_GX_READ_MAP_INDEX, 0x3);
- for (i = 0; i < 16384; i++)
- if (save)
- pNv->saved_vga_font[3][i] = MMIO_IN32(pNv->FB_BAR, i * 4);
- else
- MMIO_OUT32(pNv->FB_BAR, i * 4, pNv->saved_vga_font[3][i]);
-
- /* restore control regs */
- NVWritePRMVIO(pNv, 0, NV_PRMVIO_MISC__WRITE, misc);
- NVWriteVgaGr(pNv, 0, NV_VIO_GX_READ_MAP_INDEX, gr4);
- NVWriteVgaGr(pNv, 0, NV_VIO_GX_MODE_INDEX, gr5);
- NVWriteVgaGr(pNv, 0, NV_VIO_GX_MISC_INDEX, gr6);
- NVWriteVgaSeq(pNv, 0, NV_VIO_SR_PLANE_MASK_INDEX, seq2);
- NVWriteVgaSeq(pNv, 0, NV_VIO_SR_MEM_MODE_INDEX, seq4);
-
- if (pNv->twoHeads)
- NVBlankScreen(pNv, 1, false);
- NVBlankScreen(pNv, 0, false);
-}
-
-/*
- * mode state save/load
- */
-
-static void rd_cio_state(NVPtr pNv, int head,
- struct nouveau_crtc_state *crtcstate, int index)
-{
- crtcstate->CRTC[index] = NVReadVgaCrtc(pNv, head, index);
-}
-
-static void wr_cio_state(NVPtr pNv, int head,
- struct nouveau_crtc_state *crtcstate, int index)
-{
- NVWriteVgaCrtc(pNv, head, index, crtcstate->CRTC[index]);
-}
-
-static void
-nv_save_state_ramdac(ScrnInfoPtr pScrn, int head, struct nouveau_mode_state *state)
-{
- NVPtr pNv = NVPTR(pScrn);
- struct nouveau_crtc_state *regp = &state->head[head];
- int i;
-
- if (pNv->Architecture >= NV_ARCH_10)
- regp->nv10_cursync = NVReadRAMDAC(pNv, head, NV_RAMDAC_NV10_CURSYNC);
-
- nouveau_hw_get_pllvals(pScrn, head ? VPLL2 : VPLL1, &regp->pllvals);
- state->pllsel = NVReadRAMDAC(pNv, 0, NV_PRAMDAC_PLL_COEFF_SELECT);
- if (pNv->twoHeads)
- state->sel_clk = NVReadRAMDAC(pNv, 0, NV_PRAMDAC_SEL_CLK);
- if (pNv->NVArch == 0x11)
- regp->dither = NVReadRAMDAC(pNv, head, NV_RAMDAC_DITHER_NV11);
-
- regp->ramdac_gen_ctrl = NVReadRAMDAC(pNv, head, NV_PRAMDAC_GENERAL_CONTROL);
-
- if (pNv->gf4_disp_arch)
- regp->ramdac_630 = NVReadRAMDAC(pNv, head, NV_PRAMDAC_630);
- if (pNv->NVArch >= 0x30)
- regp->ramdac_634 = NVReadRAMDAC(pNv, head, NV_PRAMDAC_634);
-
- for (i = 0; i < 7; i++) {
- uint32_t ramdac_reg = NV_PRAMDAC_FP_VDISPLAY_END + (i * 4);
-
- regp->fp_vert_regs[i] = NVReadRAMDAC(pNv, head, ramdac_reg);
- regp->fp_horiz_regs[i] = NVReadRAMDAC(pNv, head, ramdac_reg + 0x20);
- }
-
- if (pNv->gf4_disp_arch) {
- regp->dither = NVReadRAMDAC(pNv, head, NV_RAMDAC_FP_DITHER);
- for (i = 0; i < 3; i++) {
- regp->dither_regs[i] = NVReadRAMDAC(pNv, head, NV_PRAMDAC_850 + i * 4);
- regp->dither_regs[i + 3] = NVReadRAMDAC(pNv, head, NV_PRAMDAC_85C + i * 4);
- }
- }
-
- regp->fp_control = NVReadRAMDAC(pNv, head, NV_PRAMDAC_FP_TG_CONTROL);
- regp->fp_debug_0 = NVReadRAMDAC(pNv, head, NV_PRAMDAC_FP_DEBUG_0);
- if (!pNv->gf4_disp_arch && head == 0)
- /* early chips don't allow access to PRAMDAC_TMDS_* without
- * the head A FPCLK on (nv11 even locks up) */
- NVWriteRAMDAC(pNv, 0, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0 &
- ~NV_PRAMDAC_FP_DEBUG_0_PWRDOWN_FPCLK);
- regp->fp_debug_1 = NVReadRAMDAC(pNv, head, NV_PRAMDAC_FP_DEBUG_1);
- regp->fp_debug_2 = NVReadRAMDAC(pNv, head, NV_PRAMDAC_FP_DEBUG_2);
-
- if (pNv->Architecture == NV_ARCH_40) {
- regp->ramdac_a20 = NVReadRAMDAC(pNv, head, NV_PRAMDAC_A20);
- regp->ramdac_a24 = NVReadRAMDAC(pNv, head, NV_PRAMDAC_A24);
- regp->ramdac_a34 = NVReadRAMDAC(pNv, head, NV_PRAMDAC_A34);
- }
-}
-
-static void nv_load_state_ramdac(ScrnInfoPtr pScrn, int head, struct nouveau_mode_state *state)
-{
- NVPtr pNv = NVPTR(pScrn);
- struct nouveau_crtc_state *regp = &state->head[head];
- uint32_t pllreg = head ? NV_RAMDAC_VPLL2 : NV_PRAMDAC_VPLL_COEFF;
- int i;
-
- if (pNv->Architecture >= NV_ARCH_10)
- NVWriteRAMDAC(pNv, head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
-
- nouveau_hw_setpll(pScrn, pllreg, &regp->pllvals);
- NVWriteRAMDAC(pNv, 0, NV_PRAMDAC_PLL_COEFF_SELECT, state->pllsel);
- if (pNv->twoHeads)
- NVWriteRAMDAC(pNv, 0, NV_PRAMDAC_SEL_CLK, state->sel_clk);
- if (pNv->NVArch == 0x11)
- NVWriteRAMDAC(pNv, head, NV_RAMDAC_DITHER_NV11, regp->dither);
-
- NVWriteRAMDAC(pNv, head, NV_PRAMDAC_GENERAL_CONTROL, regp->ramdac_gen_ctrl);
-
- if (pNv->gf4_disp_arch)
- NVWriteRAMDAC(pNv, head, NV_PRAMDAC_630, regp->ramdac_630);
- if (pNv->NVArch >= 0x30)
- NVWriteRAMDAC(pNv, head, NV_PRAMDAC_634, regp->ramdac_634);
-
- for (i = 0; i < 7; i++) {
- uint32_t ramdac_reg = NV_PRAMDAC_FP_VDISPLAY_END + (i * 4);
-
- NVWriteRAMDAC(pNv, head, ramdac_reg, regp->fp_vert_regs[i]);
- NVWriteRAMDAC(pNv, head, ramdac_reg + 0x20, regp->fp_horiz_regs[i]);
- }
-
- if (pNv->gf4_disp_arch) {
- NVWriteRAMDAC(pNv, head, NV_RAMDAC_FP_DITHER, regp->dither);
- for (i = 0; i < 3; i++) {
- NVWriteRAMDAC(pNv, head, NV_PRAMDAC_850 + i * 4, regp->dither_regs[i]);
- NVWriteRAMDAC(pNv, head, NV_PRAMDAC_85C + i * 4, regp->dither_regs[i + 3]);
- }
- }
-
- NVWriteRAMDAC(pNv, head, NV_PRAMDAC_FP_TG_CONTROL, regp->fp_control);
- NVWriteRAMDAC(pNv, head, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0);
- NVWriteRAMDAC(pNv, head, NV_PRAMDAC_FP_DEBUG_1, regp->fp_debug_1);
- NVWriteRAMDAC(pNv, head, NV_PRAMDAC_FP_DEBUG_2, regp->fp_debug_2);
-
- if (pNv->Architecture == NV_ARCH_40) {
- NVWriteRAMDAC(pNv, head, NV_PRAMDAC_A20, regp->ramdac_a20);
- NVWriteRAMDAC(pNv, head, NV_PRAMDAC_A24, regp->ramdac_a24);
- NVWriteRAMDAC(pNv, head, NV_PRAMDAC_A34, regp->ramdac_a34);
- }
-}
-
-static void
-nv_save_state_vga(NVPtr pNv, int head, struct nouveau_mode_state *state)
-{
- struct nouveau_crtc_state *regp = &state->head[head];
- int i;
-
- regp->MiscOutReg = NVReadPRMVIO(pNv, head, NV_PRMVIO_MISC__READ);
-
- for (i = 0; i < 25; i++)
- rd_cio_state(pNv, head, regp, i);
-
- NVSetEnablePalette(pNv, head, true);
- for (i = 0; i < 21; i++)
- regp->Attribute[i] = NVReadVgaAttr(pNv, head, i);
- NVSetEnablePalette(pNv, head, false);
-
- for (i = 0; i < 9; i++)
- regp->Graphics[i] = NVReadVgaGr(pNv, head, i);
-
- for (i = 0; i < 5; i++)
- regp->Sequencer[i] = NVReadVgaSeq(pNv, head, i);
-}
-
-static void nv_load_state_vga(NVPtr pNv, int head, struct nouveau_mode_state *state)
-{
- struct nouveau_crtc_state *regp = &state->head[head];
- int i;
-
- NVWritePRMVIO(pNv, head, NV_PRMVIO_MISC__WRITE, regp->MiscOutReg);
-
- for (i = 0; i < 5; i++)
- NVWriteVgaSeq(pNv, head, i, regp->Sequencer[i]);
-
- nv_lock_vga_crtc_base(pNv, head, false);
- for (i = 0; i < 25; i++)
- wr_cio_state(pNv, head, regp, i);
- nv_lock_vga_crtc_base(pNv, head, true);
-
- for (i = 0; i < 9; i++)
- NVWriteVgaGr(pNv, head, i, regp->Graphics[i]);
-
- NVSetEnablePalette(pNv, head, true);
- for (i = 0; i < 21; i++)
- NVWriteVgaAttr(pNv, head, i, regp->Attribute[i]);
- NVSetEnablePalette(pNv, head, false);
-}
-
-static void
-nv_save_state_ext(NVPtr pNv, int head, struct nouveau_mode_state *state)
-{
- struct nouveau_crtc_state *regp = &state->head[head];
- int i;
-
- rd_cio_state(pNv, head, regp, NV_CIO_CRE_LCD__INDEX);
- rd_cio_state(pNv, head, regp, NV_CIO_CRE_RPC0_INDEX);
- rd_cio_state(pNv, head, regp, NV_CIO_CRE_RPC1_INDEX);
- rd_cio_state(pNv, head, regp, NV_CIO_CRE_LSR_INDEX);
- rd_cio_state(pNv, head, regp, NV_CIO_CRE_PIXEL_INDEX);
- rd_cio_state(pNv, head, regp, NV_CIO_CRE_HEB__INDEX);
- rd_cio_state(pNv, head, regp, NV_CIO_CRE_ENH_INDEX);
-
- rd_cio_state(pNv, head, regp, NV_CIO_CRE_FF_INDEX);
- rd_cio_state(pNv, head, regp, NV_CIO_CRE_FFLWM__INDEX);
- rd_cio_state(pNv, head, regp, NV_CIO_CRE_21);
- if (pNv->Architecture >= NV_ARCH_30)
- rd_cio_state(pNv, head, regp, NV_CIO_CRE_47);
- rd_cio_state(pNv, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
- rd_cio_state(pNv, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
- rd_cio_state(pNv, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
- rd_cio_state(pNv, head, regp, NV_CIO_CRE_ILACE__INDEX);
-
- if (pNv->Architecture >= NV_ARCH_10) {
- regp->crtc_830 = NVReadCRTC(pNv, head, NV_PCRTC_830);
- regp->crtc_834 = NVReadCRTC(pNv, head, NV_PCRTC_834);
- if (pNv->Architecture == NV_ARCH_40) {
- regp->crtc_850 = NVReadCRTC(pNv, head, NV_PCRTC_850);
- regp->gpio_ext = NVReadCRTC(pNv, head, NV_PCRTC_GPIO_EXT);
- }
- if (pNv->twoHeads)
- regp->crtc_eng_ctrl = NVReadCRTC(pNv, head, NV_PCRTC_ENGINE_CTRL);
- regp->cursor_cfg = NVReadCRTC(pNv, head, NV_PCRTC_CURSOR_CONFIG);
- }
-
- regp->crtc_cfg = NVReadCRTC(pNv, head, NV_PCRTC_CONFIG);
-
- rd_cio_state(pNv, head, regp, NV_CIO_CRE_SCRATCH3__INDEX);
- rd_cio_state(pNv, head, regp, NV_CIO_CRE_SCRATCH4__INDEX);
- if (pNv->Architecture >= NV_ARCH_10) {
- rd_cio_state(pNv, head, regp, NV_CIO_CRE_EBR_INDEX);
- rd_cio_state(pNv, head, regp, NV_CIO_CRE_CSB);
- rd_cio_state(pNv, head, regp, NV_CIO_CRE_4B);
- rd_cio_state(pNv, head, regp, NV_CIO_CRE_TVOUT_LATENCY);
- }
- if (pNv->gf4_disp_arch) {
- rd_cio_state(pNv, head, regp, NV_CIO_CRE_53);
- rd_cio_state(pNv, head, regp, NV_CIO_CRE_54);
-
- for (i = 0; i < 0x10; i++)
- regp->CR58[i] = NVReadVgaCrtc5758(pNv, head, i);
- rd_cio_state(pNv, head, regp, NV_CIO_CRE_59);
- rd_cio_state(pNv, head, regp, NV_CIO_CRE_5B);
-
- rd_cio_state(pNv, head, regp, NV_CIO_CRE_85);
- rd_cio_state(pNv, head, regp, NV_CIO_CRE_86);
- }
-
- regp->fb_start = NVReadCRTC(pNv, head, NV_PCRTC_START);
-}
-
-static void nv_load_state_ext(NVPtr pNv, int head, struct nouveau_mode_state *state)
-{
- struct nouveau_crtc_state *regp = &state->head[head];
- int i;
-
- if (pNv->Architecture >= NV_ARCH_10) {
- if (pNv->twoHeads)
- /* setting ENGINE_CTRL (EC) *must* come before
- * CIO_CRE_LCD, as writing CRE_LCD sets bits 16 & 17 in
- * EC that should not be overwritten by writing stale EC
- */
- NVWriteCRTC(pNv, head, NV_PCRTC_ENGINE_CTRL, regp->crtc_eng_ctrl);
-
- nvWriteVIDEO(pNv, NV_PVIDEO_STOP, 1);
- nvWriteVIDEO(pNv, NV_PVIDEO_INTR_EN, 0);
- nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(0), 0);
- nvWriteVIDEO(pNv, NV_PVIDEO_OFFSET_BUFF(1), 0);
- nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(0), pNv->VRAMPhysicalSize - 1);
- nvWriteVIDEO(pNv, NV_PVIDEO_LIMIT(1), pNv->VRAMPhysicalSize - 1);
- nvWriteVIDEO(pNv, NV_PVIDEO_UVPLANE_LIMIT(0), pNv->VRAMPhysicalSize - 1);
- nvWriteVIDEO(pNv, NV_PVIDEO_UVPLANE_LIMIT(1), pNv->VRAMPhysicalSize - 1);
- nvWriteMC(pNv, NV_PBUS_POWERCTRL_2, 0);
-
- NVWriteCRTC(pNv, head, NV_PCRTC_CURSOR_CONFIG, regp->cursor_cfg);
- NVWriteCRTC(pNv, head, NV_PCRTC_830, regp->crtc_830);
- NVWriteCRTC(pNv, head, NV_PCRTC_834, regp->crtc_834);
- if (pNv->Architecture == NV_ARCH_40) {
- NVWriteCRTC(pNv, head, NV_PCRTC_850, regp->crtc_850);
- NVWriteCRTC(pNv, head, NV_PCRTC_GPIO_EXT, regp->gpio_ext);
- }
-
- if (pNv->Architecture == NV_ARCH_40) {
- uint32_t reg900 = NVReadRAMDAC(pNv, head, NV_PRAMDAC_900);
- if (regp->crtc_cfg == NV_PCRTC_CONFIG_START_ADDRESS_HSYNC)
- NVWriteRAMDAC(pNv, head, NV_PRAMDAC_900, reg900 | 0x10000);
- else
- NVWriteRAMDAC(pNv, head, NV_PRAMDAC_900, reg900 & ~0x10000);
- }
- }
-
- NVWriteCRTC(pNv, head, NV_PCRTC_CONFIG, regp->crtc_cfg);
-
- wr_cio_state(pNv, head, regp, NV_CIO_CRE_RPC0_INDEX);
- wr_cio_state(pNv, head, regp, NV_CIO_CRE_RPC1_INDEX);
- wr_cio_state(pNv, head, regp, NV_CIO_CRE_LSR_INDEX);
- wr_cio_state(pNv, head, regp, NV_CIO_CRE_PIXEL_INDEX);
- wr_cio_state(pNv, head, regp, NV_CIO_CRE_LCD__INDEX);
- wr_cio_state(pNv, head, regp, NV_CIO_CRE_HEB__INDEX);
- wr_cio_state(pNv, head, regp, NV_CIO_CRE_ENH_INDEX);
- wr_cio_state(pNv, head, regp, NV_CIO_CRE_FF_INDEX);
- wr_cio_state(pNv, head, regp, NV_CIO_CRE_FFLWM__INDEX);
- if (pNv->Architecture >= NV_ARCH_30)
- wr_cio_state(pNv, head, regp, NV_CIO_CRE_47);
-
- wr_cio_state(pNv, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
- wr_cio_state(pNv, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
- wr_cio_state(pNv, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
- if (pNv->Architecture == NV_ARCH_40)
- nv_fix_nv40_hw_cursor(pNv, head);
- wr_cio_state(pNv, head, regp, NV_CIO_CRE_ILACE__INDEX);
-
- wr_cio_state(pNv, head, regp, NV_CIO_CRE_SCRATCH3__INDEX);
- wr_cio_state(pNv, head, regp, NV_CIO_CRE_SCRATCH4__INDEX);
- if (pNv->Architecture >= NV_ARCH_10) {
- wr_cio_state(pNv, head, regp, NV_CIO_CRE_EBR_INDEX);
- wr_cio_state(pNv, head, regp, NV_CIO_CRE_CSB);
- wr_cio_state(pNv, head, regp, NV_CIO_CRE_4B);
- wr_cio_state(pNv, head, regp, NV_CIO_CRE_TVOUT_LATENCY);
- }
- if (pNv->gf4_disp_arch) {
- wr_cio_state(pNv, head, regp, NV_CIO_CRE_53);
- wr_cio_state(pNv, head, regp, NV_CIO_CRE_54);
-
- for (i = 0; i < 0x10; i++)
- NVWriteVgaCrtc5758(pNv, head, i, regp->CR58[i]);
- wr_cio_state(pNv, head, regp, NV_CIO_CRE_59);
- wr_cio_state(pNv, head, regp, NV_CIO_CRE_5B);
-
- wr_cio_state(pNv, head, regp, NV_CIO_CRE_85);
- wr_cio_state(pNv, head, regp, NV_CIO_CRE_86);
- }
-
- NVWriteCRTC(pNv, head, NV_PCRTC_START, regp->fb_start);
-
- /* Setting 1 on this value gives you interrupts for every vblank period. */
- NVWriteCRTC(pNv, head, NV_PCRTC_INTR_EN_0, 0);
- NVWriteCRTC(pNv, head, NV_PCRTC_INTR_0, NV_PCRTC_INTR_0_VBLANK);
-}
-
-static void
-nv_save_state_palette(NVPtr pNv, int head, struct nouveau_mode_state *state)
-{
- int head_offset = head * NV_PRMDIO_SIZE, i;
-
- VGA_WR08(pNv->REGS, NV_PRMDIO_PIXEL_MASK + head_offset, NV_PRMDIO_PIXEL_MASK_MASK);
- VGA_WR08(pNv->REGS, NV_PRMDIO_READ_MODE_ADDRESS + head_offset, 0x0);
-
- for (i = 0; i < 768; i++) {
- state->head[head].DAC[i] = NV_RD08(pNv->REGS, NV_PRMDIO_PALETTE_DATA + head_offset);
- DDXMMIOH("nv_save_state_palette: head %d reg 0x%04x data 0x%02x\n", head, NV_PRMDIO_PALETTE_DATA + head_offset, state->head[head].DAC[i]);
- }
-
- NVSetEnablePalette(pNv, head, false);
-}
-
-void nouveau_hw_load_state_palette(NVPtr pNv, int head,
- struct nouveau_mode_state *state)
-{
- int head_offset = head * NV_PRMDIO_SIZE, i;
-
- VGA_WR08(pNv->REGS, NV_PRMDIO_PIXEL_MASK + head_offset, NV_PRMDIO_PIXEL_MASK_MASK);
- VGA_WR08(pNv->REGS, NV_PRMDIO_WRITE_MODE_ADDRESS + head_offset, 0x0);
-
- for (i = 0; i < 768; i++) {
- DDXMMIOH("nouveau_mode_state_load_palette: head %d reg 0x%04x data 0x%02x\n", head, NV_PRMDIO_PALETTE_DATA + head_offset, state->head[head].DAC[i]);
- NV_WR08(pNv->REGS, NV_PRMDIO_PALETTE_DATA + head_offset, state->head[head].DAC[i]);
- }
-
- NVSetEnablePalette(pNv, head, false);
-}
-
-void nouveau_hw_save_state(ScrnInfoPtr pScrn, int head,
- struct nouveau_mode_state *state)
-{
- NVPtr pNv = NVPTR(pScrn);
-
- if (pNv->NVArch == 0x11)
- /* NB: no attempt is made to restore the bad pll later on */
- nouveau_hw_fix_bad_vpll(pScrn, head);
- nv_save_state_ramdac(pScrn, head, state);
- nv_save_state_vga(pNv, head, state);
- nv_save_state_palette(pNv, head, state);
- nv_save_state_ext(pNv, head, state);
-}
-
-void nouveau_hw_load_state(ScrnInfoPtr pScrn, int head,
- struct nouveau_mode_state *state)
-{
- NVPtr pNv = NVPTR(pScrn);
-
- NVVgaProtect(pNv, head, true);
- nv_load_state_ramdac(pScrn, head, state);
- nv_load_state_ext(pNv, head, state);
- nouveau_hw_load_state_palette(pNv, head, state);
- nv_load_state_vga(pNv, head, state);
- NVVgaProtect(pNv, head, false);
-}
View
352 src/nouveau_hw.h
@@ -1,352 +0,0 @@
-/*
- * Copyright 2008 Stuart Bennett
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
- * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- */
-
-#ifndef __NOUVEAU_HW_H__
-#define __NOUVEAU_HW_H__
-
-#define MASK(field) ((0xffffffff >> (31 - ((1?field) - (0?field)))) << (0?field))
-#define XLATE(src, srclowbit, outfield) ((((src) >> (srclowbit)) << (0?outfield)) & MASK(outfield))
-
-#define nvReadMC(pNv, reg) DDXMMIOW("nvReadMC: reg %08x val %08x\n", reg, (uint32_t)MMIO_IN32(pNv->REGS, reg))
-#define nvWriteMC(pNv, reg, val) MMIO_OUT32(pNv->REGS, reg, DDXMMIOW("nvWriteMC: reg %08x val %08x\n", reg, val))
-
-#define nvReadVIDEO(pNv, reg) DDXMMIOW("nvReadVIDEO: reg %08x val %08x\n", reg, (uint32_t)MMIO_IN32(pNv->REGS, reg))
-#define nvWriteVIDEO(pNv, reg, val) MMIO_OUT32(pNv->REGS, reg, DDXMMIOW("nvWriteVIDEO: reg %08x val %08x\n", reg, val))
-
-#define nvReadFB(pNv, reg) DDXMMIOW("nvReadFB: reg %08x val %08x\n", reg, (uint32_t)MMIO_IN32(pNv->REGS, reg))
-#define nvWriteFB(pNv, reg, val) MMIO_OUT32(pNv->REGS, reg, DDXMMIOW("nvWriteFB: reg %08x val %08x\n", reg, val))
-
-#define nvReadEXTDEV(pNv, reg) DDXMMIOW("nvReadEXTDEV: reg %08x val %08x\n", reg, (uint32_t)MMIO_IN32(pNv->REGS, reg))
-#define nvWriteEXTDEV(pNv, reg, val) MMIO_OUT32(pNv->REGS, reg, DDXMMIOW("nvWriteEXTDEV: reg %08x val %08x\n", reg, val))
-
-static inline uint32_t NVRead(NVPtr pNv, uint32_t reg)
-{
- DDXMMIOW("NVRead: reg %08x val %08x\n", reg, (uint32_t)NV_RD32(pNv->REGS, reg));
- return NV_RD32(pNv->REGS, reg);
-}
-
-static inline void NVWrite(NVPtr pNv, uint32_t reg, uint32_t val)
-{
- DDXMMIOW("NVWrite: reg %08x val %08x\n", reg, NV_WR32(pNv->REGS, reg, val));
-}
-
-static inline uint32_t NVReadCRTC(NVPtr pNv, int head, uint32_t reg)
-{
- if (head)
- reg += NV_PCRTC0_SIZE;
- DDXMMIOH("NVReadCRTC: head %d reg %08x val %08x\n", head, reg, (uint32_t)NV_RD32(pNv->REGS, reg));
- return NV_RD32(pNv->REGS, reg);
-}
-
-static inline void NVWriteCRTC(NVPtr pNv, int head, uint32_t reg, uint32_t val)
-{
- if (head)
- reg += NV_PCRTC0_SIZE;
- DDXMMIOH("NVWriteCRTC: head %d reg %08x val %08x\n", head, reg, val);
- NV_WR32(pNv->REGS, reg, val);
-}
-
-static inline uint32_t NVReadRAMDAC(NVPtr pNv, int head, uint32_t reg)
-{
- if (head)
- reg += NV_PRAMDAC0_SIZE;
- DDXMMIOH("NVReadRamdac: head %d reg %08x val %08x\n", head, reg, (uint32_t)NV_RD32(pNv->REGS, reg));
- return NV_RD32(pNv->REGS, reg);
-}
-
-static inline void
-NVWriteRAMDAC(NVPtr pNv, int head, uint32_t reg, uint32_t val)
-{
- if (head)
- reg += NV_PRAMDAC0_SIZE;
- DDXMMIOH("NVWriteRamdac: head %d reg %08x val %08x\n", head, reg, val);
- NV_WR32(pNv->REGS, reg, val);
-}
-
-static inline uint8_t nv_read_tmds(NVPtr pNv, int or, int dl, uint8_t address)
-{
- int ramdac = (or & OUTPUT_C) >> 2;
-
- NVWriteRAMDAC(pNv, ramdac, NV_PRAMDAC_FP_TMDS_CONTROL + dl * 8,
- NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE | address);
- return NVReadRAMDAC(pNv, ramdac, NV_PRAMDAC_FP_TMDS_DATA + dl * 8);
-}
-
-static inline void
-nv_write_tmds(NVPtr pNv, int or, int dl, uint8_t address, uint8_t data)
-{
- int ramdac = (or & OUTPUT_C) >> 2;
-
- NVWriteRAMDAC(pNv, ramdac, NV_PRAMDAC_FP_TMDS_DATA + dl * 8, data);
- NVWriteRAMDAC(pNv, ramdac, NV_PRAMDAC_FP_TMDS_CONTROL + dl * 8, address);
-}
-
-static inline void
-NVWriteVgaCrtc(NVPtr pNv, int head, uint8_t index, uint8_t value)
-{
- DDXMMIOH("NVWriteVgaCrtc: head %d index 0x%02x data 0x%02x\n", head, index, value);
- NV_WR08(pNv->REGS, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index);
- NV_WR08(pNv->REGS, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE, value);
-}
-
-static inline uint8_t NVReadVgaCrtc(NVPtr pNv, int head, uint8_t index)
-{
- NV_WR08(pNv->REGS, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index);
- DDXMMIOH("NVReadVgaCrtc: head %d index 0x%02x data 0x%02x\n", head, index, NV_RD08(pNv->REGS, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE));
- return NV_RD08(pNv->REGS, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE);
-}
-
-/* CR57 and CR58 are a fun pair of regs. CR57 provides an index (0-0xf) for CR58
- * I suspect they in fact do nothing, but are merely a way to carry useful
- * per-head variables around
- *
- * Known uses:
- * CR57 CR58
- * 0x00 index to the appropriate dcb entry (or 7f for inactive)
- * 0x02 dcb entry's "or" value (or 00 for inactive)
- * 0x03 bit0 set for dual link (LVDS, possibly elsewhere too)
- * 0x08 or 0x09 pxclk in MHz
- * 0x0f laptop panel info - low nibble for PEXTDEV_BOOT_0 strap
- * high nibble for xlat strap value
- */
-
-static inline void
-NVWriteVgaCrtc5758(NVPtr pNv, int head, uint8_t index, uint8_t value)
-{
- NVWriteVgaCrtc(pNv, head, NV_CIO_CRE_57, index);
- NVWriteVgaCrtc(pNv, head, NV_CIO_CRE_58, value);
-}
-
-static inline uint8_t NVReadVgaCrtc5758(NVPtr pNv, int head, uint8_t index)
-{
- NVWriteVgaCrtc(pNv, head, NV_CIO_CRE_57, index);
- return NVReadVgaCrtc(pNv, head, NV_CIO_CRE_58);
-}
-
-static inline uint8_t NVReadPRMVIO(NVPtr pNv, int head, uint32_t reg)
-{
- /* Only NV4x have two pvio ranges; other twoHeads cards MUST call
- * NVSetOwner for the relevant head to be programmed */
- if (head && pNv->Architecture == NV_ARCH_40)
- reg += NV_PRMVIO_SIZE;
-
- DDXMMIOH("NVReadPRMVIO: head %d reg %08x val %02x\n", head, reg, NV_RD08(pNv->REGS, reg));
- return NV_RD08(pNv->REGS, reg);
-}
-
-static inline void
-NVWritePRMVIO(NVPtr pNv, int head, uint32_t reg, uint8_t value)
-{
- /* Only NV4x have two pvio ranges; other twoHeads cards MUST call
- * NVSetOwner for the relevant head to be programmed */
- if (head && pNv->Architecture == NV_ARCH_40)
- reg += NV_PRMVIO_SIZE;
-
- DDXMMIOH("NVWritePRMVIO: head %d reg %08x val %02x\n", head, reg, value);
- NV_WR08(pNv->REGS, reg, value);
-}
-
-static inline void NVSetEnablePalette(NVPtr pNv, int head, bool enable)
-{
- VGA_RD08(pNv->REGS, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
- VGA_WR08(pNv->REGS, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE,
- enable ? 0 : 0x20);
-}
-
-static inline bool NVGetEnablePalette(NVPtr pNv, int head)
-{
- VGA_RD08(pNv->REGS, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
- return !(VGA_RD08(pNv->REGS, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE) &
- 0x20);
-}
-
-static inline void NVWriteVgaAttr(NVPtr pNv, int head, uint8_t index, uint8_t value)
-{
- if (NVGetEnablePalette(pNv, head))
- index &= ~0x20;
- else
- index |= 0x20;
-
- NV_RD08(pNv->REGS, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
- DDXMMIOH("NVWriteVgaAttr: head %d index 0x%02x data 0x%02x\n", head, index, value);
- NV_WR08(pNv->REGS, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, index);
- NV_WR08(pNv->REGS, NV_PRMCIO_AR__WRITE + head * NV_PRMCIO_SIZE, value);
-}
-
-static inline uint8_t NVReadVgaAttr(NVPtr pNv, int head, uint8_t index)
-{
- if (NVGetEnablePalette(pNv, head))
- index &= ~0x20;
- else
- index |= 0x20;
-
- NV_RD08(pNv->REGS, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
- NV_WR08(pNv->REGS, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, index);
- DDXMMIOH("NVReadVgaAttr: head %d index 0x%02x data 0x%02x\n", head, index, NV_RD08(pNv->REGS, NV_PRMCIO_AR__READ + head * NV_PRMCIO_SIZE));
- return NV_RD08(pNv->REGS, NV_PRMCIO_AR__READ + head * NV_PRMCIO_SIZE);
-}
-
-static inline void NVVgaSeqReset(NVPtr pNv, int head, bool start)
-{
- NVWriteVgaSeq(pNv, head, NV_VIO_SR_RESET_INDEX, start ? 0x1 : 0x3);
-}
-
-static inline void NVVgaProtect(NVPtr pNv, int head, bool protect)
-{
- uint8_t seq1 = NVReadVgaSeq(pNv, head, NV_VIO_SR_CLOCK_INDEX);
-
- if (protect) {
- NVVgaSeqReset(pNv, head, true);
- NVWriteVgaSeq(pNv, head, NV_VIO_SR_CLOCK_INDEX, seq1 | 0x20);
- } else {
- /* Reenable sequencer, then turn on screen */
- NVWriteVgaSeq(pNv, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20); /* reenable display */
- NVVgaSeqReset(pNv, head, false);
- }
- NVSetEnablePalette(pNv, head, protect);
-}
-
-static inline bool nv_heads_tied(NVPtr pNv)
-{
- if (pNv->NVArch == 0x11)
- return !!(nvReadMC(pNv, NV_PBUS_DEBUG_1) & (1 << 28));
-
- return (NVReadVgaCrtc(pNv, 0, NV_CIO_CRE_44) & 0x4);
-}
-
-/* makes cr0-7 on the specified head read-only */
-static inline bool nv_lock_vga_crtc_base(NVPtr pNv, int head, bool lock)
-{
- uint8_t cr11 = NVReadVgaCrtc(pNv, head, NV_CIO_CR_VRE_INDEX);
- bool waslocked = cr11 & 0x80;
-
- if (lock)
- cr11 |= 0x80;
- else
- cr11 &= ~0x80;
- NVWriteVgaCrtc(pNv, head, NV_CIO_CR_VRE_INDEX, cr11);
-
- return waslocked;
-}
-
-static inline void nv_lock_vga_crtc_shadow(NVPtr pNv, int head, int lock)
-{
- /* shadow lock: connects 0x60?3d? regs to "real" 0x3d? regs
- * bit7: unlocks HDT, HBS, HBE, HRS, HRE, HEB
- * bit6: seems to have some effect on CR09 (double scan, VBS_9)
- * bit5: unlocks HDE
- * bit4: unlocks VDE
- * bit3: unlocks VDT, OVL, VRS, ?VRE?, VBS, VBE, LSR, EBR
- * bit2: same as bit 1 of 0x60?804
- * bit0: same as bit 0 of 0x60?804
- */
-
- uint8_t cr21 = lock;
-
- if (lock < 0)
- /* 0xfa is generic "unlock all" mask */
- cr21 = NVReadVgaCrtc(pNv, head, NV_CIO_CRE_21) | 0xfa;
-
- NVWriteVgaCrtc(pNv, head, NV_CIO_CRE_21, cr21);
-}
-
-/* renders the extended crtc regs (cr19+) on all crtcs impervious:
- * immutable and unreadable
- */
-static inline bool NVLockVgaCrtcs(NVPtr pNv, bool lock)
-{
- bool waslocked = !NVReadVgaCrtc(pNv, 0, NV_CIO_SR_LOCK_INDEX);
-
- NVWriteVgaCrtc(pNv, 0, NV_CIO_SR_LOCK_INDEX,
- lock ? NV_CIO_SR_LOCK_VALUE : NV_CIO_SR_UNLOCK_RW_VALUE);
- /* NV11 has independently lockable extended crtcs, except when tied */
- if (pNv->NVArch == 0x11 && !nv_heads_tied(pNv))
- NVWriteVgaCrtc(pNv, 1, NV_CIO_SR_LOCK_INDEX,
- lock ? NV_CIO_SR_LOCK_VALUE :
- NV_CIO_SR_UNLOCK_RW_VALUE);
-
- return waslocked;
-}
-
-/* nv04 cursor max dimensions of 32x32 (A1R5G5B5) */
-#define NV04_CURSOR_SIZE 32
-/* limit nv10 cursors to 64x64 (ARGB8) (we could go to 64x255) */
-#define NV10_CURSOR_SIZE 64
-
-static inline int nv_cursor_width(NVPtr pNv)
-{
- return pNv->NVArch >= 0x10 ? NV10_CURSOR_SIZE : NV04_CURSOR_SIZE;
-}
-
-static inline int nv_cursor_pixels(NVPtr pNv)
-{
- int width = nv_cursor_width(pNv);
-
- return width * width;
-}
-
-static inline void nv_fix_nv40_hw_cursor(NVPtr pNv, int head)
-{
- /* on some nv40 (such as the "true" (in the NV_PFB_BOOT_0 sense) nv40,
- * the gf6800gt) a hardware bug requires a write to PRAMDAC_CURSOR_POS
- * for changes to the CRTC CURCTL regs to take effect, whether changing
- * the pixmap location, or just showing/hiding the cursor
- */
- volatile uint32_t curpos = NVReadRAMDAC(pNv, head,
- NV_PRAMDAC_CU_START_POS);
- NVWriteRAMDAC(pNv, head, NV_PRAMDAC_CU_START_POS, curpos);
-}
-
-static inline void nv_show_cursor(NVPtr pNv, int head, bool show)
-{
- uint8_t *curctl1 =
- &pNv->set_state.head[head].CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX];
-
- if (show)
- *curctl1 |= MASK(NV_CIO_CRE_HCUR_ADDR1_ENABLE);
- else
- *curctl1 &= ~MASK(NV_CIO_CRE_HCUR_ADDR1_ENABLE);
- NVWriteVgaCrtc(pNv, head, NV_CIO_CRE_HCUR_ADDR1_INDEX, *curctl1);
-
- if (pNv->Architecture == NV_ARCH_40)
- nv_fix_nv40_hw_cursor(pNv, head);
-}
-
-static inline uint32_t nv_pitch_align(NVPtr pNv, uint32_t width, int bpp)
-{
- int mask;
-
- if (bpp == 15)
- bpp = 16;
- if (bpp == 24 || bpp == 30)
- bpp = 8;
-
- /* Alignment requirements taken from the Haiku driver */
- if (pNv->Architecture == NV_ARCH_04)
- mask = 128 / bpp - 1;
- else
- mask = 512 / bpp - 1;
-
- return (width + mask) & ~mask;
-}
-
-#endif /* __NOUVEAU_HW_H__ */
View
31 src/nouveau_modeset.h
@@ -1,31 +0,0 @@
-/*
- * Copyright 2008 Maarten Maathuis
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
- * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- */
-
-#ifndef __NOUVEAU_MODESET_H_
-#define __NOUVEAU_MODESET_H_
-
-/* Forward declarations. */
-typedef struct nouveauCrtc *nouveauCrtcPtr;
-typedef struct nouveauConnector *nouveauConnectorPtr;
-typedef struct nouveauOutput *nouveauOutputPtr;
-
-#endif /* __NOUVEAU_MODESET_H_ */
View
159 src/nouveau_ms.h
@@ -1,159 +0,0 @@
-/*
- * Copyright 2006 Dave Airlie
- * Copyright 2007 Maarten Maathuis
- * Copyright 2007-2009 Stuart Bennett
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef __NOUVEAU_MS_H__
-#define __NOUVEAU_MS_H__