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  • Arctic Code Vault Contributor

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@openrisc

Popular repositories

  1. SDRAM controller with multiple wishbone slave ports

    Verilog 13 8

  2. i2s core, with support for both transmit and receive

    Verilog 13 9

  3. LLVM backend for OpenRISC 1000

    C++ 9 8

  4. Clang for OpenRISC 1000

    C++ 7 6

  5. A Device Independent Integrated Logic Analyzer

    Verilog 7 1

2 contributions in the last year

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Contribution activity

January - September 2020

skristiansson has no activity yet for this period.

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