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Organizations

@openrisc

Popular repositories

  1. llvm-or1k

    LLVM backend for OpenRISC 1000

    C++ 9 8

  2. ar100-info

    C 9 4

  3. clang-or1k

    Clang for OpenRISC 1000

    C++ 7 6

  4. wb_sdram_ctrl

    SDRAM controller with multiple wishbone slave ports

    Verilog 7 6

  5. diila

    A Device Independent Integrated Logic Analyzer

    Verilog 6 1

  6. i2s

    i2s core, with support for both transmit and receive

    Verilog 5 6

1 contribution in the last year

Aug Sep Oct Nov Dec Jan Feb Mar Apr May Jun Jul Aug Mon Wed Fri

Contribution activity

January - August 2018

skristiansson has no activity yet for this period.

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