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  • 10 commits
  • 23 files changed
  • 0 commit comments
  • 1 contributor
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4 .gitignore
@@ -21,7 +21,9 @@
#==============================================================================#
# Explicit files to ignore (only matches one).
#==============================================================================#
+.cproject
.gitusers
+.project
autom4te.cache
cscope.files
cscope.out
@@ -40,3 +42,5 @@ projects/*
tools/clang
# LLDB, which is tracked independently.
tools/lldb
+# build directory
+build
View
23 lib/Target/OR1K/InstPrinter/LLVMBuild.txt
@@ -0,0 +1,23 @@
+;===- ./lib/Target/OR1K/InstPrinter/LLVMBuild.txt --------------*- Conf -*--===;
+;
+; The LLVM Compiler Infrastructure
+;
+; This file is distributed under the University of Illinois Open Source
+; License. See LICENSE.TXT for details.
+;
+;===------------------------------------------------------------------------===;
+;
+; This is an LLVMBuild description file for the components in this subdirectory.
+;
+; For more information on the LLVMBuild system, please see:
+;
+; http://llvm.org/docs/LLVMBuild.html
+;
+;===------------------------------------------------------------------------===;
+
+[component_0]
+type = Library
+name = OR1KAsmPrinter
+parent = OR1K
+required_libraries = MC Support
+add_to_library_groups = OR1K
View
15 lib/Target/OR1K/InstPrinter/Makefile
@@ -0,0 +1,15 @@
+##===- lib/Target/OR1K/InstPrinter/Makefile ----------------*- Makefile -*-===##
+#
+# The LLVM Compiler Infrastructure
+#
+# This file is distributed under the University of Illinois Open Source
+# License. See LICENSE.TXT for details.
+#
+##===----------------------------------------------------------------------===##
+LEVEL = ../../../..
+LIBRARYNAME = LLVMOR1KAsmPrinter
+
+# Hack: we need to include 'main' OR1K target directory to grab private headers
+CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
+
+include $(LEVEL)/Makefile.common
View
44 lib/Target/OR1K/InstPrinter/OR1KInstPrinter.cpp
@@ -0,0 +1,44 @@
+//===-- OR1KInstPrinter.cpp - Convert OR1K MCInst to asm syntax -----------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This class prints an OR1K MCInst to a .s file.
+//
+//===----------------------------------------------------------------------===//
+
+#define DEBUG_TYPE "asm-printer"
+#include "OR1K.h"
+#include "OR1KInstPrinter.h"
+#include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCAsmInfo.h"
+#include "llvm/MC/MCExpr.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/FormattedStream.h"
+using namespace llvm;
+
+
+// Include the auto-generated portion of the assembly writer.
+#include "OR1KGenAsmWriter.inc"
+
+void OR1KInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
+ StringRef Annot) {
+ printInstruction(MI, O);
+ printAnnotation(O, Annot);
+}
+
+void OR1KInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
+ raw_ostream &O, const char *Modifier) {
+ assert((Modifier == 0 || Modifier[0] == 0) && "No modifiers supported");
+ const MCOperand &Op = MI->getOperand(OpNo);
+ if (Op.isReg()) {
+ O << getRegisterName(Op.getReg());
+ } else if (Op.isImm()) {
+ O << Op.getImm();
+ } else
+ assert(0 && "Unknown operand in printOperand");
+}
View
38 lib/Target/OR1K/InstPrinter/OR1KInstPrinter.h
@@ -0,0 +1,38 @@
+//= OR1KInstPrinter.h - Convert OR1K MCInst to asm syntax ---------*- C++ -*--//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This class prints a OR1K MCInst to a .s file.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef OR1KINSTPRINTER_H
+#define OR1KINSTPRINTER_H
+
+#include "llvm/MC/MCInstPrinter.h"
+
+namespace llvm {
+ class MCOperand;
+
+ class OR1KInstPrinter : public MCInstPrinter {
+ public:
+ OR1KInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
+ const MCRegisterInfo &MRI)
+ : MCInstPrinter(MAI, MII, MRI) {}
+
+ void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
+ void printOperand(const MCInst *MI, unsigned OpNo,
+ raw_ostream &O, const char *Modifier = 0);
+
+ // Autogenerated by tblgen.
+ void printInstruction(const MCInst *MI, raw_ostream &O);
+ static const char *getRegisterName(unsigned RegNo);
+ };
+}
+
+#endif
View
4 lib/Target/OR1K/LLVMBuild.txt
@@ -16,7 +16,7 @@
;===------------------------------------------------------------------------===;
[common]
-subdirectories = MCTargetDesc TargetInfo
+subdirectories = InstPrinter MCTargetDesc TargetInfo
[component_0]
type = TargetGroup
@@ -28,5 +28,5 @@ has_asmprinter = 1
type = Library
name = OR1KCodeGen
parent = OR1K
-required_libraries = AsmPrinter CodeGen Core MC SelectionDAG OR1KDesc OR1KInfo Support Target
+required_libraries = AsmPrinter CodeGen Core MC OR1KAsmPrinter SelectionDAG OR1KDesc OR1KInfo Support Target
add_to_library_groups = OR1K
View
2 lib/Target/OR1K/MCTargetDesc/LLVMBuild.txt
@@ -19,5 +19,5 @@
type = Library
name = OR1KDesc
parent = OR1K
-required_libraries = MC OR1KInfo Support
+required_libraries = MC OR1KAsmPrinter OR1KInfo Support
add_to_library_groups = OR1K
View
16 lib/Target/OR1K/MCTargetDesc/OR1KMCTargetDesc.cpp
@@ -13,6 +13,7 @@
#include "OR1KMCTargetDesc.h"
#include "OR1KMCAsmInfo.h"
+#include "InstPrinter/OR1KInstPrinter.h"
#include "llvm/MC/MCCodeGenInfo.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
@@ -58,6 +59,17 @@ static MCCodeGenInfo *createOR1KMCCodeGenInfo(StringRef TT, Reloc::Model RM,
return X;
}
+static MCInstPrinter *createOR1KMCInstPrinter(const Target &T,
+ unsigned SyntaxVariant,
+ const MCAsmInfo &MAI,
+ const MCInstrInfo &MII,
+ const MCRegisterInfo &MRI,
+ const MCSubtargetInfo &STI) {
+ if (SyntaxVariant == 0)
+ return new OR1KInstPrinter(MAI, MII, MRI);
+ return 0;
+}
+
extern "C" void LLVMInitializeOR1KTargetMC() {
// Register the MC asm info.
RegisterMCAsmInfo<OR1KMCAsmInfo> X(TheOR1KTarget);
@@ -75,4 +87,8 @@ extern "C" void LLVMInitializeOR1KTargetMC() {
// Register the MC subtarget info.
TargetRegistry::RegisterMCSubtargetInfo(TheOR1KTarget,
createOR1KMCSubtargetInfo);
+
+ // Register the MCInstPrinter.
+ TargetRegistry::RegisterMCInstPrinter(TheOR1KTarget,
+ createOR1KMCInstPrinter);
}
View
3 lib/Target/OR1K/Makefile
@@ -16,6 +16,7 @@ BUILT_SOURCES = OR1KGenRegisterInfo.inc OR1KGenInstrInfo.inc \
OR1KGenAsmWriter.inc OR1KGenDAGISel.inc \
OR1KGenSubtargetInfo.inc OR1KGenCallingConv.inc
-DIRS = TargetInfo MCTargetDesc
+DIRS = InstPrinter TargetInfo MCTargetDesc
include $(LEVEL)/Makefile.common
+
View
24 lib/Target/OR1K/OR1K.td
@@ -1,10 +1,10 @@
//===- OR1K.td - Describe the OR1K Target Machine --------*- tablegen -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
//
@@ -18,19 +18,7 @@ include "llvm/Target/Target.td"
//===----------------------------------------------------------------------===//
// OR1K Subtarget features.
-//
-
-/*
-def FeatureV9
- : SubtargetFeature<"v9", "IsV9", "true",
- "Enable SPARC-V9 instructions">;
-def FeatureV8Deprecated
- : SubtargetFeature<"deprecated-v8", "V8DeprecatedInsts", "true",
- "Enable deprecated V8 instructions in V9 mode">;
-def FeatureVIS
- : SubtargetFeature<"vis", "IsVIS", "true",
- "Enable UltraSPARC Visual Instruction Set extensions">;
-*/
+//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Register File, Calling Conv, Instruction Descriptions
@@ -51,12 +39,16 @@ class Proc<string Name, list<SubtargetFeature> Features>
def : Proc<"generic", []>;
def : Proc<"or1200", []>;
-
+def OpenRISCInstPrinter : AsmWriter {
+ string AsmWriterClassName = "InstPrinter";
+ bit isMCAsmWriter = 1;
+}
//===----------------------------------------------------------------------===//
// Declare the target which we are implementing
//===----------------------------------------------------------------------===//
def OR1K : Target {
// Pull in Instruction Info:
let InstructionSet = OR1KInstrInfo;
+ let AssemblyWriters = [OpenRISCInstPrinter];
}
View
181 lib/Target/OR1K/OR1KAsmPrinter.cpp
@@ -1,4 +1,4 @@
-//===-- OR1KAsmPrinter.cpp - OR1K LLVM assembly writer ------------------===//
+//===-- OR1KAsmPrinter.cpp - OR1K LLVM assembly writer --------------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -8,21 +8,30 @@
//===----------------------------------------------------------------------===//
//
// This file contains a printer that converts from our internal representation
-// of machine-dependent LLVM code to GAS-format SPARC assembly language.
+// of machine-dependent LLVM code to the OR1K assembly language.
//
//===----------------------------------------------------------------------===//
#define DEBUG_TYPE "asm-printer"
#include "OR1K.h"
#include "OR1KInstrInfo.h"
+#include "OR1KMCInstLower.h"
#include "OR1KTargetMachine.h"
+#include "InstPrinter/OR1KInstPrinter.h"
+#include "llvm/Constants.h"
+#include "llvm/DerivedTypes.h"
+#include "llvm/Module.h"
+#include "llvm/Assembly/Writer.h"
#include "llvm/CodeGen/AsmPrinter.h"
+#include "llvm/CodeGen/MachineModuleInfo.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/MC/MCAsmInfo.h"
+#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/Target/Mangler.h"
-#include "llvm/ADT/SmallString.h"
#include "llvm/Support/TargetRegistry.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
@@ -37,171 +46,21 @@ namespace {
return "OR1K Assembly Printer";
}
- void printOperand(const MachineInstr *MI, int opNum, raw_ostream &OS);
- void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &OS,
- const char *Modifier = 0);
- void printCCOperand(const MachineInstr *MI, int opNum, raw_ostream &OS);
-
- virtual void EmitInstruction(const MachineInstr *MI) {
- SmallString<128> Str;
- raw_svector_ostream OS(Str);
- printInstruction(MI, OS);
- OutStreamer.EmitRawText(OS.str());
- }
- void printInstruction(const MachineInstr *MI, raw_ostream &OS);// autogen'd.
- static const char *getRegisterName(unsigned RegNo);
-
- bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
- unsigned AsmVariant, const char *ExtraCode,
- raw_ostream &O);
- bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
- unsigned AsmVariant, const char *ExtraCode,
- raw_ostream &O);
-
- bool printGetPCX(const MachineInstr *MI, unsigned OpNo, raw_ostream &OS);
-
- virtual bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB)
- const;
+ void EmitInstruction(const MachineInstr *MI);
};
} // end of anonymous namespace
-#include "OR1KGenAsmWriter.inc"
-
-void OR1KAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
- raw_ostream &O) {
-}
-
-void OR1KAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum,
- raw_ostream &O, const char *Modifier) {
- printOperand(MI, opNum, O);
-
- // If this is an ADD operand, emit it like normal operands.
- if (Modifier && !strcmp(Modifier, "arith")) {
- O << ", ";
- printOperand(MI, opNum+1, O);
- return;
- }
- if (MI->getOperand(opNum+1).isImm() &&
- MI->getOperand(opNum+1).getImm() == 0)
- return; // don't print "+0"
-
- O << "+";
- if (MI->getOperand(opNum+1).isGlobal() ||
- MI->getOperand(opNum+1).isCPI()) {
- O << "%lo(";
- printOperand(MI, opNum+1, O);
- O << ")";
- } else {
- printOperand(MI, opNum+1, O);
- }
-}
-
-bool OR1KAsmPrinter::printGetPCX(const MachineInstr *MI, unsigned opNum,
- raw_ostream &O) {
- std::string operand = "";
- const MachineOperand &MO = MI->getOperand(opNum);
- switch (MO.getType()) {
- default: llvm_unreachable("Operand is not a register");
- case MachineOperand::MO_Register:
- assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
- "Operand is not a physical register ");
- operand = "%" + StringRef(getRegisterName(MO.getReg())).lower();
- break;
- }
-
- unsigned mfNum = MI->getParent()->getParent()->getFunctionNumber();
- unsigned bbNum = MI->getParent()->getNumber();
-
- O << '\n' << ".LLGETPCH" << mfNum << '_' << bbNum << ":\n";
- O << "\tcall\t.LLGETPC" << mfNum << '_' << bbNum << '\n' ;
-
- O << "\t sethi\t"
- << "%hi(_GLOBAL_OFFSET_TABLE_+(.-.LLGETPCH" << mfNum << '_' << bbNum
- << ")), " << operand << '\n' ;
-
- O << ".LLGETPC" << mfNum << '_' << bbNum << ":\n" ;
- O << "\tor\t" << operand
- << ", %lo(_GLOBAL_OFFSET_TABLE_+(.-.LLGETPCH" << mfNum << '_' << bbNum
- << ")), " << operand << '\n';
- O << "\tadd\t" << operand << ", %o7, " << operand << '\n';
-
- return true;
-}
-
-void OR1KAsmPrinter::printCCOperand(const MachineInstr *MI, int opNum,
- raw_ostream &O) {
-}
-
-/// PrintAsmOperand - Print out an operand for an inline asm expression.
-///
-bool OR1KAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
- unsigned AsmVariant,
- const char *ExtraCode,
- raw_ostream &O) {
- if (ExtraCode && ExtraCode[0]) {
- if (ExtraCode[1] != 0) return true; // Unknown modifier.
-
- switch (ExtraCode[0]) {
- default: return true; // Unknown modifier.
- case 'r':
- break;
- }
- }
-
- printOperand(MI, OpNo, O);
-
- return false;
-}
-
-bool OR1KAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
- unsigned OpNo, unsigned AsmVariant,
- const char *ExtraCode,
- raw_ostream &O) {
- if (ExtraCode && ExtraCode[0])
- return true; // Unknown modifier
-
- O << '[';
- printMemOperand(MI, OpNo, O);
- O << ']';
-
- return false;
-}
+//===----------------------------------------------------------------------===//
+void OR1KAsmPrinter::EmitInstruction(const MachineInstr *MI) {
+ OR1KMCInstLower MCInstLowering(OutContext, *Mang, *this);
-/// isBlockOnlyReachableByFallthough - Return true if the basic block has
-/// exactly one predecessor and the control transfer mechanism between
-/// the predecessor and this block is a fall-through.
-///
-/// This overrides AsmPrinter's implementation to handle delay slots.
-bool OR1KAsmPrinter::
-isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const {
- // If this is a landing pad, it isn't a fall through. If it has no preds,
- // then nothing falls through to it.
- if (MBB->isLandingPad() || MBB->pred_empty())
- return false;
-
- // If there isn't exactly one predecessor, it can't be a fall through.
- MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), PI2 = PI;
- ++PI2;
- if (PI2 != MBB->pred_end())
- return false;
-
- // The predecessor has to be immediately before this block.
- const MachineBasicBlock *Pred = *PI;
-
- if (!Pred->isLayoutSuccessor(MBB))
- return false;
-
- // Check if the last terminator is an unconditional branch.
- MachineBasicBlock::const_iterator I = Pred->end();
- while (I != Pred->begin() && !(--I)->getDesc().isTerminator())
- ; // Noop
- return I == Pred->end() || !I->getDesc().isBarrier();
+ MCInst TmpInst;
+ MCInstLowering.Lower(MI, TmpInst);
+ OutStreamer.EmitInstruction(TmpInst);
}
-
-
// Force static initialization.
-extern "C" void LLVMInitializeOR1KAsmPrinter() {
+extern "C" void LLVMInitializeOR1KAsmPrinter() {
RegisterAsmPrinter<OR1KAsmPrinter> X(TheOR1KTarget);
}
View
2 lib/Target/OR1K/OR1KDelaySlotFiller.cpp
@@ -70,7 +70,7 @@ bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
if (I->getDesc().hasDelaySlot()) {
MachineBasicBlock::iterator J = I;
++J;
- BuildMI(MBB, J, DebugLoc(), TII->get(OR1K::NOP));
+ BuildMI(MBB, J, DebugLoc(), TII->get(OR1K::NOP)).addImm(0);
++FilledSlots;
Changed = true;
}
View
4 lib/Target/OR1K/OR1KISelDAGToDAG.cpp
@@ -1,4 +1,4 @@
-//===-- OR1KISelDAGToDAG.cpp - A dag to dag inst selector for OR1K ----===//
+//===-- OR1KISelDAGToDAG.cpp - A dag to dag inst selector for OR1K --------===//
//
// The LLVM Compiler Infrastructure
//
@@ -11,7 +11,7 @@
//
//===----------------------------------------------------------------------===//
-#define DEBUG_TYPE "mblaze-isel"
+#define DEBUG_TYPE "or1k-isel"
#include "OR1K.h"
#include "OR1KMachineFunctionInfo.h"
#include "OR1KRegisterInfo.h"
View
18 lib/Target/OR1K/OR1KISelLowering.cpp
@@ -1,4 +1,4 @@
-//===-- OR1KISelLowering.cpp - OR1K DAG Lowering Implementation -------===//
+//===-- OR1KISelLowering.cpp - OR1K DAG Lowering Implementation -----------===//
//
// The LLVM Compiler Infrastructure
//
@@ -567,15 +567,11 @@ LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<SDValue> &OutVals,
DebugLoc dl, SelectionDAG &DAG) const {
- return DAG.getNode(OR1KISD::Ret, dl, MVT::Other,
- Chain, DAG.getRegister(OR1K::R15, MVT::i32));
-#if 0
- // CCValAssign - represent the assignment of
- // the return value to a location
+ // CCValAssign - represent the assignment of the return value to a location
SmallVector<CCValAssign, 16> RVLocs;
// CCState - Info about the registers and stack slot.
- CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
+ CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), getTargetMachine(),
RVLocs, *DAG.getContext());
// Analize return values.
@@ -604,14 +600,10 @@ LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
Flag = Chain.getValue(1);
}
- // Return on OR1K is always a "rtsd R15, 8"
if (Flag.getNode())
- return DAG.getNode(OR1KISD::Ret, dl, MVT::Other,
- Chain, DAG.getRegister(OR1K::R15, MVT::i32), Flag);
+ return DAG.getNode(OR1KISD::Ret, dl, MVT::Other, Chain, Flag);
else // Return Void
- return DAG.getNode(OR1KISD::Ret, dl, MVT::Other,
- Chain, DAG.getRegister(OR1K::R15, MVT::i32));
-#endif
+ return DAG.getNode(OR1KISD::Ret, dl, MVT::Other, Chain);
}
//===----------------------------------------------------------------------===//
View
21 lib/Target/OR1K/OR1KInstrInfo.cpp
@@ -1,4 +1,4 @@
-//===- OR1KInstrInfo.cpp - OR1K Instruction Information -------*- C++ -*-===//
+//===-- OR1KInstrInfo.cpp - OR1K Instruction Information -------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@@ -82,24 +82,21 @@ OR1KInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB);
return 1;
}
+#endif
void OR1KInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator I, DebugLoc DL,
- unsigned DestReg, unsigned SrcReg,
- bool KillSrc) const {
- if (SP::IntRegsRegClass.contains(DestReg, SrcReg))
- BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0)
- .addReg(SrcReg, getKillRegState(KillSrc));
- else if (SP::FPRegsRegClass.contains(DestReg, SrcReg))
- BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)
- .addReg(SrcReg, getKillRegState(KillSrc));
- else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg))
- BuildMI(MBB, I, DL, get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD), DestReg)
+ MachineBasicBlock::iterator I, DebugLoc DL,
+ unsigned DestReg, unsigned SrcReg,
+ bool KillSrc) const {
+ if (OR1K::GPRRegClass.contains(DestReg, SrcReg))
+ BuildMI(MBB, I, DL, get(OR1K::OR), DestReg)
+ .addReg(SrcReg, getKillRegState(KillSrc))
.addReg(SrcReg, getKillRegState(KillSrc));
else
llvm_unreachable("Impossible reg-to-reg copy");
}
+#if 0
void OR1KInstrInfo::
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned SrcReg, bool isKill, int FI,
View
3 lib/Target/OR1K/OR1KInstrInfo.h
@@ -71,12 +71,11 @@ class OR1KInstrInfo : public OR1KGenInstrInfo {
DebugLoc DL) const;
*/
-/*
virtual void copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, DebugLoc DL,
unsigned DestReg, unsigned SrcReg,
bool KillSrc) const;
-*/
+
/*
virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
View
56 lib/Target/OR1K/OR1KInstrInfo.td
@@ -1,4 +1,4 @@
-//===- OR1KInstrInfo.td - Target Description for OR1K Target ------------===//
+//===-- OR1KInstrInfo.td - Target Description for OR1K Target -------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -51,7 +51,7 @@ def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_OR1KCallSeqEnd,
class SF_RR<bits<5> op2Val, string asmstr>
: InstRR<0x9, (outs), (ins GPR:$rA, GPR:$rB),
- !strconcat(asmstr, " $rA, $rB"), []>
+ !strconcat(asmstr, "\t$rA, $rB"), []>
{
bits<5> op2;
bits<5> rA;
@@ -66,7 +66,7 @@ class SF_RR<bits<5> op2Val, string asmstr>
class SF_RI<bits<5> op2Val, string asmstr>
: InstRI<0xf, (outs), (ins GPR:$rA, i16imm:$imm),
- !strconcat(asmstr, "i $rA, $imm"), []>
+ !strconcat(asmstr, "i\t$rA, $imm"), []>
{
bits<5> op2;
bits<5> rA;
@@ -105,7 +105,7 @@ defm SFLES : SF<0xd, "l.sfles">;
class ALU_RI<bits<4> subOp, string asmstr, SDNode OpNode>
: InstRI<subOp, (outs GPR:$rD), (ins GPR:$rA, i32imm:$imm16),
- !strconcat(asmstr, "$rD, $rA, $imm16"),
+ !strconcat(asmstr, "\t$rD, $rA, $imm16"),
[(set GPR:$rD, (OpNode GPR:$rA, imm_s16:$imm16))]>
{
bits<5> rD;
@@ -128,7 +128,7 @@ def MULI : ALU_RI<0xc, "l.muli", mul>;
class ALU_RR<bits<4> subOp, string asmstr, SDNode OpNode>
: InstRR<0x8, (outs GPR:$rD), (ins GPR:$rA, GPR:$rB),
- !strconcat(asmstr, "$rD, $rA, $rB"),
+ !strconcat(asmstr, "\t$rD, $rA, $rB"),
[(set GPR:$rD, (OpNode GPR:$rA, GPR:$rB))]>
{
bits<5> rD;
@@ -148,13 +148,16 @@ class ALU_RR<bits<4> subOp, string asmstr, SDNode OpNode>
let op3 = subOp;
}
+let isCommutable=1 in {
def ADD : ALU_RR<0x0, "l.add", add>;
def ADDC : ALU_RR<0x1, "l.addc", add>;
-def SUB : ALU_RR<0x2, "l.sub", sub>;
def AND : ALU_RR<0x3, "l.and", and>;
def OR : ALU_RR<0x4, "l.or", or>;
def XOR : ALU_RR<0x5, "l.xor", xor>;
def MUL : ALU_RR<0x6, "l.mul", mul>;
+}
+
+def SUB : ALU_RR<0x2, "l.sub", sub>;
// -------------------------------------------------- //
@@ -163,7 +166,7 @@ def MUL : ALU_RR<0x6, "l.mul", mul>;
class SHIFT_RR<bits<2> op2Val, string asmstr, SDNode OpNode>
: InstRR<0x8, (outs GPR:$rD), (ins GPR:$rA, GPR:$rB),
- !strconcat(asmstr, " $rD, $rA, $rB"),
+ !strconcat(asmstr, "\t$rD, $rA, $rB"),
[(set GPR:$rD, (OpNode GPR:$rA, GPR:$rB))]>
{
bits<5> rD;
@@ -188,7 +191,7 @@ class SHIFT_RR<bits<2> op2Val, string asmstr, SDNode OpNode>
class SHIFT_RI<bits<2> op2Val, string asmstr, SDNode OpNode>
: InstRI<0xE, (outs GPR:$rD), (ins GPR:$rA, i32imm:$imm),
- !strconcat(asmstr, "i $rD, $rA, $imm"),
+ !strconcat(asmstr, "i\t$rD, $rA, $imm"),
[(set GPR:$rD, (OpNode GPR:$rA, imm_z6:$imm))]>
{
bits<5> rD;
@@ -224,7 +227,7 @@ defm ROR : SHIFT<0x3, "l.ror", rotr>;
/*class STORE<bits<4> subOp, string asmstring>
: InstRR<subOp, (outs), (ins GPR:$rD, GPR:$rB, i16imm:$offset),
- !strconcat(asmstring, " ($offset)$rA, $rB"),
+ !strconcat(asmstring, "\t($offset)$rA, $rB"),
[(store ...)]>
{
bits<5> rD;
@@ -249,7 +252,7 @@ def SH : STORE<0x7, "l.sh">;
class LOAD:<bits<4> subop, string asmstring>
: InstRI<subop, (outs GPR:$rD), (ins GPR:$rA, i16imm:$offset),
- !strconcat(asmstring, " $rA, ($offset)$rb")),
+ !strconcat(asmstring, "\t$rA, ($offset)$rb")),
[(load ...)]]>
{
bits<5> rD;
@@ -279,7 +282,7 @@ def LHS : LOAD<0x6, "l.lhs">;
class BRANCH<bits<4> subOp, string asmstring>
: InstBR<subOp, (outs), (ins i32imm:$imm),
- !strconcat(asmstring, " $imm"),
+ !strconcat(asmstring, "\t$imm"),
[]>
{
bits<26> imm26;
@@ -296,7 +299,7 @@ def BF : BRANCH<0x3, "l.bf">;
class BRANCH_R<bits<4> subOp, string asmstring>
: InstBR<subOp, (outs), (ins GPR:$rB),
- !strconcat(asmstring, " $rB"),
+ !strconcat(asmstring, "\t$rB"),
[]>
{
bits<5> rB;
@@ -328,7 +331,7 @@ def RFE :
class NOP_I<bits<2> op2Val, string asmstr>
: InstRI<0x5, (outs), (ins i16imm:$imm),
- !strconcat(asmstr, " $imm"), []>
+ !strconcat(asmstr, "\t$imm"), []>
{
bits<2> op2;
bits<16> imm16;
@@ -344,24 +347,21 @@ let neverHasSideEffects = 1 in
let isReturn = 1, isTerminator = 1, hasDelaySlot=1, isBarrier = 1 in {
def RET : InstBR<0x1, (outs), (ins),
- "l.jr r9",
+ "l.jr\tr9",
[(retflag)]>;
}
-// Pseudo instructions.
-class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
- : InstOR1K<outs, ins, asmstr, pattern>;
-
-
-
-// As stack alignment is always done with addiu, we need a 16-bit immediate
+// ADJCALLSTACKDOWN/UP implicitly use/def R1 because they may be expanded into
+// a stack adjustment and the codegen must know that they may modify the stack
+// pointer before prolog-epilog rewriting occurs.
+// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
+// sub / add which can clobber R1.
let Defs = [R1], Uses = [R1] in {
-def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
- "${:comment} ADJCALLSTACKDOWN $amt",
- [(callseq_start timm:$amt)]>;
-def ADJCALLSTACKUP : Pseudo<(outs),
- (ins i32imm:$amt1, i32imm:$amt2),
- "${:comment} ADJCALLSTACKUP $amt1",
- [(callseq_end timm:$amt1, timm:$amt2)]>;
+def ADJCALLSTACKDOWN : InstOR1K<(outs), (ins i32imm:$amt),
+ "#ADJCALLSTACKDOWN",
+ [(callseq_start timm:$amt)]>;
+def ADJCALLSTACKUP : InstOR1K<(outs), (ins i32imm:$amt1, i32imm:$amt2),
+ "#ADJCALLSTACKUP",
+ [(callseq_end timm:$amt1, timm:$amt2)]>;
}
View
58 lib/Target/OR1K/OR1KMCInstLower.cpp
@@ -0,0 +1,58 @@
+//=-- OR1KMCInstLower.cpp - Convert OR1K MachineInstr to an MCInst ----------=//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains code to lower OR1K MachineInstrs to their corresponding
+// MCInst records.
+//
+//===----------------------------------------------------------------------===//
+
+#include "OR1KMCInstLower.h"
+#include "llvm/CodeGen/AsmPrinter.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/MC/MCAsmInfo.h"
+#include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCExpr.h"
+#include "llvm/MC/MCInst.h"
+#include "llvm/Target/Mangler.h"
+#include "llvm/Support/raw_ostream.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/ADT/SmallString.h"
+using namespace llvm;
+
+void OR1KMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
+ OutMI.setOpcode(MI->getOpcode());
+
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ const MachineOperand &MO = MI->getOperand(i);
+
+ MCOperand MCOp;
+ switch (MO.getType()) {
+ default:
+ MI->dump();
+ llvm_unreachable("unknown operand type");
+ case MachineOperand::MO_Register:
+ // Ignore all implicit register operands.
+ if (MO.isImplicit()) continue;
+ MCOp = MCOperand::CreateReg(MO.getReg());
+ break;
+ case MachineOperand::MO_Immediate:
+ MCOp = MCOperand::CreateImm(MO.getImm());
+ break;
+ case MachineOperand::MO_MachineBasicBlock:
+ MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create(
+ MO.getMBB()->getSymbol(), Ctx));
+ break;
+ case MachineOperand::MO_RegisterMask:
+ continue;
+ }
+
+ OutMI.addOperand(MCOp);
+ }
+}
View
41 lib/Target/OR1K/OR1KMCInstLower.h
@@ -0,0 +1,41 @@
+//===-- OR1KMCInstLower.h - Lower MachineInstr to MCInst --------*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef OR1K_MCINSTLOWER_H
+#define OR1K_MCINSTLOWER_H
+
+#include "llvm/Support/Compiler.h"
+
+namespace llvm {
+ class AsmPrinter;
+ class MCContext;
+ class MCInst;
+ class MCOperand;
+ class MCSymbol;
+ class MachineInstr;
+ class MachineModuleInfoMachO;
+ class MachineOperand;
+ class Mangler;
+
+ /// OR1KMCInstLower - This class is used to lower an MachineInstr
+ /// into an MCInst.
+class LLVM_LIBRARY_VISIBILITY OR1KMCInstLower {
+ MCContext &Ctx;
+ Mangler &Mang;
+
+ AsmPrinter &Printer;
+public:
+ OR1KMCInstLower(MCContext &ctx, Mangler &mang, AsmPrinter &printer)
+ : Ctx(ctx), Mang(mang), Printer(printer) {}
+ void Lower(const MachineInstr *MI, MCInst &OutMI) const;
+};
+
+}
+
+#endif
View
14 lib/Target/OR1K/OR1KMachineFunctionInfo.cpp
@@ -0,0 +1,14 @@
+//===-- OR1KMachineFuctionInfo.cpp - OR1K machine function info ---===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "OR1KMachineFunctionInfo.h"
+
+using namespace llvm;
+
+void OR1KMachineFunctionInfo::anchor() { }
View
37 lib/Target/OR1K/OR1KMachineFunctionInfo.h
@@ -1,4 +1,4 @@
-//===- OR1KMachineFunctionInfo.h - OR1K Machine Function Info -*- C++ -*-===//
+//===- OR1KMachineFuctionInfo.h - OR1K machine func info ---------*- C++ -*-==//
//
// The LLVM Compiler Infrastructure
//
@@ -7,36 +7,27 @@
//
//===----------------------------------------------------------------------===//
//
-// This file declares OR1K specific per-machine-function information.
+// This file declares OR1K-specific per-machine-function information.
//
//===----------------------------------------------------------------------===//
-#ifndef SPARCMACHINEFUNCTIONINFO_H
-#define SPARCMACHINEFUNCTIONINFO_H
+
+#ifndef OR1KMACHINEFUNCTIONINFO_H
+#define OR1KMACHINEFUNCTIONINFO_H
#include "llvm/CodeGen/MachineFunction.h"
namespace llvm {
- class OR1KMachineFunctionInfo : public MachineFunctionInfo {
- private:
-/*
- unsigned GlobalBaseReg;
-
- /// VarArgsFrameOffset - Frame offset to start of varargs area.
- int VarArgsFrameOffset;
-*/
- public:
- OR1KMachineFunctionInfo() {}
- explicit OR1KMachineFunctionInfo(MachineFunction &MF) {}
+/// OR1KMachineFunctionInfo - This class is derived from MachineFunction and
+/// contains private OR1K target-specific information for each MachineFunction.
+class OR1KMachineFunctionInfo : public MachineFunctionInfo {
+ virtual void anchor();
+public:
+ OR1KMachineFunctionInfo() {}
-/*
- unsigned getGlobalBaseReg() const { return GlobalBaseReg; }
- void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; }
+ explicit OR1KMachineFunctionInfo(MachineFunction &MF) {}
+};
- int getVarArgsFrameOffset() const { return VarArgsFrameOffset; }
- void setVarArgsFrameOffset(int Offset) { VarArgsFrameOffset = Offset; }
-*/
- };
-}
+} // End llvm namespace
#endif
View
13 lib/Target/OR1K/OR1KRegisterInfo.cpp
@@ -1,4 +1,4 @@
-//===- OR1KRegisterInfo.cpp - OR1K Register Information -------*- C++ -*-===//
+//===-- OR1KRegisterInfo.cpp - OR1K Register Information --------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@@ -19,10 +19,12 @@
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineLocation.h"
#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Target/TargetFrameLowering.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Type.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h"
+
#define GET_REGINFO_TARGET_DESC
#include "OR1KGenRegisterInfo.inc"
using namespace llvm;
@@ -44,9 +46,12 @@ OR1KRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
BitVector OR1KRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
BitVector Reserved(getNumRegs());
+ const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
+
Reserved.set(OR1K::R0);
Reserved.set(OR1K::R1);
- Reserved.set(OR1K::R2);
+ if (TFI->hasFP(MF))
+ Reserved.set(OR1K::R2);
Reserved.set(OR1K::R9);
Reserved.set(OR1K::R10);
Reserved.set(OR1K::R11);
@@ -84,7 +89,9 @@ unsigned OR1KRegisterInfo::getRARegister() const {
}
unsigned OR1KRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
- return 0;
+ const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
+
+ return TFI->hasFP(MF) ? OR1K::R2 : OR1K::R1;
}
unsigned OR1KRegisterInfo::getEHExceptionRegister() const {
View
66 lib/Target/OR1K/OR1KRegisterInfo.td
@@ -49,38 +49,38 @@ def FCC : SparcCtrlReg<"FCC">;
*/
// Integer registers
-def R0 : Ri< 0, "R0">, DwarfRegNum<[0]>;
-def R1 : Ri< 1, "R1">, DwarfRegNum<[1]>;
-def R2 : Ri< 2, "R2">, DwarfRegNum<[2]>;
-def R3 : Ri< 3, "R3">, DwarfRegNum<[3]>;
-def R4 : Ri< 4, "R4">, DwarfRegNum<[4]>;
-def R5 : Ri< 5, "R5">, DwarfRegNum<[5]>;
-def R6 : Ri< 6, "R6">, DwarfRegNum<[6]>;
-def R7 : Ri< 7, "R7">, DwarfRegNum<[7]>;
-def R8 : Ri< 8, "R8">, DwarfRegNum<[8]>;
-def R9 : Ri< 9, "R9">, DwarfRegNum<[9]>;
-def R10 : Ri<10, "R10">, DwarfRegNum<[10]>;
-def R11 : Ri<11, "R11">, DwarfRegNum<[11]>;
-def R12 : Ri<12, "R12">, DwarfRegNum<[12]>;
-def R13 : Ri<13, "R13">, DwarfRegNum<[13]>;
-def R14 : Ri<14, "R14">, DwarfRegNum<[14]>;
-def R15 : Ri<15, "R15">, DwarfRegNum<[15]>;
-def R16 : Ri<16, "R16">, DwarfRegNum<[16]>;
-def R17 : Ri<17, "R17">, DwarfRegNum<[17]>;
-def R18 : Ri<18, "R18">, DwarfRegNum<[18]>;
-def R19 : Ri<19, "R19">, DwarfRegNum<[19]>;
-def R20 : Ri<20, "R20">, DwarfRegNum<[20]>;
-def R21 : Ri<21, "R21">, DwarfRegNum<[21]>;
-def R22 : Ri<22, "R22">, DwarfRegNum<[22]>;
-def R23 : Ri<23, "R23">, DwarfRegNum<[23]>;
-def R24 : Ri<24, "R24">, DwarfRegNum<[24]>;
-def R25 : Ri<25, "R25">, DwarfRegNum<[25]>;
-def R26 : Ri<26, "R26">, DwarfRegNum<[26]>;
-def R27 : Ri<27, "R27">, DwarfRegNum<[27]>;
-def R28 : Ri<28, "R28">, DwarfRegNum<[28]>;
-def R29 : Ri<29, "R29">, DwarfRegNum<[29]>;
-def R30 : Ri<30, "R30">, DwarfRegNum<[30]>;
-def R31 : Ri<31, "R31">, DwarfRegNum<[31]>;
+def R0 : Ri< 0, "r0">, DwarfRegNum<[0]>;
+def R1 : Ri< 1, "r1">, DwarfRegNum<[1]>;
+def R2 : Ri< 2, "r2">, DwarfRegNum<[2]>;
+def R3 : Ri< 3, "r3">, DwarfRegNum<[3]>;
+def R4 : Ri< 4, "r4">, DwarfRegNum<[4]>;
+def R5 : Ri< 5, "r5">, DwarfRegNum<[5]>;
+def R6 : Ri< 6, "r6">, DwarfRegNum<[6]>;
+def R7 : Ri< 7, "r7">, DwarfRegNum<[7]>;
+def R8 : Ri< 8, "r8">, DwarfRegNum<[8]>;
+def R9 : Ri< 9, "r9">, DwarfRegNum<[9]>;
+def R10 : Ri<10, "r10">, DwarfRegNum<[10]>;
+def R11 : Ri<11, "r11">, DwarfRegNum<[11]>;
+def R12 : Ri<12, "r12">, DwarfRegNum<[12]>;
+def R13 : Ri<13, "r13">, DwarfRegNum<[13]>;
+def R14 : Ri<14, "r14">, DwarfRegNum<[14]>;
+def R15 : Ri<15, "r15">, DwarfRegNum<[15]>;
+def R16 : Ri<16, "r16">, DwarfRegNum<[16]>;
+def R17 : Ri<17, "r17">, DwarfRegNum<[17]>;
+def R18 : Ri<18, "r18">, DwarfRegNum<[18]>;
+def R19 : Ri<19, "r19">, DwarfRegNum<[19]>;
+def R20 : Ri<20, "r20">, DwarfRegNum<[20]>;
+def R21 : Ri<21, "r21">, DwarfRegNum<[21]>;
+def R22 : Ri<22, "r22">, DwarfRegNum<[22]>;
+def R23 : Ri<23, "r23">, DwarfRegNum<[23]>;
+def R24 : Ri<24, "r24">, DwarfRegNum<[24]>;
+def R25 : Ri<25, "r25">, DwarfRegNum<[25]>;
+def R26 : Ri<26, "r26">, DwarfRegNum<[26]>;
+def R27 : Ri<27, "r27">, DwarfRegNum<[27]>;
+def R28 : Ri<28, "r28">, DwarfRegNum<[28]>;
+def R29 : Ri<29, "r29">, DwarfRegNum<[29]>;
+def R30 : Ri<30, "r30">, DwarfRegNum<[30]>;
+def R31 : Ri<31, "r31">, DwarfRegNum<[31]>;
/*
@@ -152,7 +152,7 @@ def GPR : RegisterClass<"OR1K", [i32], 32, (add R3, R4, R5, R6, R7,
R1, // stack ptr
R2, // frame ptr
R9, // link register
- R0 // constant 0
+ R0 // constant 0
)>;
/*

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