A HLS tool to synthesize verilog from epsilon
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docs
epsilon
examples
verilog
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README
build_depend_doc.sh

README

epsilon-to-verilog is a minimalistic educational hardware compiler developed as a course project for EE677 at IIT Bombay.

To get started with this tool, refer to docs/ folder
Also, you can get screenshots showing what to do and how to use from the [Downloads](https://github.com/savvy2020/epsilon-to-verilog/downloads) page of the repo.

(On Ubuntu running
$ chmod +x build_depend_doc.sh
$ ./build_depend_doc.sh
will install all the dependencies and make the docuementation)
Append the PYTHONPATH environment variable with the complete path of the core/ folder
	cd verilog
	python main.py -i ../examples/sum_till_n.epsilon

This would result in two verilog files being generated: "sum_till_n.v"
and "sum_till_n.testbench.v" in the examples/ folder. To test the correctness
of the generated verilog files, execute "iverilog sum_till_n.testbench.v"
This would result in a binary file and a vcd file.