RISCV-Simulator implemented in C++. Support RV32I ISA.
For a full report on how I made this simulator, refer to Make You a RISC-V Simulator (PDF, Chinese)
For statistics and reports on sample programs, refer to Travis-CI build log.
This branch simulates a RISC-V CPU of 2 stage: issue and execute, which supports out-of-order execution.
It implements out-of-order execution with Tomasulo algorithm. For branch, It applies hardware speculation to speculate the following instructions. 3 load buffer, 3 store buffer, 4 ALU unit, and a 12-entry reorder buffer. Use Two-level adaptive predictor for branch prediction.
Note that since I was unable to design the equivalent circuit, this branch just shows a programmer's way to illustrate out-of-order execution design.
|seq||A sequential implementation. First edition. No feed forward.|
|feedforward||Second edition. Based on seq. Feeding forward runs faster. (Though I don't like it.)|
|pipeline||Pipelined version. Based on seq. Handle hazard by forwarding. Two-level adaptive predictor.|
|out-of-order||Out-of-order execution with Tomasulo algorithm and Speculation.|
|master||For online judge|