From c48d56917c90f64f96deefef0441e9c3593a890e Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Thu, 8 Feb 2024 16:07:27 -0800 Subject: [PATCH] adding support for hardware/AbacoPc821 --- .../AbacoPc821/pcie/ip/AbacoPc821PciePhy.dcp | 3 + .../AbacoPc821/pcie/ip/AbacoPc821PciePhy.xci | 1575 +++++++++++++++++ .../AbacoPc821/pcie/ip/AbacoPc821PciePhy.xdc | 204 +++ .../pcie/rtl/AbacoPc821PciePhyWrapper.vhd | 328 ++++ hardware/AbacoPc821/pcie/ruckus.tcl | 13 + hardware/AbacoPc821/rtl/AbacoPc821Core.vhd | 297 ++++ hardware/AbacoPc821/rtl/KU085/AxiPciePkg.vhd | 42 + hardware/AbacoPc821/rtl/KU115/AxiPciePkg.vhd | 42 + hardware/AbacoPc821/ruckus.tcl | 28 + hardware/AbacoPc821/xdc/AbacoPc821App.xdc | 9 + hardware/AbacoPc821/xdc/AbacoPc821Core.xdc | 138 ++ python/axipcie/_PcieAxiVersion.py | 5 +- shared/rtl/AxiPcieSharedPkg.vhd | 37 +- 13 files changed, 2703 insertions(+), 18 deletions(-) create mode 100644 hardware/AbacoPc821/pcie/ip/AbacoPc821PciePhy.dcp create mode 100644 hardware/AbacoPc821/pcie/ip/AbacoPc821PciePhy.xci create mode 100644 hardware/AbacoPc821/pcie/ip/AbacoPc821PciePhy.xdc create mode 100644 hardware/AbacoPc821/pcie/rtl/AbacoPc821PciePhyWrapper.vhd create mode 100644 hardware/AbacoPc821/pcie/ruckus.tcl create mode 100644 hardware/AbacoPc821/rtl/AbacoPc821Core.vhd create mode 100644 hardware/AbacoPc821/rtl/KU085/AxiPciePkg.vhd create mode 100644 hardware/AbacoPc821/rtl/KU115/AxiPciePkg.vhd create mode 100644 hardware/AbacoPc821/ruckus.tcl create mode 100644 hardware/AbacoPc821/xdc/AbacoPc821App.xdc create mode 100644 hardware/AbacoPc821/xdc/AbacoPc821Core.xdc diff --git a/hardware/AbacoPc821/pcie/ip/AbacoPc821PciePhy.dcp b/hardware/AbacoPc821/pcie/ip/AbacoPc821PciePhy.dcp new file mode 100644 index 0000000..2a6f92f --- /dev/null +++ b/hardware/AbacoPc821/pcie/ip/AbacoPc821PciePhy.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:3c19d4c85ce9660825d4f5f04873bcbf92424a33a0895c29ca2ba6e6454bab13 +size 5347355 diff --git a/hardware/AbacoPc821/pcie/ip/AbacoPc821PciePhy.xci b/hardware/AbacoPc821/pcie/ip/AbacoPc821PciePhy.xci new file mode 100644 index 0000000..078aa77 --- /dev/null +++ b/hardware/AbacoPc821/pcie/ip/AbacoPc821PciePhy.xci @@ -0,0 +1,1575 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "AbacoPc821PciePhy", + "component_reference": "xilinx.com:ip:axi_pcie3:3.0", + "ip_revision": "26", + "gen_directory": "../../../../AbacoPc821Ku115DmaLoopback_project.gen/sources_1/ip/AbacoPc821PciePhy", + "parameters": { + "component_parameters": { + "Component_Name": [ { "value": "AbacoPc821PciePhy", "resolve_type": "user", "usage": "all" } ], + "mode_selection": [ { "value": "Advanced", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "device_port_type": [ { "value": "PCI_Express_Endpoint_device", "resolve_type": "user", "usage": "all" } ], + "pcie_blk_locn": [ { "value": "X0Y0", "resolve_type": "user", "usage": "all" } ], + "pl_link_cap_max_link_width": [ { "value": "X8", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "pl_link_cap_max_link_speed": [ { "value": "8.0_GT/s", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "ref_clk_freq": [ { "value": "100_MHz", "resolve_type": "user", "usage": "all" } ], + "axi_addr_width": [ { "value": "40", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "axi_data_width": [ { "value": "256_bit", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "coreclk_freq": [ { "value": "500", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "plltype": [ { "value": "QPLL1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "axisten_freq": [ { "value": "250", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "en_axi_slave_if": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "en_axi_master_if": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "pipe_sim": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "en_ext_ch_gt_drp": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "en_pcie_drp": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "dedicate_perst": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "sys_reset_polarity": [ { "value": "ACTIVE_LOW", "resolve_type": "user", "usage": "all" } ], + "mcap_enablement": [ { "value": "None", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "mcap_fpga_bitstream_version": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "en_debug_ports": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "vu9p_board": [ { "value": "false", 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"value_src": "user", "resolve_type": "user", "usage": "all" } ], + "pf0_device_id": [ { "value": "2030", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "pf0_revision_id": [ { "value": "00", "resolve_type": "user", "usage": "all" } ], + "pf0_subsystem_vendor_id": [ { "value": "1A4A", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "pf0_subsystem_id": [ { "value": "2030", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "pf0_Use_Class_Code_Lookup_Assistant": [ { "value": "false", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "pf0_base_class_menu": [ { "value": "Device_was_built_before_Class_Code_definitions_were_finalized", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "pf0_class_code_base": [ { "value": "11", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "pf0_sub_class_interface_menu": [ { "value": "VGA-compatible_devices", "value_src": "user", "resolve_type": "user", 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true, + "access": "read-only" + }, + "Bridge_info": { + "address_offset": "0x130", + "size": 32, + "display_name": "Bridge info", + "description": "Provide general configuration info about AXI4-Stream Bridge.", + "access": "read-only", + "fields": { + "gen2_capable": { + "bit_offset": 0, + "bit_width": 1, + "display_name": "gen2 capable", + "description": "If set underlying integrated block supports GEN2 speed\n", + "is_volatile": true, + "access": "read-only" + }, + "root_port_present": { + "bit_offset": 1, + "bit_width": 1, + "display_name": "root port present", + "description": "Indicates the underlying integrated block is a Root Port when this bit is set.\n", + "is_volatile": true, + "access": "read-only" + }, + "gen3_capable": { + "bit_offset": 3, + "bit_width": 1, + "display_name": "gen3 capable", + "description": "If set underlying integrated block supports GEN3 speed\n", + "is_volatile": true, + "access": "read-only" + } + } + }, + "Bridge_status_control": { + "address_offset": "0x134", + "size": 32, + "display_name": "Bridge status and control", + "description": "Provides info how read and writes to the core config access aperture are handled", + "access": "read-only", + "fields": { + "global_disable": { + "bit_offset": 8, + "bit_width": 1, + "display_name": "global disable", + "description": "when set disables interrupts line from being asserted. doesn't prevents bitsin interrupt decode register from being set.\n", + "is_volatile": true, + "access": "read-write" + } + } + }, + "interrupt_decode_register": { + "address_offset": "0x138", + "size": 32, + "display_name": "interrupt decode register", + "description": "provide info where Host processor ISR can determine what cause interrupt to be asserted and how to clear it.", + "is_volatile": true, + "access": "read-write", + "fields": { + "Link_down": { + "bit_offset": 0, + "bit_width": 1, + "display_name": "Link down", + "description": "show link-up on PCIe Link was lost. not asserted unless linkup had previously been seen.\n", + "is_volatile": true, + "access": "read-write" + }, + "Hot_Reset": { + "bit_offset": 3, + "bit_width": 1, + "display_name": "Hot Reset", + "description": "indicates a hot reset was detected.\n", + "is_volatile": true, + "access": "read-write" + }, + "Cfg_Completion_Status": { + "bit_offset": 5, + "bit_width": 3, + "display_name": "Cfg Completion Status", + "description": "indicates Cfg Completion Status.\n", + "is_volatile": true, + "access": "read-write" + }, + "Cfg_Timeout": { + "bit_offset": 8, + "bit_width": 1, + "display_name": "Cfg timeout", + "description": "indicates timeout on an ECAM mechanism access. applicable for RP only.\n", + "is_volatile": true, + "access": "read-write" + }, + "Correctable": { + "bit_offset": 9, + "bit_width": 1, + "display_name": "Correctable", + "description": "indicates correctable error msg was received. Applicable for RP only\n", + "is_volatile": true, + "access": "read-write" + }, + "Non_Fatal": { + "bit_offset": 10, + "bit_width": 1, + "display_name": "Non Fatal", + "description": "indicates Non-Fatal error msg was received. Applicable for RP only\n", + "is_volatile": true, + "access": "read-write" + }, + "Fatal": { + "bit_offset": 11, + "bit_width": 1, + "display_name": "Fatal", + "description": "indicates Fatal error msg was received. Applicable for RP only\n", + "is_volatile": true, + "access": "read-write" + }, + "Intx_interrupt_received": { + "bit_offset": 16, + "bit_width": 1, + "display_name": "Intx interrupt received", + "description": "indicates Intx interrupt was received. Applicable for RP only\n", + "is_volatile": true, + "access": "read-write" + }, + "MSI_interrupt_received": { + "bit_offset": 17, + "bit_width": 1, + "display_name": "MSI interrupt received", + "description": "indicates MSI(x) interrupt was received. Applicable for RP only\n", + "is_volatile": true, + "access": "read-write" + }, + "Slave_Unsupported_request": { + "bit_offset": 20, + "bit_width": 1, + "display_name": "Slave Unsupported request", + "description": "indicates that a completion TLP was received with status 0b001- unsupported request.\n", + "is_volatile": true, + "access": "read-write" + }, + "Slave_Unexpected_completion": { + "bit_offset": 21, + "bit_width": 1, + "display_name": "Slave Unexpected completion", + "description": "indicates that a completion TLP was received that was unexpected.\n", + "is_volatile": true, + "access": "read-write" + }, + "Slave_Completion_timeout": { + "bit_offset": 22, + "bit_width": 1, + "display_name": "Slave Completion timeout", + "description": "indicates that a completion TLP for a read request for PCIe was not returned within C_COMP_TIMEOUT parameter.\n", + "is_volatile": true, + "access": "read-write" + }, + "Slave_Error_poison": { + "bit_offset": 23, + "bit_width": 1, + "display_name": "Slave Error Poison", + "description": "indicates that error poison[EP] bit was set in a completion TLP.\n", + "is_volatile": true, + "access": "read-write" + }, + "Slave_completer_abort": { + "bit_offset": 24, + "bit_width": 1, + "display_name": "Slave completer abort", + "description": "indicates that completion TLP was received with status of 0b100-completer abort.\n", + "is_volatile": true, + "access": "read-write" + }, + "Slave_Illegal_burst": { + "bit_offset": 25, + "bit_width": 1, + "display_name": "Slave Illegal Burst", + "description": "indicates that Burst type other than INCR was requested by AXI master.\n", + "is_volatile": true, + "access": "read-write" + }, + "Master_Decerr": { + "bit_offset": 26, + "bit_width": 1, + "display_name": "Master Decerr", + "description": "Indicates a Decoder Error response was received.\n", + "is_volatile": true, + "access": "read-write" + }, + "Master_Slverr": { + "bit_offset": 27, + "bit_width": 1, + "display_name": "Master Slverr", + "description": "Indicates a slaveError response was received.\n", + "is_volatile": true, + "access": "read-write" + } + } + }, + "Interrupt_mask_register": { + "address_offset": "0x13C", + "size": 32, + "display_name": "Interrupt mask register", + "description": "control whether interrupt source can cause the interrupt line to be asserted.", + "is_volatile": true, + "access": "read-write", + "fields": { + "Link_down": { + "bit_offset": 0, + "bit_width": 1, + "display_name": "Link down", + "description": "enables interrupt for Link down events when bit is set.\n", + "is_volatile": true, + "access": "read-write" + }, + "Hot_Reset": { + "bit_offset": 3, + "bit_width": 1, + "display_name": "Hot Reset", + "description": "enables interrupt for hot reset events when bit is set[writable for EP else =0]\n", + "is_volatile": true, + "access": "read-write" + }, + "Cfg_Completion_Status": { + "bit_offset": 5, + "bit_width": 3, + "display_name": "Cfg Completion Status", + "description": "enables interrupt for Cfg Completion Status events when bit is set[writable for RP else =0]\n", + "is_volatile": true, + "access": "read-write" + }, + "Cfg_Timeout": { + "bit_offset": 8, + "bit_width": 1, + "display_name": "Cfg timeout", + "description": "enables interrupt for cfg timeout events when bit is set[writable for RP else =0]\n", + "is_volatile": true, + "access": "read-only" + }, + "Correctable": { + "bit_offset": 9, + "bit_width": 1, + "display_name": "Correctable", + "description": "enables interrupt for correctable events when bit is set[writable for RP else =0]\n", + "is_volatile": true, + "access": "read-only" + }, + "Non_Fatal": { + "bit_offset": 10, + "bit_width": 1, + "display_name": "Non Fatal", + "description": "enables interrupt for non-fatal events when bit is set[writable for RP else =0]\n", + "is_volatile": true, + "access": "read-only" + }, + "Fatal": { + "bit_offset": 11, + "bit_width": 1, + "display_name": "Fatal", + "description": "enables interrupt for fatal events when bit is set[writable for RP else =0]\n", + "is_volatile": true, + "access": "read-only" + }, + "Intx_interrupt_received": { + "bit_offset": 16, + "bit_width": 1, + "display_name": "Intx interrupt received", + "description": "enables interrupt for intx interrupt events when bit is set[writable for RP else =0]\n", + "is_volatile": true, + "access": "read-write" + }, + "MSI_interrupt_received": { + "bit_offset": 17, + "bit_width": 1, + "display_name": "MSI interrupt received", + "description": "enables interrupt for MSI interrupt events when bit is set[writable for RP else =0]\n", + "is_volatile": true, + "access": "read-only" + }, + "Slave_Unsupported_request": { + "bit_offset": 20, + "bit_width": 1, + "display_name": "Slave Unsupported request", + "description": "enables the slave unsupported request interrupt events when bit is set\n", + "is_volatile": true, + "access": "read-write" + }, + "Slave_Unexpected_completion": { + "bit_offset": 21, + "bit_width": 1, + "display_name": "Slave Unexpected completion", + "description": "enables the slave unexpected completion interrupt when bit is set\n", + "is_volatile": true, + "access": "read-write" + }, + "Slave_Completion_timeout": { + "bit_offset": 22, + "bit_width": 1, + "display_name": "Slave Completion timeout", + "description": "enables the slave completion timeout interrupt when bit is set\n", + "is_volatile": true, + "access": "read-write" + }, + "Slave_Error_poison": { + "bit_offset": 23, + "bit_width": 1, + "display_name": "Slave Error Poison", + "description": "enables the slave completion poison interrupt when bit is set\n", + "is_volatile": true, + "access": "read-write" + }, + "Slave_completer_abort": { + "bit_offset": 24, + "bit_width": 1, + "display_name": "Slave completer abort", + "description": "enables the slave completion abort interrupt when bit is set\n", + "is_volatile": true, + "access": "read-write" + }, + "Slave_Illegal_burst": { + "bit_offset": 25, + "bit_width": 1, + "display_name": "Slave Illegal Burst", + "description": "enables the slave illegal burst interrupt when bit is set\n", + "is_volatile": true, + "access": "read-write" + }, + "Master_Decerr": { + "bit_offset": 26, + "bit_width": 1, + "display_name": "Master Decerr", + "description": "enables a master DECERR interrupt when bit is set.\n", + "is_volatile": true, + "access": "read-write" + }, + "Master_Slverr": { + "bit_offset": 27, + "bit_width": 1, + "display_name": "Master Slverr", + "description": "enables a master SLVERR interrupt when bit is set.\n", + "is_volatile": true, + "access": "read-write" + } + } + }, + "bus_location_register": { + "address_offset": "0x140", + "size": 32, + "display_name": "bus location register", + "description": "report the busdevice and function number and the port number for PCIe port.", + "is_volatile": true, + "access": "read-only", + "fields": { + "function_number": { + "bit_offset": 0, + "bit_width": 3, + "display_name": "function number", + "description": "function number for the port for PCIe. hard wired to 0.\n", + "is_volatile": true, + "access": "read-only" + }, + "Device_number": { + "bit_offset": 3, + "bit_width": 5, + "display_name": "device number", + "description": "device number of port for pcie for EP and this is set by RP.\n", + "is_volatile": true, + "access": "read-only" + }, + "Bus_number": { + "bit_offset": 8, + "bit_width": 8, + "display_name": "Bus number", + "description": "bus number for the port for PCIe. this is set by RP.\n", + "is_volatile": true, + "access": "read-only" + }, + "Port_number": { + "bit_offset": 8, + "bit_width": 8, + "display_name": "Port number", + "description": "sets the port number field of the link capabilities register\nEP- always read 0 and is not writable\nRP- is writable\n", + "is_volatile": true, + "access": "read-write" + } + } + }, + "Phy_status_control_register": { + "address_offset": "0x144", + "size": 32, + "display_name": "Phy status control register", + "description": "provide the status current PHY state as well as control of speed and rate switching for gen2 capable.", + "is_volatile": true, + "access": "read-only", + "fields": { + "Link_Rate_is_gen2": { + "bit_offset": 0, + "bit_width": 1, + "display_name": "Link Rate is gen2", + "description": "report the current link rate.\n 0 - 2.5 GT/s(if bit [12]=0),or 8.0 GT/s (if bit[12]=1)\n 1 - 5.0 GT/s \n", + "is_volatile": true, + "access": "read-only" + }, + "Link_Width": { + "bit_offset": 1, + "bit_width": 2, + "display_name": "Link Width", + "description": "report the current link width. 00 = x1, 01 =x2, 10 =x4, 11 =x8. \n", + "is_volatile": true, + "access": "read-only" + }, + "Ltssm_State": { + "bit_offset": 3, + "bit_width": 6, + "display_name": "Ltssm State", + "description": "Report the current LTSSM state. \n", + "is_volatile": true, + "access": "read-only" + }, + "Link_Up": { + "bit_offset": 11, + "bit_width": 1, + "display_name": "Link Up", + "description": "report the current PHY link up state. 1 = link up, 0 = link down \n", + "is_volatile": true, + "access": "read-only" + }, + "Link_Rate_is_gen3": { + "bit_offset": 12, + "bit_width": 1, + "display_name": "Link Rate is gen3", + "description": "report the current link rate. 0 = see bit[0], 1 = 8.0 GT/s \n", + "is_volatile": true, + "access": "read-only" + }, + "Link_Width_is_x16": { + "bit_offset": 13, + "bit_width": 1, + "display_name": "Link Width is x16", + "description": "report the current link width. 0 = see bit[2:1], 1 = x16. \n", + "is_volatile": true, + "access": "read-only" + } + } + }, + "Root_Port_status_control_register": { + "address_offset": "0x148", + "size": 32, + "display_name": "Root Port status control register", + "description": "provide the access to the RP specific status and control. applicable for RP for non-RP cores it return 0 and writes are ignored.", + "is_volatile": true, + "access": "read-only", + "fields": { + "Bridge_Enable": { + "bit_offset": 0, + "bit_width": 1, + "display_name": "Bridge Enable", + "description": "when set allows read/write to axibar. RP software nned to write 1 to this bit when enumeration is done. Bridge clear this when Link up to Link down tarnsition. \n", + "is_volatile": true, + "access": "read-write" + }, + "Error_FIFO_not_empty": { + "bit_offset": 16, + "bit_width": 1, + "display_name": "Error FIFO not empty", + "description": "Indicates that the Root port error FIFO has data to read. \n", + "is_volatile": true, + "access": "read-only" + }, + "Error_FIFO_overflow": { + "bit_offset": 17, + "bit_width": 1, + "display_name": "Error FIFO overflow", + "description": "Indicates that the Root port error FIFO overflowed and an error msg was dropped. writing 1 clears the overflow status.\n", + "is_volatile": true, + "access": "read-write" + }, + "Interrupt_FIFO_not_empty": { + "bit_offset": 18, + "bit_width": 1, + "display_name": "Interrupt FIFO not empty", + "description": "Indicates that the Root port interrupt FIFO has data to read.\n", + "is_volatile": true, + "access": "read-only" + }, + "Interrupt_FIFO_overflow": { + "bit_offset": 19, + "bit_width": 1, + "display_name": "Interrupt FIFO overflow", + "description": "Indicates that the Root port interrupt FIFO overflowed and an interrupt msg was dropped. writting 1 to clear the overflow status.\n", + "is_volatile": true, + "access": "read-write" + } + } + }, + "Root_Port_MSI_base_register_1": { + "address_offset": "0x14C", + "size": 32, + "display_name": "Root Port MSI base register 1", + "description": "provide the access to the RP specific status and control. applicable for RP for non-RP cores it return 0 and writes are ignored.", + "is_volatile": true, + "access": "read-write", + "fields": { + "MSI_Base": { + "bit_offset": 0, + "bit_width": 32, + "display_name": "MSI Base", + "description": "4K alligned address for MSI interrupt.\n", + "is_volatile": true, + "access": "read-write" + } + } + }, + "Root_Port_MSI_base_register_2": { + "address_offset": "0x150", + "size": 32, + "display_name": "Root Port MSI base register 2", + "description": "sets the address window in RP cores used for MSI interrupts. MemWr TLP to address in this range are interpreted as MSI interrupt.", + "is_volatile": true, + "access": "read-write", + "fields": { + "MSI_Base": { + "bit_offset": 0, + "bit_width": 32, + "display_name": "MSI Base", + "description": "4K alligned address for MSI interrupt.\n", + "is_volatile": true, + "access": "read-write" + } + } + }, + "Root_Port_error_FIFO_read_register": { + "address_offset": "0x154", + "size": 32, + "display_name": "Root Port error FIFO read register", + "description": "reads from this location return a queued error(correctable/Non-fatal/Fatal) message.", + "is_volatile": true, + "access": "read-write", + "fields": { + "Requester_ID": { + "bit_offset": 0, + "bit_width": 16, + "display_name": "Requester ID", + "description": "Requester ID belonging to the requester of the error message\n", + "is_volatile": true, + "access": "read-write" + }, + "Error_Type": { + "bit_offset": 16, + "bit_width": 2, + "display_name": "Error Type", + "description": "Indicates the type of error 00b: correctable, 01b: Non-fatal, 10b: Fatal.\n", + "is_volatile": true, + "access": "read-write" + }, + "Error_Valid": { + "bit_offset": 16, + "bit_width": 2, + "display_name": "Error Valid", + "description": "Indicates whether read succeeded 1b: success, 0b: no msg to read.\n", + "is_volatile": true, + "access": "read-write" + } + } + }, + "Root_Port_interrupt_FIFO_read_register_1": { + "address_offset": "0x158", + "size": 32, + "display_name": "Root Port interrupt FIFO read register 1", + "description": "Read from this location return queued interrupt msg. for MSI interrupt payload present in RP interrupt FIFO read 2 register.", + "is_volatile": true, + "access": "read-write", + "fields": { + "Requester_ID": { + "bit_offset": 0, + "bit_width": 16, + "display_name": "Requester ID", + "description": "Requester ID belonging to the requester of the error message\n", + "is_volatile": true, + "access": "read-write" + }, + "MSI_Address": { + "bit_offset": 16, + "bit_width": 11, + "display_name": "MSI Address", + "description": "for MSI interrupts, contain address bits 12:2 from TLP address field.\n", + "is_volatile": true, + "access": "read-write" + }, + "Interrupt_Line": { + "bit_offset": 16, + "bit_width": 11, + "display_name": "Interrupt Line", + "description": "Indicate interrupt line is used. 00b = INTA, 01b = INTB, 10b = INTC, 11b = INTD\n", + "is_volatile": true, + "access": "read-write" + }, + "Interrupt_Assert": { + "bit_offset": 29, + "bit_width": 1, + "display_name": "Interrupt Assert", + "description": "Interrupt Assert or deassert for INTx. 1b = assert, 0b = deassert\n", + "is_volatile": true, + "access": "read-write" + }, + "MSI_Interrupt": { + "bit_offset": 30, + "bit_width": 1, + "display_name": "MSI Interrupt", + "description": "indicates whether interrupt is MSI or INTx. 1b = MSI, 0b = INTx\n", + "is_volatile": true, + "access": "read-write" + }, + "Interrupt_Valid": { + "bit_offset": 31, + "bit_width": 1, + "display_name": "Interrupt Valid", + "description": "indicates whether read succeeded. 1b: success, 0b: no interrupt to read\n", + "is_volatile": true, + "access": "read-write" + } + } + }, + "Root_Port_interrupt_FIFO_read_register_2": { + "address_offset": "0x15C", + "size": 32, + "display_name": "Root Port interrupt FIFO read register 2", + "description": "Read from this location return queued interrupt msg. for MSI interrupt payload present in RP in this register.", + "is_volatile": true, + "access": "read-write", + "fields": { + "Message_Data": { + "bit_offset": 0, + "bit_width": 16, + "display_name": "Message Data", + "description": "payload for MSI messages\n", + "is_volatile": true, + "access": "read-write" + } + } + }, + "Configuration_control_register": { + "address_offset": "0x168", + "size": 32, + "display_name": "Configuration control register", + "description": "allow user application to indicate if correctable or uncorrectable error has occured and report it is respective AER status.", + "is_volatile": true, + "access": "read-write", + "fields": { + "Uncorrectable_Error": { + "bit_offset": 0, + "bit_width": 1, + "display_name": "Uncorrectable Error", + "description": "user app writes 1 to this bit to indicate an uncorrectable error was detected within the user logic that need to reported as an internal error through PCIe AER. In response core set the uncorrected internal error status bit in AER uncorrectable error status register of all enabled function. this error is not considered function specfic.\n", + "is_volatile": true, + "access": "read-write" + }, + "Correctable_Error": { + "bit_offset": 1, + "bit_width": 1, + "display_name": "Correctable Error", + "description": "user app writes 1 to this bit to indicate an correctable error was detected within the user logic that need to reported as an internal error through PCIe AER. In response core set the corrected internal error status bit in AER correctable error status register of all enabled function. this error is not considered function specfic.\n", + "is_volatile": true, + "access": "read-write" + } + } + }, + "VSEC_Capability_register_2": { + "address_offset": "0x200", + "size": 32, + "display_name": "VSEC_Capability_register_2", + "description": "VSEC capability register allows the memory space for the core to appear as though it is part of underlying PCIe configuration space.", + "is_volatile": true, + "access": "read-only", + "fields": { + "VSEC_Capability_ID": { + "bit_offset": 0, + "bit_width": 16, + "display_name": "VSEC Capability ID", + "description": "PCI-SG defined ID identifying this enhanced capability as a Vendor-specific cabalility. HARDCODED to 0x000b\n", + "is_volatile": true, + "access": "read-only" + }, + "Capability_Version": { + "bit_offset": 16, + "bit_width": 4, + "display_name": "Capability Version", + "description": "Version of this capability structure. HARDCODED to 0x01b\n", + "is_volatile": true, + "access": "read-only" + }, + "Next_Capability_offset": { + "bit_offset": 20, + "bit_width": 12, + "display_name": "Next Capability offset", + "description": "offset of next capabilties.\n", + "is_volatile": true, + "access": "read-only" + } + } + }, + "VSEC_Header_register_2": { + "address_offset": "0x204", + "size": 32, + "display_name": "VSEC_Header_register_2", + "description": "provides a unique identifier for the layout and contents of the VSEC structure as well as revision and length.", + "is_volatile": true, + "access": "read-only", + "fields": { + "VSEC_ID": { + "bit_offset": 0, + "bit_width": 16, + "display_name": "VSEC Capability", + "description": "ID value identifying the nature and format of this VSEC structure.\n", + "is_volatile": true, + "access": "read-only" + }, + "VSEC_REV": { + "bit_offset": 16, + "bit_width": 4, + "display_name": "VSEC REV", + "description": "Version of this capability structure. Hardcoded to 0x0\n", + "is_volatile": true, + "access": "read-only" + }, + "VSEC_Lenght": { + "bit_offset": 20, + "bit_width": 11, + "display_name": "VSEC Lenght", + "description": "Length of entire VSEC structure in bytes. Hardcoded to 0x038\n", + "is_volatile": true, + "access": "read-only" + } + } + } + } + } + } + }, + "S_AXI": { + "address_blocks": { + "BAR0": { + "base_address": "0", + "range": "1048576", + "usage": "memory", + "access": "read-write", + "parameters": { + "OFFSET_BASE_PARAM": [ { "value": "axibar_0" } ], + "OFFSET_HIGH_PARAM": [ { "value": "axibar_highaddr_0" } ] + } + } + } + } + } + } + } +} \ No newline at end of file diff --git a/hardware/AbacoPc821/pcie/ip/AbacoPc821PciePhy.xdc b/hardware/AbacoPc821/pcie/ip/AbacoPc821PciePhy.xdc new file mode 100644 index 0000000..8b692af --- /dev/null +++ b/hardware/AbacoPc821/pcie/ip/AbacoPc821PciePhy.xdc @@ -0,0 +1,204 @@ +##----------------------------------------------------------------------------- +## +## (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved. +## +## This file contains confidential and proprietary information +## of Xilinx, Inc. and is protected under U.S. and +## international copyright and other intellectual property +## laws. +## +## DISCLAIMER +## This disclaimer is not a license and does not grant any +## rights to the materials distributed herewith. Except as +## otherwise provided in a valid license issued to you by +## Xilinx, and to the maximum extent permitted by applicable +## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +## (2) Xilinx shall not be liable (whether in contract or tort, +## including negligence, or under any other theory of +## liability) for any loss or damage of any kind or nature +## related to, arising under or in connection with these +## materials, including for any direct, or any indirect, +## special, incidental, or consequential loss or damage +## (including loss of data, profits, goodwill, or any type of +## loss or damage suffered as a result of any action brought +## by a third party) even if such damage or loss was +## reasonably foreseeable or Xilinx had been advised of the +## possibility of the same. +## +## CRITICAL APPLICATIONS +## Xilinx products are not designed or intended to be fail- +## safe, or for use in any application requiring fail-safe +## performance, such as life-support or safety devices or +## systems, Class III medical devices, nuclear facilities, +## applications related to the deployment of airbags, or any +## other applications that could lead to death, personal +## injury, or severe property or environmental damage +## (individually and collectively, "Critical +## Applications"). Customer assumes the sole risk and +## liability of any use of Xilinx products in Critical +## Applications, subject only to applicable laws and +## regulations governing limitations on product liability. +## +## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +## PART OF THIS FILE AT ALL TIMES. +## +##----------------------------------------------------------------------------- +## +## Project : Ultrascale FPGA Gen3 Integrated Block for PCI Express +## File : AbacoPc821PciePhy_pcie3_ip-PCIE_X0Y0.xdc +## Version : 4.4 +##----------------------------------------------------------------------------- +# +############################################################################### +# User Time Names / User Time Groups / Time Specs +############################################################################### +# Family - kintexu +# Part - xcku115 +# Package - flvb1760 +# Speed grade - -2 +############################################################################### +# User Physical Constraints +############################################################################### + +############################################################################### +# Pinout and Related I/O Constraints +############################################################################### +# +# Transceiver instance placement. This constraint selects the +# transceivers to be used, which also dictates the pinout for the +# transmit and receive differential pairs. Please refer to the +# Virtex-7 GT Transceiver User Guide (UG) for more information. +# +############################################################################### +############################################################################### +# Physical Constraints +############################################################################### +############################################################################### +# +# PCI Express Block placement. This constraint selects the PCI Express +# Block to be used. +# +############################################################################### +set_property LOC PCIE_3_1_X0Y0 [get_cells AbacoPc821PciePhy_pcie3_ip_pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/PCIE_3_1_inst] + +############################################################################### +# Buffer (BRAM) Placement Constraints +############################################################################### + +#Request Buffer RAMB Placement + +set_property LOC RAMB18_X16Y2 [get_cells {AbacoPc821PciePhy_pcie3_ip_pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/bram_inst/bram_req_inst/bram_req_8k_inst/RAMB18E2[0].ramb18e2_inst}] +set_property LOC RAMB18_X16Y3 [get_cells {AbacoPc821PciePhy_pcie3_ip_pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/bram_inst/bram_req_inst/bram_req_8k_inst/RAMB18E2[1].ramb18e2_inst}] +set_property LOC RAMB18_X16Y4 [get_cells {AbacoPc821PciePhy_pcie3_ip_pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/bram_inst/bram_req_inst/bram_req_8k_inst/RAMB18E2[2].ramb18e2_inst}] +set_property LOC RAMB18_X16Y5 [get_cells {AbacoPc821PciePhy_pcie3_ip_pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/bram_inst/bram_req_inst/bram_req_8k_inst/RAMB18E2[3].ramb18e2_inst}] + +# Completion Buffer RAMB Placement + +# Extreme - 8 +set_property LOC RAMB18_X16Y8 [get_cells {AbacoPc821PciePhy_pcie3_ip_pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/bram_inst/bram_cpl_inst/CPL_FIFO_16KB.bram_16k_inst/RAMB18E2[0].ramb18e2_inst}] +set_property LOC RAMB18_X16Y9 [get_cells {AbacoPc821PciePhy_pcie3_ip_pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/bram_inst/bram_cpl_inst/CPL_FIFO_16KB.bram_16k_inst/RAMB18E2[1].ramb18e2_inst}] +set_property LOC RAMB18_X16Y10 [get_cells {AbacoPc821PciePhy_pcie3_ip_pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/bram_inst/bram_cpl_inst/CPL_FIFO_16KB.bram_16k_inst/RAMB18E2[2].ramb18e2_inst}] +set_property LOC RAMB18_X16Y11 [get_cells {AbacoPc821PciePhy_pcie3_ip_pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/bram_inst/bram_cpl_inst/CPL_FIFO_16KB.bram_16k_inst/RAMB18E2[3].ramb18e2_inst}] +set_property LOC RAMB18_X16Y12 [get_cells {AbacoPc821PciePhy_pcie3_ip_pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/bram_inst/bram_cpl_inst/CPL_FIFO_16KB.bram_16k_inst/RAMB18E2[4].ramb18e2_inst}] +set_property LOC RAMB18_X16Y13 [get_cells {AbacoPc821PciePhy_pcie3_ip_pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/bram_inst/bram_cpl_inst/CPL_FIFO_16KB.bram_16k_inst/RAMB18E2[5].ramb18e2_inst}] +set_property LOC RAMB18_X16Y14 [get_cells {AbacoPc821PciePhy_pcie3_ip_pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/bram_inst/bram_cpl_inst/CPL_FIFO_16KB.bram_16k_inst/RAMB18E2[6].ramb18e2_inst}] +set_property LOC RAMB18_X16Y15 [get_cells {AbacoPc821PciePhy_pcie3_ip_pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/bram_inst/bram_cpl_inst/CPL_FIFO_16KB.bram_16k_inst/RAMB18E2[7].ramb18e2_inst}] + + +# Replay Buffer RAMB Placement +set_property LOC RAMB36_X16Y9 [get_cells {AbacoPc821PciePhy_pcie3_ip_pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/bram_inst/bram_rep_inst/bram_rep_8k_inst/RAMB36E2[0].ramb36e2_inst}] +set_property LOC RAMB36_X16Y10 [get_cells {AbacoPc821PciePhy_pcie3_ip_pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/bram_inst/bram_rep_inst/bram_rep_8k_inst/RAMB36E2[1].ramb36e2_inst}] + +############################################################################### +# Timing Constraints +############################################################################### + +# TXOUTCLKSEL switches during reset. Set the tool to analyze timing with TXOUTCLKSEL set to 'b101. +set_case_analysis 1 [get_nets AbacoPc821PciePhy_pcie3_ip_gt_top_i/PHY_TXOUTCLKSEL[2]] +set_case_analysis 0 [get_nets AbacoPc821PciePhy_pcie3_ip_gt_top_i/PHY_TXOUTCLKSEL[1]] +set_case_analysis 1 [get_nets AbacoPc821PciePhy_pcie3_ip_gt_top_i/PHY_TXOUTCLKSEL[0]] + + +set_case_analysis 0 [get_pins -filter {REF_PIN_NAME=~TXRATE[0]} -of_objects [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ ADVANCED.GT.* }]] +set_case_analysis 0 [get_pins -filter {REF_PIN_NAME=~RXRATE[0]} -of_objects [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ ADVANCED.GT.* }]] +set_case_analysis 1 [get_pins -filter {REF_PIN_NAME=~TXRATE[1]} -of_objects [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ ADVANCED.GT.* }]] +set_case_analysis 1 [get_pins -filter {REF_PIN_NAME=~RXRATE[1]} -of_objects [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ ADVANCED.GT.* }]] +# +# +# +# Set Divide By 2 +set_case_analysis 1 [get_pins AbacoPc821PciePhy_pcie3_ip_gt_top_i/phy_clk_i/bufg_gt_userclk/DIV[0]] +set_case_analysis 0 [get_pins AbacoPc821PciePhy_pcie3_ip_gt_top_i/phy_clk_i/bufg_gt_userclk/DIV[1]] +set_case_analysis 0 [get_pins AbacoPc821PciePhy_pcie3_ip_gt_top_i/phy_clk_i/bufg_gt_userclk/DIV[2]] +# Set Divide By 2 +set_case_analysis 1 [get_pins AbacoPc821PciePhy_pcie3_ip_gt_top_i/phy_clk_i/bufg_gt_pclk/DIV[0]] +set_case_analysis 0 [get_pins AbacoPc821PciePhy_pcie3_ip_gt_top_i/phy_clk_i/bufg_gt_pclk/DIV[1]] +set_case_analysis 0 [get_pins AbacoPc821PciePhy_pcie3_ip_gt_top_i/phy_clk_i/bufg_gt_pclk/DIV[2]] +# Set Divide By 4 +set_case_analysis 1 [get_pins AbacoPc821PciePhy_pcie3_ip_gt_top_i/bufg_mcap_clk/DIV[0]] +set_case_analysis 1 [get_pins AbacoPc821PciePhy_pcie3_ip_gt_top_i/bufg_mcap_clk/DIV[1]] +set_case_analysis 0 [get_pins AbacoPc821PciePhy_pcie3_ip_gt_top_i/bufg_mcap_clk/DIV[2]] +# Set Divide By 1 +set_case_analysis 0 [get_pins AbacoPc821PciePhy_pcie3_ip_gt_top_i/phy_clk_i/bufg_gt_coreclk/DIV[0]] +set_case_analysis 0 [get_pins AbacoPc821PciePhy_pcie3_ip_gt_top_i/phy_clk_i/bufg_gt_coreclk/DIV[1]] +set_case_analysis 0 [get_pins AbacoPc821PciePhy_pcie3_ip_gt_top_i/phy_clk_i/bufg_gt_coreclk/DIV[2]] +# + +# + +set_false_path -to [get_pins -hier *sync_reg[0]/D] + +#------------------------------------------------------------------------------ +# CDC Registers +#------------------------------------------------------------------------------ +# This path is crossing clock domains between pipe_clk and sys_clk +set_false_path -from [get_pins {AbacoPc821PciePhy_pcie3_ip_gt_top_i/phy_rst_i/prst_n_r_reg_reg/C}] -to [get_pins {AbacoPc821PciePhy_pcie3_ip_gt_top_i/phy_rst_i/sync_prst_n/sync_vec[0].sync_cell_i/sync_reg[0]/D}] +set_false_path -from [get_pins {AbacoPc821PciePhy_pcie3_ip_gt_top_i/phy_rst_i/idle_reg/C}] -to [get_pins {AbacoPc821PciePhy_pcie3_ip_pcie3_uscale_top_inst/init_ctrl_inst/reg_phy_rdy_reg[0]/D}] +# These paths are crossing clock domains between sys_clk and user_clk +set_false_path -from [get_pins {AbacoPc821PciePhy_pcie3_ip_gt_top_i/gt_wizard.gtwizard_top_i/AbacoPc821PciePhy_pcie3_ip_gt_i/inst/gen_gtwizard_gthe3_top.AbacoPc821PciePhy_pcie3_ip_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[*].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[*].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2}] -to [get_pins {AbacoPc821PciePhy_pcie3_ip_gt_top_i/phy_rst_i/sync_phystatus/sync_vec[*].sync_cell_i/sync_reg[0]/D}] +set_false_path -from [get_pins {AbacoPc821PciePhy_pcie3_ip_gt_top_i/gt_wizard.gtwizard_top_i/AbacoPc821PciePhy_pcie3_ip_gt_i/inst/gen_gtwizard_gthe3_top.AbacoPc821PciePhy_pcie3_ip_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[*].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[*].GTHE3_CHANNEL_PRIM_INST/RXUSRCLK2}] -to [get_pins {AbacoPc821PciePhy_pcie3_ip_gt_top_i/phy_rst_i/sync_rxresetdone/sync_vec[*].sync_cell_i/sync_reg[0]/D}] +set_false_path -from [get_pins {AbacoPc821PciePhy_pcie3_ip_gt_top_i/gt_wizard.gtwizard_top_i/AbacoPc821PciePhy_pcie3_ip_gt_i/inst/gen_gtwizard_gthe3_top.AbacoPc821PciePhy_pcie3_ip_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[*].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/gthe3_channel_gen.gen_gthe3_channel_inst[*].GTHE3_CHANNEL_PRIM_INST/TXUSRCLK2}] -to [get_pins {AbacoPc821PciePhy_pcie3_ip_gt_top_i/phy_rst_i/sync_txresetdone/sync_vec[*].sync_cell_i/sync_reg[0]/D}] +#set_clock_groups -name async_sysClk_pclk -asynchronous -group [get_clocks -of_objects [get_pins bufg_gt_sysclk/O]] -group [get_clocks -of_objects [get_pins AbacoPc821PciePhy_pcie3_ip_gt_top_i/phy_clk_i/bufg_gt_pclk/O]] +#set_clock_groups -name async_pclk_sysClk -asynchronous -group [get_clocks -of_objects [get_pins AbacoPc821PciePhy_pcie3_ip_gt_top_i/phy_clk_i/bufg_gt_pclk/O]] -group [get_clocks -of_objects [get_pins bufg_gt_sysclk/O]] + +# Async reset registers +set_false_path -to [get_pins user_lnk_up_reg/CLR] +set_false_path -to [get_pins user_reset_reg/PRE] +# + +#------------------------------------------------------------------------------ +# Asynchronous Pins +#------------------------------------------------------------------------------ +# These pins are not associated with any clock domain + +set_false_path -through [get_pins -filter {REF_PIN_NAME=~RXELECIDLE} -of_objects [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ ADVANCED.GT.* }]] +set_false_path -through [get_pins -filter {REF_PIN_NAME=~PCIEPERST0B} -of_objects [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ ADVANCED.PCIE.* }]] +set_false_path -through [get_pins -filter {REF_PIN_NAME=~PCIERATEGEN3} -of_objects [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ ADVANCED.GT.* }]] +set_false_path -through [get_pins -filter {REF_PIN_NAME=~RXPRGDIVRESETDONE} -of_objects [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ ADVANCED.GT.* }]] +set_false_path -through [get_pins -filter {REF_PIN_NAME=~TXPRGDIVRESETDONE} -of_objects [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ ADVANCED.GT.* }]] +set_false_path -through [get_pins -filter {REF_PIN_NAME=~PCIESYNCTXSYNCDONE} -of_objects [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ ADVANCED.GT.* }]] +set_false_path -through [get_pins -filter {REF_PIN_NAME=~GTPOWERGOOD} -of_objects [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ ADVANCED.GT.* }]] +set_false_path -through [get_pins -filter {REF_PIN_NAME=~CPLLLOCK} -of_objects [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ ADVANCED.GT.* }]] + +set_false_path -through [get_pins -filter {REF_PIN_NAME=~QPLL1LOCK} -of_objects [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ ADVANCED.GT.* }]] + + + + +## Set the clock root on the PCIe clocks to limit skew to the PCIe Hardblock pins. +#set_property USER_CLOCK_ROOT X4Y0 [get_nets -of_objects [get_pins AbacoPc821PciePhy_pcie3_ip_gt_top_i/phy_clk_i/bufg_gt_pclk/O]] +#set_property USER_CLOCK_ROOT X4Y0 [get_nets -of_objects [get_pins AbacoPc821PciePhy_pcie3_ip_gt_top_i/phy_clk_i/bufg_gt_userclk/O]] +#set_property USER_CLOCK_ROOT X4Y0 [get_nets -of_objects [get_pins AbacoPc821PciePhy_pcie3_ip_gt_top_i/phy_clk_i/bufg_gt_coreclk/O]] +#create_waiver -internal -scope -id "TIMING-1" -user "pcie3_uscale" -tag "1019576" -desc " TIMING-1 wavied" +#create_waiver -internal -scope -id "TIMING-3" -user "pcie3_uscale" -tag "1019576" -desc " TIMING-3 wavied" +#create_waiver -internal -scope -id "TIMING-7" -user "pcie3_uscale" -tag "1019576" -desc " TIMING-7 wavied" +#create_waiver -internal -scope -id "RTSTAT-10" -user "pcie3_uscale" -tag "1019576" -desc "RTSTAT-10 wavied" +#create_waiver -internal -scope -id "LUTAR-1" -user "pcie3_uscale" -tag "1019576" -desc "LUTAR-1 wavied" +# + +create_waiver -type CDC -id {CDC-1} -internal -scoped -tags "1019576" -desc "properly_synced" -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter { NAME =~ *pipe_misc_inst/pipe_stages_1.pipe_tx_rate_q_reg[*]}]] -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter { NAME =~ *rxlpmen_i_reg[*]}]] + diff --git a/hardware/AbacoPc821/pcie/rtl/AbacoPc821PciePhyWrapper.vhd b/hardware/AbacoPc821/pcie/rtl/AbacoPc821PciePhyWrapper.vhd new file mode 100644 index 0000000..8216756 --- /dev/null +++ b/hardware/AbacoPc821/pcie/rtl/AbacoPc821PciePhyWrapper.vhd @@ -0,0 +1,328 @@ +------------------------------------------------------------------------------- +-- File : AbacoPc821PciePhyWrapper.vhd +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Wrapper for AXI PCIe Core +------------------------------------------------------------------------------- +-- This file is part of 'axi-pcie-core'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'axi-pcie-core', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiPkg.all; +use surf.AxiLitePkg.all; + +library axi_pcie_core; +use axi_pcie_core.AxiPciePkg.all; + +library unisim; +use unisim.vcomponents.all; + +entity AbacoPc821PciePhyWrapper is + generic ( + TPD_G : time := 1 ns); + port ( + -- AXI4 Interfaces + axiClk : out sl; + axiRst : out sl; + dmaReadMaster : in AxiReadMasterType; + dmaReadSlave : out AxiReadSlaveType; + dmaWriteMaster : in AxiWriteMasterType; + dmaWriteSlave : out AxiWriteSlaveType; + regReadMaster : out AxiReadMasterType; + regReadSlave : in AxiReadSlaveType; + regWriteMaster : out AxiWriteMasterType; + regWriteSlave : in AxiWriteSlaveType; + phyReadMaster : in AxiLiteReadMasterType; + phyReadSlave : out AxiLiteReadSlaveType; + phyWriteMaster : in AxiLiteWriteMasterType; + phyWriteSlave : out AxiLiteWriteSlaveType; + -- Interrupt Interface + dmaIrq : in sl; + -- PCIe Ports + pciRstL : in sl; + pciRefClkP : in sl; + pciRefClkN : in sl; + pciRxP : in slv(7 downto 0); + pciRxN : in slv(7 downto 0); + pciTxP : out slv(7 downto 0); + pciTxN : out slv(7 downto 0)); +end AbacoPc821PciePhyWrapper; + +architecture mapping of AbacoPc821PciePhyWrapper is + + component AbacoPc821PciePhy + port ( + sys_rst_n : in std_logic; + cfg_ltssm_state : out std_logic_vector(5 downto 0); + user_link_up : out std_logic; + axi_ctl_aclk : in std_logic; + sys_clk_gt : in std_logic; + intx_msi_request : in std_logic; + s_axi_awid : in std_logic_vector(AXI_PCIE_CONFIG_C.ID_BITS_C-1 downto 0); + s_axi_awaddr : in std_logic_vector(AXI_PCIE_CONFIG_C.ADDR_WIDTH_C-1 downto 0); + s_axi_awregion : in std_logic_vector(3 downto 0); + s_axi_awlen : in std_logic_vector(AXI_PCIE_CONFIG_C.LEN_BITS_C-1 downto 0); + s_axi_awsize : in std_logic_vector(2 downto 0); + s_axi_awburst : in std_logic_vector(1 downto 0); + s_axi_awvalid : in std_logic; + s_axi_wdata : in std_logic_vector(8*AXI_PCIE_CONFIG_C.DATA_BYTES_C-1 downto 0); + s_axi_wuser : in std_logic_vector(31 downto 0); + s_axi_wstrb : in std_logic_vector(AXI_PCIE_CONFIG_C.DATA_BYTES_C-1 downto 0); + s_axi_wlast : in std_logic; + s_axi_wvalid : in std_logic; + s_axi_bready : in std_logic; + s_axi_arid : in std_logic_vector(AXI_PCIE_CONFIG_C.ID_BITS_C-1 downto 0); + s_axi_araddr : in std_logic_vector(AXI_PCIE_CONFIG_C.ADDR_WIDTH_C-1 downto 0); + s_axi_arregion : in std_logic_vector(3 downto 0); + s_axi_arlen : in std_logic_vector(AXI_PCIE_CONFIG_C.LEN_BITS_C-1 downto 0); + s_axi_arsize : in std_logic_vector(2 downto 0); + s_axi_arburst : in std_logic_vector(1 downto 0); + s_axi_arvalid : in std_logic; + s_axi_rready : in std_logic; + m_axi_awready : in std_logic; + m_axi_wready : in std_logic; + m_axi_bid : in std_logic_vector(2 downto 0); + m_axi_bresp : in std_logic_vector(1 downto 0); + m_axi_bvalid : in std_logic; + m_axi_arready : in std_logic; + m_axi_rid : in std_logic_vector(2 downto 0); + m_axi_rdata : in std_logic_vector(8*AXI_PCIE_CONFIG_C.DATA_BYTES_C-1 downto 0); + m_axi_ruser : in std_logic_vector(31 downto 0); + m_axi_rresp : in std_logic_vector(1 downto 0); + m_axi_rlast : in std_logic; + m_axi_rvalid : in std_logic; + pci_exp_rxp : in std_logic_vector(7 downto 0); + pci_exp_rxn : in std_logic_vector(7 downto 0); + refclk : in std_logic; + s_axi_ctl_awaddr : in std_logic_vector(11 downto 0); + s_axi_ctl_awvalid : in std_logic; + s_axi_ctl_wdata : in std_logic_vector(31 downto 0); + s_axi_ctl_wstrb : in std_logic_vector(3 downto 0); + s_axi_ctl_wvalid : in std_logic; + s_axi_ctl_bready : in std_logic; + s_axi_ctl_araddr : in std_logic_vector(11 downto 0); + s_axi_ctl_arvalid : in std_logic; + s_axi_ctl_rready : in std_logic; + axi_aclk : out std_logic; + axi_aresetn : out std_logic; + axi_ctl_aresetn : out std_logic; + interrupt_out : out std_logic; + intx_msi_grant : out std_logic; + s_axi_awready : out std_logic; + s_axi_wready : out std_logic; + s_axi_bid : out std_logic_vector(AXI_PCIE_CONFIG_C.ID_BITS_C-1 downto 0); + s_axi_bresp : out std_logic_vector(1 downto 0); + s_axi_bvalid : out std_logic; + s_axi_arready : out std_logic; + s_axi_rid : out std_logic_vector(AXI_PCIE_CONFIG_C.ID_BITS_C-1 downto 0); + s_axi_rdata : out std_logic_vector(8*AXI_PCIE_CONFIG_C.DATA_BYTES_C-1 downto 0); + s_axi_ruser : out std_logic_vector(31 downto 0); + s_axi_rresp : out std_logic_vector(1 downto 0); + s_axi_rlast : out std_logic; + s_axi_rvalid : out std_logic; + m_axi_awid : out std_logic_vector(2 downto 0); + m_axi_awaddr : out std_logic_vector(AXI_PCIE_CONFIG_C.ADDR_WIDTH_C-1 downto 0); + m_axi_awlen : out std_logic_vector(AXI_PCIE_CONFIG_C.LEN_BITS_C-1 downto 0); + m_axi_awsize : out std_logic_vector(2 downto 0); + m_axi_awburst : out std_logic_vector(1 downto 0); + m_axi_awprot : out std_logic_vector(2 downto 0); + m_axi_awvalid : out std_logic; + m_axi_awlock : out std_logic; + m_axi_awcache : out std_logic_vector(3 downto 0); + m_axi_wdata : out std_logic_vector(8*AXI_PCIE_CONFIG_C.DATA_BYTES_C-1 downto 0); + m_axi_wuser : out std_logic_vector(31 downto 0); + m_axi_wstrb : out std_logic_vector(AXI_PCIE_CONFIG_C.DATA_BYTES_C-1 downto 0); + m_axi_wlast : out std_logic; + m_axi_wvalid : out std_logic; + m_axi_bready : out std_logic; + m_axi_arid : out std_logic_vector(2 downto 0); + m_axi_araddr : out std_logic_vector(AXI_PCIE_CONFIG_C.ADDR_WIDTH_C-1 downto 0); + m_axi_arlen : out std_logic_vector(AXI_PCIE_CONFIG_C.LEN_BITS_C-1 downto 0); + m_axi_arsize : out std_logic_vector(2 downto 0); + m_axi_arburst : out std_logic_vector(1 downto 0); + m_axi_arprot : out std_logic_vector(2 downto 0); + m_axi_arvalid : out std_logic; + m_axi_arlock : out std_logic; + m_axi_arcache : out std_logic_vector(3 downto 0); + m_axi_rready : out std_logic; + pci_exp_txp : out std_logic_vector(7 downto 0); + pci_exp_txn : out std_logic_vector(7 downto 0); + s_axi_ctl_awready : out std_logic; + s_axi_ctl_wready : out std_logic; + s_axi_ctl_bresp : out std_logic_vector(1 downto 0); + s_axi_ctl_bvalid : out std_logic; + s_axi_ctl_arready : out std_logic; + s_axi_ctl_rdata : out std_logic_vector(31 downto 0); + s_axi_ctl_rresp : out std_logic_vector(1 downto 0); + s_axi_ctl_rvalid : out std_logic; + int_qpll1lock_out : out std_logic_vector(1 downto 0); + int_qpll1outrefclk_out : out std_logic_vector(1 downto 0); + int_qpll1outclk_out : out std_logic_vector(1 downto 0) + ); + end component; + + signal refClk : sl; + signal refClkGt : sl; + signal clk : sl; + signal rst : sl; + signal rstL : sl; + signal axiClock : sl; + signal axiReset : sl; +begin + + axiClk <= clk; + U_Rst : entity surf.RstPipeline + generic map ( + TPD_G => TPD_G, + INV_RST_G => true) + port map ( + clk => clk, + rstIn => rstL, + rstOut => axiRst); + + ------------------ + -- Clock and Reset + ------------------ + U_IBUFDS_GTE3 : IBUFDS_GTE3 + generic map ( + REFCLK_EN_TX_PATH => '0', + REFCLK_HROW_CK_SEL => "00", -- 2'b00: ODIV2 = O + REFCLK_ICNTL_RX => "00") + port map ( + I => pciRefClkP, + IB => pciRefClkN, + CEB => '0', + ODIV2 => refClk, + O => refClkGt); + + ------------------- + -- AXI PCIe IP Core + ------------------- + U_AxiPcie : AbacoPc821PciePhy + port map ( + -- Clocks and Resets + sys_clk_gt => refClkGt, + refclk => refClk, + sys_rst_n => pciRstL, + axi_aclk => clk, + axi_aresetn => rstL, + axi_ctl_aclk => clk, + axi_ctl_aresetn => open, + user_link_up => open, + cfg_ltssm_state => open, + -- Interrupt Interface + intx_msi_request => dmaIrq, + intx_msi_grant => open, + interrupt_out => open, + -- Slave AXI4 Interface + s_axi_awid => dmaWriteMaster.awid(AXI_PCIE_CONFIG_C.ID_BITS_C-1 downto 0), + s_axi_awaddr => dmaWriteMaster.awaddr(AXI_PCIE_CONFIG_C.ADDR_WIDTH_C-1 downto 0), + s_axi_awregion => dmaWriteMaster.awregion, + s_axi_awlen => dmaWriteMaster.awlen(AXI_PCIE_CONFIG_C.LEN_BITS_C-1 downto 0), + s_axi_awsize => dmaWriteMaster.awsize(2 downto 0), + s_axi_awburst => dmaWriteMaster.awburst(1 downto 0), + s_axi_awvalid => dmaWriteMaster.awvalid, + s_axi_awready => dmaWriteSlave.awready, + s_axi_wdata => dmaWriteMaster.wdata(8*AXI_PCIE_CONFIG_C.DATA_BYTES_C-1 downto 0), + s_axi_wuser => (others => '0'), + s_axi_wstrb => dmaWriteMaster.wstrb(AXI_PCIE_CONFIG_C.DATA_BYTES_C-1 downto 0), + s_axi_wlast => dmaWriteMaster.wlast, + s_axi_wvalid => dmaWriteMaster.wvalid, + s_axi_wready => dmaWriteSlave.wready, + s_axi_bid => dmaWriteSlave.bid(AXI_PCIE_CONFIG_C.ID_BITS_C-1 downto 0), + s_axi_bresp => dmaWriteSlave.bresp(1 downto 0), + s_axi_bvalid => dmaWriteSlave.bvalid, + s_axi_bready => dmaWriteMaster.bready, + s_axi_arid => dmaReadMaster.arid(AXI_PCIE_CONFIG_C.ID_BITS_C-1 downto 0), + s_axi_araddr => dmaReadMaster.araddr(AXI_PCIE_CONFIG_C.ADDR_WIDTH_C-1 downto 0), + s_axi_arregion => dmaReadMaster.arregion, + s_axi_arlen => dmaReadMaster.arlen(AXI_PCIE_CONFIG_C.LEN_BITS_C-1 downto 0), + s_axi_arsize => dmaReadMaster.arsize(2 downto 0), + s_axi_arburst => dmaReadMaster.arburst(1 downto 0), + s_axi_arvalid => dmaReadMaster.arvalid, + s_axi_arready => dmaReadSlave.arready, + s_axi_rid => dmaReadSlave.rid(AXI_PCIE_CONFIG_C.ID_BITS_C-1 downto 0), + s_axi_rdata => dmaReadSlave.rdata(8*AXI_PCIE_CONFIG_C.DATA_BYTES_C-1 downto 0), + s_axi_ruser => open, + s_axi_rresp => dmaReadSlave.rresp(1 downto 0), + s_axi_rlast => dmaReadSlave.rlast, + s_axi_rvalid => dmaReadSlave.rvalid, + s_axi_rready => dmaReadMaster.rready, + -- Master AXI4 Interface + m_axi_awaddr => regWriteMaster.awaddr(AXI_PCIE_CONFIG_C.ADDR_WIDTH_C-1 downto 0), + m_axi_awlen => regWriteMaster.awlen(AXI_PCIE_CONFIG_C.LEN_BITS_C-1 downto 0), + m_axi_awsize => regWriteMaster.awsize(2 downto 0), + m_axi_awburst => regWriteMaster.awburst(1 downto 0), + m_axi_awprot => regWriteMaster.awprot, + m_axi_awvalid => regWriteMaster.awvalid, + m_axi_awready => regWriteSlave.awready, + m_axi_awlock => regWriteMaster.awlock(0), + m_axi_awcache => regWriteMaster.awcache, + m_axi_wdata => regWriteMaster.wdata(8*AXI_PCIE_CONFIG_C.DATA_BYTES_C-1 downto 0), + m_axi_wuser => open, + m_axi_wstrb => regWriteMaster.wstrb(AXI_PCIE_CONFIG_C.DATA_BYTES_C-1 downto 0), + m_axi_wlast => regWriteMaster.wlast, + m_axi_wvalid => regWriteMaster.wvalid, + m_axi_wready => regWriteSlave.wready, + m_axi_bid => regWriteSlave.bid(2 downto 0), + -- m_axi_bresp => regWriteSlave.bresp(1 downto 0), + m_axi_bresp => AXI_RESP_OK_C, -- Always respond OK + m_axi_bvalid => regWriteSlave.bvalid, + m_axi_bready => regWriteMaster.bready, + m_axi_araddr => regReadMaster.araddr(AXI_PCIE_CONFIG_C.ADDR_WIDTH_C-1 downto 0), + m_axi_arlen => regReadMaster.arlen(AXI_PCIE_CONFIG_C.LEN_BITS_C-1 downto 0), + m_axi_arsize => regReadMaster.arsize(2 downto 0), + m_axi_arburst => regReadMaster.arburst(1 downto 0), + m_axi_arprot => regReadMaster.arprot, + m_axi_arvalid => regReadMaster.arvalid, + m_axi_arready => regReadSlave.arready, + m_axi_arlock => regReadMaster.arlock(0), + m_axi_arcache => regReadMaster.arcache, + m_axi_rid => regReadSlave.rid(2 downto 0), + m_axi_rdata => regReadSlave.rdata(8*AXI_PCIE_CONFIG_C.DATA_BYTES_C-1 downto 0), + m_axi_ruser => (others => '0'), + -- m_axi_rresp => regReadSlave.rresp(1 downto 0), + m_axi_rresp => AXI_RESP_OK_C, -- Always respond OK + m_axi_rlast => regReadSlave.rlast, + m_axi_rvalid => regReadSlave.rvalid, + m_axi_rready => regReadMaster.rready, + -- PCIe PHY Interface + pci_exp_txp => pciTxP, + pci_exp_txn => pciTxN, + pci_exp_rxp => pciRxP, + pci_exp_rxn => pciRxN, + -- Slave AXI4-Lite Interface + s_axi_ctl_awaddr => phyWriteMaster.awaddr(11 downto 0), + s_axi_ctl_awvalid => phyWriteMaster.awvalid, + s_axi_ctl_awready => phyWriteSlave.awready, + s_axi_ctl_wdata => phyWriteMaster.wdata, + s_axi_ctl_wstrb => phyWriteMaster.wstrb, + s_axi_ctl_wvalid => phyWriteMaster.wvalid, + s_axi_ctl_wready => phyWriteSlave.wready, + s_axi_ctl_bresp => phyWriteSlave.bresp, + s_axi_ctl_bvalid => phyWriteSlave.bvalid, + s_axi_ctl_bready => phyWriteMaster.bready, + s_axi_ctl_araddr => phyReadMaster.araddr(11 downto 0), + s_axi_ctl_arvalid => phyReadMaster.arvalid, + s_axi_ctl_arready => phyReadSlave.arready, + s_axi_ctl_rdata => phyReadSlave.rdata, + s_axi_ctl_rresp => phyReadSlave.rresp, + s_axi_ctl_rvalid => phyReadSlave.rvalid, + s_axi_ctl_rready => phyReadMaster.rready, + -- QPLL Interface + int_qpll1lock_out => open, + int_qpll1outrefclk_out => open, + int_qpll1outclk_out => open); + +end mapping; diff --git a/hardware/AbacoPc821/pcie/ruckus.tcl b/hardware/AbacoPc821/pcie/ruckus.tcl new file mode 100644 index 0000000..9f3f58c --- /dev/null +++ b/hardware/AbacoPc821/pcie/ruckus.tcl @@ -0,0 +1,13 @@ +# Load RUCKUS environment and library +source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl + +# Load local Source Code and Constraints +loadSource -lib axi_pcie_core -dir "$::DIR_PATH/rtl" + +# loadIpCore -path "$::DIR_PATH/ip/AbacoPc821PciePhy.xci" +loadSource -lib axi_pcie_core -path "$::DIR_PATH/ip/AbacoPc821PciePhy.dcp" + +loadConstraints -path "$::DIR_PATH/ip/AbacoPc821PciePhy.xdc" +set_property PROCESSING_ORDER {EARLY} [get_files {AbacoPc821PciePhy.xdc}] +set_property SCOPED_TO_REF {AbacoPc821PciePhy_pcie3_ip} [get_files {AbacoPc821PciePhy.xdc}] +set_property SCOPED_TO_CELLS {inst} [get_files {AbacoPc821PciePhy.xdc}] diff --git a/hardware/AbacoPc821/rtl/AbacoPc821Core.vhd b/hardware/AbacoPc821/rtl/AbacoPc821Core.vhd new file mode 100644 index 0000000..79ec848 --- /dev/null +++ b/hardware/AbacoPc821/rtl/AbacoPc821Core.vhd @@ -0,0 +1,297 @@ +------------------------------------------------------------------------------- +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- This file is part of 'axi-pcie-core'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'axi-pcie-core', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiLitePkg.all; +use surf.AxiStreamPkg.all; +use surf.AxiPkg.all; + +library axi_pcie_core; +use axi_pcie_core.AxiPciePkg.all; + +library unisim; +use unisim.vcomponents.all; + +entity AbacoPc821Core is + generic ( + TPD_G : time := 1 ns; + ROGUE_SIM_EN_G : boolean := false; + ROGUE_SIM_PORT_NUM_G : natural range 1024 to 49151 := 8000; + ROGUE_SIM_CH_COUNT_G : natural range 1 to 256 := 256; + BUILD_INFO_G : BuildInfoType; + DMA_AXIS_CONFIG_G : AxiStreamConfigType; + DRIVER_TYPE_ID_G : slv(31 downto 0) := x"00000000"; + DMA_BURST_BYTES_G : positive range 256 to 4096 := 256; + DMA_SIZE_G : positive range 1 to 8 := 1); + port ( + ------------------------ + -- Top Level Interfaces + ------------------------ + -- DMA Interfaces (dmaClk domain) + dmaClk : out sl; + dmaRst : out sl; + dmaBuffGrpPause : out slv(7 downto 0); + dmaObMasters : out AxiStreamMasterArray(DMA_SIZE_G-1 downto 0); + dmaObSlaves : in AxiStreamSlaveArray(DMA_SIZE_G-1 downto 0); + dmaIbMasters : in AxiStreamMasterArray(DMA_SIZE_G-1 downto 0); + dmaIbSlaves : out AxiStreamSlaveArray(DMA_SIZE_G-1 downto 0); + -- Application AXI-Lite Interfaces [0x00100000:0x00FFFFFF] (appClk domain) + appClk : in sl; + appRst : in sl; + appReadMaster : out AxiLiteReadMasterType; + appReadSlave : in AxiLiteReadSlaveType; + appWriteMaster : out AxiLiteWriteMasterType; + appWriteSlave : in AxiLiteWriteSlaveType; + ------------------- + -- Top Level Ports + ------------------- + -- Boot Memory Ports + flashAddr : out slv(25 downto 0); + flashData : inout slv(15 downto 4); + flashOeL : out sl; + flashWeL : out sl; + -- PCIe Ports + pciRstL : in sl; + pciRefClkP : in sl; + pciRefClkN : in sl; + pciRxP : in slv(7 downto 0); + pciRxN : in slv(7 downto 0); + pciTxP : out slv(7 downto 0); + pciTxN : out slv(7 downto 0)); +end AbacoPc821Core; + +architecture mapping of AbacoPc821Core is + + signal dmaReadMaster : AxiReadMasterType; + signal dmaReadSlave : AxiReadSlaveType; + signal dmaWriteMaster : AxiWriteMasterType; + signal dmaWriteSlave : AxiWriteSlaveType; + + signal regReadMaster : AxiReadMasterType; + signal regReadSlave : AxiReadSlaveType; + signal regWriteMaster : AxiWriteMasterType; + signal regWriteSlave : AxiWriteSlaveType; + + signal dmaCtrlReadMasters : AxiLiteReadMasterArray(2 downto 0); + signal dmaCtrlReadSlaves : AxiLiteReadSlaveArray(2 downto 0) := (others => AXI_LITE_READ_SLAVE_EMPTY_OK_C); + signal dmaCtrlWriteMasters : AxiLiteWriteMasterArray(2 downto 0); + signal dmaCtrlWriteSlaves : AxiLiteWriteSlaveArray(2 downto 0) := (others => AXI_LITE_WRITE_SLAVE_EMPTY_OK_C); + + signal phyReadMaster : AxiLiteReadMasterType; + signal phyReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_EMPTY_OK_C; + signal phyWriteMaster : AxiLiteWriteMasterType; + signal phyWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_EMPTY_OK_C; + + signal sysClock : sl; + signal sysReset : sl; + signal systemReset : sl; + signal cardReset : sl; + signal dmaIrq : sl; + + signal bpiClk : sl; + signal bpiCeL : sl; + signal bpiDin : slv(15 downto 0); + signal bpiDout : slv(15 downto 0); + signal bpiTri : sl; + signal bpiDts : slv(3 downto 0); + signal bpiAddr : slv(28 downto 0); + +begin + + dmaClk <= sysClock; + + U_Rst : entity surf.RstPipeline + generic map ( + TPD_G => TPD_G) + port map ( + clk => sysClock, + rstIn => systemReset, + rstOut => dmaRst); + + systemReset <= sysReset or cardReset; + + --------------- + -- AXI PCIe PHY + --------------- + REAL_PCIE : if (not ROGUE_SIM_EN_G) generate + U_AxiPciePhy : entity axi_pcie_core.AbacoPc821PciePhyWrapper + generic map ( + TPD_G => TPD_G) + port map ( + -- AXI4 Interfaces + axiClk => sysClock, + axiRst => sysReset, + dmaReadMaster => dmaReadMaster, + dmaReadSlave => dmaReadSlave, + dmaWriteMaster => dmaWriteMaster, + dmaWriteSlave => dmaWriteSlave, + regReadMaster => regReadMaster, + regReadSlave => regReadSlave, + regWriteMaster => regWriteMaster, + regWriteSlave => regWriteSlave, + phyReadMaster => phyReadMaster, + phyReadSlave => phyReadSlave, + phyWriteMaster => phyWriteMaster, + phyWriteSlave => phyWriteSlave, + -- Interrupt Interface + dmaIrq => dmaIrq, + -- PCIe Ports + pciRstL => pciRstL, + pciRefClkP => pciRefClkP, + pciRefClkN => pciRefClkN, + pciRxP => pciRxP, + pciRxN => pciRxN, + pciTxP => pciTxP, + pciTxN => pciTxN); + end generate; + SIM_PCIE : if (ROGUE_SIM_EN_G) generate + U_sysClock : entity surf.ClkRst + generic map ( + CLK_PERIOD_G => 4 ns, -- 250 MHz + RST_START_DELAY_G => 0 ns, + RST_HOLD_TIME_G => 1000 ns) + port map ( + clkP => sysClock, + rst => sysReset); + end generate; + + --------------- + -- AXI PCIe REG + --------------- + U_REG : entity axi_pcie_core.AxiPcieReg + generic map ( + TPD_G => TPD_G, + ROGUE_SIM_EN_G => ROGUE_SIM_EN_G, + ROGUE_SIM_PORT_NUM_G => ROGUE_SIM_PORT_NUM_G, + BUILD_INFO_G => BUILD_INFO_G, + XIL_DEVICE_G => "ULTRASCALE", + BOOT_PROM_G => "BPI", -- s29gl01gs-bpi-x16 + DRIVER_TYPE_ID_G => DRIVER_TYPE_ID_G, + PCIE_HW_TYPE_G => HW_TYPE_ABACO_PC821_TYPE_C, + DMA_AXIS_CONFIG_G => DMA_AXIS_CONFIG_G, + DMA_SIZE_G => DMA_SIZE_G) + port map ( + -- AXI4 Interfaces + axiClk => sysClock, + axiRst => sysReset, + regReadMaster => regReadMaster, + regReadSlave => regReadSlave, + regWriteMaster => regWriteMaster, + regWriteSlave => regWriteSlave, + -- DMA AXI-Lite Interfaces + dmaCtrlReadMasters => dmaCtrlReadMasters, + dmaCtrlReadSlaves => dmaCtrlReadSlaves, + dmaCtrlWriteMasters => dmaCtrlWriteMasters, + dmaCtrlWriteSlaves => dmaCtrlWriteSlaves, + -- PHY AXI-Lite Interfaces + phyReadMaster => phyReadMaster, + phyReadSlave => phyReadSlave, + phyWriteMaster => phyWriteMaster, + phyWriteSlave => phyWriteSlave, + -- (Optional) Application AXI-Lite Interfaces + appClk => appClk, + appRst => appRst, + appReadMaster => appReadMaster, + appReadSlave => appReadSlave, + appWriteMaster => appWriteMaster, + appWriteSlave => appWriteSlave, + -- Application Force reset + cardResetOut => cardReset, + cardResetIn => systemReset, + -- Boot Memory Ports + bpiAddr => bpiAddr, + bpiAdv => open, + bpiClk => bpiClk, + bpiRstL => open, + bpiCeL => bpiCeL, + bpiOeL => flashOeL, + bpiWeL => flashWeL, + bpiDin => bpiDin, + bpiDout => bpiDout, + bpiTri => bpiTri); + + flashAddr <= bpiAddr(25 downto 0); + bpiDts <= (others => bpiTri); + + GEN_IOBUF : + for i in 15 downto 4 generate + IOBUF_inst : IOBUF + port map ( + O => bpiDout(i), -- Buffer output + IO => flashData(i), -- Buffer inout port (connect directly to top-level port) + I => bpiDin(i), -- Buffer input + T => bpiTri); -- 3-state enable input, high=input, low=output + end generate GEN_IOBUF; + + U_STARTUPE3 : STARTUPE3 + generic map ( + PROG_USR => "FALSE", -- Activate program event security feature. Requires encrypted bitstreams. + SIM_CCLK_FREQ => 0.0) -- Set the Configuration Clock Frequency(ns) for simulation + port map ( + CFGCLK => open, -- 1-bit output: Configuration main clock output + CFGMCLK => open, -- 1-bit output: Configuration internal oscillator clock output + DI => bpiDin(3 downto 0), + EOS => open, -- 1-bit output: Active high output signal indicating the End Of Startup. + PREQ => open, -- 1-bit output: PROGRAM request to fabric output + DO => bpiDout(3 downto 0), + DTS => bpiDts, + FCSBO => bpiCeL, + FCSBTS => '0', -- 1-bit input: Tristate the FCS_B pin + GSR => '0', -- 1-bit input: Global Set/Reset input (GSR cannot be used for the port name) + GTS => '1', -- 1-bit input: Global 3-state input (GTS cannot be used for the port name) + KEYCLEARB => '0', -- 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM) + PACK => '0', -- 1-bit input: PROGRAM acknowledge input + USRCCLKO => bpiClk, -- 1-bit input: User CCLK input + USRCCLKTS => '1', -- 1-bit input: User CCLK 3-state enable input + USRDONEO => '0', -- 1-bit input: User DONE pin output control + USRDONETS => '1'); -- 1-bit input: User DONE 3-state enable output + + --------------- + -- AXI PCIe DMA + --------------- + U_AxiPcieDma : entity axi_pcie_core.AxiPcieDma + generic map ( + TPD_G => TPD_G, + ROGUE_SIM_EN_G => ROGUE_SIM_EN_G, + ROGUE_SIM_PORT_NUM_G => ROGUE_SIM_PORT_NUM_G, + ROGUE_SIM_CH_COUNT_G => ROGUE_SIM_CH_COUNT_G, + DMA_SIZE_G => DMA_SIZE_G, + DMA_BURST_BYTES_G => DMA_BURST_BYTES_G, + DMA_AXIS_CONFIG_G => DMA_AXIS_CONFIG_G) + port map ( + axiClk => sysClock, + axiRst => sysReset, + -- AXI4 Interfaces ( + axiReadMaster => dmaReadMaster, + axiReadSlave => dmaReadSlave, + axiWriteMaster => dmaWriteMaster, + axiWriteSlave => dmaWriteSlave, + -- AXI4-Lite Interfaces + axilReadMasters => dmaCtrlReadMasters, + axilReadSlaves => dmaCtrlReadSlaves, + axilWriteMasters => dmaCtrlWriteMasters, + axilWriteSlaves => dmaCtrlWriteSlaves, + -- DMA Interfaces + dmaIrq => dmaIrq, + dmaBuffGrpPause => dmaBuffGrpPause, + dmaObMasters => dmaObMasters, + dmaObSlaves => dmaObSlaves, + dmaIbMasters => dmaIbMasters, + dmaIbSlaves => dmaIbSlaves); + +end mapping; diff --git a/hardware/AbacoPc821/rtl/KU085/AxiPciePkg.vhd b/hardware/AbacoPc821/rtl/KU085/AxiPciePkg.vhd new file mode 100644 index 0000000..2d38199 --- /dev/null +++ b/hardware/AbacoPc821/rtl/KU085/AxiPciePkg.vhd @@ -0,0 +1,42 @@ +------------------------------------------------------------------------------- +-- File : AxiPciePkg.vhd +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Package file for AXI PCIe Core +------------------------------------------------------------------------------- +-- This file is part of 'axi-pcie-core'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'axi-pcie-core', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiLitePkg.all; +use surf.AxiStreamPkg.all; +use surf.AxiPkg.all; + +library axi_pcie_core; +use axi_pcie_core.AxiPcieSharedPkg.all; + +package AxiPciePkg is + + constant HW_TYPE_ABACO_PC821_TYPE_C : slv(31 downto 0) := HW_TYPE_ABACO_PC821_KU085_C; + + -- System Clock Frequency + constant DMA_CLK_FREQ_C : real := 250.0E+6; -- units of Hz + + -- PCIE PHY AXI Configuration + constant AXI_PCIE_CONFIG_C : AxiConfigType := ( + ADDR_WIDTH_C => 40, -- 40-bit address interface + DATA_BYTES_C => 32, -- 256-bit data interface + ID_BITS_C => 4, -- Up to 16 DMA IDS + LEN_BITS_C => 8); -- 8-bit awlen/arlen interface + +end package AxiPciePkg; diff --git a/hardware/AbacoPc821/rtl/KU115/AxiPciePkg.vhd b/hardware/AbacoPc821/rtl/KU115/AxiPciePkg.vhd new file mode 100644 index 0000000..e02e516 --- /dev/null +++ b/hardware/AbacoPc821/rtl/KU115/AxiPciePkg.vhd @@ -0,0 +1,42 @@ +------------------------------------------------------------------------------- +-- File : AxiPciePkg.vhd +-- Company : SLAC National Accelerator Laboratory +------------------------------------------------------------------------------- +-- Description: Package file for AXI PCIe Core +------------------------------------------------------------------------------- +-- This file is part of 'axi-pcie-core'. +-- It is subject to the license terms in the LICENSE.txt file found in the +-- top-level directory of this distribution and at: +-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +-- No part of 'axi-pcie-core', including this file, +-- may be copied, modified, propagated, or distributed except according to +-- the terms contained in the LICENSE.txt file. +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +library surf; +use surf.StdRtlPkg.all; +use surf.AxiLitePkg.all; +use surf.AxiStreamPkg.all; +use surf.AxiPkg.all; + +library axi_pcie_core; +use axi_pcie_core.AxiPcieSharedPkg.all; + +package AxiPciePkg is + + constant HW_TYPE_ABACO_PC821_TYPE_C : slv(31 downto 0) := HW_TYPE_ABACO_PC821_KU115_C; + + -- System Clock Frequency + constant DMA_CLK_FREQ_C : real := 250.0E+6; -- units of Hz + + -- PCIE PHY AXI Configuration + constant AXI_PCIE_CONFIG_C : AxiConfigType := ( + ADDR_WIDTH_C => 40, -- 40-bit address interface + DATA_BYTES_C => 32, -- 256-bit data interface + ID_BITS_C => 4, -- Up to 16 DMA IDS + LEN_BITS_C => 8); -- 8-bit awlen/arlen interface + +end package AxiPciePkg; diff --git a/hardware/AbacoPc821/ruckus.tcl b/hardware/AbacoPc821/ruckus.tcl new file mode 100644 index 0000000..dff693b --- /dev/null +++ b/hardware/AbacoPc821/ruckus.tcl @@ -0,0 +1,28 @@ +# Load RUCKUS environment and library +source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl + +# Check for version 2023.1 of Vivado (or later) +if { [VersionCheck 2023.1] < 0 } {exit -1} + +# Load shared source code +loadRuckusTcl "$::DIR_PATH/../../shared" + +# Set the target language for Verilog (removes warning messages in PCIe IP core) +set_property target_language Verilog [current_project] + +# Check for valid FPGA part number +if { $::env(PRJ_PART) == "XCKU085-FLVB1760-2-E" } { + loadSource -lib axi_pcie_core -dir "$::DIR_PATH/rtl/KU085" +} elseif { $::env(PRJ_PART) == "XCKU115-FLVB1760-2-E" } { + loadSource -lib axi_pcie_core -dir "$::DIR_PATH/rtl/KU115" +} else { + puts "\n\nERROR: PRJ_PART was not defined as XCKU085-FLVB1760-2-E or XCKU115-FLVB1760-2-E in the Makefile\n\n"; exit -1 +} + +# Load local Source Code and Constraints +loadSource -lib axi_pcie_core -dir "$::DIR_PATH/rtl" +loadConstraints -path "$::DIR_PATH/xdc/AbacoPc821Core.xdc" +loadConstraints -path "$::DIR_PATH/xdc/AbacoPc821App.xdc" + +# Load the primary PCIe core +loadRuckusTcl "$::DIR_PATH/pcie" diff --git a/hardware/AbacoPc821/xdc/AbacoPc821App.xdc b/hardware/AbacoPc821/xdc/AbacoPc821App.xdc new file mode 100644 index 0000000..c708f1d --- /dev/null +++ b/hardware/AbacoPc821/xdc/AbacoPc821App.xdc @@ -0,0 +1,9 @@ +############################################################################## +## This file is part of 'axi-pcie-core'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'axi-pcie-core', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## diff --git a/hardware/AbacoPc821/xdc/AbacoPc821Core.xdc b/hardware/AbacoPc821/xdc/AbacoPc821Core.xdc new file mode 100644 index 0000000..ab25335 --- /dev/null +++ b/hardware/AbacoPc821/xdc/AbacoPc821Core.xdc @@ -0,0 +1,138 @@ +############################################################################## +## This file is part of 'axi-pcie-core'. +## It is subject to the license terms in the LICENSE.txt file found in the +## top-level directory of this distribution and at: +## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +## No part of 'axi-pcie-core', including this file, +## may be copied, modified, propagated, or distributed except according to +## the terms contained in the LICENSE.txt file. +############################################################################## + +############################# +# Flash programming interface +############################# + +# NOTE: the STARTUPE3 primitive is used to connect D0 to D3 and FLASH_nCE +# Flash data 11 downto 0 connects to physical pins 15 downto 4 + +set_property -dict { PACKAGE_PIN AV21 IOSTANDARD LVCMOS18 } [get_ports flashOeL] +set_property -dict { PACKAGE_PIN AV22 IOSTANDARD LVCMOS18 } [get_ports flashWeL] + +set_property -dict { PACKAGE_PIN BA25 IOSTANDARD LVCMOS18 } [get_ports {flashAddr[0]}] +set_property -dict { PACKAGE_PIN BB25 IOSTANDARD LVCMOS18 } [get_ports {flashAddr[1]}] +set_property -dict { PACKAGE_PIN AY28 IOSTANDARD LVCMOS18 } [get_ports {flashAddr[2]}] +set_property -dict { PACKAGE_PIN BA28 IOSTANDARD LVCMOS18 } [get_ports {flashAddr[3]}] +set_property -dict { PACKAGE_PIN AY25 IOSTANDARD LVCMOS18 } [get_ports {flashAddr[4]}] +set_property -dict { PACKAGE_PIN AY26 IOSTANDARD LVCMOS18 } [get_ports {flashAddr[5]}] +set_property -dict { PACKAGE_PIN AW26 IOSTANDARD LVCMOS18 } [get_ports {flashAddr[6]}] +set_property -dict { PACKAGE_PIN AY27 IOSTANDARD LVCMOS18 } [get_ports {flashAddr[7]}] +set_property -dict { PACKAGE_PIN AW23 IOSTANDARD LVCMOS18 } [get_ports {flashAddr[8]}] +set_property -dict { PACKAGE_PIN AY23 IOSTANDARD LVCMOS18 } [get_ports {flashAddr[9]}] +set_property -dict { PACKAGE_PIN AW24 IOSTANDARD LVCMOS18 } [get_ports {flashAddr[10]}] +set_property -dict { PACKAGE_PIN AW25 IOSTANDARD LVCMOS18 } [get_ports {flashAddr[11]}] +set_property -dict { PACKAGE_PIN BB21 IOSTANDARD LVCMOS18 } [get_ports {flashAddr[12]}] +set_property -dict { PACKAGE_PIN BB22 IOSTANDARD LVCMOS18 } [get_ports {flashAddr[13]}] +set_property -dict { PACKAGE_PIN BA23 IOSTANDARD LVCMOS18 } [get_ports {flashAddr[14]}] +set_property -dict { PACKAGE_PIN BA24 IOSTANDARD LVCMOS18 } [get_ports {flashAddr[15]}] +set_property -dict { PACKAGE_PIN AW21 IOSTANDARD LVCMOS18 } [get_ports {flashAddr[16]}] +set_property -dict { PACKAGE_PIN AY21 IOSTANDARD LVCMOS18 } [get_ports {flashAddr[17]}] +set_property -dict { PACKAGE_PIN AY22 IOSTANDARD LVCMOS18 } [get_ports {flashAddr[18]}] +set_property -dict { PACKAGE_PIN BA22 IOSTANDARD LVCMOS18 } [get_ports {flashAddr[19]}] +set_property -dict { PACKAGE_PIN AT22 IOSTANDARD LVCMOS18 } [get_ports {flashAddr[20]}] +set_property -dict { PACKAGE_PIN AT23 IOSTANDARD LVCMOS18 } [get_ports {flashAddr[21]}] +set_property -dict { PACKAGE_PIN AR25 IOSTANDARD LVCMOS18 } [get_ports {flashAddr[22]}] +set_property -dict { PACKAGE_PIN AR26 IOSTANDARD LVCMOS18 } [get_ports {flashAddr[23]}] +set_property -dict { PACKAGE_PIN AU22 IOSTANDARD LVCMOS18 } [get_ports {flashAddr[24]}] +# Flash 25 goes through CPLD for factory save image loading +set_property -dict { PACKAGE_PIN AV23 IOSTANDARD LVCMOS18 } [get_ports {flashAddr[25]}] + +set_property -dict { PACKAGE_PIN AV26 IOSTANDARD LVCMOS18 } [get_ports {flashData[4]}] +set_property -dict { PACKAGE_PIN AV27 IOSTANDARD LVCMOS18 } [get_ports {flashData[5]}] +set_property -dict { PACKAGE_PIN AU29 IOSTANDARD LVCMOS18 } [get_ports {flashData[6]}] +set_property -dict { PACKAGE_PIN AV29 IOSTANDARD LVCMOS18 } [get_ports {flashData[7]}] +set_property -dict { PACKAGE_PIN AU25 IOSTANDARD LVCMOS18 } [get_ports {flashData[8]}] +set_property -dict { PACKAGE_PIN AU26 IOSTANDARD LVCMOS18 } [get_ports {flashData[9]}] +set_property -dict { PACKAGE_PIN AU27 IOSTANDARD LVCMOS18 } [get_ports {flashData[10]}] +set_property -dict { PACKAGE_PIN AV28 IOSTANDARD LVCMOS18 } [get_ports {flashData[11]}] +set_property -dict { PACKAGE_PIN BB26 IOSTANDARD LVCMOS18 } [get_ports {flashData[12]}] +set_property -dict { PACKAGE_PIN BB27 IOSTANDARD LVCMOS18 } [get_ports {flashData[13]}] +set_property -dict { PACKAGE_PIN AW28 IOSTANDARD LVCMOS18 } [get_ports {flashData[14]}] +set_property -dict { PACKAGE_PIN AW29 IOSTANDARD LVCMOS18 } [get_ports {flashData[15]}] + +#################### +# PCIe Constraints # +#################### + +set_property PACKAGE_PIN BB3 [get_ports {pciRxN[7]}] +set_property PACKAGE_PIN BB4 [get_ports {pciRxP[7]}] +set_property PACKAGE_PIN BB7 [get_ports {pciTxN[7]}] +set_property PACKAGE_PIN BB8 [get_ports {pciTxP[7]}] + +set_property PACKAGE_PIN BA1 [get_ports {pciRxN[6]}] +set_property PACKAGE_PIN BA2 [get_ports {pciRxP[6]}] +set_property PACKAGE_PIN BA5 [get_ports {pciTxN[6]}] +set_property PACKAGE_PIN BA6 [get_ports {pciTxP[6]}] + +set_property PACKAGE_PIN AY3 [get_ports {pciRxN[5]}] +set_property PACKAGE_PIN AY4 [get_ports {pciRxP[5]}] +set_property PACKAGE_PIN AY7 [get_ports {pciTxN[5]}] +set_property PACKAGE_PIN AY8 [get_ports {pciTxP[5]}] + +set_property PACKAGE_PIN AW1 [get_ports {pciRxN[4]}] +set_property PACKAGE_PIN AW2 [get_ports {pciRxP[4]}] +set_property PACKAGE_PIN AW5 [get_ports {pciTxN[4]}] +set_property PACKAGE_PIN AW6 [get_ports {pciTxP[4]}] + +set_property PACKAGE_PIN AV3 [get_ports {pciRxN[3]}] +set_property PACKAGE_PIN AV4 [get_ports {pciRxP[3]}] +set_property PACKAGE_PIN AV7 [get_ports {pciTxN[3]}] +set_property PACKAGE_PIN AV8 [get_ports {pciTxP[3]}] + +set_property PACKAGE_PIN AU1 [get_ports {pciRxN[2]}] +set_property PACKAGE_PIN AU2 [get_ports {pciRxP[2]}] +set_property PACKAGE_PIN AU5 [get_ports {pciTxN[2]}] +set_property PACKAGE_PIN AU6 [get_ports {pciTxP[2]}] + +set_property PACKAGE_PIN AT3 [get_ports {pciRxN[1]}] +set_property PACKAGE_PIN AT4 [get_ports {pciRxP[1]}] +set_property PACKAGE_PIN AT7 [get_ports {pciTxN[1]}] +set_property PACKAGE_PIN AT8 [get_ports {pciTxP[1]}] + +set_property PACKAGE_PIN AR1 [get_ports {pciRxN[0]}] +set_property PACKAGE_PIN AR2 [get_ports {pciRxP[0]}] +set_property PACKAGE_PIN AR5 [get_ports {pciTxN[0]}] +set_property PACKAGE_PIN AR6 [get_ports {pciTxP[0]}] + +set_property PACKAGE_PIN AR9 [get_ports pciRefClkN]; # 100 MHz +set_property PACKAGE_PIN AR10 [get_ports pciRefClkP]; # 100 MHz + +set_property -dict { PACKAGE_PIN AP28 IOSTANDARD LVCMOS18 PULLUP true } [get_ports {pciRstL}] + +########## +# Clocks # +########## + +create_clock -name pciRefClkP -period 10.000 [get_ports {pciRefClkP}] +create_clock -period 16.000 -name dnaClk [get_pins {U_Core/U_REG/U_Version/GEN_DEVICE_DNA.DeviceDna_1/GEN_ULTRA_SCALE.DeviceDnaUltraScale_Inst/BUFGCE_DIV_Inst/O}] +create_clock -period 16.000 -name iprogClk [get_pins {U_Core/U_REG/U_Version/GEN_ICAP.Iprog_1/GEN_ULTRA_SCALE.IprogUltraScale_Inst/BUFGCE_DIV_Inst/O}] + +set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks {pciRefClkP}] -group [get_clocks {dnaClk}] -group [get_clocks {iprogClk}] + +set_false_path -from [get_ports {pciRstL}] +set_false_path -through [get_nets {U_Core/REAL_PCIE.U_AxiPciePhy/U_AxiPcie/inst/inst/cfg_max*}] + +set_property HIGH_PRIORITY true [get_nets {U_Core/REAL_PCIE.U_AxiPciePhy/U_AxiPcie/inst/pcie3_ip_i/inst/gt_top_i/phy_clk_i/CLK_USERCLK}] + +###################################### +# BITSTREAM: .bit file Configuration # +###################################### + +set_property BITSTREAM.GENERAL.COMPRESS True [current_design] +set_property BITSTREAM.CONFIG.BPI_PAGE_SIZE 8 [current_design] +set_property BITSTREAM.CONFIG.BPI_1ST_READ_CYCLE 3 [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 3 [current_design] +set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DIV-2 [current_design] + +set_property CFGBVS GND [current_design] +set_property CONFIG_VOLTAGE 1.8 [current_design] +set_property CONFIG_MODE BPI16 [current_design] diff --git a/python/axipcie/_PcieAxiVersion.py b/python/axipcie/_PcieAxiVersion.py index f846ef2..764994e 100644 --- a/python/axipcie/_PcieAxiVersion.py +++ b/python/axipcie/_PcieAxiVersion.py @@ -212,7 +212,7 @@ def __init__(self, enum = { 0x00_00_00_00: 'Undefined', 0x00_00_00_01: 'AlphaDataKu3', - 0x00_00_00_02: 'BittWareXupVv8', + 0x00_00_00_02: 'BittWareXupVv8Vu13p', 0x00_00_00_03: 'SlacPgpCardG3', 0x00_00_00_04: 'SlacPgpCardG4', 0x00_00_00_05: 'XilinxAc701', @@ -227,5 +227,8 @@ def __init__(self, 0x00_00_00_0E: 'XilinxVcu128', 0x00_00_00_0F: 'XilinxAlveoU55C', 0x00_00_00_10: 'XilinxVariumC1100', + 0x00_00_00_11: 'AbacoPc821Ku085', + 0x00_00_00_12: 'AbacoPc821Ku115', + 0x00_00_00_13: 'BittWareXupVv8Vu9p', }, )) diff --git a/shared/rtl/AxiPcieSharedPkg.vhd b/shared/rtl/AxiPcieSharedPkg.vhd index 6c44d83..717917d 100644 --- a/shared/rtl/AxiPcieSharedPkg.vhd +++ b/shared/rtl/AxiPcieSharedPkg.vhd @@ -24,22 +24,25 @@ use surf.StdRtlPkg.all; package AxiPcieSharedPkg is -- List of PCIe Hardware Types - constant HW_TYPE_UNDEFINED_C : slv(31 downto 0) := x"00_00_00_00"; - constant HW_TYPE_ALPHADATA_KU3_C : slv(31 downto 0) := x"00_00_00_01"; - constant HW_TYPE_BITTWARE_XUP_VV8_C : slv(31 downto 0) := x"00_00_00_02"; - constant HW_TYPE_SLAC_PGP_GEN3_C : slv(31 downto 0) := x"00_00_00_03"; - constant HW_TYPE_SLAC_PGP_GEN4_C : slv(31 downto 0) := x"00_00_00_04"; - constant HW_TYPE_XILINX_AC701_C : slv(31 downto 0) := x"00_00_00_05"; - constant HW_TYPE_XILINX_U50_C : slv(31 downto 0) := x"00_00_00_06"; - constant HW_TYPE_XILINX_U200_C : slv(31 downto 0) := x"00_00_00_07"; - constant HW_TYPE_XILINX_U250_C : slv(31 downto 0) := x"00_00_00_08"; - constant HW_TYPE_XILINX_U280_C : slv(31 downto 0) := x"00_00_00_09"; - constant HW_TYPE_XILINX_KC705_C : slv(31 downto 0) := x"00_00_00_0A"; - constant HW_TYPE_XILINX_KCU105_C : slv(31 downto 0) := x"00_00_00_0B"; - constant HW_TYPE_XILINX_KCU116_C : slv(31 downto 0) := x"00_00_00_0C"; - constant HW_TYPE_XILINX_KCU1500_C : slv(31 downto 0) := x"00_00_00_0D"; - constant HW_TYPE_XILINX_VCU128_C : slv(31 downto 0) := x"00_00_00_0E"; - constant HW_TYPE_XILINX_U55C_C : slv(31 downto 0) := x"00_00_00_0F"; - constant HW_TYPE_XILINX_C1100_C : slv(31 downto 0) := x"00_00_00_10"; + constant HW_TYPE_UNDEFINED_C : slv(31 downto 0) := x"00_00_00_00"; + constant HW_TYPE_ALPHADATA_KU3_C : slv(31 downto 0) := x"00_00_00_01"; + constant HW_TYPE_BITTWARE_XUP_VV8_VU13P_C : slv(31 downto 0) := x"00_00_00_02"; + constant HW_TYPE_SLAC_PGP_GEN3_C : slv(31 downto 0) := x"00_00_00_03"; + constant HW_TYPE_SLAC_PGP_GEN4_C : slv(31 downto 0) := x"00_00_00_04"; + constant HW_TYPE_XILINX_AC701_C : slv(31 downto 0) := x"00_00_00_05"; + constant HW_TYPE_XILINX_U50_C : slv(31 downto 0) := x"00_00_00_06"; + constant HW_TYPE_XILINX_U200_C : slv(31 downto 0) := x"00_00_00_07"; + constant HW_TYPE_XILINX_U250_C : slv(31 downto 0) := x"00_00_00_08"; + constant HW_TYPE_XILINX_U280_C : slv(31 downto 0) := x"00_00_00_09"; + constant HW_TYPE_XILINX_KC705_C : slv(31 downto 0) := x"00_00_00_0A"; + constant HW_TYPE_XILINX_KCU105_C : slv(31 downto 0) := x"00_00_00_0B"; + constant HW_TYPE_XILINX_KCU116_C : slv(31 downto 0) := x"00_00_00_0C"; + constant HW_TYPE_XILINX_KCU1500_C : slv(31 downto 0) := x"00_00_00_0D"; + constant HW_TYPE_XILINX_VCU128_C : slv(31 downto 0) := x"00_00_00_0E"; + constant HW_TYPE_XILINX_U55C_C : slv(31 downto 0) := x"00_00_00_0F"; + constant HW_TYPE_XILINX_C1100_C : slv(31 downto 0) := x"00_00_00_10"; + constant HW_TYPE_ABACO_PC821_KU085_C : slv(31 downto 0) := x"00_00_00_11"; + constant HW_TYPE_ABACO_PC821_KU115_C : slv(31 downto 0) := x"00_00_00_12"; + constant HW_TYPE_BITTWARE_XUP_VV8_VU9P_C : slv(31 downto 0) := x"00_00_00_13"; end package AxiPcieSharedPkg;