Use PLLDIVCLK1 for OUT clocks

slaclab · Apr 5, 2023 · 72e8652 · 72e8652
1 parent 9d638ee
commit 72e8652
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Showing 2 changed files with 8 additions and 8 deletions.
diff --git a/protocols/pgp/pgp2b/gtyUltraScale+/ip/PgpGtyCore.dcp b/protocols/pgp/pgp2b/gtyUltraScale+/ip/PgpGtyCore.dcp
diff --git a/protocols/pgp/pgp2b/gtyUltraScale+/ip/PgpGtyCore.xci b/protocols/pgp/pgp2b/gtyUltraScale+/ip/PgpGtyCore.xci
@@ -37,7 +37,7 @@
         "TX_INT_DATA_WIDTH": [ { "value": "20", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "TX_BUFFER_MODE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "TX_QPLL_FRACN_NUMERATOR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "TX_OUTCLK_SOURCE": [ { "value": "TXOUTCLKPMA", "resolve_type": "user", "usage": "all" } ],
+        "TX_OUTCLK_SOURCE": [ { "value": "TXPLLREFCLK_DIV1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
         "TX_DIFF_SWING_EMPH_MODE": [ { "value": "CUSTOM", "resolve_type": "user", "usage": "all" } ],
         "RX_LINE_RATE": [ { "value": "3.125", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
         "RX_PLL_TYPE": [ { "value": "CPLL", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
@@ -50,7 +50,7 @@
         "RX_EQ_MODE": [ { "value": "AUTO", "resolve_type": "user", "usage": "all" } ],
         "RX_JTOL_FC": [ { "value": "1.8746251", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
         "RX_JTOL_LF_SLOPE": [ { "value": "-20", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "RX_OUTCLK_SOURCE": [ { "value": "RXOUTCLKPMA", "resolve_type": "user", "usage": "all" } ],
+        "RX_OUTCLK_SOURCE": [ { "value": "RXPLLREFCLK_DIV1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
         "SIM_CPLL_CAL_BYPASS": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "PCIE_ENABLE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "RX_TERMINATION": [ { "value": "PROGRAMMABLE", "resolve_type": "user", "usage": "all" } ],
@@ -170,7 +170,7 @@
         "PRESET": [ { "value": "GTY-Aurora_8B10B", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
         "INTERNAL_PRESET": [ { "value": "Aurora_8B10B", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
         "INTERNAL_PORT_USAGE_UPDATED": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
-        "INTERNAL_PORT_ENABLEMENT_UPDATED": [ { "value": "27", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "INTERNAL_PORT_ENABLEMENT_UPDATED": [ { "value": "37", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
         "INTERNAL_CHANNEL_SITES_UPDATED": [ { "value": "5", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
         "INTERNAL_CHANNEL_COLUMN_LOC_MAX": [ { "value": "96", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
         "INTERNAL_RX_COMMA_PRESET_UPDATE": [ { "value": "8", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
@@ -778,7 +778,7 @@
         "C_RX_MASTER_CHANNEL_IDX": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_RX_OUTCLK_BUFG_GT_DIV": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_RX_OUTCLK_FREQUENCY": [ { "value": "156.2500000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
-        "C_RX_OUTCLK_SOURCE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RX_OUTCLK_SOURCE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_RX_PLL_TYPE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_RX_RECCLK_OUTPUT": [ { "value": "0x000000000000000000000000000000000000000000000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
         "C_RX_REFCLK_FREQUENCY": [ { "value": "156.25", "resolve_type": "generated", "format": "float", "usage": "all" } ],
@@ -809,7 +809,7 @@
         "C_TX_MASTER_CHANNEL_IDX": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_TX_OUTCLK_BUFG_GT_DIV": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_TX_OUTCLK_FREQUENCY": [ { "value": "156.2500000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
-        "C_TX_OUTCLK_SOURCE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_TX_OUTCLK_SOURCE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_TX_PLL_TYPE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_TX_REFCLK_FREQUENCY": [ { "value": "156.25", "resolve_type": "generated", "format": "float", "usage": "all" } ],
         "C_TX_USER_CLOCKING_CONTENTS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
@@ -827,7 +827,7 @@
         "BOARD_CONNECTIONS": [ { "value": "" } ],
         "DEVICE": [ { "value": "xcvu9p" } ],
         "PACKAGE": [ { "value": "fsgd2104" } ],
-        "PREFHDL": [ { "value": "VERILOG" } ],
+        "PREFHDL": [ { "value": "VHDL" } ],
         "SILICON_REVISION": [ { "value": "" } ],
         "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
         "SPEEDGRADE": [ { "value": "-2" } ],