Merge pull request #1086 from slaclab/pre-release

Release Candidate v2.43.0

.github/workflows/surf_ci.yml

@@ -11,7 +11,6 @@
 # ----------------------------------------------------------------------------
 # The following environment variables are required for this process:
 # secrets.GH_TOKEN
-# secrets.CONDA_UPLOAD_TOKEN_DEV
 # secrets.CONDA_UPLOAD_TOKEN_TAG
 
 name: SURF Integration
@@ -116,7 +115,7 @@ jobs:
   conda_build:
     name: Anaconda Build
     needs: [test_and_document]
-    if: startsWith(github.ref, 'refs/tags/') || github.ref == 'refs/heads/pre-release'
+    if: startsWith(github.ref, 'refs/tags/')
     strategy:
       matrix:
         os:
@@ -153,16 +152,10 @@ jobs:
       - name: Get Image Information
         id: get_image_info
         env:
-          CONDA_UPLOAD_TOKEN_DEV: ${{ secrets.CONDA_UPLOAD_TOKEN_DEV }}
           CONDA_UPLOAD_TOKEN_TAG: ${{ secrets.CONDA_UPLOAD_TOKEN_TAG }}
           OS_NAME: ${{ matrix.os }}
         run: |
-          if [ ${GITHUB_REF} == "refs/heads/pre-release" ]
-          then
-              echo ::set-output name=token::$CONDA_UPLOAD_TOKEN_DEV
-          else
-              echo ::set-output name=token::$CONDA_UPLOAD_TOKEN_TAG
-          fi
+          echo ::set-output name=token::$CONDA_UPLOAD_TOKEN_TAG
           echo ::set-output name=os::linux-64
 
       - name: Build And Upload

protocols/clink/rtl/ClinkFraming.vhd

@@ -339,8 +339,39 @@ begin
             -- 10 bits, base, medium, full & deca, cameraLink spec V2.0 pages 19-28
             when CDM_10BIT_C =>
                if chanConfig.linkMode = CLM_DECA_C then
-                  v.byteData := r.portData;
-                  v.bytes    := 16;
+
+                  v.byteData.data(0)(7 downto 0) := r.portData.data(0)(7 downto 0);  -- T0.BIT[07:00]
+                  v.byteData.data(1)(1 downto 0) := r.portData.data(1)(1 downto 0);  -- T0.BIT[09:08]
+
+                  v.byteData.data(1)(7 downto 2) := r.portData.data(2)(5 downto 0);  -- T1.BIT[05:00]
+                  v.byteData.data(2)(1 downto 0) := r.portData.data(2)(7 downto 6);  -- T1.BIT[07:06]
+                  v.byteData.data(2)(3 downto 2) := r.portData.data(3)(1 downto 0);  -- T1.BIT[09:08]
+
+                  v.byteData.data(2)(7 downto 4) := r.portData.data(4)(3 downto 0);  -- T2.BIT[03:00]
+                  v.byteData.data(3)(3 downto 0) := r.portData.data(4)(7 downto 4);  -- T2.BIT[07:04]
+                  v.byteData.data(3)(5 downto 4) := r.portData.data(5)(1 downto 0);  -- T2.BIT[09:08]
+
+                  v.byteData.data(3)(7 downto 6) := r.portData.data(6)(1 downto 0);  -- T3.BIT[01:00]
+                  v.byteData.data(4)(5 downto 0) := r.portData.data(6)(7 downto 2);  -- T3.BIT[07:02]
+                  v.byteData.data(4)(7 downto 6) := r.portData.data(7)(1 downto 0);  -- T3.BIT[09:08]
+
+                  v.byteData.data(5)(7 downto 0) := r.portData.data(8)(7 downto 0);  -- T4.BIT[07:00]
+                  v.byteData.data(6)(1 downto 0) := r.portData.data(9)(1 downto 0);  -- T4.BIT[09:08]
+
+                  v.byteData.data(6)(7 downto 2) := r.portData.data(10)(5 downto 0);  -- T5.BIT[05:00]
+                  v.byteData.data(7)(1 downto 0) := r.portData.data(10)(7 downto 6);  -- T5.BIT[07:06]
+                  v.byteData.data(7)(3 downto 2) := r.portData.data(11)(1 downto 0);  -- T5.BIT[09:08]
+
+                  v.byteData.data(7)(7 downto 4) := r.portData.data(12)(3 downto 0);  -- T6.BIT[03:00]
+                  v.byteData.data(8)(3 downto 0) := r.portData.data(12)(7 downto 4);  -- T6.BIT[07:04]
+                  v.byteData.data(8)(5 downto 4) := r.portData.data(13)(1 downto 0);  -- T6.BIT[09:08]
+
+                  v.byteData.data(8)(7 downto 6) := r.portData.data(14)(1 downto 0);  -- T7.BIT[01:00]
+                  v.byteData.data(9)(5 downto 0) := r.portData.data(14)(7 downto 2);  -- T7.BIT[07:02]
+                  v.byteData.data(9)(7 downto 6) := r.portData.data(15)(1 downto 0);  -- T7.BIT[09:08]
+
+                  v.bytes := 10;        -- No ZERO padding for DECA mode
+
                else
                   v.byteData.data(0)             := r.portData.data(0);  -- T1, DA[07:00]
                   v.byteData.data(1)(1 downto 0) := r.portData.data(1)(1 downto 0);  -- T1, DA[09:08]

protocols/pgp/shared/PgpTxVcFifo.vhd

@@ -33,6 +33,7 @@ entity PgpTxVcFifo is
       MEMORY_TYPE_G      : string   := "block";
       GEN_SYNC_FIFO_G    : boolean  := false;
       FIFO_ADDR_WIDTH_G  : positive := 9;
+      CASCADE_SIZE_G     : positive := 1;
       APP_AXI_CONFIG_G   : AxiStreamConfigType;
       PHY_AXI_CONFIG_G   : AxiStreamConfigType);
    port (
@@ -140,6 +141,8 @@ begin
          GEN_SYNC_FIFO_G     => GEN_SYNC_FIFO_G,
          FIFO_ADDR_WIDTH_G   => FIFO_ADDR_WIDTH_G,
          FIFO_PAUSE_THRESH_G => (2**FIFO_ADDR_WIDTH_G)-4,
+         CASCADE_PAUSE_SEL_G => CASCADE_SIZE_G-1,
+         CASCADE_SIZE_G      => CASCADE_SIZE_G,
          -- AXI Stream Port Configurations
          SLAVE_AXI_CONFIG_G  => APP_AXI_CONFIG_G,
          MASTER_AXI_CONFIG_G => PHY_AXI_CONFIG_G)

protocols/pgp/shared/PgpXvcWrapper.vhd

@@ -0,0 +1,115 @@
+-------------------------------------------------------------------------------
+-- Company    : SLAC National Accelerator Laboratory
+-------------------------------------------------------------------------------
+-- Description: XVC Wrapper
+-------------------------------------------------------------------------------
+-- This file is part of 'SLAC Firmware Standard Library'.
+-- It is subject to the license terms in the LICENSE.txt file found in the
+-- top-level directory of this distribution and at:
+--    https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
+-- No part of 'SLAC Firmware Standard Library', including this file,
+-- may be copied, modified, propagated, or distributed except according to
+-- the terms contained in the LICENSE.txt file.
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library surf;
+use surf.StdRtlPkg.all;
+use surf.AxiStreamPkg.all;
+use surf.EthMacPkg.all;
+
+entity PgpXvcWrapper is
+   generic (
+      TPD_G            : time    := 1 ns;
+      SIMULATION_G     : boolean := false;
+      AXIS_CLK_FREQ_G  : real    := 156.25e6;
+      PHY_AXI_CONFIG_G : AxiStreamConfigType);
+   port (
+      -- Clock and Reset (xvcClk domain)
+      xvcClk      : in  sl;
+      xvcRst      : in  sl;
+      -- Clock and Reset (pgpClk domain)
+      pgpClk      : in  sl;
+      pgpRst      : in  sl;
+      -- PGP Interface (pgpClk domain)
+      rxlinkReady : in  sl;
+      txlinkReady : in  sl;
+      -- TX FIFO  (pgpClk domain)
+      pgpTxMaster : out AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C;
+      pgpTxSlave  : in  AxiStreamSlaveType;
+      -- RX FIFO  (pgpClk domain)
+      pgpRxMaster : in  AxiStreamMasterType;
+      pgpRxCtrl   : out AxiStreamCtrlType   := AXI_STREAM_CTRL_UNUSED_C);
+end PgpXvcWrapper;
+
+architecture rtl of PgpXvcWrapper is
+
+   signal ibXvcMaster : AxiStreamMasterType := axiStreamMasterInit(EMAC_AXIS_CONFIG_C);
+   signal ibXvcSlave  : AxiStreamSlaveType  := AXI_STREAM_SLAVE_FORCE_C;
+   signal obXvcMaster : AxiStreamMasterType := axiStreamMasterInit(EMAC_AXIS_CONFIG_C);
+   signal obXvcSlave  : AxiStreamSlaveType  := AXI_STREAM_SLAVE_FORCE_C;
+
+begin
+
+   GEN_REAL : if (SIMULATION_G = false) generate
+
+      -----------------------------------------------------------------
+      -- Xilinx Virtual Cable (XVC)
+      -- https://www.xilinx.com/products/intellectual-property/xvc.html
+      -----------------------------------------------------------------
+      U_XVC : entity surf.UdpDebugBridgeWrapper
+         generic map (
+            TPD_G           => TPD_G,
+            AXIS_CLK_FREQ_G => AXIS_CLK_FREQ_G)
+         port map (
+            -- Clock and Reset
+            clk            => xvcClk,
+            rst            => xvcRst,
+            -- UDP XVC Interface
+            obServerMaster => ibXvcMaster,
+            obServerSlave  => ibXvcSlave,
+            ibServerMaster => obXvcMaster,
+            ibServerSlave  => obXvcSlave);
+
+      U_VC_RX : entity surf.PgpRxVcFifo
+         generic map (
+            TPD_G            => TPD_G,
+            PHY_AXI_CONFIG_G => PHY_AXI_CONFIG_G,
+            APP_AXI_CONFIG_G => EMAC_AXIS_CONFIG_C)
+         port map (
+            -- PGP Interface (pgpClk domain)
+            pgpClk      => pgpClk,
+            pgpRst      => pgpRst,
+            rxlinkReady => rxlinkReady,
+            pgpRxMaster => pgpRxMaster,
+            pgpRxCtrl   => pgpRxCtrl,
+            -- AXIS Interface (axisClk domain)
+            axisClk     => xvcClk,
+            axisRst     => xvcRst,
+            axisMaster  => ibXvcMaster,
+            axisSlave   => ibXvcSlave);
+
+      U_VC_TX : entity surf.PgpTxVcFifo
+         generic map (
+            TPD_G            => TPD_G,
+            APP_AXI_CONFIG_G => EMAC_AXIS_CONFIG_C,
+            PHY_AXI_CONFIG_G => PHY_AXI_CONFIG_G)
+         port map (
+            -- AXIS Interface (axisClk domain)
+            axisClk     => xvcClk,
+            axisRst     => xvcRst,
+            axisMaster  => obXvcMaster,
+            axisSlave   => obXvcSlave,
+            -- PGP Interface (pgpClk domain)
+            pgpClk      => pgpClk,
+            pgpRst      => pgpRst,
+            rxlinkReady => rxlinkReady,
+            txlinkReady => txlinkReady,
+            pgpTxMaster => pgpTxMaster,
+            pgpTxSlave  => pgpTxSlave);
+
+   end generate GEN_REAL;
+
+end rtl;

protocols/xvc-udp/dcp/core/UdpDebugBridgeImplWrapper.vhd

@@ -25,6 +25,8 @@ use surf.AxiStreamPkg.all;
 use surf.UdpDebugBridgePkg.all;
 
 entity UdpDebugBridge is
+   generic (
+      AXIS_CLK_FREQ_G : real := 156.25e6);
    port (
       axisClk          : in sl;
       axisRst          : in sl;
@@ -38,11 +40,14 @@ entity UdpDebugBridge is
 end entity UdpDebugBridge;
 
 architecture UdpDebugBridgeImpl of UdpDebugBridge is
+
+   constant XVC_TCLK_DIV2_C   : positive := positive( ieee.math_real.round( AXIS_CLK_FREQ_G/XVC_TCLK_FREQ_C/2.0 ) );
+
 begin
 
    U_AxisJtagDebugBridge : entity surf.AxisJtagDebugBridge(AxisJtagDebugBridgeImpl)
       generic map (
-         AXIS_FREQ_G         => XVC_ACLK_FREQ_C,
+         AXIS_FREQ_G         => AXIS_CLK_FREQ_G,
          CLK_DIV2_G          => XVC_TCLK_DIV2_C,
          AXIS_WIDTH_G        => XVC_AXIS_WIDTH_C,
          MEM_DEPTH_G         => XVC_MEM_DEPTH_C,

protocols/xvc-udp/dcp/core/UdpDebugBridgePkg.vhd

@@ -37,8 +37,6 @@ package UdpDebugBridgePkg is
 
    constant XVC_MEM_SIZE_C    : natural  := 1450/2; -- non-jumbo MTU; mem must hold max. reply = max request/2
    constant XVC_TCLK_FREQ_C   : real     := 15.0E+6;
-   constant XVC_ACLK_FREQ_C   : real     := 156.25E+6;
-   constant XVC_TCLK_DIV2_C   : positive := positive( ieee.math_real.round( XVC_ACLK_FREQ_C/XVC_TCLK_FREQ_C/2.0 ) );
    constant XVC_AXIS_WIDTH_C  : positive range 4 to 16 := EMAC_AXIS_CONFIG_C.TDATA_BYTES_C;
 
    constant XVC_MEM_DEPTH_C   : natural range 0 to 65535 :=  XVC_MEM_SIZE_C/XVC_AXIS_WIDTH_C;

protocols/xvc-udp/dcp/core/UdpDebugBridgeStubWrapper.vhd

@@ -25,6 +25,8 @@ use surf.AxiStreamPkg.all;
 use surf.UdpDebugBridgePkg.all;
 
 entity UdpDebugBridge is
+   generic (
+      AXIS_CLK_FREQ_G : real := 156.25e6);
    port (
       axisClk          : in sl;
       axisRst          : in sl;
@@ -38,11 +40,14 @@ entity UdpDebugBridge is
 end entity UdpDebugBridge;
 
 architecture UdpDebugBridgeImpl of UdpDebugBridge is
+
+   constant XVC_TCLK_DIV2_C   : positive := positive( ieee.math_real.round( AXIS_CLK_FREQ_G/XVC_TCLK_FREQ_C/2.0 ) );
+
 begin
 
    U_AxisJtagDebugBridge : entity surf.AxisJtagDebugBridge(AxisJtagDebugBridgeStub)
       generic map (
-         AXIS_FREQ_G         => XVC_ACLK_FREQ_C,
+         AXIS_FREQ_G         => AXIS_CLK_FREQ_C,
          CLK_DIV2_G          => XVC_TCLK_DIV2_C,
          AXIS_WIDTH_G        => XVC_AXIS_WIDTH_C,
          MEM_DEPTH_G         => XVC_MEM_DEPTH_C,