Merge pull request #1089 from slaclab/delay3patch_fix

fix Delay3PatchFSM: init issue (JIRA ESSURF-24)
slaclab · Jun 27, 2023 · c755ebe · c755ebe
2 parents b40b1e3 + 7ce7d63
commit c755ebe
Showing 1 changed file with 13 additions and 8 deletions.
diff --git a/xilinx/UltraScale/general/rtl/Delaye3PatchFsm.vhd b/xilinx/UltraScale/general/rtl/Delaye3PatchFsm.vhd
@@ -49,6 +49,7 @@ architecture rtl of Delaye3PatchFsm is
 
    type StateType is (
       IDLE_S,
+      CHECK_CNT_S,
       LOAD_S,
       WAIT_S);
 
@@ -84,26 +85,30 @@ begin
          v.Load := '0';
 
          -- Check for load request
-         if (LOAD = '1') then
-            -- Update the target delay value
-            v.dlyTarget := CNTVALUEIN;
-         end if;
-
          -- Main state machine
          case r.state is
             ----------------------------------------------------------------------
             when IDLE_S =>
+               if (LOAD = '1') then
+                  -- Update the target delay value on load request
+                  v.dlyTarget := CNTVALUEIN;
+                  v.state     := CHECK_CNT_S;
+               end if;
+            ----------------------------------------------------------------------
+            when CHECK_CNT_S =>
                -- Check if load target different from current output
-               if (v.dlyTarget /= CNTVALUEOUT) then
+               if (r.dlyTarget /= CNTVALUEOUT) then
                   -- Check if we should increment the value
-                  if (v.dlyTarget > CNTVALUEOUT) then
+                  if (r.dlyTarget > CNTVALUEOUT) then
                      v.dlyValue := CNTVALUEOUT + 1;
                   -- Else decrement the value
                   else
                      v.dlyValue := CNTVALUEOUT - 1;
                   end if;
                   -- Next state
                   v.state := LOAD_S;
+               else
+                  v.state := IDLE_S;
                end if;
             ----------------------------------------------------------------------
             when LOAD_S =>
@@ -121,7 +126,7 @@ begin
                   -- Reset the counter
                   v.waitCnt := (others => '0');
                   -- Next state
-                  v.state   := IDLE_S;
+                  v.state   := CHECK_CNT_S;
                end if;
          ----------------------------------------------------------------------
          end case;